micheleandClaude Sonnet 5
8e014d8d49
FASE #1 hardware freeze for FPGA-Neural V2, N4/P8, single external SDRAM (Alliance Memory AS4C4M16SA-6TIN) serving weights, activations, and results through one physical sdram_controller.v instance. Removes the PSRAM dependency (hardware/v1/rtl/psram_controller.v + memory_interface.v) from the V2 physical path entirely -- V1 itself remains fully unmodified, the golden reference. New RTL: sdram_unified_backend.v (2-way W/AR arbitration over one SDRAM controller, real per-byte DQM write masking added to sdram_controller.v for correct single-byte result writes with no read-modify-write), nms_neural_multiprocessor_sdram_unified.v (the frozen top-level). Two real bugs found and fixed via full-system testing before being accepted (ERR-0023): a deadlock and an off-by-one data-shift bug in the new arbitration logic. Real results: N=4 and N=2 D-Stress bit-exact (256/256 neurons), 40 real AUTO REFRESH events interleaved with zero corruption, real Yosys+nextpnr-ecp5 synthesis/P&R for LFE5U-45F-8CABGA381 (149/245 TRELLIS_IO, a real 45-pin reduction from the prior dual-memory design). Timing is MARGINAL (1/8 P&R seeds >=80MHz), reported honestly rather than masked by the best seed. Real, sourced ball-level pinout for the SDRAM bus + clk/rst (39/149 signals, P&R-verified) using the official Lattice ECP5U-45 pinout CSV found on disk during this step's own pre-commit review -- corrects an earlier draft that wrongly assumed no real pinout data was available. Chip readiness: NO. Real, disclosed blockers remain (no physical host interface exists yet -- the RTL's own reg_* ports are a 110-pin raw test-harness bus; clock source/PLL decision; power/configuration component selection) -- see hardware/v2/docs/{HARDWARE_FREEZE, CHIP_READINESS,OPEN_ITEMS}.md for the complete, itemized status. Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
2085 lines
42 KiB
Plaintext
2085 lines
42 KiB
Plaintext
.device LFE5U-45F
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.comment Part: LFE5U-45F-8CABGA381
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.tile CIB_R10C3:PVT_COUNT2
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unknown: F2B0
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unknown: F3B0
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unknown: F5B0
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unknown: F11B0
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unknown: F13B0
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.tile CIB_R10C42:CIB_EBR
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arc: N3_V06N0303 S3_V06N0303
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.tile CIB_R13C89:CIB_LR
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arc: N3_V06N0303 JF5
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.tile CIB_R1C10:CIB
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arc: S3_V06S0203 H06W0203
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.tile CIB_R1C13:CIB
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arc: W3_H06W0203 E3_H06W0203
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.tile CIB_R1C19:CIB
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arc: W3_H06W0203 E3_H06W0103
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.tile CIB_R1C25:CIB
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arc: W3_H06W0103 E3_H06W0003
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.tile CIB_R1C31:CIB
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arc: W3_H06W0003 E3_H06W0003
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.tile CIB_R1C37:CIB
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arc: W3_H06W0003 E3_H06W0003
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.tile CIB_R1C42:CIB
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arc: JA0 V02N0501
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enum: CIB.JB0MUX 0
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.tile CIB_R1C43:CIB
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arc: W3_H06W0003 JQ0
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.tile CIB_R1C47:CIB
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arc: E1_H02E0201 S3_V06N0103
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.tile CIB_R1C48:CIB
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arc: JD7 H02E0201
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.tile CIB_R1C5:CIB
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arc: JA0 V02N0501
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enum: CIB.JB0MUX 0
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.tile CIB_R1C6:CIB
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arc: S3_V06S0003 JQ0
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.tile CIB_R1C9:CIB
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arc: S3_V06S0003 JQ0
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.tile CIB_R22C42:CIB_DSP
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arc: N3_V06N0303 S3_V06N0203
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.tile CIB_R26C1:CIB_LR
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arc: E3_H06E0303 JQ5
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.tile CIB_R28C1:CIB_LR
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arc: JA0 H02W0701
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enum: CIB.JB0MUX 0
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.tile CIB_R29C1:CIB_LR
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arc: E1_H02E0501 JF5
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arc: E3_H06E0303 JQ5
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.tile CIB_R29C89:CIB_LR
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arc: JA3 H02E0701
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enum: CIB.JB3MUX 0
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.tile CIB_R30C1:CIB_LR
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arc: S1_V02S0001 H06W0003
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.tile CIB_R31C1:CIB_LR
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arc: E3_H06E0303 JF5
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arc: JA3 V00B0000
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arc: S1_V02S0301 E3_H06W0003
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arc: V00B0000 V02S0001
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enum: CIB.JB3MUX 0
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.tile CIB_R31C89:CIB_LR
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arc: W3_H06W0303 JQ5
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.tile CIB_R32C1:CIB_LR
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arc: H00L0100 V02S0301
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arc: JA0 E1_H02W0701
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arc: JA3 H00L0100
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enum: CIB.JB3MUX 0
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enum: CIB.JB0MUX 0
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.tile CIB_R34C87:CIB_EBR
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arc: E1_H02E0701 V06S0203
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.tile CIB_R34C89:CIB_LR_S
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arc: JA0 W1_H02E0701
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enum: CIB.JB0MUX 0
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.tile CIB_R5C1:CIB_PLL1
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enum: CIB.JA3MUX 0
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enum: CIB.JB3MUX 0
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.tile CIB_R5C89:CIB_PLL1
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enum: CIB.JA3MUX 0
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enum: CIB.JB3MUX 0
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.tile CIB_R70C3:CIB_PLL3
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enum: CIB.JA3MUX 0
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enum: CIB.JB3MUX 0
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.tile CIB_R70C42:VCIB_DCU0
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enum: CIB.JA1MUX 0
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enum: CIB.JA3MUX 0
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enum: CIB.JA5MUX 0
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enum: CIB.JA7MUX 0
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enum: CIB.JB1MUX 0
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enum: CIB.JB3MUX 0
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enum: CIB.JB5MUX 0
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enum: CIB.JB7MUX 0
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enum: CIB.JC0MUX 0
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enum: CIB.JC2MUX 0
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enum: CIB.JC4MUX 0
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enum: CIB.JC6MUX 0
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enum: CIB.JD0MUX 0
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enum: CIB.JD2MUX 0
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enum: CIB.JD4MUX 0
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enum: CIB.JD6MUX 0
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.tile CIB_R70C43:VCIB_DCUA
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enum: CIB.JA1MUX 0
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enum: CIB.JA3MUX 0
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enum: CIB.JA5MUX 0
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enum: CIB.JA7MUX 0
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enum: CIB.JB1MUX 0
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enum: CIB.JB3MUX 0
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enum: CIB.JB5MUX 0
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enum: CIB.JB7MUX 0
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enum: CIB.JC0MUX 0
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enum: CIB.JC2MUX 0
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enum: CIB.JC4MUX 0
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enum: CIB.JC6MUX 0
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enum: CIB.JD0MUX 0
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enum: CIB.JD2MUX 0
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enum: CIB.JD4MUX 0
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enum: CIB.JD6MUX 0
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.tile CIB_R70C44:VCIB_DCUB
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enum: CIB.JA1MUX 0
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enum: CIB.JA3MUX 0
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enum: CIB.JA5MUX 0
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enum: CIB.JA7MUX 0
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enum: CIB.JB1MUX 0
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enum: CIB.JB3MUX 0
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enum: CIB.JB5MUX 0
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enum: CIB.JB7MUX 0
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enum: CIB.JC0MUX 0
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enum: CIB.JC2MUX 0
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enum: CIB.JC4MUX 0
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enum: CIB.JC6MUX 0
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enum: CIB.JD0MUX 0
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enum: CIB.JD2MUX 0
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enum: CIB.JD4MUX 0
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enum: CIB.JD6MUX 0
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.tile CIB_R70C45:VCIB_DCUC
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enum: CIB.JA1MUX 0
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enum: CIB.JA3MUX 0
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enum: CIB.JA5MUX 0
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enum: CIB.JA7MUX 0
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enum: CIB.JB1MUX 0
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enum: CIB.JB3MUX 0
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enum: CIB.JB5MUX 0
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enum: CIB.JB7MUX 0
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enum: CIB.JC0MUX 0
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enum: CIB.JC2MUX 0
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enum: CIB.JC4MUX 0
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enum: CIB.JC6MUX 0
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enum: CIB.JD0MUX 0
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enum: CIB.JD2MUX 0
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enum: CIB.JD4MUX 0
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enum: CIB.JD6MUX 0
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.tile CIB_R70C46:VCIB_DCUD
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enum: CIB.JA1MUX 0
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enum: CIB.JA5MUX 0
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enum: CIB.JA7MUX 0
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enum: CIB.JB1MUX 0
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enum: CIB.JB3MUX 0
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enum: CIB.JB5MUX 0
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enum: CIB.JB7MUX 0
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enum: CIB.JC0MUX 0
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enum: CIB.JC2MUX 0
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enum: CIB.JC4MUX 0
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enum: CIB.JC6MUX 0
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enum: CIB.JD0MUX 0
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enum: CIB.JD2MUX 0
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enum: CIB.JD4MUX 0
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enum: CIB.JD6MUX 0
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.tile CIB_R70C47:VCIB_DCUF
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enum: CIB.JA1MUX 0
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enum: CIB.JA3MUX 0
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enum: CIB.JA5MUX 0
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enum: CIB.JA7MUX 0
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enum: CIB.JB1MUX 0
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enum: CIB.JB3MUX 0
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enum: CIB.JB5MUX 0
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enum: CIB.JB7MUX 0
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enum: CIB.JC0MUX 0
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enum: CIB.JC2MUX 0
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enum: CIB.JC4MUX 0
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enum: CIB.JC6MUX 0
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enum: CIB.JD0MUX 0
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enum: CIB.JD2MUX 0
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enum: CIB.JD4MUX 0
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enum: CIB.JD6MUX 0
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.tile CIB_R70C48:VCIB_DCU3
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enum: CIB.JA5MUX 0
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enum: CIB.JA7MUX 0
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enum: CIB.JB1MUX 0
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enum: CIB.JB3MUX 0
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enum: CIB.JB5MUX 0
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enum: CIB.JB7MUX 0
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enum: CIB.JC0MUX 0
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enum: CIB.JC4MUX 0
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enum: CIB.JC6MUX 0
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enum: CIB.JD0MUX 0
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enum: CIB.JD2MUX 0
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enum: CIB.JD4MUX 0
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enum: CIB.JD6MUX 0
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.tile CIB_R70C49:VCIB_DCU2
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enum: CIB.JB1MUX 0
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enum: CIB.JB3MUX 0
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enum: CIB.JB5MUX 0
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enum: CIB.JB7MUX 0
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enum: CIB.JD0MUX 0
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enum: CIB.JD2MUX 0
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enum: CIB.JD4MUX 0
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enum: CIB.JD6MUX 0
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.tile CIB_R70C50:VCIB_DCUG
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enum: CIB.JB1MUX 0
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enum: CIB.JB3MUX 0
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enum: CIB.JB5MUX 0
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enum: CIB.JB7MUX 0
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enum: CIB.JD0MUX 0
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enum: CIB.JD2MUX 0
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enum: CIB.JD4MUX 0
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enum: CIB.JD6MUX 0
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.tile CIB_R70C51:VCIB_DCUH
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enum: CIB.JB1MUX 0
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enum: CIB.JB3MUX 0
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enum: CIB.JB5MUX 0
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enum: CIB.JB7MUX 0
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enum: CIB.JD0MUX 0
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enum: CIB.JD2MUX 0
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enum: CIB.JD4MUX 0
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enum: CIB.JD6MUX 0
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.tile CIB_R70C52:VCIB_DCUI
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enum: CIB.JB1MUX 0
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enum: CIB.JB3MUX 0
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enum: CIB.JB5MUX 0
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enum: CIB.JB7MUX 0
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enum: CIB.JD0MUX 0
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enum: CIB.JD2MUX 0
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enum: CIB.JD4MUX 0
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enum: CIB.JD6MUX 0
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.tile CIB_R70C53:VCIB_DCU1
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enum: CIB.JB1MUX 0
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enum: CIB.JB3MUX 0
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enum: CIB.JB5MUX 0
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enum: CIB.JD0MUX 0
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enum: CIB.JD2MUX 0
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.tile CIB_R70C69:VCIB_DCU0
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enum: CIB.JA1MUX 0
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enum: CIB.JA3MUX 0
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enum: CIB.JA5MUX 0
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enum: CIB.JA7MUX 0
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enum: CIB.JB1MUX 0
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enum: CIB.JB3MUX 0
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enum: CIB.JB5MUX 0
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enum: CIB.JB7MUX 0
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enum: CIB.JC0MUX 0
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enum: CIB.JC2MUX 0
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enum: CIB.JC4MUX 0
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enum: CIB.JC6MUX 0
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enum: CIB.JD0MUX 0
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enum: CIB.JD2MUX 0
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enum: CIB.JD4MUX 0
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enum: CIB.JD6MUX 0
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.tile CIB_R70C6:CIB_EFB0
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enum: CIB.JB3MUX 0
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enum: CIB.JC6MUX 0
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enum: CIB.JD6MUX 0
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.tile CIB_R70C70:VCIB_DCUA
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enum: CIB.JA1MUX 0
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enum: CIB.JA3MUX 0
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enum: CIB.JA5MUX 0
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enum: CIB.JA7MUX 0
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enum: CIB.JB1MUX 0
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enum: CIB.JB3MUX 0
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enum: CIB.JB5MUX 0
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enum: CIB.JB7MUX 0
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enum: CIB.JC0MUX 0
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enum: CIB.JC2MUX 0
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enum: CIB.JC4MUX 0
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enum: CIB.JC6MUX 0
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enum: CIB.JD0MUX 0
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enum: CIB.JD2MUX 0
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enum: CIB.JD4MUX 0
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enum: CIB.JD6MUX 0
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.tile CIB_R70C71:VCIB_DCUB
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enum: CIB.JA1MUX 0
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enum: CIB.JA3MUX 0
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enum: CIB.JA5MUX 0
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enum: CIB.JA7MUX 0
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enum: CIB.JB1MUX 0
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enum: CIB.JB3MUX 0
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enum: CIB.JB5MUX 0
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enum: CIB.JB7MUX 0
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enum: CIB.JC0MUX 0
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enum: CIB.JC2MUX 0
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enum: CIB.JC4MUX 0
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enum: CIB.JC6MUX 0
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enum: CIB.JD0MUX 0
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enum: CIB.JD2MUX 0
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enum: CIB.JD4MUX 0
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enum: CIB.JD6MUX 0
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.tile CIB_R70C72:VCIB_DCUC
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enum: CIB.JA1MUX 0
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enum: CIB.JA3MUX 0
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enum: CIB.JA5MUX 0
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enum: CIB.JA7MUX 0
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enum: CIB.JB1MUX 0
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enum: CIB.JB3MUX 0
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enum: CIB.JB5MUX 0
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enum: CIB.JB7MUX 0
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enum: CIB.JC0MUX 0
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enum: CIB.JC2MUX 0
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enum: CIB.JC4MUX 0
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enum: CIB.JC6MUX 0
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enum: CIB.JD0MUX 0
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enum: CIB.JD2MUX 0
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enum: CIB.JD4MUX 0
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enum: CIB.JD6MUX 0
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.tile CIB_R70C73:VCIB_DCUD
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enum: CIB.JA1MUX 0
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enum: CIB.JA5MUX 0
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enum: CIB.JA7MUX 0
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enum: CIB.JB1MUX 0
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enum: CIB.JB3MUX 0
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enum: CIB.JB5MUX 0
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enum: CIB.JB7MUX 0
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enum: CIB.JC0MUX 0
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enum: CIB.JC2MUX 0
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enum: CIB.JC4MUX 0
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enum: CIB.JC6MUX 0
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enum: CIB.JD0MUX 0
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enum: CIB.JD2MUX 0
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enum: CIB.JD4MUX 0
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enum: CIB.JD6MUX 0
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.tile CIB_R70C74:VCIB_DCUF
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enum: CIB.JA1MUX 0
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enum: CIB.JA3MUX 0
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enum: CIB.JA5MUX 0
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enum: CIB.JA7MUX 0
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enum: CIB.JB1MUX 0
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enum: CIB.JB3MUX 0
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enum: CIB.JB5MUX 0
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enum: CIB.JB7MUX 0
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enum: CIB.JC0MUX 0
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enum: CIB.JC2MUX 0
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enum: CIB.JC4MUX 0
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enum: CIB.JC6MUX 0
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enum: CIB.JD0MUX 0
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enum: CIB.JD2MUX 0
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enum: CIB.JD4MUX 0
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enum: CIB.JD6MUX 0
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.tile CIB_R70C75:VCIB_DCU3
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enum: CIB.JA5MUX 0
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enum: CIB.JA7MUX 0
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enum: CIB.JB1MUX 0
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enum: CIB.JB3MUX 0
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enum: CIB.JB5MUX 0
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enum: CIB.JB7MUX 0
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enum: CIB.JC0MUX 0
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enum: CIB.JC4MUX 0
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enum: CIB.JC6MUX 0
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enum: CIB.JD0MUX 0
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enum: CIB.JD2MUX 0
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enum: CIB.JD4MUX 0
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enum: CIB.JD6MUX 0
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.tile CIB_R70C76:VCIB_DCU2
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enum: CIB.JB1MUX 0
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enum: CIB.JB3MUX 0
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enum: CIB.JB5MUX 0
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enum: CIB.JB7MUX 0
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enum: CIB.JD0MUX 0
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enum: CIB.JD2MUX 0
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enum: CIB.JD4MUX 0
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enum: CIB.JD6MUX 0
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.tile CIB_R70C77:VCIB_DCUG
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enum: CIB.JB1MUX 0
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enum: CIB.JB3MUX 0
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enum: CIB.JB5MUX 0
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enum: CIB.JB7MUX 0
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enum: CIB.JD0MUX 0
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enum: CIB.JD2MUX 0
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enum: CIB.JD4MUX 0
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enum: CIB.JD6MUX 0
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.tile CIB_R70C78:VCIB_DCUH
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enum: CIB.JB1MUX 0
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enum: CIB.JB3MUX 0
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enum: CIB.JB5MUX 0
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enum: CIB.JB7MUX 0
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enum: CIB.JD0MUX 0
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enum: CIB.JD2MUX 0
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enum: CIB.JD4MUX 0
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enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C79:VCIB_DCUI
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C7:CIB_EFB1
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JA4MUX 0
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JA6MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB4MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB6MUX 0
|
|
enum: CIB.JC3MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
enum: CIB.JC5MUX 0
|
|
enum: CIB.JD3MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD5MUX 0
|
|
|
|
.tile CIB_R70C80:VCIB_DCU1
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
|
|
.tile CIB_R70C87:CIB_PLL3
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
|
|
.tile CIB_R7C89:CIB_LR
|
|
arc: W3_H06W0303 S3_V06N0303
|
|
|
|
.tile MIB_R0C3:BANKREF0
|
|
enum: BANK.VCCIO 3V3
|
|
|
|
.tile MIB_R0C40:TMID_0
|
|
arc: G_TDCC0CLKI G_JTRQPCLKCIB1
|
|
|
|
.tile MIB_R0C42:PIOT0
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R0C43:PIOT1
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOB.HYSTERESIS ON
|
|
|
|
.tile MIB_R0C5:PIOT1
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R0C6:PIOT0
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOA.HYSTERESIS ON
|
|
|
|
.tile MIB_R0C87:BANKREF1
|
|
enum: BANK.VCCIO 3V3
|
|
|
|
.tile MIB_R0C9:PIOT0
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOA.HYSTERESIS ON
|
|
|
|
.tile MIB_R10C0:BANKREF7
|
|
enum: BANK.VCCIO 3V3
|
|
|
|
.tile MIB_R10C12:EBR_SPINE_UL1
|
|
arc: G_VPTX0000 G_HPRX0000
|
|
|
|
.tile MIB_R10C40:CMUX_UL_0
|
|
arc: G_DCS0CLK0 G_VPFN0000
|
|
arc: G_ULPCLK0 G_VPFS0000
|
|
|
|
.tile MIB_R10C41:CMUX_UR_0
|
|
arc: G_DCS0CLK1 G_VPFN0000
|
|
arc: G_URPCLK0 G_VPFS0000
|
|
|
|
.tile MIB_R10C90:BANKREF2
|
|
enum: BANK.VCCIO 3V3
|
|
|
|
.tile MIB_R12C90:PICR1
|
|
enum: PIOC.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOC.HYSTERESIS ON
|
|
|
|
.tile MIB_R13C90:PICR2
|
|
enum: PIOC.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C42:PICT0
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C43:PICT1
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C5:PICT1
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C6:PICT0
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C9:PICT0
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R26C0:PICL0
|
|
arc: JDIB JPADDIB_PIO
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R27C0:PICL1_DQS0
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOB.HYSTERESIS ON
|
|
enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R28C0:PICL2_DQS1
|
|
enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R29C0:PICL0_DQS2
|
|
arc: JDIA JPADDIA_PIO
|
|
arc: JDIB JPADDIB_PIO
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R29C90:PICR0_DQS2
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R30C0:PICL1_DQS3
|
|
enum: PIOC.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOC.HYSTERESIS ON
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOB.HYSTERESIS ON
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOA.HYSTERESIS ON
|
|
enum: PIOD.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R30C90:PICR1_DQS3
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
enum: PIOD.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOD.HYSTERESIS ON
|
|
|
|
.tile MIB_R31C0:PICL2
|
|
enum: PIOC.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOD.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R31C90:PICR2
|
|
enum: PIOD.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R32C0:PICL0
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R33C0:PICL1
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
enum: PIOD.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOD.HYSTERESIS ON
|
|
|
|
.tile MIB_R33C90:PICR1
|
|
enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R34C0:MIB_CIB_LR
|
|
enum: PIOD.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R34C90:MIB_CIB_LR_A
|
|
enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R58C40:CMUX_LL_0
|
|
arc: G_DCS1CLK0 G_VPFN0000
|
|
arc: G_LLPCLK0 G_VPFS0000
|
|
|
|
.tile MIB_R58C41:CMUX_LR_0
|
|
arc: G_DCS1CLK1 G_VPFN0000
|
|
arc: G_LRPCLK0 G_VPFS0000
|
|
|
|
.tile MIB_R71C4:EFB0_PICB0
|
|
unknown: F54B1
|
|
unknown: F56B1
|
|
unknown: F82B1
|
|
unknown: F94B1
|
|
|
|
.tile R12C5:PLC2
|
|
arc: N3_V06N0103 S3_V06N0103
|
|
|
|
.tile R13C10:PLC2
|
|
arc: S3_V06S0303 N3_V06S0203
|
|
|
|
.tile R13C6:PLC2
|
|
arc: S3_V06S0203 N3_V06S0103
|
|
|
|
.tile R13C9:PLC2
|
|
arc: S3_V06S0103 N3_V06S0003
|
|
|
|
.tile R16C42:PLC2
|
|
arc: N3_V06N0303 S3_V06N0303
|
|
|
|
.tile R18C5:PLC2
|
|
arc: N3_V06N0103 S3_V06N0003
|
|
|
|
.tile R19C10:PLC2
|
|
arc: S3_V06S0003 N3_V06S0303
|
|
|
|
.tile R19C6:PLC2
|
|
arc: S3_V06S0203 N3_V06S0203
|
|
|
|
.tile R19C9:PLC2
|
|
arc: S3_V06S0203 N3_V06S0103
|
|
|
|
.tile R21C21:PLC2
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
|
|
.tile R24C5:PLC2
|
|
arc: N3_V06N0003 S3_V06N0003
|
|
|
|
.tile R25C10:PLC2
|
|
arc: S3_V06S0103 N3_V06S0003
|
|
|
|
.tile R25C6:PLC2
|
|
arc: S3_V06S0303 N3_V06S0203
|
|
|
|
.tile R25C9:PLC2
|
|
arc: S3_V06S0203 N3_V06S0203
|
|
|
|
.tile R26C7:PLC2
|
|
arc: S1_V02S0601 W3_H06E0303
|
|
|
|
.tile R28C11:PLC2
|
|
arc: W1_H02W0501 V02N0501
|
|
|
|
.tile R28C15:PLC2
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
|
|
.tile R28C21:PLC2
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
|
|
.tile R28C27:PLC2
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
|
|
.tile R28C2:PLC2
|
|
arc: W1_H02W0701 E3_H06W0203
|
|
|
|
.tile R28C33:PLC2
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
|
|
.tile R28C39:PLC2
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
|
|
.tile R28C42:PLC2
|
|
arc: N3_V06N0203 H06E0203
|
|
|
|
.tile R28C6:PLC2
|
|
arc: E1_H02E0601 V06S0303
|
|
arc: S1_V02S0201 E1_H02W0201
|
|
|
|
.tile R28C7:PLC2
|
|
arc: E1_H02E0201 S1_V02N0201
|
|
arc: E1_H02E0601 V01N0001
|
|
arc: S1_V02S0101 E1_H01W0100
|
|
arc: S1_V02S0201 E1_H01W0000
|
|
arc: S1_V02S0501 E1_H01W0100
|
|
arc: S1_V02S0701 N1_V02S0601
|
|
|
|
.tile R28C8:PLC2
|
|
arc: S1_V02S0401 V01N0001
|
|
arc: S1_V02S0701 V01N0101
|
|
arc: W3_H06W0203 E1_H01W0000
|
|
arc: A0 S1_V02N0501
|
|
arc: C0 W1_H02E0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H02E0201
|
|
arc: F0 F0_SLICE
|
|
arc: H01W0000 Q0
|
|
arc: H01W0100 Q0
|
|
arc: MUXCLK0 CLK0
|
|
arc: S1_V02S0001 Q0
|
|
arc: S1_V02S0201 Q0
|
|
arc: V01S0000 Q0
|
|
arc: V01S0100 Q0
|
|
arc: W1_H02W0201 Q0
|
|
word: SLICEA.K0.INIT 1111010110100000
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.B0MUX 1
|
|
|
|
.tile R28C9:PLC2
|
|
arc: V00B0100 V02N0101
|
|
arc: A1 V01N0101
|
|
arc: B0 V00T0000
|
|
arc: B1 Q1
|
|
arc: C0 W1_H02E0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02N0201
|
|
arc: D1 V00B0100
|
|
arc: E3_H06E0003 Q0
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: H01W0000 Q1
|
|
arc: LSR0 E1_H02W0501
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: V00T0000 Q0
|
|
word: SLICEA.K1.INIT 1001100101100110
|
|
word: SLICEA.K0.INIT 1100001100111100
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
|
|
.tile R29C10:PLC2
|
|
arc: A0 H01E0001
|
|
arc: B1 Q1
|
|
arc: C0 H00L0000
|
|
arc: C1 H02E0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H02E0201
|
|
arc: D1 H01E0101
|
|
arc: E3_H06E0103 Q1
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: H00L0000 Q0
|
|
arc: H01W0000 Q0
|
|
arc: LSR0 H02W0501
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
word: SLICEA.K0.INIT 1010010101011010
|
|
word: SLICEA.K1.INIT 1100001100111100
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
|
|
.tile R29C11:PLC2
|
|
arc: N1_V02N0501 S1_V02N0501
|
|
arc: W1_H02W0501 S1_V02N0501
|
|
|
|
.tile R29C16:PLC2
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
|
|
.tile R29C22:PLC2
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
|
|
.tile R29C28:PLC2
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
|
|
.tile R29C34:PLC2
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
|
|
.tile R29C3:PLC2
|
|
arc: E3_H06E0303 W1_H02E0501
|
|
arc: S3_V06S0203 E3_H06W0203
|
|
|
|
.tile R29C40:PLC2
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
|
|
.tile R29C46:PLC2
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
|
|
.tile R29C52:PLC2
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
|
|
.tile R29C58:PLC2
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
|
|
.tile R29C5:PLC2
|
|
arc: E1_H02E0301 S1_V02N0301
|
|
arc: V00B0000 S1_V02N0001
|
|
arc: V00B0100 H02W0501
|
|
arc: CLK0 G_HPBX0000
|
|
arc: LSR0 V00B0000
|
|
arc: M2 V00B0100
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXLSR1 LSR0
|
|
arc: S1_V02S0201 Q2
|
|
arc: V01S0000 Q2
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R29C64:PLC2
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
|
|
.tile R29C6:PLC2
|
|
arc: S1_V02S0301 E1_H02W0301
|
|
arc: S1_V02S0501 E1_H02W0501
|
|
arc: CLK0 G_HPBX0000
|
|
arc: H00R0100 Q5
|
|
arc: LSR0 H02E0301
|
|
arc: M5 H02W0001
|
|
arc: M7 H00R0100
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR2 LSR0
|
|
arc: MUXLSR3 LSR0
|
|
arc: W1_H02W0501 Q7
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R29C70:PLC2
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
|
|
.tile R29C76:PLC2
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
|
|
.tile R29C7:PLC2
|
|
arc: E1_H02E0501 W3_H06E0303
|
|
arc: E1_H02E0601 S1_V02N0601
|
|
arc: E1_H02E0701 V02S0701
|
|
arc: H00L0000 H02W0201
|
|
arc: H00L0100 H02W0101
|
|
arc: S1_V02S0701 E1_H01W0100
|
|
arc: V00B0000 V02N0201
|
|
arc: V00T0000 H02W0201
|
|
arc: V00T0100 H02W0101
|
|
arc: W1_H02W0001 V01N0001
|
|
arc: A0 H00L0100
|
|
arc: A1 H00L0100
|
|
arc: A2 H00L0100
|
|
arc: A3 H00L0100
|
|
arc: A4 V00T0100
|
|
arc: A5 E1_H01W0000
|
|
arc: B0 V02S0101
|
|
arc: B1 V02S0101
|
|
arc: B2 V02S0101
|
|
arc: B3 V02S0101
|
|
arc: B4 V02S0501
|
|
arc: B5 E1_H02W0301
|
|
arc: C0 H00L0000
|
|
arc: C1 H00L0000
|
|
arc: C2 H00L0000
|
|
arc: C3 H00L0000
|
|
arc: C4 V00T0000
|
|
arc: C5 E1_H02W0401
|
|
arc: CE0 V02N0201
|
|
arc: CE1 V02N0201
|
|
arc: CLK1 G_HPBX0000
|
|
arc: D0 V02N0201
|
|
arc: D1 V02N0001
|
|
arc: D2 V02N0001
|
|
arc: D3 V02N0001
|
|
arc: D4 E1_H01W0100
|
|
arc: D5 E1_H02W0201
|
|
arc: E1_H02E0101 Q3
|
|
arc: E1_H02E0201 Q0
|
|
arc: E1_H02E0301 Q1
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: LSR1 V00B0000
|
|
arc: MUXCLK0 CLK1
|
|
arc: MUXCLK1 CLK1
|
|
arc: N1_V01N0001 Q2
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
enum: SLICEC.MODE RAMW
|
|
enum: SLICEB.MODE DPRAM
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE DPRAM
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE DPRAM
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE DPRAM
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.WREMUX WRE
|
|
enum: CLK1.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK1.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK1.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK1.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK1.CLKMUX CLK
|
|
|
|
.tile R29C82:PLC2
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
|
|
.tile R29C88:PLC2
|
|
arc: E1_H02E0701 W3_H06E0203
|
|
|
|
.tile R29C8:PLC2
|
|
arc: E1_H02E0101 N1_V01S0100
|
|
arc: E1_H02E0301 N1_V01S0100
|
|
arc: H00L0000 H02W0001
|
|
arc: W1_H02W0301 N1_V01S0100
|
|
arc: W1_H02W0501 N1_V01S0100
|
|
arc: A0 H02E0701
|
|
arc: A1 H02E0501
|
|
arc: A6 H02W0501
|
|
arc: B2 H00L0000
|
|
arc: C0 H00L0000
|
|
arc: C1 H00L0000
|
|
arc: C2 H02E0601
|
|
arc: C6 V00T0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V00T0100
|
|
arc: D1 V02N0201
|
|
arc: D2 N1_V01S0000
|
|
arc: D6 H02W0001
|
|
arc: E1_H01E0001 Q0
|
|
arc: E1_H01E0101 Q6
|
|
arc: E1_H02E0001 Q0
|
|
arc: E1_H02E0201 Q0
|
|
arc: E1_H02E0401 Q6
|
|
arc: E1_H02E0601 Q6
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 Q6
|
|
arc: H01W0100 F7
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q2
|
|
arc: N1_V01N0101 Q0
|
|
arc: S1_V02S0001 Q0
|
|
arc: S1_V02S0101 Q1
|
|
arc: S1_V02S0401 Q6
|
|
arc: S1_V02S0601 Q6
|
|
arc: V00T0000 Q0
|
|
arc: V00T0100 Q1
|
|
arc: V01S0000 Q2
|
|
arc: V01S0100 Q1
|
|
arc: W1_H02W0101 Q1
|
|
arc: W1_H02W0201 Q2
|
|
word: SLICED.K0.INIT 1010101011110000
|
|
word: SLICEA.K0.INIT 1010111110100000
|
|
word: SLICEA.K1.INIT 1010111110100000
|
|
word: SLICEB.K0.INIT 1111001111000000
|
|
word: SLICED.K1.INIT 1111111111111111
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R29C9:PLC2
|
|
arc: E1_H02E0201 W1_H02E0201
|
|
arc: E1_H02E0601 W1_H02E0301
|
|
arc: H00L0000 V02N0001
|
|
arc: H00R0000 H02E0601
|
|
arc: N1_V02N0101 W1_H02E0101
|
|
arc: V00B0000 H02E0401
|
|
arc: W1_H02W0001 E1_H02W0501
|
|
arc: W1_H02W0201 V02N0201
|
|
arc: W1_H02W0301 V02N0301
|
|
arc: W1_H02W0401 H01E0001
|
|
arc: W1_H02W0501 W3_H06E0303
|
|
arc: W3_H06W0203 E1_H01W0000
|
|
arc: A0 V01N0101
|
|
arc: A1 V01N0101
|
|
arc: A2 V01N0101
|
|
arc: A3 V01N0101
|
|
arc: A4 V02N0101
|
|
arc: A5 V00B0000
|
|
arc: B0 V00B0000
|
|
arc: B1 V00B0000
|
|
arc: B2 H00R0000
|
|
arc: B3 H00R0000
|
|
arc: B4 H01E0101
|
|
arc: B5 S1_V02N0501
|
|
arc: C0 H00L0000
|
|
arc: C1 S1_V02N0601
|
|
arc: C2 S1_V02N0401
|
|
arc: C3 S1_V02N0401
|
|
arc: C4 V02N0001
|
|
arc: C5 H01E0001
|
|
arc: CE0 H02E0101
|
|
arc: CE1 H02E0101
|
|
arc: CLK1 G_HPBX0000
|
|
arc: D0 H02E0201
|
|
arc: D1 H02E0001
|
|
arc: D2 H02E0201
|
|
arc: D3 H02E0201
|
|
arc: D4 H02E0001
|
|
arc: D5 V01N0001
|
|
arc: E1_H01E0001 Q0
|
|
arc: E1_H01E0101 Q1
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: LSR1 H02E0301
|
|
arc: MUXCLK0 CLK1
|
|
arc: MUXCLK1 CLK1
|
|
arc: N1_V01N0101 Q3
|
|
arc: N1_V02N0201 Q2
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
enum: SLICEC.MODE RAMW
|
|
enum: SLICEB.MODE DPRAM
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE DPRAM
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE DPRAM
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE DPRAM
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.WREMUX WRE
|
|
enum: CLK1.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK1.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK1.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK1.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK1.CLKMUX CLK
|
|
|
|
.tile R2C42:PLC2
|
|
arc: N1_V02N0501 S1_V02N0501
|
|
|
|
.tile R2C5:PLC2
|
|
arc: N1_V02N0501 S1_V02N0401
|
|
|
|
.tile R30C10:PLC2
|
|
arc: W1_H02W0601 H01E0001
|
|
|
|
.tile R30C11:PLC2
|
|
arc: W1_H02W0501 V02N0501
|
|
|
|
.tile R30C4:PLC2
|
|
arc: H00L0000 E1_H02W0201
|
|
arc: V00B0100 V02N0301
|
|
arc: B0 V00T0000
|
|
arc: C0 H00L0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 E1_H02W0001
|
|
arc: E1_H02E0601 Q6
|
|
arc: F0 F0_SLICE
|
|
arc: LSR1 H02W0301
|
|
arc: M6 V00B0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR3 LSR1
|
|
arc: V00T0000 Q0
|
|
arc: W3_H06W0003 Q0
|
|
word: SLICEA.K0.INIT 1100001100111100
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
|
|
.tile R30C5:PLC2
|
|
arc: E1_H02E0601 N1_V01S0000
|
|
arc: H00R0000 H02E0601
|
|
arc: V00B0000 V02S0201
|
|
arc: V00B0100 V02N0301
|
|
arc: W1_H02W0301 V02N0301
|
|
arc: B0 V00T0000
|
|
arc: C0 E1_H01W0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 E1_H02W0001
|
|
arc: E1_H02E0301 Q3
|
|
arc: F0 F0_SLICE
|
|
arc: LSR0 V00B0100
|
|
arc: LSR1 V00B0100
|
|
arc: M2 N1_V01N0001
|
|
arc: M3 H00R0000
|
|
arc: M4 V00B0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR0
|
|
arc: N1_V01N0001 Q4
|
|
arc: N3_V06N0003 Q0
|
|
arc: S1_V02S0201 Q2
|
|
arc: V00T0000 Q0
|
|
word: SLICEA.K0.INIT 1100001100111100
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
|
|
.tile R30C6:PLC2
|
|
arc: E1_H02E0001 V01N0001
|
|
arc: H00L0000 H02W0201
|
|
arc: H00R0100 H02W0701
|
|
arc: V00B0000 N1_V02S0201
|
|
arc: V00B0100 H02W0701
|
|
arc: V00T0000 H02W0201
|
|
arc: W1_H02W0001 E1_H02W0001
|
|
arc: A0 E1_H02W0701
|
|
arc: A1 E1_H02W0501
|
|
arc: A2 E1_H02W0701
|
|
arc: A3 E1_H02W0701
|
|
arc: A4 E1_H02W0501
|
|
arc: A5 V00B0000
|
|
arc: B0 V00B0000
|
|
arc: B1 V00B0000
|
|
arc: B2 V02S0301
|
|
arc: B3 V02S0301
|
|
arc: B4 V02S0501
|
|
arc: B5 E1_H02W0101
|
|
arc: C0 E1_H02W0601
|
|
arc: C1 E1_H02W0401
|
|
arc: C2 E1_H02W0601
|
|
arc: C3 E1_H02W0601
|
|
arc: C4 E1_H02W0401
|
|
arc: C5 V00B0100
|
|
arc: CE0 H00L0000
|
|
arc: CE1 H00L0000
|
|
arc: CLK1 G_HPBX0000
|
|
arc: D0 H02W0201
|
|
arc: D1 H02W0201
|
|
arc: D2 H02W0201
|
|
arc: D3 H02W0201
|
|
arc: D4 H00R0100
|
|
arc: D5 E1_H02W0201
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: H01W0000 Q3
|
|
arc: LSR1 V00T0000
|
|
arc: MUXCLK0 CLK1
|
|
arc: MUXCLK1 CLK1
|
|
arc: V01S0000 Q1
|
|
arc: V01S0100 Q0
|
|
arc: W1_H02W0201 Q2
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
enum: SLICEC.MODE RAMW
|
|
enum: SLICEB.MODE DPRAM
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE DPRAM
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE DPRAM
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE DPRAM
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.WREMUX WRE
|
|
enum: CLK1.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK1.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK1.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK1.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK1.CLKMUX CLK
|
|
|
|
.tile R30C7:PLC2
|
|
arc: E1_H02E0701 V02S0701
|
|
arc: W1_H02W0001 E1_H01W0000
|
|
arc: W1_H02W0701 V02S0701
|
|
arc: A0 E1_H01E0001
|
|
arc: B0 W1_H02E0301
|
|
arc: C0 W1_H02E0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 N1_V02S0201
|
|
arc: E1_H01E0001 Q0
|
|
arc: F0 F0_SLICE
|
|
arc: LSR1 E1_H02W0501
|
|
arc: M1 H02E0001
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: N1_V01N0001 Q1
|
|
arc: N1_V02N0001 Q0
|
|
arc: N1_V02N0201 Q0
|
|
arc: W1_H02W0201 Q0
|
|
word: SLICEA.K0.INIT 0110100110010110
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET SET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R30C8:PLC2
|
|
arc: E1_H02E0401 V02S0401
|
|
arc: H00L0100 H02W0301
|
|
arc: H00R0000 V02S0401
|
|
arc: H00R0100 N1_V02S0701
|
|
arc: N1_V02N0201 N1_V01S0000
|
|
arc: N1_V02N0501 H02W0501
|
|
arc: S1_V02S0501 E1_H01W0100
|
|
arc: V00B0000 N1_V02S0001
|
|
arc: V00B0100 V02S0101
|
|
arc: V00T0000 V02S0601
|
|
arc: V00T0100 H02W0301
|
|
arc: W1_H02W0101 N1_V01S0100
|
|
arc: W1_H02W0201 N1_V01S0000
|
|
arc: W1_H02W0401 N1_V01S0000
|
|
arc: W1_H02W0501 N1_V01S0100
|
|
arc: W1_H02W0601 N1_V01S0000
|
|
arc: W1_H02W0701 N1_V01S0100
|
|
arc: A0 H00L0100
|
|
arc: A1 H00L0100
|
|
arc: A2 H00L0100
|
|
arc: A3 H00L0100
|
|
arc: A4 V00T0100
|
|
arc: A5 H02E0701
|
|
arc: B0 V00T0000
|
|
arc: B1 V00T0000
|
|
arc: B2 H00R0000
|
|
arc: B3 H00R0000
|
|
arc: B4 H00R0000
|
|
arc: B5 V00B0100
|
|
arc: C0 E1_H01W0000
|
|
arc: C1 E1_H01W0000
|
|
arc: C2 E1_H01W0000
|
|
arc: C3 E1_H01W0000
|
|
arc: C4 E1_H02W0601
|
|
arc: C5 H01E0001
|
|
arc: CE0 N1_V02S0201
|
|
arc: CE1 N1_V02S0201
|
|
arc: CLK1 G_HPBX0000
|
|
arc: D0 V02S0001
|
|
arc: D1 V02S0001
|
|
arc: D2 V02S0001
|
|
arc: D3 V02S0001
|
|
arc: D4 H00R0100
|
|
arc: D5 N1_V02S0401
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: H01W0000 Q3
|
|
arc: LSR1 V00B0000
|
|
arc: MUXCLK0 CLK1
|
|
arc: MUXCLK1 CLK1
|
|
arc: V01S0000 Q0
|
|
arc: V01S0100 Q1
|
|
arc: W1_H02W0001 Q2
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
enum: SLICEC.MODE RAMW
|
|
enum: SLICEB.MODE DPRAM
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE DPRAM
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE DPRAM
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE DPRAM
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.WREMUX WRE
|
|
enum: CLK1.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK1.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK1.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK1.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK1.CLKMUX CLK
|
|
|
|
.tile R30C9:PLC2
|
|
arc: V00T0100 V02N0701
|
|
arc: W1_H02W0501 E1_H02W0501
|
|
arc: A0 E1_H02W0501
|
|
arc: A1 E1_H02W0501
|
|
arc: B1 V00T0000
|
|
arc: C0 H02E0401
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V00T0100
|
|
arc: D1 V02N0201
|
|
arc: E1_H01E0001 Q0
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: H01W0000 Q0
|
|
arc: H01W0100 Q1
|
|
arc: MUXCLK0 CLK0
|
|
arc: N1_V01N0001 Q0
|
|
arc: N1_V01N0101 Q1
|
|
arc: N1_V02N0001 Q0
|
|
arc: N1_V02N0101 Q1
|
|
arc: N1_V02N0201 Q0
|
|
arc: N1_V02N0301 Q1
|
|
arc: V00T0000 Q0
|
|
arc: V01S0000 Q0
|
|
arc: V01S0100 Q1
|
|
arc: W1_H02W0301 Q1
|
|
word: SLICEA.K0.INIT 1111101001010000
|
|
word: SLICEA.K1.INIT 1110111001000100
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R31C10:PLC2
|
|
arc: W1_H02W0201 N3_V06S0103
|
|
arc: W3_H06W0303 E1_H01W0100
|
|
|
|
.tile R31C11:PLC2
|
|
arc: H01W0100 E3_H06W0303
|
|
arc: N1_V02N0501 E3_H06W0303
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
|
|
.tile R31C14:PLC2
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
|
|
.tile R31C17:PLC2
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
|
|
.tile R31C20:PLC2
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
|
|
.tile R31C23:PLC2
|
|
arc: W3_H06W0303 E3_H06W0203
|
|
|
|
.tile R31C26:PLC2
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
|
|
.tile R31C29:PLC2
|
|
arc: W3_H06W0203 E3_H06W0203
|
|
|
|
.tile R31C32:PLC2
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
|
|
.tile R31C35:PLC2
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
|
|
.tile R31C38:PLC2
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
|
|
.tile R31C41:PLC2
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
|
|
.tile R31C44:PLC2
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
|
|
.tile R31C47:PLC2
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
|
|
.tile R31C4:PLC2
|
|
arc: E1_H02E0501 E3_H06W0303
|
|
arc: H00R0000 V02N0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: H00R0100 Q7
|
|
arc: LSR0 H02W0301
|
|
arc: M1 H00R0100
|
|
arc: M7 H00R0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR3 LSR0
|
|
arc: N1_V02N0301 Q1
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R31C50:PLC2
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
|
|
.tile R31C53:PLC2
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
|
|
.tile R31C56:PLC2
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
|
|
.tile R31C59:PLC2
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
|
|
.tile R31C5:PLC2
|
|
arc: E1_H02E0301 E3_H06W0003
|
|
arc: H00L0000 V02S0201
|
|
arc: N1_V02N0001 E3_H06W0003
|
|
arc: N1_V02N0301 E3_H06W0003
|
|
arc: S1_V02S0301 E3_H06W0003
|
|
arc: W1_H02W0301 E3_H06W0003
|
|
arc: CLK0 G_HPBX0000
|
|
arc: LSR0 H02E0501
|
|
arc: M0 V00B0100
|
|
arc: M5 H00L0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR2 LSR0
|
|
arc: S1_V02S0001 Q0
|
|
arc: V00B0100 Q5
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R31C62:PLC2
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
|
|
.tile R31C65:PLC2
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
|
|
.tile R31C68:PLC2
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
|
|
.tile R31C6:PLC2
|
|
arc: E1_H02E0201 N1_V01S0000
|
|
arc: E1_H02E0301 N1_V01S0100
|
|
arc: E1_H02E0501 W1_H02E0501
|
|
arc: H00R0000 V02N0401
|
|
arc: V00T0000 H02W0201
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0101 Q2
|
|
arc: H01W0100 Q1
|
|
arc: LSR1 H02E0301
|
|
arc: M1 H00R0000
|
|
arc: M2 V00T0000
|
|
arc: M3 H01W0100
|
|
arc: M4 E1_H01E0101
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR1
|
|
arc: N1_V01N0001 Q3
|
|
arc: S1_V02S0401 Q4
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R31C71:PLC2
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
|
|
.tile R31C74:PLC2
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
|
|
.tile R31C77:PLC2
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
|
|
.tile R31C7:PLC2
|
|
arc: N1_V02N0601 W3_H06E0303
|
|
arc: V00T0100 H02W0101
|
|
arc: B0 H02E0301
|
|
arc: C0 H00L0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H02W0001
|
|
arc: F0 F0_SLICE
|
|
arc: H00L0000 Q0
|
|
arc: H00R0000 Q4
|
|
arc: LSR1 W1_H02E0301
|
|
arc: M2 V00B0100
|
|
arc: M4 V00T0100
|
|
arc: M7 H00R0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR1
|
|
arc: V00B0100 Q7
|
|
arc: W1_H02W0201 Q2
|
|
arc: W3_H06W0003 Q0
|
|
word: SLICEA.K0.INIT 1100001100111100
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
|
|
.tile R31C80:PLC2
|
|
arc: E1_H01E0001 W3_H06E0003
|
|
|
|
.tile R31C81:PLC2
|
|
arc: E3_H06E0203 H01E0001
|
|
|
|
.tile R31C83:PLC2
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
|
|
.tile R31C87:PLC2
|
|
arc: S3_V06S0203 W3_H06E0203
|
|
|
|
.tile R31C8:PLC2
|
|
arc: H00R0100 V02S0501
|
|
arc: W1_H02W0001 N1_V01S0000
|
|
arc: B0 V00T0000
|
|
arc: C0 N1_V01S0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 W1_H02E0201
|
|
arc: E3_H06E0003 Q0
|
|
arc: F0 F0_SLICE
|
|
arc: LSR1 W1_H02E0501
|
|
arc: M1 H00R0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: V00T0000 Q0
|
|
arc: W1_H02W0101 Q1
|
|
word: SLICEA.K0.INIT 1100001100111100
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
|
|
.tile R31C9:PLC2
|
|
arc: N1_V02N0201 H02W0201
|
|
arc: N1_V02N0401 N1_V01S0000
|
|
arc: N1_V02N0501 N1_V01S0100
|
|
arc: N1_V02N0601 N1_V01S0000
|
|
arc: N1_V02N0701 N3_V06S0203
|
|
|
|
.tile R32C3:PLC2
|
|
arc: W1_H02W0701 V06S0203
|
|
|
|
.tile R32C4:PLC2
|
|
arc: V00T0100 H02W0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: LSR0 H02W0301
|
|
arc: M6 V00T0100
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR3 LSR0
|
|
arc: N1_V02N0601 Q6
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R32C5:PLC2
|
|
arc: E1_H02E0301 V02S0301
|
|
arc: H00L0000 V02S0001
|
|
arc: V00B0100 V02S0301
|
|
arc: W1_H02W0301 V02S0301
|
|
arc: CLK0 G_HPBX0000
|
|
arc: LSR0 V00B0100
|
|
arc: M1 H00L0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: W1_H02W0101 Q1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R32C6:PLC2
|
|
arc: H00R0000 V02S0401
|
|
arc: CLK0 G_HPBX0000
|
|
arc: LSR0 H02E0301
|
|
arc: M5 H00R0000
|
|
arc: M6 V00B0100
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR2 LSR0
|
|
arc: MUXLSR3 LSR0
|
|
arc: N1_V02N0401 Q6
|
|
arc: V00B0100 Q5
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R4C42:PLC2
|
|
arc: N1_V02N0501 S3_V06N0303
|
|
|
|
.tile R4C5:PLC2
|
|
arc: N1_V02N0401 S1_V02N0101
|
|
|
|
.tile R6C5:PLC2
|
|
arc: N1_V02N0101 S3_V06N0103
|
|
|
|
.tile R7C10:PLC2
|
|
arc: S3_V06S0203 N3_V06S0203
|
|
|
|
.tile R7C47:PLC2
|
|
arc: N3_V06N0103 E3_H06W0103
|
|
|
|
.tile R7C53:PLC2
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
|
|
.tile R7C59:PLC2
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
|
|
.tile R7C65:PLC2
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
|
|
.tile R7C6:PLC2
|
|
arc: S3_V06S0103 N3_V06S0003
|
|
|
|
.tile R7C71:PLC2
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
|
|
.tile R7C77:PLC2
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
|
|
.tile R7C83:PLC2
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
|
|
.tile R7C9:PLC2
|
|
arc: S3_V06S0003 N3_V06S0003
|
|
|
|
.tile TAP_R28C13:TAP_DRIVE
|
|
arc: L_HPBX0000 G_VPTX0000
|
|
|
|
.tile TAP_R29C13:TAP_DRIVE
|
|
arc: L_HPBX0000 G_VPTX0000
|
|
|
|
.tile TAP_R30C13:TAP_DRIVE
|
|
arc: L_HPBX0000 G_VPTX0000
|
|
|
|
.tile TAP_R31C13:TAP_DRIVE
|
|
arc: L_HPBX0000 G_VPTX0000
|
|
|
|
.tile TAP_R32C13:TAP_DRIVE
|
|
arc: L_HPBX0000 G_VPTX0000
|
|
|