michele/FPGA-Neural
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity
Files
59901a4905db4f5667a4268d64e4c002b555ccf8
FPGA-Neural/hardware/v2/nms/synthesis/wt_direct_n8_t256/nextpnr.log
T
micheleandClaude Sonnet 5 8e014d8d49 V2.0.0 hardware freeze - single SDRAM 
FASE #1 hardware freeze for FPGA-Neural V2, N4/P8, single external
SDRAM (Alliance Memory AS4C4M16SA-6TIN) serving weights, activations,
and results through one physical sdram_controller.v instance. Removes
the PSRAM dependency (hardware/v1/rtl/psram_controller.v +
memory_interface.v) from the V2 physical path entirely -- V1 itself
remains fully unmodified, the golden reference.

New RTL: sdram_unified_backend.v (2-way W/AR arbitration over one
SDRAM controller, real per-byte DQM write masking added to
sdram_controller.v for correct single-byte result writes with no
read-modify-write), nms_neural_multiprocessor_sdram_unified.v (the
frozen top-level). Two real bugs found and fixed via full-system
testing before being accepted (ERR-0023): a deadlock and an off-by-one
data-shift bug in the new arbitration logic.

Real results: N=4 and N=2 D-Stress bit-exact (256/256 neurons), 40
real AUTO REFRESH events interleaved with zero corruption, real
Yosys+nextpnr-ecp5 synthesis/P&R for LFE5U-45F-8CABGA381 (149/245
TRELLIS_IO, a real 45-pin reduction from the prior dual-memory
design). Timing is MARGINAL (1/8 P&R seeds >=80MHz), reported honestly
rather than masked by the best seed.

Real, sourced ball-level pinout for the SDRAM bus + clk/rst (39/149
signals, P&R-verified) using the official Lattice ECP5U-45 pinout CSV
found on disk during this step's own pre-commit review -- corrects an
earlier draft that wrongly assumed no real pinout data was available.

Chip readiness: NO. Real, disclosed blockers remain (no physical host
interface exists yet -- the RTL's own reg_* ports are a 110-pin raw
test-harness bus; clock source/PLL decision; power/configuration
component selection) -- see hardware/v2/docs/{HARDWARE_FREEZE,
CHIP_READINESS,OPEN_ITEMS}.md for the complete, itemized status.

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
2026-09-06 13:39:55 +02:00

200 lines
9.6 KiB
Plaintext
Raw Blame History

Info: Logic utilisation before packing:
Info: Total LUT4s: 124/43848 0%
Info: logic LUTs: 124/43848 0%
Info: carry LUTs: 0/43848 0%
Info: RAM LUTs: 0/ 5481 0%
Info: RAMW LUTs: 0/10962 0%
Info: Total DFFs: 136/43848 0%
Info: Packing IOs..
Info: Packing constants..
Info: Packing carries...
Info: Packing LUTs...
Info: Packing LUT5-7s...
Info: Packing FFs...
Info: 18 FFs paired with LUTs.
Info: Generating derived timing constraints...
Info: Promoting globals...
Info: promoting clock net clk$TRELLIS_IO_IN to global network
Info: Checksum: 0x1670f00e
Info: Device utilisation:
Info: TRELLIS_IO: 18/ 245 7%
Info: DCCA: 1/ 56 1%
Info: DP16KD: 8/ 108 7%
Info: MULT18X18D: 0/ 72 0%
Info: ALU54B: 0/ 36 0%
Info: EHXPLLL: 0/ 4 0%
Info: EXTREFB: 0/ 2 0%
Info: DCUA: 0/ 2 0%
Info: PCSCLKDIV: 0/ 2 0%
Info: IOLOGIC: 0/ 160 0%
Info: SIOLOGIC: 0/ 85 0%
Info: GSR: 0/ 1 0%
Info: JTAGG: 0/ 1 0%
Info: OSCG: 0/ 1 0%
Info: SEDGA: 0/ 1 0%
Info: DTR: 0/ 1 0%
Info: USRMCLK: 0/ 1 0%
Info: CLKDIVF: 0/ 4 0%
Info: ECLKSYNCB: 0/ 10 0%
Info: DLLDELD: 0/ 8 0%
Info: DDRDLL: 0/ 4 0%
Info: DQSBUFM: 0/ 10 0%
Info: TRELLIS_ECLKBUF: 0/ 8 0%
Info: ECLKBRIDGECS: 0/ 2 0%
Info: DCSC: 0/ 2 0%
Info: TRELLIS_FF: 136/ 43848 0%
Info: TRELLIS_COMB: 126/ 43848 0%
Info: TRELLIS_RAMW: 0/ 5481 0%
Info: Placed 0 cells based on constraints.
Info: Creating initial analytic placement for 239 cells, random placement wirelen = 22024.
Info: at initial placer iter 0, wirelen = 1121
Info: at initial placer iter 1, wirelen = 1054
Info: at initial placer iter 2, wirelen = 1018
Info: at initial placer iter 3, wirelen = 1001
Info: Running main analytical placer, max placement attempts per cell = 10440.
Info: at iteration #1, type ALL: wirelen solved = 990, spread = 4556, legal = 4538; time = 0.01s
Info: at iteration #2, type ALL: wirelen solved = 1000, spread = 4277, legal = 4337; time = 0.00s
Info: at iteration #3, type ALL: wirelen solved = 1000, spread = 4304, legal = 4342; time = 0.00s
Info: at iteration #4, type ALL: wirelen solved = 1134, spread = 4250, legal = 4315; time = 0.00s
Info: at iteration #5, type ALL: wirelen solved = 1164, spread = 4520, legal = 4547; time = 0.00s
Info: at iteration #6, type ALL: wirelen solved = 1153, spread = 4554, legal = 4606; time = 0.00s
Info: at iteration #7, type ALL: wirelen solved = 1216, spread = 4502, legal = 4552; time = 0.00s
Info: at iteration #8, type ALL: wirelen solved = 1240, spread = 4698, legal = 4704; time = 0.00s
Info: at iteration #9, type ALL: wirelen solved = 1227, spread = 4951, legal = 4986; time = 0.00s
Info: HeAP Placer Time: 0.06s
Info: of which solving equations: 0.03s
Info: of which spreading cells: 0.01s
Info: of which strict legalisation: 0.00s
Info: Running simulated annealing placer for refinement.
Info: at iteration #1: temp = 0.000000, timing cost = 41, wirelen = 4315
Info: at iteration #5: temp = 0.000000, timing cost = 46, wirelen = 3439
Info: at iteration #10: temp = 0.000000, timing cost = 42, wirelen = 3372
Info: at iteration #11: temp = 0.000000, timing cost = 36, wirelen = 3375
Info: SA placement time 0.03s
Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 118.54 MHz (PASS at 80.00 MHz)
Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 6.07 ns
Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 6.53 ns
Info: Slack histogram:
Info: legend: * represents 3 endpoint(s)
Info: + represents [1,3) endpoint(s)
Info: [ 4064, 4448) |+
Info: [ 4448, 4832) |+
Info: [ 4832, 5216) |+
Info: [ 5216, 5600) |+
Info: [ 5600, 5984) |
Info: [ 5984, 6368) |
Info: [ 6368, 6752) |
Info: [ 6752, 7136) |
Info: [ 7136, 7520) |
Info: [ 7520, 7904) |
Info: [ 7904, 8288) |
Info: [ 8288, 8672) |
Info: [ 8672, 9056) |
Info: [ 9056, 9440) |**+
Info: [ 9440, 9824) |***************+
Info: [ 9824, 10208) |******************************************+
Info: [ 10208, 10592) |************************************************************
Info: [ 10592, 10976) |*******************************************+
Info: [ 10976, 11360) |*********************+
Info: [ 11360, 11744) |***********+
Info: Checksum: 0x9978c53f
Info: Routing globals...
Info: routing clock net $glbnet$clk$TRELLIS_IO_IN using global 0
Info: Routing..
Info: Setting up routing queue.
Info: Routing 1105 arcs.
Info: | (re-)routed arcs | delta | remaining| time spent |
Info: IterCnt | w/ripup wo/ripup | w/r wo/r | arcs| batch(sec) total(sec)|
Info: 1000 | 157 836 | 157 836 | 275| 0.17 0.17|
Info: 1316 | 194 1111 | 37 275 | 0| 0.04 0.21|
Info: Routing complete.
Info: Router1 time 0.21s
Info: Checksum: 0xf5d95f64
Info: Critical path report for clock '$glbnet$clk$TRELLIS_IO_IN' (posedge -> posedge):
Info: type curr total name
Info: clk-to-q 4.10 4.10 Source dut.GEN_SLOT[0].mem.0.0.DOA4
Info: routing 1.34 5.43 Net dut.GEN_SLOT[0].mem.0.0_DOA4[1] (10,10) -> (5,20)
Info: Sink dut.GEN_SLOT[6].mem.0.0_DOA4_LUT4_Z.C
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 5.61 Source dut.GEN_SLOT[6].mem.0.0_DOA4_LUT4_Z.F
Info: routing 0.31 5.93 Net dut.GEN_SLOT[6].mem.0.0_DOA4[3] (5,20) -> (5,20)
Info: Sink dut.GEN_SLOT[2].mem.0.0_DOA4_LUT4_C_Z_LUT4_Z.D
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 6.11 Source dut.GEN_SLOT[2].mem.0.0_DOA4_LUT4_C_Z_LUT4_Z.F
Info: routing 0.51 6.61 Net dut.GEN_SLOT[2].mem.0.0_DOA4_LUT4_C_Z[4] (5,20) -> (5,21)
Info: Sink dut.GEN_SLOT[2].mem.0.0_DOA0_LUT4_D_Z_LUT4_D_Z_PFUMX_Z_BLUT_LUT4_Z.M
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.19 6.81 Source dut.GEN_SLOT[2].mem.0.0_DOA0_LUT4_D_Z_LUT4_D_Z_PFUMX_Z_BLUT_LUT4_Z.OFX
Info: routing 0.51 7.31 Net dut.GEN_SLOT[2].mem.0.0_DOA0_LUT4_D_Z_LUT4_D_Z[4] (5,21) -> (5,20)
Info: Sink chk_TRELLIS_FF_Q_1.M
Info: setup 0.00 7.31 Source chk_TRELLIS_FF_Q_1.M
Info: 4.65 ns logic, 2.66 ns routing
Info: Critical path report for cross-domain path '<async>' -> 'posedge $glbnet$clk$TRELLIS_IO_IN':
Info: type curr total name
Info: source 0.00 0.00 Source seed[4]$tr_io.O
Info: routing 3.89 3.89 Net seed[4]$TRELLIS_IO_IN (90,26) -> (6,26)
Info: Sink seed_LUT4_B_Z_LUT4_Z.B
Info: Defined in:
Info: hardware/v2/nms/synthesis/harness_nms_weight_direct.v:14.23-14.27
Info: logic 0.18 4.07 Source seed_LUT4_B_Z_LUT4_Z.F
Info: routing 0.12 4.18 Net seed_LUT4_B_Z[4] (6,26) -> (6,26)
Info: Sink lfsr_TRELLIS_FF_Q_18.DI
Info: setup 0.00 4.18 Source lfsr_TRELLIS_FF_Q_18.DI
Info: 0.18 ns logic, 4.01 ns routing
Info: Critical path report for cross-domain path 'posedge $glbnet$clk$TRELLIS_IO_IN' -> '<async>':
Info: type curr total name
Info: clk-to-q 0.40 0.40 Source chk_TRELLIS_FF_Q.Q
Info: routing 3.83 4.22 Net checksum[3]$TRELLIS_IO_OUT (4,18) -> (90,17)
Info: Sink checksum[3]$tr_io.I
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: 0.40 ns logic, 3.83 ns routing
Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 136.72 MHz (PASS at 80.00 MHz)
Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 4.18 ns
Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 4.22 ns
Info: Slack histogram:
Info: legend: * represents 4 endpoint(s)
Info: + represents [1,4) endpoint(s)
Info: [ 5186, 5517) |*+
Info: [ 5517, 5848) |+
Info: [ 5848, 6179) |
Info: [ 6179, 6510) |
Info: [ 6510, 6841) |
Info: [ 6841, 7172) |
Info: [ 7172, 7503) |
Info: [ 7503, 7834) |
Info: [ 7834, 8165) |
Info: [ 8165, 8496) |
Info: [ 8496, 8827) |
Info: [ 8827, 9158) |+
Info: [ 9158, 9489) |+
Info: [ 9489, 9820) |+
Info: [ 9820, 10151) |***+
Info: [ 10151, 10482) |***************************************+
Info: [ 10482, 10813) |************************************************************
Info: [ 10813, 11144) |***************************+
Info: [ 11144, 11475) |*********************+
Info: [ 11475, 11806) |****+
Info: Program finished normally.
Reference in New Issue View Git Blame Copy Permalink