micheleandClaude Sonnet 5 598feb975b feat: first genuine N=2 multi-core system verified against real DDR3 (EXP-0070) ...

Swapped mig_native_adapter.v + sdram_arbiter_n.v into the full N=2
system (neural_director_packed.v + 2x packed_slot.v), replacing the
SDR SDRAM placeholder used since EXP-0057. Verified against the real
Vivado-generated ddr3_model.sv end-to-end: 8/8 positions bit-exact
against golden model, 0 errors, real JEDEC command traffic observed.

This is the first fully real V3 system-level correctness result:
real packed DSP cores + real weight-reuse scheduling + real N-way
arbitration + real DDR3 timing, all verified together.

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01MUG92aM9m68TRc4rG55BcC

2026-09-17 08:51:43 +02:00

..

rtl

feat: real DDR3 memory path verified against MIG's own ddr3_model.sv (EXP-0068)

2026-09-17 08:43:22 +02:00

sim

feat: first genuine N=2 multi-core system verified against real DDR3 (EXP-0070)

2026-09-17 08:51:43 +02:00

synth

exp: real P&R of the N=2 multi-core system, first genuine system Fmax (EXP-0067)

2026-09-17 00:21:01 +02:00