micheleandClaude Sonnet 5
8e014d8d49
FASE #1 hardware freeze for FPGA-Neural V2, N4/P8, single external SDRAM (Alliance Memory AS4C4M16SA-6TIN) serving weights, activations, and results through one physical sdram_controller.v instance. Removes the PSRAM dependency (hardware/v1/rtl/psram_controller.v + memory_interface.v) from the V2 physical path entirely -- V1 itself remains fully unmodified, the golden reference. New RTL: sdram_unified_backend.v (2-way W/AR arbitration over one SDRAM controller, real per-byte DQM write masking added to sdram_controller.v for correct single-byte result writes with no read-modify-write), nms_neural_multiprocessor_sdram_unified.v (the frozen top-level). Two real bugs found and fixed via full-system testing before being accepted (ERR-0023): a deadlock and an off-by-one data-shift bug in the new arbitration logic. Real results: N=4 and N=2 D-Stress bit-exact (256/256 neurons), 40 real AUTO REFRESH events interleaved with zero corruption, real Yosys+nextpnr-ecp5 synthesis/P&R for LFE5U-45F-8CABGA381 (149/245 TRELLIS_IO, a real 45-pin reduction from the prior dual-memory design). Timing is MARGINAL (1/8 P&R seeds >=80MHz), reported honestly rather than masked by the best seed. Real, sourced ball-level pinout for the SDRAM bus + clk/rst (39/149 signals, P&R-verified) using the official Lattice ECP5U-45 pinout CSV found on disk during this step's own pre-commit review -- corrects an earlier draft that wrongly assumed no real pinout data was available. Chip readiness: NO. Real, disclosed blockers remain (no physical host interface exists yet -- the RTL's own reg_* ports are a 110-pin raw test-harness bus; clock source/PLL decision; power/configuration component selection) -- see hardware/v2/docs/{HARDWARE_FREEZE, CHIP_READINESS,OPEN_ITEMS}.md for the complete, itemized status. Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
233 lines
9.3 KiB
Verilog
233 lines
9.3 KiB
Verilog
// ============================================================
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// Neural Memory System (NMS) -- STEP11: per-slot memory manager, REAL
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// WEIGHT PREFETCH variant ("_pf").
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//
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// Identical external interface to nms_memory_manager.v (drop-in, same
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// Director/Dependency-Manager side, same Neural-Processor-facing
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// operand/result streams) -- the ONLY change is the private weight
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// path: prefetch_engine.v (single-shot, one tile in flight, real
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// per-tile control-restart overhead, ERR-0013/STEP11's own analysis)
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// is replaced by weight_prefetch_engine.v (continuous multi-tile
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// fetch stream, configurable PREFETCH_DISTANCE lookahead window).
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//
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// nms_memory_manager.v itself is UNTOUCHED -- this file exists
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// alongside it specifically so "Current NMS" (baseline) and "NMS +
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// weight prefetch" remain independently reproducible for the A/B
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// comparison STEP11 explicitly requires.
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// ============================================================
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module nms_memory_manager_pf #(
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parameter DATA_WIDTH = 8,
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parameter P_IN = 8,
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parameter ADDR_WIDTH = 23,
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parameter MAX_TILES = 16,
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parameter PREFETCH_DISTANCE = 8,
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parameter TIW = (MAX_TILES <= 1) ? 1 : $clog2(MAX_TILES),
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parameter CNTW = $clog2(MAX_TILES+1)
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)(
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input wire clk,
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input wire rst,
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input wire job_start,
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input wire [ADDR_WIDTH-1:0] x_base,
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input wire [ADDR_WIDTH-1:0] w_base,
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input wire [15:0] n_tiles,
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input wire [ADDR_WIDTH-1:0] result_addr,
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output reg job_done,
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output reg operand_valid,
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input wire operand_ready,
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output reg signed [DATA_WIDTH*P_IN-1:0] input_data,
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output reg signed [DATA_WIDTH*P_IN-1:0] weight_data,
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output reg tile_last,
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input wire result_valid,
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output reg result_ready,
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input wire signed [DATA_WIDTH-1:0] result_data,
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output wire job_active,
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output wire [ADDR_WIDTH-1:0] job_x_base,
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output wire [15:0] job_n_tiles,
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input wire [ADDR_WIDTH-1:0] act_resident_tag,
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input wire [CNTW-1:0] act_resident_count,
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output reg act_rd_en,
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output reg [TIW-1:0] act_rd_addr,
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input wire signed [DATA_WIDTH*P_IN-1:0] act_rd_data,
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// ---- weight SRAM fill port now driven by weight_prefetch_engine
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// (below), NOT by this FSM directly -- read port unchanged ----
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output wire wgt_fill_we,
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output wire [TIW-1:0] wgt_fill_addr,
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output wire [DATA_WIDTH*P_IN-1:0] wgt_fill_data,
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output reg wgt_rd_en,
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output reg [TIW-1:0] wgt_rd_addr,
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input wire signed [DATA_WIDTH*P_IN-1:0] wgt_rd_data,
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output wire mem_req,
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output wire mem_wr,
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output wire [ADDR_WIDTH-1:0] mem_addr,
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output wire [15:0] mem_wdata,
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output wire mem_lb_n,
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output wire mem_ub_n,
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input wire [15:0] mem_rdata,
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input wire mem_ready
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);
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localparam ST_IDLE = 3'd0;
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localparam ST_RUN = 3'd1;
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localparam ST_WAIT_RESULT = 3'd2;
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localparam ST_WRITE_RES = 3'd3;
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localparam ST_DONE = 3'd4;
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reg [2:0] state;
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reg job_active_reg;
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assign job_active = job_active_reg;
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assign job_x_base = x_base_reg;
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assign job_n_tiles = n_tiles_reg;
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reg [ADDR_WIDTH-1:0] x_base_reg, w_base_reg, result_addr_reg;
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reg [15:0] n_tiles_reg;
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reg [CNTW-1:0] tile_idx;
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reg read_issued;
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reg read_ready;
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wire [CNTW-1:0] wgt_ready_count;
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wire usable_act_count_valid = (act_resident_tag == x_base_reg);
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wire [CNTW-1:0] usable_act = usable_act_count_valid ? act_resident_count : {CNTW{1'b0}};
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wire can_present = ({{(16-CNTW){1'b0}}, tile_idx} < n_tiles_reg) &&
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(tile_idx < wgt_ready_count) &&
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(tile_idx < usable_act);
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// ---- REAL weight prefetch engine (STEP11): continuous multi-tile
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// fetch stream, PREFETCH_DISTANCE-bounded lookahead ahead of
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// tile_idx (this module's own consumption pointer) ----
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weight_prefetch_engine #(
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.DATA_WIDTH(DATA_WIDTH), .P_IN(P_IN), .ADDR_WIDTH(ADDR_WIDTH),
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.MAX_TILES(MAX_TILES), .PREFETCH_DISTANCE(PREFETCH_DISTANCE)
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) u_wpf (
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.clk(clk), .rst(rst),
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.job_active(job_active_reg), .w_base(w_base_reg), .n_tiles(n_tiles_reg),
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.consumed_count(tile_idx),
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.wgt_fill_we(wgt_fill_we), .wgt_fill_addr(wgt_fill_addr), .wgt_fill_data(wgt_fill_data),
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.ready_count(wgt_ready_count),
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.mem_req(mem_req_wpf), .mem_wr(mem_wr_wpf), .mem_addr(mem_addr_wpf), .mem_wdata(mem_wdata_wpf),
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.mem_lb_n(mem_lb_n_wpf), .mem_ub_n(mem_ub_n_wpf),
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.mem_rdata(mem_rdata), .mem_ready(mem_ready)
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);
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wire mem_req_wpf, mem_wr_wpf;
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wire [ADDR_WIDTH-1:0] mem_addr_wpf;
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wire [15:0] mem_wdata_wpf;
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wire mem_lb_n_wpf, mem_ub_n_wpf;
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reg wr_mem_req;
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reg [ADDR_WIDTH-1:0] wr_mem_addr;
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reg [15:0] wr_mem_wdata;
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reg wr_mem_lb_n, wr_mem_ub_n;
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wire wr_active = (state == ST_WRITE_RES) || (state == ST_DONE);
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assign mem_req = wr_active ? wr_mem_req : mem_req_wpf;
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assign mem_wr = wr_active ? 1'b1 : mem_wr_wpf;
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assign mem_addr = wr_active ? wr_mem_addr : mem_addr_wpf;
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assign mem_wdata = wr_active ? wr_mem_wdata : mem_wdata_wpf;
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assign mem_lb_n = wr_active ? wr_mem_lb_n : mem_lb_n_wpf;
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assign mem_ub_n = wr_active ? wr_mem_ub_n : mem_ub_n_wpf;
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always @(posedge clk) begin
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if (rst) begin
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state <= ST_IDLE;
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job_active_reg <= 1'b0;
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job_done <= 1'b0;
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operand_valid <= 1'b0;
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tile_last <= 1'b0;
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result_ready <= 1'b0;
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tile_idx <= {CNTW{1'b0}};
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read_issued <= 1'b0;
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read_ready <= 1'b0;
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act_rd_en <= 1'b0;
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wgt_rd_en <= 1'b0;
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wr_mem_req <= 1'b0;
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wr_mem_lb_n <= 1'b1;
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wr_mem_ub_n <= 1'b1;
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end else begin
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job_done <= 1'b0;
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act_rd_en <= 1'b0;
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wgt_rd_en <= 1'b0;
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result_ready <= 1'b0;
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case (state)
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ST_IDLE: begin
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if (job_start) begin
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x_base_reg <= x_base;
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w_base_reg <= w_base;
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n_tiles_reg <= n_tiles;
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result_addr_reg <= result_addr;
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tile_idx <= {CNTW{1'b0}};
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read_issued <= 1'b0;
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read_ready <= 1'b0;
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operand_valid <= 1'b0;
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job_active_reg <= 1'b1;
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state <= ST_RUN;
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end
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end
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ST_RUN: begin
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if (!operand_valid && !read_issued && !read_ready && can_present) begin
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act_rd_en <= 1'b1;
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act_rd_addr <= tile_idx[TIW-1:0];
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wgt_rd_en <= 1'b1;
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wgt_rd_addr <= tile_idx[TIW-1:0];
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read_issued <= 1'b1;
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end else if (read_issued) begin
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read_issued <= 1'b0;
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read_ready <= 1'b1;
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end else if (read_ready) begin
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operand_valid <= 1'b1;
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input_data <= act_rd_data;
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weight_data <= wgt_rd_data;
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tile_last <= ({{(16-CNTW){1'b0}}, tile_idx} == n_tiles_reg - 16'd1);
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read_ready <= 1'b0;
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end else if (operand_valid && operand_ready) begin
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operand_valid <= 1'b0;
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if ({{(16-CNTW){1'b0}}, tile_idx} + 16'd1 == n_tiles_reg) begin
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job_active_reg <= 1'b0;
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state <= ST_WAIT_RESULT;
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end else begin
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tile_idx <= tile_idx + 1'b1;
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end
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end
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end
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ST_WAIT_RESULT: begin
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result_ready <= 1'b1;
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if (result_valid && result_ready) begin
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wr_mem_wdata <= result_addr_reg[0] ? {result_data, 8'h00} : {8'h00, result_data};
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wr_mem_lb_n <= result_addr_reg[0] ? 1'b1 : 1'b0;
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wr_mem_ub_n <= result_addr_reg[0] ? 1'b0 : 1'b1;
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state <= ST_WRITE_RES;
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end
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end
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ST_WRITE_RES: begin
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wr_mem_req <= 1'b1;
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wr_mem_addr <= result_addr_reg[ADDR_WIDTH-1:1];
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state <= ST_DONE;
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end
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ST_DONE: begin
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wr_mem_req <= 1'b0;
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if (mem_ready) begin
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job_done <= 1'b1;
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state <= ST_IDLE;
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end
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end
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default: state <= ST_IDLE;
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endcase
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end
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end
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endmodule
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