micheleandClaude Sonnet 5
55c827bedf
PSRAM page-mode read burst support in psram_controller.v: enables the ISSI IS66WVE4M16EBLL-70BLI's page mode via its configuration-register software-access sequence at boot (disabled by default on the real chip), then keeps CE#/OE# asserted after a read so a same-page continuation only pays tAPA (20ns) instead of a full tAA (70ns) random access, with automatic tCEM-safe session closing. Only a WRITE closes the page -- byte-enable changes do not, since int8_memory_access.v alternates them on nearly every access and an early implementation attempt that treated them as a close condition measured a real regression (53.25->61.25 cycles/edge) before being corrected (53.25->37.53 cycles/edge, +42% gather bandwidth). sim/psram_model.v gained independent tAPA/tAA and tCEM enforcement (with a real Verilog same-timestep event-ordering race found and fixed via a #0 sync) so the regression proves real timing compliance, not just data correctness. New sim/psram_page_mode_tb.v; full 26-file regression suite re-run clean. Real nextpnr-ecp5 Fmax re-measured on the full spi_neuron_top system: 75.73MHz (P2, up from 55.59MHz) and 65.13MHz (P8) -- still under the 80MHz target but not regressed, with the critical path confirmed (not assumed) to remain entirely inside neuron_parallel's accumulate chain, never psram_controller. Also includes this session's other already-validated work: the graph engine (Type #2 sparse-graph network: act_buffer, graph_engine, netasm host assembler), real CABGA381 pinout (.lpf, place&route verified) and physical IRQ_N/DATA_READY_N pins, and Phase 7 timing closure logs -- all previously uncommitted, documented in WORKLOG.md. Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01LH3jPeJ3eFMfF2v8SQhpkk
455 lines
48 KiB
Plaintext
455 lines
48 KiB
Plaintext
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Info: Logic utilisation before packing:
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Info: Total LUT4s: 3149/43848 7%
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Info: logic LUTs: 2367/43848 5%
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Info: carry LUTs: 782/43848 1%
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Info: RAM LUTs: 0/ 5481 0%
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Info: RAMW LUTs: 0/10962 0%
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Info: Total DFFs: 2406/43848 5%
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Info: Packing IOs..
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Info: $psram_dq[15]$iobuf_i: psram_dq_$_TBUF__Y.Y
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Info: $psram_dq[14]$iobuf_i: psram_dq_$_TBUF__Y_15.Y
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Info: $psram_dq[13]$iobuf_i: psram_dq_$_TBUF__Y_14.Y
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Info: $psram_dq[12]$iobuf_i: psram_dq_$_TBUF__Y_13.Y
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Info: $psram_dq[11]$iobuf_i: psram_dq_$_TBUF__Y_12.Y
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Info: $psram_dq[10]$iobuf_i: psram_dq_$_TBUF__Y_11.Y
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Info: $psram_dq[9]$iobuf_i: psram_dq_$_TBUF__Y_10.Y
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Info: $psram_dq[8]$iobuf_i: psram_dq_$_TBUF__Y_9.Y
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Info: $psram_dq[7]$iobuf_i: psram_dq_$_TBUF__Y_8.Y
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Info: $psram_dq[6]$iobuf_i: psram_dq_$_TBUF__Y_7.Y
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Info: $psram_dq[5]$iobuf_i: psram_dq_$_TBUF__Y_6.Y
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Info: $psram_dq[4]$iobuf_i: psram_dq_$_TBUF__Y_5.Y
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Info: $psram_dq[3]$iobuf_i: psram_dq_$_TBUF__Y_4.Y
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Info: $psram_dq[2]$iobuf_i: psram_dq_$_TBUF__Y_3.Y
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Info: $psram_dq[1]$iobuf_i: psram_dq_$_TBUF__Y_2.Y
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Info: $psram_dq[0]$iobuf_i: psram_dq_$_TBUF__Y_1.Y
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Info: Packing constants..
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Info: Packing carries...
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Info: Packing LUTs...
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Info: Packing LUT5-7s...
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Info: Packing FFs...
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Info: 531 FFs paired with LUTs.
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Info: Generating derived timing constraints...
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Info: Promoting globals...
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Info: promoting clock net clk$TRELLIS_IO_IN to global network
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Info: Checksum: 0x5c4a2f5c
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Info: Device utilisation:
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Info: TRELLIS_IO: 51/ 245 20%
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Info: DCCA: 1/ 56 1%
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Info: DP16KD: 2/ 108 1%
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Info: MULT18X18D: 4/ 72 5%
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Info: ALU54B: 0/ 36 0%
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Info: EHXPLLL: 0/ 4 0%
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Info: EXTREFB: 0/ 2 0%
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Info: DCUA: 0/ 2 0%
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Info: PCSCLKDIV: 0/ 2 0%
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Info: IOLOGIC: 0/ 160 0%
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Info: SIOLOGIC: 0/ 85 0%
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Info: GSR: 0/ 1 0%
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Info: JTAGG: 0/ 1 0%
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Info: OSCG: 0/ 1 0%
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Info: SEDGA: 0/ 1 0%
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Info: DTR: 0/ 1 0%
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Info: USRMCLK: 0/ 1 0%
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Info: CLKDIVF: 0/ 4 0%
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Info: ECLKSYNCB: 0/ 10 0%
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Info: DLLDELD: 0/ 8 0%
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Info: DDRDLL: 0/ 4 0%
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Info: DQSBUFM: 0/ 10 0%
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Info: TRELLIS_ECLKBUF: 0/ 8 0%
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Info: ECLKBRIDGECS: 0/ 2 0%
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Info: DCSC: 0/ 2 0%
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Info: TRELLIS_FF: 2406/ 43848 5%
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Info: TRELLIS_COMB: 3323/ 43848 7%
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Info: TRELLIS_RAMW: 0/ 5481 0%
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Info: Placed 0 cells based on constraints.
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Info: Creating initial analytic placement for 3949 cells, random placement wirelen = 288769.
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Info: at initial placer iter 0, wirelen = 6890
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Info: at initial placer iter 1, wirelen = 5748
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Info: at initial placer iter 2, wirelen = 5649
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Info: at initial placer iter 3, wirelen = 5500
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Info: Running main analytical placer, max placement attempts per cell = 4186171.
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Info: at iteration #1, type ALL: wirelen solved = 5383, spread = 39030, legal = 42969; time = 0.06s
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Info: at iteration #2, type ALL: wirelen solved = 7509, spread = 31684, legal = 34802; time = 0.05s
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Info: at iteration #3, type ALL: wirelen solved = 9013, spread = 26738, legal = 29801; time = 0.05s
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Info: at iteration #4, type ALL: wirelen solved = 10004, spread = 23829, legal = 26763; time = 0.05s
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Info: at iteration #5, type ALL: wirelen solved = 11589, spread = 22527, legal = 25422; time = 0.05s
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Info: at iteration #6, type ALL: wirelen solved = 12653, spread = 21357, legal = 24399; time = 0.04s
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Info: at iteration #7, type ALL: wirelen solved = 12926, spread = 22524, legal = 24721; time = 0.04s
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Info: at iteration #8, type ALL: wirelen solved = 14389, spread = 22702, legal = 24274; time = 0.04s
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Info: at iteration #9, type ALL: wirelen solved = 15595, spread = 21999, legal = 23756; time = 0.04s
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Info: at iteration #10, type ALL: wirelen solved = 15732, spread = 22001, legal = 24381; time = 0.04s
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Info: at iteration #11, type ALL: wirelen solved = 16261, spread = 26159, legal = 27602; time = 0.04s
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Info: at iteration #12, type ALL: wirelen solved = 19061, spread = 22799, legal = 25029; time = 0.04s
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Info: at iteration #13, type ALL: wirelen solved = 18034, spread = 21603, legal = 24515; time = 0.04s
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Info: at iteration #14, type ALL: wirelen solved = 17581, spread = 23933, legal = 26144; time = 0.04s
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Info: HeAP Placer Time: 0.88s
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Info: of which solving equations: 0.58s
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Info: of which spreading cells: 0.09s
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Info: of which strict legalisation: 0.09s
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Info: Running simulated annealing placer for refinement.
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Info: at iteration #1: temp = 0.000000, timing cost = 1222, wirelen = 23756
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Info: at iteration #5: temp = 0.000000, timing cost = 1311, wirelen = 19908
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Info: at iteration #10: temp = 0.000000, timing cost = 1167, wirelen = 18883
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Info: at iteration #15: temp = 0.000000, timing cost = 1224, wirelen = 18364
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Info: at iteration #20: temp = 0.000000, timing cost = 1212, wirelen = 18001
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Info: at iteration #25: temp = 0.000000, timing cost = 1189, wirelen = 17890
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Info: at iteration #30: temp = 0.000000, timing cost = 1185, wirelen = 17832
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Info: at iteration #32: temp = 0.000000, timing cost = 1182, wirelen = 17826
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Info: SA placement time 2.28s
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Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 55.56 MHz (FAIL at 80.00 MHz)
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Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 9.59 ns
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Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 8.45 ns
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Info: Slack histogram:
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Info: legend: * represents 16 endpoint(s)
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Info: + represents [1,16) endpoint(s)
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Info: [ -5498, -4626) |+
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Info: [ -4626, -3754) |+
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Info: [ -3754, -2882) |+
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Info: [ -2882, -2010) |**+
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Info: [ -2010, -1138) |+
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Info: [ -1138, -266) |+
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Info: [ -266, 606) |
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Info: [ 606, 1478) |
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Info: [ 1478, 2350) |
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Info: [ 2350, 3222) |+
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Info: [ 3222, 4094) |*****+
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Info: [ 4094, 4966) |*******+
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Info: [ 4966, 5838) |***********+
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Info: [ 5838, 6710) |******************************************************+
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Info: [ 6710, 7582) |****************************************+
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Info: [ 7582, 8454) |****************************************+
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Info: [ 8454, 9326) |**********************************+
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Info: [ 9326, 10198) |*************************************************+
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Info: [ 10198, 11070) |************************************************************
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Info: [ 11070, 11942) |*************************************+
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Info: Checksum: 0x72c14411
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Info: Routing globals...
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Info: routing clock net $glbnet$clk$TRELLIS_IO_IN using global 0
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Info: Routing..
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Info: Setting up routing queue.
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Info: Routing 16416 arcs.
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Info: | (re-)routed arcs | delta | remaining| time spent |
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Info: IterCnt | w/ripup wo/ripup | w/r wo/r | arcs| batch(sec) total(sec)|
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Info: 1000 | 338 661 | 338 661 | 15767| 0.16 0.16|
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Info: 2000 | 648 1351 | 310 690 | 15166| 0.08 0.24|
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Info: 3000 | 927 2072 | 279 721 | 14505| 0.08 0.32|
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Info: 4000 | 1359 2640 | 432 568 | 14040| 0.12 0.44|
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Info: 5000 | 1665 3334 | 306 694 | 13405| 0.11 0.55|
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Info: 6000 | 1992 4007 | 327 673 | 12798| 0.10 0.66|
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Info: 7000 | 2432 4567 | 440 560 | 12454| 0.15 0.81|
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Info: 8000 | 2831 5168 | 399 601 | 11914| 0.12 0.93|
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Info: 9000 | 3084 5882 | 253 714 | 11183| 0.08 1.00|
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Info: 10000 | 3374 6437 | 290 555 | 10498| 0.07 1.08|
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Info: 11000 | 3870 6888 | 496 451 | 10036| 0.08 1.16|
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Info: 12000 | 4408 7325 | 538 437 | 9594| 0.08 1.24|
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Info: 13000 | 4913 7817 | 505 492 | 9149| 0.09 1.33|
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Info: 14000 | 5434 8296 | 521 479 | 8727| 0.12 1.45|
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Info: 15000 | 5942 8788 | 508 492 | 8254| 0.10 1.54|
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Info: 16000 | 6101 9629 | 159 841 | 7426| 0.13 1.68|
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Info: 17000 | 6216 10510 | 115 881 | 6592| 0.12 1.80|
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Info: 18000 | 6338 11356 | 122 846 | 5740| 0.12 1.92|
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Info: 19000 | 6439 12175 | 101 819 | 4859| 0.09 2.01|
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Info: 20000 | 6531 12972 | 92 797 | 3962| 0.10 2.11|
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Info: 21000 | 6597 13805 | 66 833 | 3038| 0.08 2.19|
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Info: 22000 | 6680 14650 | 83 845 | 2150| 0.09 2.27|
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Info: 23000 | 6771 15530 | 91 880 | 1252| 0.10 2.38|
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Info: 24000 | 6791 16414 | 20 884 | 276| 0.13 2.50|
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Info: 24282 | 6797 16660 | 6 246 | 0| 0.05 2.55|
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Info: Routing complete.
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Info: Router1 time 2.55s
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Info: Checksum: 0x546593af
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Info: Critical path report for clock '$glbnet$clk$TRELLIS_IO_IN' (posedge -> posedge):
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Info: type curr total name
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Info: clk-to-q 0.40 0.40 Source u_neuron_memory.u_neuron.group_index_TRELLIS_FF_Q_3.Q
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Info: routing 0.95 1.35 Net u_spi_engine.nm_start_LUT4_A_Z_LUT4_Z_D_CCU2C_A0_A1[1] (7,29) -> (12,29)
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Info: Sink u_neuron_memory.w_mem[24]_LUT4_C_Z_PFUMX_BLUT_Z_LUT4_Z.D
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Info: Defined in:
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Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
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Info: logic 0.18 1.53 Source u_neuron_memory.w_mem[24]_LUT4_C_Z_PFUMX_BLUT_Z_LUT4_Z.F
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Info: routing 1.49 3.02 Net u_neuron_memory.w_mem[24]_LUT4_C_Z_PFUMX_BLUT_Z[2] (12,29) -> (3,17)
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Info: Sink u_neuron_memory.u_neuron.u_mac8.w_bus_LUT4_Z_5_D_LUT4_Z_D_LUT4_Z_1.C
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Info: Defined in:
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Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
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Info: logic 0.18 3.20 Source u_neuron_memory.u_neuron.u_mac8.w_bus_LUT4_Z_5_D_LUT4_Z_D_LUT4_Z_1.F
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Info: routing 0.16 3.36 Net u_neuron_memory.u_neuron.u_mac8.w_bus_LUT4_Z_5_D_LUT4_Z_D[2] (3,17) -> (3,17)
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Info: Sink u_neuron_memory.u_neuron.u_mac8.w_bus_LUT4_Z_5_D_LUT4_Z.D
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Info: Defined in:
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Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
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Info: logic 0.18 3.54 Source u_neuron_memory.u_neuron.u_mac8.w_bus_LUT4_Z_5_D_LUT4_Z.F
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Info: routing 0.54 4.07 Net u_neuron_memory.u_neuron.u_mac8.w_bus_LUT4_Z_5_D[3] (3,17) -> (3,18)
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Info: Sink u_neuron_memory.u_neuron.u_mac8.w_bus_LUT4_Z_5.D
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Info: Defined in:
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Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
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Info: logic 0.18 4.25 Source u_neuron_memory.u_neuron.u_mac8.w_bus_LUT4_Z_5.F
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Info: routing 1.20 5.46 Net u_neuron_memory.u_neuron.w_group[12] (3,18) -> (5,22)
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Info: Sink u_neuron_memory.u_neuron.u_mac8.GEN_MAC[1].u_mac.product_MULT18X18D_P9.B4
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Info: Defined in:
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Info: /tmp/before_rewrite/neuron_parallel.v:93.43-93.50
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Info: logic 3.07 8.52 Source u_neuron_memory.u_neuron.u_mac8.GEN_MAC[1].u_mac.product_MULT18X18D_P9.P0
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Info: routing 1.17 9.70 Net u_neuron_memory.u_neuron.u_mac8.products[1][0] (5,22) -> (6,23)
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Info: Sink u_layer_sequencer.nm_activation_LUT4_A_Z_PFUMX_BLUT_Z_LUT4_C_Z_LUT4_Z_C_CCU2C_S0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S1_B1_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.A
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Info: Defined in:
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Info: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:73.9-73.13
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Info: logic 0.35 10.05 Source u_layer_sequencer.nm_activation_LUT4_A_Z_PFUMX_BLUT_Z_LUT4_C_Z_LUT4_Z_C_CCU2C_S0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S1_B1_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
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Info: routing 0.00 10.05 Net u_layer_sequencer.nm_activation_LUT4_A_Z_PFUMX_BLUT_Z_LUT4_C_Z_LUT4_Z_C_CCU2C_S0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S1_B1_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (6,23) -> (6,23)
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Info: Sink u_layer_sequencer.nm_activation_LUT4_A_Z_PFUMX_BLUT_Z_LUT4_C_Z_LUT4_Z_C_CCU2C_S0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S1_B1_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
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Info: logic 0.00 10.05 Source u_layer_sequencer.nm_activation_LUT4_A_Z_PFUMX_BLUT_Z_LUT4_C_Z_LUT4_Z_C_CCU2C_S0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S1_B1_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
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Info: routing 0.00 10.05 Net u_layer_sequencer.nm_activation_LUT4_A_Z_PFUMX_BLUT_Z_LUT4_C_Z_LUT4_Z_C_CCU2C_S0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S1_B1_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (6,23) -> (6,23)
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Info: Sink u_layer_sequencer.nm_activation_LUT4_A_Z_PFUMX_BLUT_Z_LUT4_C_Z_LUT4_Z_C_CCU2C_S0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S1_B1_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
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Info: Defined in:
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Info: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44
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Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
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Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
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Info: logic 0.06 10.11 Source u_layer_sequencer.nm_activation_LUT4_A_Z_PFUMX_BLUT_Z_LUT4_C_Z_LUT4_Z_C_CCU2C_S0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S1_B1_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
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Info: routing 0.00 10.11 Net u_layer_sequencer.nm_activation_LUT4_A_Z_PFUMX_BLUT_Z_LUT4_C_Z_LUT4_Z_C_CCU2C_S0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S1_B1_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (6,23) -> (6,23)
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Info: Sink u_layer_sequencer.nm_activation_LUT4_A_Z_PFUMX_BLUT_Z_LUT4_C_Z_LUT4_Z_C_CCU2C_S0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S1_B1_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
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Info: logic 0.00 10.11 Source u_layer_sequencer.nm_activation_LUT4_A_Z_PFUMX_BLUT_Z_LUT4_C_Z_LUT4_Z_C_CCU2C_S0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S1_B1_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
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Info: routing 0.00 10.11 Net u_layer_sequencer.nm_activation_LUT4_A_Z_PFUMX_BLUT_Z_LUT4_C_Z_LUT4_Z_C_CCU2C_S0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S1_B1_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (6,23) -> (6,23)
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Info: Sink u_layer_sequencer.nm_activation_LUT4_A_Z_PFUMX_BLUT_Z_LUT4_C_Z_LUT4_Z_C_CCU2C_S0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S1_B1_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
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Info: Defined in:
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Info: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44
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Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
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Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
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Info: logic 0.06 10.16 Source u_layer_sequencer.nm_activation_LUT4_A_Z_PFUMX_BLUT_Z_LUT4_C_Z_LUT4_Z_C_CCU2C_S0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S1_B1_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
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Info: routing 0.00 10.16 Net u_layer_sequencer.nm_activation_LUT4_A_Z_PFUMX_BLUT_Z_LUT4_C_Z_LUT4_Z_C_CCU2C_S0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S1_B1_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (6,23) -> (6,23)
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Info: Sink u_layer_sequencer.nm_activation_LUT4_A_Z_PFUMX_BLUT_Z_LUT4_C_Z_LUT4_Z_C_CCU2C_S0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S1_B1_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
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Info: logic 0.00 10.16 Source u_layer_sequencer.nm_activation_LUT4_A_Z_PFUMX_BLUT_Z_LUT4_C_Z_LUT4_Z_C_CCU2C_S0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S1_B1_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
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Info: routing 0.00 10.16 Net u_layer_sequencer.nm_activation_LUT4_A_Z_PFUMX_BLUT_Z_LUT4_C_Z_LUT4_Z_C_CCU2C_S0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S1_B1_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (6,23) -> (7,23)
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Info: Sink u_layer_sequencer.nm_activation_LUT4_A_Z_PFUMX_BLUT_Z_LUT4_C_Z_LUT4_Z_C_CCU2C_S0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S1_B1_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
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Info: Defined in:
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Info: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44
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Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
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Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
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Info: logic 0.06 10.22 Source u_layer_sequencer.nm_activation_LUT4_A_Z_PFUMX_BLUT_Z_LUT4_C_Z_LUT4_Z_C_CCU2C_S0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S1_B1_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
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Info: routing 0.00 10.22 Net u_layer_sequencer.nm_activation_LUT4_A_Z_PFUMX_BLUT_Z_LUT4_C_Z_LUT4_Z_C_CCU2C_S0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S1_B1_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (7,23) -> (7,23)
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Info: Sink u_layer_sequencer.nm_activation_LUT4_A_Z_PFUMX_BLUT_Z_LUT4_C_Z_LUT4_Z_C_CCU2C_S0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S1_B1_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
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Info: logic 0.29 10.51 Source u_layer_sequencer.nm_activation_LUT4_A_Z_PFUMX_BLUT_Z_LUT4_C_Z_LUT4_Z_C_CCU2C_S0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S1_B1_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.F
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Info: routing 1.03 11.55 Net u_layer_sequencer.nm_activation_LUT4_A_Z_PFUMX_BLUT_Z_LUT4_C_Z_LUT4_Z_C_CCU2C_S0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S1_B1_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1 (7,23) -> (7,26)
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Info: Sink u_layer_sequencer.nm_activation_LUT4_A_Z_PFUMX_BLUT_Z_LUT4_C_Z_LUT4_Z_C_CCU2C_S0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S1$CCU2_COMB1.B
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Info: logic 0.35 11.90 Source u_layer_sequencer.nm_activation_LUT4_A_Z_PFUMX_BLUT_Z_LUT4_C_Z_LUT4_Z_C_CCU2C_S0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S1$CCU2_COMB1.FCO
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Info: routing 0.00 11.90 Net u_layer_sequencer.nm_activation_LUT4_A_Z_PFUMX_BLUT_Z_LUT4_C_Z_LUT4_Z_C_CCU2C_S0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S1_COUT (7,26) -> (7,26)
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Info: Sink u_layer_sequencer.nm_activation_LUT4_A_Z_PFUMX_BLUT_Z_LUT4_C_Z_LUT4_Z_C_CCU2C_S0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S1$CCU2_COMB0.FCI
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Info: Defined in:
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Info: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:115.9-115.38
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Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
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Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
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Info: logic 0.06 11.96 Source u_layer_sequencer.nm_activation_LUT4_A_Z_PFUMX_BLUT_Z_LUT4_C_Z_LUT4_Z_C_CCU2C_S0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S1$CCU2_COMB0.FCO
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Info: routing 0.00 11.96 Net u_layer_sequencer.nm_activation_LUT4_A_Z_PFUMX_BLUT_Z_LUT4_C_Z_LUT4_Z_C_CCU2C_S0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S1$CCU2_FCI_INT (7,26) -> (7,26)
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Info: Sink u_layer_sequencer.nm_activation_LUT4_A_Z_PFUMX_BLUT_Z_LUT4_C_Z_LUT4_Z_C_CCU2C_S0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S1$CCU2_COMB1.FCI
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Info: logic 0.00 11.96 Source u_layer_sequencer.nm_activation_LUT4_A_Z_PFUMX_BLUT_Z_LUT4_C_Z_LUT4_Z_C_CCU2C_S0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S1$CCU2_COMB1.FCO
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Info: routing 0.00 11.96 Net u_layer_sequencer.nm_activation_LUT4_A_Z_PFUMX_BLUT_Z_LUT4_C_Z_LUT4_Z_C_CCU2C_S0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S1_COUT (7,26) -> (7,26)
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Info: Sink u_layer_sequencer.nm_activation_LUT4_A_Z_PFUMX_BLUT_Z_LUT4_C_Z_LUT4_Z_C_CCU2C_S0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S1$CCU2_COMB0.FCI
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Info: Defined in:
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Info: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:115.9-115.38
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Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
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Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
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Info: logic 0.33 12.28 Source u_layer_sequencer.nm_activation_LUT4_A_Z_PFUMX_BLUT_Z_LUT4_C_Z_LUT4_Z_C_CCU2C_S0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S1$CCU2_COMB0.F
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Info: routing 1.01 13.30 Net u_layer_sequencer.nm_activation_LUT4_A_Z_PFUMX_BLUT_Z_LUT4_C_Z_LUT4_Z_C_CCU2C_S0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S0[0] (7,26) -> (8,27)
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Info: Sink u_layer_sequencer.nm_activation_LUT4_A_Z_PFUMX_BLUT_Z_LUT4_C_Z_LUT4_Z_C_CCU2C_S0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.B
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Info: Defined in:
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Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
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Info: logic 0.35 13.65 Source u_layer_sequencer.nm_activation_LUT4_A_Z_PFUMX_BLUT_Z_LUT4_C_Z_LUT4_Z_C_CCU2C_S0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
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Info: routing 0.00 13.65 Net u_layer_sequencer.nm_activation_LUT4_A_Z_PFUMX_BLUT_Z_LUT4_C_Z_LUT4_Z_C_CCU2C_S0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (8,27) -> (8,27)
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Info: Sink u_layer_sequencer.nm_activation_LUT4_A_Z_PFUMX_BLUT_Z_LUT4_C_Z_LUT4_Z_C_CCU2C_S0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
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Info: logic 0.00 13.65 Source u_layer_sequencer.nm_activation_LUT4_A_Z_PFUMX_BLUT_Z_LUT4_C_Z_LUT4_Z_C_CCU2C_S0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
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Info: routing 0.00 13.65 Net u_layer_sequencer.nm_activation_LUT4_A_Z_PFUMX_BLUT_Z_LUT4_C_Z_LUT4_Z_C_CCU2C_S0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (8,27) -> (8,27)
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Info: Sink u_layer_sequencer.nm_activation_LUT4_A_Z_PFUMX_BLUT_Z_LUT4_C_Z_LUT4_Z_C_CCU2C_S0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
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Info: Defined in:
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Info: /tmp/before_rewrite/neuron_parallel.v:128.24-128.43
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Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
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Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
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Info: logic 0.33 13.98 Source u_layer_sequencer.nm_activation_LUT4_A_Z_PFUMX_BLUT_Z_LUT4_C_Z_LUT4_Z_C_CCU2C_S0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.F
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Info: routing 1.01 15.00 Net u_layer_sequencer.nm_activation_LUT4_A_Z_PFUMX_BLUT_Z_LUT4_C_Z_LUT4_Z_C_CCU2C_S0_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S0[2] (8,27) -> (10,28)
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Info: Sink u_layer_sequencer.nm_activation_LUT4_A_Z_PFUMX_BLUT_Z_LUT4_C_Z_LUT4_Z_1_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.A
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Info: Defined in:
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Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
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Info: logic 0.35 15.35 Source u_layer_sequencer.nm_activation_LUT4_A_Z_PFUMX_BLUT_Z_LUT4_C_Z_LUT4_Z_1_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
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Info: routing 0.00 15.35 Net u_layer_sequencer.nm_activation_LUT4_A_Z_PFUMX_BLUT_Z_LUT4_C_Z_LUT4_Z_1_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (10,28) -> (11,28)
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Info: Sink u_layer_sequencer.nm_activation_LUT4_A_Z_PFUMX_BLUT_Z_LUT4_C_Z_LUT4_Z_1_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
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Info: Defined in:
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Info: /tmp/before_rewrite/neuron_parallel.v:165.42-165.58
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Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
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Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
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Info: logic 0.06 15.41 Source u_layer_sequencer.nm_activation_LUT4_A_Z_PFUMX_BLUT_Z_LUT4_C_Z_LUT4_Z_1_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
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Info: routing 0.00 15.41 Net u_layer_sequencer.nm_activation_LUT4_A_Z_PFUMX_BLUT_Z_LUT4_C_Z_LUT4_Z_1_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (11,28) -> (11,28)
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Info: Sink u_layer_sequencer.nm_activation_LUT4_A_Z_PFUMX_BLUT_Z_LUT4_C_Z_LUT4_Z_1_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
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Info: logic 0.00 15.41 Source u_layer_sequencer.nm_activation_LUT4_A_Z_PFUMX_BLUT_Z_LUT4_C_Z_LUT4_Z_1_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
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Info: routing 0.00 15.41 Net u_layer_sequencer.nm_activation_LUT4_A_Z_PFUMX_BLUT_Z_LUT4_C_Z_LUT4_Z_1_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (11,28) -> (11,28)
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Info: Sink u_layer_sequencer.nm_activation_LUT4_A_Z_PFUMX_BLUT_Z_LUT4_C_Z_LUT4_Z_1_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
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Info: Defined in:
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Info: /tmp/before_rewrite/neuron_parallel.v:165.42-165.58
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Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
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Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
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Info: logic 0.06 15.46 Source u_layer_sequencer.nm_activation_LUT4_A_Z_PFUMX_BLUT_Z_LUT4_C_Z_LUT4_Z_1_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
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Info: routing 0.00 15.46 Net u_layer_sequencer.nm_activation_LUT4_A_Z_PFUMX_BLUT_Z_LUT4_C_Z_LUT4_Z_1_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (11,28) -> (11,28)
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Info: Sink u_layer_sequencer.nm_activation_LUT4_A_Z_PFUMX_BLUT_Z_LUT4_C_Z_LUT4_Z_1_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
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Info: logic 0.00 15.46 Source u_layer_sequencer.nm_activation_LUT4_A_Z_PFUMX_BLUT_Z_LUT4_C_Z_LUT4_Z_1_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
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Info: routing 0.00 15.46 Net u_layer_sequencer.nm_activation_LUT4_A_Z_PFUMX_BLUT_Z_LUT4_C_Z_LUT4_Z_1_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (11,28) -> (11,28)
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Info: Sink u_layer_sequencer.nm_activation_LUT4_A_Z_PFUMX_BLUT_Z_LUT4_C_Z_LUT4_Z_1_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
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Info: Defined in:
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Info: /tmp/before_rewrite/neuron_parallel.v:165.42-165.58
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Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
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Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
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Info: logic 0.06 15.52 Source u_layer_sequencer.nm_activation_LUT4_A_Z_PFUMX_BLUT_Z_LUT4_C_Z_LUT4_Z_1_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
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Info: routing 0.00 15.52 Net u_layer_sequencer.nm_activation_LUT4_A_Z_PFUMX_BLUT_Z_LUT4_C_Z_LUT4_Z_1_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (11,28) -> (11,28)
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Info: Sink u_layer_sequencer.nm_activation_LUT4_A_Z_PFUMX_BLUT_Z_LUT4_C_Z_LUT4_Z_1_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
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Info: logic 0.00 15.52 Source u_layer_sequencer.nm_activation_LUT4_A_Z_PFUMX_BLUT_Z_LUT4_C_Z_LUT4_Z_1_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
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Info: routing 0.00 15.52 Net u_layer_sequencer.nm_activation_LUT4_A_Z_PFUMX_BLUT_Z_LUT4_C_Z_LUT4_Z_1_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (11,28) -> (11,28)
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Info: Sink u_layer_sequencer.nm_activation_LUT4_A_Z_PFUMX_BLUT_Z_LUT4_C_Z_LUT4_Z_1_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
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Info: Defined in:
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Info: /tmp/before_rewrite/neuron_parallel.v:165.42-165.58
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Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
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Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
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Info: logic 0.06 15.57 Source u_layer_sequencer.nm_activation_LUT4_A_Z_PFUMX_BLUT_Z_LUT4_C_Z_LUT4_Z_1_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
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Info: routing 0.00 15.57 Net u_layer_sequencer.nm_activation_LUT4_A_Z_PFUMX_BLUT_Z_LUT4_C_Z_LUT4_Z_1_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (11,28) -> (11,28)
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Info: Sink u_layer_sequencer.nm_activation_LUT4_A_Z_PFUMX_BLUT_Z_LUT4_C_Z_LUT4_Z_1_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
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Info: logic 0.00 15.57 Source u_layer_sequencer.nm_activation_LUT4_A_Z_PFUMX_BLUT_Z_LUT4_C_Z_LUT4_Z_1_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
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Info: routing 0.00 15.57 Net u_layer_sequencer.nm_activation_LUT4_A_Z_PFUMX_BLUT_Z_LUT4_C_Z_LUT4_Z_1_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (11,28) -> (12,28)
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Info: Sink u_layer_sequencer.nm_activation_LUT4_A_Z_PFUMX_BLUT_Z_LUT4_C_Z_LUT4_Z_1_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
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Info: Defined in:
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Info: /tmp/before_rewrite/neuron_parallel.v:165.42-165.58
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Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
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Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
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Info: logic 0.06 15.63 Source u_layer_sequencer.nm_activation_LUT4_A_Z_PFUMX_BLUT_Z_LUT4_C_Z_LUT4_Z_1_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
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Info: routing 0.00 15.63 Net u_layer_sequencer.nm_activation_LUT4_A_Z_PFUMX_BLUT_Z_LUT4_C_Z_LUT4_Z_1_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (12,28) -> (12,28)
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Info: Sink u_layer_sequencer.nm_activation_LUT4_A_Z_PFUMX_BLUT_Z_LUT4_C_Z_LUT4_Z_1_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
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Info: logic 0.00 15.63 Source u_layer_sequencer.nm_activation_LUT4_A_Z_PFUMX_BLUT_Z_LUT4_C_Z_LUT4_Z_1_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
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Info: routing 0.00 15.63 Net u_layer_sequencer.nm_activation_LUT4_A_Z_PFUMX_BLUT_Z_LUT4_C_Z_LUT4_Z_1_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (12,28) -> (12,28)
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Info: Sink u_layer_sequencer.nm_activation_LUT4_A_Z_PFUMX_BLUT_Z_LUT4_C_Z_LUT4_Z_1_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
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Info: Defined in:
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Info: /tmp/before_rewrite/neuron_parallel.v:165.42-165.58
|
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Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
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Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
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Info: logic 0.06 15.69 Source u_layer_sequencer.nm_activation_LUT4_A_Z_PFUMX_BLUT_Z_LUT4_C_Z_LUT4_Z_1_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
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Info: routing 0.00 15.69 Net u_layer_sequencer.nm_activation_LUT4_A_Z_PFUMX_BLUT_Z_LUT4_C_Z_LUT4_Z_1_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (12,28) -> (12,28)
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Info: Sink u_layer_sequencer.nm_activation_LUT4_A_Z_PFUMX_BLUT_Z_LUT4_C_Z_LUT4_Z_1_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
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Info: logic 0.00 15.69 Source u_layer_sequencer.nm_activation_LUT4_A_Z_PFUMX_BLUT_Z_LUT4_C_Z_LUT4_Z_1_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
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Info: routing 0.00 15.69 Net u_layer_sequencer.nm_activation_LUT4_A_Z_PFUMX_BLUT_Z_LUT4_C_Z_LUT4_Z_1_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (12,28) -> (12,28)
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Info: Sink u_layer_sequencer.nm_activation_LUT4_A_Z_PFUMX_BLUT_Z_LUT4_C_Z_LUT4_Z_1_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
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Info: Defined in:
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Info: /tmp/before_rewrite/neuron_parallel.v:165.42-165.58
|
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Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
|
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Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
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Info: logic 0.06 15.74 Source u_layer_sequencer.nm_activation_LUT4_A_Z_PFUMX_BLUT_Z_LUT4_C_Z_LUT4_Z_1_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
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Info: routing 0.00 15.74 Net u_layer_sequencer.nm_activation_LUT4_A_Z_PFUMX_BLUT_Z_LUT4_C_Z_LUT4_Z_1_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (12,28) -> (12,28)
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Info: Sink u_layer_sequencer.nm_activation_LUT4_A_Z_PFUMX_BLUT_Z_LUT4_C_Z_LUT4_Z_1_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
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Info: logic 0.00 15.74 Source u_layer_sequencer.nm_activation_LUT4_A_Z_PFUMX_BLUT_Z_LUT4_C_Z_LUT4_Z_1_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
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Info: routing 0.00 15.74 Net u_layer_sequencer.nm_activation_LUT4_A_Z_PFUMX_BLUT_Z_LUT4_C_Z_LUT4_Z_1_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN (12,28) -> (12,28)
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Info: Sink u_layer_sequencer.nm_activation_LUT4_A_Z_PFUMX_BLUT_Z_LUT4_C_Z_LUT4_Z_1_D_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
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Info: Defined in:
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Info: /tmp/before_rewrite/neuron_parallel.v:165.42-165.58
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Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
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Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
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Info: logic 0.06 15.80 Source u_layer_sequencer.nm_activation_LUT4_A_Z_PFUMX_BLUT_Z_LUT4_C_Z_LUT4_Z_1_D_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
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Info: routing 0.00 15.80 Net u_layer_sequencer.nm_activation_LUT4_A_Z_PFUMX_BLUT_Z_LUT4_C_Z_LUT4_Z_1_D_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (12,28) -> (12,28)
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Info: Sink u_layer_sequencer.nm_activation_LUT4_A_Z_PFUMX_BLUT_Z_LUT4_C_Z_LUT4_Z_1_D_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
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Info: logic 0.00 15.80 Source u_layer_sequencer.nm_activation_LUT4_A_Z_PFUMX_BLUT_Z_LUT4_C_Z_LUT4_Z_1_D_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
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Info: routing 0.00 15.80 Net u_layer_sequencer.nm_activation_LUT4_A_Z_PFUMX_BLUT_Z_LUT4_C_Z_LUT4_Z_1_D_CCU2C_COUT_CIN (12,28) -> (13,28)
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Info: Sink u_layer_sequencer.nm_activation_LUT4_A_Z_PFUMX_BLUT_Z_LUT4_C_Z_LUT4_Z_1_D_CCU2C_COUT$CCU2_COMB0.FCI
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Info: Defined in:
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Info: /tmp/before_rewrite/neuron_parallel.v:165.42-165.58
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Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
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Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
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Info: logic 0.06 15.85 Source u_layer_sequencer.nm_activation_LUT4_A_Z_PFUMX_BLUT_Z_LUT4_C_Z_LUT4_Z_1_D_CCU2C_COUT$CCU2_COMB0.FCO
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Info: routing 0.00 15.85 Net u_layer_sequencer.nm_activation_LUT4_A_Z_PFUMX_BLUT_Z_LUT4_C_Z_LUT4_Z_1_D_CCU2C_COUT$CCU2_FCI_INT (13,28) -> (13,28)
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Info: Sink u_layer_sequencer.nm_activation_LUT4_A_Z_PFUMX_BLUT_Z_LUT4_C_Z_LUT4_Z_1_D_CCU2C_COUT$CCU2_COMB1.FCI
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Info: logic 0.00 15.85 Source u_layer_sequencer.nm_activation_LUT4_A_Z_PFUMX_BLUT_Z_LUT4_C_Z_LUT4_Z_1_D_CCU2C_COUT$CCU2_COMB1.FCO
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Info: routing 0.00 15.85 Net $nextpnr_CCU2C_11$CIN (13,28) -> (13,28)
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Info: Sink $nextpnr_CCU2C_11$CCU2_COMB0.FCI
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Info: logic 0.33 16.18 Source $nextpnr_CCU2C_11$CCU2_COMB0.F
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Info: routing 0.75 16.94 Net u_layer_sequencer.nm_activation_LUT4_A_Z_PFUMX_BLUT_Z_LUT4_C_Z_LUT4_Z_1_D (13,28) -> (15,27)
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Info: Sink u_layer_sequencer.nm_activation_LUT4_A_Z_PFUMX_BLUT_Z_LUT4_C_Z_LUT4_Z_1.D
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Info: Defined in:
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Info: /tmp/before_rewrite/neuron_parallel.v:165.42-165.58
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Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
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Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
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Info: logic 0.18 17.12 Source u_layer_sequencer.nm_activation_LUT4_A_Z_PFUMX_BLUT_Z_LUT4_C_Z_LUT4_Z_1.F
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Info: routing 0.57 17.69 Net u_layer_sequencer.nm_activation_LUT4_A_Z_PFUMX_BLUT_Z_LUT4_C_Z[2] (15,27) -> (15,26)
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Info: Sink u_layer_sequencer.nm_activation_LUT4_A_Z_PFUMX_BLUT_Z_LUT4_C_1_Z_LUT4_Z_6.C
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Info: Defined in:
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Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
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Info: logic 0.18 17.87 Source u_layer_sequencer.nm_activation_LUT4_A_Z_PFUMX_BLUT_Z_LUT4_C_1_Z_LUT4_Z_6.F
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Info: routing 0.12 17.99 Net u_layer_sequencer.nm_activation_LUT4_A_Z_PFUMX_BLUT_Z_LUT4_C_1_Z[0] (15,26) -> (15,26)
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Info: Sink u_neuron_memory.u_neuron.y_TRELLIS_FF_Q_7.DI
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Info: setup 0.00 17.99 Source u_neuron_memory.u_neuron.y_TRELLIS_FF_Q_7.DI
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Info: 7.97 ns logic, 10.02 ns routing
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Info: Critical path report for cross-domain path '<async>' -> 'posedge $glbnet$clk$TRELLIS_IO_IN':
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Info: type curr total name
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Info: source 0.00 0.00 Source rst$tr_io.O
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Info: routing 2.75 2.75 Net rst$TRELLIS_IO_IN (29,0) -> (36,31)
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Info: Sink graph_rst_LUT4_Z.C
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Info: Defined in:
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Info: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_slave.v:23.16-23.19
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Info: logic 0.18 2.93 Source graph_rst_LUT4_Z.F
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Info: routing 1.95 4.88 Net graph_rst (36,31) -> (8,24)
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Info: Sink u_neuron_memory.access_req_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_D_Z_LUT4_Z.D
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Info: Defined in:
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Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
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Info: logic 0.18 5.06 Source u_neuron_memory.access_req_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_D_Z_LUT4_Z.F
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Info: routing 1.03 6.09 Net u_neuron_memory.access_req_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_D_Z[0] (8,24) -> (13,26)
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Info: Sink u_neuron_memory.w_mem[2]_TRELLIS_FF_Q_CE_LUT4_Z.D
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Info: Defined in:
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Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
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Info: logic 0.18 6.27 Source u_neuron_memory.w_mem[2]_TRELLIS_FF_Q_CE_LUT4_Z.F
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Info: routing 1.33 7.61 Net u_neuron_memory.w_mem[2]_TRELLIS_FF_Q_CE (13,26) -> (13,29)
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Info: Sink u_neuron_memory.w_mem[2]_TRELLIS_FF_Q_3.CE
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Info: setup 0.00 7.61 Source u_neuron_memory.w_mem[2]_TRELLIS_FF_Q_3.CE
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Info: 0.54 ns logic, 7.07 ns routing
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Info: Critical path report for cross-domain path 'posedge $glbnet$clk$TRELLIS_IO_IN' -> '<async>':
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Info: type curr total name
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Info: clk-to-q 0.40 0.40 Source u_psram_ctrl.dq_oe_TRELLIS_FF_Q.Q
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Info: routing 4.34 4.73 Net u_psram_ctrl.dq_oe (2,35) -> (88,20)
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Info: Sink psram_dq[1]$tr_io$invert_T.A
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Info: Defined in:
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Info: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/psram_controller.v:90.27-90.32
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Info: logic 0.18 4.91 Source psram_dq[1]$tr_io$invert_T.F
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Info: routing 0.69 5.60 Net psram_dq[1]$tr_io$invert_T$conn$Z (88,20) -> (90,20)
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Info: Sink psram_dq[1]$tr_io.T
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Info: 0.57 ns logic, 5.02 ns routing
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ERROR: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 55.59 MHz (FAIL at 80.00 MHz)
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Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 7.61 ns
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Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 5.60 ns
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Info: Slack histogram:
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Info: legend: * represents 20 endpoint(s)
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Info: + represents [1,20) endpoint(s)
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Info: [ -5490, -4625) |+
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Info: [ -4625, -3760) |
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Info: [ -3760, -2895) |+
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Info: [ -2895, -2030) |**+
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Info: [ -2030, -1165) |+
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Info: [ -1165, -300) |+
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Info: [ -300, 565) |
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Info: [ 565, 1430) |
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Info: [ 1430, 2295) |
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Info: [ 2295, 3160) |
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Info: [ 3160, 4025) |
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Info: [ 4025, 4890) |***+
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Info: [ 4890, 5755) |***********+
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Info: [ 5755, 6620) |*********+
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Info: [ 6620, 7485) |****************************+
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Info: [ 7485, 8350) |**************************************+
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Info: [ 8350, 9215) |***********************************+
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Info: [ 9215, 10080) |****************************************
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Info: [ 10080, 10945) |************************************************************
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Info: [ 10945, 11810) |***********************************************+
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0 warnings, 1 error
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Info: Program finished normally.
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