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55c827bedf7cc3b7203e895512c650d089fe9255
FPGA-Neural/synth/ecp5/spi_neuron_top.lpf
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micheleandClaude Sonnet 5 55c827bedf feat: PSRAM page-mode reads + graph engine (Type #2) + real pinout/IRQ pins 
PSRAM page-mode read burst support in psram_controller.v: enables the
ISSI IS66WVE4M16EBLL-70BLI's page mode via its configuration-register
software-access sequence at boot (disabled by default on the real
chip), then keeps CE#/OE# asserted after a read so a same-page
continuation only pays tAPA (20ns) instead of a full tAA (70ns)
random access, with automatic tCEM-safe session closing. Only a WRITE
closes the page -- byte-enable changes do not, since
int8_memory_access.v alternates them on nearly every access and an
early implementation attempt that treated them as a close condition
measured a real regression (53.25->61.25 cycles/edge) before being
corrected (53.25->37.53 cycles/edge, +42% gather bandwidth).
sim/psram_model.v gained independent tAPA/tAA and tCEM enforcement
(with a real Verilog same-timestep event-ordering race found and
fixed via a #0 sync) so the regression proves real timing compliance,
not just data correctness. New sim/psram_page_mode_tb.v; full 26-file
regression suite re-run clean. Real nextpnr-ecp5 Fmax re-measured on
the full spi_neuron_top system: 75.73MHz (P2, up from 55.59MHz) and
65.13MHz (P8) -- still under the 80MHz target but not regressed, with
the critical path confirmed (not assumed) to remain entirely inside
neuron_parallel's accumulate chain, never psram_controller.

Also includes this session's other already-validated work: the graph
engine (Type #2 sparse-graph network: act_buffer, graph_engine,
netasm host assembler), real CABGA381 pinout (.lpf, place&route
verified) and physical IRQ_N/DATA_READY_N pins, and Phase 7 timing
closure logs -- all previously uncommitted, documented in WORKLOG.md.

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01LH3jPeJ3eFMfF2v8SQhpkk
2026-09-03 17:12:05 +02:00

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BLOCK ASYNCPATHS;
BLOCK RESETPATHS;
LOCATE COMP "clk" SITE "H5";
IOBUF PORT "clk" IO_TYPE=LVCMOS33;
LOCATE COMP "cs_n" SITE "B3";
IOBUF PORT "cs_n" IO_TYPE=LVCMOS33;
LOCATE COMP "data_ready_n" SITE "C3";
IOBUF PORT "data_ready_n" IO_TYPE=LVCMOS33;
LOCATE COMP "irq_n" SITE "C4";
IOBUF PORT "irq_n" IO_TYPE=LVCMOS33;
LOCATE COMP "miso" SITE "A3";
IOBUF PORT "miso" IO_TYPE=LVCMOS33;
LOCATE COMP "mosi" SITE "C5";
IOBUF PORT "mosi" IO_TYPE=LVCMOS33;
LOCATE COMP "psram_a[0]" SITE "E16";
IOBUF PORT "psram_a[0]" IO_TYPE=LVCMOS33;
LOCATE COMP "psram_a[10]" SITE "H17";
IOBUF PORT "psram_a[10]" IO_TYPE=LVCMOS33;
LOCATE COMP "psram_a[11]" SITE "H18";
IOBUF PORT "psram_a[11]" IO_TYPE=LVCMOS33;
LOCATE COMP "psram_a[12]" SITE "J16";
IOBUF PORT "psram_a[12]" IO_TYPE=LVCMOS33;
LOCATE COMP "psram_a[13]" SITE "J17";
IOBUF PORT "psram_a[13]" IO_TYPE=LVCMOS33;
LOCATE COMP "psram_a[14]" SITE "C20";
IOBUF PORT "psram_a[14]" IO_TYPE=LVCMOS33;
LOCATE COMP "psram_a[15]" SITE "D19";
IOBUF PORT "psram_a[15]" IO_TYPE=LVCMOS33;
LOCATE COMP "psram_a[16]" SITE "E19";
IOBUF PORT "psram_a[16]" IO_TYPE=LVCMOS33;
LOCATE COMP "psram_a[17]" SITE "E20";
IOBUF PORT "psram_a[17]" IO_TYPE=LVCMOS33;
LOCATE COMP "psram_a[18]" SITE "F19";
IOBUF PORT "psram_a[18]" IO_TYPE=LVCMOS33;
LOCATE COMP "psram_a[19]" SITE "F20";
IOBUF PORT "psram_a[19]" IO_TYPE=LVCMOS33;
LOCATE COMP "psram_a[1]" SITE "F16";
IOBUF PORT "psram_a[1]" IO_TYPE=LVCMOS33;
LOCATE COMP "psram_a[20]" SITE "G20";
IOBUF PORT "psram_a[20]" IO_TYPE=LVCMOS33;
LOCATE COMP "psram_a[21]" SITE "H20";
IOBUF PORT "psram_a[21]" IO_TYPE=LVCMOS33;
LOCATE COMP "psram_a[22]" SITE "P18";
IOBUF PORT "psram_a[22]" IO_TYPE=LVCMOS33;
LOCATE COMP "psram_a[2]" SITE "D18";
IOBUF PORT "psram_a[2]" IO_TYPE=LVCMOS33;
LOCATE COMP "psram_a[3]" SITE "E17";
IOBUF PORT "psram_a[3]" IO_TYPE=LVCMOS33;
LOCATE COMP "psram_a[4]" SITE "E18";
IOBUF PORT "psram_a[4]" IO_TYPE=LVCMOS33;
LOCATE COMP "psram_a[5]" SITE "F18";
IOBUF PORT "psram_a[5]" IO_TYPE=LVCMOS33;
LOCATE COMP "psram_a[6]" SITE "F17";
IOBUF PORT "psram_a[6]" IO_TYPE=LVCMOS33;
LOCATE COMP "psram_a[7]" SITE "G16";
IOBUF PORT "psram_a[7]" IO_TYPE=LVCMOS33;
LOCATE COMP "psram_a[8]" SITE "G18";
IOBUF PORT "psram_a[8]" IO_TYPE=LVCMOS33;
LOCATE COMP "psram_a[9]" SITE "H16";
IOBUF PORT "psram_a[9]" IO_TYPE=LVCMOS33;
LOCATE COMP "psram_ce_n" SITE "N17";
IOBUF PORT "psram_ce_n" IO_TYPE=LVCMOS33;
LOCATE COMP "psram_dq[0]" SITE "K18";
IOBUF PORT "psram_dq[0]" IO_TYPE=LVCMOS33;
LOCATE COMP "psram_dq[10]" SITE "L17";
IOBUF PORT "psram_dq[10]" IO_TYPE=LVCMOS33;
LOCATE COMP "psram_dq[11]" SITE "M18";
IOBUF PORT "psram_dq[11]" IO_TYPE=LVCMOS33;
LOCATE COMP "psram_dq[12]" SITE "M17";
IOBUF PORT "psram_dq[12]" IO_TYPE=LVCMOS33;
LOCATE COMP "psram_dq[13]" SITE "N16";
IOBUF PORT "psram_dq[13]" IO_TYPE=LVCMOS33;
LOCATE COMP "psram_dq[14]" SITE "N18";
IOBUF PORT "psram_dq[14]" IO_TYPE=LVCMOS33;
LOCATE COMP "psram_dq[15]" SITE "P17";
IOBUF PORT "psram_dq[15]" IO_TYPE=LVCMOS33;
LOCATE COMP "psram_dq[1]" SITE "C18";
IOBUF PORT "psram_dq[1]" IO_TYPE=LVCMOS33;
LOCATE COMP "psram_dq[2]" SITE "D17";
IOBUF PORT "psram_dq[2]" IO_TYPE=LVCMOS33;
LOCATE COMP "psram_dq[3]" SITE "D20";
IOBUF PORT "psram_dq[3]" IO_TYPE=LVCMOS33;
LOCATE COMP "psram_dq[4]" SITE "G19";
IOBUF PORT "psram_dq[4]" IO_TYPE=LVCMOS33;
LOCATE COMP "psram_dq[5]" SITE "J18";
IOBUF PORT "psram_dq[5]" IO_TYPE=LVCMOS33;
LOCATE COMP "psram_dq[6]" SITE "J19";
IOBUF PORT "psram_dq[6]" IO_TYPE=LVCMOS33;
LOCATE COMP "psram_dq[7]" SITE "J20";
IOBUF PORT "psram_dq[7]" IO_TYPE=LVCMOS33;
LOCATE COMP "psram_dq[8]" SITE "K19";
IOBUF PORT "psram_dq[8]" IO_TYPE=LVCMOS33;
LOCATE COMP "psram_dq[9]" SITE "K20";
IOBUF PORT "psram_dq[9]" IO_TYPE=LVCMOS33;
LOCATE COMP "psram_lb_n" SITE "T16";
IOBUF PORT "psram_lb_n" IO_TYPE=LVCMOS33;
LOCATE COMP "psram_oe_n" SITE "R16";
IOBUF PORT "psram_oe_n" IO_TYPE=LVCMOS33;
LOCATE COMP "psram_ub_n" SITE "N19";
IOBUF PORT "psram_ub_n" IO_TYPE=LVCMOS33;
LOCATE COMP "psram_we_n" SITE "R17";
IOBUF PORT "psram_we_n" IO_TYPE=LVCMOS33;
LOCATE COMP "psram_zz_n" SITE "N20";
IOBUF PORT "psram_zz_n" IO_TYPE=LVCMOS33;
LOCATE COMP "rst" SITE "B4";
IOBUF PORT "rst" IO_TYPE=LVCMOS33;
LOCATE COMP "sclk" SITE "B5";
IOBUF PORT "sclk" IO_TYPE=LVCMOS33;
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