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FPGA-Neural/sim/memory_interface.vcd
T
micheleandClaude Sonnet 5 55c827bedf feat: PSRAM page-mode reads + graph engine (Type #2) + real pinout/IRQ pins 
PSRAM page-mode read burst support in psram_controller.v: enables the
ISSI IS66WVE4M16EBLL-70BLI's page mode via its configuration-register
software-access sequence at boot (disabled by default on the real
chip), then keeps CE#/OE# asserted after a read so a same-page
continuation only pays tAPA (20ns) instead of a full tAA (70ns)
random access, with automatic tCEM-safe session closing. Only a WRITE
closes the page -- byte-enable changes do not, since
int8_memory_access.v alternates them on nearly every access and an
early implementation attempt that treated them as a close condition
measured a real regression (53.25->61.25 cycles/edge) before being
corrected (53.25->37.53 cycles/edge, +42% gather bandwidth).
sim/psram_model.v gained independent tAPA/tAA and tCEM enforcement
(with a real Verilog same-timestep event-ordering race found and
fixed via a #0 sync) so the regression proves real timing compliance,
not just data correctness. New sim/psram_page_mode_tb.v; full 26-file
regression suite re-run clean. Real nextpnr-ecp5 Fmax re-measured on
the full spi_neuron_top system: 75.73MHz (P2, up from 55.59MHz) and
65.13MHz (P8) -- still under the 80MHz target but not regressed, with
the critical path confirmed (not assumed) to remain entirely inside
neuron_parallel's accumulate chain, never psram_controller.

Also includes this session's other already-validated work: the graph
engine (Type #2 sparse-graph network: act_buffer, graph_engine,
netasm host assembler), real CABGA381 pinout (.lpf, place&route
verified) and physical IRQ_N/DATA_READY_N pins, and Phase 7 timing
closure logs -- all previously uncommitted, documented in WORKLOG.md.

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01LH3jPeJ3eFMfF2v8SQhpkk
2026-09-03 17:12:05 +02:00

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$date
Thu Sep 3 17:04:40 2026
$end
$version
Icarus Verilog
$end
$timescale
1ps
$end
$scope module memory_interface_tb $end
$var wire 1 ! ready $end
$var wire 16 " rdata [15:0] $end
$var wire 1 # mem_wr $end
$var wire 16 $ mem_wdata [15:0] $end
$var wire 1 % mem_req $end
$var wire 1 & mem_ready $end
$var wire 16 ' mem_rdata [15:0] $end
$var wire 23 ( mem_addr [22:0] $end
$var parameter 32 ) ADDR_WIDTH $end
$var parameter 32 * DATA_WIDTH $end
$var reg 23 + addr [22:0] $end
$var reg 1 , clk $end
$var reg 1 - req $end
$var reg 1 . rst $end
$var reg 16 / wdata [15:0] $end
$var reg 1 0 wr $end
$scope module dut $end
$var wire 23 1 addr [22:0] $end
$var wire 1 , clk $end
$var wire 1 2 lb_n $end
$var wire 1 - req $end
$var wire 1 . rst $end
$var wire 1 3 ub_n $end
$var wire 16 4 wdata [15:0] $end
$var wire 1 0 wr $end
$var wire 1 & mem_ready $end
$var wire 16 5 mem_rdata [15:0] $end
$var parameter 32 6 ADDR_WIDTH $end
$var parameter 32 7 DATA_WIDTH $end
$var parameter 2 8 STATE_IDLE $end
$var parameter 2 9 STATE_WAIT $end
$var reg 23 : mem_addr [22:0] $end
$var reg 1 ; mem_lb_n $end
$var reg 1 % mem_req $end
$var reg 1 < mem_ub_n $end
$var reg 16 = mem_wdata [15:0] $end
$var reg 1 # mem_wr $end
$var reg 16 > rdata [15:0] $end
$var reg 1 ! ready $end
$var reg 2 ? state [1:0] $end
$upscope $end
$scope module memory $end
$var wire 23 @ addr [22:0] $end
$var wire 1 , clk $end
$var wire 1 % req $end
$var wire 1 . rst $end
$var wire 16 A wdata [15:0] $end
$var wire 1 # wr $end
$var parameter 32 B ADDR_WIDTH $end
$var parameter 32 C DATA_WIDTH $end
$var parameter 32 D DEPTH $end
$var parameter 32 E READ_LATENCY $end
$var reg 1 F busy $end
$var reg 23 G pending_addr [22:0] $end
$var reg 16 H pending_wdata [15:0] $end
$var reg 1 I pending_wr $end
$var reg 16 J rdata [15:0] $end
$var reg 1 & ready $end
$var integer 32 K delay_count [31:0] $end
$var integer 32 L i [31:0] $end
$upscope $end
$scope task read_mem $end
$var reg 23 M address [22:0] $end
$var reg 16 N expected [15:0] $end
$var reg 16 O received [15:0] $end
$upscope $end
$scope task write_mem $end
$var reg 23 P address [22:0] $end
$var reg 16 Q data [15:0] $end
$upscope $end
$upscope $end
$enddefinitions $end
$comment Show the parameter values. $end
$dumpall
b10 E
b1000000000000 D
b10000 C
b10111 B
b1 9
b0 8
b10000 7
b10111 6
b10000 *
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$end
#0
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