micheleandClaude Sonnet 5
932aec2490
Adds packed_pe.v (packed_slot.v's compute+activation-fetch+writeback subsystem, reusing ddr_prefetch_mgr.v/neural_processor_packed.v/ result_writeback.v completely unmodified, with its own private weight-fetch removed) and systolic_group.v (one real layer_prefetch_ ctrl.v+layer_weight_buffer.v+weight_tile_gather.v shared by 4x packed_pe.v via a real, barrier-synchronized broadcast bus). Real design choice confirmed with the user before writing any RTL (AskUserQuestion, concrete topology preview): shared-weight broadcast, not a literal PE-to-PE systolic shift register -- achieves the real, quantified rationale (4x reduction in redundant weight-fetch DDR3 traffic per group of 4 PEs) with much lower real risk than genuine inter-PE pipeline fill/drain. The real new design is the barrier: each PE's own tcnt is the join key against the group's broadcast tcnt, self-synchronizing regardless of which PE is momentarily ahead/behind (e.g. a real DDR3 row-switch stall on one PE's own activation fetch). Found and fixed a real bug during verification (not by inspection): the first full test run reported every result as undefined despite every control-flow signal tracing correctly -- root-caused via real signal tracing down to a 5-way test arbiter bus mis-sliced at the wrong slot offset (single-bit handshake buses happened to use a correct range and masked it from the control-flow trace; only the wide, byte-offset buses were wrong). Verified in isolation (tb_systolic_group.v, real Icarus xsim, real sdram_arbiter_n.v generalized to NUM_REQ=5 with zero changes): 8/8 PASS across 2 consecutive group jobs (exercising the barrier's own per-job reset path, not just cold start). Deliberately scoped to the isolated mechanism only, per this project's "one variable at a time" discipline -- Director/SPI job dispatch for group jobs, a real N=16 top-level, and real P&R are real, disclosed next steps, not done here. Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01MUG92aM9m68TRc4rG55BcC
324 lines
15 KiB
Verilog
324 lines
15 KiB
Verilog
`timescale 1ns/1ps
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// ============================================================
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// V3 -- systolic_group.v: real group controller for the "4 groups x
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// 4-PE weight-stationary chains" hybrid scaling direction
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// (docs/ARCHITECTURE_ANALYSIS.md S5.6, EXP-0089). User-confirmed real
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// design choice (2026-09-20, explicit A/B decision): SHARED-WEIGHT
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// BROADCAST, not a literal PE-to-PE systolic shift register -- one
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// real weight fetch per group of 4 PEs (instead of 4 independent
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// fetches), each PE then computes its own, independent activation
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// positions in parallel. This achieves the doc's own real, quantified
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// rationale (reduce redundant weight-fetch DDR3 traffic 4x per group)
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// with far less real risk/complexity than a literal systolic pipeline
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// -- no inter-PE result propagation, no pipeline fill/drain at chain
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// boundaries, both of which the doc's own S5.6 explicitly flagged as
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// "a real, new design, not a trivial extension".
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//
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// STRUCTURE: ONE real layer_prefetch_ctrl.v + layer_weight_buffer.v +
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// weight_tile_gather.v (unmodified, identical instances to what
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// packed_slot.v already owns per-slot -- just now group-level, shared
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// by reference not duplicated), driving 4x packed_pe.v (packed_slot.v
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// minus its own weight-fetch, see packed_pe.v's own header) via a
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// real, level-held, tcnt-tagged broadcast bus.
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//
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// REAL BARRIER SYNCHRONIZATION (the actual new design, not asserted
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// correct without real verification -- see tb_systolic_group.v): the
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// group only advances to tile N+1's weight fetch once ALL 4 PEs have
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// ack'd tile N (`pe_tile_ack[i]`, individually latched since PEs may
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// consume at different real cycles -- e.g. one PE's own activation
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// fetch hit a real DDR3 row switch the others didn't). This is a real,
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// necessary extension of the "S_TILEWAIT join" discipline every other
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// module in this project already uses for 2-source joins (weight +
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// activation) -- here it's a 4-way join (one group weight source, 4
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// independent PE acks), same underlying principle: never advance past
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// a shared resource until every real consumer has confirmed it read
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// what it needed.
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// ============================================================
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module systolic_group #(
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parameter DATA_WIDTH = 8,
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parameter P_IN = 8,
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parameter ACC_WIDTH = 32,
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parameter BURST_LEN = 8,
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parameter ADDR_WIDTH = 26,
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parameter LAYER_BYTES = 128,
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parameter BUFADDRW = $clog2(LAYER_BYTES)
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)(
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input wire clk,
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input wire rst,
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// ---- group-level job dispatch: ONE shared w_base/n_tiles (all 4
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// PEs process the SAME layer, weight-stationary), 4x independent
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// per-PE x_base_a/b/result_addr_a/b/node_id_a/b ----
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input wire job_start,
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input wire [ADDR_WIDTH-1:0] w_base,
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input wire [15:0] n_tiles,
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input wire [4*ADDR_WIDTH-1:0] pe_x_base_a, pe_x_base_b,
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input wire [4*ADDR_WIDTH-1:0] pe_result_addr_a, pe_result_addr_b,
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input wire [4*16-1:0] pe_node_id_a, pe_node_id_b,
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output reg job_done, // one-cycle pulse, ALL 4 PEs done
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output wire [4*DATA_WIDTH-1:0] pe_result_data_a, pe_result_data_b,
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output wire [4*16-1:0] pe_result_node_id_a, pe_result_node_id_b,
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output wire [4*ADDR_WIDTH-1:0] pe_result_addr_a_out, pe_result_addr_b_out,
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// ---- group's own single arbiter port, for the shared weight
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// fetch only -- each of the 4 PEs still owns ITS OWN separate
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// arbiter port for activation-fetch+writeback (see top-level
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// integration; not this module's own concern) ----
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output wire mem_active,
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input wire mem_grant,
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output wire ctrl_req,
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output wire ctrl_wr,
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output wire [ADDR_WIDTH-2:0] ctrl_addr,
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output wire [32*BURST_LEN-1:0] ctrl_wdata,
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output wire [4*BURST_LEN-1:0] ctrl_wmask,
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input wire [32*BURST_LEN-1:0] ctrl_rdata,
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input wire ctrl_ready,
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input wire ctrl_busy,
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// ---- 4 independent per-PE arbiter ports (activation-fetch +
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// result-writeback, NOT shared -- flattened NUM_PE*width buses) ----
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output wire [3:0] pe_mem_active,
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input wire [3:0] pe_mem_grant,
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output wire [3:0] pe_ctrl_req,
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output wire [3:0] pe_ctrl_wr,
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output wire [4*(ADDR_WIDTH-1)-1:0] pe_ctrl_addr,
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output wire [4*32*BURST_LEN-1:0] pe_ctrl_wdata,
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output wire [4*4*BURST_LEN-1:0] pe_ctrl_wmask,
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input wire [4*32*BURST_LEN-1:0] pe_ctrl_rdata,
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input wire [3:0] pe_ctrl_ready,
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input wire [3:0] pe_ctrl_busy
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);
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localparam S_IDLE = 4'd0,
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S_MEMWAIT = 4'd1,
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S_PREFETCH = 4'd2,
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S_SWAP = 4'd3,
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S_PEJOBSTART = 4'd4,
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S_TILELOOP = 4'd5,
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S_WAITDONE = 4'd6;
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reg [3:0] state;
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reg [ADDR_WIDTH-1:0] w_base_lat;
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reg [15:0] n_tiles_lat;
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reg [15:0] tcnt;
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// ---- shared weight fetch: layer_prefetch_ctrl.v -> layer_weight_
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// buffer.v -> weight_tile_gather.v, IDENTICAL instances to what
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// packed_slot.v already owns per-slot, just group-level now ----
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reg pf_start;
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wire pf_busy, pf_done;
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wire pf_fill_we;
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wire [BUFADDRW-1:0] pf_fill_addr;
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wire [DATA_WIDTH-1:0] pf_fill_data;
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reg consume_done;
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layer_prefetch_ctrl #(
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.DATA_WIDTH(DATA_WIDTH), .LAYER_BYTES(LAYER_BYTES), .BURST_LEN(BURST_LEN), .ADDR_WIDTH(ADDR_WIDTH-1)
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) u_pf (
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.clk(clk), .rst(rst),
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.start(pf_start), .layer_base(w_base_lat[ADDR_WIDTH-2:0]), .busy(pf_busy), .done(pf_done),
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.fill_we(pf_fill_we), .fill_addr(pf_fill_addr), .fill_data(pf_fill_data),
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.ctrl_req(ctrl_req), .ctrl_wr(ctrl_wr), .ctrl_addr(ctrl_addr),
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.ctrl_wdata(ctrl_wdata), .ctrl_wmask(ctrl_wmask),
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.ctrl_rdata(ctrl_rdata), .ctrl_ready(ctrl_ready), .ctrl_busy(ctrl_busy)
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);
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assign mem_active = (state == S_MEMWAIT) || (state == S_PREFETCH);
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wire [BUFADDRW-1:0] lwb_rd_addr;
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wire [DATA_WIDTH-1:0] lwb_rd_data;
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layer_weight_buffer #(.DATA_WIDTH(DATA_WIDTH), .LAYER_DEPTH(LAYER_BYTES)) u_lwb (
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.clk(clk), .rst(rst),
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.fill_we(pf_fill_we), .fill_addr(pf_fill_addr), .fill_data(pf_fill_data), .fill_done(pf_done),
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.rd_addr(lwb_rd_addr), .rd_data(lwb_rd_data), .consume_done(consume_done),
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.active_sel(), .swapped()
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);
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reg tile_req;
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reg [BUFADDRW-1:0] tile_base;
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wire tile_valid;
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wire [DATA_WIDTH*P_IN-1:0] tile_data;
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wire [15:0] tcnt_next = tcnt + 16'd1;
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weight_tile_gather #(
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.DATA_WIDTH(DATA_WIDTH), .P_IN(P_IN), .BUFADDRW(BUFADDRW)
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) u_gather (
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.clk(clk), .rst(rst),
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.tile_req(tile_req), .tile_base(tile_base),
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.tile_valid(tile_valid), .tile_data(tile_data),
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.rd_addr(lwb_rd_addr), .rd_data(lwb_rd_data)
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);
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// ---- real broadcast bus to all 4 PEs (level-held, tcnt-tagged --
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// see packed_pe.v's own header for the real join discipline) ----
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reg group_tile_valid;
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reg [DATA_WIDTH*P_IN-1:0] group_tile_data_r;
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reg [3:0] pe_acked; // per-PE ack latch, cleared each tile
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wire [3:0] pe_job_start_w = {4{(state == S_PEJOBSTART)}};
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wire [3:0] pe_job_done_w;
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wire [3:0] pe_acked_pulse;
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genvar gi;
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generate
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for (gi = 0; gi < 4; gi = gi + 1) begin : GEN_PE
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packed_pe #(
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.DATA_WIDTH(DATA_WIDTH), .P_IN(P_IN), .ACC_WIDTH(ACC_WIDTH),
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.BURST_LEN(BURST_LEN), .ADDR_WIDTH(ADDR_WIDTH)
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) u_pe (
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.clk(clk), .rst(rst),
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.job_start(pe_job_start_w[gi]),
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.x_base_a(pe_x_base_a[gi*ADDR_WIDTH +: ADDR_WIDTH]),
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.x_base_b(pe_x_base_b[gi*ADDR_WIDTH +: ADDR_WIDTH]),
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.result_addr_a(pe_result_addr_a[gi*ADDR_WIDTH +: ADDR_WIDTH]),
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.result_addr_b(pe_result_addr_b[gi*ADDR_WIDTH +: ADDR_WIDTH]),
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.node_id_a(pe_node_id_a[gi*16 +: 16]), .node_id_b(pe_node_id_b[gi*16 +: 16]),
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.job_done(pe_job_done_w[gi]),
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.result_data_a(pe_result_data_a[gi*DATA_WIDTH +: DATA_WIDTH]),
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.result_data_b(pe_result_data_b[gi*DATA_WIDTH +: DATA_WIDTH]),
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.result_node_id_a(pe_result_node_id_a[gi*16 +: 16]),
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.result_node_id_b(pe_result_node_id_b[gi*16 +: 16]),
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.result_addr_a_out(pe_result_addr_a_out[gi*ADDR_WIDTH +: ADDR_WIDTH]),
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.result_addr_b_out(pe_result_addr_b_out[gi*ADDR_WIDTH +: ADDR_WIDTH]),
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.group_n_tiles(n_tiles_lat), .group_tcnt(tcnt),
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.group_tile_data(group_tile_data_r), .group_tile_valid(group_tile_valid),
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.pe_tile_ack(pe_acked_pulse[gi]),
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.mem_active(pe_mem_active[gi]), .mem_grant(pe_mem_grant[gi]),
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.ctrl_req(pe_ctrl_req[gi]), .ctrl_wr(pe_ctrl_wr[gi]),
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.ctrl_addr(pe_ctrl_addr[gi*(ADDR_WIDTH-1) +: (ADDR_WIDTH-1)]),
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.ctrl_wdata(pe_ctrl_wdata[gi*32*BURST_LEN +: 32*BURST_LEN]),
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.ctrl_wmask(pe_ctrl_wmask[gi*4*BURST_LEN +: 4*BURST_LEN]),
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.ctrl_rdata(pe_ctrl_rdata[gi*32*BURST_LEN +: 32*BURST_LEN]),
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.ctrl_ready(pe_ctrl_ready[gi]), .ctrl_busy(pe_ctrl_busy[gi])
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);
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end
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endgenerate
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reg [3:0] pe_done_latch;
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// combinational "what pe_acked/pe_done_latch would be if we also
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// fold in THIS cycle's own pulses" -- used both to DECIDE the
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// barrier this cycle (no extra latency) and, explicitly, as what
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// gets written back when the barrier hasn't cleared yet. Kept as
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// named wires (not relying on nonblocking-assignment-order
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// last-write-wins semantics) so the real intent is unambiguous to
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// a future reader, not just technically correct.
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wire [3:0] pe_acked_next = pe_acked | pe_acked_pulse;
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wire [3:0] pe_done_latch_next = pe_done_latch | pe_job_done_w;
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always @(posedge clk) begin
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if (rst) begin
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state <= S_IDLE;
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job_done <= 1'b0;
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pf_start <= 1'b0;
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consume_done <= 1'b0;
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tile_req <= 1'b0;
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group_tile_valid <= 1'b0;
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pe_acked <= 4'b0;
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pe_done_latch <= 4'b0;
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tcnt <= 16'd0;
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end else begin
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job_done <= 1'b0;
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pf_start <= 1'b0;
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consume_done <= 1'b0;
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tile_req <= 1'b0;
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// real race, deliberately handled: a PE's own job_done can
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// pulse the SAME cycle S_TILELOOP's barrier clears for the
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// LAST tile (i.e. the same cycle the group transitions to
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// S_WAITDONE) -- its own downstream writeback can complete
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// before the group has even formally entered S_WAITDONE.
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// Accumulate unconditionally, every cycle, so no early
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// pe_job_done_w pulse is ever missed; S_WAITDONE's own
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// success branch below explicitly overrides this back to 0
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// (Verilog's own last-nonblocking-write-wins rule within
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// one always block -- intentional here, unlike pe_acked's
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// window which is fully contained inside S_TILELOOP and so
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// uses the more explicit if/else form instead).
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pe_done_latch <= pe_done_latch_next;
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case (state)
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S_IDLE: begin
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if (job_start) begin
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w_base_lat <= w_base;
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n_tiles_lat <= n_tiles;
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tcnt <= 16'd0;
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state <= S_MEMWAIT;
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end
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end
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S_MEMWAIT: begin
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if (mem_grant) begin
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pf_start <= 1'b1;
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state <= S_PREFETCH;
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end
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end
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S_PREFETCH: begin
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if (pf_done) begin
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consume_done <= 1'b1;
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state <= S_SWAP;
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end
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end
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S_SWAP: begin
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// one settle cycle, same real reason packed_slot.v's
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// own S_SWAP exists (layer_weight_buffer.v's do_swap).
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state <= S_PEJOBSTART;
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end
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S_PEJOBSTART: begin
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// pe_job_start_w is combinational on (state ==
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// S_PEJOBSTART), so all 4 PEs see job_start the
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// SAME cycle -- real, established one-shot-pulse
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// discipline (EXP-0066), now applied 4-way.
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tile_req <= 1'b1;
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tile_base <= tcnt[BUFADDRW-1:0]*P_IN[BUFADDRW-1:0];
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state <= S_TILELOOP;
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end
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// real barrier: hold this tile's data broadcast until
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// ALL 4 PEs have ack'd it (pe_acked_next all-ones), THEN
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// advance tcnt and issue the next weight_tile_gather
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// request -- see this module's own header for why a
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// bare pulse/level race would be unsafe here. pe_acked
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// is explicitly written on EVERY path through this
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// state (either reset to 0 when the barrier clears, or
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// folded forward via pe_acked_next otherwise) -- never
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// relies on assignment order elsewhere in the block.
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S_TILELOOP: begin
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if (tile_valid && !group_tile_valid) begin
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group_tile_data_r <= tile_data;
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group_tile_valid <= 1'b1;
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end
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if (group_tile_valid && (&pe_acked_next)) begin
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group_tile_valid <= 1'b0;
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pe_acked <= 4'b0;
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if (tcnt == n_tiles_lat - 16'd1) begin
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state <= S_WAITDONE;
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end else begin
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tcnt <= tcnt_next;
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tile_req <= 1'b1;
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tile_base <= tcnt_next[BUFADDRW-1:0]*P_IN[BUFADDRW-1:0];
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state <= S_TILELOOP;
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end
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end else begin
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pe_acked <= pe_acked_next;
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end
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end
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S_WAITDONE: begin
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if (&pe_done_latch_next) begin
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pe_done_latch <= 4'b0;
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job_done <= 1'b1;
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state <= S_IDLE;
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end
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end
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default: state <= S_IDLE;
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endcase
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end
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end
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endmodule
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