micheleandClaude Sonnet 5
dc0b331d3e
Begins the V2 Neural Multiprocessor / Dataflow architecture per docs/v2-description.md, per explicit user request to freeze V1 and start V2 development, copying from V1 what's needed. Scaffold: - hardware/v1/: byte-exact, read-only copy of the current V1 codebase (rtl, testbenches, tools, constraints, a representative subset of synthesis results, and reference docs) -- verified identical via diff/cmp against the live top-level tree before being made filesystem-read-only. The live top-level tree is untouched and remains the project's "production" V1 (see hardware/v1/README.md and hardware/v2/logs/decisions.log DEC-0001 for why copy-not-move). - hardware/v2/: mandatory structure (rtl/sim/constraints/synthesis/ reports/scripts/logs/docs) plus the full logging system required by the spec (development/architecture/simulation/synthesis/timing/ benchmark/decisions/experiments/errors.log). M1 -- Neural Processor (hardware/v2/rtl/neural_processor.v): - 8-stage pipelined perceptron unit (P_IN=8): input align, 8 multipliers, 3-level adder tree, accumulator, bias+activation, INT8 saturation. Genuine 1-tile/cycle throughput, not just a wider combinational datapath. - 7-state FSM (NP_IDLE..NP_ERROR per docs/v2-description.md §6, with 4 baseline states merged into NP_WAIT_OPERANDS -- see decisions.log DEC-0002); valid/ready/data/last stream interfaces per §7. - Bit-exact vs the frozen hardware/v1/rtl/neuron_parallel.v + mac8.v + mac_unit.v: 7/7 tests pass (hardware/v2/sim/tb_neural_processor.v), covering regular/mixed-sign/extreme-INT8 vectors, both activations, a zero-idle-gap back-to-back-tiles throughput check, and an 8-tile job -- verified with Verilator (see below for why). - Real synthesis + place&route (Yosys + nextpnr-ecp5): 0 CHECK problems, Fmax 183.12 MHz at ACC_WIDTH=32 (PASS at 80MHz, ~3x V1's isolated PARALLEL=8 Fmax of 61.71 MHz) and 176.21 MHz at ACC_WIDTH=24 (a user-requested comparison experiment, also bit-exact-verified; see experiments.log EXP-0001/EXP-0002 and benchmark.log). Three real bugs found and resolved during M1 development (full diagnostic record in errors.log): - Two independent, reproducible Icarus Verilog v13.0 scheduling defects (ERR-0001, ERR-0002) that silently produced wrong simulation results for standard sequential Verilog -- confirmed via Verilator 5.050 giving correct results on the same minimal repros. Verilator is now the trusted simulator for hardware/v2/ (decisions.log DEC-0004); Icarus's affected protocol-violation check was removed from the RTL and deferred architecturally to the Neural Director (DEC-0003) rather than chased further. - One real RTL bug (ERR-0003): last0 wasn't gated like valid0, letting a "last tile" tag leak into the pipeline ahead of its actual valid tile on back-to-back jobs. Fixed and verified. Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
1970 lines
111 KiB
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1970 lines
111 KiB
Plaintext
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/----------------------------------------------------------------------------\
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| yosys -- Yosys Open SYnthesis Suite |
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| Copyright (C) 2012 - 2026 Claire Xenia Wolf <claire@yosyshq.com> |
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| Distributed under an ISC-like license, type "license" to see terms |
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\----------------------------------------------------------------------------/
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Yosys 0.68+post (git sha1 c12172fbae8af5e20f6fb52e3d4e92d56ed587b6, Release, AppleClang clang++ 21.0.0.21000101)
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-- Running command `
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read_verilog hardware/v2/rtl/neural_processor.v
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chparam -set ACC_WIDTH 24 neural_processor
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synth_ecp5 -json hardware/v2/synthesis/neural_processor_p8_acc24/top.json -top neural_processor
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' --
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1. Executing Verilog-2005 frontend: hardware/v2/rtl/neural_processor.v
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Parsing Verilog input from `hardware/v2/rtl/neural_processor.v' to AST representation.
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Generating RTLIL representation for module `\neural_processor'.
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Warning: Replacing memory \tree with list of registers. See hardware/v2/rtl/neural_processor.v:193
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Warning: Replacing memory \prod1 with list of registers. See hardware/v2/rtl/neural_processor.v:151
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Warning: Replacing memory \w0 with list of registers. See hardware/v2/rtl/neural_processor.v:122
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Warning: Replacing memory \x0 with list of registers. See hardware/v2/rtl/neural_processor.v:121
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Successfully finished Verilog frontend.
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Parameter \ACC_WIDTH = 24
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2. Executing AST frontend in derive mode using pre-parsed AST for module `\neural_processor'.
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Parameter \ACC_WIDTH = 24
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Generating RTLIL representation for module `$paramod\neural_processor\ACC_WIDTH=s32'00000000000000000000000000011000'.
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Warning: Replacing memory \tree with list of registers. See hardware/v2/rtl/neural_processor.v:193
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Warning: Replacing memory \prod1 with list of registers. See hardware/v2/rtl/neural_processor.v:151
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Warning: Replacing memory \w0 with list of registers. See hardware/v2/rtl/neural_processor.v:122
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Warning: Replacing memory \x0 with list of registers. See hardware/v2/rtl/neural_processor.v:121
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3. Executing SYNTH_LATTICE pass.
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3.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v
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Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v' to AST representation.
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Generating RTLIL representation for module `\LUT4'.
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Generating RTLIL representation for module `\$__ABC9_LUT5'.
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Generating RTLIL representation for module `\$__ABC9_LUT6'.
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Generating RTLIL representation for module `\$__ABC9_LUT7'.
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Generating RTLIL representation for module `\L6MUX21'.
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Generating RTLIL representation for module `\TRELLIS_RAM16X2'.
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Generating RTLIL representation for module `\PFUMX'.
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Generating RTLIL representation for module `\TRELLIS_DPR16X4'.
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Generating RTLIL representation for module `\DPR16X4C'.
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Generating RTLIL representation for module `\LUT2'.
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Generating RTLIL representation for module `\TRELLIS_FF'.
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Generating RTLIL representation for module `\TRELLIS_IO'.
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Generating RTLIL representation for module `\INV'.
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Generating RTLIL representation for module `\TRELLIS_COMB'.
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Generating RTLIL representation for module `\VLO'.
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Generating RTLIL representation for module `\VHI'.
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Generating RTLIL representation for module `\FD1P3AX'.
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Generating RTLIL representation for module `\FD1P3AY'.
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Generating RTLIL representation for module `\FD1P3BX'.
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Generating RTLIL representation for module `\FD1P3DX'.
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Generating RTLIL representation for module `\FD1P3IX'.
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Generating RTLIL representation for module `\FD1P3JX'.
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Generating RTLIL representation for module `\FD1S3AX'.
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Generating RTLIL representation for module `\FD1S3AY'.
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Generating RTLIL representation for module `\FD1S3BX'.
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Generating RTLIL representation for module `\FD1S3DX'.
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Generating RTLIL representation for module `\FD1S3IX'.
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Generating RTLIL representation for module `\FD1S3JX'.
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Generating RTLIL representation for module `\IFS1P3BX'.
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Generating RTLIL representation for module `\IFS1P3DX'.
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Generating RTLIL representation for module `\IFS1P3IX'.
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Generating RTLIL representation for module `\IFS1P3JX'.
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Generating RTLIL representation for module `\OFS1P3BX'.
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Generating RTLIL representation for module `\OFS1P3DX'.
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Generating RTLIL representation for module `\OFS1P3IX'.
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Generating RTLIL representation for module `\OFS1P3JX'.
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Generating RTLIL representation for module `\IB'.
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Generating RTLIL representation for module `\IBPU'.
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Generating RTLIL representation for module `\IBPD'.
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Generating RTLIL representation for module `\OB'.
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Generating RTLIL representation for module `\OBZ'.
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Generating RTLIL representation for module `\OBZPU'.
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Generating RTLIL representation for module `\OBZPD'.
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Generating RTLIL representation for module `\OBCO'.
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Generating RTLIL representation for module `\BB'.
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Generating RTLIL representation for module `\BBPU'.
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Generating RTLIL representation for module `\BBPD'.
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Generating RTLIL representation for module `\ILVDS'.
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Generating RTLIL representation for module `\OLVDS'.
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Generating RTLIL representation for module `\CCU2C'.
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Generating RTLIL representation for module `\DP16KD'.
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Replacing existing blackbox module `\FD1P3AX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:2.1-2.261.
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Generating RTLIL representation for module `\FD1P3AX'.
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Replacing existing blackbox module `\FD1P3AY' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:3.1-3.261.
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Generating RTLIL representation for module `\FD1P3AY'.
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Replacing existing blackbox module `\FD1P3BX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:4.1-4.261.
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Generating RTLIL representation for module `\FD1P3BX'.
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Replacing existing blackbox module `\FD1P3DX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:5.1-5.261.
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Generating RTLIL representation for module `\FD1P3DX'.
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Replacing existing blackbox module `\FD1P3IX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:6.1-6.261.
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Generating RTLIL representation for module `\FD1P3IX'.
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Replacing existing blackbox module `\FD1P3JX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:7.1-7.261.
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Generating RTLIL representation for module `\FD1P3JX'.
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Replacing existing blackbox module `\FD1S3AX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:8.1-8.261.
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Generating RTLIL representation for module `\FD1S3AX'.
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Replacing existing blackbox module `\FD1S3AY' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:9.1-9.261.
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Generating RTLIL representation for module `\FD1S3AY'.
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Replacing existing blackbox module `\FD1S3BX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:10.1-10.261.
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Generating RTLIL representation for module `\FD1S3BX'.
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Replacing existing blackbox module `\FD1S3DX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:11.1-11.261.
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Generating RTLIL representation for module `\FD1S3DX'.
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Replacing existing blackbox module `\FD1S3IX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:12.1-12.261.
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Generating RTLIL representation for module `\FD1S3IX'.
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Replacing existing blackbox module `\FD1S3JX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:13.1-13.261.
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Generating RTLIL representation for module `\FD1S3JX'.
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Replacing existing blackbox module `\IFS1P3BX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:26.1-26.301.
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Generating RTLIL representation for module `\IFS1P3BX'.
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Replacing existing blackbox module `\IFS1P3DX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:27.1-27.301.
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Generating RTLIL representation for module `\IFS1P3DX'.
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Replacing existing blackbox module `\IFS1P3IX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:28.1-28.301.
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Generating RTLIL representation for module `\IFS1P3IX'.
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Replacing existing blackbox module `\IFS1P3JX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:29.1-29.301.
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Generating RTLIL representation for module `\IFS1P3JX'.
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Replacing existing blackbox module `\OFS1P3BX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:31.1-31.302.
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Generating RTLIL representation for module `\OFS1P3BX'.
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Replacing existing blackbox module `\OFS1P3DX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:32.1-32.302.
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Generating RTLIL representation for module `\OFS1P3DX'.
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Replacing existing blackbox module `\OFS1P3IX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:33.1-33.302.
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Generating RTLIL representation for module `\OFS1P3IX'.
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Replacing existing blackbox module `\OFS1P3JX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:34.1-34.302.
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Generating RTLIL representation for module `\OFS1P3JX'.
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Replacing existing blackbox module `\IB' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:2.1-2.157.
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Generating RTLIL representation for module `\IB'.
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Replacing existing blackbox module `\IBPU' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:3.1-3.157.
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Generating RTLIL representation for module `\IBPU'.
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Replacing existing blackbox module `\IBPD' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:4.1-4.157.
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Generating RTLIL representation for module `\IBPD'.
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Replacing existing blackbox module `\OB' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:5.1-5.157.
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Generating RTLIL representation for module `\OB'.
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Replacing existing blackbox module `\OBZ' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:6.1-6.164.
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Generating RTLIL representation for module `\OBZ'.
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Replacing existing blackbox module `\OBZPU' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:7.1-7.164.
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Generating RTLIL representation for module `\OBZPU'.
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Replacing existing blackbox module `\OBZPD' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:8.1-8.164.
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Generating RTLIL representation for module `\OBZPD'.
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Replacing existing blackbox module `\OBCO' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:9.1-9.90.
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Generating RTLIL representation for module `\OBCO'.
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Replacing existing blackbox module `\BB' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:10.1-10.179.
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Generating RTLIL representation for module `\BB'.
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Replacing existing blackbox module `\BBPU' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:11.1-11.179.
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Generating RTLIL representation for module `\BBPU'.
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Replacing existing blackbox module `\BBPD' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:12.1-12.179.
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Generating RTLIL representation for module `\BBPD'.
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Replacing existing blackbox module `\ILVDS' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:13.1-13.139.
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Generating RTLIL representation for module `\ILVDS'.
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Replacing existing blackbox module `\OLVDS' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:14.1-14.146.
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Generating RTLIL representation for module `\OLVDS'.
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Successfully finished Verilog frontend.
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3.2. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v
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Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v' to AST representation.
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Generating RTLIL representation for module `\GSR'.
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Generating RTLIL representation for module `\PUR'.
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Generating RTLIL representation for module `\SGSR'.
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Generating RTLIL representation for module `\PDPW16KD'.
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Generating RTLIL representation for module `\MULT18X18D'.
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Generating RTLIL representation for module `\ALU54B'.
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Generating RTLIL representation for module `\CLKDIVF'.
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Generating RTLIL representation for module `\PCSCLKDIV'.
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Generating RTLIL representation for module `\DCSC'.
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Generating RTLIL representation for module `\DCCA'.
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Generating RTLIL representation for module `\ECLKSYNCB'.
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Generating RTLIL representation for module `\ECLKBRIDGECS'.
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Generating RTLIL representation for module `\DELAYF'.
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Generating RTLIL representation for module `\DELAYG'.
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Generating RTLIL representation for module `\USRMCLK'.
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Generating RTLIL representation for module `\DQSBUFM'.
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Generating RTLIL representation for module `\DDRDLLA'.
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Generating RTLIL representation for module `\DLLDELD'.
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Generating RTLIL representation for module `\IDDRX1F'.
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Generating RTLIL representation for module `\IDDRX2F'.
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Generating RTLIL representation for module `\IDDR71B'.
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Generating RTLIL representation for module `\IDDRX2DQA'.
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Generating RTLIL representation for module `\ODDRX1F'.
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Generating RTLIL representation for module `\ODDRX2F'.
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Generating RTLIL representation for module `\ODDR71B'.
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Generating RTLIL representation for module `\OSHX2A'.
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Generating RTLIL representation for module `\TSHX2DQA'.
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Generating RTLIL representation for module `\TSHX2DQSA'.
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Generating RTLIL representation for module `\ODDRX2DQA'.
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Generating RTLIL representation for module `\ODDRX2DQSB'.
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Generating RTLIL representation for module `\EHXPLLL'.
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Generating RTLIL representation for module `\DTR'.
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Generating RTLIL representation for module `\OSCG'.
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Generating RTLIL representation for module `\EXTREFB'.
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Generating RTLIL representation for module `\JTAGG'.
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Generating RTLIL representation for module `\DCUA'.
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Successfully finished Verilog frontend.
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3.3. Executing HIERARCHY pass (managing design hierarchy).
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3.3.1. Analyzing design hierarchy..
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Top module: \neural_processor
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3.3.2. Analyzing design hierarchy..
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Top module: \neural_processor
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Removed 0 unused modules.
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3.4. Executing PROC pass (convert processes to netlists).
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3.4.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
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Cleaned up 0 empty switches.
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3.4.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
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Marked 2 switch rules as full_case in process $proc$hardware/v2/rtl/neural_processor.v:104$83 in module neural_processor.
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Marked 1 switch rules as full_case in process $proc$hardware/v2/rtl/neural_processor.v:143$88 in module neural_processor.
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Marked 2 switch rules as full_case in process $proc$hardware/v2/rtl/neural_processor.v:215$89 in module neural_processor.
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Marked 1 switch rules as full_case in process $proc$hardware/v2/rtl/neural_processor.v:245$92 in module neural_processor.
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Marked 2 switch rules as full_case in process $proc$hardware/v2/rtl/neural_processor.v:278$105 in module neural_processor.
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Marked 2 switch rules as full_case in process $proc$hardware/v2/rtl/neural_processor.v:305$115 in module neural_processor.
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Marked 1 switch rules as full_case in process $proc$hardware/v2/rtl/neural_processor.v:181$120 in module neural_processor.
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Marked 1 switch rules as full_case in process $proc$hardware/v2/rtl/neural_processor.v:181$129 in module neural_processor.
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Marked 1 switch rules as full_case in process $proc$hardware/v2/rtl/neural_processor.v:181$134 in module neural_processor.
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Removed a total of 0 dead cases.
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3.4.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
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Removed 15 redundant assignments.
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Promoted 25 assignments to connections.
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3.4.4. Executing PROC_INIT pass (extract init attributes).
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3.4.5. Executing PROC_ARST pass (detect async resets in processes).
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3.4.6. Executing PROC_ROM pass (convert switches to ROMs).
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Converted 0 switches.
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<suppressed ~18 debug messages>
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3.4.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
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Creating decoders for process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:104$83'.
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1/20: $2\gi[31:0]
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2/20: $0\last0[0:0]
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3/20: $0\valid0[0:0]
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4/20: $1\gi[31:0]
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5/20: $0\w0[7][7:0]
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6/20: $0\w0[6][7:0]
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7/20: $0\w0[5][7:0]
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8/20: $0\w0[4][7:0]
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9/20: $0\w0[3][7:0]
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10/20: $0\w0[2][7:0]
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11/20: $0\w0[1][7:0]
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12/20: $0\w0[0][7:0]
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13/20: $0\x0[7][7:0]
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14/20: $0\x0[6][7:0]
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15/20: $0\x0[5][7:0]
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16/20: $0\x0[4][7:0]
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17/20: $0\x0[3][7:0]
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18/20: $0\x0[2][7:0]
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19/20: $0\x0[1][7:0]
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20/20: $0\x0[0][7:0]
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Creating decoders for process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:143$88'.
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1/11: $0\last1[0:0]
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2/11: $0\valid1[0:0]
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3/11: $4\gi[31:0]
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4/11: $0\prod1[7][23:0]
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5/11: $0\prod1[6][23:0]
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6/11: $0\prod1[5][23:0]
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7/11: $0\prod1[4][23:0]
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8/11: $0\prod1[3][23:0]
|
|
9/11: $0\prod1[2][23:0]
|
|
10/11: $0\prod1[1][23:0]
|
|
11/11: $0\prod1[0][23:0]
|
|
Creating decoders for process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:215$89'.
|
|
1/3: $0\last5[0:0]
|
|
2/3: $0\valid5[0:0]
|
|
3/3: $0\acc_reg[23:0]
|
|
Creating decoders for process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:245$92'.
|
|
1/3: $0\last6[0:0]
|
|
2/3: $0\valid6[0:0]
|
|
3/3: $0\final_acc_reg[23:0]
|
|
Creating decoders for process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:278$105'.
|
|
1/2: $0\valid7[0:0]
|
|
2/2: $0\y7[7:0]
|
|
Creating decoders for process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:305$115'.
|
|
1/8: $0\node_id_reg[15:0]
|
|
2/8: $0\activation_reg[1:0]
|
|
3/8: $0\bias_reg[7:0]
|
|
4/8: $0\np_error[0:0]
|
|
5/8: $0\np_state[3:0]
|
|
6/8: $0\result_node_id[15:0]
|
|
7/8: $0\result_data[7:0]
|
|
8/8: $0\result_valid[0:0]
|
|
Creating decoders for process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:181$120'.
|
|
1/2: $0\last_tree[0:0]
|
|
2/2: $0\valid_tree[0:0]
|
|
Creating decoders for process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:192$121'.
|
|
Creating decoders for process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:192$123'.
|
|
Creating decoders for process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:192$125'.
|
|
Creating decoders for process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:192$127'.
|
|
Creating decoders for process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:181$129'.
|
|
1/2: $0\last_tree[1:1]
|
|
2/2: $0\valid_tree[1:1]
|
|
Creating decoders for process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:196$130'.
|
|
Creating decoders for process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:196$132'.
|
|
Creating decoders for process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:181$134'.
|
|
1/2: $0\last_tree[2:2]
|
|
2/2: $0\valid_tree[2:2]
|
|
Creating decoders for process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:196$135'.
|
|
Creating decoders for process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:139$137'.
|
|
Creating decoders for process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:139$139'.
|
|
Creating decoders for process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:139$141'.
|
|
Creating decoders for process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:139$143'.
|
|
Creating decoders for process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:139$145'.
|
|
Creating decoders for process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:139$147'.
|
|
Creating decoders for process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:139$149'.
|
|
Creating decoders for process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:139$151'.
|
|
Creating decoders for process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:170$153'.
|
|
Creating decoders for process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:170$154'.
|
|
Creating decoders for process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:170$155'.
|
|
Creating decoders for process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:170$156'.
|
|
Creating decoders for process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:170$157'.
|
|
Creating decoders for process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:170$158'.
|
|
Creating decoders for process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:170$159'.
|
|
Creating decoders for process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:170$160'.
|
|
|
|
3.4.8. Executing PROC_DLATCH pass (convert process syncs to latches).
|
|
No latch inferred for signal `\neural_processor.\product_comb[0]' from process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:139$137'.
|
|
No latch inferred for signal `\neural_processor.\product_comb[1]' from process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:139$139'.
|
|
No latch inferred for signal `\neural_processor.\product_comb[2]' from process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:139$141'.
|
|
No latch inferred for signal `\neural_processor.\product_comb[3]' from process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:139$143'.
|
|
No latch inferred for signal `\neural_processor.\product_comb[4]' from process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:139$145'.
|
|
No latch inferred for signal `\neural_processor.\product_comb[5]' from process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:139$147'.
|
|
No latch inferred for signal `\neural_processor.\product_comb[6]' from process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:139$149'.
|
|
No latch inferred for signal `\neural_processor.\product_comb[7]' from process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:139$151'.
|
|
No latch inferred for signal `\neural_processor.\level0[0]' from process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:170$153'.
|
|
No latch inferred for signal `\neural_processor.\level0[1]' from process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:170$154'.
|
|
No latch inferred for signal `\neural_processor.\level0[2]' from process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:170$155'.
|
|
No latch inferred for signal `\neural_processor.\level0[3]' from process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:170$156'.
|
|
No latch inferred for signal `\neural_processor.\level0[4]' from process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:170$157'.
|
|
No latch inferred for signal `\neural_processor.\level0[5]' from process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:170$158'.
|
|
No latch inferred for signal `\neural_processor.\level0[6]' from process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:170$159'.
|
|
No latch inferred for signal `\neural_processor.\level0[7]' from process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:170$160'.
|
|
|
|
3.4.9. Executing PROC_DFF pass (convert process syncs to FFs).
|
|
Creating register for signal `\neural_processor.\valid0' using process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:104$83'.
|
|
created $dff cell `$procdff$680' with positive edge clock.
|
|
Creating register for signal `\neural_processor.\last0' using process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:104$83'.
|
|
created $dff cell `$procdff$681' with positive edge clock.
|
|
Creating register for signal `\neural_processor.\gi' using process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:104$83'.
|
|
created $dff cell `$procdff$682' with positive edge clock.
|
|
Creating register for signal `\neural_processor.\x0[0]' using process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:104$83'.
|
|
created $dff cell `$procdff$683' with positive edge clock.
|
|
Creating register for signal `\neural_processor.\x0[1]' using process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:104$83'.
|
|
created $dff cell `$procdff$684' with positive edge clock.
|
|
Creating register for signal `\neural_processor.\x0[2]' using process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:104$83'.
|
|
created $dff cell `$procdff$685' with positive edge clock.
|
|
Creating register for signal `\neural_processor.\x0[3]' using process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:104$83'.
|
|
created $dff cell `$procdff$686' with positive edge clock.
|
|
Creating register for signal `\neural_processor.\x0[4]' using process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:104$83'.
|
|
created $dff cell `$procdff$687' with positive edge clock.
|
|
Creating register for signal `\neural_processor.\x0[5]' using process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:104$83'.
|
|
created $dff cell `$procdff$688' with positive edge clock.
|
|
Creating register for signal `\neural_processor.\x0[6]' using process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:104$83'.
|
|
created $dff cell `$procdff$689' with positive edge clock.
|
|
Creating register for signal `\neural_processor.\x0[7]' using process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:104$83'.
|
|
created $dff cell `$procdff$690' with positive edge clock.
|
|
Creating register for signal `\neural_processor.\w0[0]' using process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:104$83'.
|
|
created $dff cell `$procdff$691' with positive edge clock.
|
|
Creating register for signal `\neural_processor.\w0[1]' using process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:104$83'.
|
|
created $dff cell `$procdff$692' with positive edge clock.
|
|
Creating register for signal `\neural_processor.\w0[2]' using process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:104$83'.
|
|
created $dff cell `$procdff$693' with positive edge clock.
|
|
Creating register for signal `\neural_processor.\w0[3]' using process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:104$83'.
|
|
created $dff cell `$procdff$694' with positive edge clock.
|
|
Creating register for signal `\neural_processor.\w0[4]' using process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:104$83'.
|
|
created $dff cell `$procdff$695' with positive edge clock.
|
|
Creating register for signal `\neural_processor.\w0[5]' using process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:104$83'.
|
|
created $dff cell `$procdff$696' with positive edge clock.
|
|
Creating register for signal `\neural_processor.\w0[6]' using process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:104$83'.
|
|
created $dff cell `$procdff$697' with positive edge clock.
|
|
Creating register for signal `\neural_processor.\w0[7]' using process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:104$83'.
|
|
created $dff cell `$procdff$698' with positive edge clock.
|
|
Creating register for signal `\neural_processor.\gi' using process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:143$88'.
|
|
created $dff cell `$procdff$699' with positive edge clock.
|
|
Creating register for signal `\neural_processor.\valid1' using process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:143$88'.
|
|
created $dff cell `$procdff$700' with positive edge clock.
|
|
Creating register for signal `\neural_processor.\last1' using process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:143$88'.
|
|
created $dff cell `$procdff$701' with positive edge clock.
|
|
Creating register for signal `\neural_processor.\prod1[0]' using process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:143$88'.
|
|
created $dff cell `$procdff$702' with positive edge clock.
|
|
Creating register for signal `\neural_processor.\prod1[1]' using process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:143$88'.
|
|
created $dff cell `$procdff$703' with positive edge clock.
|
|
Creating register for signal `\neural_processor.\prod1[2]' using process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:143$88'.
|
|
created $dff cell `$procdff$704' with positive edge clock.
|
|
Creating register for signal `\neural_processor.\prod1[3]' using process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:143$88'.
|
|
created $dff cell `$procdff$705' with positive edge clock.
|
|
Creating register for signal `\neural_processor.\prod1[4]' using process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:143$88'.
|
|
created $dff cell `$procdff$706' with positive edge clock.
|
|
Creating register for signal `\neural_processor.\prod1[5]' using process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:143$88'.
|
|
created $dff cell `$procdff$707' with positive edge clock.
|
|
Creating register for signal `\neural_processor.\prod1[6]' using process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:143$88'.
|
|
created $dff cell `$procdff$708' with positive edge clock.
|
|
Creating register for signal `\neural_processor.\prod1[7]' using process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:143$88'.
|
|
created $dff cell `$procdff$709' with positive edge clock.
|
|
Creating register for signal `\neural_processor.\acc_reg' using process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:215$89'.
|
|
created $dff cell `$procdff$710' with positive edge clock.
|
|
Creating register for signal `\neural_processor.\valid5' using process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:215$89'.
|
|
created $dff cell `$procdff$711' with positive edge clock.
|
|
Creating register for signal `\neural_processor.\last5' using process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:215$89'.
|
|
created $dff cell `$procdff$712' with positive edge clock.
|
|
Creating register for signal `\neural_processor.\valid6' using process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:245$92'.
|
|
created $dff cell `$procdff$713' with positive edge clock.
|
|
Creating register for signal `\neural_processor.\last6' using process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:245$92'.
|
|
created $dff cell `$procdff$714' with positive edge clock.
|
|
Creating register for signal `\neural_processor.\final_acc_reg' using process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:245$92'.
|
|
created $dff cell `$procdff$715' with positive edge clock.
|
|
Creating register for signal `\neural_processor.\valid7' using process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:278$105'.
|
|
created $dff cell `$procdff$716' with positive edge clock.
|
|
Creating register for signal `\neural_processor.\y7' using process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:278$105'.
|
|
created $dff cell `$procdff$717' with positive edge clock.
|
|
Creating register for signal `\neural_processor.\result_valid' using process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:305$115'.
|
|
created $dff cell `$procdff$718' with positive edge clock.
|
|
Creating register for signal `\neural_processor.\result_data' using process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:305$115'.
|
|
created $dff cell `$procdff$719' with positive edge clock.
|
|
Creating register for signal `\neural_processor.\result_node_id' using process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:305$115'.
|
|
created $dff cell `$procdff$720' with positive edge clock.
|
|
Creating register for signal `\neural_processor.\np_state' using process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:305$115'.
|
|
created $dff cell `$procdff$721' with positive edge clock.
|
|
Creating register for signal `\neural_processor.\np_error' using process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:305$115'.
|
|
created $dff cell `$procdff$722' with positive edge clock.
|
|
Creating register for signal `\neural_processor.\bias_reg' using process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:305$115'.
|
|
created $dff cell `$procdff$723' with positive edge clock.
|
|
Creating register for signal `\neural_processor.\activation_reg' using process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:305$115'.
|
|
created $dff cell `$procdff$724' with positive edge clock.
|
|
Creating register for signal `\neural_processor.\node_id_reg' using process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:305$115'.
|
|
created $dff cell `$procdff$725' with positive edge clock.
|
|
Creating register for signal `\neural_processor.\valid_tree [0]' using process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:181$120'.
|
|
created $dff cell `$procdff$726' with positive edge clock.
|
|
Creating register for signal `\neural_processor.\last_tree [0]' using process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:181$120'.
|
|
created $dff cell `$procdff$727' with positive edge clock.
|
|
Creating register for signal `\neural_processor.\tree[0]' using process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:192$121'.
|
|
created $dff cell `$procdff$728' with positive edge clock.
|
|
Creating register for signal `\neural_processor.\tree[1]' using process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:192$123'.
|
|
created $dff cell `$procdff$729' with positive edge clock.
|
|
Creating register for signal `\neural_processor.\tree[2]' using process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:192$125'.
|
|
created $dff cell `$procdff$730' with positive edge clock.
|
|
Creating register for signal `\neural_processor.\tree[3]' using process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:192$127'.
|
|
created $dff cell `$procdff$731' with positive edge clock.
|
|
Creating register for signal `\neural_processor.\valid_tree [1]' using process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:181$129'.
|
|
created $dff cell `$procdff$732' with positive edge clock.
|
|
Creating register for signal `\neural_processor.\last_tree [1]' using process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:181$129'.
|
|
created $dff cell `$procdff$733' with positive edge clock.
|
|
Creating register for signal `\neural_processor.\tree[8]' using process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:196$130'.
|
|
created $dff cell `$procdff$734' with positive edge clock.
|
|
Creating register for signal `\neural_processor.\tree[9]' using process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:196$132'.
|
|
created $dff cell `$procdff$735' with positive edge clock.
|
|
Creating register for signal `\neural_processor.\valid_tree [2]' using process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:181$134'.
|
|
created $dff cell `$procdff$736' with positive edge clock.
|
|
Creating register for signal `\neural_processor.\last_tree [2]' using process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:181$134'.
|
|
created $dff cell `$procdff$737' with positive edge clock.
|
|
Creating register for signal `\neural_processor.\tree[16]' using process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:196$135'.
|
|
created $dff cell `$procdff$738' with positive edge clock.
|
|
|
|
3.4.10. Executing PROC_MEMWR pass (convert process memory writes to cells).
|
|
|
|
3.4.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
|
|
Found and cleaned up 2 empty switches in `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:104$83'.
|
|
Removing empty process `neural_processor.$proc$hardware/v2/rtl/neural_processor.v:104$83'.
|
|
Found and cleaned up 1 empty switch in `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:143$88'.
|
|
Removing empty process `neural_processor.$proc$hardware/v2/rtl/neural_processor.v:143$88'.
|
|
Found and cleaned up 3 empty switches in `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:215$89'.
|
|
Removing empty process `neural_processor.$proc$hardware/v2/rtl/neural_processor.v:215$89'.
|
|
Found and cleaned up 1 empty switch in `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:245$92'.
|
|
Removing empty process `neural_processor.$proc$hardware/v2/rtl/neural_processor.v:245$92'.
|
|
Found and cleaned up 2 empty switches in `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:278$105'.
|
|
Removing empty process `neural_processor.$proc$hardware/v2/rtl/neural_processor.v:278$105'.
|
|
Found and cleaned up 6 empty switches in `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:305$115'.
|
|
Removing empty process `neural_processor.$proc$hardware/v2/rtl/neural_processor.v:305$115'.
|
|
Found and cleaned up 1 empty switch in `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:181$120'.
|
|
Removing empty process `neural_processor.$proc$hardware/v2/rtl/neural_processor.v:181$120'.
|
|
Removing empty process `neural_processor.$proc$hardware/v2/rtl/neural_processor.v:192$121'.
|
|
Removing empty process `neural_processor.$proc$hardware/v2/rtl/neural_processor.v:192$123'.
|
|
Removing empty process `neural_processor.$proc$hardware/v2/rtl/neural_processor.v:192$125'.
|
|
Removing empty process `neural_processor.$proc$hardware/v2/rtl/neural_processor.v:192$127'.
|
|
Found and cleaned up 1 empty switch in `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:181$129'.
|
|
Removing empty process `neural_processor.$proc$hardware/v2/rtl/neural_processor.v:181$129'.
|
|
Removing empty process `neural_processor.$proc$hardware/v2/rtl/neural_processor.v:196$130'.
|
|
Removing empty process `neural_processor.$proc$hardware/v2/rtl/neural_processor.v:196$132'.
|
|
Found and cleaned up 1 empty switch in `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:181$134'.
|
|
Removing empty process `neural_processor.$proc$hardware/v2/rtl/neural_processor.v:181$134'.
|
|
Removing empty process `neural_processor.$proc$hardware/v2/rtl/neural_processor.v:196$135'.
|
|
Removing empty process `neural_processor.$proc$hardware/v2/rtl/neural_processor.v:139$137'.
|
|
Removing empty process `neural_processor.$proc$hardware/v2/rtl/neural_processor.v:139$139'.
|
|
Removing empty process `neural_processor.$proc$hardware/v2/rtl/neural_processor.v:139$141'.
|
|
Removing empty process `neural_processor.$proc$hardware/v2/rtl/neural_processor.v:139$143'.
|
|
Removing empty process `neural_processor.$proc$hardware/v2/rtl/neural_processor.v:139$145'.
|
|
Removing empty process `neural_processor.$proc$hardware/v2/rtl/neural_processor.v:139$147'.
|
|
Removing empty process `neural_processor.$proc$hardware/v2/rtl/neural_processor.v:139$149'.
|
|
Removing empty process `neural_processor.$proc$hardware/v2/rtl/neural_processor.v:139$151'.
|
|
Removing empty process `neural_processor.$proc$hardware/v2/rtl/neural_processor.v:170$153'.
|
|
Removing empty process `neural_processor.$proc$hardware/v2/rtl/neural_processor.v:170$154'.
|
|
Removing empty process `neural_processor.$proc$hardware/v2/rtl/neural_processor.v:170$155'.
|
|
Removing empty process `neural_processor.$proc$hardware/v2/rtl/neural_processor.v:170$156'.
|
|
Removing empty process `neural_processor.$proc$hardware/v2/rtl/neural_processor.v:170$157'.
|
|
Removing empty process `neural_processor.$proc$hardware/v2/rtl/neural_processor.v:170$158'.
|
|
Removing empty process `neural_processor.$proc$hardware/v2/rtl/neural_processor.v:170$159'.
|
|
Removing empty process `neural_processor.$proc$hardware/v2/rtl/neural_processor.v:170$160'.
|
|
Cleaned up 18 empty switches.
|
|
|
|
3.4.12. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module neural_processor.
|
|
<suppressed ~7 debug messages>
|
|
|
|
3.5. Executing CHECK pass (checking for obvious problems).
|
|
Checking module neural_processor...
|
|
Warning: multiple conflicting drivers for neural_processor.\gi [31]:
|
|
port Q[31] of cell $procdff$699 ($dff)
|
|
port Q[31] of cell $procdff$682 ($dff)
|
|
Warning: multiple conflicting drivers for neural_processor.\gi [30]:
|
|
port Q[30] of cell $procdff$699 ($dff)
|
|
port Q[30] of cell $procdff$682 ($dff)
|
|
Warning: multiple conflicting drivers for neural_processor.\gi [29]:
|
|
port Q[29] of cell $procdff$699 ($dff)
|
|
port Q[29] of cell $procdff$682 ($dff)
|
|
Warning: multiple conflicting drivers for neural_processor.\gi [28]:
|
|
port Q[28] of cell $procdff$699 ($dff)
|
|
port Q[28] of cell $procdff$682 ($dff)
|
|
Warning: multiple conflicting drivers for neural_processor.\gi [27]:
|
|
port Q[27] of cell $procdff$699 ($dff)
|
|
port Q[27] of cell $procdff$682 ($dff)
|
|
Warning: multiple conflicting drivers for neural_processor.\gi [26]:
|
|
port Q[26] of cell $procdff$699 ($dff)
|
|
port Q[26] of cell $procdff$682 ($dff)
|
|
Warning: multiple conflicting drivers for neural_processor.\gi [25]:
|
|
port Q[25] of cell $procdff$699 ($dff)
|
|
port Q[25] of cell $procdff$682 ($dff)
|
|
Warning: multiple conflicting drivers for neural_processor.\gi [24]:
|
|
port Q[24] of cell $procdff$699 ($dff)
|
|
port Q[24] of cell $procdff$682 ($dff)
|
|
Warning: multiple conflicting drivers for neural_processor.\gi [23]:
|
|
port Q[23] of cell $procdff$699 ($dff)
|
|
port Q[23] of cell $procdff$682 ($dff)
|
|
Warning: multiple conflicting drivers for neural_processor.\gi [22]:
|
|
port Q[22] of cell $procdff$699 ($dff)
|
|
port Q[22] of cell $procdff$682 ($dff)
|
|
Warning: multiple conflicting drivers for neural_processor.\gi [21]:
|
|
port Q[21] of cell $procdff$699 ($dff)
|
|
port Q[21] of cell $procdff$682 ($dff)
|
|
Warning: multiple conflicting drivers for neural_processor.\gi [20]:
|
|
port Q[20] of cell $procdff$699 ($dff)
|
|
port Q[20] of cell $procdff$682 ($dff)
|
|
Warning: multiple conflicting drivers for neural_processor.\gi [19]:
|
|
port Q[19] of cell $procdff$699 ($dff)
|
|
port Q[19] of cell $procdff$682 ($dff)
|
|
Warning: multiple conflicting drivers for neural_processor.\gi [18]:
|
|
port Q[18] of cell $procdff$699 ($dff)
|
|
port Q[18] of cell $procdff$682 ($dff)
|
|
Warning: multiple conflicting drivers for neural_processor.\gi [17]:
|
|
port Q[17] of cell $procdff$699 ($dff)
|
|
port Q[17] of cell $procdff$682 ($dff)
|
|
Warning: multiple conflicting drivers for neural_processor.\gi [16]:
|
|
port Q[16] of cell $procdff$699 ($dff)
|
|
port Q[16] of cell $procdff$682 ($dff)
|
|
Warning: multiple conflicting drivers for neural_processor.\gi [15]:
|
|
port Q[15] of cell $procdff$699 ($dff)
|
|
port Q[15] of cell $procdff$682 ($dff)
|
|
Warning: multiple conflicting drivers for neural_processor.\gi [14]:
|
|
port Q[14] of cell $procdff$699 ($dff)
|
|
port Q[14] of cell $procdff$682 ($dff)
|
|
Warning: multiple conflicting drivers for neural_processor.\gi [13]:
|
|
port Q[13] of cell $procdff$699 ($dff)
|
|
port Q[13] of cell $procdff$682 ($dff)
|
|
Warning: multiple conflicting drivers for neural_processor.\gi [12]:
|
|
port Q[12] of cell $procdff$699 ($dff)
|
|
port Q[12] of cell $procdff$682 ($dff)
|
|
Warning: multiple conflicting drivers for neural_processor.\gi [11]:
|
|
port Q[11] of cell $procdff$699 ($dff)
|
|
port Q[11] of cell $procdff$682 ($dff)
|
|
Warning: multiple conflicting drivers for neural_processor.\gi [10]:
|
|
port Q[10] of cell $procdff$699 ($dff)
|
|
port Q[10] of cell $procdff$682 ($dff)
|
|
Warning: multiple conflicting drivers for neural_processor.\gi [9]:
|
|
port Q[9] of cell $procdff$699 ($dff)
|
|
port Q[9] of cell $procdff$682 ($dff)
|
|
Warning: multiple conflicting drivers for neural_processor.\gi [8]:
|
|
port Q[8] of cell $procdff$699 ($dff)
|
|
port Q[8] of cell $procdff$682 ($dff)
|
|
Warning: multiple conflicting drivers for neural_processor.\gi [7]:
|
|
port Q[7] of cell $procdff$699 ($dff)
|
|
port Q[7] of cell $procdff$682 ($dff)
|
|
Warning: multiple conflicting drivers for neural_processor.\gi [6]:
|
|
port Q[6] of cell $procdff$699 ($dff)
|
|
port Q[6] of cell $procdff$682 ($dff)
|
|
Warning: multiple conflicting drivers for neural_processor.\gi [5]:
|
|
port Q[5] of cell $procdff$699 ($dff)
|
|
port Q[5] of cell $procdff$682 ($dff)
|
|
Warning: multiple conflicting drivers for neural_processor.\gi [4]:
|
|
port Q[4] of cell $procdff$699 ($dff)
|
|
port Q[4] of cell $procdff$682 ($dff)
|
|
Warning: multiple conflicting drivers for neural_processor.\gi [3]:
|
|
port Q[3] of cell $procdff$699 ($dff)
|
|
port Q[3] of cell $procdff$682 ($dff)
|
|
Warning: multiple conflicting drivers for neural_processor.\gi [2]:
|
|
port Q[2] of cell $procdff$699 ($dff)
|
|
port Q[2] of cell $procdff$682 ($dff)
|
|
Warning: multiple conflicting drivers for neural_processor.\gi [1]:
|
|
port Q[1] of cell $procdff$699 ($dff)
|
|
port Q[1] of cell $procdff$682 ($dff)
|
|
Warning: multiple conflicting drivers for neural_processor.\gi [0]:
|
|
port Q[0] of cell $procdff$699 ($dff)
|
|
port Q[0] of cell $procdff$682 ($dff)
|
|
Found and reported 32 problems.
|
|
|
|
3.6. Executing FLATTEN pass (flatten design).
|
|
|
|
3.7. Executing TRIBUF pass.
|
|
|
|
3.8. Executing DEMINOUT pass (demote inout ports to input or output).
|
|
|
|
3.9. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module neural_processor.
|
|
|
|
3.10. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \neural_processor..
|
|
Removed 6 unused cells and 200 unused wires.
|
|
<suppressed ~25 debug messages>
|
|
|
|
3.11. Executing CHECK pass (checking for obvious problems).
|
|
Checking module neural_processor...
|
|
Found and reported 0 problems.
|
|
|
|
3.12. Executing OPT pass (performing simple optimizations).
|
|
|
|
3.12.1. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module neural_processor.
|
|
|
|
3.12.2. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\neural_processor'.
|
|
Computing hashes of 206 cells of `\neural_processor'.
|
|
Finding duplicate cells in `\neural_processor'.
|
|
Computing hashes of 193 cells of `\neural_processor'.
|
|
Finding duplicate cells in `\neural_processor'.
|
|
<suppressed ~39 debug messages>
|
|
Removed a total of 13 cells.
|
|
|
|
3.12.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \neural_processor..
|
|
Creating internal representation of mux trees.
|
|
Evaluating internal representation of mux trees.
|
|
Analyzing evaluation results.
|
|
Removed 0 multiplexer ports.
|
|
<suppressed ~142 debug messages>
|
|
|
|
3.12.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \neural_processor.
|
|
Performed a total of 0 changes.
|
|
|
|
3.12.5. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\neural_processor'.
|
|
Computing hashes of 193 cells of `\neural_processor'.
|
|
Finding duplicate cells in `\neural_processor'.
|
|
Removed a total of 0 cells.
|
|
|
|
3.12.6. Executing OPT_DFF pass (perform DFF optimizations).
|
|
|
|
3.12.7. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \neural_processor..
|
|
Removed 0 unused cells and 13 unused wires.
|
|
<suppressed ~1 debug messages>
|
|
|
|
3.12.8. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module neural_processor.
|
|
|
|
3.12.9. Rerunning OPT passes. (Maybe there is more to do..)
|
|
|
|
3.12.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \neural_processor..
|
|
Creating internal representation of mux trees.
|
|
Evaluating internal representation of mux trees.
|
|
Analyzing evaluation results.
|
|
Removed 0 multiplexer ports.
|
|
<suppressed ~142 debug messages>
|
|
|
|
3.12.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \neural_processor.
|
|
Performed a total of 0 changes.
|
|
|
|
3.12.12. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\neural_processor'.
|
|
Computing hashes of 193 cells of `\neural_processor'.
|
|
Finding duplicate cells in `\neural_processor'.
|
|
Removed a total of 0 cells.
|
|
|
|
3.12.13. Executing OPT_DFF pass (perform DFF optimizations).
|
|
|
|
3.12.14. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \neural_processor..
|
|
|
|
3.12.15. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module neural_processor.
|
|
|
|
3.12.16. Finished fast OPT passes. (There is nothing left to do.)
|
|
|
|
3.13. Executing FSM pass (extract and optimize FSM).
|
|
|
|
3.13.1. Executing FSM_DETECT pass (finding FSMs in design).
|
|
Not marking neural_processor.np_state as FSM state register:
|
|
Register is connected to module port.
|
|
Users of register don't seem to benefit from recoding.
|
|
|
|
3.13.2. Executing FSM_EXTRACT pass (extracting FSM from design).
|
|
|
|
3.13.3. Executing FSM_OPT pass (simple optimizations of FSMs).
|
|
|
|
3.13.4. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \neural_processor..
|
|
|
|
3.13.5. Executing FSM_OPT pass (simple optimizations of FSMs).
|
|
|
|
3.13.6. Executing FSM_RECODE pass (re-assigning FSM state encoding).
|
|
|
|
3.13.7. Executing FSM_INFO pass (dumping all available information on FSM cells).
|
|
|
|
3.13.8. Executing FSM_MAP pass (mapping FSMs to basic logic).
|
|
|
|
3.14. Executing OPT pass (performing simple optimizations).
|
|
|
|
3.14.1. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module neural_processor.
|
|
|
|
3.14.2. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\neural_processor'.
|
|
Computing hashes of 193 cells of `\neural_processor'.
|
|
Finding duplicate cells in `\neural_processor'.
|
|
Removed a total of 0 cells.
|
|
|
|
3.14.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \neural_processor..
|
|
Creating internal representation of mux trees.
|
|
Evaluating internal representation of mux trees.
|
|
Analyzing evaluation results.
|
|
Removed 0 multiplexer ports.
|
|
<suppressed ~142 debug messages>
|
|
|
|
3.14.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \neural_processor.
|
|
Performed a total of 0 changes.
|
|
|
|
3.14.5. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\neural_processor'.
|
|
Computing hashes of 193 cells of `\neural_processor'.
|
|
Finding duplicate cells in `\neural_processor'.
|
|
Removed a total of 0 cells.
|
|
|
|
3.14.6. Executing OPT_DFF pass (perform DFF optimizations).
|
|
Adding SRST signal on $procdff$720 ($dff) from module neural_processor (D = $procmux$633_Y, Q = \result_node_id, rval = 16'0000000000000000).
|
|
Adding EN signal on $auto$ff.cc:337:slice$739 ($sdff) from module neural_processor (D = \node_id_reg, Q = \result_node_id).
|
|
Adding SRST signal on $procdff$721 ($dff) from module neural_processor (D = $procmux$608_Y, Q = \np_state, rval = 4'0000).
|
|
Adding EN signal on $auto$ff.cc:337:slice$743 ($sdff) from module neural_processor (D = $procmux$608_Y, Q = \np_state).
|
|
Adding EN signal on $procdff$722 ($dff) from module neural_processor (D = 1'0, Q = \np_error).
|
|
Adding SRST signal on $procdff$723 ($dff) from module neural_processor (D = $procmux$599_Y, Q = \bias_reg, rval = 8'00000000).
|
|
Adding EN signal on $auto$ff.cc:337:slice$758 ($sdff) from module neural_processor (D = \job_bias, Q = \bias_reg).
|
|
Adding SRST signal on $procdff$724 ($dff) from module neural_processor (D = $procmux$585_Y, Q = \activation_reg, rval = 2'01).
|
|
Adding EN signal on $auto$ff.cc:337:slice$762 ($sdff) from module neural_processor (D = \job_activation, Q = \activation_reg).
|
|
Adding SRST signal on $procdff$725 ($dff) from module neural_processor (D = $procmux$571_Y, Q = \node_id_reg, rval = 16'0000000000000000).
|
|
Adding EN signal on $auto$ff.cc:337:slice$766 ($sdff) from module neural_processor (D = \job_node_id, Q = \node_id_reg).
|
|
Adding SRST signal on $procdff$737 ($dff) from module neural_processor (D = \last_tree [1], Q = \last_tree [2], rval = 1'0).
|
|
Adding SRST signal on $procdff$736 ($dff) from module neural_processor (D = \valid_tree [1], Q = \valid_tree [2], rval = 1'0).
|
|
Adding SRST signal on $procdff$726 ($dff) from module neural_processor (D = \valid1, Q = \valid_tree [0], rval = 1'0).
|
|
Adding SRST signal on $procdff$727 ($dff) from module neural_processor (D = \last1, Q = \last_tree [0], rval = 1'0).
|
|
Adding SRST signal on $procdff$732 ($dff) from module neural_processor (D = \valid_tree [0], Q = \valid_tree [1], rval = 1'0).
|
|
Adding SRST signal on $procdff$680 ($dff) from module neural_processor (D = $logic_and$hardware/v2/rtl/neural_processor.v:109$84_Y, Q = \valid0, rval = 1'0).
|
|
Adding SRST signal on $procdff$681 ($dff) from module neural_processor (D = \tile_last, Q = \last0, rval = 1'0).
|
|
Adding EN signal on $procdff$683 ($dff) from module neural_processor (D = \input_data [7:0], Q = \x0[0]).
|
|
Adding EN signal on $procdff$684 ($dff) from module neural_processor (D = \input_data [15:8], Q = \x0[1]).
|
|
Adding EN signal on $procdff$685 ($dff) from module neural_processor (D = \input_data [23:16], Q = \x0[2]).
|
|
Adding EN signal on $procdff$686 ($dff) from module neural_processor (D = \input_data [31:24], Q = \x0[3]).
|
|
Adding EN signal on $procdff$687 ($dff) from module neural_processor (D = \input_data [39:32], Q = \x0[4]).
|
|
Adding EN signal on $procdff$688 ($dff) from module neural_processor (D = \input_data [47:40], Q = \x0[5]).
|
|
Adding EN signal on $procdff$689 ($dff) from module neural_processor (D = \input_data [55:48], Q = \x0[6]).
|
|
Adding EN signal on $procdff$690 ($dff) from module neural_processor (D = \input_data [63:56], Q = \x0[7]).
|
|
Adding EN signal on $procdff$691 ($dff) from module neural_processor (D = \weight_data [7:0], Q = \w0[0]).
|
|
Adding EN signal on $procdff$692 ($dff) from module neural_processor (D = \weight_data [15:8], Q = \w0[1]).
|
|
Adding EN signal on $procdff$693 ($dff) from module neural_processor (D = \weight_data [23:16], Q = \w0[2]).
|
|
Adding EN signal on $procdff$694 ($dff) from module neural_processor (D = \weight_data [31:24], Q = \w0[3]).
|
|
Adding EN signal on $procdff$695 ($dff) from module neural_processor (D = \weight_data [39:32], Q = \w0[4]).
|
|
Adding EN signal on $procdff$696 ($dff) from module neural_processor (D = \weight_data [47:40], Q = \w0[5]).
|
|
Adding EN signal on $procdff$697 ($dff) from module neural_processor (D = \weight_data [55:48], Q = \w0[6]).
|
|
Adding EN signal on $procdff$698 ($dff) from module neural_processor (D = \weight_data [63:56], Q = \w0[7]).
|
|
Adding SRST signal on $procdff$733 ($dff) from module neural_processor (D = \last_tree [0], Q = \last_tree [1], rval = 1'0).
|
|
Adding SRST signal on $procdff$700 ($dff) from module neural_processor (D = \valid0, Q = \valid1, rval = 1'0).
|
|
Adding SRST signal on $procdff$701 ($dff) from module neural_processor (D = \last0, Q = \last1, rval = 1'0).
|
|
Adding EN signal on $procdff$702 ($dff) from module neural_processor (D = { \product_comb[0] [15] \product_comb[0] [15] \product_comb[0] [15] \product_comb[0] [15] \product_comb[0] [15] \product_comb[0] [15] \product_comb[0] [15] \product_comb[0] [15] \product_comb[0] }, Q = \prod1[0]).
|
|
Adding EN signal on $procdff$703 ($dff) from module neural_processor (D = { \product_comb[1] [15] \product_comb[1] [15] \product_comb[1] [15] \product_comb[1] [15] \product_comb[1] [15] \product_comb[1] [15] \product_comb[1] [15] \product_comb[1] [15] \product_comb[1] }, Q = \prod1[1]).
|
|
Adding EN signal on $procdff$704 ($dff) from module neural_processor (D = { \product_comb[2] [15] \product_comb[2] [15] \product_comb[2] [15] \product_comb[2] [15] \product_comb[2] [15] \product_comb[2] [15] \product_comb[2] [15] \product_comb[2] [15] \product_comb[2] }, Q = \prod1[2]).
|
|
Adding EN signal on $procdff$705 ($dff) from module neural_processor (D = { \product_comb[3] [15] \product_comb[3] [15] \product_comb[3] [15] \product_comb[3] [15] \product_comb[3] [15] \product_comb[3] [15] \product_comb[3] [15] \product_comb[3] [15] \product_comb[3] }, Q = \prod1[3]).
|
|
Adding EN signal on $procdff$706 ($dff) from module neural_processor (D = { \product_comb[4] [15] \product_comb[4] [15] \product_comb[4] [15] \product_comb[4] [15] \product_comb[4] [15] \product_comb[4] [15] \product_comb[4] [15] \product_comb[4] [15] \product_comb[4] }, Q = \prod1[4]).
|
|
Adding EN signal on $procdff$707 ($dff) from module neural_processor (D = { \product_comb[5] [15] \product_comb[5] [15] \product_comb[5] [15] \product_comb[5] [15] \product_comb[5] [15] \product_comb[5] [15] \product_comb[5] [15] \product_comb[5] [15] \product_comb[5] }, Q = \prod1[5]).
|
|
Adding EN signal on $procdff$708 ($dff) from module neural_processor (D = { \product_comb[6] [15] \product_comb[6] [15] \product_comb[6] [15] \product_comb[6] [15] \product_comb[6] [15] \product_comb[6] [15] \product_comb[6] [15] \product_comb[6] [15] \product_comb[6] }, Q = \prod1[6]).
|
|
Adding EN signal on $procdff$709 ($dff) from module neural_processor (D = { \product_comb[7] [15] \product_comb[7] [15] \product_comb[7] [15] \product_comb[7] [15] \product_comb[7] [15] \product_comb[7] [15] \product_comb[7] [15] \product_comb[7] [15] \product_comb[7] }, Q = \prod1[7]).
|
|
Adding SRST signal on $procdff$710 ($dff) from module neural_processor (D = $procmux$536_Y, Q = \acc_reg, rval = 24'000000000000000000000000).
|
|
Adding EN signal on $auto$ff.cc:337:slice$872 ($sdff) from module neural_processor (D = $add$hardware/v2/rtl/neural_processor.v:226$91_Y, Q = \acc_reg).
|
|
Adding SRST signal on $procdff$711 ($dff) from module neural_processor (D = \valid_tree [2], Q = \valid5, rval = 1'0).
|
|
Adding SRST signal on $procdff$712 ($dff) from module neural_processor (D = \last_tree [2], Q = \last5, rval = 1'0).
|
|
Adding SRST signal on $procdff$713 ($dff) from module neural_processor (D = \valid5, Q = \valid6, rval = 1'0).
|
|
Adding SRST signal on $procdff$714 ($dff) from module neural_processor (D = \last5, Q = \last6, rval = 1'0).
|
|
Adding EN signal on $procdff$715 ($dff) from module neural_processor (D = $add$hardware/v2/rtl/neural_processor.v:252$93_Y, Q = \final_acc_reg).
|
|
Adding SRST signal on $procdff$716 ($dff) from module neural_processor (D = \last6, Q = \valid7, rval = 1'0).
|
|
Adding EN signal on $procdff$717 ($dff) from module neural_processor (D = $procmux$557_Y, Q = \y7).
|
|
Adding SRST signal on $procdff$718 ($dff) from module neural_processor (D = $procmux$654_Y, Q = \result_valid, rval = 1'0).
|
|
Adding EN signal on $auto$ff.cc:337:slice$883 ($sdff) from module neural_processor (D = $procmux$654_Y, Q = \result_valid).
|
|
Adding SRST signal on $procdff$719 ($dff) from module neural_processor (D = $procmux$644_Y, Q = \result_data, rval = 8'00000000).
|
|
Adding EN signal on $auto$ff.cc:337:slice$893 ($sdff) from module neural_processor (D = \y7, Q = \result_data).
|
|
Setting constant 0-bit at position 0 on $auto$ff.cc:337:slice$757 ($dffe) from module neural_processor.
|
|
|
|
3.14.7. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \neural_processor..
|
|
Removed 79 unused cells and 79 unused wires.
|
|
<suppressed ~80 debug messages>
|
|
|
|
3.14.8. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module neural_processor.
|
|
<suppressed ~2 debug messages>
|
|
|
|
3.14.9. Rerunning OPT passes. (Maybe there is more to do..)
|
|
|
|
3.14.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \neural_processor..
|
|
Creating internal representation of mux trees.
|
|
Evaluating internal representation of mux trees.
|
|
Analyzing evaluation results.
|
|
Removed 0 multiplexer ports.
|
|
<suppressed ~16 debug messages>
|
|
|
|
3.14.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \neural_processor.
|
|
Performed a total of 0 changes.
|
|
|
|
3.14.12. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\neural_processor'.
|
|
Computing hashes of 163 cells of `\neural_processor'.
|
|
Finding duplicate cells in `\neural_processor'.
|
|
Computing hashes of 143 cells of `\neural_processor'.
|
|
Finding duplicate cells in `\neural_processor'.
|
|
Computing hashes of 128 cells of `\neural_processor'.
|
|
Finding duplicate cells in `\neural_processor'.
|
|
<suppressed ~105 debug messages>
|
|
Removed a total of 35 cells.
|
|
|
|
3.14.13. Executing OPT_DFF pass (perform DFF optimizations).
|
|
|
|
3.14.14. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \neural_processor..
|
|
Removed 0 unused cells and 35 unused wires.
|
|
<suppressed ~1 debug messages>
|
|
|
|
3.14.15. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module neural_processor.
|
|
|
|
3.14.16. Rerunning OPT passes. (Maybe there is more to do..)
|
|
|
|
3.14.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \neural_processor..
|
|
Creating internal representation of mux trees.
|
|
Evaluating internal representation of mux trees.
|
|
Analyzing evaluation results.
|
|
Removed 0 multiplexer ports.
|
|
<suppressed ~16 debug messages>
|
|
|
|
3.14.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \neural_processor.
|
|
Performed a total of 0 changes.
|
|
|
|
3.14.19. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\neural_processor'.
|
|
Computing hashes of 128 cells of `\neural_processor'.
|
|
Finding duplicate cells in `\neural_processor'.
|
|
Removed a total of 0 cells.
|
|
|
|
3.14.20. Executing OPT_DFF pass (perform DFF optimizations).
|
|
|
|
3.14.21. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \neural_processor..
|
|
|
|
3.14.22. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module neural_processor.
|
|
|
|
3.14.23. Finished fast OPT passes. (There is nothing left to do.)
|
|
|
|
3.15. Executing WREDUCE pass (reducing word size of cells).
|
|
Removed top 8 bits (of 24) from FF cell neural_processor.$auto$ff.cc:337:slice$871 ($dffe).
|
|
Removed top 8 bits (of 24) from FF cell neural_processor.$auto$ff.cc:337:slice$870 ($dffe).
|
|
Removed top 8 bits (of 24) from FF cell neural_processor.$auto$ff.cc:337:slice$869 ($dffe).
|
|
Removed top 8 bits (of 24) from FF cell neural_processor.$auto$ff.cc:337:slice$868 ($dffe).
|
|
Removed top 8 bits (of 24) from FF cell neural_processor.$auto$ff.cc:337:slice$867 ($dffe).
|
|
Removed top 8 bits (of 24) from FF cell neural_processor.$auto$ff.cc:337:slice$866 ($dffe).
|
|
Removed top 8 bits (of 24) from FF cell neural_processor.$auto$ff.cc:337:slice$865 ($dffe).
|
|
Removed top 8 bits (of 24) from FF cell neural_processor.$auto$ff.cc:337:slice$864 ($dffe).
|
|
Removed top 1 bits (of 2) from port B of cell neural_processor.$auto$opt_dff.cc:320:make_patterns_logic$750 ($ne).
|
|
Removed top 1 bits (of 2) from port B of cell neural_processor.$auto$opt_dff.cc:320:make_patterns_logic$746 ($ne).
|
|
Removed top 16 bits (of 24) from port B of cell neural_processor.$add$hardware/v2/rtl/neural_processor.v:252$93 ($add).
|
|
Converting cell neural_processor.$add$hardware/v2/rtl/neural_processor.v:193$122 ($add) from unsigned to signed.
|
|
Removed top 8 bits (of 24) from port A of cell neural_processor.$add$hardware/v2/rtl/neural_processor.v:193$122 ($add).
|
|
Removed top 8 bits (of 24) from port B of cell neural_processor.$add$hardware/v2/rtl/neural_processor.v:193$122 ($add).
|
|
Removed top 7 bits (of 24) from port Y of cell neural_processor.$add$hardware/v2/rtl/neural_processor.v:193$122 ($add).
|
|
Converting cell neural_processor.$add$hardware/v2/rtl/neural_processor.v:193$124 ($add) from unsigned to signed.
|
|
Removed top 8 bits (of 24) from port A of cell neural_processor.$add$hardware/v2/rtl/neural_processor.v:193$124 ($add).
|
|
Removed top 8 bits (of 24) from port B of cell neural_processor.$add$hardware/v2/rtl/neural_processor.v:193$124 ($add).
|
|
Removed top 7 bits (of 24) from port Y of cell neural_processor.$add$hardware/v2/rtl/neural_processor.v:193$124 ($add).
|
|
Converting cell neural_processor.$add$hardware/v2/rtl/neural_processor.v:193$126 ($add) from unsigned to signed.
|
|
Removed top 8 bits (of 24) from port A of cell neural_processor.$add$hardware/v2/rtl/neural_processor.v:193$126 ($add).
|
|
Removed top 8 bits (of 24) from port B of cell neural_processor.$add$hardware/v2/rtl/neural_processor.v:193$126 ($add).
|
|
Removed top 7 bits (of 24) from port Y of cell neural_processor.$add$hardware/v2/rtl/neural_processor.v:193$126 ($add).
|
|
Converting cell neural_processor.$add$hardware/v2/rtl/neural_processor.v:193$128 ($add) from unsigned to signed.
|
|
Removed top 8 bits (of 24) from port A of cell neural_processor.$add$hardware/v2/rtl/neural_processor.v:193$128 ($add).
|
|
Removed top 8 bits (of 24) from port B of cell neural_processor.$add$hardware/v2/rtl/neural_processor.v:193$128 ($add).
|
|
Removed top 7 bits (of 24) from port Y of cell neural_processor.$add$hardware/v2/rtl/neural_processor.v:193$128 ($add).
|
|
Removed top 1 bits (of 4) from port B of cell neural_processor.$procmux$609_CMP0 ($eq).
|
|
Removed top 1 bits (of 4) from port B of cell neural_processor.$procmux$610_CMP0 ($eq).
|
|
Removed top 2 bits (of 4) from port B of cell neural_processor.$procmux$619_CMP0 ($eq).
|
|
Removed top 3 bits (of 4) from port B of cell neural_processor.$procmux$620_CMP0 ($eq).
|
|
Removed top 1 bits (of 4) from port B of cell neural_processor.$procmux$655_CMP0 ($eq).
|
|
Removed top 2 bits (of 4) from port B of cell neural_processor.$procmux$658_CMP0 ($eq).
|
|
Removed top 7 bits (of 24) from FF cell neural_processor.$procdff$728 ($dff).
|
|
Removed top 7 bits (of 24) from FF cell neural_processor.$procdff$729 ($dff).
|
|
Removed top 7 bits (of 24) from FF cell neural_processor.$procdff$730 ($dff).
|
|
Removed top 7 bits (of 24) from FF cell neural_processor.$procdff$731 ($dff).
|
|
Converting cell neural_processor.$add$hardware/v2/rtl/neural_processor.v:197$131 ($add) from unsigned to signed.
|
|
Removed top 7 bits (of 24) from port A of cell neural_processor.$add$hardware/v2/rtl/neural_processor.v:197$131 ($add).
|
|
Removed top 7 bits (of 24) from port B of cell neural_processor.$add$hardware/v2/rtl/neural_processor.v:197$131 ($add).
|
|
Removed top 6 bits (of 24) from port Y of cell neural_processor.$add$hardware/v2/rtl/neural_processor.v:197$131 ($add).
|
|
Converting cell neural_processor.$add$hardware/v2/rtl/neural_processor.v:197$133 ($add) from unsigned to signed.
|
|
Removed top 7 bits (of 24) from port A of cell neural_processor.$add$hardware/v2/rtl/neural_processor.v:197$133 ($add).
|
|
Removed top 7 bits (of 24) from port B of cell neural_processor.$add$hardware/v2/rtl/neural_processor.v:197$133 ($add).
|
|
Removed top 6 bits (of 24) from port Y of cell neural_processor.$add$hardware/v2/rtl/neural_processor.v:197$133 ($add).
|
|
|
|
3.16. Executing PEEPOPT pass (run peephole optimizers).
|
|
|
|
3.17. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \neural_processor..
|
|
|
|
3.18. Executing SHARE pass (SAT-based resource sharing).
|
|
|
|
3.19. Executing TECHMAP pass (map to technology primitives).
|
|
|
|
3.19.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/cmp2lut.v
|
|
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/cmp2lut.v' to AST representation.
|
|
Generating RTLIL representation for module `\_90_lut_cmp_'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
3.19.2. Continuing TECHMAP pass.
|
|
No more expansions possible.
|
|
<suppressed ~6 debug messages>
|
|
|
|
3.20. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module neural_processor.
|
|
|
|
3.21. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \neural_processor..
|
|
|
|
3.22. Executing TECHMAP pass (map to technology primitives).
|
|
|
|
3.22.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/mul2dsp.v
|
|
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/mul2dsp.v' to AST representation.
|
|
Generating RTLIL representation for module `\_80_mul'.
|
|
Generating RTLIL representation for module `\_90_soft_mul'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
3.22.2. Continuing TECHMAP pass.
|
|
Using template $paramod$cc733e0dbb038034434917c1e0de96998ec4103f\_80_mul for cells of type $mul.
|
|
No more expansions possible.
|
|
<suppressed ~92 debug messages>
|
|
|
|
3.23. Executing TECHMAP pass (map to technology primitives).
|
|
|
|
3.23.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/dsp_map_18x18.v
|
|
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/dsp_map_18x18.v' to AST representation.
|
|
Generating RTLIL representation for module `$__MUL18X18'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
3.23.2. Continuing TECHMAP pass.
|
|
Using template $paramod$ea686d7c43b0ae12a4f0d39aec4e01bcc4449b23$__MUL18X18 for cells of type $__MUL18X18.
|
|
No more expansions possible.
|
|
<suppressed ~30 debug messages>
|
|
|
|
3.24. Executing ALUMACC pass (create $alu and $macc cells).
|
|
Extracting $alu and $macc cells in module neural_processor:
|
|
creating $macc model for $add$hardware/v2/rtl/neural_processor.v:226$91 ($add).
|
|
creating $macc model for $add$hardware/v2/rtl/neural_processor.v:252$93 ($add).
|
|
creating $macc model for $add$hardware/v2/rtl/neural_processor.v:193$122 ($add).
|
|
creating $macc model for $add$hardware/v2/rtl/neural_processor.v:193$124 ($add).
|
|
creating $macc model for $add$hardware/v2/rtl/neural_processor.v:193$126 ($add).
|
|
creating $macc model for $add$hardware/v2/rtl/neural_processor.v:193$128 ($add).
|
|
creating $macc model for $add$hardware/v2/rtl/neural_processor.v:197$131 ($add).
|
|
creating $macc model for $add$hardware/v2/rtl/neural_processor.v:197$133 ($add).
|
|
creating $macc model for $add$hardware/v2/rtl/neural_processor.v:197$136 ($add).
|
|
creating $alu model for $macc $add$hardware/v2/rtl/neural_processor.v:197$136.
|
|
creating $alu model for $macc $add$hardware/v2/rtl/neural_processor.v:197$133.
|
|
creating $alu model for $macc $add$hardware/v2/rtl/neural_processor.v:197$131.
|
|
creating $alu model for $macc $add$hardware/v2/rtl/neural_processor.v:193$128.
|
|
creating $alu model for $macc $add$hardware/v2/rtl/neural_processor.v:193$126.
|
|
creating $alu model for $macc $add$hardware/v2/rtl/neural_processor.v:193$124.
|
|
creating $alu model for $macc $add$hardware/v2/rtl/neural_processor.v:193$122.
|
|
creating $alu model for $macc $add$hardware/v2/rtl/neural_processor.v:252$93.
|
|
creating $alu model for $macc $add$hardware/v2/rtl/neural_processor.v:226$91.
|
|
creating $alu cell for $add$hardware/v2/rtl/neural_processor.v:226$91: $auto$alumacc.cc:548:replace_alu$914
|
|
creating $alu cell for $add$hardware/v2/rtl/neural_processor.v:252$93: $auto$alumacc.cc:548:replace_alu$917
|
|
creating $alu cell for $add$hardware/v2/rtl/neural_processor.v:193$122: $auto$alumacc.cc:548:replace_alu$920
|
|
creating $alu cell for $add$hardware/v2/rtl/neural_processor.v:193$124: $auto$alumacc.cc:548:replace_alu$923
|
|
creating $alu cell for $add$hardware/v2/rtl/neural_processor.v:193$126: $auto$alumacc.cc:548:replace_alu$926
|
|
creating $alu cell for $add$hardware/v2/rtl/neural_processor.v:193$128: $auto$alumacc.cc:548:replace_alu$929
|
|
creating $alu cell for $add$hardware/v2/rtl/neural_processor.v:197$131: $auto$alumacc.cc:548:replace_alu$932
|
|
creating $alu cell for $add$hardware/v2/rtl/neural_processor.v:197$133: $auto$alumacc.cc:548:replace_alu$935
|
|
creating $alu cell for $add$hardware/v2/rtl/neural_processor.v:197$136: $auto$alumacc.cc:548:replace_alu$938
|
|
created 9 $alu and 0 $macc cells.
|
|
|
|
3.25. Executing OPT pass (performing simple optimizations).
|
|
|
|
3.25.1. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module neural_processor.
|
|
|
|
3.25.2. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\neural_processor'.
|
|
Computing hashes of 128 cells of `\neural_processor'.
|
|
Finding duplicate cells in `\neural_processor'.
|
|
Removed a total of 0 cells.
|
|
|
|
3.25.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \neural_processor..
|
|
Creating internal representation of mux trees.
|
|
Evaluating internal representation of mux trees.
|
|
Analyzing evaluation results.
|
|
Removed 0 multiplexer ports.
|
|
<suppressed ~16 debug messages>
|
|
|
|
3.25.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \neural_processor.
|
|
Performed a total of 0 changes.
|
|
|
|
3.25.5. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\neural_processor'.
|
|
Computing hashes of 128 cells of `\neural_processor'.
|
|
Finding duplicate cells in `\neural_processor'.
|
|
Removed a total of 0 cells.
|
|
|
|
3.25.6. Executing OPT_DFF pass (perform DFF optimizations).
|
|
|
|
3.25.7. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \neural_processor..
|
|
Removed 0 unused cells and 64 unused wires.
|
|
<suppressed ~1 debug messages>
|
|
|
|
3.25.8. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module neural_processor.
|
|
|
|
3.25.9. Rerunning OPT passes. (Maybe there is more to do..)
|
|
|
|
3.25.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \neural_processor..
|
|
Creating internal representation of mux trees.
|
|
Evaluating internal representation of mux trees.
|
|
Analyzing evaluation results.
|
|
Removed 0 multiplexer ports.
|
|
<suppressed ~16 debug messages>
|
|
|
|
3.25.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \neural_processor.
|
|
Performed a total of 0 changes.
|
|
|
|
3.25.12. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\neural_processor'.
|
|
Computing hashes of 128 cells of `\neural_processor'.
|
|
Finding duplicate cells in `\neural_processor'.
|
|
Removed a total of 0 cells.
|
|
|
|
3.25.13. Executing OPT_DFF pass (perform DFF optimizations).
|
|
|
|
3.25.14. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \neural_processor..
|
|
|
|
3.25.15. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module neural_processor.
|
|
|
|
3.25.16. Finished fast OPT passes. (There is nothing left to do.)
|
|
|
|
3.26. Executing MEMORY pass.
|
|
|
|
3.26.1. Executing OPT_MEM pass (optimize memories).
|
|
Performed a total of 0 transformations.
|
|
|
|
3.26.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations).
|
|
Performed a total of 0 transformations.
|
|
|
|
3.26.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths).
|
|
|
|
3.26.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs).
|
|
|
|
3.26.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd).
|
|
|
|
3.26.6. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \neural_processor..
|
|
|
|
3.26.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells).
|
|
|
|
3.26.8. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide).
|
|
Performed a total of 0 transformations.
|
|
|
|
3.26.9. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \neural_processor..
|
|
|
|
3.26.10. Executing MEMORY_COLLECT pass (generating $mem cells).
|
|
|
|
3.27. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \neural_processor..
|
|
|
|
3.28. Executing MEMORY_LIBMAP pass (mapping memories to cells).
|
|
|
|
3.29. Executing TECHMAP pass (map to technology primitives).
|
|
|
|
3.29.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/lutrams_map_trellis.v
|
|
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/lutrams_map_trellis.v' to AST representation.
|
|
Generating RTLIL representation for module `$__TRELLIS_DPR16X4_'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
3.29.2. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/brams_map_16kd.v
|
|
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/brams_map_16kd.v' to AST representation.
|
|
Generating RTLIL representation for module `$__DP16KD_'.
|
|
Generating RTLIL representation for module `$__PDPW16KD_'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
3.29.3. Continuing TECHMAP pass.
|
|
No more expansions possible.
|
|
<suppressed ~5 debug messages>
|
|
|
|
3.30. Executing OPT pass (performing simple optimizations).
|
|
|
|
3.30.1. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module neural_processor.
|
|
<suppressed ~8 debug messages>
|
|
|
|
3.30.2. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\neural_processor'.
|
|
Computing hashes of 122 cells of `\neural_processor'.
|
|
Finding duplicate cells in `\neural_processor'.
|
|
Removed a total of 0 cells.
|
|
|
|
3.30.3. Executing OPT_DFF pass (perform DFF optimizations).
|
|
|
|
3.30.4. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \neural_processor..
|
|
Removed 0 unused cells and 6 unused wires.
|
|
<suppressed ~1 debug messages>
|
|
|
|
3.30.5. Finished fast OPT passes.
|
|
|
|
3.31. Executing MEMORY_MAP pass (converting memories to logic and flip-flops).
|
|
|
|
3.32. Executing OPT pass (performing simple optimizations).
|
|
|
|
3.32.1. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module neural_processor.
|
|
|
|
3.32.2. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\neural_processor'.
|
|
Computing hashes of 122 cells of `\neural_processor'.
|
|
Finding duplicate cells in `\neural_processor'.
|
|
Removed a total of 0 cells.
|
|
|
|
3.32.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \neural_processor..
|
|
Creating internal representation of mux trees.
|
|
Evaluating internal representation of mux trees.
|
|
Analyzing evaluation results.
|
|
Removed 0 multiplexer ports.
|
|
<suppressed ~10 debug messages>
|
|
|
|
3.32.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \neural_processor.
|
|
Consolidated identical input bits for $pmux cell $procmux$608:
|
|
Old ports: A=4'0110, B=24'000100100011010001010000, Y=$procmux$608_Y
|
|
New ports: A=3'110, B=18'001010011100101000, Y=$procmux$608_Y [2:0]
|
|
New connections: $procmux$608_Y [3] = 1'0
|
|
Consolidated identical input bits for $mux cell $ternary$hardware/v2/rtl/neural_processor.v:264$101:
|
|
Old ports: A=8'01111111, B=8'10000000, Y=$ternary$hardware/v2/rtl/neural_processor.v:264$101_Y
|
|
New ports: A=2'01, B=2'10, Y={ $ternary$hardware/v2/rtl/neural_processor.v:264$101_Y [7] $ternary$hardware/v2/rtl/neural_processor.v:264$101_Y [0] }
|
|
New connections: $ternary$hardware/v2/rtl/neural_processor.v:264$101_Y [6:1] = { $ternary$hardware/v2/rtl/neural_processor.v:264$101_Y [0] $ternary$hardware/v2/rtl/neural_processor.v:264$101_Y [0] $ternary$hardware/v2/rtl/neural_processor.v:264$101_Y [0] $ternary$hardware/v2/rtl/neural_processor.v:264$101_Y [0] $ternary$hardware/v2/rtl/neural_processor.v:264$101_Y [0] $ternary$hardware/v2/rtl/neural_processor.v:264$101_Y [0] }
|
|
Optimizing cells in module \neural_processor.
|
|
Performed a total of 2 changes.
|
|
|
|
3.32.5. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\neural_processor'.
|
|
Computing hashes of 122 cells of `\neural_processor'.
|
|
Finding duplicate cells in `\neural_processor'.
|
|
Removed a total of 0 cells.
|
|
|
|
3.32.6. Executing OPT_DFF pass (perform DFF optimizations).
|
|
|
|
3.32.7. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \neural_processor..
|
|
|
|
3.32.8. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module neural_processor.
|
|
|
|
3.32.9. Rerunning OPT passes. (Maybe there is more to do..)
|
|
|
|
3.32.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \neural_processor..
|
|
Creating internal representation of mux trees.
|
|
Evaluating internal representation of mux trees.
|
|
Analyzing evaluation results.
|
|
Removed 0 multiplexer ports.
|
|
<suppressed ~10 debug messages>
|
|
|
|
3.32.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \neural_processor.
|
|
Performed a total of 0 changes.
|
|
|
|
3.32.12. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\neural_processor'.
|
|
Computing hashes of 122 cells of `\neural_processor'.
|
|
Finding duplicate cells in `\neural_processor'.
|
|
Removed a total of 0 cells.
|
|
|
|
3.32.13. Executing OPT_DFF pass (perform DFF optimizations).
|
|
Setting constant 0-bit at position 3 on $auto$ff.cc:337:slice$744 ($sdffe) from module neural_processor.
|
|
|
|
3.32.14. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \neural_processor..
|
|
|
|
3.32.15. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module neural_processor.
|
|
<suppressed ~1 debug messages>
|
|
|
|
3.32.16. Rerunning OPT passes. (Maybe there is more to do..)
|
|
|
|
3.32.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \neural_processor..
|
|
Creating internal representation of mux trees.
|
|
Evaluating internal representation of mux trees.
|
|
Analyzing evaluation results.
|
|
Removed 0 multiplexer ports.
|
|
<suppressed ~10 debug messages>
|
|
|
|
3.32.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \neural_processor.
|
|
Performed a total of 0 changes.
|
|
|
|
3.32.19. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\neural_processor'.
|
|
Computing hashes of 122 cells of `\neural_processor'.
|
|
Finding duplicate cells in `\neural_processor'.
|
|
Removed a total of 0 cells.
|
|
|
|
3.32.20. Executing OPT_DFF pass (perform DFF optimizations).
|
|
|
|
3.32.21. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \neural_processor..
|
|
|
|
3.32.22. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module neural_processor.
|
|
|
|
3.32.23. Finished fast OPT passes. (There is nothing left to do.)
|
|
|
|
3.33. Executing TECHMAP pass (map to technology primitives).
|
|
|
|
3.33.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/techmap.v
|
|
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/techmap.v' to AST representation.
|
|
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
|
|
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
|
|
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
|
|
Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
|
|
Generating RTLIL representation for module `\_90_simplemap_various'.
|
|
Generating RTLIL representation for module `\_90_simplemap_registers'.
|
|
Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
|
|
Generating RTLIL representation for module `\_90_shift_shiftx'.
|
|
Generating RTLIL representation for module `\_90_fa'.
|
|
Generating RTLIL representation for module `\_90_lcu_brent_kung'.
|
|
Generating RTLIL representation for module `\_90_alu'.
|
|
Generating RTLIL representation for module `\_90_macc'.
|
|
Generating RTLIL representation for module `\_90_alumacc'.
|
|
Generating RTLIL representation for module `$__div_mod_u'.
|
|
Generating RTLIL representation for module `$__div_mod_trunc'.
|
|
Generating RTLIL representation for module `\_90_div'.
|
|
Generating RTLIL representation for module `\_90_mod'.
|
|
Generating RTLIL representation for module `$__div_mod_floor'.
|
|
Generating RTLIL representation for module `\_90_divfloor'.
|
|
Generating RTLIL representation for module `\_90_modfloor'.
|
|
Generating RTLIL representation for module `\_90_pow'.
|
|
Generating RTLIL representation for module `\_90_demux'.
|
|
Generating RTLIL representation for module `\_90_lut'.
|
|
Generating RTLIL representation for module `$connect'.
|
|
Generating RTLIL representation for module `$input_port'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
3.33.2. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v
|
|
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v' to AST representation.
|
|
Generating RTLIL representation for module `\_80_ccu2c_alu'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
3.33.3. Continuing TECHMAP pass.
|
|
Using extmapper simplemap for cells of type $sdffe.
|
|
Using template $paramod$59c4d9a723a469db99eee461ca4fdd9fae171b7b\_80_ccu2c_alu for cells of type $alu.
|
|
Using template $paramod$5e21cfa2ff6d644e10a0fc1dcdb22e5eb183bcd3\_80_ccu2c_alu for cells of type $alu.
|
|
Using template $paramod$2470b7ea32c975a55c3ab8b283381b72d09e16d3\_80_ccu2c_alu for cells of type $alu.
|
|
Using template $paramod$ef1d37f0fdd78e5767d894c01dbc000728b00267\_80_ccu2c_alu for cells of type $alu.
|
|
Using extmapper simplemap for cells of type $reduce_and.
|
|
Using extmapper simplemap for cells of type $reduce_bool.
|
|
Using extmapper simplemap for cells of type $dffe.
|
|
Using extmapper simplemap for cells of type $sdff.
|
|
Using extmapper simplemap for cells of type $reduce_or.
|
|
Using extmapper simplemap for cells of type $not.
|
|
Using extmapper simplemap for cells of type $ne.
|
|
Using extmapper simplemap for cells of type $logic_and.
|
|
Using extmapper simplemap for cells of type $or.
|
|
Using extmapper simplemap for cells of type $mux.
|
|
Using extmapper simplemap for cells of type $logic_or.
|
|
Using extmapper simplemap for cells of type $logic_not.
|
|
Using extmapper simplemap for cells of type $eq.
|
|
Using extmapper simplemap for cells of type $pmux.
|
|
Using extmapper simplemap for cells of type $dff.
|
|
Using extmapper simplemap for cells of type $xor.
|
|
Using extmapper simplemap for cells of type $pos.
|
|
No more expansions possible.
|
|
<suppressed ~680 debug messages>
|
|
|
|
3.34. Executing OPT pass (performing simple optimizations).
|
|
|
|
3.34.1. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module neural_processor.
|
|
<suppressed ~277 debug messages>
|
|
|
|
3.34.2. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\neural_processor'.
|
|
Computing hashes of 1480 cells of `\neural_processor'.
|
|
Finding duplicate cells in `\neural_processor'.
|
|
Computing hashes of 1448 cells of `\neural_processor'.
|
|
Finding duplicate cells in `\neural_processor'.
|
|
Computing hashes of 1430 cells of `\neural_processor'.
|
|
Finding duplicate cells in `\neural_processor'.
|
|
<suppressed ~150 debug messages>
|
|
Removed a total of 50 cells.
|
|
|
|
3.34.3. Executing OPT_DFF pass (perform DFF optimizations).
|
|
|
|
3.34.4. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \neural_processor..
|
|
Removed 668 unused cells and 609 unused wires.
|
|
<suppressed ~669 debug messages>
|
|
|
|
3.34.5. Finished fast OPT passes.
|
|
|
|
3.35. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \neural_processor..
|
|
|
|
3.36. Executing DFFLEGALIZE pass (convert FFs to types supported by the target).
|
|
|
|
3.37. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\neural_processor'.
|
|
Computing hashes of 762 cells of `\neural_processor'.
|
|
Finding duplicate cells in `\neural_processor'.
|
|
Removed a total of 0 cells.
|
|
|
|
3.38. Executing TECHMAP pass (map to technology primitives).
|
|
|
|
3.38.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v
|
|
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v' to AST representation.
|
|
Generating RTLIL representation for module `$_DFF_N_'.
|
|
Generating RTLIL representation for module `$_DFF_P_'.
|
|
Generating RTLIL representation for module `$_DFFE_NN_'.
|
|
Generating RTLIL representation for module `$_DFFE_PN_'.
|
|
Generating RTLIL representation for module `$_DFFE_NP_'.
|
|
Generating RTLIL representation for module `$_DFFE_PP_'.
|
|
Generating RTLIL representation for module `$_DFF_NP0_'.
|
|
Generating RTLIL representation for module `$_DFF_NP1_'.
|
|
Generating RTLIL representation for module `$_DFF_PP0_'.
|
|
Generating RTLIL representation for module `$_DFF_PP1_'.
|
|
Generating RTLIL representation for module `$_SDFF_NP0_'.
|
|
Generating RTLIL representation for module `$_SDFF_NP1_'.
|
|
Generating RTLIL representation for module `$_SDFF_PP0_'.
|
|
Generating RTLIL representation for module `$_SDFF_PP1_'.
|
|
Generating RTLIL representation for module `$_DFFE_NP0P_'.
|
|
Generating RTLIL representation for module `$_DFFE_NP1P_'.
|
|
Generating RTLIL representation for module `$_DFFE_PP0P_'.
|
|
Generating RTLIL representation for module `$_DFFE_PP1P_'.
|
|
Generating RTLIL representation for module `$_DFFE_NP0N_'.
|
|
Generating RTLIL representation for module `$_DFFE_NP1N_'.
|
|
Generating RTLIL representation for module `$_DFFE_PP0N_'.
|
|
Generating RTLIL representation for module `$_DFFE_PP1N_'.
|
|
Generating RTLIL representation for module `$_SDFFE_NP0P_'.
|
|
Generating RTLIL representation for module `$_SDFFE_NP1P_'.
|
|
Generating RTLIL representation for module `$_SDFFE_PP0P_'.
|
|
Generating RTLIL representation for module `$_SDFFE_PP1P_'.
|
|
Generating RTLIL representation for module `$_SDFFE_NP0N_'.
|
|
Generating RTLIL representation for module `$_SDFFE_NP1N_'.
|
|
Generating RTLIL representation for module `$_SDFFE_PP0N_'.
|
|
Generating RTLIL representation for module `$_SDFFE_PP1N_'.
|
|
Generating RTLIL representation for module `$_ALDFF_NP_'.
|
|
Generating RTLIL representation for module `$_ALDFF_PP_'.
|
|
Generating RTLIL representation for module `$_ALDFFE_NPN_'.
|
|
Generating RTLIL representation for module `$_ALDFFE_NPP_'.
|
|
Generating RTLIL representation for module `$_ALDFFE_PPN_'.
|
|
Generating RTLIL representation for module `$_ALDFFE_PPP_'.
|
|
Generating RTLIL representation for module `\FD1P3AX'.
|
|
Generating RTLIL representation for module `\FD1P3AY'.
|
|
Generating RTLIL representation for module `\FD1P3BX'.
|
|
Generating RTLIL representation for module `\FD1P3DX'.
|
|
Generating RTLIL representation for module `\FD1P3IX'.
|
|
Generating RTLIL representation for module `\FD1P3JX'.
|
|
Generating RTLIL representation for module `\FD1S3AX'.
|
|
Generating RTLIL representation for module `\FD1S3AY'.
|
|
Generating RTLIL representation for module `\FD1S3BX'.
|
|
Generating RTLIL representation for module `\FD1S3DX'.
|
|
Generating RTLIL representation for module `\FD1S3IX'.
|
|
Generating RTLIL representation for module `\FD1S3JX'.
|
|
Generating RTLIL representation for module `\IFS1P3BX'.
|
|
Generating RTLIL representation for module `\IFS1P3DX'.
|
|
Generating RTLIL representation for module `\IFS1P3IX'.
|
|
Generating RTLIL representation for module `\IFS1P3JX'.
|
|
Generating RTLIL representation for module `\OFS1P3BX'.
|
|
Generating RTLIL representation for module `\OFS1P3DX'.
|
|
Generating RTLIL representation for module `\OFS1P3IX'.
|
|
Generating RTLIL representation for module `\OFS1P3JX'.
|
|
Generating RTLIL representation for module `\IB'.
|
|
Generating RTLIL representation for module `\IBPU'.
|
|
Generating RTLIL representation for module `\IBPD'.
|
|
Generating RTLIL representation for module `\OB'.
|
|
Generating RTLIL representation for module `\OBZ'.
|
|
Generating RTLIL representation for module `\OBZPU'.
|
|
Generating RTLIL representation for module `\OBZPD'.
|
|
Generating RTLIL representation for module `\OBCO'.
|
|
Generating RTLIL representation for module `\BB'.
|
|
Generating RTLIL representation for module `\BBPU'.
|
|
Generating RTLIL representation for module `\BBPD'.
|
|
Generating RTLIL representation for module `\ILVDS'.
|
|
Generating RTLIL representation for module `\OLVDS'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
3.38.2. Continuing TECHMAP pass.
|
|
Using template $paramod$_DFF_P_\_TECHMAP_WIREINIT_Q_=1'x for cells of type $_DFF_P_.
|
|
Using template $_SDFFE_PP0P_ for cells of type $_SDFFE_PP0P_.
|
|
Using template $_SDFFE_PP1P_ for cells of type $_SDFFE_PP1P_.
|
|
Using template $_SDFF_PP0_ for cells of type $_SDFF_PP0_.
|
|
Using template $paramod$_DFFE_PP_\_TECHMAP_WIREINIT_Q_=1'x for cells of type $_DFFE_PP_.
|
|
Using template $paramod$_DFFE_PN_\_TECHMAP_WIREINIT_Q_=1'x for cells of type $_DFFE_PN_.
|
|
No more expansions possible.
|
|
<suppressed ~613 debug messages>
|
|
|
|
3.39. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module neural_processor.
|
|
|
|
3.40. Executing SIMPLEMAP pass (map simple cells to gate primitives).
|
|
|
|
3.41. Executing LATTICE_GSR pass (implement FF init values).
|
|
Handling GSR in neural_processor.
|
|
|
|
3.42. Executing ATTRMVCP pass (move or copy attributes).
|
|
|
|
3.43. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \neural_processor..
|
|
Removed 0 unused cells and 2495 unused wires.
|
|
<suppressed ~1 debug messages>
|
|
|
|
3.44. Executing CHECK pass (checking for obvious problems).
|
|
Checking module neural_processor...
|
|
Found and reported 0 problems.
|
|
|
|
3.45. Executing TECHMAP pass (map to technology primitives).
|
|
|
|
3.45.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/latches_map.v
|
|
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/latches_map.v' to AST representation.
|
|
Generating RTLIL representation for module `$_DLATCH_N_'.
|
|
Generating RTLIL representation for module `$_DLATCH_P_'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
3.45.2. Continuing TECHMAP pass.
|
|
No more expansions possible.
|
|
<suppressed ~4 debug messages>
|
|
|
|
3.46. Executing ABC9 pass.
|
|
|
|
3.46.1. Executing ABC9_OPS pass (helper functions for ABC9).
|
|
|
|
3.46.2. Executing ABC9_OPS pass (helper functions for ABC9).
|
|
|
|
3.46.3. Executing SCC pass (detecting logic loops).
|
|
Found 0 SCCs in module neural_processor.
|
|
Found 0 SCCs.
|
|
|
|
3.46.4. Executing ABC9_OPS pass (helper functions for ABC9).
|
|
|
|
3.46.5. Executing TECHMAP pass (map to technology primitives).
|
|
|
|
3.46.5.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/techmap.v
|
|
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/techmap.v' to AST representation.
|
|
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
|
|
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
|
|
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
|
|
Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
|
|
Generating RTLIL representation for module `\_90_simplemap_various'.
|
|
Generating RTLIL representation for module `\_90_simplemap_registers'.
|
|
Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
|
|
Generating RTLIL representation for module `\_90_shift_shiftx'.
|
|
Generating RTLIL representation for module `\_90_fa'.
|
|
Generating RTLIL representation for module `\_90_lcu_brent_kung'.
|
|
Generating RTLIL representation for module `\_90_alu'.
|
|
Generating RTLIL representation for module `\_90_macc'.
|
|
Generating RTLIL representation for module `\_90_alumacc'.
|
|
Generating RTLIL representation for module `$__div_mod_u'.
|
|
Generating RTLIL representation for module `$__div_mod_trunc'.
|
|
Generating RTLIL representation for module `\_90_div'.
|
|
Generating RTLIL representation for module `\_90_mod'.
|
|
Generating RTLIL representation for module `$__div_mod_floor'.
|
|
Generating RTLIL representation for module `\_90_divfloor'.
|
|
Generating RTLIL representation for module `\_90_modfloor'.
|
|
Generating RTLIL representation for module `\_90_pow'.
|
|
Generating RTLIL representation for module `\_90_demux'.
|
|
Generating RTLIL representation for module `\_90_lut'.
|
|
Generating RTLIL representation for module `$connect'.
|
|
Generating RTLIL representation for module `$input_port'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
3.46.5.2. Continuing TECHMAP pass.
|
|
No more expansions possible.
|
|
<suppressed ~166 debug messages>
|
|
|
|
3.46.6. Executing OPT pass (performing simple optimizations).
|
|
|
|
3.46.6.1. Executing OPT_EXPR pass (perform const folding).
|
|
|
|
3.46.6.2. Executing OPT_MERGE pass (detect identical cells).
|
|
Removed a total of 0 cells.
|
|
|
|
3.46.6.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Removed 0 multiplexer ports.
|
|
|
|
3.46.6.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Performed a total of 0 changes.
|
|
|
|
3.46.6.5. Executing OPT_MERGE pass (detect identical cells).
|
|
Removed a total of 0 cells.
|
|
|
|
3.46.6.6. Executing OPT_DFF pass (perform DFF optimizations).
|
|
|
|
3.46.6.7. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
|
|
3.46.6.8. Executing OPT_EXPR pass (perform const folding).
|
|
|
|
3.46.6.9. Finished fast OPT passes. (There is nothing left to do.)
|
|
|
|
3.46.7. Executing TECHMAP pass (map to technology primitives).
|
|
|
|
3.46.7.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/abc9_map.v
|
|
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/abc9_map.v' to AST representation.
|
|
Successfully finished Verilog frontend.
|
|
|
|
3.46.7.2. Continuing TECHMAP pass.
|
|
No more expansions possible.
|
|
<suppressed ~2 debug messages>
|
|
|
|
3.46.8. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/abc9_model.v
|
|
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/abc9_model.v' to AST representation.
|
|
Generating RTLIL representation for module `$__ABC9_DELAY'.
|
|
Generating RTLIL representation for module `$__ABC9_SCC_BREAKER'.
|
|
Generating RTLIL representation for module `$__DFF_N__$abc9_flop'.
|
|
Generating RTLIL representation for module `$__DFF_P__$abc9_flop'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
3.46.9. Executing ABC9_OPS pass (helper functions for ABC9).
|
|
<suppressed ~2 debug messages>
|
|
|
|
3.46.10. Executing ABC9_OPS pass (helper functions for ABC9).
|
|
|
|
3.46.11. Executing ABC9_OPS pass (helper functions for ABC9).
|
|
<suppressed ~2 debug messages>
|
|
|
|
3.46.12. Executing TECHMAP pass (map to technology primitives).
|
|
|
|
3.46.12.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/techmap.v
|
|
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/techmap.v' to AST representation.
|
|
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
|
|
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
|
|
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
|
|
Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
|
|
Generating RTLIL representation for module `\_90_simplemap_various'.
|
|
Generating RTLIL representation for module `\_90_simplemap_registers'.
|
|
Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
|
|
Generating RTLIL representation for module `\_90_shift_shiftx'.
|
|
Generating RTLIL representation for module `\_90_fa'.
|
|
Generating RTLIL representation for module `\_90_lcu_brent_kung'.
|
|
Generating RTLIL representation for module `\_90_alu'.
|
|
Generating RTLIL representation for module `\_90_macc'.
|
|
Generating RTLIL representation for module `\_90_alumacc'.
|
|
Generating RTLIL representation for module `$__div_mod_u'.
|
|
Generating RTLIL representation for module `$__div_mod_trunc'.
|
|
Generating RTLIL representation for module `\_90_div'.
|
|
Generating RTLIL representation for module `\_90_mod'.
|
|
Generating RTLIL representation for module `$__div_mod_floor'.
|
|
Generating RTLIL representation for module `\_90_divfloor'.
|
|
Generating RTLIL representation for module `\_90_modfloor'.
|
|
Generating RTLIL representation for module `\_90_pow'.
|
|
Generating RTLIL representation for module `\_90_demux'.
|
|
Generating RTLIL representation for module `\_90_lut'.
|
|
Generating RTLIL representation for module `$connect'.
|
|
Generating RTLIL representation for module `$input_port'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
3.46.12.2. Continuing TECHMAP pass.
|
|
Using template $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C for cells of type $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C.
|
|
Using extmapper simplemap for cells of type $or.
|
|
Using extmapper simplemap for cells of type $and.
|
|
Using extmapper simplemap for cells of type $not.
|
|
Using extmapper simplemap for cells of type $xor.
|
|
Using template $paramod\LUT2\INIT=4'1010 for cells of type LUT2.
|
|
Using template $paramod\LUT4\INIT=16'1001011010101010 for cells of type LUT4.
|
|
Using extmapper simplemap for cells of type $mux.
|
|
No more expansions possible.
|
|
<suppressed ~205 debug messages>
|
|
|
|
3.46.13. Executing OPT pass (performing simple optimizations).
|
|
|
|
3.46.13.1. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module neural_processor.
|
|
<suppressed ~18 debug messages>
|
|
|
|
3.46.13.2. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\neural_processor'.
|
|
Computing hashes of 59 cells of `\neural_processor'.
|
|
Finding duplicate cells in `\neural_processor'.
|
|
Computing hashes of 57 cells of `\neural_processor'.
|
|
Finding duplicate cells in `\neural_processor'.
|
|
<suppressed ~6 debug messages>
|
|
Removed a total of 2 cells.
|
|
|
|
3.46.13.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \neural_processor..
|
|
Creating internal representation of mux trees.
|
|
No muxes found in this module.
|
|
Removed 0 multiplexer ports.
|
|
|
|
3.46.13.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \neural_processor.
|
|
Performed a total of 0 changes.
|
|
|
|
3.46.13.5. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\neural_processor'.
|
|
Computing hashes of 57 cells of `\neural_processor'.
|
|
Finding duplicate cells in `\neural_processor'.
|
|
Removed a total of 0 cells.
|
|
|
|
3.46.13.6. Executing OPT_DFF pass (perform DFF optimizations).
|
|
|
|
3.46.13.7. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \neural_processor..
|
|
Removed 0 unused cells and 55 unused wires.
|
|
<suppressed ~1 debug messages>
|
|
|
|
3.46.13.8. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module neural_processor.
|
|
|
|
3.46.13.9. Rerunning OPT passes. (Maybe there is more to do..)
|
|
|
|
3.46.13.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \neural_processor..
|
|
Creating internal representation of mux trees.
|
|
No muxes found in this module.
|
|
Removed 0 multiplexer ports.
|
|
|
|
3.46.13.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \neural_processor.
|
|
Performed a total of 0 changes.
|
|
|
|
3.46.13.12. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\neural_processor'.
|
|
Computing hashes of 57 cells of `\neural_processor'.
|
|
Finding duplicate cells in `\neural_processor'.
|
|
Removed a total of 0 cells.
|
|
|
|
3.46.13.13. Executing OPT_DFF pass (perform DFF optimizations).
|
|
|
|
3.46.13.14. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \neural_processor..
|
|
|
|
3.46.13.15. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module neural_processor.
|
|
|
|
3.46.13.16. Finished fast OPT passes. (There is nothing left to do.)
|
|
|
|
3.46.14. Executing AIGMAP pass (map logic to AIG).
|
|
Module neural_processor: replaced 18 cells with 120 new cells, skipped 39 cells.
|
|
replaced 3 cell types:
|
|
14 $_MUX_
|
|
2 $_OR_
|
|
2 $_XOR_
|
|
not replaced 3 cell types:
|
|
4 $_AND_
|
|
4 $_NOT_
|
|
31 $specify2
|
|
|
|
3.46.15. Executing AIGMAP pass (map logic to AIG).
|
|
Module neural_processor: replaced 110 cells with 545 new cells, skipped 652 cells.
|
|
replaced 2 cell types:
|
|
35 $_MUX_
|
|
75 $_OR_
|
|
not replaced 5 cell types:
|
|
30 $_AND_
|
|
15 $_NOT_
|
|
509 TRELLIS_FF
|
|
8 MULT18X18D
|
|
90 $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C
|
|
|
|
3.46.15.1. Executing ABC9_OPS pass (helper functions for ABC9).
|
|
|
|
3.46.15.2. Executing ABC9_OPS pass (helper functions for ABC9).
|
|
|
|
3.46.15.3. Executing XAIGER backend.
|
|
<suppressed ~11 debug messages>
|
|
Extracted 210 AND gates and 1715 wires from module `neural_processor' to a netlist network with 797 inputs and 521 outputs.
|
|
|
|
3.46.15.4. Executing ABC9_EXE pass (technology mapping using ABC9).
|
|
|
|
3.46.15.5. Executing ABC9.
|
|
Running ABC command: "<yosys-exe-dir>/yosys-abc" -s -f <abc-temp-dir>/abc.script 2>&1
|
|
ABC: ======== ABC command line "source <abc-temp-dir>/abc.script"
|
|
ABC: + read_lut <abc-temp-dir>/input.lut
|
|
ABC: + read_box <abc-temp-dir>/input.box
|
|
ABC: + &read <abc-temp-dir>/input.xaig
|
|
ABC: + &ps
|
|
ABC: <abc-temp-dir>/input : i/o = 797/ 521 and = 174 lev = 12 (0.12) mem = 0.04 MB box = 90 bb = 0
|
|
ABC: + &scorr
|
|
ABC: Warning: The network is combinational.
|
|
ABC: + &sweep
|
|
ABC: + &dc2
|
|
ABC: + &dch -f -r
|
|
ABC: + &ps
|
|
ABC: <abc-temp-dir>/input : i/o = 797/ 521 and = 202 lev = 10 (0.09) mem = 0.04 MB ch = 22 box = 88 bb = 0
|
|
ABC: cst = 0 cls = 22 lit = 22 unused = 1219 proof = 0
|
|
ABC: + &if -W 300 -v
|
|
ABC: K = 7. Memory (bytes): Truth = 0. Cut = 76. Obj = 156. Set = 780. CutMin = no
|
|
ABC: Node = 202. Ch = 22. Total mem = 0.42 MB. Peak cut mem = 0.02 MB.
|
|
ABC: P: Del = 2201.00. Ar = 161.0. Edge = 219. Cut = 1846. T = 0.00 sec
|
|
ABC: P: Del = 2180.00. Ar = 160.0. Edge = 215. Cut = 1698. T = 0.00 sec
|
|
ABC: P: Del = 2180.00. Ar = 114.0. Edge = 188. Cut = 3153. T = 0.00 sec
|
|
ABC: F: Del = 2180.00. Ar = 104.0. Edge = 188. Cut = 2063. T = 0.00 sec
|
|
ABC: A: Del = 2180.00. Ar = 103.0. Edge = 182. Cut = 1829. T = 0.00 sec
|
|
ABC: A: Del = 2180.00. Ar = 103.0. Edge = 180. Cut = 1964. T = 0.00 sec
|
|
ABC: Total time = 0.00 sec
|
|
ABC: + &write -n <abc-temp-dir>/output.aig
|
|
ABC: + &mfs
|
|
ABC: + &ps -l
|
|
ABC: <abc-temp-dir>/input : i/o = 797/ 521 and = 115 lev = 9 (0.09) mem = 0.04 MB box = 88 bb = 0
|
|
ABC: Mapping (K=6) : lut = 38 edge = 139 lev = 4 (0.04) levB = 12 mem = 0.01 MB
|
|
ABC: LUT = 38 : 2=6 15.8 % 3=9 23.7 % 4=17 44.7 % 5=4 10.5 % 6=2 5.3 % Ave = 3.66
|
|
ABC: + &write -n <abc-temp-dir>/output.aig
|
|
ABC: + &verify
|
|
ABC: Networks are equivalent. Time = 0.01 sec
|
|
ABC: + time
|
|
ABC: elapse: 0.02 seconds, total: 0.02 seconds
|
|
|
|
3.46.15.6. Executing AIGER frontend.
|
|
<suppressed ~10 debug messages>
|
|
Removed 156 unused cells and 2203 unused wires.
|
|
|
|
3.46.15.7. Executing ABC_OPS_REINTEGRATE pass (reintegrate ABC mapped design into module).
|
|
ABC RESULTS: $lut cells: 39
|
|
ABC RESULTS: $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C cells: 88
|
|
ABC RESULTS: input signals: 32
|
|
ABC RESULTS: output signals: 64
|
|
<suppressed ~2638 debug messages>
|
|
Removing temp directory.
|
|
|
|
3.46.16. Executing TECHMAP pass (map to technology primitives).
|
|
|
|
3.46.16.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/abc9_unmap.v
|
|
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/abc9_unmap.v' to AST representation.
|
|
Generating RTLIL representation for module `$__DFF_x__$abc9_flop'.
|
|
Generating RTLIL representation for module `$__ABC9_SCC_BREAKER'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
3.46.16.2. Continuing TECHMAP pass.
|
|
Using template $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C for cells of type $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C.
|
|
No more expansions possible.
|
|
<suppressed ~94 debug messages>
|
|
Removed 3 unused cells and 3080 unused wires.
|
|
|
|
3.47. Executing TECHMAP pass (map to technology primitives).
|
|
|
|
3.47.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v
|
|
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v' to AST representation.
|
|
Generating RTLIL representation for module `$_DFF_N_'.
|
|
Generating RTLIL representation for module `$_DFF_P_'.
|
|
Generating RTLIL representation for module `$_DFFE_NN_'.
|
|
Generating RTLIL representation for module `$_DFFE_PN_'.
|
|
Generating RTLIL representation for module `$_DFFE_NP_'.
|
|
Generating RTLIL representation for module `$_DFFE_PP_'.
|
|
Generating RTLIL representation for module `$_DFF_NP0_'.
|
|
Generating RTLIL representation for module `$_DFF_NP1_'.
|
|
Generating RTLIL representation for module `$_DFF_PP0_'.
|
|
Generating RTLIL representation for module `$_DFF_PP1_'.
|
|
Generating RTLIL representation for module `$_SDFF_NP0_'.
|
|
Generating RTLIL representation for module `$_SDFF_NP1_'.
|
|
Generating RTLIL representation for module `$_SDFF_PP0_'.
|
|
Generating RTLIL representation for module `$_SDFF_PP1_'.
|
|
Generating RTLIL representation for module `$_DFFE_NP0P_'.
|
|
Generating RTLIL representation for module `$_DFFE_NP1P_'.
|
|
Generating RTLIL representation for module `$_DFFE_PP0P_'.
|
|
Generating RTLIL representation for module `$_DFFE_PP1P_'.
|
|
Generating RTLIL representation for module `$_DFFE_NP0N_'.
|
|
Generating RTLIL representation for module `$_DFFE_NP1N_'.
|
|
Generating RTLIL representation for module `$_DFFE_PP0N_'.
|
|
Generating RTLIL representation for module `$_DFFE_PP1N_'.
|
|
Generating RTLIL representation for module `$_SDFFE_NP0P_'.
|
|
Generating RTLIL representation for module `$_SDFFE_NP1P_'.
|
|
Generating RTLIL representation for module `$_SDFFE_PP0P_'.
|
|
Generating RTLIL representation for module `$_SDFFE_PP1P_'.
|
|
Generating RTLIL representation for module `$_SDFFE_NP0N_'.
|
|
Generating RTLIL representation for module `$_SDFFE_NP1N_'.
|
|
Generating RTLIL representation for module `$_SDFFE_PP0N_'.
|
|
Generating RTLIL representation for module `$_SDFFE_PP1N_'.
|
|
Generating RTLIL representation for module `$_ALDFF_NP_'.
|
|
Generating RTLIL representation for module `$_ALDFF_PP_'.
|
|
Generating RTLIL representation for module `$_ALDFFE_NPN_'.
|
|
Generating RTLIL representation for module `$_ALDFFE_NPP_'.
|
|
Generating RTLIL representation for module `$_ALDFFE_PPN_'.
|
|
Generating RTLIL representation for module `$_ALDFFE_PPP_'.
|
|
Generating RTLIL representation for module `\FD1P3AX'.
|
|
Generating RTLIL representation for module `\FD1P3AY'.
|
|
Generating RTLIL representation for module `\FD1P3BX'.
|
|
Generating RTLIL representation for module `\FD1P3DX'.
|
|
Generating RTLIL representation for module `\FD1P3IX'.
|
|
Generating RTLIL representation for module `\FD1P3JX'.
|
|
Generating RTLIL representation for module `\FD1S3AX'.
|
|
Generating RTLIL representation for module `\FD1S3AY'.
|
|
Generating RTLIL representation for module `\FD1S3BX'.
|
|
Generating RTLIL representation for module `\FD1S3DX'.
|
|
Generating RTLIL representation for module `\FD1S3IX'.
|
|
Generating RTLIL representation for module `\FD1S3JX'.
|
|
Generating RTLIL representation for module `\IFS1P3BX'.
|
|
Generating RTLIL representation for module `\IFS1P3DX'.
|
|
Generating RTLIL representation for module `\IFS1P3IX'.
|
|
Generating RTLIL representation for module `\IFS1P3JX'.
|
|
Generating RTLIL representation for module `\OFS1P3BX'.
|
|
Generating RTLIL representation for module `\OFS1P3DX'.
|
|
Generating RTLIL representation for module `\OFS1P3IX'.
|
|
Generating RTLIL representation for module `\OFS1P3JX'.
|
|
Generating RTLIL representation for module `\IB'.
|
|
Generating RTLIL representation for module `\IBPU'.
|
|
Generating RTLIL representation for module `\IBPD'.
|
|
Generating RTLIL representation for module `\OB'.
|
|
Generating RTLIL representation for module `\OBZ'.
|
|
Generating RTLIL representation for module `\OBZPU'.
|
|
Generating RTLIL representation for module `\OBZPD'.
|
|
Generating RTLIL representation for module `\OBCO'.
|
|
Generating RTLIL representation for module `\BB'.
|
|
Generating RTLIL representation for module `\BBPU'.
|
|
Generating RTLIL representation for module `\BBPD'.
|
|
Generating RTLIL representation for module `\ILVDS'.
|
|
Generating RTLIL representation for module `\OLVDS'.
|
|
Generating RTLIL representation for module `$lut'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
3.47.2. Continuing TECHMAP pass.
|
|
Using template $paramod$8c24dc0cdd336b7fb88bbf7eed45cec5cbae862b$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11111101 for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11001010 for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0001 for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10000000 for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000001 for cells of type $lut.
|
|
Using template $paramod$ee19d45db61acb4c70d938b97483a4ed4b792645$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1000 for cells of type $lut.
|
|
Using template $paramod$251994398653c4cf8de320f1e306e535d5d2d624$lut for cells of type $lut.
|
|
Using template $paramod$571404c0889eaf57f492cb5e37f8acb5df5852f9$lut for cells of type $lut.
|
|
Using template $paramod$658b9ed803f0d3d335616d3858b53e0a2522f1e8$lut for cells of type $lut.
|
|
Using template $paramod$eba7de026ff587370e320127e266317dae097a89$lut for cells of type $lut.
|
|
Using template $paramod$cf6936c7d99de0c7f4156f3db3bf26d8befb0936$lut for cells of type $lut.
|
|
Using template $paramod$1c0b02bad8ada563354b10a04b512fba38cd212e$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10011100 for cells of type $lut.
|
|
Using template $paramod$8e44661def013b6bf9fe6f8b049ef2c838d749f9$lut for cells of type $lut.
|
|
Using template $paramod$3fd3cd243a8b2f71b0ffe04bdaebf6ad83bcc78e$lut for cells of type $lut.
|
|
Using template $paramod$c600b4b1adc22857e1c1ba3b6aeb516fabe09da0$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000111 for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000100 for cells of type $lut.
|
|
Using template $paramod$bcd60d8aadb204b5d5fe51d3d608555c1aa7d58d$lut for cells of type $lut.
|
|
Using template $paramod$64b84593fae19d6c4d7d26333a195e5cc6b30160$lut for cells of type $lut.
|
|
Using template $paramod$6d6beead1425af15cf78b27fd9b11b41b5d4bce8$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0100 for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000001\LUT=2'01 for cells of type $lut.
|
|
No more expansions possible.
|
|
<suppressed ~436 debug messages>
|
|
|
|
3.48. Executing OPT_LUT_INS pass (discard unused LUT inputs).
|
|
Optimizing LUTs in neural_processor.
|
|
Optimizing lut $abc$5229$lut$aiger5228$1138.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
|
|
Optimizing lut $abc$5229$lut$aiger5228$1129.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
|
|
Optimizing lut $abc$5229$lut$aiger5228$1129.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
|
|
Optimizing lut $abc$5229$lut$aiger5228$1129.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
|
|
Optimizing lut $abc$5229$lut$aiger5228$1138.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $abc$5229$lut$aiger5228$1138.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
|
|
Optimizing lut $abc$5229$lut$aiger5228$1124.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $abc$5229$lut$aiger5228$1119.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $abc$5229$lut$aiger5228$1112.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $abc$5229$lut$aiger5228$1094.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Removed 0 unused cells and 88 unused wires.
|
|
|
|
3.49. Executing AUTONAME pass.
|
|
Renamed 812 objects in module neural_processor.
|
|
<suppressed ~812 debug messages>
|
|
|
|
3.50. Executing HIERARCHY pass (managing design hierarchy).
|
|
Attribute `top' found on module `neural_processor'. Setting top module to neural_processor.
|
|
|
|
3.50.1. Analyzing design hierarchy..
|
|
Top module: \neural_processor
|
|
|
|
3.50.2. Analyzing design hierarchy..
|
|
Top module: \neural_processor
|
|
Removed 0 unused modules.
|
|
|
|
3.51. Printing statistics.
|
|
|
|
=== neural_processor ===
|
|
|
|
+----------Local Count, excluding submodules.
|
|
|
|
|
235 wires
|
|
1784 wire bits
|
|
235 public wires
|
|
1784 public wire bits
|
|
18 ports
|
|
192 port bits
|
|
8 cells
|
|
8 MULT18X18D
|
|
656 submodules
|
|
88 CCU2C
|
|
2 L6MUX21
|
|
49 LUT4
|
|
8 PFUMX
|
|
509 TRELLIS_FF
|
|
|
|
=== design hierarchy ===
|
|
|
|
+----------Count including submodules.
|
|
|
|
|
8 neural_processor
|
|
|
|
+----------Count including submodules.
|
|
|
|
|
235 wires
|
|
1784 wire bits
|
|
235 public wires
|
|
1784 public wire bits
|
|
18 ports
|
|
192 port bits
|
|
- memories
|
|
- memory bits
|
|
- processes
|
|
8 cells
|
|
8 MULT18X18D
|
|
656 submodules
|
|
88 CCU2C
|
|
2 L6MUX21
|
|
49 LUT4
|
|
8 PFUMX
|
|
509 TRELLIS_FF
|
|
|
|
3.52. Executing CHECK pass (checking for obvious problems).
|
|
Checking module neural_processor...
|
|
Found and reported 0 problems.
|
|
|
|
3.53. Executing JSON backend.
|
|
|
|
Warnings: 36 unique messages, 40 total
|
|
End of script. Logfile hash: 8b4b561f5b, time: 0.39s, user: 0.34s, system: 0.01s, MEM: 40.95 MB peak
|
|
Yosys 0.68+post (git sha1 c12172fbae8af5e20f6fb52e3d4e92d56ed587b6, Release, AppleClang clang++ 21.0.0.21000101)
|
|
Time spent: 47% 21x read_verilog (0 sec), 11% 1x abc9_exe (0 sec), ...
|