micheleandClaude Sonnet 5
175f697ae1
Implements M4: memory_manager.v (arbitration/buffering/forwarding/ latency hiding/double buffering, §12) + prefetch_engine.v (double-buffered tile fetch, §13), sitting on the REAL, UNMODIFIED V1 PSRAM backend chain (int8_memory_access.v -> memory_interface.v -> psram_controller.v, per §15's explicit mandate not to touch the controller). Verified fully end-to-end with Verilator: real neural_processor (M1) fed entirely by memory_manager, computing against PSRAM-resident X/W tiles (double-buffered prefetch across up to 5 tiles) and writing its result back to PSRAM -- checked via an independent PSRAM read-back, with poison bytes around the operand regions to catch addressing errors. 3/3 jobs pass (1/3/5-tile configurations). Three real RTL bugs found and fixed during integration (full diagnostic trail in errors.log ERR-0006): prefetch_engine had no single-in-flight-request discipline, letting a queued request corrupt the bank bookkeeping of a fetch already running; the fix's own !pf_busy guard had a one-cycle blind spot (pf_busy lags pf_start by a clock) that needed an explicit !pf_start term; and a state-based mux for the shared backend port was off by one cycle, silently dropping the PSRAM result write entirely. Real synthesis: 0 CHECK problems, 851 LUT4/789 FF/108 CCU2C/0 DSP (expected, no multiplication in this module). Real place&route (via a synthesis-only timing harness, needed for the same TRELLIS_IO pin- budget reason as M2's array): Fmax 165.86 MHz, PASS at 80MHz. Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
130 lines
4.8 KiB
Verilog
130 lines
4.8 KiB
Verilog
`timescale 1ns/1ps
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// ================================================================
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// FPGA-Neural V2 -- Prefetch Engine (M4, docs/v2-description.md §13)
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//
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// Fetches ONE tile (P_IN activation bytes + P_IN weight bytes) from
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// the byte-level Memory Backend Interface into a pair of output
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// registers, sequentially (2*P_IN single-byte transactions -- the
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// same byte-at-a-time convention hardware/v1/rtl/neuron_memory.v
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// already uses against the same backend, reused unmodified here).
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//
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// This module fetches exactly one tile per fetch_start pulse; the
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// double-buffering strategy itself (§13: compute tile N while
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// prefetching tile N+1, swap, repeat) is memory_manager.v's
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// responsibility -- it retargets this single engine at whichever
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// bank currently needs refilling, so no internal arbitration between
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// multiple fetch engines sharing the backend port is ever needed.
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//
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// The backend port (mem_req/mem_wr/mem_addr/mem_wdata/mem_rdata/
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// mem_ready) matches hardware/v1/rtl/int8_memory_access.v's contract
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// exactly -- this engine can sit directly on top of that unmodified
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// V1 module (which itself sits on memory_interface.v ->
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// psram_controller.v, also unmodified, per §15).
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// ================================================================
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module prefetch_engine #(
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parameter DATA_WIDTH = 8,
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parameter P_IN = 8,
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parameter ADDR_WIDTH = 23
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)(
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input wire clk,
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input wire rst,
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input wire fetch_start,
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input wire [ADDR_WIDTH-1:0] x_addr, // base addr of this tile's P_IN X bytes
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input wire [ADDR_WIDTH-1:0] w_addr, // base addr of this tile's P_IN W bytes
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output reg fetch_busy,
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output reg fetch_done, // one-cycle pulse
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output reg signed [DATA_WIDTH*P_IN-1:0] tile_x,
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output reg signed [DATA_WIDTH*P_IN-1:0] tile_w,
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output reg mem_req,
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output reg mem_wr,
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output reg [ADDR_WIDTH-1:0] mem_addr,
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output reg signed [7:0] mem_wdata,
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input wire signed [7:0] mem_rdata,
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input wire mem_ready
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);
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localparam ST_IDLE = 2'd0;
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localparam ST_READ_X = 2'd1;
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localparam ST_READ_W = 2'd2;
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localparam ST_DONE = 2'd3;
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reg [1:0] state;
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reg [$clog2(P_IN+1)-1:0] byte_idx;
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always @(posedge clk) begin
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if (rst) begin
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state <= ST_IDLE;
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byte_idx <= 0;
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fetch_busy <= 1'b0;
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fetch_done <= 1'b0;
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mem_req <= 1'b0;
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mem_wr <= 1'b0;
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mem_addr <= {ADDR_WIDTH{1'b0}};
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mem_wdata <= 8'sd0;
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end else begin
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mem_req <= 1'b0;
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fetch_done <= 1'b0;
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case (state)
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ST_IDLE: begin
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if (fetch_start) begin
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fetch_busy <= 1'b1;
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byte_idx <= 0;
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mem_req <= 1'b1;
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mem_wr <= 1'b0;
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mem_addr <= x_addr;
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state <= ST_READ_X;
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end
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end
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ST_READ_X: begin
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if (mem_ready) begin
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tile_x[byte_idx*DATA_WIDTH +: DATA_WIDTH] <= mem_rdata;
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if (byte_idx == P_IN[$clog2(P_IN+1)-1:0] - 1'b1) begin
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byte_idx <= 0;
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mem_req <= 1'b1;
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mem_wr <= 1'b0;
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mem_addr <= w_addr;
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state <= ST_READ_W;
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end else begin
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byte_idx <= byte_idx + 1'b1;
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mem_req <= 1'b1;
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mem_wr <= 1'b0;
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mem_addr <= x_addr + byte_idx + 1'b1;
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end
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end
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end
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ST_READ_W: begin
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if (mem_ready) begin
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tile_w[byte_idx*DATA_WIDTH +: DATA_WIDTH] <= mem_rdata;
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if (byte_idx == P_IN[$clog2(P_IN+1)-1:0] - 1'b1) begin
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state <= ST_DONE;
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end else begin
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byte_idx <= byte_idx + 1'b1;
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mem_req <= 1'b1;
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mem_wr <= 1'b0;
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mem_addr <= w_addr + byte_idx + 1'b1;
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end
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end
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end
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ST_DONE: begin
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fetch_busy <= 1'b0;
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fetch_done <= 1'b1;
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state <= ST_IDLE;
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end
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default: state <= ST_IDLE;
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endcase
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end
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end
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endmodule
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