micheleandClaude Sonnet 5
175f697ae1
Implements M4: memory_manager.v (arbitration/buffering/forwarding/ latency hiding/double buffering, §12) + prefetch_engine.v (double-buffered tile fetch, §13), sitting on the REAL, UNMODIFIED V1 PSRAM backend chain (int8_memory_access.v -> memory_interface.v -> psram_controller.v, per §15's explicit mandate not to touch the controller). Verified fully end-to-end with Verilator: real neural_processor (M1) fed entirely by memory_manager, computing against PSRAM-resident X/W tiles (double-buffered prefetch across up to 5 tiles) and writing its result back to PSRAM -- checked via an independent PSRAM read-back, with poison bytes around the operand regions to catch addressing errors. 3/3 jobs pass (1/3/5-tile configurations). Three real RTL bugs found and fixed during integration (full diagnostic trail in errors.log ERR-0006): prefetch_engine had no single-in-flight-request discipline, letting a queued request corrupt the bank bookkeeping of a fetch already running; the fix's own !pf_busy guard had a one-cycle blind spot (pf_busy lags pf_start by a clock) that needed an explicit !pf_start term; and a state-based mux for the shared backend port was off by one cycle, silently dropping the PSRAM result write entirely. Real synthesis: 0 CHECK problems, 851 LUT4/789 FF/108 CCU2C/0 DSP (expected, no multiplication in this module). Real place&route (via a synthesis-only timing harness, needed for the same TRELLIS_IO pin- budget reason as M2's array): Fmax 165.86 MHz, PASS at 80MHz. Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
2555 lines
174 KiB
Plaintext
2555 lines
174 KiB
Plaintext
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/----------------------------------------------------------------------------\
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| yosys -- Yosys Open SYnthesis Suite |
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| Copyright (C) 2012 - 2026 Claire Xenia Wolf <claire@yosyshq.com> |
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| Distributed under an ISC-like license, type "license" to see terms |
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\----------------------------------------------------------------------------/
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Yosys 0.68+post (git sha1 c12172fbae8af5e20f6fb52e3d4e92d56ed587b6, Release, AppleClang clang++ 21.0.0.21000101)
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-- Parsing `hardware/v2/rtl/memory_manager.v' using frontend ` -vlog2k' --
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1. Executing Verilog-2005 frontend: hardware/v2/rtl/memory_manager.v
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Parsing Verilog input from `hardware/v2/rtl/memory_manager.v' to AST representation.
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Storing AST representation for module `$abstract\memory_manager'.
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Successfully finished Verilog frontend.
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-- Parsing `hardware/v2/rtl/prefetch_engine.v' using frontend ` -vlog2k' --
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2. Executing Verilog-2005 frontend: hardware/v2/rtl/prefetch_engine.v
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Parsing Verilog input from `hardware/v2/rtl/prefetch_engine.v' to AST representation.
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Storing AST representation for module `$abstract\prefetch_engine'.
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Successfully finished Verilog frontend.
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-- Parsing `hardware/v2/synthesis/harness_memory_manager.v' using frontend ` -vlog2k' --
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3. Executing Verilog-2005 frontend: hardware/v2/synthesis/harness_memory_manager.v
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Parsing Verilog input from `hardware/v2/synthesis/harness_memory_manager.v' to AST representation.
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Storing AST representation for module `$abstract\harness_memory_manager'.
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Successfully finished Verilog frontend.
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-- Running command `synth_ecp5 -json hardware/v2/synthesis/harness_memory_manager/top.json -top harness_memory_manager' --
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4. Executing SYNTH_LATTICE pass.
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4.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v
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Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v' to AST representation.
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Generating RTLIL representation for module `\LUT4'.
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Generating RTLIL representation for module `\$__ABC9_LUT5'.
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Generating RTLIL representation for module `\$__ABC9_LUT6'.
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Generating RTLIL representation for module `\$__ABC9_LUT7'.
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Generating RTLIL representation for module `\L6MUX21'.
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Generating RTLIL representation for module `\TRELLIS_RAM16X2'.
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Generating RTLIL representation for module `\PFUMX'.
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Generating RTLIL representation for module `\TRELLIS_DPR16X4'.
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Generating RTLIL representation for module `\DPR16X4C'.
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Generating RTLIL representation for module `\LUT2'.
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Generating RTLIL representation for module `\TRELLIS_FF'.
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Generating RTLIL representation for module `\TRELLIS_IO'.
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Generating RTLIL representation for module `\INV'.
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Generating RTLIL representation for module `\TRELLIS_COMB'.
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Generating RTLIL representation for module `\VLO'.
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Generating RTLIL representation for module `\VHI'.
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Generating RTLIL representation for module `\FD1P3AX'.
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Generating RTLIL representation for module `\FD1P3AY'.
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Generating RTLIL representation for module `\FD1P3BX'.
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Generating RTLIL representation for module `\FD1P3DX'.
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Generating RTLIL representation for module `\FD1P3IX'.
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Generating RTLIL representation for module `\FD1P3JX'.
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Generating RTLIL representation for module `\FD1S3AX'.
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Generating RTLIL representation for module `\FD1S3AY'.
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Generating RTLIL representation for module `\FD1S3BX'.
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Generating RTLIL representation for module `\FD1S3DX'.
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Generating RTLIL representation for module `\FD1S3IX'.
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Generating RTLIL representation for module `\FD1S3JX'.
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Generating RTLIL representation for module `\IFS1P3BX'.
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Generating RTLIL representation for module `\IFS1P3DX'.
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Generating RTLIL representation for module `\IFS1P3IX'.
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Generating RTLIL representation for module `\IFS1P3JX'.
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Generating RTLIL representation for module `\OFS1P3BX'.
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Generating RTLIL representation for module `\OFS1P3DX'.
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Generating RTLIL representation for module `\OFS1P3IX'.
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Generating RTLIL representation for module `\OFS1P3JX'.
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Generating RTLIL representation for module `\IB'.
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Generating RTLIL representation for module `\IBPU'.
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Generating RTLIL representation for module `\IBPD'.
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Generating RTLIL representation for module `\OB'.
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Generating RTLIL representation for module `\OBZ'.
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Generating RTLIL representation for module `\OBZPU'.
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Generating RTLIL representation for module `\OBZPD'.
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Generating RTLIL representation for module `\OBCO'.
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Generating RTLIL representation for module `\BB'.
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Generating RTLIL representation for module `\BBPU'.
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Generating RTLIL representation for module `\BBPD'.
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Generating RTLIL representation for module `\ILVDS'.
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Generating RTLIL representation for module `\OLVDS'.
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Generating RTLIL representation for module `\CCU2C'.
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Generating RTLIL representation for module `\DP16KD'.
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Replacing existing blackbox module `\FD1P3AX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:2.1-2.261.
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Generating RTLIL representation for module `\FD1P3AX'.
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Replacing existing blackbox module `\FD1P3AY' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:3.1-3.261.
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Generating RTLIL representation for module `\FD1P3AY'.
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Replacing existing blackbox module `\FD1P3BX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:4.1-4.261.
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Generating RTLIL representation for module `\FD1P3BX'.
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Replacing existing blackbox module `\FD1P3DX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:5.1-5.261.
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Generating RTLIL representation for module `\FD1P3DX'.
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Replacing existing blackbox module `\FD1P3IX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:6.1-6.261.
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Generating RTLIL representation for module `\FD1P3IX'.
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Replacing existing blackbox module `\FD1P3JX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:7.1-7.261.
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Generating RTLIL representation for module `\FD1P3JX'.
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Replacing existing blackbox module `\FD1S3AX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:8.1-8.261.
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Generating RTLIL representation for module `\FD1S3AX'.
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Replacing existing blackbox module `\FD1S3AY' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:9.1-9.261.
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Generating RTLIL representation for module `\FD1S3AY'.
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Replacing existing blackbox module `\FD1S3BX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:10.1-10.261.
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Generating RTLIL representation for module `\FD1S3BX'.
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Replacing existing blackbox module `\FD1S3DX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:11.1-11.261.
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Generating RTLIL representation for module `\FD1S3DX'.
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Replacing existing blackbox module `\FD1S3IX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:12.1-12.261.
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Generating RTLIL representation for module `\FD1S3IX'.
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Replacing existing blackbox module `\FD1S3JX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:13.1-13.261.
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Generating RTLIL representation for module `\FD1S3JX'.
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Replacing existing blackbox module `\IFS1P3BX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:26.1-26.301.
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Generating RTLIL representation for module `\IFS1P3BX'.
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Replacing existing blackbox module `\IFS1P3DX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:27.1-27.301.
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Generating RTLIL representation for module `\IFS1P3DX'.
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Replacing existing blackbox module `\IFS1P3IX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:28.1-28.301.
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Generating RTLIL representation for module `\IFS1P3IX'.
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Replacing existing blackbox module `\IFS1P3JX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:29.1-29.301.
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Generating RTLIL representation for module `\IFS1P3JX'.
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Replacing existing blackbox module `\OFS1P3BX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:31.1-31.302.
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Generating RTLIL representation for module `\OFS1P3BX'.
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Replacing existing blackbox module `\OFS1P3DX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:32.1-32.302.
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Generating RTLIL representation for module `\OFS1P3DX'.
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Replacing existing blackbox module `\OFS1P3IX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:33.1-33.302.
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Generating RTLIL representation for module `\OFS1P3IX'.
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Replacing existing blackbox module `\OFS1P3JX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:34.1-34.302.
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Generating RTLIL representation for module `\OFS1P3JX'.
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Replacing existing blackbox module `\IB' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:2.1-2.157.
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Generating RTLIL representation for module `\IB'.
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Replacing existing blackbox module `\IBPU' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:3.1-3.157.
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Generating RTLIL representation for module `\IBPU'.
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Replacing existing blackbox module `\IBPD' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:4.1-4.157.
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Generating RTLIL representation for module `\IBPD'.
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Replacing existing blackbox module `\OB' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:5.1-5.157.
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Generating RTLIL representation for module `\OB'.
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Replacing existing blackbox module `\OBZ' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:6.1-6.164.
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Generating RTLIL representation for module `\OBZ'.
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Replacing existing blackbox module `\OBZPU' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:7.1-7.164.
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Generating RTLIL representation for module `\OBZPU'.
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Replacing existing blackbox module `\OBZPD' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:8.1-8.164.
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Generating RTLIL representation for module `\OBZPD'.
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Replacing existing blackbox module `\OBCO' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:9.1-9.90.
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Generating RTLIL representation for module `\OBCO'.
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Replacing existing blackbox module `\BB' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:10.1-10.179.
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Generating RTLIL representation for module `\BB'.
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Replacing existing blackbox module `\BBPU' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:11.1-11.179.
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Generating RTLIL representation for module `\BBPU'.
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Replacing existing blackbox module `\BBPD' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:12.1-12.179.
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Generating RTLIL representation for module `\BBPD'.
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Replacing existing blackbox module `\ILVDS' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:13.1-13.139.
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Generating RTLIL representation for module `\ILVDS'.
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Replacing existing blackbox module `\OLVDS' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:14.1-14.146.
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Generating RTLIL representation for module `\OLVDS'.
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Successfully finished Verilog frontend.
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4.2. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v
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Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v' to AST representation.
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Generating RTLIL representation for module `\GSR'.
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Generating RTLIL representation for module `\PUR'.
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Generating RTLIL representation for module `\SGSR'.
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Generating RTLIL representation for module `\PDPW16KD'.
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Generating RTLIL representation for module `\MULT18X18D'.
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Generating RTLIL representation for module `\ALU54B'.
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Generating RTLIL representation for module `\CLKDIVF'.
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Generating RTLIL representation for module `\PCSCLKDIV'.
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Generating RTLIL representation for module `\DCSC'.
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Generating RTLIL representation for module `\DCCA'.
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Generating RTLIL representation for module `\ECLKSYNCB'.
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Generating RTLIL representation for module `\ECLKBRIDGECS'.
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Generating RTLIL representation for module `\DELAYF'.
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Generating RTLIL representation for module `\DELAYG'.
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Generating RTLIL representation for module `\USRMCLK'.
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Generating RTLIL representation for module `\DQSBUFM'.
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Generating RTLIL representation for module `\DDRDLLA'.
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Generating RTLIL representation for module `\DLLDELD'.
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Generating RTLIL representation for module `\IDDRX1F'.
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Generating RTLIL representation for module `\IDDRX2F'.
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Generating RTLIL representation for module `\IDDR71B'.
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Generating RTLIL representation for module `\IDDRX2DQA'.
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Generating RTLIL representation for module `\ODDRX1F'.
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Generating RTLIL representation for module `\ODDRX2F'.
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Generating RTLIL representation for module `\ODDR71B'.
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Generating RTLIL representation for module `\OSHX2A'.
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Generating RTLIL representation for module `\TSHX2DQA'.
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Generating RTLIL representation for module `\TSHX2DQSA'.
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Generating RTLIL representation for module `\ODDRX2DQA'.
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Generating RTLIL representation for module `\ODDRX2DQSB'.
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Generating RTLIL representation for module `\EHXPLLL'.
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Generating RTLIL representation for module `\DTR'.
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Generating RTLIL representation for module `\OSCG'.
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Generating RTLIL representation for module `\EXTREFB'.
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Generating RTLIL representation for module `\JTAGG'.
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Generating RTLIL representation for module `\DCUA'.
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Successfully finished Verilog frontend.
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4.3. Executing HIERARCHY pass (managing design hierarchy).
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4.4. Executing AST frontend in derive mode using pre-parsed AST for module `\harness_memory_manager'.
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Generating RTLIL representation for module `\harness_memory_manager'.
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4.4.1. Analyzing design hierarchy..
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Top module: \harness_memory_manager
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Parameter \DATA_WIDTH = 8
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Parameter \P_IN = 8
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Parameter \ADDR_WIDTH = 23
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4.4.2. Executing AST frontend in derive mode using pre-parsed AST for module `\memory_manager'.
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Parameter \DATA_WIDTH = 8
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Parameter \P_IN = 8
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Parameter \ADDR_WIDTH = 23
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Generating RTLIL representation for module `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\memory_manager'.
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4.4.3. Analyzing design hierarchy..
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Top module: \harness_memory_manager
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Used module: $paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\memory_manager
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Parameter \DATA_WIDTH = 8
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Parameter \P_IN = 8
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Parameter \ADDR_WIDTH = 23
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4.4.4. Executing AST frontend in derive mode using pre-parsed AST for module `\prefetch_engine'.
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Parameter \DATA_WIDTH = 8
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Parameter \P_IN = 8
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Parameter \ADDR_WIDTH = 23
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Generating RTLIL representation for module `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\prefetch_engine'.
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4.4.5. Analyzing design hierarchy..
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Top module: \harness_memory_manager
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Used module: $paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\memory_manager
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Used module: $paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\prefetch_engine
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4.4.6. Analyzing design hierarchy..
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Top module: \harness_memory_manager
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Used module: $paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\memory_manager
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Used module: $paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\prefetch_engine
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Removing unused module `$abstract\harness_memory_manager'.
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Removing unused module `$abstract\prefetch_engine'.
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Removing unused module `$abstract\memory_manager'.
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Removed 3 unused modules.
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4.5. Executing PROC pass (convert processes to netlists).
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4.5.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
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Cleaned up 0 empty switches.
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4.5.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
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Removed 1 dead cases from process $proc$hardware/v2/rtl/prefetch_engine.v:58$339 in module $paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\prefetch_engine.
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Marked 6 switch rules as full_case in process $proc$hardware/v2/rtl/prefetch_engine.v:58$339 in module $paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\prefetch_engine.
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Marked 6 switch rules as full_case in process $proc$hardware/v2/rtl/memory_manager.v:157$252 in module $paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\memory_manager.
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Marked 1 switch rules as full_case in process $proc$hardware/v2/synthesis/harness_memory_manager.v:63$231 in module harness_memory_manager.
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Marked 1 switch rules as full_case in process $proc$hardware/v2/synthesis/harness_memory_manager.v:24$226 in module harness_memory_manager.
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Removed a total of 1 dead cases.
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4.5.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
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Removed 7 redundant assignments.
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Promoted 16 assignments to connections.
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4.5.4. Executing PROC_INIT pass (extract init attributes).
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4.5.5. Executing PROC_ARST pass (detect async resets in processes).
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4.5.6. Executing PROC_ROM pass (convert switches to ROMs).
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Converted 0 switches.
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<suppressed ~23 debug messages>
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4.5.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
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Creating decoders for process `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\prefetch_engine.$proc$hardware/v2/rtl/prefetch_engine.v:58$339'.
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1/20: $3$lookahead\tile_w$338[63:0]$368
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2/20: $3$bitselwrite$pos$hardware/v2/rtl/prefetch_engine.v:105$336[31:0]$367
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3/20: $3$lookahead\tile_x$337[63:0]$353
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4/20: $3$bitselwrite$pos$hardware/v2/rtl/prefetch_engine.v:87$335[31:0]$352
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5/20: $2$lookahead\tile_w$338[63:0]$351
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6/20: $2$lookahead\tile_x$337[63:0]$350
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7/20: $2$bitselwrite$pos$hardware/v2/rtl/prefetch_engine.v:105$336[31:0]$349
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8/20: $2$bitselwrite$pos$hardware/v2/rtl/prefetch_engine.v:87$335[31:0]$348
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9/20: $0\mem_req[0:0]
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10/20: $0\fetch_done[0:0]
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11/20: $1$lookahead\tile_w$338[63:0]$347
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12/20: $1$lookahead\tile_x$337[63:0]$346
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13/20: $1$bitselwrite$pos$hardware/v2/rtl/prefetch_engine.v:105$336[31:0]$345
|
|
14/20: $1$bitselwrite$pos$hardware/v2/rtl/prefetch_engine.v:87$335[31:0]$344
|
|
15/20: $0\byte_idx[3:0]
|
|
16/20: $0\fetch_busy[0:0]
|
|
17/20: $0\state[1:0]
|
|
18/20: $0\mem_wdata[7:0]
|
|
19/20: $0\mem_addr[22:0]
|
|
20/20: $0\mem_wr[0:0]
|
|
Creating decoders for process `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\memory_manager.$proc$hardware/v2/rtl/memory_manager.v:157$252'.
|
|
1/46: $5$lookahead\bank_ready$251[1:0]$306
|
|
2/46: $3$bitselwrite$pos$hardware/v2/rtl/memory_manager.v:247$241[0:0]$305
|
|
3/46: $4$lookahead\bank_ready$251[1:0]$292
|
|
4/46: $3$lookahead\bank_ready$251[1:0]$291
|
|
5/46: $2$bitselwrite$pos$hardware/v2/rtl/memory_manager.v:247$241[0:0]$290
|
|
6/46: $2$lookahead\bank_ready$251[1:0]$278
|
|
7/46: $2$bitselwrite$pos$hardware/v2/rtl/memory_manager.v:183$240[0:0]$271
|
|
8/46: $2$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$243_EN[63:0]$277
|
|
9/46: $2$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$243_DATA[63:0]$276
|
|
10/46: $2$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$243_ADDR[0:0]$275
|
|
11/46: $2$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$242_EN[63:0]$274
|
|
12/46: $2$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$242_DATA[63:0]$273
|
|
13/46: $2$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$242_ADDR[0:0]$272
|
|
14/46: $1$lookahead\bank_ready$251[1:0]$270
|
|
15/46: $0\pf_start[0:0]
|
|
16/46: $0\result_ready[0:0]
|
|
17/46: $0\job_done[0:0]
|
|
18/46: $1$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$243_EN[63:0]$269
|
|
19/46: $1$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$243_DATA[63:0]$268
|
|
20/46: $1$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$243_ADDR[0:0]$267
|
|
21/46: $1$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$242_EN[63:0]$266
|
|
22/46: $1$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$242_DATA[63:0]$265
|
|
23/46: $1$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$242_ADDR[0:0]$264
|
|
24/46: $1$bitselwrite$pos$hardware/v2/rtl/memory_manager.v:247$241[0:0]$263
|
|
25/46: $1$bitselwrite$pos$hardware/v2/rtl/memory_manager.v:183$240[0:0]$262
|
|
26/46: $0\wr_mem_wdata[7:0]
|
|
27/46: $0\wr_mem_addr[22:0]
|
|
28/46: $0\wr_mem_req[0:0]
|
|
29/46: $0\pf_pending_bank[0:0]
|
|
30/46: $0\pf_pending_w[22:0]
|
|
31/46: $0\pf_pending_x[22:0]
|
|
32/46: $0\pf_pending[0:0]
|
|
33/46: $0\pf_target_bank[0:0]
|
|
34/46: $0\pf_w_addr[22:0]
|
|
35/46: $0\pf_x_addr[22:0]
|
|
36/46: $0\current_bank[0:0]
|
|
37/46: $0\tile_idx[15:0]
|
|
38/46: $0\n_tiles_reg[15:0]
|
|
39/46: $0\result_addr_reg[22:0]
|
|
40/46: $0\w_base_reg[22:0]
|
|
41/46: $0\x_base_reg[22:0]
|
|
42/46: $0\state[2:0]
|
|
43/46: $0\tile_last[0:0]
|
|
44/46: $0\weight_data[63:0]
|
|
45/46: $0\input_data[63:0]
|
|
46/46: $0\operand_valid[0:0]
|
|
Creating decoders for process `\harness_memory_manager.$proc$hardware/v2/synthesis/harness_memory_manager.v:63$231'.
|
|
1/1: $0\chk[7:0]
|
|
Creating decoders for process `\harness_memory_manager.$proc$hardware/v2/synthesis/harness_memory_manager.v:24$226'.
|
|
1/1: $0\lfsr[31:0]
|
|
|
|
4.5.8. Executing PROC_DLATCH pass (convert process syncs to latches).
|
|
|
|
4.5.9. Executing PROC_DFF pass (convert process syncs to FFs).
|
|
Creating register for signal `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\prefetch_engine.\mem_req' using process `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\prefetch_engine.$proc$hardware/v2/rtl/prefetch_engine.v:58$339'.
|
|
created $dff cell `$procdff$1086' with positive edge clock.
|
|
Creating register for signal `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\prefetch_engine.\mem_wr' using process `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\prefetch_engine.$proc$hardware/v2/rtl/prefetch_engine.v:58$339'.
|
|
created $dff cell `$procdff$1087' with positive edge clock.
|
|
Creating register for signal `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\prefetch_engine.\mem_addr' using process `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\prefetch_engine.$proc$hardware/v2/rtl/prefetch_engine.v:58$339'.
|
|
created $dff cell `$procdff$1088' with positive edge clock.
|
|
Creating register for signal `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\prefetch_engine.\mem_wdata' using process `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\prefetch_engine.$proc$hardware/v2/rtl/prefetch_engine.v:58$339'.
|
|
created $dff cell `$procdff$1089' with positive edge clock.
|
|
Creating register for signal `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\prefetch_engine.\state' using process `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\prefetch_engine.$proc$hardware/v2/rtl/prefetch_engine.v:58$339'.
|
|
created $dff cell `$procdff$1090' with positive edge clock.
|
|
Creating register for signal `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\prefetch_engine.\fetch_busy' using process `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\prefetch_engine.$proc$hardware/v2/rtl/prefetch_engine.v:58$339'.
|
|
created $dff cell `$procdff$1091' with positive edge clock.
|
|
Creating register for signal `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\prefetch_engine.\fetch_done' using process `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\prefetch_engine.$proc$hardware/v2/rtl/prefetch_engine.v:58$339'.
|
|
created $dff cell `$procdff$1092' with positive edge clock.
|
|
Creating register for signal `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\prefetch_engine.\tile_x' using process `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\prefetch_engine.$proc$hardware/v2/rtl/prefetch_engine.v:58$339'.
|
|
created $dff cell `$procdff$1093' with positive edge clock.
|
|
Creating register for signal `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\prefetch_engine.\tile_w' using process `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\prefetch_engine.$proc$hardware/v2/rtl/prefetch_engine.v:58$339'.
|
|
created $dff cell `$procdff$1094' with positive edge clock.
|
|
Creating register for signal `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\prefetch_engine.\byte_idx' using process `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\prefetch_engine.$proc$hardware/v2/rtl/prefetch_engine.v:58$339'.
|
|
created $dff cell `$procdff$1095' with positive edge clock.
|
|
Creating register for signal `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\prefetch_engine.$bitselwrite$pos$hardware/v2/rtl/prefetch_engine.v:87$335' using process `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\prefetch_engine.$proc$hardware/v2/rtl/prefetch_engine.v:58$339'.
|
|
created $dff cell `$procdff$1096' with positive edge clock.
|
|
Creating register for signal `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\prefetch_engine.$bitselwrite$pos$hardware/v2/rtl/prefetch_engine.v:105$336' using process `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\prefetch_engine.$proc$hardware/v2/rtl/prefetch_engine.v:58$339'.
|
|
created $dff cell `$procdff$1097' with positive edge clock.
|
|
Creating register for signal `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\prefetch_engine.$lookahead\tile_x$337' using process `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\prefetch_engine.$proc$hardware/v2/rtl/prefetch_engine.v:58$339'.
|
|
created $dff cell `$procdff$1098' with positive edge clock.
|
|
Creating register for signal `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\prefetch_engine.$lookahead\tile_w$338' using process `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\prefetch_engine.$proc$hardware/v2/rtl/prefetch_engine.v:58$339'.
|
|
created $dff cell `$procdff$1099' with positive edge clock.
|
|
Creating register for signal `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\memory_manager.\job_done' using process `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\memory_manager.$proc$hardware/v2/rtl/memory_manager.v:157$252'.
|
|
created $dff cell `$procdff$1100' with positive edge clock.
|
|
Creating register for signal `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\memory_manager.\operand_valid' using process `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\memory_manager.$proc$hardware/v2/rtl/memory_manager.v:157$252'.
|
|
created $dff cell `$procdff$1101' with positive edge clock.
|
|
Creating register for signal `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\memory_manager.\input_data' using process `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\memory_manager.$proc$hardware/v2/rtl/memory_manager.v:157$252'.
|
|
created $dff cell `$procdff$1102' with positive edge clock.
|
|
Creating register for signal `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\memory_manager.\weight_data' using process `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\memory_manager.$proc$hardware/v2/rtl/memory_manager.v:157$252'.
|
|
created $dff cell `$procdff$1103' with positive edge clock.
|
|
Creating register for signal `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\memory_manager.\tile_last' using process `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\memory_manager.$proc$hardware/v2/rtl/memory_manager.v:157$252'.
|
|
created $dff cell `$procdff$1104' with positive edge clock.
|
|
Creating register for signal `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\memory_manager.\result_ready' using process `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\memory_manager.$proc$hardware/v2/rtl/memory_manager.v:157$252'.
|
|
created $dff cell `$procdff$1105' with positive edge clock.
|
|
Creating register for signal `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\memory_manager.\state' using process `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\memory_manager.$proc$hardware/v2/rtl/memory_manager.v:157$252'.
|
|
created $dff cell `$procdff$1106' with positive edge clock.
|
|
Creating register for signal `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\memory_manager.\x_base_reg' using process `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\memory_manager.$proc$hardware/v2/rtl/memory_manager.v:157$252'.
|
|
created $dff cell `$procdff$1107' with positive edge clock.
|
|
Creating register for signal `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\memory_manager.\w_base_reg' using process `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\memory_manager.$proc$hardware/v2/rtl/memory_manager.v:157$252'.
|
|
created $dff cell `$procdff$1108' with positive edge clock.
|
|
Creating register for signal `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\memory_manager.\result_addr_reg' using process `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\memory_manager.$proc$hardware/v2/rtl/memory_manager.v:157$252'.
|
|
created $dff cell `$procdff$1109' with positive edge clock.
|
|
Creating register for signal `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\memory_manager.\n_tiles_reg' using process `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\memory_manager.$proc$hardware/v2/rtl/memory_manager.v:157$252'.
|
|
created $dff cell `$procdff$1110' with positive edge clock.
|
|
Creating register for signal `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\memory_manager.\tile_idx' using process `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\memory_manager.$proc$hardware/v2/rtl/memory_manager.v:157$252'.
|
|
created $dff cell `$procdff$1111' with positive edge clock.
|
|
Creating register for signal `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\memory_manager.\current_bank' using process `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\memory_manager.$proc$hardware/v2/rtl/memory_manager.v:157$252'.
|
|
created $dff cell `$procdff$1112' with positive edge clock.
|
|
Creating register for signal `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\memory_manager.\bank_ready' using process `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\memory_manager.$proc$hardware/v2/rtl/memory_manager.v:157$252'.
|
|
created $dff cell `$procdff$1113' with positive edge clock.
|
|
Creating register for signal `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\memory_manager.\pf_start' using process `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\memory_manager.$proc$hardware/v2/rtl/memory_manager.v:157$252'.
|
|
created $dff cell `$procdff$1114' with positive edge clock.
|
|
Creating register for signal `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\memory_manager.\pf_x_addr' using process `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\memory_manager.$proc$hardware/v2/rtl/memory_manager.v:157$252'.
|
|
created $dff cell `$procdff$1115' with positive edge clock.
|
|
Creating register for signal `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\memory_manager.\pf_w_addr' using process `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\memory_manager.$proc$hardware/v2/rtl/memory_manager.v:157$252'.
|
|
created $dff cell `$procdff$1116' with positive edge clock.
|
|
Creating register for signal `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\memory_manager.\pf_target_bank' using process `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\memory_manager.$proc$hardware/v2/rtl/memory_manager.v:157$252'.
|
|
created $dff cell `$procdff$1117' with positive edge clock.
|
|
Creating register for signal `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\memory_manager.\pf_pending' using process `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\memory_manager.$proc$hardware/v2/rtl/memory_manager.v:157$252'.
|
|
created $dff cell `$procdff$1118' with positive edge clock.
|
|
Creating register for signal `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\memory_manager.\pf_pending_x' using process `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\memory_manager.$proc$hardware/v2/rtl/memory_manager.v:157$252'.
|
|
created $dff cell `$procdff$1119' with positive edge clock.
|
|
Creating register for signal `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\memory_manager.\pf_pending_w' using process `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\memory_manager.$proc$hardware/v2/rtl/memory_manager.v:157$252'.
|
|
created $dff cell `$procdff$1120' with positive edge clock.
|
|
Creating register for signal `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\memory_manager.\pf_pending_bank' using process `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\memory_manager.$proc$hardware/v2/rtl/memory_manager.v:157$252'.
|
|
created $dff cell `$procdff$1121' with positive edge clock.
|
|
Creating register for signal `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\memory_manager.\wr_mem_req' using process `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\memory_manager.$proc$hardware/v2/rtl/memory_manager.v:157$252'.
|
|
created $dff cell `$procdff$1122' with positive edge clock.
|
|
Creating register for signal `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\memory_manager.\wr_mem_addr' using process `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\memory_manager.$proc$hardware/v2/rtl/memory_manager.v:157$252'.
|
|
created $dff cell `$procdff$1123' with positive edge clock.
|
|
Creating register for signal `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\memory_manager.\wr_mem_wdata' using process `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\memory_manager.$proc$hardware/v2/rtl/memory_manager.v:157$252'.
|
|
created $dff cell `$procdff$1124' with positive edge clock.
|
|
Creating register for signal `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\memory_manager.$bitselwrite$pos$hardware/v2/rtl/memory_manager.v:183$240' using process `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\memory_manager.$proc$hardware/v2/rtl/memory_manager.v:157$252'.
|
|
created $dff cell `$procdff$1125' with positive edge clock.
|
|
Creating register for signal `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\memory_manager.$bitselwrite$pos$hardware/v2/rtl/memory_manager.v:247$241' using process `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\memory_manager.$proc$hardware/v2/rtl/memory_manager.v:157$252'.
|
|
created $dff cell `$procdff$1126' with positive edge clock.
|
|
Creating register for signal `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\memory_manager.$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$242_ADDR' using process `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\memory_manager.$proc$hardware/v2/rtl/memory_manager.v:157$252'.
|
|
created $dff cell `$procdff$1127' with positive edge clock.
|
|
Creating register for signal `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\memory_manager.$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$242_DATA' using process `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\memory_manager.$proc$hardware/v2/rtl/memory_manager.v:157$252'.
|
|
created $dff cell `$procdff$1128' with positive edge clock.
|
|
Creating register for signal `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\memory_manager.$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$242_EN' using process `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\memory_manager.$proc$hardware/v2/rtl/memory_manager.v:157$252'.
|
|
created $dff cell `$procdff$1129' with positive edge clock.
|
|
Creating register for signal `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\memory_manager.$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$243_ADDR' using process `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\memory_manager.$proc$hardware/v2/rtl/memory_manager.v:157$252'.
|
|
created $dff cell `$procdff$1130' with positive edge clock.
|
|
Creating register for signal `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\memory_manager.$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$243_DATA' using process `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\memory_manager.$proc$hardware/v2/rtl/memory_manager.v:157$252'.
|
|
created $dff cell `$procdff$1131' with positive edge clock.
|
|
Creating register for signal `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\memory_manager.$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$243_EN' using process `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\memory_manager.$proc$hardware/v2/rtl/memory_manager.v:157$252'.
|
|
created $dff cell `$procdff$1132' with positive edge clock.
|
|
Creating register for signal `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\memory_manager.$lookahead\bank_ready$251' using process `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\memory_manager.$proc$hardware/v2/rtl/memory_manager.v:157$252'.
|
|
created $dff cell `$procdff$1133' with positive edge clock.
|
|
Creating register for signal `\harness_memory_manager.\chk' using process `\harness_memory_manager.$proc$hardware/v2/synthesis/harness_memory_manager.v:63$231'.
|
|
created $dff cell `$procdff$1134' with positive edge clock.
|
|
Creating register for signal `\harness_memory_manager.\lfsr' using process `\harness_memory_manager.$proc$hardware/v2/synthesis/harness_memory_manager.v:24$226'.
|
|
created $dff cell `$procdff$1135' with positive edge clock.
|
|
|
|
4.5.10. Executing PROC_MEMWR pass (convert process memory writes to cells).
|
|
|
|
4.5.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
|
|
Found and cleaned up 7 empty switches in `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\prefetch_engine.$proc$hardware/v2/rtl/prefetch_engine.v:58$339'.
|
|
Removing empty process `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\prefetch_engine.$proc$hardware/v2/rtl/prefetch_engine.v:58$339'.
|
|
Found and cleaned up 14 empty switches in `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\memory_manager.$proc$hardware/v2/rtl/memory_manager.v:157$252'.
|
|
Removing empty process `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\memory_manager.$proc$hardware/v2/rtl/memory_manager.v:157$252'.
|
|
Found and cleaned up 1 empty switch in `\harness_memory_manager.$proc$hardware/v2/synthesis/harness_memory_manager.v:63$231'.
|
|
Removing empty process `harness_memory_manager.$proc$hardware/v2/synthesis/harness_memory_manager.v:63$231'.
|
|
Found and cleaned up 1 empty switch in `\harness_memory_manager.$proc$hardware/v2/synthesis/harness_memory_manager.v:24$226'.
|
|
Removing empty process `harness_memory_manager.$proc$hardware/v2/synthesis/harness_memory_manager.v:24$226'.
|
|
Cleaned up 23 empty switches.
|
|
|
|
4.5.12. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module $paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\prefetch_engine.
|
|
<suppressed ~10 debug messages>
|
|
Optimizing module $paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\memory_manager.
|
|
<suppressed ~19 debug messages>
|
|
Optimizing module harness_memory_manager.
|
|
<suppressed ~1 debug messages>
|
|
|
|
4.6. Executing CHECK pass (checking for obvious problems).
|
|
Checking module $paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\prefetch_engine...
|
|
Checking module $paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\memory_manager...
|
|
Checking module harness_memory_manager...
|
|
Found and reported 0 problems.
|
|
|
|
4.7. Executing FLATTEN pass (flatten design).
|
|
Deleting now unused module $paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\prefetch_engine.
|
|
Deleting now unused module $paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\memory_manager.
|
|
<suppressed ~2 debug messages>
|
|
|
|
4.8. Executing TRIBUF pass.
|
|
|
|
4.9. Executing DEMINOUT pass (demote inout ports to input or output).
|
|
|
|
4.10. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module harness_memory_manager.
|
|
<suppressed ~10 debug messages>
|
|
|
|
4.11. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \harness_memory_manager..
|
|
Removed 47 unused cells and 312 unused wires.
|
|
<suppressed ~50 debug messages>
|
|
|
|
4.12. Executing CHECK pass (checking for obvious problems).
|
|
Checking module harness_memory_manager...
|
|
Found and reported 0 problems.
|
|
|
|
4.13. Executing OPT pass (performing simple optimizations).
|
|
|
|
4.13.1. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module harness_memory_manager.
|
|
|
|
4.13.2. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\harness_memory_manager'.
|
|
Computing hashes of 391 cells of `\harness_memory_manager'.
|
|
Finding duplicate cells in `\harness_memory_manager'.
|
|
Computing hashes of 316 cells of `\harness_memory_manager'.
|
|
Finding duplicate cells in `\harness_memory_manager'.
|
|
Computing hashes of 313 cells of `\harness_memory_manager'.
|
|
Finding duplicate cells in `\harness_memory_manager'.
|
|
Computing hashes of 312 cells of `\harness_memory_manager'.
|
|
Finding duplicate cells in `\harness_memory_manager'.
|
|
<suppressed ~237 debug messages>
|
|
Removed a total of 79 cells.
|
|
|
|
4.13.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \harness_memory_manager..
|
|
Creating internal representation of mux trees.
|
|
Evaluating internal representation of mux trees.
|
|
Replacing known input bits on port B of cell $flatten\dut.$procmux$811: { \lfsr [7:0] \lfsr [14:0] } -> { \lfsr [7:1] 1'1 \lfsr [14:1] 1'1 }
|
|
Replacing known input bits on port B of cell $flatten\dut.$procmux$837: \lfsr [22:0] -> { \lfsr [22:1] 1'1 }
|
|
Replacing known input bits on port B of cell $flatten\dut.$procmux$925: \lfsr [15:0] -> { \lfsr [15:1] 1'1 }
|
|
Replacing known input bits on port B of cell $flatten\dut.$procmux$939: { \lfsr [3:0] \lfsr [18:0] } -> { \lfsr [3:1] 1'1 \lfsr [18:1] 1'1 }
|
|
Replacing known input bits on port B of cell $flatten\dut.$procmux$953: { \lfsr [7:0] \lfsr [14:0] } -> { \lfsr [7:1] 1'1 \lfsr [14:1] 1'1 }
|
|
Replacing known input bits on port B of cell $flatten\dut.$procmux$967: \lfsr [22:0] -> { \lfsr [22:1] 1'1 }
|
|
Replacing known input bits on port B of cell $flatten\dut.$procmux$1063: \dut.operand_valid -> 1'1
|
|
Replacing known input bits on port A of cell $flatten\dut.$procmux$1061: \dut.operand_valid -> 1'0
|
|
Analyzing evaluation results.
|
|
dead port 2/2 on $mux $flatten\dut.$procmux$595.
|
|
dead port 1/2 on $mux $flatten\dut.$procmux$598.
|
|
dead port 2/2 on $mux $flatten\dut.$procmux$621.
|
|
dead port 1/2 on $mux $flatten\dut.$procmux$624.
|
|
dead port 1/2 on $mux $flatten\dut.$procmux$634.
|
|
dead port 1/2 on $mux $flatten\dut.$procmux$661.
|
|
dead port 1/2 on $mux $flatten\dut.$procmux$667.
|
|
dead port 1/2 on $mux $flatten\dut.$procmux$673.
|
|
dead port 1/2 on $mux $flatten\dut.$procmux$679.
|
|
dead port 1/2 on $mux $flatten\dut.$procmux$685.
|
|
dead port 1/2 on $mux $flatten\dut.$procmux$691.
|
|
dead port 1/2 on $mux $flatten\dut.\u_prefetch.$procmux$434.
|
|
dead port 1/2 on $mux $flatten\dut.\u_prefetch.$procmux$426.
|
|
dead port 1/2 on $mux $flatten\dut.\u_prefetch.$procmux$408.
|
|
dead port 2/2 on $mux $flatten\dut.\u_prefetch.$procmux$405.
|
|
dead port 1/2 on $mux $flatten\dut.\u_prefetch.$procmux$389.
|
|
dead port 2/2 on $mux $flatten\dut.\u_prefetch.$procmux$386.
|
|
Removed 17 multiplexer ports.
|
|
<suppressed ~250 debug messages>
|
|
|
|
4.13.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \harness_memory_manager.
|
|
Consolidated identical input bits for $mux cell $flatten\dut.$procmux$658:
|
|
Old ports: A=64'0000000000000000000000000000000000000000000000000000000000000000, B=64'1111111111111111111111111111111111111111111111111111111111111111, Y=$flatten\dut.$procmux$658_Y
|
|
New ports: A=1'0, B=1'1, Y=$flatten\dut.$procmux$658_Y [0]
|
|
New connections: $flatten\dut.$procmux$658_Y [63:1] = { $flatten\dut.$procmux$658_Y [0] $flatten\dut.$procmux$658_Y [0] $flatten\dut.$procmux$658_Y [0] $flatten\dut.$procmux$658_Y [0] $flatten\dut.$procmux$658_Y [0] $flatten\dut.$procmux$658_Y [0] $flatten\dut.$procmux$658_Y [0] $flatten\dut.$procmux$658_Y [0] $flatten\dut.$procmux$658_Y [0] $flatten\dut.$procmux$658_Y [0] $flatten\dut.$procmux$658_Y [0] $flatten\dut.$procmux$658_Y [0] $flatten\dut.$procmux$658_Y [0] $flatten\dut.$procmux$658_Y [0] $flatten\dut.$procmux$658_Y [0] $flatten\dut.$procmux$658_Y [0] $flatten\dut.$procmux$658_Y [0] $flatten\dut.$procmux$658_Y [0] $flatten\dut.$procmux$658_Y [0] $flatten\dut.$procmux$658_Y [0] $flatten\dut.$procmux$658_Y [0] $flatten\dut.$procmux$658_Y [0] $flatten\dut.$procmux$658_Y [0] $flatten\dut.$procmux$658_Y [0] $flatten\dut.$procmux$658_Y [0] $flatten\dut.$procmux$658_Y [0] $flatten\dut.$procmux$658_Y [0] $flatten\dut.$procmux$658_Y [0] $flatten\dut.$procmux$658_Y [0] $flatten\dut.$procmux$658_Y [0] $flatten\dut.$procmux$658_Y [0] $flatten\dut.$procmux$658_Y [0] $flatten\dut.$procmux$658_Y [0] $flatten\dut.$procmux$658_Y [0] $flatten\dut.$procmux$658_Y [0] $flatten\dut.$procmux$658_Y [0] $flatten\dut.$procmux$658_Y [0] $flatten\dut.$procmux$658_Y [0] $flatten\dut.$procmux$658_Y [0] $flatten\dut.$procmux$658_Y [0] $flatten\dut.$procmux$658_Y [0] $flatten\dut.$procmux$658_Y [0] $flatten\dut.$procmux$658_Y [0] $flatten\dut.$procmux$658_Y [0] $flatten\dut.$procmux$658_Y [0] $flatten\dut.$procmux$658_Y [0] $flatten\dut.$procmux$658_Y [0] $flatten\dut.$procmux$658_Y [0] $flatten\dut.$procmux$658_Y [0] $flatten\dut.$procmux$658_Y [0] $flatten\dut.$procmux$658_Y [0] $flatten\dut.$procmux$658_Y [0] $flatten\dut.$procmux$658_Y [0] $flatten\dut.$procmux$658_Y [0] $flatten\dut.$procmux$658_Y [0] $flatten\dut.$procmux$658_Y [0] $flatten\dut.$procmux$658_Y [0] $flatten\dut.$procmux$658_Y [0] $flatten\dut.$procmux$658_Y [0] $flatten\dut.$procmux$658_Y [0] $flatten\dut.$procmux$658_Y [0] $flatten\dut.$procmux$658_Y [0] $flatten\dut.$procmux$658_Y [0] }
|
|
Consolidated identical input bits for $mux cell $flatten\dut.$procmux$676:
|
|
Old ports: A=64'0000000000000000000000000000000000000000000000000000000000000000, B=64'1111111111111111111111111111111111111111111111111111111111111111, Y=$flatten\dut.$procmux$676_Y
|
|
New ports: A=1'0, B=1'1, Y=$flatten\dut.$procmux$676_Y [0]
|
|
New connections: $flatten\dut.$procmux$676_Y [63:1] = { $flatten\dut.$procmux$676_Y [0] $flatten\dut.$procmux$676_Y [0] $flatten\dut.$procmux$676_Y [0] $flatten\dut.$procmux$676_Y [0] $flatten\dut.$procmux$676_Y [0] $flatten\dut.$procmux$676_Y [0] $flatten\dut.$procmux$676_Y [0] $flatten\dut.$procmux$676_Y [0] $flatten\dut.$procmux$676_Y [0] $flatten\dut.$procmux$676_Y [0] $flatten\dut.$procmux$676_Y [0] $flatten\dut.$procmux$676_Y [0] $flatten\dut.$procmux$676_Y [0] $flatten\dut.$procmux$676_Y [0] $flatten\dut.$procmux$676_Y [0] $flatten\dut.$procmux$676_Y [0] $flatten\dut.$procmux$676_Y [0] $flatten\dut.$procmux$676_Y [0] $flatten\dut.$procmux$676_Y [0] $flatten\dut.$procmux$676_Y [0] $flatten\dut.$procmux$676_Y [0] $flatten\dut.$procmux$676_Y [0] $flatten\dut.$procmux$676_Y [0] $flatten\dut.$procmux$676_Y [0] $flatten\dut.$procmux$676_Y [0] $flatten\dut.$procmux$676_Y [0] $flatten\dut.$procmux$676_Y [0] $flatten\dut.$procmux$676_Y [0] $flatten\dut.$procmux$676_Y [0] $flatten\dut.$procmux$676_Y [0] $flatten\dut.$procmux$676_Y [0] $flatten\dut.$procmux$676_Y [0] $flatten\dut.$procmux$676_Y [0] $flatten\dut.$procmux$676_Y [0] $flatten\dut.$procmux$676_Y [0] $flatten\dut.$procmux$676_Y [0] $flatten\dut.$procmux$676_Y [0] $flatten\dut.$procmux$676_Y [0] $flatten\dut.$procmux$676_Y [0] $flatten\dut.$procmux$676_Y [0] $flatten\dut.$procmux$676_Y [0] $flatten\dut.$procmux$676_Y [0] $flatten\dut.$procmux$676_Y [0] $flatten\dut.$procmux$676_Y [0] $flatten\dut.$procmux$676_Y [0] $flatten\dut.$procmux$676_Y [0] $flatten\dut.$procmux$676_Y [0] $flatten\dut.$procmux$676_Y [0] $flatten\dut.$procmux$676_Y [0] $flatten\dut.$procmux$676_Y [0] $flatten\dut.$procmux$676_Y [0] $flatten\dut.$procmux$676_Y [0] $flatten\dut.$procmux$676_Y [0] $flatten\dut.$procmux$676_Y [0] $flatten\dut.$procmux$676_Y [0] $flatten\dut.$procmux$676_Y [0] $flatten\dut.$procmux$676_Y [0] $flatten\dut.$procmux$676_Y [0] $flatten\dut.$procmux$676_Y [0] $flatten\dut.$procmux$676_Y [0] $flatten\dut.$procmux$676_Y [0] $flatten\dut.$procmux$676_Y [0] $flatten\dut.$procmux$676_Y [0] }
|
|
New ctrl vector for $pmux cell $flatten\dut.\u_prefetch.$procmux$428: { $auto$opt_reduce.cc:137:opt_pmux$1141 $flatten\dut.\u_prefetch.$procmux$581_CMP }
|
|
New ctrl vector for $pmux cell $flatten\dut.\u_prefetch.$procmux$420: { $auto$opt_reduce.cc:137:opt_pmux$1143 $flatten\dut.\u_prefetch.$procmux$575_CMP }
|
|
Optimizing cells in module \harness_memory_manager.
|
|
Consolidated identical input bits for $mux cell $flatten\dut.$procmux$718:
|
|
Old ports: A=$flatten\dut.$2$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$243_EN[63:0]$277, B=64'0000000000000000000000000000000000000000000000000000000000000000, Y=$flatten\dut.$0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$243_EN[63:0]$260
|
|
New ports: A=$flatten\dut.$procmux$658_Y [0], B=1'0, Y=$flatten\dut.$0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$243_EN[63:0]$260 [0]
|
|
New connections: $flatten\dut.$0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$243_EN[63:0]$260 [63:1] = { $flatten\dut.$0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$243_EN[63:0]$260 [0] $flatten\dut.$0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$243_EN[63:0]$260 [0] $flatten\dut.$0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$243_EN[63:0]$260 [0] $flatten\dut.$0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$243_EN[63:0]$260 [0] $flatten\dut.$0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$243_EN[63:0]$260 [0] $flatten\dut.$0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$243_EN[63:0]$260 [0] $flatten\dut.$0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$243_EN[63:0]$260 [0] $flatten\dut.$0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$243_EN[63:0]$260 [0] $flatten\dut.$0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$243_EN[63:0]$260 [0] $flatten\dut.$0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$243_EN[63:0]$260 [0] $flatten\dut.$0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$243_EN[63:0]$260 [0] $flatten\dut.$0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$243_EN[63:0]$260 [0] $flatten\dut.$0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$243_EN[63:0]$260 [0] $flatten\dut.$0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$243_EN[63:0]$260 [0] $flatten\dut.$0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$243_EN[63:0]$260 [0] $flatten\dut.$0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$243_EN[63:0]$260 [0] $flatten\dut.$0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$243_EN[63:0]$260 [0] $flatten\dut.$0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$243_EN[63:0]$260 [0] $flatten\dut.$0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$243_EN[63:0]$260 [0] $flatten\dut.$0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$243_EN[63:0]$260 [0] $flatten\dut.$0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$243_EN[63:0]$260 [0] $flatten\dut.$0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$243_EN[63:0]$260 [0] $flatten\dut.$0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$243_EN[63:0]$260 [0] $flatten\dut.$0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$243_EN[63:0]$260 [0] $flatten\dut.$0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$243_EN[63:0]$260 [0] $flatten\dut.$0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$243_EN[63:0]$260 [0] $flatten\dut.$0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$243_EN[63:0]$260 [0] $flatten\dut.$0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$243_EN[63:0]$260 [0] $flatten\dut.$0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$243_EN[63:0]$260 [0] $flatten\dut.$0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$243_EN[63:0]$260 [0] $flatten\dut.$0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$243_EN[63:0]$260 [0] $flatten\dut.$0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$243_EN[63:0]$260 [0] $flatten\dut.$0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$243_EN[63:0]$260 [0] $flatten\dut.$0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$243_EN[63:0]$260 [0] $flatten\dut.$0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$243_EN[63:0]$260 [0] $flatten\dut.$0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$243_EN[63:0]$260 [0] $flatten\dut.$0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$243_EN[63:0]$260 [0] $flatten\dut.$0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$243_EN[63:0]$260 [0] $flatten\dut.$0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$243_EN[63:0]$260 [0] $flatten\dut.$0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$243_EN[63:0]$260 [0] $flatten\dut.$0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$243_EN[63:0]$260 [0] $flatten\dut.$0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$243_EN[63:0]$260 [0] $flatten\dut.$0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$243_EN[63:0]$260 [0] $flatten\dut.$0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$243_EN[63:0]$260 [0] $flatten\dut.$0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$243_EN[63:0]$260 [0] $flatten\dut.$0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$243_EN[63:0]$260 [0] $flatten\dut.$0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$243_EN[63:0]$260 [0] $flatten\dut.$0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$243_EN[63:0]$260 [0] $flatten\dut.$0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$243_EN[63:0]$260 [0] $flatten\dut.$0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$243_EN[63:0]$260 [0] $flatten\dut.$0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$243_EN[63:0]$260 [0] $flatten\dut.$0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$243_EN[63:0]$260 [0] $flatten\dut.$0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$243_EN[63:0]$260 [0] $flatten\dut.$0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$243_EN[63:0]$260 [0] $flatten\dut.$0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$243_EN[63:0]$260 [0] $flatten\dut.$0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$243_EN[63:0]$260 [0] $flatten\dut.$0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$243_EN[63:0]$260 [0] $flatten\dut.$0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$243_EN[63:0]$260 [0] $flatten\dut.$0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$243_EN[63:0]$260 [0] $flatten\dut.$0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$243_EN[63:0]$260 [0] $flatten\dut.$0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$243_EN[63:0]$260 [0] $flatten\dut.$0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$243_EN[63:0]$260 [0] $flatten\dut.$0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$243_EN[63:0]$260 [0] }
|
|
Consolidated identical input bits for $mux cell $flatten\dut.$procmux$727:
|
|
Old ports: A=$flatten\dut.$2$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$242_EN[63:0]$274, B=64'0000000000000000000000000000000000000000000000000000000000000000, Y=$flatten\dut.$0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$242_EN[63:0]$257
|
|
New ports: A=$flatten\dut.$procmux$676_Y [0], B=1'0, Y=$flatten\dut.$0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$242_EN[63:0]$257 [0]
|
|
New connections: $flatten\dut.$0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$242_EN[63:0]$257 [63:1] = { $flatten\dut.$0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$242_EN[63:0]$257 [0] $flatten\dut.$0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$242_EN[63:0]$257 [0] $flatten\dut.$0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$242_EN[63:0]$257 [0] $flatten\dut.$0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$242_EN[63:0]$257 [0] $flatten\dut.$0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$242_EN[63:0]$257 [0] $flatten\dut.$0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$242_EN[63:0]$257 [0] $flatten\dut.$0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$242_EN[63:0]$257 [0] $flatten\dut.$0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$242_EN[63:0]$257 [0] $flatten\dut.$0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$242_EN[63:0]$257 [0] $flatten\dut.$0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$242_EN[63:0]$257 [0] $flatten\dut.$0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$242_EN[63:0]$257 [0] $flatten\dut.$0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$242_EN[63:0]$257 [0] $flatten\dut.$0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$242_EN[63:0]$257 [0] $flatten\dut.$0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$242_EN[63:0]$257 [0] $flatten\dut.$0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$242_EN[63:0]$257 [0] $flatten\dut.$0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$242_EN[63:0]$257 [0] $flatten\dut.$0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$242_EN[63:0]$257 [0] $flatten\dut.$0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$242_EN[63:0]$257 [0] $flatten\dut.$0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$242_EN[63:0]$257 [0] $flatten\dut.$0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$242_EN[63:0]$257 [0] $flatten\dut.$0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$242_EN[63:0]$257 [0] $flatten\dut.$0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$242_EN[63:0]$257 [0] $flatten\dut.$0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$242_EN[63:0]$257 [0] $flatten\dut.$0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$242_EN[63:0]$257 [0] $flatten\dut.$0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$242_EN[63:0]$257 [0] $flatten\dut.$0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$242_EN[63:0]$257 [0] $flatten\dut.$0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$242_EN[63:0]$257 [0] $flatten\dut.$0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$242_EN[63:0]$257 [0] $flatten\dut.$0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$242_EN[63:0]$257 [0] $flatten\dut.$0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$242_EN[63:0]$257 [0] $flatten\dut.$0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$242_EN[63:0]$257 [0] $flatten\dut.$0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$242_EN[63:0]$257 [0] $flatten\dut.$0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$242_EN[63:0]$257 [0] $flatten\dut.$0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$242_EN[63:0]$257 [0] $flatten\dut.$0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$242_EN[63:0]$257 [0] $flatten\dut.$0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$242_EN[63:0]$257 [0] $flatten\dut.$0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$242_EN[63:0]$257 [0] $flatten\dut.$0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$242_EN[63:0]$257 [0] $flatten\dut.$0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$242_EN[63:0]$257 [0] $flatten\dut.$0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$242_EN[63:0]$257 [0] $flatten\dut.$0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$242_EN[63:0]$257 [0] $flatten\dut.$0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$242_EN[63:0]$257 [0] $flatten\dut.$0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$242_EN[63:0]$257 [0] $flatten\dut.$0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$242_EN[63:0]$257 [0] $flatten\dut.$0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$242_EN[63:0]$257 [0] $flatten\dut.$0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$242_EN[63:0]$257 [0] $flatten\dut.$0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$242_EN[63:0]$257 [0] $flatten\dut.$0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$242_EN[63:0]$257 [0] $flatten\dut.$0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$242_EN[63:0]$257 [0] $flatten\dut.$0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$242_EN[63:0]$257 [0] $flatten\dut.$0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$242_EN[63:0]$257 [0] $flatten\dut.$0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$242_EN[63:0]$257 [0] $flatten\dut.$0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$242_EN[63:0]$257 [0] $flatten\dut.$0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$242_EN[63:0]$257 [0] $flatten\dut.$0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$242_EN[63:0]$257 [0] $flatten\dut.$0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$242_EN[63:0]$257 [0] $flatten\dut.$0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$242_EN[63:0]$257 [0] $flatten\dut.$0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$242_EN[63:0]$257 [0] $flatten\dut.$0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$242_EN[63:0]$257 [0] $flatten\dut.$0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$242_EN[63:0]$257 [0] $flatten\dut.$0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$242_EN[63:0]$257 [0] $flatten\dut.$0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$242_EN[63:0]$257 [0] $flatten\dut.$0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$242_EN[63:0]$257 [0] }
|
|
Optimizing cells in module \harness_memory_manager.
|
|
Performed a total of 6 changes.
|
|
|
|
4.13.5. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\harness_memory_manager'.
|
|
Computing hashes of 297 cells of `\harness_memory_manager'.
|
|
Finding duplicate cells in `\harness_memory_manager'.
|
|
Computing hashes of 294 cells of `\harness_memory_manager'.
|
|
Finding duplicate cells in `\harness_memory_manager'.
|
|
Computing hashes of 292 cells of `\harness_memory_manager'.
|
|
Finding duplicate cells in `\harness_memory_manager'.
|
|
<suppressed ~15 debug messages>
|
|
Removed a total of 5 cells.
|
|
|
|
4.13.6. Executing OPT_DFF pass (perform DFF optimizations).
|
|
|
|
4.13.7. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \harness_memory_manager..
|
|
Removed 0 unused cells and 101 unused wires.
|
|
<suppressed ~1 debug messages>
|
|
|
|
4.13.8. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module harness_memory_manager.
|
|
|
|
4.13.9. Rerunning OPT passes. (Maybe there is more to do..)
|
|
|
|
4.13.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \harness_memory_manager..
|
|
Creating internal representation of mux trees.
|
|
Evaluating internal representation of mux trees.
|
|
Analyzing evaluation results.
|
|
Removed 0 multiplexer ports.
|
|
<suppressed ~229 debug messages>
|
|
|
|
4.13.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \harness_memory_manager.
|
|
Performed a total of 0 changes.
|
|
|
|
4.13.12. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\harness_memory_manager'.
|
|
Computing hashes of 292 cells of `\harness_memory_manager'.
|
|
Finding duplicate cells in `\harness_memory_manager'.
|
|
Removed a total of 0 cells.
|
|
|
|
4.13.13. Executing OPT_DFF pass (perform DFF optimizations).
|
|
|
|
4.13.14. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \harness_memory_manager..
|
|
|
|
4.13.15. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module harness_memory_manager.
|
|
|
|
4.13.16. Finished fast OPT passes. (There is nothing left to do.)
|
|
|
|
4.14. Executing FSM pass (extract and optimize FSM).
|
|
|
|
4.14.1. Executing FSM_DETECT pass (finding FSMs in design).
|
|
Found FSM state register harness_memory_manager.dut.state.
|
|
Found FSM state register harness_memory_manager.dut.u_prefetch.state.
|
|
Not marking harness_memory_manager.dut.u_prefetch.mem_wdata as FSM state register:
|
|
Users of register don't seem to benefit from recoding.
|
|
|
|
4.14.2. Executing FSM_EXTRACT pass (extracting FSM from design).
|
|
Extracting FSM `\dut.state' from module `\harness_memory_manager'.
|
|
found $dff cell for state register: $flatten\dut.$procdff$1106
|
|
root of input selection tree: $flatten\dut.$0\state[2:0]
|
|
found reset state: 3'000 (guessed from mux tree)
|
|
found ctrl input: \rst
|
|
found ctrl input: $flatten\dut.$eq$hardware/v2/rtl/memory_manager.v:151$245_Y
|
|
found ctrl input: $flatten\dut.$eq$hardware/v2/rtl/memory_manager.v:151$244_Y
|
|
found ctrl input: $flatten\dut.$procmux$705_CMP
|
|
found ctrl input: $flatten\dut.$procmux$1012_CMP
|
|
found ctrl input: $flatten\dut.$procmux$1015_CMP
|
|
found ctrl input: $flatten\dut.$procmux$1076_CMP
|
|
found state code: 3'000
|
|
found ctrl input: \lfsr [4]
|
|
found state code: 3'101
|
|
found ctrl input: $flatten\dut.$logic_and$hardware/v2/rtl/memory_manager.v:284$334_Y
|
|
found state code: 3'100
|
|
found ctrl input: $flatten\dut.$logic_and$hardware/v2/rtl/memory_manager.v:245$304_Y
|
|
found ctrl input: $flatten\dut.$eq$hardware/v2/rtl/memory_manager.v:252$317_Y
|
|
found state code: 3'011
|
|
found ctrl input: $flatten\dut.$logic_or$hardware/v2/rtl/memory_manager.v:227$295_Y
|
|
found state code: 3'010
|
|
found ctrl input: \lfsr [0]
|
|
found state code: 3'001
|
|
found ctrl output: $flatten\dut.$procmux$1015_CMP
|
|
found ctrl output: $flatten\dut.$eq$hardware/v2/rtl/memory_manager.v:151$244_Y
|
|
found ctrl output: $flatten\dut.$procmux$705_CMP
|
|
found ctrl output: $flatten\dut.$procmux$1076_CMP
|
|
found ctrl output: $flatten\dut.$procmux$1012_CMP
|
|
found ctrl output: $flatten\dut.$eq$hardware/v2/rtl/memory_manager.v:151$245_Y
|
|
ctrl inputs: { $flatten\dut.$logic_or$hardware/v2/rtl/memory_manager.v:227$295_Y $flatten\dut.$logic_and$hardware/v2/rtl/memory_manager.v:245$304_Y $flatten\dut.$eq$hardware/v2/rtl/memory_manager.v:252$317_Y $flatten\dut.$logic_and$hardware/v2/rtl/memory_manager.v:284$334_Y \lfsr [4] \lfsr [0] \rst }
|
|
ctrl outputs: { $flatten\dut.$eq$hardware/v2/rtl/memory_manager.v:151$244_Y $flatten\dut.$eq$hardware/v2/rtl/memory_manager.v:151$245_Y $flatten\dut.$0\state[2:0] $flatten\dut.$procmux$705_CMP $flatten\dut.$procmux$1012_CMP $flatten\dut.$procmux$1015_CMP $flatten\dut.$procmux$1076_CMP }
|
|
transition: 3'000 7'-----00 -> 3'000 9'000000001
|
|
transition: 3'000 7'-----10 -> 3'001 9'000010001
|
|
transition: 3'000 7'------1 -> 3'000 9'000000001
|
|
transition: 3'100 7'------0 -> 3'101 9'101010000
|
|
transition: 3'100 7'------1 -> 3'000 9'100000000
|
|
transition: 3'010 7'-0----0 -> 3'010 9'000100100
|
|
transition: 3'010 7'-10---0 -> 3'010 9'000100100
|
|
transition: 3'010 7'-11---0 -> 3'011 9'000110100
|
|
transition: 3'010 7'------1 -> 3'000 9'000000100
|
|
transition: 3'001 7'0-----0 -> 3'001 9'000010010
|
|
transition: 3'001 7'1-----0 -> 3'010 9'000100010
|
|
transition: 3'001 7'------1 -> 3'000 9'000000010
|
|
transition: 3'101 7'----0-0 -> 3'101 9'011010000
|
|
transition: 3'101 7'----1-0 -> 3'000 9'010000000
|
|
transition: 3'101 7'------1 -> 3'000 9'010000000
|
|
transition: 3'011 7'---0--0 -> 3'011 9'000111000
|
|
transition: 3'011 7'---1--0 -> 3'100 9'001001000
|
|
transition: 3'011 7'------1 -> 3'000 9'000001000
|
|
Extracting FSM `\dut.u_prefetch.state' from module `\harness_memory_manager'.
|
|
found $dff cell for state register: $flatten\dut.\u_prefetch.$procdff$1090
|
|
root of input selection tree: $flatten\dut.\u_prefetch.$0\state[1:0]
|
|
found reset state: 2'00 (guessed from mux tree)
|
|
found ctrl input: \rst
|
|
found ctrl input: $flatten\dut.\u_prefetch.$procmux$421_CMP
|
|
found ctrl input: $flatten\dut.\u_prefetch.$procmux$387_CMP
|
|
found ctrl input: $flatten\dut.\u_prefetch.$procmux$406_CMP
|
|
found ctrl input: $flatten\dut.\u_prefetch.$procmux$424_CMP
|
|
found state code: 2'00
|
|
found ctrl input: \lfsr [4]
|
|
found ctrl input: $flatten\dut.\u_prefetch.$eq$hardware/v2/rtl/prefetch_engine.v:106$378_Y
|
|
found state code: 2'11
|
|
found state code: 2'10
|
|
found ctrl input: \dut.pf_start
|
|
found state code: 2'01
|
|
found ctrl output: $flatten\dut.\u_prefetch.$procmux$421_CMP
|
|
found ctrl output: $flatten\dut.\u_prefetch.$procmux$387_CMP
|
|
found ctrl output: $flatten\dut.\u_prefetch.$procmux$406_CMP
|
|
found ctrl output: $flatten\dut.\u_prefetch.$procmux$424_CMP
|
|
ctrl inputs: { \dut.pf_start $flatten\dut.\u_prefetch.$eq$hardware/v2/rtl/prefetch_engine.v:106$378_Y \lfsr [4] \rst }
|
|
ctrl outputs: { $flatten\dut.\u_prefetch.$procmux$424_CMP $flatten\dut.\u_prefetch.$procmux$421_CMP $flatten\dut.\u_prefetch.$procmux$406_CMP $flatten\dut.\u_prefetch.$procmux$387_CMP $flatten\dut.\u_prefetch.$0\state[1:0] }
|
|
transition: 2'00 4'0--0 -> 2'00 6'100000
|
|
transition: 2'00 4'1--0 -> 2'01 6'100001
|
|
transition: 2'00 4'---1 -> 2'00 6'100000
|
|
transition: 2'10 4'--00 -> 2'10 6'000110
|
|
transition: 2'10 4'-010 -> 2'10 6'000110
|
|
transition: 2'10 4'-110 -> 2'11 6'000111
|
|
transition: 2'10 4'---1 -> 2'00 6'000100
|
|
transition: 2'01 4'--00 -> 2'01 6'001001
|
|
transition: 2'01 4'-010 -> 2'01 6'001001
|
|
transition: 2'01 4'-110 -> 2'10 6'001010
|
|
transition: 2'01 4'---1 -> 2'00 6'001000
|
|
transition: 2'11 4'---0 -> 2'00 6'010000
|
|
transition: 2'11 4'---1 -> 2'00 6'010000
|
|
|
|
4.14.3. Executing FSM_OPT pass (simple optimizations of FSMs).
|
|
Optimizing FSM `$fsm$\dut.u_prefetch.state$1152' from module `\harness_memory_manager'.
|
|
Merging pattern 4'---0 and 4'---1 from group (3 0 6'010000).
|
|
Merging pattern 4'---1 and 4'---0 from group (3 0 6'010000).
|
|
Optimizing FSM `$fsm$\dut.state$1144' from module `\harness_memory_manager'.
|
|
|
|
4.14.4. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \harness_memory_manager..
|
|
Removed 27 unused cells and 27 unused wires.
|
|
<suppressed ~28 debug messages>
|
|
|
|
4.14.5. Executing FSM_OPT pass (simple optimizations of FSMs).
|
|
Optimizing FSM `$fsm$\dut.state$1144' from module `\harness_memory_manager'.
|
|
Removing unused output signal $flatten\dut.$0\state[2:0] [0].
|
|
Removing unused output signal $flatten\dut.$0\state[2:0] [1].
|
|
Removing unused output signal $flatten\dut.$0\state[2:0] [2].
|
|
Optimizing FSM `$fsm$\dut.u_prefetch.state$1152' from module `\harness_memory_manager'.
|
|
Removing unused output signal $flatten\dut.\u_prefetch.$0\state[1:0] [0].
|
|
Removing unused output signal $flatten\dut.\u_prefetch.$0\state[1:0] [1].
|
|
|
|
4.14.6. Executing FSM_RECODE pass (re-assigning FSM state encoding).
|
|
Recoding FSM `$fsm$\dut.state$1144' from module `\harness_memory_manager' using `auto' encoding:
|
|
mapping auto encoding to `one-hot` for this FSM.
|
|
000 -> -----1
|
|
100 -> ----1-
|
|
010 -> ---1--
|
|
001 -> --1---
|
|
101 -> -1----
|
|
011 -> 1-----
|
|
Recoding FSM `$fsm$\dut.u_prefetch.state$1152' from module `\harness_memory_manager' using `auto' encoding:
|
|
mapping auto encoding to `one-hot` for this FSM.
|
|
00 -> ---1
|
|
10 -> --1-
|
|
01 -> -1--
|
|
11 -> 1---
|
|
|
|
4.14.7. Executing FSM_INFO pass (dumping all available information on FSM cells).
|
|
|
|
FSM `$fsm$\dut.state$1144' from module `harness_memory_manager':
|
|
-------------------------------------
|
|
|
|
Information on FSM $fsm$\dut.state$1144 (\dut.state):
|
|
|
|
Number of input signals: 7
|
|
Number of output signals: 6
|
|
Number of state bits: 6
|
|
|
|
Input signals:
|
|
0: \rst
|
|
1: \lfsr [0]
|
|
2: \lfsr [4]
|
|
3: $flatten\dut.$logic_and$hardware/v2/rtl/memory_manager.v:284$334_Y
|
|
4: $flatten\dut.$eq$hardware/v2/rtl/memory_manager.v:252$317_Y
|
|
5: $flatten\dut.$logic_and$hardware/v2/rtl/memory_manager.v:245$304_Y
|
|
6: $flatten\dut.$logic_or$hardware/v2/rtl/memory_manager.v:227$295_Y
|
|
|
|
Output signals:
|
|
0: $flatten\dut.$procmux$1076_CMP
|
|
1: $flatten\dut.$procmux$1015_CMP
|
|
2: $flatten\dut.$procmux$1012_CMP
|
|
3: $flatten\dut.$procmux$705_CMP
|
|
4: $flatten\dut.$eq$hardware/v2/rtl/memory_manager.v:151$245_Y
|
|
5: $flatten\dut.$eq$hardware/v2/rtl/memory_manager.v:151$244_Y
|
|
|
|
State encoding:
|
|
0: 6'-----1 <RESET STATE>
|
|
1: 6'----1-
|
|
2: 6'---1--
|
|
3: 6'--1---
|
|
4: 6'-1----
|
|
5: 6'1-----
|
|
|
|
Transition Table (state_in, ctrl_in, state_out, ctrl_out):
|
|
0: 0 7'-----00 -> 0 6'000001
|
|
1: 0 7'------1 -> 0 6'000001
|
|
2: 0 7'-----10 -> 3 6'000001
|
|
3: 1 7'------1 -> 0 6'100000
|
|
4: 1 7'------0 -> 4 6'100000
|
|
5: 2 7'------1 -> 0 6'000100
|
|
6: 2 7'-10---0 -> 2 6'000100
|
|
7: 2 7'-0----0 -> 2 6'000100
|
|
8: 2 7'-11---0 -> 5 6'000100
|
|
9: 3 7'------1 -> 0 6'000010
|
|
10: 3 7'1-----0 -> 2 6'000010
|
|
11: 3 7'0-----0 -> 3 6'000010
|
|
12: 4 7'----1-0 -> 0 6'010000
|
|
13: 4 7'------1 -> 0 6'010000
|
|
14: 4 7'----0-0 -> 4 6'010000
|
|
15: 5 7'------1 -> 0 6'001000
|
|
16: 5 7'---1--0 -> 1 6'001000
|
|
17: 5 7'---0--0 -> 5 6'001000
|
|
|
|
-------------------------------------
|
|
|
|
FSM `$fsm$\dut.u_prefetch.state$1152' from module `harness_memory_manager':
|
|
-------------------------------------
|
|
|
|
Information on FSM $fsm$\dut.u_prefetch.state$1152 (\dut.u_prefetch.state):
|
|
|
|
Number of input signals: 4
|
|
Number of output signals: 4
|
|
Number of state bits: 4
|
|
|
|
Input signals:
|
|
0: \rst
|
|
1: \lfsr [4]
|
|
2: $flatten\dut.\u_prefetch.$eq$hardware/v2/rtl/prefetch_engine.v:106$378_Y
|
|
3: \dut.pf_start
|
|
|
|
Output signals:
|
|
0: $flatten\dut.\u_prefetch.$procmux$387_CMP
|
|
1: $flatten\dut.\u_prefetch.$procmux$406_CMP
|
|
2: $flatten\dut.\u_prefetch.$procmux$421_CMP
|
|
3: $flatten\dut.\u_prefetch.$procmux$424_CMP
|
|
|
|
State encoding:
|
|
0: 4'---1 <RESET STATE>
|
|
1: 4'--1-
|
|
2: 4'-1--
|
|
3: 4'1---
|
|
|
|
Transition Table (state_in, ctrl_in, state_out, ctrl_out):
|
|
0: 0 4'0--0 -> 0 4'1000
|
|
1: 0 4'---1 -> 0 4'1000
|
|
2: 0 4'1--0 -> 2 4'1000
|
|
3: 1 4'---1 -> 0 4'0001
|
|
4: 1 4'--00 -> 1 4'0001
|
|
5: 1 4'-010 -> 1 4'0001
|
|
6: 1 4'-110 -> 3 4'0001
|
|
7: 2 4'---1 -> 0 4'0010
|
|
8: 2 4'-110 -> 1 4'0010
|
|
9: 2 4'--00 -> 2 4'0010
|
|
10: 2 4'-010 -> 2 4'0010
|
|
11: 3 4'---- -> 0 4'0100
|
|
|
|
-------------------------------------
|
|
|
|
4.14.8. Executing FSM_MAP pass (mapping FSMs to basic logic).
|
|
Mapping FSM `$fsm$\dut.state$1144' from module `\harness_memory_manager'.
|
|
Mapping FSM `$fsm$\dut.u_prefetch.state$1152' from module `\harness_memory_manager'.
|
|
|
|
4.15. Executing OPT pass (performing simple optimizations).
|
|
|
|
4.15.1. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module harness_memory_manager.
|
|
<suppressed ~11 debug messages>
|
|
|
|
4.15.2. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\harness_memory_manager'.
|
|
Computing hashes of 315 cells of `\harness_memory_manager'.
|
|
Finding duplicate cells in `\harness_memory_manager'.
|
|
Computing hashes of 311 cells of `\harness_memory_manager'.
|
|
Finding duplicate cells in `\harness_memory_manager'.
|
|
<suppressed ~12 debug messages>
|
|
Removed a total of 4 cells.
|
|
|
|
4.15.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \harness_memory_manager..
|
|
Creating internal representation of mux trees.
|
|
Evaluating internal representation of mux trees.
|
|
Analyzing evaluation results.
|
|
Removed 0 multiplexer ports.
|
|
<suppressed ~212 debug messages>
|
|
|
|
4.15.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \harness_memory_manager.
|
|
Performed a total of 0 changes.
|
|
|
|
4.15.5. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\harness_memory_manager'.
|
|
Computing hashes of 311 cells of `\harness_memory_manager'.
|
|
Finding duplicate cells in `\harness_memory_manager'.
|
|
Removed a total of 0 cells.
|
|
|
|
4.15.6. Executing OPT_DFF pass (perform DFF optimizations).
|
|
Adding SRST signal on $procdff$1135 ($dff) from module harness_memory_manager (D = { \lfsr [30:7] $xor$hardware/v2/synthesis/harness_memory_manager.v:26$230_Y }, Q = { \lfsr [31:8] \lfsr [0] }, rval = 25'0000000000000000000000001).
|
|
Adding SRST signal on $procdff$1134 ($dff) from module harness_memory_manager (D = $xor$hardware/v2/synthesis/harness_memory_manager.v:65$239_Y, Q = \chk, rval = 8'00000000).
|
|
Adding SRST signal on $flatten\dut.\u_prefetch.$procdff$1086 ($dff) from module harness_memory_manager (D = $flatten\dut.\u_prefetch.$procmux$459_Y, Q = \dut.u_prefetch.mem_req, rval = 1'0).
|
|
Adding SRST signal on $flatten\dut.\u_prefetch.$procdff$1087 ($dff) from module harness_memory_manager (D = $flatten\dut.\u_prefetch.$procmux$574_Y, Q = \dut.u_prefetch.mem_wr, rval = 1'0).
|
|
Adding EN signal on $auto$ff.cc:337:slice$1262 ($sdff) from module harness_memory_manager (D = $flatten\dut.\u_prefetch.$procmux$574_Y, Q = \dut.u_prefetch.mem_wr).
|
|
Adding SRST signal on $flatten\dut.\u_prefetch.$procdff$1088 ($dff) from module harness_memory_manager (D = $flatten\dut.\u_prefetch.$procmux$552_Y, Q = \dut.u_prefetch.mem_addr, rval = 23'00000000000000000000000).
|
|
Adding EN signal on $auto$ff.cc:337:slice$1276 ($sdff) from module harness_memory_manager (D = $flatten\dut.\u_prefetch.$procmux$552_Y, Q = \dut.u_prefetch.mem_addr).
|
|
Adding EN signal on $flatten\dut.\u_prefetch.$procdff$1089 ($dff) from module harness_memory_manager (D = 8'00000000, Q = \dut.u_prefetch.mem_wdata).
|
|
Adding SRST signal on $flatten\dut.\u_prefetch.$procdff$1091 ($dff) from module harness_memory_manager (D = $flatten\dut.\u_prefetch.$procmux$512_Y, Q = \dut.u_prefetch.fetch_busy, rval = 1'0).
|
|
Adding EN signal on $auto$ff.cc:337:slice$1291 ($sdff) from module harness_memory_manager (D = $flatten\dut.\u_prefetch.$procmux$512_Y, Q = \dut.u_prefetch.fetch_busy).
|
|
Adding SRST signal on $flatten\dut.\u_prefetch.$procdff$1092 ($dff) from module harness_memory_manager (D = $flatten\dut.\u_prefetch.$procmux$473_Y, Q = \dut.u_prefetch.fetch_done, rval = 1'0).
|
|
Adding EN signal on $flatten\dut.\u_prefetch.$procdff$1093 ($dff) from module harness_memory_manager (D = $flatten\dut.\u_prefetch.$2$lookahead\tile_x$337[63:0]$350, Q = \dut.u_prefetch.tile_x).
|
|
Adding EN signal on $flatten\dut.\u_prefetch.$procdff$1094 ($dff) from module harness_memory_manager (D = $flatten\dut.\u_prefetch.$2$lookahead\tile_w$338[63:0]$351, Q = \dut.u_prefetch.tile_w).
|
|
Adding SRST signal on $flatten\dut.\u_prefetch.$procdff$1095 ($dff) from module harness_memory_manager (D = $flatten\dut.\u_prefetch.$procmux$497_Y, Q = \dut.u_prefetch.byte_idx, rval = 4'0000).
|
|
Adding EN signal on $auto$ff.cc:337:slice$1318 ($sdff) from module harness_memory_manager (D = $flatten\dut.\u_prefetch.$procmux$497_Y, Q = \dut.u_prefetch.byte_idx).
|
|
Adding SRST signal on $flatten\dut.$procdff$1124 ($dff) from module harness_memory_manager (D = $flatten\dut.$procmux$746_Y, Q = \dut.wr_mem_wdata, rval = 8'00000000).
|
|
Adding EN signal on $auto$ff.cc:337:slice$1332 ($sdff) from module harness_memory_manager (D = \lfsr [7:0], Q = \dut.wr_mem_wdata).
|
|
Adding SRST signal on $flatten\dut.$procdff$1123 ($dff) from module harness_memory_manager (D = $flatten\dut.$procmux$753_Y, Q = \dut.wr_mem_addr, rval = 23'00000000000000000000000).
|
|
Adding EN signal on $auto$ff.cc:337:slice$1336 ($sdff) from module harness_memory_manager (D = \dut.result_addr_reg, Q = \dut.wr_mem_addr).
|
|
Adding SRST signal on $flatten\dut.$procdff$1122 ($dff) from module harness_memory_manager (D = $flatten\dut.$procmux$759_Y, Q = \dut.wr_mem_req, rval = 1'0).
|
|
Adding EN signal on $auto$ff.cc:337:slice$1338 ($sdff) from module harness_memory_manager (D = $flatten\dut.$procmux$759_Y, Q = \dut.wr_mem_req).
|
|
Adding EN signal on $flatten\dut.$procdff$1121 ($dff) from module harness_memory_manager (D = $flatten\dut.$procmux$777_Y, Q = \dut.pf_pending_bank).
|
|
Adding EN signal on $flatten\dut.$procdff$1120 ($dff) from module harness_memory_manager (D = $flatten\dut.$procmux$803_Y, Q = \dut.pf_pending_w).
|
|
Adding EN signal on $flatten\dut.$procdff$1119 ($dff) from module harness_memory_manager (D = $flatten\dut.$procmux$829_Y, Q = \dut.pf_pending_x).
|
|
Adding SRST signal on $flatten\dut.$procdff$1118 ($dff) from module harness_memory_manager (D = $flatten\dut.$procmux$857_Y, Q = \dut.pf_pending, rval = 1'0).
|
|
Adding EN signal on $flatten\dut.$procdff$1117 ($dff) from module harness_memory_manager (D = \dut.pf_pending_bank, Q = \dut.pf_target_bank).
|
|
Adding EN signal on $flatten\dut.$procdff$1116 ($dff) from module harness_memory_manager (D = \dut.pf_pending_w, Q = \dut.pf_w_addr).
|
|
Adding EN signal on $flatten\dut.$procdff$1115 ($dff) from module harness_memory_manager (D = \dut.pf_pending_x, Q = \dut.pf_x_addr).
|
|
Adding SRST signal on $flatten\dut.$procdff$1114 ($dff) from module harness_memory_manager (D = $flatten\dut.$procmux$696_Y, Q = \dut.pf_start, rval = 1'0).
|
|
Adding SRST signal on $flatten\dut.$procdff$1113 ($dff) from module harness_memory_manager (D = $flatten\dut.$3$lookahead\bank_ready$251[1:0]$291, Q = \dut.bank_ready, rval = 2'00).
|
|
Adding SRST signal on $flatten\dut.$procdff$1112 ($dff) from module harness_memory_manager (D = $flatten\dut.$procmux$893_Y, Q = \dut.current_bank, rval = 1'0).
|
|
Adding EN signal on $auto$ff.cc:337:slice$1417 ($sdff) from module harness_memory_manager (D = $flatten\dut.$procmux$893_Y, Q = \dut.current_bank).
|
|
Adding SRST signal on $flatten\dut.$procdff$1111 ($dff) from module harness_memory_manager (D = $flatten\dut.$procmux$909_Y, Q = \dut.tile_idx, rval = 16'0000000000000000).
|
|
Adding EN signal on $auto$ff.cc:337:slice$1427 ($sdff) from module harness_memory_manager (D = $flatten\dut.$procmux$909_Y, Q = \dut.tile_idx).
|
|
Adding EN signal on $flatten\dut.$procdff$1110 ($dff) from module harness_memory_manager (D = { \lfsr [15:1] 1'1 }, Q = \dut.n_tiles_reg).
|
|
Adding EN signal on $flatten\dut.$procdff$1109 ($dff) from module harness_memory_manager (D = { \lfsr [3:1] 1'1 \lfsr [18:1] 1'1 }, Q = \dut.result_addr_reg).
|
|
Adding EN signal on $flatten\dut.$procdff$1108 ($dff) from module harness_memory_manager (D = { \lfsr [7:1] 1'1 \lfsr [14:1] 1'1 }, Q = \dut.w_base_reg).
|
|
Adding EN signal on $flatten\dut.$procdff$1107 ($dff) from module harness_memory_manager (D = { \lfsr [22:1] 1'1 }, Q = \dut.x_base_reg).
|
|
Adding SRST signal on $flatten\dut.$procdff$1105 ($dff) from module harness_memory_manager (D = $flatten\dut.$procmux$704_Y, Q = \dut.result_ready, rval = 1'0).
|
|
Adding SRST signal on $flatten\dut.$procdff$1104 ($dff) from module harness_memory_manager (D = $flatten\dut.$procmux$1011_Y, Q = \dut.tile_last, rval = 1'0).
|
|
Adding EN signal on $auto$ff.cc:337:slice$1458 ($sdff) from module harness_memory_manager (D = $flatten\dut.$procmux$1011_Y, Q = \dut.tile_last).
|
|
Adding SRST signal on $flatten\dut.$procdff$1103 ($dff) from module harness_memory_manager (D = $flatten\dut.$procmux$1030_Y, Q = \dut.weight_data, rval = 64'0000000000000000000000000000000000000000000000000000000000000000).
|
|
Adding EN signal on $auto$ff.cc:337:slice$1472 ($sdff) from module harness_memory_manager (D = $flatten\dut.$procmux$1030_Y, Q = \dut.weight_data).
|
|
Adding SRST signal on $flatten\dut.$procdff$1102 ($dff) from module harness_memory_manager (D = $flatten\dut.$procmux$1049_Y, Q = \dut.input_data, rval = 64'0000000000000000000000000000000000000000000000000000000000000000).
|
|
Adding EN signal on $auto$ff.cc:337:slice$1486 ($sdff) from module harness_memory_manager (D = $flatten\dut.$procmux$1049_Y, Q = \dut.input_data).
|
|
Adding SRST signal on $flatten\dut.$procdff$1101 ($dff) from module harness_memory_manager (D = $flatten\dut.$procmux$1068_Y, Q = \dut.operand_valid, rval = 1'0).
|
|
Adding EN signal on $auto$ff.cc:337:slice$1500 ($sdff) from module harness_memory_manager (D = $flatten\dut.$procmux$1068_Y, Q = \dut.operand_valid).
|
|
Adding SRST signal on $flatten\dut.$procdff$1100 ($dff) from module harness_memory_manager (D = $flatten\dut.$procmux$710_Y, Q = \dut.job_done, rval = 1'0).
|
|
Setting constant 1-bit at position 0 on $auto$ff.cc:337:slice$1452 ($dffe) from module harness_memory_manager.
|
|
Setting constant 1-bit at position 0 on $auto$ff.cc:337:slice$1447 ($dffe) from module harness_memory_manager.
|
|
Setting constant 1-bit at position 15 on $auto$ff.cc:337:slice$1447 ($dffe) from module harness_memory_manager.
|
|
Setting constant 1-bit at position 0 on $auto$ff.cc:337:slice$1442 ($dffe) from module harness_memory_manager.
|
|
Setting constant 1-bit at position 19 on $auto$ff.cc:337:slice$1442 ($dffe) from module harness_memory_manager.
|
|
Setting constant 1-bit at position 0 on $auto$ff.cc:337:slice$1437 ($dffe) from module harness_memory_manager.
|
|
Setting constant 0-bit at position 0 on $auto$ff.cc:337:slice$1290 ($dffe) from module harness_memory_manager.
|
|
Setting constant 0-bit at position 1 on $auto$ff.cc:337:slice$1290 ($dffe) from module harness_memory_manager.
|
|
Setting constant 0-bit at position 2 on $auto$ff.cc:337:slice$1290 ($dffe) from module harness_memory_manager.
|
|
Setting constant 0-bit at position 3 on $auto$ff.cc:337:slice$1290 ($dffe) from module harness_memory_manager.
|
|
Setting constant 0-bit at position 4 on $auto$ff.cc:337:slice$1290 ($dffe) from module harness_memory_manager.
|
|
Setting constant 0-bit at position 5 on $auto$ff.cc:337:slice$1290 ($dffe) from module harness_memory_manager.
|
|
Setting constant 0-bit at position 6 on $auto$ff.cc:337:slice$1290 ($dffe) from module harness_memory_manager.
|
|
Setting constant 0-bit at position 7 on $auto$ff.cc:337:slice$1290 ($dffe) from module harness_memory_manager.
|
|
|
|
4.15.7. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \harness_memory_manager..
|
|
Removed 49 unused cells and 71 unused wires.
|
|
<suppressed ~50 debug messages>
|
|
|
|
4.15.8. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module harness_memory_manager.
|
|
<suppressed ~17 debug messages>
|
|
|
|
4.15.9. Rerunning OPT passes. (Maybe there is more to do..)
|
|
|
|
4.15.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \harness_memory_manager..
|
|
Creating internal representation of mux trees.
|
|
Evaluating internal representation of mux trees.
|
|
Analyzing evaluation results.
|
|
Removed 0 multiplexer ports.
|
|
<suppressed ~149 debug messages>
|
|
|
|
4.15.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \harness_memory_manager.
|
|
New ctrl vector for $pmux cell $flatten\dut.\u_prefetch.$procmux$428: \dut.u_prefetch.state [2]
|
|
New ctrl vector for $pmux cell $flatten\dut.\u_prefetch.$procmux$420: \dut.u_prefetch.state [1]
|
|
Optimizing cells in module \harness_memory_manager.
|
|
Performed a total of 2 changes.
|
|
|
|
4.15.12. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\harness_memory_manager'.
|
|
Computing hashes of 366 cells of `\harness_memory_manager'.
|
|
Finding duplicate cells in `\harness_memory_manager'.
|
|
Computing hashes of 306 cells of `\harness_memory_manager'.
|
|
Finding duplicate cells in `\harness_memory_manager'.
|
|
Computing hashes of 294 cells of `\harness_memory_manager'.
|
|
Finding duplicate cells in `\harness_memory_manager'.
|
|
<suppressed ~216 debug messages>
|
|
Removed a total of 72 cells.
|
|
|
|
4.15.13. Executing OPT_DFF pass (perform DFF optimizations).
|
|
|
|
4.15.14. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \harness_memory_manager..
|
|
Removed 0 unused cells and 72 unused wires.
|
|
<suppressed ~1 debug messages>
|
|
|
|
4.15.15. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module harness_memory_manager.
|
|
|
|
4.15.16. Rerunning OPT passes. (Maybe there is more to do..)
|
|
|
|
4.15.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \harness_memory_manager..
|
|
Creating internal representation of mux trees.
|
|
Evaluating internal representation of mux trees.
|
|
Analyzing evaluation results.
|
|
Removed 0 multiplexer ports.
|
|
<suppressed ~151 debug messages>
|
|
|
|
4.15.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \harness_memory_manager.
|
|
Performed a total of 0 changes.
|
|
|
|
4.15.19. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\harness_memory_manager'.
|
|
Computing hashes of 294 cells of `\harness_memory_manager'.
|
|
Finding duplicate cells in `\harness_memory_manager'.
|
|
Removed a total of 0 cells.
|
|
|
|
4.15.20. Executing OPT_DFF pass (perform DFF optimizations).
|
|
|
|
4.15.21. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \harness_memory_manager..
|
|
|
|
4.15.22. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module harness_memory_manager.
|
|
|
|
4.15.23. Finished fast OPT passes. (There is nothing left to do.)
|
|
|
|
4.16. Executing WREDUCE pass (reducing word size of cells).
|
|
Removed top 31 address bits (of 32) from memory read port harness_memory_manager.$flatten\dut.$memrd$\bank_w$hardware/v2/rtl/memory_manager.v:232$298 (dut.bank_w).
|
|
Removed top 31 address bits (of 32) from memory read port harness_memory_manager.$flatten\dut.$memrd$\bank_x$hardware/v2/rtl/memory_manager.v:231$296 (dut.bank_x).
|
|
Removed top 56 bits (of 64) from FF cell harness_memory_manager.$auto$ff.cc:337:slice$1487 ($sdffe).
|
|
Removed top 56 bits (of 64) from FF cell harness_memory_manager.$auto$ff.cc:337:slice$1473 ($sdffe).
|
|
Removed top 1 bits (of 2) from port B of cell harness_memory_manager.$auto$opt_dff.cc:320:make_patterns_logic$1327 ($ne).
|
|
Removed top 1 bits (of 3) from port B of cell harness_memory_manager.$auto$fsm_map.cc:77:implement_pattern_cache$1246 ($eq).
|
|
Removed top 7 bits (of 8) from port B of cell harness_memory_manager.$xor$hardware/v2/synthesis/harness_memory_manager.v:65$234 ($xor).
|
|
Removed top 6 bits (of 8) from port B of cell harness_memory_manager.$xor$hardware/v2/synthesis/harness_memory_manager.v:65$235 ($xor).
|
|
Removed top 7 bits (of 8) from port B of cell harness_memory_manager.$xor$hardware/v2/synthesis/harness_memory_manager.v:65$237 ($xor).
|
|
Removed top 7 bits (of 8) from port B of cell harness_memory_manager.$xor$hardware/v2/synthesis/harness_memory_manager.v:65$238 ($xor).
|
|
Removed top 24 bits (of 32) from mux cell harness_memory_manager.$procmux$1084 ($mux).
|
|
Removed top 25 bits (of 33) from port A of cell harness_memory_manager.$flatten\dut.\u_prefetch.$neg$hardware/v2/rtl/prefetch_engine.v:105$375 ($neg).
|
|
Converting cell harness_memory_manager.$flatten\dut.\u_prefetch.$neg$hardware/v2/rtl/prefetch_engine.v:105$375 ($neg) from signed to unsigned.
|
|
Removed top 1 bits (of 8) from port A of cell harness_memory_manager.$flatten\dut.\u_prefetch.$neg$hardware/v2/rtl/prefetch_engine.v:105$375 ($neg).
|
|
Removed top 1 bits (of 4) from port B of cell harness_memory_manager.$flatten\dut.\u_prefetch.$eq$hardware/v2/rtl/prefetch_engine.v:106$378 ($eq).
|
|
Removed top 56 bits (of 64) from mux cell harness_memory_manager.$flatten\dut.$procmux$1049 ($pmux).
|
|
Removed top 56 bits (of 64) from mux cell harness_memory_manager.$flatten\dut.$procmux$1047 ($mux).
|
|
Removed top 56 bits (of 64) from mux cell harness_memory_manager.$flatten\dut.$procmux$1044 ($mux).
|
|
Removed top 56 bits (of 64) from mux cell harness_memory_manager.$flatten\dut.$procmux$1042 ($mux).
|
|
Removed top 56 bits (of 64) from mux cell harness_memory_manager.$flatten\dut.$procmux$1030 ($pmux).
|
|
Removed top 56 bits (of 64) from mux cell harness_memory_manager.$flatten\dut.$procmux$1028 ($mux).
|
|
Removed top 56 bits (of 64) from mux cell harness_memory_manager.$flatten\dut.$procmux$1025 ($mux).
|
|
Removed top 56 bits (of 64) from mux cell harness_memory_manager.$flatten\dut.$procmux$1023 ($mux).
|
|
Removed top 15 bits (of 16) from port B of cell harness_memory_manager.$flatten\dut.$sub$hardware/v2/rtl/memory_manager.v:277$332 ($sub).
|
|
Removed top 14 bits (of 16) from port B of cell harness_memory_manager.$flatten\dut.$add$hardware/v2/rtl/memory_manager.v:266$323 ($add).
|
|
Removed top 6 bits (of 23) from port Y of cell harness_memory_manager.$flatten\dut.$add$hardware/v2/rtl/memory_manager.v:266$323 ($add).
|
|
Removed top 3 bits (of 23) from port B of cell harness_memory_manager.$flatten\dut.$add$hardware/v2/rtl/memory_manager.v:265$322 ($add).
|
|
Removed top 14 bits (of 16) from port B of cell harness_memory_manager.$flatten\dut.$add$hardware/v2/rtl/memory_manager.v:255$318 ($add).
|
|
Removed top 15 bits (of 16) from port B of cell harness_memory_manager.$flatten\dut.$add$hardware/v2/rtl/memory_manager.v:252$316 ($add).
|
|
Converting cell harness_memory_manager.$flatten\dut.$neg$hardware/v2/rtl/memory_manager.v:247$311 ($neg) from signed to unsigned.
|
|
Removed top 1 bits (of 2) from port A of cell harness_memory_manager.$flatten\dut.$neg$hardware/v2/rtl/memory_manager.v:247$311 ($neg).
|
|
Removed top 19 bits (of 23) from port B of cell harness_memory_manager.$flatten\dut.$add$hardware/v2/rtl/memory_manager.v:237$303 ($add).
|
|
Removed top 19 bits (of 23) from port B of cell harness_memory_manager.$flatten\dut.$add$hardware/v2/rtl/memory_manager.v:236$302 ($add).
|
|
Removed top 15 bits (of 16) from port B of cell harness_memory_manager.$flatten\dut.$gt$hardware/v2/rtl/memory_manager.v:234$301 ($gt).
|
|
Converting cell harness_memory_manager.$flatten\dut.$neg$hardware/v2/rtl/memory_manager.v:183$283 ($neg) from signed to unsigned.
|
|
Removed top 1 bits (of 2) from port A of cell harness_memory_manager.$flatten\dut.$neg$hardware/v2/rtl/memory_manager.v:183$283 ($neg).
|
|
Removed top 15 bits (of 23) from mux cell harness_memory_manager.$flatten\dut.$ternary$hardware/v2/rtl/memory_manager.v:154$249 ($mux).
|
|
Removed top 15 bits (of 23) from FF cell harness_memory_manager.$auto$ff.cc:337:slice$1337 ($sdffe).
|
|
Removed top 15 bits (of 23) from FF cell harness_memory_manager.$auto$ff.cc:337:slice$1277 ($sdffe).
|
|
Removed top 56 bits (of 64) from mux cell harness_memory_manager.$flatten\dut.$procmux$1051 ($mux).
|
|
Removed top 56 bits (of 64) from mux cell harness_memory_manager.$flatten\dut.$procmux$1032 ($mux).
|
|
Removed top 14 bits (of 21) from FF cell harness_memory_manager.$auto$ff.cc:337:slice$1517 ($dffe).
|
|
Removed top 15 bits (of 23) from mux cell harness_memory_manager.$flatten\dut.\u_prefetch.$procmux$552 ($pmux).
|
|
Removed top 56 bits (of 64) from mux cell harness_memory_manager.$flatten\dut.$ternary$hardware/v2/rtl/memory_manager.v:232$299 ($mux).
|
|
Removed top 56 bits (of 64) from mux cell harness_memory_manager.$flatten\dut.$ternary$hardware/v2/rtl/memory_manager.v:231$297 ($mux).
|
|
Removed top 15 bits (of 23) from mux cell harness_memory_manager.$flatten\dut.\u_prefetch.$procmux$550 ($mux).
|
|
Removed top 15 bits (of 23) from mux cell harness_memory_manager.$flatten\dut.\u_prefetch.$procmux$558 ($mux).
|
|
Removed top 15 bits (of 23) from mux cell harness_memory_manager.$flatten\dut.\u_prefetch.$procmux$561 ($mux).
|
|
Removed top 15 bits (of 23) from mux cell harness_memory_manager.$flatten\dut.\u_prefetch.$procmux$548 ($mux).
|
|
Removed top 15 bits (of 23) from mux cell harness_memory_manager.$flatten\dut.\u_prefetch.$procmux$556 ($mux).
|
|
Removed top 15 bits (of 23) from port Y of cell harness_memory_manager.$flatten\dut.\u_prefetch.$add$hardware/v2/rtl/prefetch_engine.v:98$366 ($add).
|
|
Removed top 15 bits (of 23) from port A of cell harness_memory_manager.$flatten\dut.\u_prefetch.$add$hardware/v2/rtl/prefetch_engine.v:98$366 ($add).
|
|
Removed top 15 bits (of 23) from port Y of cell harness_memory_manager.$flatten\dut.\u_prefetch.$add$hardware/v2/rtl/prefetch_engine.v:112$381 ($add).
|
|
Removed top 15 bits (of 23) from port A of cell harness_memory_manager.$flatten\dut.\u_prefetch.$add$hardware/v2/rtl/prefetch_engine.v:112$381 ($add).
|
|
Removed top 15 bits (of 23) from port Y of cell harness_memory_manager.$flatten\dut.\u_prefetch.$add$hardware/v2/rtl/prefetch_engine.v:98$365 ($add).
|
|
Removed top 15 bits (of 23) from port A of cell harness_memory_manager.$flatten\dut.\u_prefetch.$add$hardware/v2/rtl/prefetch_engine.v:98$365 ($add).
|
|
Removed top 15 bits (of 23) from port Y of cell harness_memory_manager.$flatten\dut.\u_prefetch.$add$hardware/v2/rtl/prefetch_engine.v:112$380 ($add).
|
|
Removed top 15 bits (of 23) from port A of cell harness_memory_manager.$flatten\dut.\u_prefetch.$add$hardware/v2/rtl/prefetch_engine.v:112$380 ($add).
|
|
Removed top 15 bits (of 23) from FF cell harness_memory_manager.$auto$ff.cc:337:slice$1410 ($dffe).
|
|
Removed top 15 bits (of 23) from FF cell harness_memory_manager.$auto$ff.cc:337:slice$1405 ($dffe).
|
|
Removed top 15 bits (of 23) from FF cell harness_memory_manager.$auto$ff.cc:337:slice$1380 ($dffe).
|
|
Removed top 15 bits (of 23) from FF cell harness_memory_manager.$auto$ff.cc:337:slice$1361 ($dffe).
|
|
Removed top 15 bits (of 23) from mux cell harness_memory_manager.$flatten\dut.$procmux$829 ($pmux).
|
|
Removed top 15 bits (of 23) from mux cell harness_memory_manager.$flatten\dut.$procmux$803 ($pmux).
|
|
Removed top 15 bits (of 23) from mux cell harness_memory_manager.$flatten\dut.$procmux$837 ($mux).
|
|
Removed top 15 bits (of 23) from mux cell harness_memory_manager.$flatten\dut.$procmux$833 ($mux).
|
|
Removed top 15 bits (of 23) from mux cell harness_memory_manager.$flatten\dut.$procmux$827 ($mux).
|
|
Removed top 15 bits (of 23) from mux cell harness_memory_manager.$flatten\dut.$procmux$811 ($mux).
|
|
Removed top 15 bits (of 23) from mux cell harness_memory_manager.$flatten\dut.$procmux$807 ($mux).
|
|
Removed top 15 bits (of 23) from mux cell harness_memory_manager.$flatten\dut.$procmux$801 ($mux).
|
|
Removed top 15 bits (of 23) from mux cell harness_memory_manager.$flatten\dut.$procmux$831 ($mux).
|
|
Removed top 15 bits (of 23) from mux cell harness_memory_manager.$flatten\dut.$procmux$825 ($mux).
|
|
Removed top 15 bits (of 23) from mux cell harness_memory_manager.$flatten\dut.$procmux$805 ($mux).
|
|
Removed top 15 bits (of 23) from mux cell harness_memory_manager.$flatten\dut.$procmux$799 ($mux).
|
|
Removed top 15 bits (of 23) from mux cell harness_memory_manager.$flatten\dut.$procmux$822 ($mux).
|
|
Removed top 15 bits (of 23) from mux cell harness_memory_manager.$flatten\dut.$procmux$796 ($mux).
|
|
Removed top 15 bits (of 23) from port Y of cell harness_memory_manager.$flatten\dut.$add$hardware/v2/rtl/memory_manager.v:237$303 ($add).
|
|
Removed top 15 bits (of 23) from port A of cell harness_memory_manager.$flatten\dut.$add$hardware/v2/rtl/memory_manager.v:237$303 ($add).
|
|
Removed top 15 bits (of 23) from port Y of cell harness_memory_manager.$flatten\dut.$add$hardware/v2/rtl/memory_manager.v:236$302 ($add).
|
|
Removed top 15 bits (of 23) from port A of cell harness_memory_manager.$flatten\dut.$add$hardware/v2/rtl/memory_manager.v:236$302 ($add).
|
|
Removed top 3 bits (of 23) from port B of cell harness_memory_manager.$flatten\dut.$add$hardware/v2/rtl/memory_manager.v:266$325 ($add).
|
|
Removed top 15 bits (of 23) from port Y of cell harness_memory_manager.$flatten\dut.$add$hardware/v2/rtl/memory_manager.v:266$325 ($add).
|
|
Removed top 15 bits (of 23) from port A of cell harness_memory_manager.$flatten\dut.$add$hardware/v2/rtl/memory_manager.v:266$325 ($add).
|
|
Removed top 12 bits (of 20) from port B of cell harness_memory_manager.$flatten\dut.$add$hardware/v2/rtl/memory_manager.v:266$325 ($add).
|
|
Removed top 15 bits (of 23) from port Y of cell harness_memory_manager.$flatten\dut.$add$hardware/v2/rtl/memory_manager.v:265$322 ($add).
|
|
Removed top 15 bits (of 23) from port A of cell harness_memory_manager.$flatten\dut.$add$hardware/v2/rtl/memory_manager.v:265$322 ($add).
|
|
Removed top 12 bits (of 20) from port B of cell harness_memory_manager.$flatten\dut.$add$hardware/v2/rtl/memory_manager.v:265$322 ($add).
|
|
Removed top 14 bits (of 21) from FF cell harness_memory_manager.$auto$ff.cc:337:slice$1516 ($dffe).
|
|
Removed top 15 bits (of 22) from FF cell harness_memory_manager.$auto$ff.cc:337:slice$1515 ($dffe).
|
|
Removed top 12 bits (of 17) from port Y of cell harness_memory_manager.$flatten\dut.$add$hardware/v2/rtl/memory_manager.v:266$323 ($add).
|
|
Removed top 11 bits (of 16) from port A of cell harness_memory_manager.$flatten\dut.$add$hardware/v2/rtl/memory_manager.v:266$323 ($add).
|
|
Removed top 56 bits (of 64) from wire harness_memory_manager.$flatten\dut.$ternary$hardware/v2/rtl/memory_manager.v:231$297_Y.
|
|
Removed top 56 bits (of 64) from wire harness_memory_manager.$flatten\dut.$procmux$1023_Y.
|
|
Removed top 56 bits (of 64) from wire harness_memory_manager.$flatten\dut.$procmux$1025_Y.
|
|
Removed top 56 bits (of 64) from wire harness_memory_manager.$flatten\dut.$procmux$1028_Y.
|
|
Removed top 56 bits (of 64) from wire harness_memory_manager.$flatten\dut.$procmux$1030_Y.
|
|
Removed top 56 bits (of 64) from wire harness_memory_manager.$flatten\dut.$procmux$1032_Y.
|
|
Removed top 18 bits (of 23) from wire harness_memory_manager.$flatten\dut.$add$hardware/v2/rtl/memory_manager.v:265$320_Y.
|
|
Removed top 56 bits (of 64) from wire harness_memory_manager.$flatten\dut.$procmux$1042_Y.
|
|
Removed top 56 bits (of 64) from wire harness_memory_manager.$flatten\dut.$procmux$1044_Y.
|
|
Removed top 56 bits (of 64) from wire harness_memory_manager.$flatten\dut.$procmux$1047_Y.
|
|
Removed top 56 bits (of 64) from wire harness_memory_manager.$flatten\dut.$procmux$1049_Y.
|
|
Removed top 56 bits (of 64) from wire harness_memory_manager.$flatten\dut.$procmux$1051_Y.
|
|
Removed top 15 bits (of 23) from wire harness_memory_manager.$flatten\dut.$add$hardware/v2/rtl/memory_manager.v:265$322_Y.
|
|
Removed top 15 bits (of 23) from wire harness_memory_manager.$flatten\dut.$add$hardware/v2/rtl/memory_manager.v:266$325_Y.
|
|
Removed top 15 bits (of 23) from wire harness_memory_manager.$flatten\dut.\u_prefetch.$procmux$561_Y.
|
|
Removed top 15 bits (of 23) from wire harness_memory_manager.$flatten\dut.\u_prefetch.$procmux$558_Y.
|
|
Removed top 15 bits (of 23) from wire harness_memory_manager.$flatten\dut.\u_prefetch.$procmux$556_Y.
|
|
Removed top 15 bits (of 23) from wire harness_memory_manager.$flatten\dut.\u_prefetch.$procmux$552_Y.
|
|
Removed top 15 bits (of 23) from wire harness_memory_manager.$flatten\dut.\u_prefetch.$procmux$550_Y.
|
|
Removed top 15 bits (of 23) from wire harness_memory_manager.$flatten\dut.\u_prefetch.$procmux$548_Y.
|
|
Removed top 56 bits (of 64) from wire harness_memory_manager.$flatten\dut.$ternary$hardware/v2/rtl/memory_manager.v:232$299_Y.
|
|
Removed top 15 bits (of 23) from wire harness_memory_manager.$flatten\dut.$procmux$796_Y.
|
|
Removed top 15 bits (of 23) from wire harness_memory_manager.$flatten\dut.$procmux$799_Y.
|
|
Removed top 15 bits (of 23) from wire harness_memory_manager.$flatten\dut.$procmux$801_Y.
|
|
Removed top 15 bits (of 23) from wire harness_memory_manager.$flatten\dut.$procmux$803_Y.
|
|
Removed top 15 bits (of 23) from wire harness_memory_manager.$flatten\dut.$procmux$805_Y.
|
|
Removed top 15 bits (of 23) from wire harness_memory_manager.$flatten\dut.$procmux$807_Y.
|
|
Removed top 15 bits (of 23) from wire harness_memory_manager.$flatten\dut.$procmux$811_Y.
|
|
Removed top 15 bits (of 23) from wire harness_memory_manager.$flatten\dut.$procmux$837_Y.
|
|
Removed top 15 bits (of 23) from wire harness_memory_manager.$flatten\dut.$procmux$833_Y.
|
|
Removed top 15 bits (of 23) from wire harness_memory_manager.$flatten\dut.$procmux$831_Y.
|
|
Removed top 15 bits (of 23) from wire harness_memory_manager.$flatten\dut.$procmux$829_Y.
|
|
Removed top 15 bits (of 23) from wire harness_memory_manager.$flatten\dut.$procmux$827_Y.
|
|
Removed top 15 bits (of 23) from wire harness_memory_manager.$flatten\dut.$procmux$825_Y.
|
|
Removed top 15 bits (of 23) from wire harness_memory_manager.$flatten\dut.\u_prefetch.$add$hardware/v2/rtl/prefetch_engine.v:112$381_Y.
|
|
Removed top 15 bits (of 23) from wire harness_memory_manager.$flatten\dut.\u_prefetch.$add$hardware/v2/rtl/prefetch_engine.v:112$380_Y.
|
|
Removed top 15 bits (of 23) from wire harness_memory_manager.$flatten\dut.$add$hardware/v2/rtl/memory_manager.v:237$303_Y.
|
|
Removed top 15 bits (of 23) from wire harness_memory_manager.$flatten\dut.\u_prefetch.$add$hardware/v2/rtl/prefetch_engine.v:98$366_Y.
|
|
Removed top 15 bits (of 23) from wire harness_memory_manager.$flatten\dut.\u_prefetch.$add$hardware/v2/rtl/prefetch_engine.v:98$365_Y.
|
|
Removed top 15 bits (of 23) from wire harness_memory_manager.$flatten\dut.$procmux$822_Y.
|
|
Removed top 15 bits (of 23) from wire harness_memory_manager.$flatten\dut.$add$hardware/v2/rtl/memory_manager.v:236$302_Y.
|
|
Removed top 24 bits (of 32) from wire harness_memory_manager.$0\lfsr[31:0].
|
|
Removed top 15 bits (of 23) from wire harness_memory_manager.mem_addr.
|
|
Removed top 56 bits (of 64) from wire harness_memory_manager.weight_data.
|
|
Removed top 56 bits (of 64) from wire harness_memory_manager.input_data.
|
|
|
|
4.17. Executing PEEPOPT pass (run peephole optimizers).
|
|
|
|
4.18. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \harness_memory_manager..
|
|
Removed 0 unused cells and 45 unused wires.
|
|
<suppressed ~1 debug messages>
|
|
|
|
4.19. Executing SHARE pass (SAT-based resource sharing).
|
|
Found 2 cells in module harness_memory_manager that may be considered for resource sharing.
|
|
Analyzing resource sharing options for $flatten\dut.$memrd$\bank_w$hardware/v2/rtl/memory_manager.v:276$331 ($memrd):
|
|
Found 1 activation_patterns using ctrl signal { \dut.operand_valid \dut.state [2] $flatten\dut.$logic_and$hardware/v2/rtl/memory_manager.v:245$304_Y $flatten\dut.$logic_and$hardware/v2/rtl/memory_manager.v:273$329_Y }.
|
|
No candidates found.
|
|
Analyzing resource sharing options for $flatten\dut.$memrd$\bank_x$hardware/v2/rtl/memory_manager.v:275$330 ($memrd):
|
|
Found 1 activation_patterns using ctrl signal { \dut.operand_valid \dut.state [2] $flatten\dut.$logic_and$hardware/v2/rtl/memory_manager.v:245$304_Y $flatten\dut.$logic_and$hardware/v2/rtl/memory_manager.v:273$329_Y }.
|
|
No candidates found.
|
|
|
|
4.20. Executing TECHMAP pass (map to technology primitives).
|
|
|
|
4.20.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/cmp2lut.v
|
|
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/cmp2lut.v' to AST representation.
|
|
Generating RTLIL representation for module `\_90_lut_cmp_'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
4.20.2. Continuing TECHMAP pass.
|
|
No more expansions possible.
|
|
<suppressed ~62 debug messages>
|
|
|
|
4.21. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module harness_memory_manager.
|
|
|
|
4.22. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \harness_memory_manager..
|
|
|
|
4.23. Executing TECHMAP pass (map to technology primitives).
|
|
|
|
4.23.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/mul2dsp.v
|
|
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/mul2dsp.v' to AST representation.
|
|
Generating RTLIL representation for module `\_80_mul'.
|
|
Generating RTLIL representation for module `\_90_soft_mul'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
4.23.2. Continuing TECHMAP pass.
|
|
No more expansions possible.
|
|
<suppressed ~4 debug messages>
|
|
|
|
4.24. Executing TECHMAP pass (map to technology primitives).
|
|
|
|
4.24.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/dsp_map_18x18.v
|
|
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/dsp_map_18x18.v' to AST representation.
|
|
Generating RTLIL representation for module `$__MUL18X18'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
4.24.2. Continuing TECHMAP pass.
|
|
No more expansions possible.
|
|
<suppressed ~3 debug messages>
|
|
|
|
4.25. Executing ALUMACC pass (create $alu and $macc cells).
|
|
Extracting $alu and $macc cells in module harness_memory_manager:
|
|
creating $macc model for $flatten\dut.$add$hardware/v2/rtl/memory_manager.v:266$323 ($add).
|
|
creating $macc model for $flatten\dut.$add$hardware/v2/rtl/memory_manager.v:265$322 ($add).
|
|
creating $macc model for $flatten\dut.$add$hardware/v2/rtl/memory_manager.v:252$316 ($add).
|
|
creating $macc model for $flatten\dut.$neg$hardware/v2/rtl/memory_manager.v:247$311 ($neg).
|
|
creating $macc model for $flatten\dut.$add$hardware/v2/rtl/memory_manager.v:237$303 ($add).
|
|
creating $macc model for $flatten\dut.$add$hardware/v2/rtl/memory_manager.v:236$302 ($add).
|
|
creating $macc model for $flatten\dut.$sub$hardware/v2/rtl/memory_manager.v:277$332 ($sub).
|
|
creating $macc model for $flatten\dut.$add$hardware/v2/rtl/memory_manager.v:255$318 ($add).
|
|
creating $macc model for $flatten\dut.$neg$hardware/v2/rtl/memory_manager.v:183$283 ($neg).
|
|
creating $macc model for $flatten\dut.$add$hardware/v2/rtl/memory_manager.v:266$325 ($add).
|
|
creating $macc model for $flatten\dut.\u_prefetch.$add$hardware/v2/rtl/prefetch_engine.v:112$381 ($add).
|
|
creating $macc model for $flatten\dut.\u_prefetch.$add$hardware/v2/rtl/prefetch_engine.v:112$380 ($add).
|
|
creating $macc model for $flatten\dut.\u_prefetch.$add$hardware/v2/rtl/prefetch_engine.v:109$379 ($add).
|
|
creating $macc model for $flatten\dut.\u_prefetch.$neg$hardware/v2/rtl/prefetch_engine.v:105$375 ($neg).
|
|
creating $macc model for $flatten\dut.\u_prefetch.$add$hardware/v2/rtl/prefetch_engine.v:98$366 ($add).
|
|
creating $macc model for $flatten\dut.\u_prefetch.$add$hardware/v2/rtl/prefetch_engine.v:98$365 ($add).
|
|
merging $macc model for $flatten\dut.\u_prefetch.$add$hardware/v2/rtl/prefetch_engine.v:98$365 into $flatten\dut.\u_prefetch.$add$hardware/v2/rtl/prefetch_engine.v:98$366.
|
|
merging $macc model for $flatten\dut.\u_prefetch.$add$hardware/v2/rtl/prefetch_engine.v:112$380 into $flatten\dut.\u_prefetch.$add$hardware/v2/rtl/prefetch_engine.v:112$381.
|
|
creating $alu model for $macc $flatten\dut.\u_prefetch.$neg$hardware/v2/rtl/prefetch_engine.v:105$375.
|
|
creating $alu model for $macc $flatten\dut.\u_prefetch.$add$hardware/v2/rtl/prefetch_engine.v:109$379.
|
|
creating $alu model for $macc $flatten\dut.\u_prefetch.$add$hardware/v2/rtl/prefetch_engine.v:98$366.
|
|
creating $alu model for $macc $flatten\dut.\u_prefetch.$add$hardware/v2/rtl/prefetch_engine.v:112$381.
|
|
creating $alu model for $macc $flatten\dut.$add$hardware/v2/rtl/memory_manager.v:266$325.
|
|
creating $alu model for $macc $flatten\dut.$neg$hardware/v2/rtl/memory_manager.v:183$283.
|
|
creating $alu model for $macc $flatten\dut.$add$hardware/v2/rtl/memory_manager.v:255$318.
|
|
creating $alu model for $macc $flatten\dut.$sub$hardware/v2/rtl/memory_manager.v:277$332.
|
|
creating $alu model for $macc $flatten\dut.$add$hardware/v2/rtl/memory_manager.v:236$302.
|
|
creating $alu model for $macc $flatten\dut.$add$hardware/v2/rtl/memory_manager.v:237$303.
|
|
creating $alu model for $macc $flatten\dut.$neg$hardware/v2/rtl/memory_manager.v:247$311.
|
|
creating $alu model for $macc $flatten\dut.$add$hardware/v2/rtl/memory_manager.v:252$316.
|
|
creating $alu model for $macc $flatten\dut.$add$hardware/v2/rtl/memory_manager.v:265$322.
|
|
creating $alu model for $macc $flatten\dut.$add$hardware/v2/rtl/memory_manager.v:266$323.
|
|
creating $alu model for $flatten\dut.$lt$hardware/v2/rtl/memory_manager.v:255$319 ($lt): new $alu
|
|
creating $alu model for $flatten\dut.$gt$hardware/v2/rtl/memory_manager.v:234$301 ($gt): merged with $flatten\dut.$sub$hardware/v2/rtl/memory_manager.v:277$332.
|
|
creating $alu model for $flatten\dut.$lt$hardware/v2/rtl/memory_manager.v:273$328 ($lt): new $alu
|
|
creating $alu cell for $flatten\dut.$lt$hardware/v2/rtl/memory_manager.v:273$328: $auto$alumacc.cc:548:replace_alu$1567
|
|
creating $alu cell for $flatten\dut.$lt$hardware/v2/rtl/memory_manager.v:255$319: $auto$alumacc.cc:548:replace_alu$1572
|
|
creating $alu cell for $flatten\dut.$add$hardware/v2/rtl/memory_manager.v:266$323: $auto$alumacc.cc:548:replace_alu$1577
|
|
creating $alu cell for $flatten\dut.$add$hardware/v2/rtl/memory_manager.v:265$322: $auto$alumacc.cc:548:replace_alu$1580
|
|
creating $alu cell for $flatten\dut.$add$hardware/v2/rtl/memory_manager.v:252$316: $auto$alumacc.cc:548:replace_alu$1583
|
|
creating $alu cell for $flatten\dut.$neg$hardware/v2/rtl/memory_manager.v:247$311: $auto$alumacc.cc:548:replace_alu$1586
|
|
creating $alu cell for $flatten\dut.$add$hardware/v2/rtl/memory_manager.v:237$303: $auto$alumacc.cc:548:replace_alu$1589
|
|
creating $alu cell for $flatten\dut.$add$hardware/v2/rtl/memory_manager.v:236$302: $auto$alumacc.cc:548:replace_alu$1592
|
|
creating $alu cell for $flatten\dut.$sub$hardware/v2/rtl/memory_manager.v:277$332, $flatten\dut.$gt$hardware/v2/rtl/memory_manager.v:234$301: $auto$alumacc.cc:548:replace_alu$1595
|
|
creating $alu cell for $flatten\dut.$add$hardware/v2/rtl/memory_manager.v:255$318: $auto$alumacc.cc:548:replace_alu$1606
|
|
creating $alu cell for $flatten\dut.$neg$hardware/v2/rtl/memory_manager.v:183$283: $auto$alumacc.cc:548:replace_alu$1609
|
|
creating $alu cell for $flatten\dut.$add$hardware/v2/rtl/memory_manager.v:266$325: $auto$alumacc.cc:548:replace_alu$1612
|
|
creating $alu cell for $flatten\dut.\u_prefetch.$add$hardware/v2/rtl/prefetch_engine.v:112$381: $auto$alumacc.cc:548:replace_alu$1615
|
|
creating $alu cell for $flatten\dut.\u_prefetch.$add$hardware/v2/rtl/prefetch_engine.v:98$366: $auto$alumacc.cc:548:replace_alu$1618
|
|
creating $alu cell for $flatten\dut.\u_prefetch.$add$hardware/v2/rtl/prefetch_engine.v:109$379: $auto$alumacc.cc:548:replace_alu$1621
|
|
creating $alu cell for $flatten\dut.\u_prefetch.$neg$hardware/v2/rtl/prefetch_engine.v:105$375: $auto$alumacc.cc:548:replace_alu$1624
|
|
created 16 $alu and 0 $macc cells.
|
|
|
|
4.26. Executing OPT pass (performing simple optimizations).
|
|
|
|
4.26.1. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module harness_memory_manager.
|
|
<suppressed ~8 debug messages>
|
|
|
|
4.26.2. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\harness_memory_manager'.
|
|
Computing hashes of 299 cells of `\harness_memory_manager'.
|
|
Finding duplicate cells in `\harness_memory_manager'.
|
|
Computing hashes of 297 cells of `\harness_memory_manager'.
|
|
Finding duplicate cells in `\harness_memory_manager'.
|
|
Computing hashes of 295 cells of `\harness_memory_manager'.
|
|
Finding duplicate cells in `\harness_memory_manager'.
|
|
<suppressed ~16 debug messages>
|
|
Removed a total of 4 cells.
|
|
|
|
4.26.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \harness_memory_manager..
|
|
Creating internal representation of mux trees.
|
|
Evaluating internal representation of mux trees.
|
|
Analyzing evaluation results.
|
|
Removed 0 multiplexer ports.
|
|
<suppressed ~151 debug messages>
|
|
|
|
4.26.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \harness_memory_manager.
|
|
Performed a total of 0 changes.
|
|
|
|
4.26.5. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\harness_memory_manager'.
|
|
Computing hashes of 295 cells of `\harness_memory_manager'.
|
|
Finding duplicate cells in `\harness_memory_manager'.
|
|
Computing hashes of 292 cells of `\harness_memory_manager'.
|
|
Finding duplicate cells in `\harness_memory_manager'.
|
|
Computing hashes of 290 cells of `\harness_memory_manager'.
|
|
Finding duplicate cells in `\harness_memory_manager'.
|
|
Computing hashes of 289 cells of `\harness_memory_manager'.
|
|
Finding duplicate cells in `\harness_memory_manager'.
|
|
Computing hashes of 288 cells of `\harness_memory_manager'.
|
|
Finding duplicate cells in `\harness_memory_manager'.
|
|
Computing hashes of 287 cells of `\harness_memory_manager'.
|
|
Finding duplicate cells in `\harness_memory_manager'.
|
|
Computing hashes of 286 cells of `\harness_memory_manager'.
|
|
Finding duplicate cells in `\harness_memory_manager'.
|
|
Computing hashes of 284 cells of `\harness_memory_manager'.
|
|
Finding duplicate cells in `\harness_memory_manager'.
|
|
<suppressed ~35 debug messages>
|
|
Removed a total of 11 cells.
|
|
|
|
4.26.6. Executing OPT_DFF pass (perform DFF optimizations).
|
|
|
|
4.26.7. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \harness_memory_manager..
|
|
Removed 1 unused cells and 21 unused wires.
|
|
<suppressed ~2 debug messages>
|
|
|
|
4.26.8. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module harness_memory_manager.
|
|
|
|
4.26.9. Rerunning OPT passes. (Maybe there is more to do..)
|
|
|
|
4.26.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \harness_memory_manager..
|
|
Creating internal representation of mux trees.
|
|
Evaluating internal representation of mux trees.
|
|
Analyzing evaluation results.
|
|
Removed 0 multiplexer ports.
|
|
<suppressed ~143 debug messages>
|
|
|
|
4.26.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \harness_memory_manager.
|
|
Performed a total of 0 changes.
|
|
|
|
4.26.12. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\harness_memory_manager'.
|
|
Computing hashes of 283 cells of `\harness_memory_manager'.
|
|
Finding duplicate cells in `\harness_memory_manager'.
|
|
Removed a total of 0 cells.
|
|
|
|
4.26.13. Executing OPT_DFF pass (perform DFF optimizations).
|
|
|
|
4.26.14. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \harness_memory_manager..
|
|
|
|
4.26.15. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module harness_memory_manager.
|
|
|
|
4.26.16. Finished fast OPT passes. (There is nothing left to do.)
|
|
|
|
4.27. Executing MEMORY pass.
|
|
|
|
4.27.1. Executing OPT_MEM pass (optimize memories).
|
|
Performed a total of 0 transformations.
|
|
|
|
4.27.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations).
|
|
Performed a total of 0 transformations.
|
|
|
|
4.27.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths).
|
|
Analyzing harness_memory_manager.dut.bank_x write port 0.
|
|
Analyzing harness_memory_manager.dut.bank_w write port 0.
|
|
|
|
4.27.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs).
|
|
|
|
4.27.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd).
|
|
Checking read port `\dut.bank_x'[0] in module `\harness_memory_manager': no output FF found.
|
|
Checking read port `\dut.bank_x'[1] in module `\harness_memory_manager': no output FF found.
|
|
Checking read port `\dut.bank_w'[0] in module `\harness_memory_manager': no output FF found.
|
|
Checking read port `\dut.bank_w'[1] in module `\harness_memory_manager': no output FF found.
|
|
Checking read port address `\dut.bank_x'[0] in module `\harness_memory_manager': no address FF found.
|
|
Checking read port address `\dut.bank_x'[1] in module `\harness_memory_manager': merged address FF to cell.
|
|
Checking read port address `\dut.bank_w'[0] in module `\harness_memory_manager': no address FF found.
|
|
Checking read port address `\dut.bank_w'[1] in module `\harness_memory_manager': merged address FF to cell.
|
|
|
|
4.27.6. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \harness_memory_manager..
|
|
|
|
4.27.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells).
|
|
Consolidating read ports of memory harness_memory_manager.dut.bank_x by address:
|
|
Consolidating read ports of memory harness_memory_manager.dut.bank_w by address:
|
|
|
|
4.27.8. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide).
|
|
Performed a total of 0 transformations.
|
|
|
|
4.27.9. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \harness_memory_manager..
|
|
|
|
4.27.10. Executing MEMORY_COLLECT pass (generating $mem cells).
|
|
|
|
4.28. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \harness_memory_manager..
|
|
|
|
4.29. Executing MEMORY_LIBMAP pass (mapping memories to cells).
|
|
using FF mapping for memory harness_memory_manager.dut.bank_w
|
|
using FF mapping for memory harness_memory_manager.dut.bank_x
|
|
<suppressed ~152 debug messages>
|
|
|
|
4.30. Executing TECHMAP pass (map to technology primitives).
|
|
|
|
4.30.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/lutrams_map_trellis.v
|
|
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/lutrams_map_trellis.v' to AST representation.
|
|
Generating RTLIL representation for module `$__TRELLIS_DPR16X4_'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
4.30.2. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/brams_map_16kd.v
|
|
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/brams_map_16kd.v' to AST representation.
|
|
Generating RTLIL representation for module `$__DP16KD_'.
|
|
Generating RTLIL representation for module `$__PDPW16KD_'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
4.30.3. Continuing TECHMAP pass.
|
|
No more expansions possible.
|
|
<suppressed ~5 debug messages>
|
|
|
|
4.31. Executing OPT pass (performing simple optimizations).
|
|
|
|
4.31.1. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module harness_memory_manager.
|
|
<suppressed ~231 debug messages>
|
|
|
|
4.31.2. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\harness_memory_manager'.
|
|
Computing hashes of 223 cells of `\harness_memory_manager'.
|
|
Finding duplicate cells in `\harness_memory_manager'.
|
|
Computing hashes of 222 cells of `\harness_memory_manager'.
|
|
Finding duplicate cells in `\harness_memory_manager'.
|
|
Computing hashes of 221 cells of `\harness_memory_manager'.
|
|
Finding duplicate cells in `\harness_memory_manager'.
|
|
<suppressed ~6 debug messages>
|
|
Removed a total of 2 cells.
|
|
|
|
4.31.3. Executing OPT_DFF pass (perform DFF optimizations).
|
|
|
|
4.31.4. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \harness_memory_manager..
|
|
Removed 0 unused cells and 71 unused wires.
|
|
<suppressed ~2 debug messages>
|
|
|
|
4.31.5. Finished fast OPT passes.
|
|
|
|
4.32. Executing MEMORY_MAP pass (converting memories to logic and flip-flops).
|
|
Mapping memory \dut.bank_w in module \harness_memory_manager:
|
|
created 2 $dff cells and 0 static cells of width 64.
|
|
Extracted addr FF from read port 1 of harness_memory_manager.dut.bank_w: $\dut.bank_w$rdreg[1]
|
|
read interface: 1 $dff and 2 $mux cells.
|
|
write interface: 2 write mux blocks.
|
|
Mapping memory \dut.bank_x in module \harness_memory_manager:
|
|
created 2 $dff cells and 0 static cells of width 64.
|
|
Extracted addr FF from read port 1 of harness_memory_manager.dut.bank_x: $\dut.bank_x$rdreg[1]
|
|
read interface: 1 $dff and 2 $mux cells.
|
|
write interface: 2 write mux blocks.
|
|
|
|
4.33. Executing OPT pass (performing simple optimizations).
|
|
|
|
4.33.1. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module harness_memory_manager.
|
|
<suppressed ~4 debug messages>
|
|
|
|
4.33.2. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\harness_memory_manager'.
|
|
Computing hashes of 235 cells of `\harness_memory_manager'.
|
|
Finding duplicate cells in `\harness_memory_manager'.
|
|
Computing hashes of 231 cells of `\harness_memory_manager'.
|
|
Finding duplicate cells in `\harness_memory_manager'.
|
|
<suppressed ~12 debug messages>
|
|
Removed a total of 4 cells.
|
|
|
|
4.33.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \harness_memory_manager..
|
|
Creating internal representation of mux trees.
|
|
Evaluating internal representation of mux trees.
|
|
Analyzing evaluation results.
|
|
Removed 0 multiplexer ports.
|
|
<suppressed ~84 debug messages>
|
|
|
|
4.33.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \harness_memory_manager.
|
|
Consolidated identical input bits for $pmux cell $flatten\dut.\u_prefetch.$procmux$574:
|
|
Old ports: A=1'0, B=2'00, Y=$flatten\dut.\u_prefetch.$procmux$574_Y
|
|
New connections: $flatten\dut.\u_prefetch.$procmux$574_Y = 1'0
|
|
Consolidated identical input bits for $pmux cell $flatten\dut.$procmux$803:
|
|
Old ports: A={ \lfsr [7:1] 1'1 }, B={ $auto$wreduce.cc:514:run$1544 [7:3] \dut.x_base_reg [2:1] 1'1 $auto$wreduce.cc:514:run$1531 [7:3] \dut.x_base_reg [2:1] 1'1 }, Y=$auto$wreduce.cc:514:run$1543 [7:0]
|
|
New ports: A=\lfsr [7:1], B={ $auto$wreduce.cc:514:run$1544 [7:3] \dut.x_base_reg [2:1] $auto$wreduce.cc:514:run$1531 [7:3] \dut.x_base_reg [2:1] }, Y=$auto$wreduce.cc:514:run$1543 [7:1]
|
|
New connections: $auto$wreduce.cc:514:run$1543 [0] = 1'1
|
|
Optimizing cells in module \harness_memory_manager.
|
|
Performed a total of 2 changes.
|
|
|
|
4.33.5. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\harness_memory_manager'.
|
|
Computing hashes of 230 cells of `\harness_memory_manager'.
|
|
Finding duplicate cells in `\harness_memory_manager'.
|
|
Removed a total of 0 cells.
|
|
|
|
4.33.6. Executing OPT_DFF pass (perform DFF optimizations).
|
|
Adding SRST signal on $\dut.bank_x$rdreg[1] ($dff) from module harness_memory_manager (D = $auto$rtlil.cc:3402:Mux$1634, Q = $\dut.bank_x$rdreg[1]$q, rval = 1'0).
|
|
|
|
4.33.7. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \harness_memory_manager..
|
|
Removed 1 unused cells and 21 unused wires.
|
|
<suppressed ~2 debug messages>
|
|
|
|
4.33.8. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module harness_memory_manager.
|
|
|
|
4.33.9. Rerunning OPT passes. (Maybe there is more to do..)
|
|
|
|
4.33.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \harness_memory_manager..
|
|
Creating internal representation of mux trees.
|
|
Evaluating internal representation of mux trees.
|
|
Analyzing evaluation results.
|
|
Removed 0 multiplexer ports.
|
|
<suppressed ~81 debug messages>
|
|
|
|
4.33.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \harness_memory_manager.
|
|
Performed a total of 0 changes.
|
|
|
|
4.33.12. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\harness_memory_manager'.
|
|
Computing hashes of 229 cells of `\harness_memory_manager'.
|
|
Finding duplicate cells in `\harness_memory_manager'.
|
|
Removed a total of 0 cells.
|
|
|
|
4.33.13. Executing OPT_DFF pass (perform DFF optimizations).
|
|
Adding EN signal on $memory\dut.bank_x[1]$1813 ($dff) from module harness_memory_manager (D = \dut.u_prefetch.tile_x, Q = \dut.bank_x[1]).
|
|
Adding EN signal on $memory\dut.bank_x[0]$1811 ($dff) from module harness_memory_manager (D = \dut.u_prefetch.tile_x, Q = \dut.bank_x[0]).
|
|
Adding EN signal on $memory\dut.bank_w[0]$1789 ($dff) from module harness_memory_manager (D = \dut.u_prefetch.tile_w, Q = \dut.bank_w[0]).
|
|
Adding EN signal on $memory\dut.bank_w[1]$1791 ($dff) from module harness_memory_manager (D = \dut.u_prefetch.tile_w, Q = \dut.bank_w[1]).
|
|
Setting constant 1-bit at position 0 on $auto$ff.cc:337:slice$1380 ($dffe) from module harness_memory_manager.
|
|
Setting constant 0-bit at position 0 on $auto$ff.cc:337:slice$1263 ($sdffe) from module harness_memory_manager.
|
|
|
|
4.33.14. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \harness_memory_manager..
|
|
Removed 4 unused cells and 4 unused wires.
|
|
<suppressed ~5 debug messages>
|
|
|
|
4.33.15. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module harness_memory_manager.
|
|
<suppressed ~1 debug messages>
|
|
|
|
4.33.16. Rerunning OPT passes. (Maybe there is more to do..)
|
|
|
|
4.33.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \harness_memory_manager..
|
|
Creating internal representation of mux trees.
|
|
Evaluating internal representation of mux trees.
|
|
Analyzing evaluation results.
|
|
Removed 0 multiplexer ports.
|
|
<suppressed ~71 debug messages>
|
|
|
|
4.33.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \harness_memory_manager.
|
|
Performed a total of 0 changes.
|
|
|
|
4.33.19. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\harness_memory_manager'.
|
|
Computing hashes of 223 cells of `\harness_memory_manager'.
|
|
Finding duplicate cells in `\harness_memory_manager'.
|
|
Removed a total of 0 cells.
|
|
|
|
4.33.20. Executing OPT_DFF pass (perform DFF optimizations).
|
|
Setting constant 1-bit at position 0 on $auto$ff.cc:337:slice$1410 ($dffe) from module harness_memory_manager.
|
|
|
|
4.33.21. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \harness_memory_manager..
|
|
|
|
4.33.22. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module harness_memory_manager.
|
|
<suppressed ~1 debug messages>
|
|
|
|
4.33.23. Rerunning OPT passes. (Maybe there is more to do..)
|
|
|
|
4.33.24. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \harness_memory_manager..
|
|
Creating internal representation of mux trees.
|
|
Evaluating internal representation of mux trees.
|
|
Analyzing evaluation results.
|
|
Removed 0 multiplexer ports.
|
|
<suppressed ~71 debug messages>
|
|
|
|
4.33.25. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \harness_memory_manager.
|
|
Performed a total of 0 changes.
|
|
|
|
4.33.26. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\harness_memory_manager'.
|
|
Computing hashes of 224 cells of `\harness_memory_manager'.
|
|
Finding duplicate cells in `\harness_memory_manager'.
|
|
Removed a total of 0 cells.
|
|
|
|
4.33.27. Executing OPT_DFF pass (perform DFF optimizations).
|
|
|
|
4.33.28. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \harness_memory_manager..
|
|
Removed 1 unused cells and 1 unused wires.
|
|
<suppressed ~2 debug messages>
|
|
|
|
4.33.29. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module harness_memory_manager.
|
|
|
|
4.33.30. Rerunning OPT passes. (Maybe there is more to do..)
|
|
|
|
4.33.31. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \harness_memory_manager..
|
|
Creating internal representation of mux trees.
|
|
Evaluating internal representation of mux trees.
|
|
Analyzing evaluation results.
|
|
Removed 0 multiplexer ports.
|
|
<suppressed ~71 debug messages>
|
|
|
|
4.33.32. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \harness_memory_manager.
|
|
Performed a total of 0 changes.
|
|
|
|
4.33.33. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\harness_memory_manager'.
|
|
Computing hashes of 223 cells of `\harness_memory_manager'.
|
|
Finding duplicate cells in `\harness_memory_manager'.
|
|
Removed a total of 0 cells.
|
|
|
|
4.33.34. Executing OPT_DFF pass (perform DFF optimizations).
|
|
|
|
4.33.35. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \harness_memory_manager..
|
|
|
|
4.33.36. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module harness_memory_manager.
|
|
|
|
4.33.37. Finished fast OPT passes. (There is nothing left to do.)
|
|
|
|
4.34. Executing TECHMAP pass (map to technology primitives).
|
|
|
|
4.34.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/techmap.v
|
|
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/techmap.v' to AST representation.
|
|
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
|
|
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
|
|
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
|
|
Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
|
|
Generating RTLIL representation for module `\_90_simplemap_various'.
|
|
Generating RTLIL representation for module `\_90_simplemap_registers'.
|
|
Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
|
|
Generating RTLIL representation for module `\_90_shift_shiftx'.
|
|
Generating RTLIL representation for module `\_90_fa'.
|
|
Generating RTLIL representation for module `\_90_lcu_brent_kung'.
|
|
Generating RTLIL representation for module `\_90_alu'.
|
|
Generating RTLIL representation for module `\_90_macc'.
|
|
Generating RTLIL representation for module `\_90_alumacc'.
|
|
Generating RTLIL representation for module `$__div_mod_u'.
|
|
Generating RTLIL representation for module `$__div_mod_trunc'.
|
|
Generating RTLIL representation for module `\_90_div'.
|
|
Generating RTLIL representation for module `\_90_mod'.
|
|
Generating RTLIL representation for module `$__div_mod_floor'.
|
|
Generating RTLIL representation for module `\_90_divfloor'.
|
|
Generating RTLIL representation for module `\_90_modfloor'.
|
|
Generating RTLIL representation for module `\_90_pow'.
|
|
Generating RTLIL representation for module `\_90_demux'.
|
|
Generating RTLIL representation for module `\_90_lut'.
|
|
Generating RTLIL representation for module `$connect'.
|
|
Generating RTLIL representation for module `$input_port'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
4.34.2. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v
|
|
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v' to AST representation.
|
|
Generating RTLIL representation for module `\_80_ccu2c_alu'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
4.34.3. Continuing TECHMAP pass.
|
|
Using extmapper simplemap for cells of type $dffe.
|
|
Using extmapper simplemap for cells of type $sdff.
|
|
Using extmapper simplemap for cells of type $not.
|
|
Using extmapper simplemap for cells of type $xor.
|
|
Using extmapper simplemap for cells of type $mux.
|
|
Using template $paramod$3e2546d640bb80c4407ce51aec1dbdbdc5bff143\_80_ccu2c_alu for cells of type $alu.
|
|
Using template $paramod$32a7b7b86c07519b7537abc18e96f0331f97914d\_90_alu for cells of type $alu.
|
|
Using template $paramod$08b2a3505d8f2cd2b03f068ccaf5ce95d4eb0556\_80_ccu2c_alu for cells of type $alu.
|
|
Using template $paramod$9e8c19db10db5b8954224cafa0587db20bab09bd\_90_alu for cells of type $alu.
|
|
Using template $paramod$3b7577489eb4433b1d5620cab7f3794743dee5ea\_80_ccu2c_alu for cells of type $alu.
|
|
Using extmapper simplemap for cells of type $reduce_and.
|
|
Using template $paramod$672a140277c71df8314410f22acc08d55222c3c7\_80_ccu2c_alu for cells of type $alu.
|
|
Using template $paramod$2af30114e9bd4ccb04dad757b3f0a8f6bf0615b0\_80_ccu2c_alu for cells of type $alu.
|
|
Using template $paramod$b18e16801adf491a64caa0542270798e5d4ac6b6\_80_ccu2c_alu for cells of type $alu.
|
|
Using template $paramod$6df0329addda9228fcc2546de2aaf14ad26c98e1\_80_ccu2c_alu for cells of type $alu.
|
|
Using extmapper simplemap for cells of type $reduce_or.
|
|
Using extmapper simplemap for cells of type $sdffe.
|
|
Using extmapper simplemap for cells of type $ne.
|
|
Using extmapper simplemap for cells of type $reduce_bool.
|
|
Using extmapper simplemap for cells of type $dff.
|
|
Using extmapper simplemap for cells of type $and.
|
|
Using extmapper simplemap for cells of type $eq.
|
|
Using extmapper simplemap for cells of type $logic_not.
|
|
Using extmapper simplemap for cells of type $or.
|
|
Using template $paramod$constmap:27fc41eec160220305c22e2c40782fd680a452dd$paramod$409781814c91f00d9cc7cbbb6c4394c1e0dab276\_90_shift_shiftx for cells of type $shift.
|
|
Analyzing pattern of constant bits for this cell:
|
|
Creating constmapped module `$paramod$constmap:f559a679ff835ab881c809a3c11cd4b7ac7c221b$paramod$409781814c91f00d9cc7cbbb6c4394c1e0dab276\_90_shift_shiftx'.
|
|
|
|
4.34.29. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module $paramod$constmap:f559a679ff835ab881c809a3c11cd4b7ac7c221b$paramod$409781814c91f00d9cc7cbbb6c4394c1e0dab276\_90_shift_shiftx..
|
|
Creating internal representation of mux trees.
|
|
Evaluating internal representation of mux trees.
|
|
Analyzing evaluation results.
|
|
dead port 2/2 on $mux $procmux$3312.
|
|
dead port 2/2 on $mux $procmux$3318.
|
|
dead port 2/2 on $mux $procmux$3324.
|
|
dead port 2/2 on $mux $procmux$3330.
|
|
dead port 2/2 on $mux $procmux$3336.
|
|
dead port 2/2 on $mux $procmux$3342.
|
|
dead port 2/2 on $mux $procmux$3348.
|
|
Removed 7 multiplexer ports.
|
|
<suppressed ~914 debug messages>
|
|
|
|
4.34.30. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module $paramod$constmap:f559a679ff835ab881c809a3c11cd4b7ac7c221b$paramod$409781814c91f00d9cc7cbbb6c4394c1e0dab276\_90_shift_shiftx.
|
|
<suppressed ~27 debug messages>
|
|
Removed 0 unused cells and 12 unused wires.
|
|
Using template $paramod$constmap:f559a679ff835ab881c809a3c11cd4b7ac7c221b$paramod$409781814c91f00d9cc7cbbb6c4394c1e0dab276\_90_shift_shiftx for cells of type $shift.
|
|
Using extmapper simplemap for cells of type $pmux.
|
|
Using extmapper simplemap for cells of type $logic_and.
|
|
Using template $paramod$constmap:de554f9cc18e049d5b7dc95f0bcf8e03e57019ff$paramod$1e265d9719406ee45a570be27d6567e3eeff81e5\_90_shift_shiftx for cells of type $shiftx.
|
|
Using template $paramod$constmap:d8aefc1ccc4cc8f7577de99159ea22c4a240a5fa$paramod$5aa0fbdc3e385f336e95d2896ce5aed0c003c799\_90_shift_shiftx for cells of type $shift.
|
|
Analyzing pattern of constant bits for this cell:
|
|
Constant input on bit 0 of port A: 1'1
|
|
Creating constmapped module `$paramod$constmap:dd82805e02d0c05f7629d78043ee7bd4bcc370d0$paramod$5aa0fbdc3e385f336e95d2896ce5aed0c003c799\_90_shift_shiftx'.
|
|
|
|
4.34.41. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module $paramod$constmap:dd82805e02d0c05f7629d78043ee7bd4bcc370d0$paramod$5aa0fbdc3e385f336e95d2896ce5aed0c003c799\_90_shift_shiftx..
|
|
Creating internal representation of mux trees.
|
|
Evaluating internal representation of mux trees.
|
|
Analyzing evaluation results.
|
|
dead port 2/2 on $mux $procmux$4017.
|
|
Removed 1 multiplexer ports.
|
|
<suppressed ~306 debug messages>
|
|
|
|
4.34.42. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module $paramod$constmap:dd82805e02d0c05f7629d78043ee7bd4bcc370d0$paramod$5aa0fbdc3e385f336e95d2896ce5aed0c003c799\_90_shift_shiftx.
|
|
<suppressed ~2 debug messages>
|
|
Removed 0 unused cells and 7 unused wires.
|
|
Using template $paramod$constmap:dd82805e02d0c05f7629d78043ee7bd4bcc370d0$paramod$5aa0fbdc3e385f336e95d2896ce5aed0c003c799\_90_shift_shiftx for cells of type $shift.
|
|
Using extmapper simplemap for cells of type $logic_or.
|
|
Using extmapper simplemap for cells of type $pos.
|
|
Using template $paramod\_90_fa\WIDTH=32'00000000000000000000000000000100 for cells of type $fa.
|
|
Using template $paramod\_90_lcu_brent_kung\WIDTH=32'00000000000000000000000000000100 for cells of type $lcu.
|
|
Using template $paramod\_90_fa\WIDTH=32'00000000000000000000000000000010 for cells of type $fa.
|
|
Using template $paramod\_90_lcu_brent_kung\WIDTH=32'00000000000000000000000000000010 for cells of type $lcu.
|
|
No more expansions possible.
|
|
<suppressed ~750 debug messages>
|
|
|
|
4.35. Executing OPT pass (performing simple optimizations).
|
|
|
|
4.35.1. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module harness_memory_manager.
|
|
<suppressed ~3279 debug messages>
|
|
|
|
4.35.2. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\harness_memory_manager'.
|
|
Computing hashes of 2705 cells of `\harness_memory_manager'.
|
|
Finding duplicate cells in `\harness_memory_manager'.
|
|
Computing hashes of 2576 cells of `\harness_memory_manager'.
|
|
Finding duplicate cells in `\harness_memory_manager'.
|
|
Computing hashes of 2554 cells of `\harness_memory_manager'.
|
|
Finding duplicate cells in `\harness_memory_manager'.
|
|
Computing hashes of 2541 cells of `\harness_memory_manager'.
|
|
Finding duplicate cells in `\harness_memory_manager'.
|
|
Computing hashes of 2532 cells of `\harness_memory_manager'.
|
|
Finding duplicate cells in `\harness_memory_manager'.
|
|
Computing hashes of 2531 cells of `\harness_memory_manager'.
|
|
Finding duplicate cells in `\harness_memory_manager'.
|
|
Computing hashes of 2530 cells of `\harness_memory_manager'.
|
|
Finding duplicate cells in `\harness_memory_manager'.
|
|
Computing hashes of 2529 cells of `\harness_memory_manager'.
|
|
Finding duplicate cells in `\harness_memory_manager'.
|
|
Computing hashes of 2528 cells of `\harness_memory_manager'.
|
|
Finding duplicate cells in `\harness_memory_manager'.
|
|
Computing hashes of 2527 cells of `\harness_memory_manager'.
|
|
Finding duplicate cells in `\harness_memory_manager'.
|
|
Computing hashes of 2526 cells of `\harness_memory_manager'.
|
|
Finding duplicate cells in `\harness_memory_manager'.
|
|
Computing hashes of 2525 cells of `\harness_memory_manager'.
|
|
Finding duplicate cells in `\harness_memory_manager'.
|
|
Computing hashes of 2524 cells of `\harness_memory_manager'.
|
|
Finding duplicate cells in `\harness_memory_manager'.
|
|
Computing hashes of 2523 cells of `\harness_memory_manager'.
|
|
Finding duplicate cells in `\harness_memory_manager'.
|
|
Computing hashes of 2522 cells of `\harness_memory_manager'.
|
|
Finding duplicate cells in `\harness_memory_manager'.
|
|
Computing hashes of 2521 cells of `\harness_memory_manager'.
|
|
Finding duplicate cells in `\harness_memory_manager'.
|
|
Computing hashes of 2520 cells of `\harness_memory_manager'.
|
|
Finding duplicate cells in `\harness_memory_manager'.
|
|
Computing hashes of 2519 cells of `\harness_memory_manager'.
|
|
Finding duplicate cells in `\harness_memory_manager'.
|
|
Computing hashes of 2518 cells of `\harness_memory_manager'.
|
|
Finding duplicate cells in `\harness_memory_manager'.
|
|
Computing hashes of 2517 cells of `\harness_memory_manager'.
|
|
Finding duplicate cells in `\harness_memory_manager'.
|
|
Computing hashes of 2516 cells of `\harness_memory_manager'.
|
|
Finding duplicate cells in `\harness_memory_manager'.
|
|
Computing hashes of 2515 cells of `\harness_memory_manager'.
|
|
Finding duplicate cells in `\harness_memory_manager'.
|
|
Computing hashes of 2514 cells of `\harness_memory_manager'.
|
|
Finding duplicate cells in `\harness_memory_manager'.
|
|
Computing hashes of 2513 cells of `\harness_memory_manager'.
|
|
Finding duplicate cells in `\harness_memory_manager'.
|
|
Computing hashes of 2512 cells of `\harness_memory_manager'.
|
|
Finding duplicate cells in `\harness_memory_manager'.
|
|
Computing hashes of 2511 cells of `\harness_memory_manager'.
|
|
Finding duplicate cells in `\harness_memory_manager'.
|
|
<suppressed ~582 debug messages>
|
|
Removed a total of 194 cells.
|
|
|
|
4.35.3. Executing OPT_DFF pass (perform DFF optimizations).
|
|
Adding SRST signal on $auto$ff.cc:337:slice$2888 ($_SDFF_PP0_) from module harness_memory_manager (D = $auto$simplemap.cc:189:logic_reduce$3659, Q = \dut.u_prefetch.mem_req, rval = 1'0).
|
|
Adding SRST signal on $auto$ff.cc:337:slice$2671 ($_DFFE_PP_) from module harness_memory_manager (D = $auto$simplemap.cc:189:logic_reduce$3887, Q = \dut.pf_pending_bank, rval = 1'0).
|
|
|
|
4.35.4. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \harness_memory_manager..
|
|
Removed 1402 unused cells and 838 unused wires.
|
|
<suppressed ~1403 debug messages>
|
|
|
|
4.35.5. Rerunning OPT passes. (Removed registers in this run.)
|
|
|
|
4.35.6. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module harness_memory_manager.
|
|
<suppressed ~5 debug messages>
|
|
|
|
4.35.7. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\harness_memory_manager'.
|
|
Computing hashes of 1106 cells of `\harness_memory_manager'.
|
|
Finding duplicate cells in `\harness_memory_manager'.
|
|
Removed a total of 0 cells.
|
|
|
|
4.35.8. Executing OPT_DFF pass (perform DFF optimizations).
|
|
|
|
4.35.9. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \harness_memory_manager..
|
|
|
|
4.35.10. Finished fast OPT passes.
|
|
|
|
4.36. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \harness_memory_manager..
|
|
|
|
4.37. Executing DFFLEGALIZE pass (convert FFs to types supported by the target).
|
|
|
|
4.38. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\harness_memory_manager'.
|
|
Computing hashes of 1108 cells of `\harness_memory_manager'.
|
|
Finding duplicate cells in `\harness_memory_manager'.
|
|
Removed a total of 0 cells.
|
|
|
|
4.39. Executing TECHMAP pass (map to technology primitives).
|
|
|
|
4.39.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v
|
|
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v' to AST representation.
|
|
Generating RTLIL representation for module `$_DFF_N_'.
|
|
Generating RTLIL representation for module `$_DFF_P_'.
|
|
Generating RTLIL representation for module `$_DFFE_NN_'.
|
|
Generating RTLIL representation for module `$_DFFE_PN_'.
|
|
Generating RTLIL representation for module `$_DFFE_NP_'.
|
|
Generating RTLIL representation for module `$_DFFE_PP_'.
|
|
Generating RTLIL representation for module `$_DFF_NP0_'.
|
|
Generating RTLIL representation for module `$_DFF_NP1_'.
|
|
Generating RTLIL representation for module `$_DFF_PP0_'.
|
|
Generating RTLIL representation for module `$_DFF_PP1_'.
|
|
Generating RTLIL representation for module `$_SDFF_NP0_'.
|
|
Generating RTLIL representation for module `$_SDFF_NP1_'.
|
|
Generating RTLIL representation for module `$_SDFF_PP0_'.
|
|
Generating RTLIL representation for module `$_SDFF_PP1_'.
|
|
Generating RTLIL representation for module `$_DFFE_NP0P_'.
|
|
Generating RTLIL representation for module `$_DFFE_NP1P_'.
|
|
Generating RTLIL representation for module `$_DFFE_PP0P_'.
|
|
Generating RTLIL representation for module `$_DFFE_PP1P_'.
|
|
Generating RTLIL representation for module `$_DFFE_NP0N_'.
|
|
Generating RTLIL representation for module `$_DFFE_NP1N_'.
|
|
Generating RTLIL representation for module `$_DFFE_PP0N_'.
|
|
Generating RTLIL representation for module `$_DFFE_PP1N_'.
|
|
Generating RTLIL representation for module `$_SDFFE_NP0P_'.
|
|
Generating RTLIL representation for module `$_SDFFE_NP1P_'.
|
|
Generating RTLIL representation for module `$_SDFFE_PP0P_'.
|
|
Generating RTLIL representation for module `$_SDFFE_PP1P_'.
|
|
Generating RTLIL representation for module `$_SDFFE_NP0N_'.
|
|
Generating RTLIL representation for module `$_SDFFE_NP1N_'.
|
|
Generating RTLIL representation for module `$_SDFFE_PP0N_'.
|
|
Generating RTLIL representation for module `$_SDFFE_PP1N_'.
|
|
Generating RTLIL representation for module `$_ALDFF_NP_'.
|
|
Generating RTLIL representation for module `$_ALDFF_PP_'.
|
|
Generating RTLIL representation for module `$_ALDFFE_NPN_'.
|
|
Generating RTLIL representation for module `$_ALDFFE_NPP_'.
|
|
Generating RTLIL representation for module `$_ALDFFE_PPN_'.
|
|
Generating RTLIL representation for module `$_ALDFFE_PPP_'.
|
|
Generating RTLIL representation for module `\FD1P3AX'.
|
|
Generating RTLIL representation for module `\FD1P3AY'.
|
|
Generating RTLIL representation for module `\FD1P3BX'.
|
|
Generating RTLIL representation for module `\FD1P3DX'.
|
|
Generating RTLIL representation for module `\FD1P3IX'.
|
|
Generating RTLIL representation for module `\FD1P3JX'.
|
|
Generating RTLIL representation for module `\FD1S3AX'.
|
|
Generating RTLIL representation for module `\FD1S3AY'.
|
|
Generating RTLIL representation for module `\FD1S3BX'.
|
|
Generating RTLIL representation for module `\FD1S3DX'.
|
|
Generating RTLIL representation for module `\FD1S3IX'.
|
|
Generating RTLIL representation for module `\FD1S3JX'.
|
|
Generating RTLIL representation for module `\IFS1P3BX'.
|
|
Generating RTLIL representation for module `\IFS1P3DX'.
|
|
Generating RTLIL representation for module `\IFS1P3IX'.
|
|
Generating RTLIL representation for module `\IFS1P3JX'.
|
|
Generating RTLIL representation for module `\OFS1P3BX'.
|
|
Generating RTLIL representation for module `\OFS1P3DX'.
|
|
Generating RTLIL representation for module `\OFS1P3IX'.
|
|
Generating RTLIL representation for module `\OFS1P3JX'.
|
|
Generating RTLIL representation for module `\IB'.
|
|
Generating RTLIL representation for module `\IBPU'.
|
|
Generating RTLIL representation for module `\IBPD'.
|
|
Generating RTLIL representation for module `\OB'.
|
|
Generating RTLIL representation for module `\OBZ'.
|
|
Generating RTLIL representation for module `\OBZPU'.
|
|
Generating RTLIL representation for module `\OBZPD'.
|
|
Generating RTLIL representation for module `\OBCO'.
|
|
Generating RTLIL representation for module `\BB'.
|
|
Generating RTLIL representation for module `\BBPU'.
|
|
Generating RTLIL representation for module `\BBPD'.
|
|
Generating RTLIL representation for module `\ILVDS'.
|
|
Generating RTLIL representation for module `\OLVDS'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
4.39.2. Continuing TECHMAP pass.
|
|
Using template $_SDFFE_PP0P_ for cells of type $_SDFFE_PP0P_.
|
|
Using template $_SDFF_PP0_ for cells of type $_SDFF_PP0_.
|
|
Using template $paramod$_DFF_P_\_TECHMAP_WIREINIT_Q_=1'x for cells of type $_DFF_P_.
|
|
Using template $_SDFF_PP1_ for cells of type $_SDFF_PP1_.
|
|
Using template $paramod$_DFFE_PP_\_TECHMAP_WIREINIT_Q_=1'x for cells of type $_DFFE_PP_.
|
|
No more expansions possible.
|
|
<suppressed ~296 debug messages>
|
|
|
|
4.40. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module harness_memory_manager.
|
|
<suppressed ~328 debug messages>
|
|
|
|
4.41. Executing SIMPLEMAP pass (map simple cells to gate primitives).
|
|
|
|
4.42. Executing LATTICE_GSR pass (implement FF init values).
|
|
Handling GSR in harness_memory_manager.
|
|
|
|
4.43. Executing ATTRMVCP pass (move or copy attributes).
|
|
|
|
4.44. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \harness_memory_manager..
|
|
Removed 0 unused cells and 1064 unused wires.
|
|
<suppressed ~1 debug messages>
|
|
|
|
4.45. Executing CHECK pass (checking for obvious problems).
|
|
Checking module harness_memory_manager...
|
|
Found and reported 0 problems.
|
|
|
|
4.46. Executing TECHMAP pass (map to technology primitives).
|
|
|
|
4.46.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/latches_map.v
|
|
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/latches_map.v' to AST representation.
|
|
Generating RTLIL representation for module `$_DLATCH_N_'.
|
|
Generating RTLIL representation for module `$_DLATCH_P_'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
4.46.2. Continuing TECHMAP pass.
|
|
No more expansions possible.
|
|
<suppressed ~4 debug messages>
|
|
|
|
4.47. Executing ABC9 pass.
|
|
|
|
4.47.1. Executing ABC9_OPS pass (helper functions for ABC9).
|
|
|
|
4.47.2. Executing ABC9_OPS pass (helper functions for ABC9).
|
|
|
|
4.47.3. Executing SCC pass (detecting logic loops).
|
|
Found 0 SCCs in module harness_memory_manager.
|
|
Found 0 SCCs.
|
|
|
|
4.47.4. Executing ABC9_OPS pass (helper functions for ABC9).
|
|
|
|
4.47.5. Executing TECHMAP pass (map to technology primitives).
|
|
|
|
4.47.5.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/techmap.v
|
|
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/techmap.v' to AST representation.
|
|
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
|
|
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
|
|
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
|
|
Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
|
|
Generating RTLIL representation for module `\_90_simplemap_various'.
|
|
Generating RTLIL representation for module `\_90_simplemap_registers'.
|
|
Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
|
|
Generating RTLIL representation for module `\_90_shift_shiftx'.
|
|
Generating RTLIL representation for module `\_90_fa'.
|
|
Generating RTLIL representation for module `\_90_lcu_brent_kung'.
|
|
Generating RTLIL representation for module `\_90_alu'.
|
|
Generating RTLIL representation for module `\_90_macc'.
|
|
Generating RTLIL representation for module `\_90_alumacc'.
|
|
Generating RTLIL representation for module `$__div_mod_u'.
|
|
Generating RTLIL representation for module `$__div_mod_trunc'.
|
|
Generating RTLIL representation for module `\_90_div'.
|
|
Generating RTLIL representation for module `\_90_mod'.
|
|
Generating RTLIL representation for module `$__div_mod_floor'.
|
|
Generating RTLIL representation for module `\_90_divfloor'.
|
|
Generating RTLIL representation for module `\_90_modfloor'.
|
|
Generating RTLIL representation for module `\_90_pow'.
|
|
Generating RTLIL representation for module `\_90_demux'.
|
|
Generating RTLIL representation for module `\_90_lut'.
|
|
Generating RTLIL representation for module `$connect'.
|
|
Generating RTLIL representation for module `$input_port'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
4.47.5.2. Continuing TECHMAP pass.
|
|
No more expansions possible.
|
|
<suppressed ~166 debug messages>
|
|
|
|
4.47.6. Executing OPT pass (performing simple optimizations).
|
|
|
|
4.47.6.1. Executing OPT_EXPR pass (perform const folding).
|
|
|
|
4.47.6.2. Executing OPT_MERGE pass (detect identical cells).
|
|
Removed a total of 0 cells.
|
|
|
|
4.47.6.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Removed 0 multiplexer ports.
|
|
|
|
4.47.6.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Performed a total of 0 changes.
|
|
|
|
4.47.6.5. Executing OPT_MERGE pass (detect identical cells).
|
|
Removed a total of 0 cells.
|
|
|
|
4.47.6.6. Executing OPT_DFF pass (perform DFF optimizations).
|
|
|
|
4.47.6.7. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
|
|
4.47.6.8. Executing OPT_EXPR pass (perform const folding).
|
|
|
|
4.47.6.9. Finished fast OPT passes. (There is nothing left to do.)
|
|
|
|
4.47.7. Executing TECHMAP pass (map to technology primitives).
|
|
|
|
4.47.7.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/abc9_map.v
|
|
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/abc9_map.v' to AST representation.
|
|
Successfully finished Verilog frontend.
|
|
|
|
4.47.7.2. Continuing TECHMAP pass.
|
|
No more expansions possible.
|
|
<suppressed ~2 debug messages>
|
|
|
|
4.47.8. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/abc9_model.v
|
|
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/abc9_model.v' to AST representation.
|
|
Generating RTLIL representation for module `$__ABC9_DELAY'.
|
|
Generating RTLIL representation for module `$__ABC9_SCC_BREAKER'.
|
|
Generating RTLIL representation for module `$__DFF_N__$abc9_flop'.
|
|
Generating RTLIL representation for module `$__DFF_P__$abc9_flop'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
4.47.9. Executing ABC9_OPS pass (helper functions for ABC9).
|
|
<suppressed ~2 debug messages>
|
|
|
|
4.47.10. Executing ABC9_OPS pass (helper functions for ABC9).
|
|
|
|
4.47.11. Executing ABC9_OPS pass (helper functions for ABC9).
|
|
<suppressed ~2 debug messages>
|
|
|
|
4.47.12. Executing TECHMAP pass (map to technology primitives).
|
|
|
|
4.47.12.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/techmap.v
|
|
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/techmap.v' to AST representation.
|
|
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
|
|
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
|
|
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
|
|
Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
|
|
Generating RTLIL representation for module `\_90_simplemap_various'.
|
|
Generating RTLIL representation for module `\_90_simplemap_registers'.
|
|
Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
|
|
Generating RTLIL representation for module `\_90_shift_shiftx'.
|
|
Generating RTLIL representation for module `\_90_fa'.
|
|
Generating RTLIL representation for module `\_90_lcu_brent_kung'.
|
|
Generating RTLIL representation for module `\_90_alu'.
|
|
Generating RTLIL representation for module `\_90_macc'.
|
|
Generating RTLIL representation for module `\_90_alumacc'.
|
|
Generating RTLIL representation for module `$__div_mod_u'.
|
|
Generating RTLIL representation for module `$__div_mod_trunc'.
|
|
Generating RTLIL representation for module `\_90_div'.
|
|
Generating RTLIL representation for module `\_90_mod'.
|
|
Generating RTLIL representation for module `$__div_mod_floor'.
|
|
Generating RTLIL representation for module `\_90_divfloor'.
|
|
Generating RTLIL representation for module `\_90_modfloor'.
|
|
Generating RTLIL representation for module `\_90_pow'.
|
|
Generating RTLIL representation for module `\_90_demux'.
|
|
Generating RTLIL representation for module `\_90_lut'.
|
|
Generating RTLIL representation for module `$connect'.
|
|
Generating RTLIL representation for module `$input_port'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
4.47.12.2. Continuing TECHMAP pass.
|
|
Using template $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C for cells of type $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C.
|
|
Using extmapper simplemap for cells of type $or.
|
|
Using extmapper simplemap for cells of type $and.
|
|
Using extmapper simplemap for cells of type $not.
|
|
Using extmapper simplemap for cells of type $xor.
|
|
Using template $paramod\LUT2\INIT=4'1010 for cells of type LUT2.
|
|
Using template $paramod\LUT4\INIT=16'1001011010101010 for cells of type LUT4.
|
|
Using extmapper simplemap for cells of type $mux.
|
|
No more expansions possible.
|
|
<suppressed ~205 debug messages>
|
|
|
|
4.47.13. Executing OPT pass (performing simple optimizations).
|
|
|
|
4.47.13.1. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module harness_memory_manager.
|
|
<suppressed ~18 debug messages>
|
|
|
|
4.47.13.2. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\harness_memory_manager'.
|
|
Computing hashes of 59 cells of `\harness_memory_manager'.
|
|
Finding duplicate cells in `\harness_memory_manager'.
|
|
Computing hashes of 57 cells of `\harness_memory_manager'.
|
|
Finding duplicate cells in `\harness_memory_manager'.
|
|
<suppressed ~6 debug messages>
|
|
Removed a total of 2 cells.
|
|
|
|
4.47.13.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \harness_memory_manager..
|
|
Creating internal representation of mux trees.
|
|
No muxes found in this module.
|
|
Removed 0 multiplexer ports.
|
|
|
|
4.47.13.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \harness_memory_manager.
|
|
Performed a total of 0 changes.
|
|
|
|
4.47.13.5. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\harness_memory_manager'.
|
|
Computing hashes of 57 cells of `\harness_memory_manager'.
|
|
Finding duplicate cells in `\harness_memory_manager'.
|
|
Removed a total of 0 cells.
|
|
|
|
4.47.13.6. Executing OPT_DFF pass (perform DFF optimizations).
|
|
|
|
4.47.13.7. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \harness_memory_manager..
|
|
Removed 0 unused cells and 55 unused wires.
|
|
<suppressed ~1 debug messages>
|
|
|
|
4.47.13.8. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module harness_memory_manager.
|
|
|
|
4.47.13.9. Rerunning OPT passes. (Maybe there is more to do..)
|
|
|
|
4.47.13.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \harness_memory_manager..
|
|
Creating internal representation of mux trees.
|
|
No muxes found in this module.
|
|
Removed 0 multiplexer ports.
|
|
|
|
4.47.13.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \harness_memory_manager.
|
|
Performed a total of 0 changes.
|
|
|
|
4.47.13.12. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\harness_memory_manager'.
|
|
Computing hashes of 57 cells of `\harness_memory_manager'.
|
|
Finding duplicate cells in `\harness_memory_manager'.
|
|
Removed a total of 0 cells.
|
|
|
|
4.47.13.13. Executing OPT_DFF pass (perform DFF optimizations).
|
|
|
|
4.47.13.14. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \harness_memory_manager..
|
|
|
|
4.47.13.15. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module harness_memory_manager.
|
|
|
|
4.47.13.16. Finished fast OPT passes. (There is nothing left to do.)
|
|
|
|
4.47.14. Executing AIGMAP pass (map logic to AIG).
|
|
Module harness_memory_manager: replaced 18 cells with 120 new cells, skipped 39 cells.
|
|
replaced 3 cell types:
|
|
14 $_MUX_
|
|
2 $_OR_
|
|
2 $_XOR_
|
|
not replaced 3 cell types:
|
|
4 $_AND_
|
|
4 $_NOT_
|
|
31 $specify2
|
|
|
|
4.47.15. Executing AIGMAP pass (map logic to AIG).
|
|
Module harness_memory_manager: replaced 623 cells with 3832 new cells, skipped 485 cells.
|
|
replaced 4 cell types:
|
|
346 $_MUX_
|
|
1 $_ORNOT_
|
|
175 $_OR_
|
|
101 $_XOR_
|
|
not replaced 5 cell types:
|
|
143 $_AND_
|
|
78 $_NOT_
|
|
2 $scopeinfo
|
|
203 TRELLIS_FF
|
|
59 $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C
|
|
|
|
4.47.15.1. Executing ABC9_OPS pass (helper functions for ABC9).
|
|
|
|
4.47.15.2. Executing ABC9_OPS pass (helper functions for ABC9).
|
|
|
|
4.47.15.3. Executing XAIGER backend.
|
|
<suppressed ~11 debug messages>
|
|
Extracted 1660 AND gates and 4563 wires from module `harness_memory_manager' to a netlist network with 213 inputs and 195 outputs.
|
|
|
|
4.47.15.4. Executing ABC9_EXE pass (technology mapping using ABC9).
|
|
|
|
4.47.15.5. Executing ABC9.
|
|
Running ABC command: "<yosys-exe-dir>/yosys-abc" -s -f <abc-temp-dir>/abc.script 2>&1
|
|
ABC: ======== ABC command line "source <abc-temp-dir>/abc.script"
|
|
ABC: + read_lut <abc-temp-dir>/input.lut
|
|
ABC: + read_box <abc-temp-dir>/input.box
|
|
ABC: + &read <abc-temp-dir>/input.xaig
|
|
ABC: + &ps
|
|
ABC: <abc-temp-dir>/input : i/o = 213/ 195 and = 1241 lev = 40 (1.56) mem = 0.03 MB box = 59 bb = 0
|
|
ABC: + &scorr
|
|
ABC: Warning: The network is combinational.
|
|
ABC: + &sweep
|
|
ABC: + &dc2
|
|
ABC: + &dch -f -r
|
|
ABC: + &ps
|
|
ABC: <abc-temp-dir>/input : i/o = 213/ 195 and = 1071 lev = 35 (0.91) mem = 0.03 MB ch = 128 box = 46 bb = 0
|
|
ABC: cst = 0 cls = 121 lit = 128 unused = 1173 proof = 0
|
|
ABC: + &if -W 300 -v
|
|
ABC: K = 7. Memory (bytes): Truth = 0. Cut = 76. Obj = 156. Set = 780. CutMin = no
|
|
ABC: Node = 1071. Ch = 121. Total mem = 0.33 MB. Peak cut mem = 0.05 MB.
|
|
ABC: P: Del = 2695.00. Ar = 421.0. Edge = 682. Cut = 10209. T = 0.00 sec
|
|
ABC: P: Del = 2695.00. Ar = 419.0. Edge = 682. Cut = 10160. T = 0.00 sec
|
|
ABC: P: Del = 2695.00. Ar = 276.0. Edge = 727. Cut = 12681. T = 0.00 sec
|
|
ABC: F: Del = 2694.00. Ar = 254.0. Edge = 706. Cut = 12158. T = 0.00 sec
|
|
ABC: A: Del = 2694.00. Ar = 253.0. Edge = 665. Cut = 11942. T = 0.00 sec
|
|
ABC: A: Del = 2694.00. Ar = 253.0. Edge = 665. Cut = 11972. T = 0.00 sec
|
|
ABC: Total time = 0.01 sec
|
|
ABC: + &write -n <abc-temp-dir>/output.aig
|
|
ABC: + &mfs
|
|
ABC: + &ps -l
|
|
ABC: <abc-temp-dir>/input : i/o = 213/ 195 and = 798 lev = 11 (0.73) mem = 0.02 MB box = 46 bb = 0
|
|
ABC: Mapping (K=7) : lut = 188 edge = 665 lev = 4 (0.36) levB = 11 mem = 0.01 MB
|
|
ABC: LUT = 188 : 2=30 16.0 % 3=79 42.0 % 4=36 19.1 % 5=36 19.1 % 6=5 2.7 % 7=2 1.1 % Ave = 3.54
|
|
ABC: + &write -n <abc-temp-dir>/output.aig
|
|
ABC: + &verify
|
|
ABC: Networks are equivalent. Time = 0.01 sec
|
|
ABC: + time
|
|
ABC: elapse: 0.06 seconds, total: 0.06 seconds
|
|
|
|
4.47.15.6. Executing AIGER frontend.
|
|
<suppressed ~10 debug messages>
|
|
Removed 1366 unused cells and 2254 unused wires.
|
|
|
|
4.47.15.7. Executing ABC_OPS_REINTEGRATE pass (reintegrate ABC mapped design into module).
|
|
ABC RESULTS: $lut cells: 192
|
|
ABC RESULTS: $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C cells: 46
|
|
ABC RESULTS: input signals: 29
|
|
ABC RESULTS: output signals: 57
|
|
<suppressed ~829 debug messages>
|
|
Removing temp directory.
|
|
|
|
4.47.16. Executing TECHMAP pass (map to technology primitives).
|
|
|
|
4.47.16.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/abc9_unmap.v
|
|
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/abc9_unmap.v' to AST representation.
|
|
Generating RTLIL representation for module `$__DFF_x__$abc9_flop'.
|
|
Generating RTLIL representation for module `$__ABC9_SCC_BREAKER'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
4.47.16.2. Continuing TECHMAP pass.
|
|
Using template $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C for cells of type $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C.
|
|
No more expansions possible.
|
|
<suppressed ~52 debug messages>
|
|
Removed 34 unused cells and 5237 unused wires.
|
|
|
|
4.48. Executing TECHMAP pass (map to technology primitives).
|
|
|
|
4.48.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v
|
|
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v' to AST representation.
|
|
Generating RTLIL representation for module `$_DFF_N_'.
|
|
Generating RTLIL representation for module `$_DFF_P_'.
|
|
Generating RTLIL representation for module `$_DFFE_NN_'.
|
|
Generating RTLIL representation for module `$_DFFE_PN_'.
|
|
Generating RTLIL representation for module `$_DFFE_NP_'.
|
|
Generating RTLIL representation for module `$_DFFE_PP_'.
|
|
Generating RTLIL representation for module `$_DFF_NP0_'.
|
|
Generating RTLIL representation for module `$_DFF_NP1_'.
|
|
Generating RTLIL representation for module `$_DFF_PP0_'.
|
|
Generating RTLIL representation for module `$_DFF_PP1_'.
|
|
Generating RTLIL representation for module `$_SDFF_NP0_'.
|
|
Generating RTLIL representation for module `$_SDFF_NP1_'.
|
|
Generating RTLIL representation for module `$_SDFF_PP0_'.
|
|
Generating RTLIL representation for module `$_SDFF_PP1_'.
|
|
Generating RTLIL representation for module `$_DFFE_NP0P_'.
|
|
Generating RTLIL representation for module `$_DFFE_NP1P_'.
|
|
Generating RTLIL representation for module `$_DFFE_PP0P_'.
|
|
Generating RTLIL representation for module `$_DFFE_PP1P_'.
|
|
Generating RTLIL representation for module `$_DFFE_NP0N_'.
|
|
Generating RTLIL representation for module `$_DFFE_NP1N_'.
|
|
Generating RTLIL representation for module `$_DFFE_PP0N_'.
|
|
Generating RTLIL representation for module `$_DFFE_PP1N_'.
|
|
Generating RTLIL representation for module `$_SDFFE_NP0P_'.
|
|
Generating RTLIL representation for module `$_SDFFE_NP1P_'.
|
|
Generating RTLIL representation for module `$_SDFFE_PP0P_'.
|
|
Generating RTLIL representation for module `$_SDFFE_PP1P_'.
|
|
Generating RTLIL representation for module `$_SDFFE_NP0N_'.
|
|
Generating RTLIL representation for module `$_SDFFE_NP1N_'.
|
|
Generating RTLIL representation for module `$_SDFFE_PP0N_'.
|
|
Generating RTLIL representation for module `$_SDFFE_PP1N_'.
|
|
Generating RTLIL representation for module `$_ALDFF_NP_'.
|
|
Generating RTLIL representation for module `$_ALDFF_PP_'.
|
|
Generating RTLIL representation for module `$_ALDFFE_NPN_'.
|
|
Generating RTLIL representation for module `$_ALDFFE_NPP_'.
|
|
Generating RTLIL representation for module `$_ALDFFE_PPN_'.
|
|
Generating RTLIL representation for module `$_ALDFFE_PPP_'.
|
|
Generating RTLIL representation for module `\FD1P3AX'.
|
|
Generating RTLIL representation for module `\FD1P3AY'.
|
|
Generating RTLIL representation for module `\FD1P3BX'.
|
|
Generating RTLIL representation for module `\FD1P3DX'.
|
|
Generating RTLIL representation for module `\FD1P3IX'.
|
|
Generating RTLIL representation for module `\FD1P3JX'.
|
|
Generating RTLIL representation for module `\FD1S3AX'.
|
|
Generating RTLIL representation for module `\FD1S3AY'.
|
|
Generating RTLIL representation for module `\FD1S3BX'.
|
|
Generating RTLIL representation for module `\FD1S3DX'.
|
|
Generating RTLIL representation for module `\FD1S3IX'.
|
|
Generating RTLIL representation for module `\FD1S3JX'.
|
|
Generating RTLIL representation for module `\IFS1P3BX'.
|
|
Generating RTLIL representation for module `\IFS1P3DX'.
|
|
Generating RTLIL representation for module `\IFS1P3IX'.
|
|
Generating RTLIL representation for module `\IFS1P3JX'.
|
|
Generating RTLIL representation for module `\OFS1P3BX'.
|
|
Generating RTLIL representation for module `\OFS1P3DX'.
|
|
Generating RTLIL representation for module `\OFS1P3IX'.
|
|
Generating RTLIL representation for module `\OFS1P3JX'.
|
|
Generating RTLIL representation for module `\IB'.
|
|
Generating RTLIL representation for module `\IBPU'.
|
|
Generating RTLIL representation for module `\IBPD'.
|
|
Generating RTLIL representation for module `\OB'.
|
|
Generating RTLIL representation for module `\OBZ'.
|
|
Generating RTLIL representation for module `\OBZPU'.
|
|
Generating RTLIL representation for module `\OBZPD'.
|
|
Generating RTLIL representation for module `\OBCO'.
|
|
Generating RTLIL representation for module `\BB'.
|
|
Generating RTLIL representation for module `\BBPU'.
|
|
Generating RTLIL representation for module `\BBPD'.
|
|
Generating RTLIL representation for module `\ILVDS'.
|
|
Generating RTLIL representation for module `\OLVDS'.
|
|
Generating RTLIL representation for module `$lut'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
4.48.2. Continuing TECHMAP pass.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10000000 for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0100 for cells of type $lut.
|
|
Using template $paramod$93ec78a4b6126ae3554c86addda654d541cb4719$lut for cells of type $lut.
|
|
Using template $paramod$77f0cd72667b23cc49e7a8bf984ad848b10003d7$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1110 for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01101010 for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10101100 for cells of type $lut.
|
|
Using template $paramod$fd904e9e35cfd343a9df248824bd3f1408724879$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01101100 for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11001010 for cells of type $lut.
|
|
Using template $paramod$0939298d426d727b8afa3e9642d621400f6da76d$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01000101 for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10001111 for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0001 for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10111010 for cells of type $lut.
|
|
Using template $paramod$9c65fdfac74256c2eb67dd209b598e25d1f0a099$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11111000 for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11101010 for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00010000 for cells of type $lut.
|
|
Using template $paramod$9dd298ae76fb41ac94779a83c068607fbc09ce4f$lut for cells of type $lut.
|
|
Using template $paramod$658b9ed803f0d3d335616d3858b53e0a2522f1e8$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000001 for cells of type $lut.
|
|
Using template $paramod$00ffcc628ccb870304683cac36ad3a16cc41b6a4$lut for cells of type $lut.
|
|
Using template $paramod$e89ac58f360f774aaa6ec82384df6d4f7265bb69$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0010 for cells of type $lut.
|
|
Using template $paramod$497f13c7e9d8874cb8b4b43fa26e853c983f9245$lut for cells of type $lut.
|
|
Using template $paramod$b5babc618720ace64bafddb303d6f59fd10af395$lut for cells of type $lut.
|
|
Using template $paramod$8512f4fb47fa9596f76cdbe5b407a5b54df368e7$lut for cells of type $lut.
|
|
Using template $paramod$d88fd66b53df71bbe52e82830648a83e094f1df5$lut for cells of type $lut.
|
|
Using template $paramod$86d1a43c2f1d620ff2cef866448dd1258c868fad$lut for cells of type $lut.
|
|
Using template $paramod$9f86076d51df9a4da463f6218e6cd2ddba0c7c03$lut for cells of type $lut.
|
|
Using template $paramod$464d286cc302627c2e44b6c4a8450c9bebc28389$lut for cells of type $lut.
|
|
Using template $paramod$ef977315233b261d896c6dc860993180807776fe$lut for cells of type $lut.
|
|
Using template $paramod$9d68839eeea365341905043c456ff287bcaf2673$lut for cells of type $lut.
|
|
Using template $paramod$571404c0889eaf57f492cb5e37f8acb5df5852f9$lut for cells of type $lut.
|
|
Using template $paramod$a2fe29d35d71ba7d334ca8c2b44396dd8da29e4d$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01001100 for cells of type $lut.
|
|
Using template $paramod$6b7c9c56fc2a32a479d463d5f3b0d3f4673b67f1$lut for cells of type $lut.
|
|
Using template $paramod$d0f38a65bef8d9a879a1b1d9ea0674536118587c$lut for cells of type $lut.
|
|
Using template $paramod$b45e5cb971154e30a797eecb0461619c3eeae12d$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00101100 for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1011 for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11001001 for cells of type $lut.
|
|
Using template $paramod$cba63f0d3ee9d49c25aa31a3006491d02c8ce45c$lut for cells of type $lut.
|
|
Using template $paramod$f5c97e291c8b48d9f1b4239d871ab7639e5a24ac$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10111000 for cells of type $lut.
|
|
Using template $paramod$87e4893c126e651fbcc858fe02419505665b5399$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01000000 for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00001101 for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1000 for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11011100 for cells of type $lut.
|
|
Using template $paramod$b27834385f52eaf4ed276ecbffb1b05d9c8a8b56$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11100100 for cells of type $lut.
|
|
Using template $paramod$5a203febca29678ab5583c0f96bc052b4d0c83a4$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10100011 for cells of type $lut.
|
|
Using template $paramod$8dea978432b975a06d487b3763d4d556f8d362b4$lut for cells of type $lut.
|
|
Using template $paramod$6a34cd5b50e324824168b4186d0b04ba5e83b039$lut for cells of type $lut.
|
|
Using template $paramod$21a9cf1c7cffed4ea7970972274e8bcced7c7005$lut for cells of type $lut.
|
|
Using template $paramod$0c822c65361ce832091b6c90f1a02f1ee0b109d4$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11011000 for cells of type $lut.
|
|
Using template $paramod$fea512844f0598125018304dfe86621dbf348f27$lut for cells of type $lut.
|
|
Using template $paramod$3718b46f9fc8e7db62b1202aeaec21c3331ed565$lut for cells of type $lut.
|
|
Using template $paramod$4f09540800ac966d6e31a7ccf5f32a559a8ce57a$lut for cells of type $lut.
|
|
Using template $paramod$05d370b062891027af6b8f05be843bc31de021fe$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01010100 for cells of type $lut.
|
|
Using template $paramod$d9f23974f72a3ab437d1a63d2f34fd3483a6f58d$lut for cells of type $lut.
|
|
Using template $paramod$68f172e97da51dd6c1b822ba5fb6b7d7637cc6ee$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000100 for cells of type $lut.
|
|
Using template $paramod$643ce31b2f69d175e7b02dbd6812353f778f3a34$lut for cells of type $lut.
|
|
Using template $paramod$87dddaec08d92df4cf510a25382b68aa17e8b57e$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00101010 for cells of type $lut.
|
|
Using template $paramod$aea49449ff8b0f1602874cfa6c3a753c41a1b4a8$lut for cells of type $lut.
|
|
Using template $paramod$8829675bb8c52553aed9f101ec0d5ef0c865e5c7$lut for cells of type $lut.
|
|
Using template $paramod$4133fe00eb18442862a284ccc67a95f8194d041c$lut for cells of type $lut.
|
|
Using template $paramod$6d6beead1425af15cf78b27fd9b11b41b5d4bce8$lut for cells of type $lut.
|
|
Using template $paramod$b9d8b7e91a2c68da033af948ea0bd8bdebbaf6b2$lut for cells of type $lut.
|
|
Using template $paramod$2713208c8364adbd0af661a2a44fb5c0ddb61fdf$lut for cells of type $lut.
|
|
Using template $paramod$41326ad8644342a66dfb051d050f2b6fbf15015b$lut for cells of type $lut.
|
|
Using template $paramod$1b4942fad7257f60532954b1eb94a6b84f2e5ae3$lut for cells of type $lut.
|
|
Using template $paramod$a03ef989f8f4e1878ce2f5c4e0e3d2dfb54307ef$lut for cells of type $lut.
|
|
Using template $paramod$c231c665eed0e54f6cd365c2b07ecdea418a10e6$lut for cells of type $lut.
|
|
Using template $paramod$2d73cf21e7a3b53006ebbae47ecc48e73975ec46$lut for cells of type $lut.
|
|
Using template $paramod$d575d3554e876f643193272ee6813447059f103f$lut for cells of type $lut.
|
|
Using template $paramod$3575d59b4ef3f53a6d1fe17e5c5d02df47e8ec93$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000001\LUT=2'01 for cells of type $lut.
|
|
No more expansions possible.
|
|
<suppressed ~1369 debug messages>
|
|
|
|
4.49. Executing OPT_LUT_INS pass (discard unused LUT inputs).
|
|
Optimizing LUTs in harness_memory_manager.
|
|
Optimizing lut $abc$17166$lut$aiger$o528.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
|
|
Optimizing lut $abc$17166$lut$aiger$o488.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
|
|
Optimizing lut $abc$17166$lut$aiger$o455.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$17187.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
|
|
Optimizing lut $abc$17166$lut$aiger17165$550.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
|
|
Optimizing lut $abc$17166$lut$aiger17165$550.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
|
|
Optimizing lut $abc$17166$lut$aiger17165$497.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
|
|
Optimizing lut $abc$17166$lut$aiger17165$497.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
|
|
Optimizing lut $abc$17166$lut$aiger17165$519.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$17166$lut$aiger$o472.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$17177.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$17177.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$17187.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$17166$lut$aiger17165$550.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$17186.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$17187.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$17166$lut$aiger$o528.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
|
|
Optimizing lut $abc$17166$lut$aiger$o528.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
|
|
Optimizing lut $abc$17166$lut$aiger$o466.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
|
|
Optimizing lut $abc$17166$lut$aiger$o488.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$17166$lut$aiger$o488.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$17166$lut$aiger17165$497.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $abc$17166$lut$aiger17165$497.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
|
|
Optimizing lut $abc$17166$lut$aiger17165$519.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$17166$lut$aiger17165$537.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
|
|
Optimizing lut $abc$17166$lut$aiger17165$527.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $abc$17166$lut$aiger17165$531.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
|
|
Optimizing lut $abc$17166$lut$aiger$o415.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Removed 0 unused cells and 423 unused wires.
|
|
|
|
4.50. Executing AUTONAME pass.
|
|
Renamed 913 objects in module harness_memory_manager.
|
|
<suppressed ~913 debug messages>
|
|
|
|
4.51. Executing HIERARCHY pass (managing design hierarchy).
|
|
Attribute `top' found on module `harness_memory_manager'. Setting top module to harness_memory_manager.
|
|
|
|
4.51.1. Analyzing design hierarchy..
|
|
Top module: \harness_memory_manager
|
|
|
|
4.51.2. Analyzing design hierarchy..
|
|
Top module: \harness_memory_manager
|
|
Removed 0 unused modules.
|
|
|
|
4.52. Printing statistics.
|
|
|
|
=== harness_memory_manager ===
|
|
|
|
+----------Local Count, excluding submodules.
|
|
|
|
|
435 wires
|
|
2001 wire bits
|
|
435 public wires
|
|
2001 public wire bits
|
|
4 ports
|
|
18 port bits
|
|
2 cells
|
|
2 $scopeinfo
|
|
571 submodules
|
|
46 CCU2C
|
|
11 L6MUX21
|
|
257 LUT4
|
|
54 PFUMX
|
|
203 TRELLIS_FF
|
|
|
|
=== design hierarchy ===
|
|
|
|
+----------Count including submodules.
|
|
|
|
|
2 harness_memory_manager
|
|
|
|
+----------Count including submodules.
|
|
|
|
|
435 wires
|
|
2001 wire bits
|
|
435 public wires
|
|
2001 public wire bits
|
|
4 ports
|
|
18 port bits
|
|
- memories
|
|
- memory bits
|
|
- processes
|
|
2 cells
|
|
2 $scopeinfo
|
|
571 submodules
|
|
46 CCU2C
|
|
11 L6MUX21
|
|
257 LUT4
|
|
54 PFUMX
|
|
203 TRELLIS_FF
|
|
|
|
4.53. Executing CHECK pass (checking for obvious problems).
|
|
Checking module harness_memory_manager...
|
|
Found and reported 0 problems.
|
|
|
|
4.54. Executing JSON backend.
|
|
|
|
End of script. Logfile hash: 18af420c8c, time: 0.61s, user: 0.53s, system: 0.02s, MEM: 65.89 MB peak
|
|
Yosys 0.68+post (git sha1 c12172fbae8af5e20f6fb52e3d4e92d56ed587b6, Release, AppleClang clang++ 21.0.0.21000101)
|
|
Time spent: 29% 25x read_verilog (0 sec), 12% 1x abc9_exe (0 sec), ...
|