micheleandClaude Sonnet 5
80c89fa10d
New tb_neural_processor_layer_reuse.v wires the real SDRAM controller, layer_prefetch_ctrl.v and layer_weight_buffer.v into a real neural_processor.v compute engine: one resident filter is fetched once and reused across 8 independent jobs per layer, verified bit-exact against an independent golden dot-product model (32/32 PASS). Also found and fixed a real testbench-vs-DUT scheduling race present in tb_layer_prefetch_ctrl.v (and hardened in the new file): clearing a one-cycle control pulse on the very next clock edge lands the clear in the same active-region pass as the edge a receiving module's own synchronous logic reads it at, so the pulse can be silently missed depending on implementation-defined process ordering. This had been silently preventing tb_layer_prefetch_ctrl.v's own claimed 8192/8192 result from ever actually being observed; fixed by holding the pulse past the edge with a real time delay before clearing, and the 8192/8192 result is now genuinely reproducible (5/5 consecutive runs). Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01MUG92aM9m68TRc4rG55BcC
359 lines
16 KiB
Verilog
359 lines
16 KiB
Verilog
`timescale 1ns/1ps
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// ============================================================
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// EXP-0058 -- first real end-to-end integration of the EXP-0057
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// weight-reuse building blocks with the real M1 compute engine
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// (neural_processor.v). Wires together, ALL real RTL except the
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// per-tile weight-byte gather (see note below):
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//
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// sdram_controller_openrow.v + sdram_model.v (real DDR-less SDR SDRAM path)
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// -> layer_prefetch_ctrl.v (real RTL, EXP-0057b)
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// -> layer_weight_buffer.v (real RTL, double-buffered, EXP-0057)
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// -> [testbench byte-gather, see note]
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// -> neural_processor.v (real RTL, M1 compute engine)
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//
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// One "layer" = one resident filter (N_INPUTS=128 taps, 16 P_IN=8
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// tiles) fetched ONCE from SDRAM into layer_weight_buffer.v, then
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// REUSED across M independent "positions" (jobs) -- exactly modeling
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// a real convolution filter held stationary while it slides across M
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// different input windows, which is the whole point of EXP-0057's
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// architecture. Input data for each position is synthetic (formula-
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// generated, not fetched from SDRAM -- representing the activation/
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// sliding-window path, which is a separate, already-existing memory
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// path not the subject of this test) but deterministic and combined
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// with an INDEPENDENT golden dot-product+bias+ReLU model (same
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// "third oracle" style as tb_neural_processor.v's own expect_relu,
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// duplicated here rather than shared, per that file's own stated
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// convention).
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//
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// NOTE on the byte-gather step: neural_processor.v consumes one
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// P_IN=8-wide (64-bit) weight_data tile per handshake cycle, but
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// layer_weight_buffer.v is byte-wide (one address = one byte, already
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// verified in isolation, EXP-0057). Assembling 8 sequential
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// byte-wide reads into one 64-bit tile bus is done here by the
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// testbench driver task. This gather step is NOT synthesizable RTL
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// yet -- a real "tile gather adapter" (8:1 byte-to-tile packer) would
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// be the natural next M4 Memory Manager deliverable if this
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// architecture is adopted, deliberately out of scope here: this
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// test's purpose is to verify DATA correctness of the weight-reuse
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// path feeding the real compute engine, not to deliver the final
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// gather RTL.
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//
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// Scope: correctness only (sequential, no prefetch/consume overlap
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// across layers -- the double-buffered PERFORMANCE benefit was
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// already measured in isolation, 7.16x, tb_layer_reuse_vs_zero_reuse.v,
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// EXP-0057, not re-derived here).
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// ============================================================
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module tb;
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localparam BURST_LEN = 8;
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localparam ROW_BITS = 13;
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localparam COL_BITS = 10;
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localparam BANK_BITS = 2;
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localparam ADDR_WIDTH = BANK_BITS + ROW_BITS + COL_BITS;
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localparam CLK_FREQ_MHZ = 64;
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localparam CLK_PERIOD_NS = 1000.0/CLK_FREQ_MHZ;
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localparam DATA_WIDTH = 8;
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localparam P_IN = 8;
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localparam ACC_WIDTH = 32;
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localparam N_INPUTS = 128; // one resident filter = 128 taps
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localparam N_TILES = N_INPUTS/P_IN; // 16
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localparam LAYER_BYTES = N_INPUTS; // 1 byte/tap, DATA_WIDTH=8
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localparam L = 4; // layers (resident filters)
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localparam M = 8; // reuse positions per layer
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localparam WORDS_PER_LAYER = LAYER_BYTES/2;
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localparam ACT_RELU = 2'd1;
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reg clk = 0;
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always #(CLK_PERIOD_NS/2.0) clk = ~clk;
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reg rst;
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integer cyc;
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always @(posedge clk) if (!rst) cyc <= cyc + 1;
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// ---- real SDRAM controller + model ----
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wire ctrl_req, ctrl_wr;
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wire [ADDR_WIDTH-1:0] ctrl_addr;
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wire [16*BURST_LEN-1:0] ctrl_wdata;
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wire [2*BURST_LEN-1:0] ctrl_wmask;
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wire [16*BURST_LEN-1:0] ctrl_rdata;
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wire ctrl_ready, ctrl_busy;
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wire cke, cs_n, ras_n, cas_n, we_n;
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wire [BANK_BITS-1:0] ba;
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wire [ROW_BITS-1:0] a;
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wire [15:0] dq;
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wire [1:0] dqm;
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sdram_controller_openrow #(
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.CLK_FREQ_MHZ(CLK_FREQ_MHZ), .BURST_LEN(BURST_LEN),
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.ROW_BITS(ROW_BITS), .COL_BITS(COL_BITS), .BANK_BITS(BANK_BITS)
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) u_ctrl (
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.clk(clk), .rst(rst),
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.req(ctrl_req), .wr(ctrl_wr), .addr(ctrl_addr), .wdata(ctrl_wdata), .wmask(ctrl_wmask),
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.rdata(ctrl_rdata), .ready(ctrl_ready), .busy(ctrl_busy),
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.sdram_cke(cke), .sdram_cs_n(cs_n), .sdram_ras_n(ras_n), .sdram_cas_n(cas_n), .sdram_we_n(we_n),
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.sdram_ba(ba), .sdram_a(a), .sdram_dq(dq), .sdram_dqm(dqm)
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);
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sdram_model #(
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.CLK_FREQ_MHZ(CLK_FREQ_MHZ), .ROW_BITS(ROW_BITS), .COL_BITS(COL_BITS), .BANK_BITS(BANK_BITS)
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) u_mem (
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.clk(clk), .cke(cke), .cs_n(cs_n), .ras_n(ras_n), .cas_n(cas_n), .we_n(we_n),
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.ba(ba), .a(a), .dq(dq), .dqm(dqm)
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);
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// separate write-capable path to preload SDRAM with the L filters'
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// weight bytes (write and prefetch never run concurrently here)
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reg wpre_req, wpre_wr;
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reg [ADDR_WIDTH-1:0] wpre_addr;
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reg [16*BURST_LEN-1:0] wpre_wdata;
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reg pre_active;
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wire pf_ctrl_req, pf_ctrl_wr;
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wire [ADDR_WIDTH-1:0] pf_ctrl_addr;
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wire [16*BURST_LEN-1:0] pf_ctrl_wdata;
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wire [2*BURST_LEN-1:0] pf_ctrl_wmask;
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assign ctrl_req = pre_active ? wpre_req : pf_ctrl_req;
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assign ctrl_wr = pre_active ? wpre_wr : pf_ctrl_wr;
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assign ctrl_addr = pre_active ? wpre_addr : pf_ctrl_addr;
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assign ctrl_wdata = pre_active ? wpre_wdata : pf_ctrl_wdata;
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assign ctrl_wmask = pre_active ? {(2*BURST_LEN){1'b0}} : pf_ctrl_wmask;
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// ---- deterministic weight/input formulas (shared between SDRAM
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// preload, the golden model, and -- for weights -- indirectly
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// verified via the real buffer read-back) ----
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function automatic signed [7:0] weight_byte(input integer li, input integer t);
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weight_byte = $signed(8'((li*17 + t*29 + 13) & 8'hFF));
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endfunction
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function automatic signed [7:0] input_byte(input integer li, input integer pos, input integer t);
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input_byte = $signed(8'((li*11 + pos*41 + t*7 + 3) & 8'hFF));
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endfunction
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task automatic sdram_write_burst(input [ADDR_WIDTH-1:0] word_addr, input [16*BURST_LEN-1:0] data);
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begin
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@(posedge clk); while (ctrl_busy) @(posedge clk);
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wpre_req = 1'b1; wpre_wr = 1'b1; wpre_addr = word_addr; wpre_wdata = data;
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@(posedge clk); wpre_req = 1'b0;
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while (!ctrl_ready) @(posedge clk);
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end
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endtask
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task automatic preload_sdram_layers;
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integer li, bi, wb, tt;
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reg [16*BURST_LEN-1:0] burst_data;
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begin
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for (li = 0; li < L; li = li + 1) begin
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for (bi = 0; bi < (LAYER_BYTES/(2*BURST_LEN)); bi = bi + 1) begin
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for (wb = 0; wb < BURST_LEN; wb = wb + 1) begin
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// one burst = BURST_LEN words = 2*BURST_LEN bytes/taps
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// (1 byte/tap); word wb holds taps [bi*2*BURST_LEN+wb*2]
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// (low byte) and [...+wb*2+1] (high byte), matching
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// layer_prefetch_ctrl.v's own drain_cnt byte order
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// (drain_cnt = wb*2 -> low byte, wb*2+1 -> high byte).
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tt = bi*(2*BURST_LEN) + wb*2;
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burst_data[wb*16 +: 16] = {weight_byte(li, tt+1), weight_byte(li, tt)};
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end
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sdram_write_burst((li*WORDS_PER_LAYER + bi*BURST_LEN), burst_data);
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end
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end
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end
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endtask
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// ---- layer_prefetch_ctrl.v (real RTL) ----
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reg pf_start;
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reg [ADDR_WIDTH-1:0] pf_layer_base;
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wire pf_busy, pf_done;
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wire pf_fill_we;
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wire [$clog2(LAYER_BYTES)-1:0] pf_fill_addr;
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wire [7:0] pf_fill_data;
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layer_prefetch_ctrl #(
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.DATA_WIDTH(8), .LAYER_BYTES(LAYER_BYTES), .BURST_LEN(BURST_LEN), .ADDR_WIDTH(ADDR_WIDTH)
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) u_pf (
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.clk(clk), .rst(rst),
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.start(pf_start), .layer_base(pf_layer_base), .busy(pf_busy), .done(pf_done),
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.fill_we(pf_fill_we), .fill_addr(pf_fill_addr), .fill_data(pf_fill_data),
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.ctrl_req(pf_ctrl_req), .ctrl_wr(pf_ctrl_wr), .ctrl_addr(pf_ctrl_addr),
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.ctrl_wdata(pf_ctrl_wdata), .ctrl_wmask(pf_ctrl_wmask),
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.ctrl_rdata(ctrl_rdata), .ctrl_ready(ctrl_ready), .ctrl_busy(ctrl_busy)
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);
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// ---- layer_weight_buffer.v (real RTL) ----
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reg [$clog2(LAYER_BYTES)-1:0] rd_addr;
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wire [7:0] rd_data;
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reg consume_done;
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wire active_sel, swapped;
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layer_weight_buffer #(.DATA_WIDTH(8), .LAYER_DEPTH(LAYER_BYTES)) u_lwb (
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.clk(clk), .rst(rst),
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.fill_we(pf_fill_we), .fill_addr(pf_fill_addr), .fill_data(pf_fill_data), .fill_done(pf_done),
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.rd_addr(rd_addr), .rd_data(rd_data), .consume_done(consume_done),
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.active_sel(active_sel), .swapped(swapped)
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);
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// ---- neural_processor.v (real RTL, M1 compute engine under test) ----
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reg job_valid;
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wire job_ready;
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reg [15:0] job_node_id;
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reg signed [DATA_WIDTH-1:0] job_bias;
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reg [1:0] job_activation;
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reg operand_valid;
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wire operand_ready;
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reg signed [DATA_WIDTH*P_IN-1:0] input_data, weight_data;
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reg tile_last;
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wire result_valid;
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reg result_ready;
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wire signed [DATA_WIDTH-1:0] result_data;
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wire [15:0] result_node_id;
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wire [3:0] np_state;
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wire np_error;
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neural_processor #(
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.DATA_WIDTH(DATA_WIDTH), .P_IN(P_IN), .ACC_WIDTH(ACC_WIDTH)
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) u_np (
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.clk(clk), .rst(rst),
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.job_valid(job_valid), .job_ready(job_ready),
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.job_node_id(job_node_id), .job_bias(job_bias), .job_activation(job_activation),
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.operand_valid(operand_valid), .operand_ready(operand_ready),
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.input_data(input_data), .weight_data(weight_data), .tile_last(tile_last),
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.result_valid(result_valid), .result_ready(result_ready),
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.result_data(result_data), .result_node_id(result_node_id),
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.np_state(np_state), .np_error(np_error)
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);
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integer errors, tests;
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integer li_i, pos_i, t, k, tt;
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reg [7:0] wbyte [0:P_IN-1];
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integer acc_calc, s_calc;
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reg signed [DATA_WIDTH-1:0] expected;
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integer t0, total_cycles;
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task automatic run_one_position(input integer li, input integer pos);
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begin
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@(posedge clk);
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tests = tests + 1;
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job_node_id = li[15:8]*8'(M) + pos[15:0];
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job_bias = {DATA_WIDTH{1'b0}};
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job_activation = ACT_RELU;
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job_valid = 1;
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while (!job_ready) @(posedge clk);
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@(posedge clk); #1; // handshake edge, then hold one extra delta before
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// clearing -- see the pulse-hardening note by
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// consume_done below (same class of same-edge
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// testbench-vs-DUT scheduling race)
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job_valid = 0;
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acc_calc = 0;
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for (t = 0; t < N_TILES; t = t + 1) begin
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// gather this tile's P_IN weight bytes from the real,
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// resident (already-swapped-in) layer_weight_buffer.v
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for (k = 0; k < P_IN; k = k + 1) begin
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rd_addr = (t*P_IN + k);
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#1;
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wbyte[k] = rd_data;
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end
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input_data = {DATA_WIDTH*P_IN{1'b0}};
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weight_data = {DATA_WIDTH*P_IN{1'b0}};
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for (k = 0; k < P_IN; k = k + 1) begin
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tt = t*P_IN + k;
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input_data[k*DATA_WIDTH +: DATA_WIDTH] = input_byte(li, pos, tt);
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weight_data[k*DATA_WIDTH +: DATA_WIDTH] = wbyte[k];
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// real, resident buffer readback must match the
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// formula used to preload SDRAM -- checked directly
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// (not just indirectly via the final dot product),
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// so a wrong buffer byte is caught even if the dot
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// product would coincidentally still match.
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if (wbyte[k] !== weight_byte(li, tt)) begin
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$display("FAIL li=%0d pos=%0d t=%0d k=%0d: buffer weight byte %0d expected %0d",
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li, pos, t, k, $signed(wbyte[k]), weight_byte(li, tt));
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errors = errors + 1;
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end
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acc_calc = acc_calc + (input_byte(li, pos, tt) * weight_byte(li, tt));
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end
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tile_last = (t == N_TILES - 1);
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operand_valid = 1;
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while (!operand_ready) @(posedge clk);
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@(posedge clk); #1;
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end
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operand_valid = 0;
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tile_last = 0;
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result_ready = 1;
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while (!result_valid) @(posedge clk);
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s_calc = acc_calc + 0; // job_bias == 0
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if (s_calc <= 0) expected = {DATA_WIDTH{1'b0}};
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else if (s_calc > 127) expected = 8'sd127;
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else expected = s_calc[DATA_WIDTH-1:0];
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if (result_data !== expected) begin
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$display("FAIL li=%0d pos=%0d: result=%0d expected=%0d (acc=%0d)",
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li, pos, $signed(result_data), $signed(expected), acc_calc);
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errors = errors + 1;
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end else begin
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$display("PASS li=%0d pos=%0d: result=%0d (acc=%0d, weight-reuse path, real RTL)",
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li, pos, $signed(result_data), acc_calc);
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end
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@(posedge clk);
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while (!job_ready || np_state !== 4'd0) @(posedge clk);
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end
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endtask
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initial begin
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errors = 0; tests = 0; cyc = 0;
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rst = 1; pre_active = 1'b1;
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wpre_req = 0; wpre_wr = 0; wpre_addr = 0; wpre_wdata = 0;
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pf_start = 0; pf_layer_base = 0; rd_addr = 0; consume_done = 0;
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job_valid = 0; job_node_id = 0; job_bias = 0; job_activation = ACT_RELU;
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operand_valid = 0; input_data = 0; weight_data = 0; tile_last = 0;
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result_ready = 0;
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repeat(5) @(posedge clk);
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rst = 0;
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@(posedge clk); while (ctrl_busy) @(posedge clk);
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$display("=== preload SDRAM with %0d resident-filter weight sets (%0d taps each) ===", L, N_INPUTS);
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preload_sdram_layers;
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@(posedge clk); // ERR-0001 workaround: sync before the first blocking
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// assignment following a time-consuming task call,
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// otherwise it can be invisible to other modules at
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// the next clock edge (see tb_neural_processor.v header)
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pre_active = 1'b0; // hand control to layer_prefetch_ctrl.v
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$display("=== EXP-0058: real RTL weight-reuse path -> real neural_processor.v, %0d layers x %0d reuse positions ===", L, M);
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t0 = cyc;
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for (li_i = 0; li_i < L; li_i = li_i + 1) begin
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pf_layer_base = li_i * WORDS_PER_LAYER;
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pf_start = 1'b1; @(posedge clk); #1; pf_start = 1'b0;
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while (!pf_done) @(posedge clk);
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#1;
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// pulse-hardening: hold consume_done past its edge with a real
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// time delay before clearing, rather than clearing on the very
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// next @(posedge clk) -- otherwise the clear can land in the
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// SAME active-region pass as the edge where layer_weight_
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// buffer.v's own always block reads it, and their relative
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// order is implementation-defined, so the pulse can be silently
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// missed (found via direct $strobe tracing while debugging this
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// exact sequence in tb_layer_prefetch_ctrl.v, EXP-0058 -- see
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// that file's own longer note on this).
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consume_done = 1'b1; @(posedge clk); #1; consume_done = 1'b0; // swap into active
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@(posedge clk); #1;
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for (pos_i = 0; pos_i < M; pos_i = pos_i + 1) begin
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run_one_position(li_i, pos_i);
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end
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end
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total_cycles = cyc - t0;
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$display("=== RESULT: %0d/%0d PASS, %0d errors, %0d total cycles for %0d layers x %0d positions (EXP-0058 integration) ===",
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tests-errors, tests, errors, total_cycles, L, M);
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if (errors == 0) $display("ALL TESTS PASSED (tb_neural_processor_layer_reuse)");
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$finish;
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end
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endmodule
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