micheleandClaude Sonnet 5
80c89fa10d
New tb_neural_processor_layer_reuse.v wires the real SDRAM controller, layer_prefetch_ctrl.v and layer_weight_buffer.v into a real neural_processor.v compute engine: one resident filter is fetched once and reused across 8 independent jobs per layer, verified bit-exact against an independent golden dot-product model (32/32 PASS). Also found and fixed a real testbench-vs-DUT scheduling race present in tb_layer_prefetch_ctrl.v (and hardened in the new file): clearing a one-cycle control pulse on the very next clock edge lands the clear in the same active-region pass as the edge a receiving module's own synchronous logic reads it at, so the pulse can be silently missed depending on implementation-defined process ordering. This had been silently preventing tb_layer_prefetch_ctrl.v's own claimed 8192/8192 result from ever actually being observed; fixed by holding the pulse past the edge with a real time delay before clearing, and the 8192/8192 result is now genuinely reproducible (5/5 consecutive runs). Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01MUG92aM9m68TRc4rG55BcC
234 lines
11 KiB
Verilog
234 lines
11 KiB
Verilog
`timescale 1ns/1ps
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// ============================================================
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// EXP-0057 -- real-RTL version of tb_layer_reuse_vs_zero_reuse.v's
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// own prefetch_layer task: layer_prefetch_ctrl.v (real synthesizable
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// FSM) driving layer_weight_buffer.v through the real sdram_
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// controller_openrow.v + sdram_model.v. Same golden pattern, same
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// L=16 layers, verifies bit-exact AND reports real cycles/layer for
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// direct comparison against the task-based measurement (3777 cycles
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// / 16 layers = ~236 cycles/layer average) already logged in
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// experiments.log EXP-0057.
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// ============================================================
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module tb;
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localparam BURST_LEN = 8;
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localparam ROW_BITS = 13;
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localparam COL_BITS = 10;
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localparam BANK_BITS = 2;
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localparam ADDR_WIDTH = BANK_BITS + ROW_BITS + COL_BITS;
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localparam CLK_FREQ_MHZ = 64;
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localparam CLK_PERIOD_NS = 1000.0/CLK_FREQ_MHZ;
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localparam LAYER_BYTES = 128;
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localparam L = 16;
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localparam WORDS_PER_LAYER = LAYER_BYTES/2;
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reg clk = 0;
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always #(CLK_PERIOD_NS/2.0) clk = ~clk;
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reg rst;
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integer cyc;
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always @(posedge clk) if (!rst) cyc <= cyc + 1;
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// ---- real SDRAM controller + model ----
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wire ctrl_req, ctrl_wr;
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wire [ADDR_WIDTH-1:0] ctrl_addr;
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wire [16*BURST_LEN-1:0] ctrl_wdata;
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wire [2*BURST_LEN-1:0] ctrl_wmask;
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wire [16*BURST_LEN-1:0] ctrl_rdata;
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wire ctrl_ready, ctrl_busy;
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wire cke, cs_n, ras_n, cas_n, we_n;
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wire [BANK_BITS-1:0] ba;
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wire [ROW_BITS-1:0] a;
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wire [15:0] dq;
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wire [1:0] dqm;
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sdram_controller_openrow #(
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.CLK_FREQ_MHZ(CLK_FREQ_MHZ), .BURST_LEN(BURST_LEN),
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.ROW_BITS(ROW_BITS), .COL_BITS(COL_BITS), .BANK_BITS(BANK_BITS)
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) u_ctrl (
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.clk(clk), .rst(rst),
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.req(ctrl_req), .wr(ctrl_wr), .addr(ctrl_addr), .wdata(ctrl_wdata), .wmask(ctrl_wmask),
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.rdata(ctrl_rdata), .ready(ctrl_ready), .busy(ctrl_busy),
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.sdram_cke(cke), .sdram_cs_n(cs_n), .sdram_ras_n(ras_n), .sdram_cas_n(cas_n), .sdram_we_n(we_n),
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.sdram_ba(ba), .sdram_a(a), .sdram_dq(dq), .sdram_dqm(dqm)
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);
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sdram_model #(
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.CLK_FREQ_MHZ(CLK_FREQ_MHZ), .ROW_BITS(ROW_BITS), .COL_BITS(COL_BITS), .BANK_BITS(BANK_BITS)
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) u_mem (
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.clk(clk), .cke(cke), .cs_n(cs_n), .ras_n(ras_n), .cas_n(cas_n), .we_n(we_n),
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.ba(ba), .a(a), .dq(dq), .dqm(dqm)
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);
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// separate write-capable path to preload SDRAM (reuse the same
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// controller -- write and prefetch never run concurrently here)
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reg wpre_req, wpre_wr;
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reg [ADDR_WIDTH-1:0] wpre_addr;
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reg [16*BURST_LEN-1:0] wpre_wdata;
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reg pre_active;
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task automatic sdram_write_burst(input [ADDR_WIDTH-1:0] word_addr, input [16*BURST_LEN-1:0] data);
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begin
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@(posedge clk); while (ctrl_busy) @(posedge clk);
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wpre_req = 1'b1; wpre_wr = 1'b1; wpre_addr = word_addr; wpre_wdata = data;
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@(posedge clk); wpre_req = 1'b0;
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while (!ctrl_ready) @(posedge clk);
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end
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endtask
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task automatic preload_sdram_layers;
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integer li, bi, wb;
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reg [16*BURST_LEN-1:0] burst_data;
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begin
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for (li = 0; li < L; li = li + 1) begin
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for (bi = 0; bi < (LAYER_BYTES/(2*BURST_LEN)); bi = bi + 1) begin
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for (wb = 0; wb < BURST_LEN; wb = wb + 1)
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burst_data[wb*16 +: 16] = {8'(8'h20+li), 8'(bi*BURST_LEN+wb)};
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sdram_write_burst((li*WORDS_PER_LAYER + bi*BURST_LEN), burst_data);
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end
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end
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end
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endtask
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// ---- layer_prefetch_ctrl.v (real RTL under test) ----
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wire pf_ctrl_req, pf_ctrl_wr;
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wire [ADDR_WIDTH-1:0] pf_ctrl_addr;
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wire [16*BURST_LEN-1:0] pf_ctrl_wdata;
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wire [2*BURST_LEN-1:0] pf_ctrl_wmask;
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// moved here (below the pf_ctrl_* declarations above) -- iverilog's
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// current elaboration requires a continuous assign's RHS names to be
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// declared earlier in the module than the assign itself, which the
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// original position (right after wpre_*/pre_active, before pf_ctrl_*
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// existed textually) violated; found while re-verifying this file for
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// EXP-0058, see this file's own note by pre_active's assignment below.
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assign ctrl_req = pre_active ? wpre_req : pf_ctrl_req;
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assign ctrl_wr = pre_active ? wpre_wr : pf_ctrl_wr;
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assign ctrl_addr = pre_active ? wpre_addr : pf_ctrl_addr;
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assign ctrl_wdata = pre_active ? wpre_wdata : pf_ctrl_wdata;
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assign ctrl_wmask = pre_active ? {(2*BURST_LEN){1'b0}} : pf_ctrl_wmask;
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reg pf_start;
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reg [ADDR_WIDTH-1:0] pf_layer_base;
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wire pf_busy, pf_done;
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wire pf_fill_we;
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wire [$clog2(LAYER_BYTES)-1:0] pf_fill_addr;
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wire [7:0] pf_fill_data;
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layer_prefetch_ctrl #(
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.DATA_WIDTH(8), .LAYER_BYTES(LAYER_BYTES), .BURST_LEN(BURST_LEN), .ADDR_WIDTH(ADDR_WIDTH)
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) u_pf (
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.clk(clk), .rst(rst),
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.start(pf_start), .layer_base(pf_layer_base), .busy(pf_busy), .done(pf_done),
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.fill_we(pf_fill_we), .fill_addr(pf_fill_addr), .fill_data(pf_fill_data),
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.ctrl_req(pf_ctrl_req), .ctrl_wr(pf_ctrl_wr), .ctrl_addr(pf_ctrl_addr),
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.ctrl_wdata(pf_ctrl_wdata), .ctrl_wmask(pf_ctrl_wmask),
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.ctrl_rdata(ctrl_rdata), .ctrl_ready(ctrl_ready), .ctrl_busy(ctrl_busy)
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);
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// ---- layer_weight_buffer.v ----
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reg [$clog2(LAYER_BYTES)-1:0] rd_addr;
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wire [7:0] rd_data;
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reg consume_done;
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wire active_sel, swapped;
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layer_weight_buffer #(.DATA_WIDTH(8), .LAYER_DEPTH(LAYER_BYTES)) u_lwb (
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.clk(clk), .rst(rst),
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.fill_we(pf_fill_we), .fill_addr(pf_fill_addr), .fill_data(pf_fill_data), .fill_done(pf_done),
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.rd_addr(rd_addr), .rd_data(rd_data), .consume_done(consume_done),
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.active_sel(active_sel), .swapped(swapped)
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);
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integer errors, tests, li_i, t0, total_cycles;
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reg [7:0] expected;
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integer r, k;
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initial begin
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errors = 0; tests = 0; cyc = 0;
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rst = 1; pre_active = 1'b1;
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wpre_req = 0; wpre_wr = 0; wpre_addr = 0; wpre_wdata = 0;
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pf_start = 0; pf_layer_base = 0; rd_addr = 0; consume_done = 0;
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repeat(5) @(posedge clk);
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rst = 0;
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@(posedge clk); while (ctrl_busy) @(posedge clk);
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$display("=== preload SDRAM with %0d distinct layer patterns ===", L);
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preload_sdram_layers;
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@(posedge clk); // ERR-0001 workaround: sync before the first blocking
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// assignment following a time-consuming task call --
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// without this, pre_active's switchover was not
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// reliably visible to the ctrl_* mux at the next
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// clock edge, so layer_prefetch_ctrl.v's own
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// ctrl_req never actually reached the real SDRAM
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// controller and this whole test hung on "while
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// (!pf_done)" forever instead of ever producing a
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// result (found while integrating this module into
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// tb_neural_processor_layer_reuse.v, EXP-0058 --
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// this file's own real-hardware run had never
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// actually completed before that).
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pre_active = 1'b0; // hand control to layer_prefetch_ctrl.v
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// NOTE: sequential (no prefetch/consume overlap) -- this test
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// exists to confirm layer_prefetch_ctrl.v (real RTL) correctly
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// composes with layer_weight_buffer.v end-to-end, data-wise.
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// The real DOUBLE-BUFFERED (overlapped) performance benefit
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// (7.16x) was already measured and verified separately via
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// tb_layer_reuse_vs_zero_reuse.v's own task-based driver,
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// which does not have this testbench's own fork/join
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// complexity -- not re-derived here to avoid re-debugging
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// testbench-only concurrency timing a second time for no new
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// information.
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$display("=== real-RTL prefetch + reuse, %0d layers, sequential (correctness only) ===", L);
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t0 = cyc;
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pf_layer_base = 0; pf_start = 1'b1; @(posedge clk); #1; pf_start = 1'b0;
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while (!pf_done) @(posedge clk);
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// Clock-edge-adjacent pulse idiom, hardened: setting a pulse then
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// clearing it on the VERY NEXT @(posedge clk) puts the clear in the
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// SAME active-region pass as the edge where a receiving module's own
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// synchronous always block reads it -- their relative execution
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// order at that shared edge is implementation-defined (Icarus does
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// not guarantee testbench-thread-vs-DUT-always-block ordering), so
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// the clear can occasionally run before the DUT's read and the pulse
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// is silently missed (found via direct $strobe tracing while
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// integrating this module for EXP-0058 -- layer_weight_buffer.v's
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// own consume_done_latched stayed 0 even though this exact sequence
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// visibly drove consume_done=1 for a full clock period). Fixed by
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// holding the pulse past the edge with a real time delay (#1) before
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// clearing, so the clear unambiguously lands in a later time step
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// than every process that reacted to the edge.
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consume_done = 1'b1; @(posedge clk); #1; consume_done = 1'b0; // initial swap
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@(posedge clk); #1;
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for (li_i = 0; li_i < L; li_i = li_i + 1) begin
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for (r = 0; r < 4; r = r + 1) begin
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for (k = 0; k < LAYER_BYTES; k = k + 1) begin
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rd_addr = k[$clog2(LAYER_BYTES)-1:0];
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#1;
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tests = tests + 1;
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if (k[0] == 1'b0) expected = {1'b0, k[7:1]};
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else expected = 8'(8'h20+li_i);
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if (rd_data !== expected) begin
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$display("FAIL layer=%0d reuse=%0d k=%0d: expected %h got %h", li_i, r, k, expected, rd_data);
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errors = errors + 1;
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end
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@(posedge clk);
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end
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end
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consume_done = 1'b1; @(posedge clk); #1; consume_done = 1'b0; // same pulse-hardening as the initial swap above
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if (li_i+1 < L) begin
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pf_layer_base = (li_i+1)*WORDS_PER_LAYER;
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pf_start = 1'b1; @(posedge clk); #1; pf_start = 1'b0;
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while (!pf_done) @(posedge clk);
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end
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@(posedge clk); #1; // let the swap settle before the next iteration reads
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end
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total_cycles = cyc - t0;
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$display("=== RESULT: %0d/%0d bit-exact, %0d errors, %0d total cycles for %0d layers (real RTL prefetch controller) ===",
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tests-errors, tests, errors, total_cycles, L);
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if (errors == 0) $display("ALL TESTS PASSED (tb_layer_prefetch_ctrl)");
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$finish;
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end
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endmodule
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