micheleandClaude Sonnet 5
8e014d8d49
FASE #1 hardware freeze for FPGA-Neural V2, N4/P8, single external SDRAM (Alliance Memory AS4C4M16SA-6TIN) serving weights, activations, and results through one physical sdram_controller.v instance. Removes the PSRAM dependency (hardware/v1/rtl/psram_controller.v + memory_interface.v) from the V2 physical path entirely -- V1 itself remains fully unmodified, the golden reference. New RTL: sdram_unified_backend.v (2-way W/AR arbitration over one SDRAM controller, real per-byte DQM write masking added to sdram_controller.v for correct single-byte result writes with no read-modify-write), nms_neural_multiprocessor_sdram_unified.v (the frozen top-level). Two real bugs found and fixed via full-system testing before being accepted (ERR-0023): a deadlock and an off-by-one data-shift bug in the new arbitration logic. Real results: N=4 and N=2 D-Stress bit-exact (256/256 neurons), 40 real AUTO REFRESH events interleaved with zero corruption, real Yosys+nextpnr-ecp5 synthesis/P&R for LFE5U-45F-8CABGA381 (149/245 TRELLIS_IO, a real 45-pin reduction from the prior dual-memory design). Timing is MARGINAL (1/8 P&R seeds >=80MHz), reported honestly rather than masked by the best seed. Real, sourced ball-level pinout for the SDRAM bus + clk/rst (39/149 signals, P&R-verified) using the official Lattice ECP5U-45 pinout CSV found on disk during this step's own pre-commit review -- corrects an earlier draft that wrongly assumed no real pinout data was available. Chip readiness: NO. Real, disclosed blockers remain (no physical host interface exists yet -- the RTL's own reg_* ports are a 110-pin raw test-harness bus; clock source/PLL decision; power/configuration component selection) -- see hardware/v2/docs/{HARDWARE_FREEZE, CHIP_READINESS,OPEN_ITEMS}.md for the complete, itemized status. Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
187 lines
8.4 KiB
Plaintext
187 lines
8.4 KiB
Plaintext
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Info: Logic utilisation before packing:
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Info: Total LUT4s: 39/43848 0%
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Info: logic LUTs: 39/43848 0%
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Info: carry LUTs: 0/43848 0%
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Info: RAM LUTs: 0/ 5481 0%
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Info: RAMW LUTs: 0/10962 0%
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Info: Total DFFs: 56/43848 0%
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Info: Packing IOs..
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Info: Packing constants..
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Info: Packing carries...
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Info: Packing LUTs...
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Info: Packing LUT5-7s...
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Info: Packing FFs...
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Info: 10 FFs paired with LUTs.
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Info: Generating derived timing constraints...
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Info: Promoting globals...
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Info: promoting clock net clk$TRELLIS_IO_IN to global network
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Info: Checksum: 0xeb969a4d
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Info: Device utilisation:
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Info: TRELLIS_IO: 18/ 245 7%
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Info: DCCA: 1/ 56 1%
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Info: DP16KD: 2/ 108 1%
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Info: MULT18X18D: 0/ 72 0%
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Info: ALU54B: 0/ 36 0%
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Info: EHXPLLL: 0/ 4 0%
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Info: EXTREFB: 0/ 2 0%
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Info: DCUA: 0/ 2 0%
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Info: PCSCLKDIV: 0/ 2 0%
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Info: IOLOGIC: 0/ 160 0%
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Info: SIOLOGIC: 0/ 85 0%
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Info: GSR: 0/ 1 0%
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Info: JTAGG: 0/ 1 0%
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Info: OSCG: 0/ 1 0%
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Info: SEDGA: 0/ 1 0%
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Info: DTR: 0/ 1 0%
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Info: USRMCLK: 0/ 1 0%
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Info: CLKDIVF: 0/ 4 0%
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Info: ECLKSYNCB: 0/ 10 0%
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Info: DLLDELD: 0/ 8 0%
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Info: DDRDLL: 0/ 4 0%
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Info: DQSBUFM: 0/ 10 0%
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Info: TRELLIS_ECLKBUF: 0/ 8 0%
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Info: ECLKBRIDGECS: 0/ 2 0%
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Info: DCSC: 0/ 2 0%
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Info: TRELLIS_FF: 56/ 43848 0%
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Info: TRELLIS_COMB: 41/ 43848 0%
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Info: TRELLIS_RAMW: 0/ 5481 0%
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Info: Placed 0 cells based on constraints.
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Info: Creating initial analytic placement for 70 cells, random placement wirelen = 6062.
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Info: at initial placer iter 0, wirelen = 1086
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Info: at initial placer iter 1, wirelen = 997
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Info: at initial placer iter 2, wirelen = 981
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Info: at initial placer iter 3, wirelen = 973
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Info: Running main analytical placer, max placement attempts per cell = 10000.
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Info: at iteration #1, type ALL: wirelen solved = 971, spread = 1237, legal = 1557; time = 0.00s
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Info: at iteration #2, type ALL: wirelen solved = 960, spread = 1285, legal = 1710; time = 0.00s
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Info: at iteration #3, type ALL: wirelen solved = 971, spread = 1270, legal = 1845; time = 0.00s
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Info: at iteration #4, type ALL: wirelen solved = 968, spread = 1264, legal = 1744; time = 0.00s
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Info: at iteration #5, type ALL: wirelen solved = 969, spread = 1317, legal = 1636; time = 0.00s
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Info: at iteration #6, type ALL: wirelen solved = 970, spread = 1246, legal = 1595; time = 0.00s
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Info: HeAP Placer Time: 0.03s
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Info: of which solving equations: 0.00s
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Info: of which spreading cells: 0.00s
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Info: of which strict legalisation: 0.00s
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Info: Running simulated annealing placer for refinement.
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Info: at iteration #1: temp = 0.000000, timing cost = 34, wirelen = 1557
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Info: at iteration #5: temp = 0.000000, timing cost = 14, wirelen = 947
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Info: at iteration #10: temp = 0.000000, timing cost = 11, wirelen = 880
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Info: at iteration #15: temp = 0.000000, timing cost = 13, wirelen = 842
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Info: at iteration #19: temp = 0.000000, timing cost = 12, wirelen = 831
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Info: SA placement time 0.02s
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Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 169.69 MHz (PASS at 80.00 MHz)
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Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 5.95 ns
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Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 6.35 ns
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Info: Slack histogram:
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Info: legend: * represents 1 endpoint(s)
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Info: + represents [1,1) endpoint(s)
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Info: [ 6607, 6864) |*******
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Info: [ 6864, 7121) |
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Info: [ 7121, 7378) |
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Info: [ 7378, 7635) |*
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Info: [ 7635, 7892) |
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Info: [ 7892, 8149) |
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Info: [ 8149, 8406) |
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Info: [ 8406, 8663) |
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Info: [ 8663, 8920) |
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Info: [ 8920, 9177) |*
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Info: [ 9177, 9434) |
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Info: [ 9434, 9691) |
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Info: [ 9691, 9948) |
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Info: [ 9948, 10205) |
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Info: [ 10205, 10462) |**
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Info: [ 10462, 10719) |********
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Info: [ 10719, 10976) |**********************
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Info: [ 10976, 11233) |******************
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Info: [ 11233, 11490) |**************************
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Info: [ 11490, 11747) |********************
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Info: Checksum: 0xda48d919
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Info: Routing globals...
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Info: routing clock net $glbnet$clk$TRELLIS_IO_IN using global 0
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Info: Routing..
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Info: Setting up routing queue.
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Info: Routing 278 arcs.
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Info: | (re-)routed arcs | delta | remaining| time spent |
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Info: IterCnt | w/ripup wo/ripup | w/r wo/r | arcs| batch(sec) total(sec)|
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Info: 321 | 40 268 | 40 268 | 0| 0.05 0.05|
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Info: Routing complete.
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Info: Router1 time 0.05s
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Info: Checksum: 0x69cb9087
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Info: Critical path report for clock '$glbnet$clk$TRELLIS_IO_IN' (posedge -> posedge):
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Info: type curr total name
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Info: clk-to-q 4.26 4.26 Source dut.GEN_SLOT[0].GEN_LANE[0].mem.0.0.DOB1
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Info: routing 0.62 4.88 Net dut.GEN_SLOT[0].GEN_LANE[0].mem.0.0_DOB1[2] (8,34) -> (6,33)
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Info: Sink dut.GEN_SLOT[0].GEN_LANE[0].mem.0.0_DOB0_LUT4_D_Z_PFUMX_Z_2_BLUT_LUT4_Z.D
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Info: Defined in:
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Info: /opt/homebrew/bin/../share/yosys/lattice/brams_map_16kd.v:46.13-46.16
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Info: logic 0.31 5.19 Source dut.GEN_SLOT[0].GEN_LANE[0].mem.0.0_DOB0_LUT4_D_Z_PFUMX_Z_2_BLUT_LUT4_Z.OFX
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Info: routing 0.47 5.66 Net dut.GEN_SLOT[0].GEN_LANE[0].mem.0.0_DOB0_LUT4_D_Z[1] (6,33) -> (7,33)
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Info: Sink chk_TRELLIS_FF_Q_1.M
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Info: setup 0.00 5.66 Source chk_TRELLIS_FF_Q_1.M
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Info: 4.57 ns logic, 1.09 ns routing
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Info: Critical path report for cross-domain path '<async>' -> 'posedge $glbnet$clk$TRELLIS_IO_IN':
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Info: type curr total name
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Info: source 0.00 0.00 Source seed[7]$tr_io.O
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Info: routing 3.69 3.69 Net seed[7]$TRELLIS_IO_IN (90,29) -> (8,29)
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Info: Sink seed_LUT4_B_Z_LUT4_Z_5.B
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Info: Defined in:
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Info: hardware/v2/nms/synthesis/harness_nms_weight_packed.v:14.23-14.27
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Info: logic 0.18 3.87 Source seed_LUT4_B_Z_LUT4_Z_5.F
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Info: routing 0.12 3.98 Net seed_LUT4_B_Z[7] (8,29) -> (8,29)
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Info: Sink lfsr_TRELLIS_FF_Q_9.DI
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Info: setup 0.00 3.98 Source lfsr_TRELLIS_FF_Q_9.DI
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Info: 0.18 ns logic, 3.81 ns routing
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Info: Critical path report for cross-domain path 'posedge $glbnet$clk$TRELLIS_IO_IN' -> '<async>':
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Info: type curr total name
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Info: clk-to-q 0.40 0.40 Source chk_TRELLIS_FF_Q_1.Q
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Info: routing 3.80 4.19 Net checksum[1]$TRELLIS_IO_OUT (7,33) -> (90,32)
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Info: Sink checksum[1]$tr_io.I
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Info: Defined in:
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Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
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Info: 0.40 ns logic, 3.80 ns routing
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Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 176.77 MHz (PASS at 80.00 MHz)
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Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 3.98 ns
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Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 4.19 ns
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Info: Slack histogram:
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Info: legend: * represents 1 endpoint(s)
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Info: + represents [1,1) endpoint(s)
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Info: [ 6843, 7091) |******
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Info: [ 7091, 7339) |*
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Info: [ 7339, 7587) |*
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Info: [ 7587, 7835) |
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Info: [ 7835, 8083) |
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Info: [ 8083, 8331) |
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Info: [ 8331, 8579) |
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Info: [ 8579, 8827) |
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Info: [ 8827, 9075) |
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Info: [ 9075, 9323) |
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Info: [ 9323, 9571) |*
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Info: [ 9571, 9819) |
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Info: [ 9819, 10067) |
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Info: [ 10067, 10315) |
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Info: [ 10315, 10563) |*
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Info: [ 10563, 10811) |***********
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Info: [ 10811, 11059) |**********************
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Info: [ 11059, 11307) |*****************************
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Info: [ 11307, 11555) |*************
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Info: [ 11555, 11803) |********************
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Info: Program finished normally.
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