micheleandClaude Sonnet 5
55c827bedf
PSRAM page-mode read burst support in psram_controller.v: enables the ISSI IS66WVE4M16EBLL-70BLI's page mode via its configuration-register software-access sequence at boot (disabled by default on the real chip), then keeps CE#/OE# asserted after a read so a same-page continuation only pays tAPA (20ns) instead of a full tAA (70ns) random access, with automatic tCEM-safe session closing. Only a WRITE closes the page -- byte-enable changes do not, since int8_memory_access.v alternates them on nearly every access and an early implementation attempt that treated them as a close condition measured a real regression (53.25->61.25 cycles/edge) before being corrected (53.25->37.53 cycles/edge, +42% gather bandwidth). sim/psram_model.v gained independent tAPA/tAA and tCEM enforcement (with a real Verilog same-timestep event-ordering race found and fixed via a #0 sync) so the regression proves real timing compliance, not just data correctness. New sim/psram_page_mode_tb.v; full 26-file regression suite re-run clean. Real nextpnr-ecp5 Fmax re-measured on the full spi_neuron_top system: 75.73MHz (P2, up from 55.59MHz) and 65.13MHz (P8) -- still under the 80MHz target but not regressed, with the critical path confirmed (not assumed) to remain entirely inside neuron_parallel's accumulate chain, never psram_controller. Also includes this session's other already-validated work: the graph engine (Type #2 sparse-graph network: act_buffer, graph_engine, netasm host assembler), real CABGA381 pinout (.lpf, place&route verified) and physical IRQ_N/DATA_READY_N pins, and Phase 7 timing closure logs -- all previously uncommitted, documented in WORKLOG.md. Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01LH3jPeJ3eFMfF2v8SQhpkk
427 lines
32 KiB
Plaintext
427 lines
32 KiB
Plaintext
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Info: Logic utilisation before packing:
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Info: Total LUT4s: 3637/43848 8%
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Info: logic LUTs: 2861/43848 6%
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Info: carry LUTs: 776/43848 1%
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Info: RAM LUTs: 0/ 5481 0%
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Info: RAMW LUTs: 0/10962 0%
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Info: Total DFFs: 2401/43848 5%
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Info: Packing IOs..
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Info: $psram_dq[15]$iobuf_i: psram_dq_$_TBUF__Y.Y
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Info: $psram_dq[14]$iobuf_i: psram_dq_$_TBUF__Y_11.Y
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Info: $psram_dq[13]$iobuf_i: psram_dq_$_TBUF__Y_10.Y
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Info: $psram_dq[12]$iobuf_i: psram_dq_$_TBUF__Y_9.Y
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Info: $psram_dq[11]$iobuf_i: psram_dq_$_TBUF__Y_8.Y
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Info: $psram_dq[10]$iobuf_i: psram_dq_$_TBUF__Y_7.Y
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Info: $psram_dq[9]$iobuf_i: psram_dq_$_TBUF__Y_6.Y
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Info: $psram_dq[8]$iobuf_i: psram_dq_$_TBUF__Y_5.Y
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Info: $psram_dq[7]$iobuf_i: psram_dq_$_TBUF__Y_4.Y
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Info: $psram_dq[6]$iobuf_i: psram_dq_$_TBUF__Y_3.Y
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Info: $psram_dq[5]$iobuf_i: psram_dq_$_TBUF__Y_2.Y
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Info: $psram_dq[4]$iobuf_i: psram_dq_$_TBUF__Y_1.Y
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Info: $psram_dq[3]$iobuf_i: psram_dq_$_TBUF__Y_15.Y
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Info: $psram_dq[2]$iobuf_i: psram_dq_$_TBUF__Y_14.Y
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Info: $psram_dq[1]$iobuf_i: psram_dq_$_TBUF__Y_13.Y
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Info: $psram_dq[0]$iobuf_i: psram_dq_$_TBUF__Y_12.Y
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Info: Packing constants..
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Info: Packing carries...
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Info: Packing LUTs...
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Info: Packing LUT5-7s...
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Info: Packing FFs...
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Info: 496 FFs paired with LUTs.
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Info: Generating derived timing constraints...
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Info: Promoting globals...
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Info: promoting clock net clk$TRELLIS_IO_IN to global network
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Info: Checksum: 0xa67103df
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Info: Device utilisation:
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Info: TRELLIS_IO: 51/ 245 20%
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Info: DCCA: 1/ 56 1%
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Info: DP16KD: 2/ 108 1%
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Info: MULT18X18D: 16/ 72 22%
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Info: ALU54B: 0/ 36 0%
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Info: EHXPLLL: 0/ 4 0%
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Info: EXTREFB: 0/ 2 0%
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Info: DCUA: 0/ 2 0%
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Info: PCSCLKDIV: 0/ 2 0%
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Info: IOLOGIC: 0/ 160 0%
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Info: SIOLOGIC: 0/ 85 0%
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Info: GSR: 0/ 1 0%
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Info: JTAGG: 0/ 1 0%
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Info: OSCG: 0/ 1 0%
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Info: SEDGA: 0/ 1 0%
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Info: DTR: 0/ 1 0%
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Info: USRMCLK: 0/ 1 0%
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Info: CLKDIVF: 0/ 4 0%
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Info: ECLKSYNCB: 0/ 10 0%
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Info: DLLDELD: 0/ 8 0%
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Info: DDRDLL: 0/ 4 0%
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Info: DQSBUFM: 0/ 10 0%
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Info: TRELLIS_ECLKBUF: 0/ 8 0%
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Info: ECLKBRIDGECS: 0/ 2 0%
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Info: DCSC: 0/ 2 0%
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Info: TRELLIS_FF: 2401/ 43848 5%
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Info: TRELLIS_COMB: 3815/ 43848 8%
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Info: TRELLIS_RAMW: 0/ 5481 0%
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Info: Placed 0 cells based on constraints.
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Info: Creating initial analytic placement for 4002 cells, random placement wirelen = 320478.
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Info: at initial placer iter 0, wirelen = 6684
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Info: at initial placer iter 1, wirelen = 5839
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Info: at initial placer iter 2, wirelen = 5740
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Info: at initial placer iter 3, wirelen = 5345
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Info: Running main analytical placer, max placement attempts per cell = 4939224.
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Info: at iteration #1, type ALL: wirelen solved = 5423, spread = 50557, legal = 54774; time = 0.06s
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Info: at iteration #2, type ALL: wirelen solved = 7859, spread = 38217, legal = 42646; time = 0.05s
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Info: at iteration #3, type ALL: wirelen solved = 9432, spread = 31167, legal = 34618; time = 0.05s
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Info: at iteration #4, type ALL: wirelen solved = 10771, spread = 30956, legal = 34502; time = 0.05s
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Info: at iteration #5, type ALL: wirelen solved = 12408, spread = 28865, legal = 32848; time = 0.05s
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Info: at iteration #6, type ALL: wirelen solved = 13436, spread = 28030, legal = 31266; time = 0.05s
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Info: at iteration #7, type ALL: wirelen solved = 14224, spread = 27759, legal = 31221; time = 0.05s
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Info: at iteration #8, type ALL: wirelen solved = 14338, spread = 27603, legal = 30592; time = 0.05s
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Info: at iteration #9, type ALL: wirelen solved = 14710, spread = 29237, legal = 31744; time = 0.05s
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Info: at iteration #10, type ALL: wirelen solved = 15516, spread = 34802, legal = 36029; time = 0.04s
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Info: at iteration #11, type ALL: wirelen solved = 19566, spread = 30253, legal = 32991; time = 0.04s
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Info: at iteration #12, type ALL: wirelen solved = 19746, spread = 31936, legal = 36444; time = 0.04s
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Info: at iteration #13, type ALL: wirelen solved = 21187, spread = 30007, legal = 34305; time = 0.04s
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Info: HeAP Placer Time: 0.93s
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Info: of which solving equations: 0.60s
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Info: of which spreading cells: 0.10s
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Info: of which strict legalisation: 0.08s
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Info: Running simulated annealing placer for refinement.
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Info: at iteration #1: temp = 0.000000, timing cost = 1465, wirelen = 30592
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Info: at iteration #5: temp = 0.000000, timing cost = 1447, wirelen = 26679
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Info: at iteration #10: temp = 0.000000, timing cost = 1483, wirelen = 25837
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Info: at iteration #15: temp = 0.000000, timing cost = 1406, wirelen = 25185
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Info: at iteration #20: temp = 0.000000, timing cost = 1401, wirelen = 24938
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Info: at iteration #25: temp = 0.000000, timing cost = 1389, wirelen = 24843
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Info: at iteration #30: temp = 0.000000, timing cost = 1350, wirelen = 24776
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Info: at iteration #35: temp = 0.000000, timing cost = 1347, wirelen = 24745
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Info: at iteration #37: temp = 0.000000, timing cost = 1346, wirelen = 24739
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Info: SA placement time 3.04s
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Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 52.90 MHz (FAIL at 80.00 MHz)
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Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 11.95 ns
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Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 8.32 ns
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Info: Slack histogram:
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Info: legend: * represents 17 endpoint(s)
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Info: + represents [1,17) endpoint(s)
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Info: [ -6404, -5487) |*+
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Info: [ -5487, -4570) |*+
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Info: [ -4570, -3653) |+
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Info: [ -3653, -2736) |+
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Info: [ -2736, -1819) |+
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Info: [ -1819, -902) |+
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Info: [ -902, 15) |+
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Info: [ 15, 932) |+
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Info: [ 932, 1849) |+
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Info: [ 1849, 2766) |+
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Info: [ 2766, 3683) |+
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Info: [ 3683, 4600) |*****+
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Info: [ 4600, 5517) |****************+
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Info: [ 5517, 6434) |****************+
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Info: [ 6434, 7351) |***************************************+
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Info: [ 7351, 8268) |************************************************+
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Info: [ 8268, 9185) |******************************************************+
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Info: [ 9185, 10102) |************************************************************
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Info: [ 10102, 11019) |**************************************************+
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Info: [ 11019, 11936) |******************************+
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Info: Checksum: 0x080818a6
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Info: Routing globals...
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Info: routing clock net $glbnet$clk$TRELLIS_IO_IN using global 0
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Info: Routing..
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Info: Setting up routing queue.
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Info: Routing 19179 arcs.
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Info: | (re-)routed arcs | delta | remaining| time spent |
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Info: IterCnt | w/ripup wo/ripup | w/r wo/r | arcs| batch(sec) total(sec)|
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Info: 1000 | 477 522 | 477 522 | 18764| 0.25 0.25|
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Info: 2000 | 904 1095 | 427 573 | 18275| 0.17 0.42|
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Info: 3000 | 1234 1765 | 330 670 | 17706| 0.30 0.72|
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Info: 4000 | 1465 2534 | 231 769 | 17011| 0.15 0.87|
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Info: 5000 | 1728 3271 | 263 737 | 16396| 0.14 1.01|
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Info: 6000 | 2085 3914 | 357 643 | 15881| 0.15 1.16|
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Info: 7000 | 2388 4611 | 303 697 | 15361| 0.24 1.40|
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Info: 8000 | 2730 5269 | 342 658 | 14792| 0.10 1.50|
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Info: 9000 | 3069 5930 | 339 661 | 14210| 0.11 1.61|
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Info: 10000 | 3506 6493 | 437 563 | 13803| 0.11 1.72|
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Info: 11000 | 3816 7183 | 310 690 | 13202| 0.10 1.82|
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Info: 12000 | 4015 7914 | 199 731 | 12584| 0.12 1.93|
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Info: 13000 | 4383 8449 | 368 535 | 12019| 0.08 2.01|
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Info: 14000 | 4915 8865 | 532 416 | 11647| 0.10 2.11|
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Info: 15000 | 5301 9361 | 386 496 | 11090| 0.08 2.19|
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Info: 16000 | 5764 9846 | 463 485 | 10580| 0.10 2.28|
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Info: 17000 | 6096 10450 | 332 604 | 9966| 0.12 2.40|
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Info: 18000 | 6474 11050 | 378 600 | 9370| 0.11 2.52|
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Info: 19000 | 6786 11733 | 312 683 | 8723| 0.11 2.63|
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Info: 20000 | 6953 12565 | 167 832 | 7927| 0.12 2.75|
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Info: 21000 | 7167 13345 | 214 780 | 7290| 0.16 2.91|
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Info: 22000 | 7328 14152 | 161 807 | 6550| 0.15 3.06|
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Info: 23000 | 7527 14870 | 199 718 | 5848| 0.12 3.18|
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Info: 24000 | 7786 15539 | 259 669 | 5223| 0.23 3.42|
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Info: 25000 | 7958 16245 | 172 706 | 4462| 0.16 3.58|
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Info: 26000 | 8133 16994 | 175 749 | 3693| 0.13 3.71|
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Info: 27000 | 8248 17779 | 115 785 | 2848| 0.13 3.84|
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Info: 28000 | 8393 18553 | 145 774 | 2061| 0.11 3.95|
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Info: 29000 | 8549 19375 | 156 822 | 1263| 0.15 4.10|
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Info: 30000 | 8624 20233 | 75 858 | 359| 0.23 4.33|
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Info: 30418 | 8664 20572 | 40 339 | 0| 0.19 4.53|
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Info: Routing complete.
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Info: Router1 time 4.53s
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Info: Checksum: 0xb1c9123a
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Info: Critical path report for clock '$glbnet$clk$TRELLIS_IO_IN' (posedge -> posedge):
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Info: type curr total name
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Info: clk-to-q 0.40 0.40 Source u_neuron_memory.u_neuron.group_index_TRELLIS_FF_Q.Q
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Info: routing 1.51 1.91 Net u_neuron_memory.u_neuron.finishing_TRELLIS_FF_Q_DI_LUT4_Z_D[1] (6,6) -> (6,24)
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Info: Sink u_neuron_memory.u_neuron.u_mac8.w_bus_PFUMX_Z_39_C0_LUT4_Z.D
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Info: Defined in:
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Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
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Info: logic 0.18 2.09 Source u_neuron_memory.u_neuron.u_mac8.w_bus_PFUMX_Z_39_C0_LUT4_Z.F
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Info: routing 0.55 2.64 Net u_neuron_memory.u_neuron.u_mac8.w_bus_PFUMX_Z_39_C0[4] (6,24) -> (6,23)
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Info: Sink u_neuron_memory.u_neuron.u_mac8.w_bus_PFUMX_Z_39_BLUT_LUT4_Z.M
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Info: Defined in:
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Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
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Info: logic 0.19 2.83 Source u_neuron_memory.u_neuron.u_mac8.w_bus_PFUMX_Z_39_BLUT_LUT4_Z.OFX
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Info: routing 2.06 4.89 Net u_neuron_memory.u_neuron.w_group[40] (6,23) -> (13,46)
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Info: Sink u_neuron_memory.u_neuron.u_mac8.GEN_MAC[5].u_mac.product_MULT18X18D_P9.B0
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Info: Defined in:
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Info: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:93.43-93.50
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Info: logic 3.07 7.95 Source u_neuron_memory.u_neuron.u_mac8.GEN_MAC[5].u_mac.product_MULT18X18D_P9.P2
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Info: routing 2.47 10.43 Net u_neuron_memory.u_neuron.u_mac8.products[5][2] (13,46) -> (4,20)
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Info: Sink u_neuron_memory.u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_S1_CCU2C_S1_S0_CCU2C_S0$CCU2_COMB0.A
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Info: Defined in:
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Info: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:73.9-73.13
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Info: logic 0.35 10.78 Source u_neuron_memory.u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_S1_CCU2C_S1_S0_CCU2C_S0$CCU2_COMB0.FCO
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Info: routing 0.00 10.78 Net u_neuron_memory.u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_S1_CCU2C_S1_S0_CCU2C_S0$CCU2_FCI_INT (4,20) -> (4,20)
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Info: Sink u_neuron_memory.u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_S1_CCU2C_S1_S0_CCU2C_S0$CCU2_COMB1.FCI
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Info: logic 0.00 10.78 Source u_neuron_memory.u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_S1_CCU2C_S1_S0_CCU2C_S0$CCU2_COMB1.FCO
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Info: routing 0.00 10.78 Net u_neuron_memory.u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_S1_CCU2C_S1_S0_CCU2C_S0_COUT (4,20) -> (4,20)
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Info: Sink u_neuron_memory.u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S0_CCU2C_S0_S1_CCU2C_S1$CCU2_COMB0.FCI
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Info: Defined in:
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Info: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44
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Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
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Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
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Info: logic 0.06 10.84 Source u_neuron_memory.u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S0_CCU2C_S0_S1_CCU2C_S1$CCU2_COMB0.FCO
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Info: routing 0.00 10.84 Net u_neuron_memory.u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S0_CCU2C_S0_S1_CCU2C_S1$CCU2_FCI_INT (4,20) -> (4,20)
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Info: Sink u_neuron_memory.u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S0_CCU2C_S0_S1_CCU2C_S1$CCU2_COMB1.FCI
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Info: logic 0.00 10.84 Source u_neuron_memory.u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S0_CCU2C_S0_S1_CCU2C_S1$CCU2_COMB1.FCO
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Info: routing 0.00 10.84 Net u_neuron_memory.u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S0_CCU2C_S0_S1_CCU2C_S1_COUT (4,20) -> (5,20)
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Info: Sink u_neuron_memory.u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S0_CCU2C_S0_S1_CCU2C_S1$CCU2_COMB0.FCI
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Info: Defined in:
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Info: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44
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Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
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Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
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Info: logic 0.06 10.89 Source u_neuron_memory.u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S0_CCU2C_S0_S1_CCU2C_S1$CCU2_COMB0.FCO
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Info: routing 0.00 10.89 Net u_neuron_memory.u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S0_CCU2C_S0_S1_CCU2C_S1$CCU2_FCI_INT (5,20) -> (5,20)
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Info: Sink u_neuron_memory.u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S0_CCU2C_S0_S1_CCU2C_S1$CCU2_COMB1.FCI
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Info: logic 0.00 10.89 Source u_neuron_memory.u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S0_CCU2C_S0_S1_CCU2C_S1$CCU2_COMB1.FCO
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Info: routing 0.00 10.89 Net u_neuron_memory.u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S0_CCU2C_S0_S1_CCU2C_S1_COUT (5,20) -> (5,20)
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Info: Sink u_neuron_memory.u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S0_CCU2C_S0_S1_CCU2C_S1$CCU2_COMB0.FCI
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Info: Defined in:
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Info: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44
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Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
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Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
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Info: logic 0.06 10.95 Source u_neuron_memory.u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S0_CCU2C_S0_S1_CCU2C_S1$CCU2_COMB0.FCO
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Info: routing 0.00 10.95 Net u_neuron_memory.u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S0_CCU2C_S0_S1_CCU2C_S1$CCU2_FCI_INT (5,20) -> (5,20)
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Info: Sink u_neuron_memory.u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S0_CCU2C_S0_S1_CCU2C_S1$CCU2_COMB1.FCI
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Info: logic 0.00 10.95 Source u_neuron_memory.u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S0_CCU2C_S0_S1_CCU2C_S1$CCU2_COMB1.FCO
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Info: routing 0.00 10.95 Net u_neuron_memory.u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S0_CCU2C_S0_S1_CCU2C_S1_COUT (5,20) -> (5,20)
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Info: Sink u_neuron_memory.u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S0_CCU2C_S0_S1_CCU2C_S1$CCU2_COMB0.FCI
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Info: Defined in:
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Info: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44
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Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
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Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
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Info: logic 0.33 11.28 Source u_neuron_memory.u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S0_CCU2C_S0_S1_CCU2C_S1$CCU2_COMB0.F
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Info: routing 0.62 11.90 Net u_neuron_memory.u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S0_CCU2C_S0_S1[2] (5,20) -> (6,18)
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Info: Sink u_neuron_memory.u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S0_LUT4_Z_1.D
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Info: Defined in:
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Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
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Info: logic 0.18 12.08 Source u_neuron_memory.u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S0_LUT4_Z_1.F
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Info: routing 0.58 12.66 Net u_neuron_memory.u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S0[3] (6,18) -> (4,19)
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Info: Sink u_neuron_memory.u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_PFUMX_Z_ALUT_LUT4_Z.A
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Info: Defined in:
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Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
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Info: logic 0.18 12.84 Source u_neuron_memory.u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_PFUMX_Z_ALUT_LUT4_Z.F
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Info: routing 0.00 12.84 Net u_neuron_memory.u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_PFUMX_Z_ALUT (4,19) -> (4,19)
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Info: Sink u_neuron_memory.u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_PFUMX_Z_BLUT_LUT4_Z.F1
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Info: Defined in:
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Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:133.22-133.24
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Info: logic 0.13 12.96 Source u_neuron_memory.u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_PFUMX_Z_BLUT_LUT4_Z.OFX
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Info: routing 0.54 13.50 Net u_neuron_memory.u_neuron.acc_next_CCU2C_S1_A1[2] (4,19) -> (5,18)
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Info: Sink u_neuron_memory.u_neuron.acc_next_CCU2C_S1_A1_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.M
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Info: Defined in:
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Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
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Info: logic 0.19 13.70 Source u_neuron_memory.u_neuron.acc_next_CCU2C_S1_A1_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.OFX
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Info: routing 0.61 14.30 Net u_neuron_memory.u_neuron.acc_next_CCU2C_S1_A1[0] (5,18) -> (4,18)
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Info: Sink u_neuron_memory.u_neuron.acc_next_CCU2C_S1_4_B0_LUT4_Z.B
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Info: Defined in:
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Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
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Info: logic 0.18 14.48 Source u_neuron_memory.u_neuron.acc_next_CCU2C_S1_4_B0_LUT4_Z.F
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Info: routing 0.84 15.33 Net u_neuron_memory.u_neuron.acc_next_CCU2C_S1_4_B0 (4,18) -> (4,16)
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Info: Sink u_neuron_memory.u_neuron.acc_next_CCU2C_S1_4$CCU2_COMB0.B
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Info: logic 0.35 15.68 Source u_neuron_memory.u_neuron.acc_next_CCU2C_S1_4$CCU2_COMB0.FCO
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Info: routing 0.00 15.68 Net u_neuron_memory.u_neuron.acc_next_CCU2C_S1_4$CCU2_FCI_INT (4,16) -> (4,16)
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Info: Sink u_neuron_memory.u_neuron.acc_next_CCU2C_S1_4$CCU2_COMB1.FCI
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Info: logic 0.00 15.68 Source u_neuron_memory.u_neuron.acc_next_CCU2C_S1_4$CCU2_COMB1.FCO
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Info: routing 0.00 15.68 Net u_neuron_memory.u_neuron.acc_next_CCU2C_S1_4_COUT (4,16) -> (5,16)
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Info: Sink u_neuron_memory.u_neuron.acc_next_CCU2C_S1_7$CCU2_COMB0.FCI
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Info: Defined in:
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Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
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Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
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Info: logic 0.06 15.74 Source u_neuron_memory.u_neuron.acc_next_CCU2C_S1_7$CCU2_COMB0.FCO
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Info: routing 0.00 15.74 Net u_neuron_memory.u_neuron.acc_next_CCU2C_S1_7$CCU2_FCI_INT (5,16) -> (5,16)
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Info: Sink u_neuron_memory.u_neuron.acc_next_CCU2C_S1_7$CCU2_COMB1.FCI
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Info: logic 0.00 15.74 Source u_neuron_memory.u_neuron.acc_next_CCU2C_S1_7$CCU2_COMB1.FCO
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Info: routing 0.00 15.74 Net u_neuron_memory.u_neuron.acc_next_CCU2C_S1_7_COUT (5,16) -> (5,16)
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Info: Sink u_neuron_memory.u_neuron.acc_next_CCU2C_S1_5$CCU2_COMB0.FCI
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Info: Defined in:
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Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
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Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
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Info: logic 0.06 15.79 Source u_neuron_memory.u_neuron.acc_next_CCU2C_S1_5$CCU2_COMB0.FCO
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Info: routing 0.00 15.79 Net u_neuron_memory.u_neuron.acc_next_CCU2C_S1_5$CCU2_FCI_INT (5,16) -> (5,16)
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Info: Sink u_neuron_memory.u_neuron.acc_next_CCU2C_S1_5$CCU2_COMB1.FCI
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Info: logic 0.00 15.79 Source u_neuron_memory.u_neuron.acc_next_CCU2C_S1_5$CCU2_COMB1.FCO
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Info: routing 0.00 15.79 Net u_neuron_memory.u_neuron.acc_next_CCU2C_S1_5_COUT (5,16) -> (5,16)
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Info: Sink u_neuron_memory.u_neuron.acc_next_CCU2C_S1_8$CCU2_COMB0.FCI
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Info: Defined in:
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Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
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Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
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Info: logic 0.06 15.85 Source u_neuron_memory.u_neuron.acc_next_CCU2C_S1_8$CCU2_COMB0.FCO
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Info: routing 0.00 15.85 Net u_neuron_memory.u_neuron.acc_next_CCU2C_S1_8$CCU2_FCI_INT (5,16) -> (5,16)
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Info: Sink u_neuron_memory.u_neuron.acc_next_CCU2C_S1_8$CCU2_COMB1.FCI
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Info: logic 0.00 15.85 Source u_neuron_memory.u_neuron.acc_next_CCU2C_S1_8$CCU2_COMB1.FCO
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Info: routing 0.00 15.85 Net u_neuron_memory.u_neuron.acc_next_CCU2C_S1_8_COUT (5,16) -> (5,16)
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Info: Sink u_neuron_memory.u_neuron.acc_next_CCU2C_S1_14$CCU2_COMB0.FCI
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Info: Defined in:
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Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
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Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
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Info: logic 0.06 15.90 Source u_neuron_memory.u_neuron.acc_next_CCU2C_S1_14$CCU2_COMB0.FCO
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Info: routing 0.00 15.90 Net u_neuron_memory.u_neuron.acc_next_CCU2C_S1_14$CCU2_FCI_INT (5,16) -> (5,16)
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Info: Sink u_neuron_memory.u_neuron.acc_next_CCU2C_S1_14$CCU2_COMB1.FCI
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Info: logic 0.00 15.90 Source u_neuron_memory.u_neuron.acc_next_CCU2C_S1_14$CCU2_COMB1.FCO
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Info: routing 0.00 15.90 Net u_neuron_memory.u_neuron.acc_next_CCU2C_S1_14_COUT (5,16) -> (6,16)
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Info: Sink u_neuron_memory.u_neuron.acc_next_CCU2C_S1_9$CCU2_COMB0.FCI
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Info: Defined in:
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Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
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Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
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Info: logic 0.06 15.96 Source u_neuron_memory.u_neuron.acc_next_CCU2C_S1_9$CCU2_COMB0.FCO
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Info: routing 0.00 15.96 Net u_neuron_memory.u_neuron.acc_next_CCU2C_S1_9$CCU2_FCI_INT (6,16) -> (6,16)
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Info: Sink u_neuron_memory.u_neuron.acc_next_CCU2C_S1_9$CCU2_COMB1.FCI
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Info: logic 0.00 15.96 Source u_neuron_memory.u_neuron.acc_next_CCU2C_S1_9$CCU2_COMB1.FCO
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Info: routing 0.00 15.96 Net u_neuron_memory.u_neuron.acc_next_CCU2C_S1_9_COUT (6,16) -> (6,16)
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Info: Sink u_neuron_memory.u_neuron.acc_next_CCU2C_S1_10$CCU2_COMB0.FCI
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Info: Defined in:
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Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
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Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
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Info: logic 0.06 16.02 Source u_neuron_memory.u_neuron.acc_next_CCU2C_S1_10$CCU2_COMB0.FCO
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Info: routing 0.00 16.02 Net u_neuron_memory.u_neuron.acc_next_CCU2C_S1_10$CCU2_FCI_INT (6,16) -> (6,16)
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Info: Sink u_neuron_memory.u_neuron.acc_next_CCU2C_S1_10$CCU2_COMB1.FCI
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Info: logic 0.00 16.02 Source u_neuron_memory.u_neuron.acc_next_CCU2C_S1_10$CCU2_COMB1.FCO
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Info: routing 0.00 16.02 Net u_neuron_memory.u_neuron.acc_next_CCU2C_S1_10_COUT (6,16) -> (6,16)
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Info: Sink u_neuron_memory.u_neuron.acc_next_CCU2C_S1_11$CCU2_COMB0.FCI
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Info: Defined in:
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Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
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Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
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Info: logic 0.06 16.07 Source u_neuron_memory.u_neuron.acc_next_CCU2C_S1_11$CCU2_COMB0.FCO
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Info: routing 0.00 16.07 Net u_neuron_memory.u_neuron.acc_next_CCU2C_S1_11$CCU2_FCI_INT (6,16) -> (6,16)
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Info: Sink u_neuron_memory.u_neuron.acc_next_CCU2C_S1_11$CCU2_COMB1.FCI
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Info: logic 0.00 16.07 Source u_neuron_memory.u_neuron.acc_next_CCU2C_S1_11$CCU2_COMB1.FCO
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Info: routing 0.00 16.07 Net u_neuron_memory.u_neuron.acc_next_CCU2C_S1_11_COUT (6,16) -> (6,16)
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Info: Sink u_neuron_memory.u_neuron.acc_next_CCU2C_S1_13$CCU2_COMB0.FCI
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Info: Defined in:
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Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
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Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
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Info: logic 0.06 16.13 Source u_neuron_memory.u_neuron.acc_next_CCU2C_S1_13$CCU2_COMB0.FCO
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Info: routing 0.00 16.13 Net u_neuron_memory.u_neuron.acc_next_CCU2C_S1_13$CCU2_FCI_INT (6,16) -> (6,16)
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Info: Sink u_neuron_memory.u_neuron.acc_next_CCU2C_S1_13$CCU2_COMB1.FCI
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Info: logic 0.00 16.13 Source u_neuron_memory.u_neuron.acc_next_CCU2C_S1_13$CCU2_COMB1.FCO
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Info: routing 0.00 16.13 Net u_neuron_memory.u_neuron.acc_next_CCU2C_S1_13_COUT (6,16) -> (7,16)
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Info: Sink u_neuron_memory.u_neuron.acc_next_CCU2C_S1_15$CCU2_COMB0.FCI
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Info: Defined in:
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Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
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Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
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Info: logic 0.06 16.18 Source u_neuron_memory.u_neuron.acc_next_CCU2C_S1_15$CCU2_COMB0.FCO
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Info: routing 0.00 16.18 Net u_neuron_memory.u_neuron.acc_next_CCU2C_S1_15$CCU2_FCI_INT (7,16) -> (7,16)
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Info: Sink u_neuron_memory.u_neuron.acc_next_CCU2C_S1_15$CCU2_COMB1.FCI
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Info: logic 0.29 16.48 Source u_neuron_memory.u_neuron.acc_next_CCU2C_S1_15$CCU2_COMB1.F
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Info: routing 0.12 16.60 Net u_neuron_memory.u_neuron.acc_next[31] (7,16) -> (7,16)
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Info: Sink u_neuron_memory.u_neuron.acc_TRELLIS_FF_Q_31.DI
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Info: Defined in:
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Info: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:9.35-9.42
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Info: setup 0.00 16.60 Source u_neuron_memory.u_neuron.acc_TRELLIS_FF_Q_31.DI
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Info: 6.70 ns logic, 9.90 ns routing
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Info: Critical path report for cross-domain path '<async>' -> 'posedge $glbnet$clk$TRELLIS_IO_IN':
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Info: type curr total name
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Info: source 0.00 0.00 Source rst$tr_io.O
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Info: routing 3.76 3.76 Net rst$TRELLIS_IO_IN (90,14) -> (12,12)
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Info: Sink graph_rst_LUT4_Z.C
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Info: Defined in:
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Info: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_slave.v:23.16-23.19
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Info: logic 0.18 3.94 Source graph_rst_LUT4_Z.F
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Info: routing 1.15 5.09 Net graph_rst (12,12) -> (9,8)
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Info: Sink u_neuron_memory.access_req_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_D_Z_LUT4_Z.D
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Info: Defined in:
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Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
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Info: logic 0.18 5.28 Source u_neuron_memory.access_req_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_D_Z_LUT4_Z.F
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Info: routing 1.16 6.44 Net u_neuron_memory.access_req_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_D_Z[0] (9,8) -> (9,25)
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Info: Sink u_neuron_memory.x_mem[21]_TRELLIS_FF_Q_CE_LUT4_Z.D
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Info: Defined in:
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Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
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Info: logic 0.18 6.62 Source u_neuron_memory.x_mem[21]_TRELLIS_FF_Q_CE_LUT4_Z.F
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Info: routing 2.02 8.64 Net u_neuron_memory.x_mem[21]_TRELLIS_FF_Q_CE (9,25) -> (13,45)
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Info: Sink u_neuron_memory.x_mem[21]_TRELLIS_FF_Q_7.CE
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Info: setup 0.00 8.64 Source u_neuron_memory.x_mem[21]_TRELLIS_FF_Q_7.CE
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Info: 0.54 ns logic, 8.10 ns routing
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Info: Critical path report for cross-domain path 'posedge $glbnet$clk$TRELLIS_IO_IN' -> '<async>':
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Info: type curr total name
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Info: clk-to-q 0.40 0.40 Source u_psram_ctrl.dq_oe_TRELLIS_FF_Q.Q
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Info: routing 4.34 4.74 Net u_psram_ctrl.dq_oe (8,30) -> (88,11)
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Info: Sink psram_dq[9]$tr_io$invert_T.A
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Info: Defined in:
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Info: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/psram_controller.v:90.27-90.32
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Info: logic 0.18 4.92 Source psram_dq[9]$tr_io$invert_T.F
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Info: routing 0.69 5.61 Net psram_dq[9]$tr_io$invert_T$conn$Z (88,11) -> (90,11)
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Info: Sink psram_dq[9]$tr_io.T
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Info: 0.57 ns logic, 5.03 ns routing
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ERROR: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 60.26 MHz (FAIL at 80.00 MHz)
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Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 8.64 ns
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Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 5.61 ns
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Info: Slack histogram:
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Info: legend: * represents 18 endpoint(s)
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Info: + represents [1,18) endpoint(s)
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Info: [ -4096, -3301) |*+
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Info: [ -3301, -2506) |*+
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Info: [ -2506, -1711) |+
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Info: [ -1711, -916) |+
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Info: [ -916, -121) |+
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Info: [ -121, 674) |+
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Info: [ 674, 1469) |+
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Info: [ 1469, 2264) |
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Info: [ 2264, 3059) |
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Info: [ 3059, 3854) |
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Info: [ 3854, 4649) |***+
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Info: [ 4649, 5444) |**********+
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Info: [ 5444, 6239) |******************+
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Info: [ 6239, 7034) |*********+
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Info: [ 7034, 7829) |*************************+
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Info: [ 7829, 8624) |***************************************************+
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Info: [ 8624, 9419) |****************************************+
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Info: [ 9419, 10214) |************************************************************
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Info: [ 10214, 11009) |**************************************************+
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Info: [ 11009, 11804) |************************************+
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0 warnings, 1 error
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Info: Program finished normally.
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