micheleandClaude Sonnet 5
2e4cedc761
Implements M5: neural_director.v dispatches job descriptors to whichever of N_SLOTS (memory_manager, neural_processor) pairs is currently free (first-free scheduling per §9's initial policy), with a parametric-depth ready-queue FIFO for jobs arriving faster than slots can absorb them. Scope for this milestone (see decisions.log DEC-0007): a reduced 4-state FSM (DIR_IDLE/SCAN_READY/ALLOCATE/ERROR) rather than §9's full 8-state baseline -- dependency tracking, the waiting queue, and wake-up are §10's explicit responsibility (Dependency Manager, M6, not yet built), and slot-completion detection runs as an always-active per-slot tracker rather than a dedicated FSM state, for the same reason DEC-0002 already gave for the Neural Processor's own FSM (gating concurrent per-unit progress behind one shared state kills throughput). Verified with Verilator (N_SLOTS=2, each slot backed by its own independent behavioral memory rather than sharing V1's real PSRAM -- M4 already proved that path for one slot; this milestone's own concern is scheduling across multiple slots): 4/4 tests pass -- 3 jobs submitted to 2 slots (first two dispatch immediately, third correctly queues until a slot frees), and a deliberate burst that forces the ready queue to genuinely fill and recover. Real synthesis: 0 CHECK problems, 382 LUT4/366 FF/4 CCU2C/0 DSP. Real place&route (via a synthesis-only timing harness, same TRELLIS_IO pin-budget reason as M2/M4): Fmax 250.50 MHz, PASS at 80MHz. Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
46 lines
2.4 KiB
Plaintext
46 lines
2.4 KiB
Plaintext
# V2 synthesis log -- solo append, mai troncato/sovrascritto (vedi README.md)
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# Nessuna entry ancora -- popolato incrementalmente man mano che avanza lo sviluppo V2.
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[2026-09-05] EXP-0001 -- neural_processor (P_IN=8, ACC_WIDTH=32)
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LUT: 55 FF: 533 DSP(MULT18X18D): 8 BRAM: 0 CCU2C: 96
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CHECK: 0 problems. 36 warnings, all "multiple conflicting drivers for
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neural_processor.\gi" -- benign Yosys quirk for an `integer` used as
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a synthesizable for-loop index in stage 0's unrolled always block,
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not a real multi-driver conflict (cross-verified functionally
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correct on 2 independent simulators). Log: hardware/v2/synthesis/
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neural_processor_p8/yosys.log
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[2026-09-05] EXP-0002 -- neural_processor (P_IN=8, ACC_WIDTH=24)
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LUT: 49 FF: 509 DSP(MULT18X18D): 8 BRAM: 0 CCU2C: 88
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CHECK: 0 problems, same 36 benign warnings as EXP-0001.
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Log: hardware/v2/synthesis/neural_processor_p8_acc24/yosys.log
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[2026-09-05] EXP-0003 -- neural_processor_array via
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harness_neural_processor_array.v (synthesis-only wrapper, see
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errors.log ERR-0005), N_PROCESSORS in {1,2,4,8}, P_IN=8
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N=1: LUT=59 FF=409 MULT18X18D=8 CCU2C=96
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N=2: LUT=106 FF=786 MULT18X18D=16 CCU2C=192
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N=4: LUT=207 FF=1540 MULT18X18D=32 CCU2C=384
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N=8: LUT=374 FF=3048 MULT18X18D=64 CCU2C=768
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CHECK: 0 problems in all 4 configurations. Perfectly linear scaling in
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N confirms no unintended cross-processor resource sharing (a first,
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flawed harness attempt fed identical data to every processor/lane
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and Yosys silently deduplicated down to 1x regardless of N -- caught
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by checking for exactly this linearity before trusting the numbers).
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[2026-09-05] EXP-0004 -- activation_buffer/weight_buffer/result_buffer,
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2 depths each
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activation_buffer D=4096: LUT=37 FF=30 DP16KD=2 (D=256: LUT=21 FF=26 DP16KD=1)
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weight_buffer D=512: LUT=88 FF=139 DP16KD=2 (D=64: LUT=73 FF=136 DP16KD=2)
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result_buffer D=4096: LUT=37 FF=30 DP16KD=2 (D=256: LUT=21 FF=26 DP16KD=1)
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CHECK: 0 problems, all 6 configs correctly infer DP16KD (no LUT-RAM
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fallback). weight_buffer's DP16KD count does NOT drop with depth
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(width-bound, not depth-bound -- see decisions.log / benchmark.log).
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[2026-09-05] EXP-0005 -- memory_manager + prefetch_engine (standalone)
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LUT4=851 TRELLIS_FF=789 CCU2C=108 MULT18X18D=0 (expected, no
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multiplication in this module). CHECK: 0 problems.
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[2026-09-05] EXP-0006 -- neural_director (N_SLOTS=4, standalone)
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LUT4=382 TRELLIS_FF=366 CCU2C=4 DSP=0. CHECK: 0 problems.
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