micheleandClaude Sonnet 5
97a21be240
Adds FPGA-exclusive access to the onboard W25Q128JV SPI NOR flash for weights/bias/network persistence, layered as spi_flash_master (raw SPI, USRMCLK-driven) -> flash_copy_engine (flash<->PSRAM streaming, erase- before-write, Page Program loop) -> flash_slot_manager (16-slot catalog with CRC32), exposed via 8 new SPI opcodes (0x40-0x47). Fixes two pre-existing bugs found during bring-up: a psram_controller.v request lost during power-up, and a one-cycle-pulse race in the PSRAM arbiter request handshake. Full simulation + real Yosys/nextpnr-ecp5 synthesis verification (0 errors, Fmax 66.68MHz) in WORKLOG.md and docs/FPGA-Neural-Flash-Subsystem-Verification.md. Also updates docs/pinout to reflect the 56-signal real .lpf (3 new flash pins) and documents the WRITE_RAM/READ_RAM host backpressure risk found while testing this subsystem. Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
11174 lines
236 KiB
Plaintext
11174 lines
236 KiB
Plaintext
.device LFE5U-45F
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.comment Part: LFE5U-45F-8CABGA381
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.tile CIB_R10C32:CIB_EBR
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arc: N3_V06N0203 S3_V06N0103
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.tile CIB_R10C34:CIB_EBR
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arc: N3_V06N0003 S3_V06N0003
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.tile CIB_R10C3:PVT_COUNT2
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unknown: F2B0
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unknown: F3B0
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unknown: F5B0
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unknown: F11B0
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unknown: F13B0
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.tile CIB_R10C47:CIB_EBR
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arc: N3_V06N0103 S3_V06N0103
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.tile CIB_R10C48:CIB_EBR
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arc: N3_V06N0203 S3_V06N0103
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.tile CIB_R13C1:CIB_LR
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arc: N3_V06N0303 JF5
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.tile CIB_R14C1:CIB_LR
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arc: JA3 H02W0701
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enum: CIB.JB3MUX 0
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.tile CIB_R14C89:CIB_LR
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arc: JA3 W1_H02E0701
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arc: W3_H06W0303 JF5
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enum: CIB.JB3MUX 0
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.tile CIB_R16C1:CIB_LR
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arc: JA0 E1_H02W0701
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enum: CIB.JB0MUX 0
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.tile CIB_R16C89:CIB_LR
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arc: W3_H06W0303 S3_V06N0303
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.tile CIB_R17C1:CIB_LR
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arc: E1_H02E0701 S1_V02N0701
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arc: E3_H06E0303 JF5
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arc: JA0 H02W0701
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arc: JA3 E1_H02W0501
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arc: JB0 E1_H01W0100
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arc: S1_V02S0101 E1_H02W0101
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arc: S3_V06S0103 E3_H06W0103
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arc: S3_V06S0303 H06W0303
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enum: CIB.JB3MUX 0
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.tile CIB_R17C89:CIB_LR
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arc: JA3 W1_H02E0701
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arc: S1_V02S0501 W1_H02E0501
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arc: V01S0100 S3_V06N0303
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arc: W3_H06W0303 JF5
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enum: CIB.JB3MUX 0
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.tile CIB_R18C1:CIB_LR
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arc: E3_H06E0103 V01N0101
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.tile CIB_R18C89:CIB_LR
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arc: W3_H06W0103 N1_V01S0100
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.tile CIB_R19C1:CIB_LR
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arc: E3_H06E0003 S3_V06N0003
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arc: E3_H06E0103 V01N0101
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arc: E3_H06E0303 S3_V06N0303
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arc: JA3 E1_H02W0701
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arc: JB3 N1_V02S0101
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arc: N1_V01N0101 JF5
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arc: N1_V02N0701 JQ5
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.tile CIB_R19C89:CIB_LR
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arc: JA3 N1_V02S0501
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arc: V01S0100 S3_V06N0303
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arc: W3_H06W0303 JF5
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enum: CIB.JB3MUX 0
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.tile CIB_R1C13:CIB
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arc: E3_H06E0103 W3_H06E0103
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.tile CIB_R1C19:CIB
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arc: E3_H06E0203 W3_H06E0103
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.tile CIB_R1C1:CIB_LR_S
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arc: E3_H06E0003 S3_V06N0003
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.tile CIB_R1C20:CIB
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arc: JA0 S1_V02N0701
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enum: CIB.JB0MUX 0
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.tile CIB_R1C23:CIB
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arc: JA0 V02N0701
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enum: CIB.JB0MUX 0
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.tile CIB_R1C24:CIB
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arc: JA0 S1_V02N0701
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enum: CIB.JB0MUX 0
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.tile CIB_R1C25:CIB
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arc: E3_H06E0003 JQ0
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arc: E3_H06E0203 W3_H06E0203
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arc: S3_V06S0003 JQ0
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.tile CIB_R1C27:CIB
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arc: E3_H06E0003 JQ0
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arc: S3_V06S0003 JQ0
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.tile CIB_R1C28:CIB
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arc: JA0 V02N0701
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arc: S3_V06S0003 H06E0003
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enum: CIB.JB0MUX 0
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.tile CIB_R1C29:CIB
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arc: E3_H06E0003 JQ0
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.tile CIB_R1C30:CIB
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arc: JA0 H02W0701
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enum: CIB.JB0MUX 0
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.tile CIB_R1C31:CIB
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arc: E3_H06E0103 W3_H06E0003
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arc: E3_H06E0303 W3_H06E0203
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arc: JA0 H02W0701
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arc: S3_V06S0003 W3_H06E0003
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arc: S3_V06S0103 E1_H01W0100
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arc: W1_H02W0701 S3_V06N0203
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enum: CIB.JB0MUX 0
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.tile CIB_R1C32:CIB
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arc: E3_H06E0003 JQ0
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arc: H01W0100 JQ0
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arc: W1_H02W0701 V06N0203
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.tile CIB_R1C33:CIB
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arc: H00L0000 S1_V02N0201
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arc: JA0 H00L0000
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arc: S3_V06S0003 W3_H06E0003
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enum: CIB.JB0MUX 0
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.tile CIB_R1C34:CIB
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arc: H00R0000 V02N0601
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arc: JA0 H00R0000
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arc: S3_V06S0103 H06E0103
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enum: CIB.JB0MUX 0
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.tile CIB_R1C35:CIB
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arc: E3_H06E0003 W3_H06E0003
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.tile CIB_R1C36:CIB
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arc: S3_V06S0003 JQ0
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.tile CIB_R1C37:CIB
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arc: E3_H06E0103 W3_H06E0103
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arc: E3_H06E0303 W3_H06E0303
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arc: JA0 H02W0501
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arc: S3_V06S0103 W3_H06E0103
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arc: S3_V06S0203 E3_H06W0203
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enum: CIB.JB0MUX 0
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.tile CIB_R1C38:CIB
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arc: JA0 H02W0501
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arc: S3_V06S0003 W3_H06E0003
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arc: S3_V06S0203 E3_H06W0203
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arc: W1_H02W0501 S1_V02N0501
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enum: CIB.JB0MUX 0
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.tile CIB_R1C39:CIB
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arc: JA0 S1_V02N0701
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arc: S3_V06S0003 E3_H06W0003
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arc: W1_H02W0501 S1_V02N0501
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enum: CIB.JB0MUX 0
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.tile CIB_R1C40:CIB
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arc: S3_V06S0003 E3_H06W0003
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arc: S3_V06S0103 H06E0103
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arc: S3_V06S0203 H06W0203
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.tile CIB_R1C41:CIB
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arc: S3_V06S0003 W3_H06E0003
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arc: S3_V06S0203 E3_H06W0203
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.tile CIB_R1C42:CIB
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arc: E1_H02E0101 V01N0101
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arc: H00R0100 V02N0701
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arc: JA0 S1_V02N0501
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arc: JB0 H00R0100
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arc: S3_V06S0003 JQ0
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arc: S3_V06S0303 E1_H01W0100
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.tile CIB_R1C43:CIB
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arc: E3_H06E0103 W3_H06E0103
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arc: E3_H06E0303 W3_H06E0303
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arc: H01W0100 JQ0
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arc: JA0 V02N0501
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arc: JB0 H02E0101
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arc: S3_V06S0103 W3_H06E0103
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arc: W3_H06W0203 E3_H06W0103
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.tile CIB_R1C44:CIB
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arc: E1_H02E0701 S3_V06N0203
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arc: JA0 V02N0701
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arc: JB0 V01N0001
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arc: S3_V06S0003 JQ0
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arc: S3_V06S0103 E3_H06W0103
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arc: S3_V06S0203 H06W0203
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arc: W3_H06W0203 E3_H06W0103
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.tile CIB_R1C45:CIB
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arc: JA0 H02E0701
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arc: JB0 V02N0301
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arc: W3_H06W0003 JQ0
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.tile CIB_R1C46:CIB
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arc: E1_H02E0501 S3_V06N0303
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arc: E1_H02E0701 S3_V06N0203
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arc: W3_H06W0003 E3_H06W0003
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.tile CIB_R1C47:CIB
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arc: E1_H02E0401 V06N0203
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arc: JA0 H02E0701
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arc: W3_H06W0203 E3_H06W0103
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enum: CIB.JB0MUX 0
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.tile CIB_R1C48:CIB
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arc: E1_H02E0401 S3_V06N0203
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arc: E1_H02E0701 V06N0203
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arc: JA0 W1_H02E0501
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arc: JD7 E1_H01W0100
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enum: CIB.JB0MUX 0
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.tile CIB_R1C49:CIB
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arc: E1_H02E0501 W1_H02E0401
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arc: E3_H06E0203 W3_H06E0103
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arc: H00R0000 H02E0401
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arc: H01W0100 W3_H06E0303
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arc: JA0 H00R0000
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arc: S3_V06S0103 W3_H06E0103
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arc: W3_H06W0103 E3_H06W0103
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enum: CIB.JB0MUX 0
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.tile CIB_R1C50:CIB
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arc: E1_H02E0701 W1_H02E0701
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arc: JA0 H02E0501
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arc: W3_H06W0103 E3_H06W0003
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enum: CIB.JB0MUX 0
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.tile CIB_R1C51:CIB
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arc: JA0 V02N0501
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enum: CIB.JB0MUX 0
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.tile CIB_R1C52:CIB
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arc: E1_H02E0701 S3_V06N0203
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arc: JA0 W1_H02E0701
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arc: S3_V06S0203 H06E0203
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arc: W3_H06W0003 E3_H06W0003
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enum: CIB.JB0MUX 0
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.tile CIB_R1C53:CIB
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arc: JA0 H02W0501
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arc: W3_H06W0103 E3_H06W0003
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enum: CIB.JB0MUX 0
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.tile CIB_R1C54:CIB
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arc: JA0 W1_H02E0701
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arc: S3_V06S0003 H06W0003
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arc: W1_H02W0501 V06N0303
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enum: CIB.JB0MUX 0
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.tile CIB_R1C55:CIB
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arc: S3_V06S0203 W3_H06E0203
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arc: W3_H06W0103 E3_H06W0003
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.tile CIB_R1C56:CIB
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arc: W3_H06W0003 JQ0
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.tile CIB_R1C57:CIB
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arc: W3_H06W0003 JQ0
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.tile CIB_R1C58:CIB
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arc: W3_H06W0003 JQ0
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.tile CIB_R1C59:CIB
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arc: W3_H06W0003 JQ0
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.tile CIB_R1C60:CIB
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arc: JA0 E1_H02W0501
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enum: CIB.JB0MUX 0
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.tile CIB_R1C61:CIB
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arc: W3_H06W0003 JQ0
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.tile CIB_R1C62:CIB
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arc: W1_H02W0501 S1_V02N0501
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.tile CIB_R1C7:CIB
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arc: E3_H06E0103 W3_H06E0003
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.tile CIB_R20C1:CIB_LR
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arc: E3_H06E0303 S3_V06N0303
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arc: JA0 E1_H02W0501
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arc: JA3 E1_H02W0701
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arc: JB0 E1_H01W0100
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arc: N1_V01N0101 JF5
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arc: S1_V02S0501 H06W0303
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enum: CIB.JB3MUX 0
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.tile CIB_R20C89:CIB_LR
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arc: JA3 W1_H02E0701
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arc: S1_V02S0301 H01E0101
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arc: S1_V02S0701 H06E0203
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arc: S3_V06S0203 W3_H06E0203
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arc: V01S0100 S3_V06N0303
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arc: W3_H06W0103 N1_V01S0100
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arc: W3_H06W0203 S3_V06N0203
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arc: W3_H06W0303 JF5
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enum: CIB.JB3MUX 0
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.tile CIB_R21C1:CIB_LR
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arc: E1_H02E0701 S1_V02N0701
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arc: E3_H06E0303 S3_V06N0303
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arc: S1_V02S0501 E3_H06W0303
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arc: S1_V02S0701 H06W0203
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arc: S3_V06S0203 E3_H06W0203
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.tile CIB_R21C89:CIB_LR
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arc: H01W0000 W3_H06E0103
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arc: S3_V06S0103 W3_H06E0103
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arc: W3_H06W0003 V01N0001
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arc: W3_H06W0303 N1_V01S0100
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.tile CIB_R22C1:CIB_LR_S
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arc: JA0 N1_V02S0501
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arc: JA3 V02S0701
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enum: CIB.JB0MUX 0
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enum: CIB.JB3MUX 0
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.tile CIB_R22C27:CIB_DSP
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arc: N3_V06N0003 S3_V06N0303
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.tile CIB_R22C31:CIB_DSP
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arc: N1_V02N0101 S3_V06N0103
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arc: N1_V02N0701 H02W0701
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.tile CIB_R22C32:CIB_DSP
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arc: E1_H02E0501 S3_V06N0303
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arc: E3_H06E0303 S3_V06N0303
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arc: N1_V02N0201 S3_V06N0103
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arc: N1_V02N0501 S3_V06N0303
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arc: N1_V02N0701 S3_V06N0203
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arc: W1_H02W0701 S3_V06N0203
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.tile CIB_R22C33:CIB_DSP
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arc: N1_V02N0401 S3_V06N0203
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arc: N1_V02N0501 H02E0501
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arc: N1_V02N0701 S3_V06N0203
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.tile CIB_R22C34:CIB_DSP
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arc: E1_H02E0001 V06N0003
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arc: E1_H02E0301 S3_V06N0003
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arc: E3_H06E0003 S3_V06N0003
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arc: N1_V02N0301 S3_V06N0003
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arc: N1_V02N0501 W1_H02E0501
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arc: N1_V02N0601 S3_V06N0303
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arc: N3_V06N0003 S3_V06N0303
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.tile CIB_R22C35:CIB_DSP
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arc: E1_H01E0101 E3_H06W0203
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arc: N1_V02N0001 H02E0001
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arc: N1_V02N0101 S3_V06N0103
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arc: N1_V02N0201 S3_V06N0103
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arc: N1_V02N0301 H02E0301
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arc: N3_V06N0203 S3_V06N0103
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.tile CIB_R22C36:CIB_DSP
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arc: N1_V02N0101 H01E0101
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arc: N1_V02N0201 H02W0201
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.tile CIB_R22C37:CIB_DSP
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arc: E1_H02E0501 V06N0303
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arc: W1_H02W0201 V06S0103
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.tile CIB_R22C38:CIB_DSP
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arc: E1_H02E0501 W3_H06E0303
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arc: E1_H02E0601 W3_H06E0303
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arc: N1_V02N0001 H06W0003
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arc: N1_V02N0301 H06W0003
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arc: N1_V02N0501 H02E0501
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arc: N3_V06N0203 H06W0203
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arc: S1_V02S0401 N1_V02S0401
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arc: S1_V02S0701 N1_V02S0601
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.tile CIB_R22C39:CIB_DSP
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arc: N1_V02N0501 H02E0501
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arc: S1_V02S0701 H02W0701
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.tile CIB_R22C40:CIB_DSP
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arc: N1_V02N0101 N1_V01S0100
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arc: N1_V02N0301 W3_H06E0003
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arc: N1_V02N0501 H02W0501
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arc: N1_V02N0601 W1_H02E0601
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arc: N1_V02N0701 S3_V06N0203
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arc: N3_V06N0003 E3_H06W0003
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arc: S1_V02S0301 H02W0301
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arc: S1_V02S0501 H02W0501
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arc: W1_H02W0701 V02S0701
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.tile CIB_R22C41:CIB_DSP
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arc: E1_H02E0301 S3_V06N0003
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arc: N1_V01N0001 S3_V06N0003
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arc: N1_V02N0001 S3_V06N0003
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arc: N1_V02N0401 S3_V06N0203
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arc: N1_V02N0701 S3_V06N0203
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arc: N3_V06N0003 S3_V06N0003
|
|
arc: N3_V06N0103 S3_V06N0003
|
|
arc: W1_H02W0301 S3_V06N0003
|
|
arc: W1_H02W0501 V06S0303
|
|
arc: W3_H06W0003 S3_V06N0003
|
|
arc: W3_H06W0203 E3_H06W0203
|
|
|
|
.tile CIB_R22C42:CIB_DSP
|
|
arc: N1_V02N0301 H02E0301
|
|
|
|
.tile CIB_R22C43:CIB_DSP
|
|
arc: N1_V02N0001 H06W0003
|
|
arc: N1_V02N0301 W1_H02E0301
|
|
|
|
.tile CIB_R22C46:CIB_DSP
|
|
arc: W3_H06W0003 E1_H01W0000
|
|
|
|
.tile CIB_R22C47:CIB_DSP
|
|
arc: H01W0000 E3_H06W0103
|
|
arc: N1_V02N0301 S3_V06N0003
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
|
|
.tile CIB_R22C53:CIB_DSP
|
|
arc: N1_V02N0501 S3_V06N0303
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
|
|
.tile CIB_R22C59:CIB_DSP
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
|
|
.tile CIB_R22C65:CIB_DSP
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
|
|
.tile CIB_R22C71:CIB_DSP
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
|
|
.tile CIB_R22C77:CIB_DSP
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
|
|
.tile CIB_R22C83:CIB_DSP
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
|
|
.tile CIB_R22C89:CIB_LR_S
|
|
arc: JA3 N1_V02S0701
|
|
arc: JB3 N1_V02S0301
|
|
arc: N1_V01N0001 JF5
|
|
arc: N3_V06N0303 JQ5
|
|
arc: W3_H06W0303 S3_V06N0303
|
|
|
|
.tile CIB_R23C1:CIB_LR
|
|
arc: E3_H06E0303 S3_V06N0303
|
|
arc: JA0 N1_V02S0501
|
|
arc: N1_V02N0701 JQ5
|
|
arc: S1_V02S0501 H06W0303
|
|
arc: S3_V06S0203 N3_V06S0103
|
|
arc: S3_V06S0303 N3_V06S0303
|
|
enum: CIB.JB0MUX 0
|
|
|
|
.tile CIB_R23C89:CIB_LR
|
|
arc: H01W0100 JQ5
|
|
arc: N3_V06N0303 JQ5
|
|
arc: S1_V02S0301 H01E0101
|
|
arc: W3_H06W0303 JF5
|
|
|
|
.tile CIB_R24C89:CIB_LR
|
|
arc: S3_V06S0203 W3_H06E0203
|
|
arc: W1_H02W0201 V06S0103
|
|
|
|
.tile CIB_R25C1:CIB_LR
|
|
arc: JA3 N1_V02S0501
|
|
arc: N3_V06N0003 S3_V06N0303
|
|
arc: N3_V06N0303 JF5
|
|
enum: CIB.JB3MUX 0
|
|
|
|
.tile CIB_R25C89:CIB_LR
|
|
arc: JA3 V02N0701
|
|
arc: JB3 N1_V02S0301
|
|
arc: N3_V06N0303 JF5
|
|
arc: S1_V02S0501 W3_H06E0303
|
|
arc: W3_H06W0303 JQ5
|
|
|
|
.tile CIB_R26C1:CIB_LR
|
|
arc: E3_H06E0303 S3_V06N0303
|
|
arc: JA0 H02W0501
|
|
arc: N3_V06N0303 JQ5
|
|
arc: S1_V02S0101 E1_H01W0100
|
|
enum: CIB.JB0MUX 0
|
|
|
|
.tile CIB_R26C89:CIB_LR
|
|
arc: N1_V02N0701 N3_V06S0203
|
|
arc: N3_V06N0203 S1_V02N0701
|
|
arc: N3_V06N0303 JQ5
|
|
arc: W3_H06W0303 JF5
|
|
|
|
.tile CIB_R27C1:CIB_LR
|
|
arc: E3_H06E0303 V01N0101
|
|
arc: N3_V06N0303 S1_V02N0501
|
|
arc: S1_V02S0701 N3_V06S0203
|
|
|
|
.tile CIB_R27C89:CIB_LR
|
|
arc: S1_V02S0201 N3_V06S0103
|
|
arc: S1_V02S0501 N1_V02S0501
|
|
arc: S1_V02S0701 H02E0701
|
|
|
|
.tile CIB_R28C1:CIB_LR
|
|
arc: E3_H06E0303 S3_V06N0303
|
|
arc: JA0 V02S0701
|
|
arc: JA3 V02N0701
|
|
arc: JB0 N1_V02S0101
|
|
arc: N1_V01N0101 JF5
|
|
enum: CIB.JB3MUX 0
|
|
|
|
.tile CIB_R28C89:CIB_LR
|
|
arc: N1_V02N0701 JQ5
|
|
arc: N3_V06N0303 JF5
|
|
arc: W3_H06W0303 S3_V06N0303
|
|
|
|
.tile CIB_R29C1:CIB_LR
|
|
arc: E3_H06E0303 S3_V06N0303
|
|
arc: H00R0100 E1_H02W0701
|
|
arc: JA0 H02W0501
|
|
arc: JB0 H00R0100
|
|
arc: N1_V02N0501 JF5
|
|
arc: N1_V02N0701 N3_V06S0203
|
|
arc: N3_V06N0303 JQ5
|
|
arc: S1_V02S0301 E1_H01W0100
|
|
arc: S1_V02S0501 N3_V06S0303
|
|
arc: S1_V02S0701 H06W0203
|
|
|
|
.tile CIB_R29C89:CIB_LR
|
|
arc: H00R0100 H02E0501
|
|
arc: JA0 N1_V02S0701
|
|
arc: JA3 N1_V02S0501
|
|
arc: JB0 H02E0301
|
|
arc: JB3 H00R0100
|
|
arc: S1_V02S0301 H01E0101
|
|
arc: W1_H02W0201 N1_V02S0201
|
|
arc: W1_H02W0501 JF5
|
|
arc: W3_H06W0303 JQ5
|
|
|
|
.tile CIB_R30C89:CIB_LR
|
|
arc: S1_V02S0701 N3_V06S0203
|
|
|
|
.tile CIB_R31C1:CIB_LR
|
|
arc: E3_H06E0303 JQ5
|
|
arc: JA0 N1_V02S0701
|
|
arc: JB0 N1_V02S0301
|
|
arc: N3_V06N0303 JF5
|
|
arc: S1_V02S0501 N1_V02S0501
|
|
|
|
.tile CIB_R31C89:CIB_LR
|
|
arc: JA0 V02S0701
|
|
arc: JA3 H02E0701
|
|
arc: JB3 N1_V02S0301
|
|
arc: S1_V02S0401 W1_H02E0401
|
|
arc: W3_H06W0303 JQ5
|
|
enum: CIB.JB0MUX 0
|
|
|
|
.tile CIB_R32C1:CIB_LR
|
|
arc: H00L0100 H02W0301
|
|
arc: JA3 H00L0100
|
|
arc: N3_V06N0303 JF5
|
|
enum: CIB.JB3MUX 0
|
|
|
|
.tile CIB_R32C89:CIB_LR
|
|
arc: JA3 H02E0501
|
|
arc: W3_H06W0303 JF5
|
|
enum: CIB.JB3MUX 0
|
|
|
|
.tile CIB_R33C1:CIB_LR
|
|
arc: S1_V02S0501 N1_V02S0501
|
|
|
|
.tile CIB_R33C89:CIB_LR
|
|
arc: S1_V02S0501 N1_V02S0401
|
|
|
|
.tile CIB_R34C12:CIB_EBR
|
|
arc: S3_V06S0103 N3_V06S0003
|
|
|
|
.tile CIB_R34C13:CIB_EBR
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
|
|
.tile CIB_R34C19:CIB_EBR
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
|
|
.tile CIB_R34C1:CIB_LR_S
|
|
arc: E3_H06E0303 JQ5
|
|
arc: N3_V06N0303 JF5
|
|
|
|
.tile CIB_R34C25:CIB_EBR
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
|
|
.tile CIB_R34C27:CIB_EBR
|
|
arc: N3_V06N0303 S3_V06N0303
|
|
|
|
.tile CIB_R34C31:CIB_EBR
|
|
arc: N3_V06N0003 W3_H06E0003
|
|
|
|
.tile CIB_R34C32:CIB_EBR
|
|
arc: N3_V06N0103 H06W0103
|
|
arc: N3_V06N0203 S3_V06N0103
|
|
|
|
.tile CIB_R34C33:CIB_EBR
|
|
arc: N3_V06N0103 S3_V06N0103
|
|
|
|
.tile CIB_R34C34:CIB_EBR
|
|
arc: N3_V06N0003 S3_V06N0303
|
|
arc: N3_V06N0103 S3_V06N0003
|
|
arc: N3_V06N0203 S3_V06N0103
|
|
|
|
.tile CIB_R34C35:CIB_EBR
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
|
|
.tile CIB_R34C37:CIB_EBR
|
|
arc: N3_V06N0003 S3_V06N0003
|
|
|
|
.tile CIB_R34C40:CIB_EBR
|
|
arc: N3_V06N0103 S3_V06N0103
|
|
|
|
.tile CIB_R34C41:CIB_EBR
|
|
arc: N3_V06N0203 S3_V06N0203
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
|
|
.tile CIB_R34C47:CIB_EBR
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
|
|
.tile CIB_R34C53:CIB_EBR
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
|
|
.tile CIB_R34C59:CIB_EBR
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
|
|
.tile CIB_R34C65:CIB_EBR
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
|
|
.tile CIB_R34C71:CIB_EBR
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
|
|
.tile CIB_R34C77:CIB_EBR
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
|
|
.tile CIB_R34C7:CIB_EBR
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
|
|
.tile CIB_R34C83:CIB_EBR
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
|
|
.tile CIB_R34C87:CIB_EBR
|
|
arc: E1_H02E0701 V06S0203
|
|
|
|
.tile CIB_R34C89:CIB_LR_S
|
|
arc: N3_V06N0303 JF5
|
|
arc: S1_V02S0701 W1_H02E0701
|
|
arc: W3_H06W0303 JQ5
|
|
|
|
.tile CIB_R35C1:CIB_LR
|
|
arc: JA3 N1_V02S0501
|
|
arc: N3_V06N0303 JF5
|
|
arc: S1_V02S0701 H02W0701
|
|
enum: CIB.JB3MUX 0
|
|
|
|
.tile CIB_R35C89:CIB_LR
|
|
arc: JA0 V02S0701
|
|
arc: JA3 N1_V02S0501
|
|
arc: S1_V02S0701 W1_H02E0701
|
|
enum: CIB.JB0MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
|
|
.tile CIB_R37C1:CIB_LR
|
|
arc: E3_H06E0303 JQ5
|
|
arc: JA0 N1_V02S0701
|
|
enum: CIB.JB0MUX 0
|
|
|
|
.tile CIB_R37C89:CIB_LR
|
|
arc: JA0 N1_V02S0701
|
|
arc: W3_H06W0303 JQ5
|
|
enum: CIB.JB0MUX 0
|
|
|
|
.tile CIB_R38C89:CIB_LR
|
|
arc: JA0 H02E0501
|
|
enum: CIB.JB0MUX 0
|
|
|
|
.tile CIB_R40C1:CIB_LR
|
|
arc: E3_H06E0303 JQ5
|
|
|
|
.tile CIB_R40C89:CIB_LR
|
|
arc: W3_H06W0303 JQ5
|
|
|
|
.tile CIB_R46C12:CIB_DSP
|
|
arc: S3_V06S0203 N3_V06S0203
|
|
|
|
.tile CIB_R46C27:CIB_DSP
|
|
arc: N3_V06N0203 S3_V06N0203
|
|
|
|
.tile CIB_R46C32:CIB_DSP
|
|
arc: N3_V06N0003 S3_V06N0303
|
|
|
|
.tile CIB_R46C33:CIB_DSP
|
|
arc: N3_V06N0103 S3_V06N0003
|
|
|
|
.tile CIB_R46C34:CIB_DSP
|
|
arc: N3_V06N0003 S3_V06N0303
|
|
arc: N3_V06N0303 S3_V06N0203
|
|
|
|
.tile CIB_R46C37:CIB_DSP
|
|
arc: N3_V06N0303 S3_V06N0203
|
|
|
|
.tile CIB_R46C40:CIB_DSP
|
|
arc: N3_V06N0003 S3_V06N0003
|
|
|
|
.tile CIB_R58C12:CIB_EBR
|
|
arc: S3_V06S0003 N3_V06S0303
|
|
|
|
.tile CIB_R58C27:CIB_EBR
|
|
arc: N3_V06N0103 S3_V06N0003
|
|
|
|
.tile CIB_R58C32:CIB_EBR
|
|
arc: N3_V06N0303 S3_V06N0203
|
|
|
|
.tile CIB_R58C33:CIB_EBR
|
|
arc: N3_V06N0303 S3_V06N0303
|
|
|
|
.tile CIB_R58C34:CIB_EBR
|
|
arc: N3_V06N0103 S3_V06N0003
|
|
arc: N3_V06N0203 S3_V06N0103
|
|
|
|
.tile CIB_R58C37:CIB_EBR
|
|
arc: N3_V06N0203 S3_V06N0203
|
|
|
|
.tile CIB_R58C40:CIB_EBR
|
|
arc: N3_V06N0003 S3_V06N0003
|
|
|
|
.tile CIB_R5C1:CIB_PLL1
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
|
|
.tile CIB_R5C89:CIB_PLL1
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
|
|
.tile CIB_R70C10:CIB
|
|
arc: E3_H06E0003 JQ0
|
|
arc: W1_H02W0701 V06S0203
|
|
|
|
.tile CIB_R70C11:CIB
|
|
arc: H00L0100 H02W0101
|
|
arc: JA0 H00L0100
|
|
enum: CIB.JB0MUX 0
|
|
|
|
.tile CIB_R70C12:CIB
|
|
arc: E3_H06E0003 JQ0
|
|
arc: W1_H02W0101 N3_V06S0103
|
|
|
|
.tile CIB_R70C13:CIB
|
|
arc: E3_H06E0003 JQ0
|
|
|
|
.tile CIB_R70C14:CIB
|
|
arc: E3_H06E0003 JQ0
|
|
|
|
.tile CIB_R70C15:CIB
|
|
arc: JA0 N1_V02S0501
|
|
enum: CIB.JB0MUX 0
|
|
|
|
.tile CIB_R70C16:CIB
|
|
arc: E3_H06E0003 JQ0
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
|
|
.tile CIB_R70C18:CIB
|
|
arc: E3_H06E0003 JQ0
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: JA0 V02S0501
|
|
arc: JB0 V00B0000
|
|
arc: V00B0000 V02S0201
|
|
|
|
.tile CIB_R70C19:CIB
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
|
|
.tile CIB_R70C20:CIB
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
|
|
.tile CIB_R70C22:CIB
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
|
|
.tile CIB_R70C24:CIB
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
|
|
.tile CIB_R70C25:CIB
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
|
|
.tile CIB_R70C26:CIB
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
|
|
.tile CIB_R70C27:CIB
|
|
arc: N3_V06N0003 H06E0003
|
|
|
|
.tile CIB_R70C28:CIB
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
|
|
.tile CIB_R70C30:CIB
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
|
|
.tile CIB_R70C31:CIB
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
|
|
.tile CIB_R70C32:CIB
|
|
arc: N3_V06N0103 W3_H06E0103
|
|
|
|
.tile CIB_R70C33:CIB
|
|
arc: N3_V06N0203 H06E0203
|
|
|
|
.tile CIB_R70C34:CIB
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: N3_V06N0003 W3_H06E0003
|
|
arc: N3_V06N0103 W3_H06E0103
|
|
|
|
.tile CIB_R70C37:CIB
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: N3_V06N0203 H06E0203
|
|
|
|
.tile CIB_R70C3:CIB_PLL3
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
|
|
.tile CIB_R70C40:CIB
|
|
arc: N3_V06N0003 H06E0003
|
|
|
|
.tile CIB_R70C42:VCIB_DCU0
|
|
enum: CIB.JA1MUX 0
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JC2MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
enum: CIB.JC6MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C43:VCIB_DCUA
|
|
enum: CIB.JA1MUX 0
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JC2MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
enum: CIB.JC6MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C44:VCIB_DCUB
|
|
enum: CIB.JA1MUX 0
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JC2MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
enum: CIB.JC6MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C45:VCIB_DCUC
|
|
enum: CIB.JA1MUX 0
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JC2MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
enum: CIB.JC6MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C46:VCIB_DCUD
|
|
enum: CIB.JA1MUX 0
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JC2MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
enum: CIB.JC6MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C47:VCIB_DCUF
|
|
enum: CIB.JA1MUX 0
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JC2MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
enum: CIB.JC6MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C48:VCIB_DCU3
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
enum: CIB.JC6MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C49:VCIB_DCU2
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C50:VCIB_DCUG
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C51:VCIB_DCUH
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C52:VCIB_DCUI
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C53:VCIB_DCU1
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
|
|
.tile CIB_R70C69:VCIB_DCU0
|
|
enum: CIB.JA1MUX 0
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JC2MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
enum: CIB.JC6MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C6:CIB_EFB0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JC6MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C70:VCIB_DCUA
|
|
enum: CIB.JA1MUX 0
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JC2MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
enum: CIB.JC6MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C71:VCIB_DCUB
|
|
enum: CIB.JA1MUX 0
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JC2MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
enum: CIB.JC6MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C72:VCIB_DCUC
|
|
enum: CIB.JA1MUX 0
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JC2MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
enum: CIB.JC6MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C73:VCIB_DCUD
|
|
enum: CIB.JA1MUX 0
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JC2MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
enum: CIB.JC6MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C74:VCIB_DCUF
|
|
enum: CIB.JA1MUX 0
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JC2MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
enum: CIB.JC6MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C75:VCIB_DCU3
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
enum: CIB.JC6MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C76:VCIB_DCU2
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C77:VCIB_DCUG
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C78:VCIB_DCUH
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C79:VCIB_DCUI
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C7:CIB_EFB1
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JA4MUX 0
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JA6MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB4MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB6MUX 0
|
|
enum: CIB.JC3MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
enum: CIB.JC5MUX 0
|
|
enum: CIB.JD3MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD5MUX 0
|
|
|
|
.tile CIB_R70C80:VCIB_DCU1
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
|
|
.tile CIB_R70C87:CIB_PLL3
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
|
|
.tile CIB_R70C9:CIB
|
|
arc: JA0 H02W0701
|
|
enum: CIB.JB0MUX 0
|
|
|
|
.tile CIB_R7C1:CIB_LR
|
|
arc: N3_V06N0003 S3_V06N0303
|
|
|
|
.tile MIB_R0C20:PIOT0
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R0C23:PIOT1
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R0C24:PIOT0
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R0C25:PIOT1
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOB.HYSTERESIS ON
|
|
|
|
.tile MIB_R0C27:PIOT0
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOA.HYSTERESIS ON
|
|
|
|
.tile MIB_R0C28:PIOT1
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R0C29:PIOT0
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOA.HYSTERESIS ON
|
|
|
|
.tile MIB_R0C30:PIOT1
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R0C31:PIOT0
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R0C32:PIOT1
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOB.HYSTERESIS ON
|
|
|
|
.tile MIB_R0C33:PIOT0
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R0C34:PIOT1
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R0C36:PIOT0
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOA.HYSTERESIS ON
|
|
|
|
.tile MIB_R0C37:PIOT1
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R0C38:PIOT0
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R0C39:PIOT1
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R0C3:BANKREF0
|
|
enum: BANK.VCCIO 3V3
|
|
|
|
.tile MIB_R0C40:TMID_0
|
|
arc: G_TDCC0CLKI G_JTRQPCLKCIB1
|
|
|
|
.tile MIB_R0C42:PIOT0
|
|
enum: PIOA.BASE_TYPE BIDIR_LVCMOS33
|
|
enum: PIOA.HYSTERESIS ON
|
|
|
|
.tile MIB_R0C43:PIOT1
|
|
enum: PIOB.BASE_TYPE BIDIR_LVCMOS33
|
|
enum: PIOB.HYSTERESIS ON
|
|
|
|
.tile MIB_R0C44:PIOT0
|
|
enum: PIOA.BASE_TYPE BIDIR_LVCMOS33
|
|
enum: PIOA.HYSTERESIS ON
|
|
|
|
.tile MIB_R0C45:PIOT1
|
|
enum: PIOB.BASE_TYPE BIDIR_LVCMOS33
|
|
enum: PIOB.HYSTERESIS ON
|
|
|
|
.tile MIB_R0C47:PIOT0
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R0C48:PIOT1
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R0C49:PIOT0
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R0C50:PIOT1
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R0C51:PIOT0
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R0C52:PIOT1
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R0C53:PIOT0
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R0C54:PIOT1
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R0C56:PIOT0
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOA.HYSTERESIS ON
|
|
|
|
.tile MIB_R0C57:PIOT1
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOB.HYSTERESIS ON
|
|
|
|
.tile MIB_R0C58:PIOT0
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOA.HYSTERESIS ON
|
|
|
|
.tile MIB_R0C59:PIOT1
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOB.HYSTERESIS ON
|
|
|
|
.tile MIB_R0C60:PIOT0
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R0C61:PIOT1
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOB.HYSTERESIS ON
|
|
|
|
.tile MIB_R0C87:BANKREF1
|
|
enum: BANK.VCCIO 3V3
|
|
|
|
.tile MIB_R10C0:BANKREF7
|
|
enum: BANK.VCCIO 3V3
|
|
|
|
.tile MIB_R10C30:EBR_SPINE_UL0
|
|
arc: G_VPTX0000 G_HPRX0000
|
|
|
|
.tile MIB_R10C40:CMUX_UL_0
|
|
arc: G_DCS0CLK0 G_VPFN0000
|
|
arc: G_ULPCLK0 G_VPFS0000
|
|
|
|
.tile MIB_R10C41:CMUX_UR_0
|
|
arc: G_DCS0CLK1 G_VPFN0000
|
|
arc: G_URPCLK0 G_VPFS0000
|
|
|
|
.tile MIB_R10C50:EBR_SPINE_UR0
|
|
arc: G_VPTX0000 G_HPRX0000
|
|
|
|
.tile MIB_R10C90:BANKREF2
|
|
enum: BANK.VCCIO 3V3
|
|
|
|
.tile MIB_R12C0:PICL1
|
|
enum: PIOC.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOC.HYSTERESIS ON
|
|
|
|
.tile MIB_R13C0:PICL2
|
|
enum: PIOC.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R14C0:PICL0
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R14C90:PICR0
|
|
arc: JDIA JPADDIA_PIO
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R15C0:PICL1_DQS0
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R15C90:PICR1_DQS0
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOA.HYSTERESIS ON
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R16C0:PICL2_DQS1
|
|
enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R17C0:PICL0_DQS2
|
|
arc: JDIA JPADDIA_PIO
|
|
enum: PIOA.BASE_TYPE BIDIR_LVCMOS33
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R17C90:PICR0_DQS2
|
|
arc: JDIA JPADDIA_PIO
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R18C0:PICL1_DQS3
|
|
enum: PIOA.BASE_TYPE BIDIR_LVCMOS33
|
|
enum: PIOA.HYSTERESIS ON
|
|
enum: PIOD.BASE_TYPE BIDIR_LVCMOS33
|
|
enum: PIOD.HYSTERESIS ON
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
enum: PIOC.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOC.HYSTERESIS ON
|
|
|
|
.tile MIB_R18C90:PICR1_DQS3
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOA.HYSTERESIS ON
|
|
enum: PIOC.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOC.HYSTERESIS ON
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
enum: PIOD.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R19C0:PICL2
|
|
enum: PIOD.BASE_TYPE BIDIR_LVCMOS33
|
|
enum: PIOC.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R19C90:PICR2
|
|
enum: PIOC.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOD.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C20:PICT0
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C23:PICT1
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C24:PICT0
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C25:PICT1
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C27:PICT0
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C28:PICT1
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C29:PICT0
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C30:PICT1
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C31:PICT0
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C32:PICT1
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C33:PICT0
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C34:PICT1
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C36:PICT0
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C37:PICT1
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C38:PICT0
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C39:PICT1
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C42:PICT0
|
|
enum: PIOA.BASE_TYPE BIDIR_LVCMOS33
|
|
|
|
.tile MIB_R1C43:PICT1
|
|
enum: PIOB.BASE_TYPE BIDIR_LVCMOS33
|
|
|
|
.tile MIB_R1C44:PICT0
|
|
enum: PIOA.BASE_TYPE BIDIR_LVCMOS33
|
|
|
|
.tile MIB_R1C45:PICT1
|
|
enum: PIOB.BASE_TYPE BIDIR_LVCMOS33
|
|
|
|
.tile MIB_R1C47:PICT0
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C48:PICT1
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C49:PICT0
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C50:PICT1
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C51:PICT0
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C52:PICT1
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C53:PICT0
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C54:PICT1
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C56:PICT0
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C57:PICT1
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C58:PICT0
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C59:PICT1
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C60:PICT0
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C61:PICT1
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R20C0:PICL0
|
|
arc: JDIA JPADDIA_PIO
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
enum: PIOA.BASE_TYPE BIDIR_LVCMOS33
|
|
|
|
.tile MIB_R20C90:PICR0
|
|
arc: JDIA JPADDIA_PIO
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R21C0:PICL1
|
|
enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
enum: PIOD.BASE_TYPE OUTPUT_LVCMOS33
|
|
enum: PIOA.BASE_TYPE BIDIR_LVCMOS33
|
|
enum: PIOA.HYSTERESIS ON
|
|
|
|
.tile MIB_R21C90:PICR1
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
enum: PIOD.BASE_TYPE BIDIR_LVCMOS33
|
|
enum: PIOD.HYSTERESIS ON
|
|
enum: PIOC.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOC.HYSTERESIS ON
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOA.HYSTERESIS ON
|
|
|
|
.tile MIB_R22C0:MIB_CIB_LR
|
|
enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33
|
|
enum: PIOD.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R22C90:MIB_CIB_LR_A
|
|
enum: PIOD.BASE_TYPE BIDIR_LVCMOS33
|
|
enum: PIOC.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R23C0:PICL0
|
|
arc: JDIB JPADDIB_PIO
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R23C90:PICR0
|
|
arc: JDIA JPADDIA_PIO
|
|
arc: JDIB JPADDIB_PIO
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R24C0:PICL1
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
enum: PIOD.BASE_TYPE OUTPUT_LVCMOS33
|
|
enum: PIOC.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOC.HYSTERESIS ON
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOB.HYSTERESIS ON
|
|
|
|
.tile MIB_R24C90:PICR1
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOA.HYSTERESIS ON
|
|
enum: PIOD.BASE_TYPE BIDIR_LVCMOS33
|
|
enum: PIOD.HYSTERESIS ON
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOB.HYSTERESIS ON
|
|
enum: PIOC.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOC.HYSTERESIS ON
|
|
|
|
.tile MIB_R25C0:PICL2
|
|
enum: PIOD.BASE_TYPE OUTPUT_LVCMOS33
|
|
enum: PIOC.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R25C90:PICR2
|
|
enum: PIOD.BASE_TYPE BIDIR_LVCMOS33
|
|
enum: PIOC.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R26C0:PICL0
|
|
arc: JDIB JPADDIB_PIO
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R26C90:PICR0
|
|
arc: JDIA JPADDIA_PIO
|
|
arc: JDIB JPADDIB_PIO
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R27C0:PICL1_DQS0
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
enum: PIOC.BASE_TYPE BIDIR_LVCMOS33
|
|
enum: PIOC.HYSTERESIS ON
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOB.HYSTERESIS ON
|
|
enum: PIOD.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R27C90:PICR1_DQS0
|
|
enum: PIOD.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOD.HYSTERESIS ON
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOB.HYSTERESIS ON
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOA.HYSTERESIS ON
|
|
enum: PIOC.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOC.HYSTERESIS ON
|
|
|
|
.tile MIB_R28C0:PICL2_DQS1
|
|
enum: PIOC.BASE_TYPE BIDIR_LVCMOS33
|
|
enum: PIOD.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R28C90:PICR2_DQS1
|
|
enum: PIOD.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOC.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R29C0:PICL0_DQS2
|
|
arc: JDIA JPADDIA_PIO
|
|
arc: JDIB JPADDIB_PIO
|
|
enum: PIOA.BASE_TYPE BIDIR_LVCMOS33
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R29C90:PICR0_DQS2
|
|
arc: JDIA JPADDIA_PIO
|
|
arc: JDIB JPADDIB_PIO
|
|
enum: PIOA.BASE_TYPE BIDIR_LVCMOS33
|
|
enum: PIOB.BASE_TYPE BIDIR_LVCMOS33
|
|
|
|
.tile MIB_R30C0:PICL1_DQS3
|
|
enum: PIOA.BASE_TYPE BIDIR_LVCMOS33
|
|
enum: PIOA.HYSTERESIS ON
|
|
enum: PIOC.BASE_TYPE BIDIR_LVCMOS33
|
|
enum: PIOC.HYSTERESIS ON
|
|
enum: PIOD.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOD.HYSTERESIS ON
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOB.HYSTERESIS ON
|
|
|
|
.tile MIB_R30C90:PICR1_DQS3
|
|
enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33
|
|
enum: PIOA.BASE_TYPE BIDIR_LVCMOS33
|
|
enum: PIOA.HYSTERESIS ON
|
|
enum: PIOD.BASE_TYPE BIDIR_LVCMOS33
|
|
enum: PIOD.HYSTERESIS ON
|
|
enum: PIOB.BASE_TYPE BIDIR_LVCMOS33
|
|
enum: PIOB.HYSTERESIS ON
|
|
|
|
.tile MIB_R31C0:PICL2
|
|
enum: PIOC.BASE_TYPE BIDIR_LVCMOS33
|
|
enum: PIOD.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R31C90:PICR2
|
|
enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33
|
|
enum: PIOD.BASE_TYPE BIDIR_LVCMOS33
|
|
|
|
.tile MIB_R32C0:PICL0
|
|
arc: JDIA JPADDIA_PIO
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R32C90:PICR0
|
|
arc: JDIA JPADDIA_PIO
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R33C0:PICL1
|
|
enum: PIOD.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOD.HYSTERESIS ON
|
|
enum: PIOC.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOC.HYSTERESIS ON
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOA.HYSTERESIS ON
|
|
|
|
.tile MIB_R33C90:PICR1
|
|
enum: PIOD.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOD.HYSTERESIS ON
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOA.HYSTERESIS ON
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
enum: PIOC.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOC.HYSTERESIS ON
|
|
|
|
.tile MIB_R34C0:MIB_CIB_LR
|
|
enum: PIOD.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOC.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R34C90:MIB_CIB_LR_A
|
|
enum: PIOD.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOC.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R35C0:PICL0
|
|
arc: JDIA JPADDIA_PIO
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R35C90:PICR0
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R36C0:PICL1
|
|
enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOA.HYSTERESIS ON
|
|
enum: PIOD.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOD.HYSTERESIS ON
|
|
|
|
.tile MIB_R36C90:PICR1
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
enum: PIOD.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOD.HYSTERESIS ON
|
|
enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R37C0:PICL2
|
|
enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33
|
|
enum: PIOD.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R37C90:PICR2
|
|
enum: PIOD.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R38C90:PICR0
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R39C0:PICL1_DQS0
|
|
enum: PIOD.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOD.HYSTERESIS ON
|
|
|
|
.tile MIB_R39C90:PICR1_DQS0
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
enum: PIOD.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOD.HYSTERESIS ON
|
|
|
|
.tile MIB_R40C0:PICL2_DQS1
|
|
enum: PIOD.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R40C90:PICR2_DQS1
|
|
enum: PIOD.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R58C40:CMUX_LL_0
|
|
arc: G_DCS1CLK0 G_VPFN0000
|
|
arc: G_LLPCLK0 G_VPFS0000
|
|
|
|
.tile MIB_R58C41:CMUX_LR_0
|
|
arc: G_DCS1CLK1 G_VPFN0000
|
|
arc: G_LRPCLK0 G_VPFS0000
|
|
|
|
.tile MIB_R71C10:PICB1
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOB.HYSTERESIS ON
|
|
|
|
.tile MIB_R71C11:PICB0
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R71C12:PICB1
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOB.HYSTERESIS ON
|
|
|
|
.tile MIB_R71C13:PICB0
|
|
arc: JDIA JPADDIA_PIO
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOA.HYSTERESIS ON
|
|
|
|
.tile MIB_R71C14:PICB1
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOB.HYSTERESIS ON
|
|
|
|
.tile MIB_R71C15:PICB0
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R71C16:PICB1
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOB.HYSTERESIS ON
|
|
|
|
.tile MIB_R71C18:SPICB0
|
|
enum: PIOA.BASE_TYPE BIDIR_LVCMOS33
|
|
enum: PIOA.BASE_TYPE BIDIR_LVCMOS33
|
|
enum: PIOA.HYSTERESIS ON
|
|
|
|
.tile MIB_R71C1:BANKREF6
|
|
enum: BANK.VCCIO 3V3
|
|
|
|
.tile MIB_R71C3:BANKREF8
|
|
enum: BANK.VCCIO 3V3
|
|
|
|
.tile MIB_R71C4:EFB0_PICB0
|
|
unknown: F54B1
|
|
unknown: F56B1
|
|
unknown: F82B1
|
|
unknown: F94B1
|
|
|
|
.tile MIB_R71C89:BANKREF3
|
|
enum: BANK.VCCIO 3V3
|
|
|
|
.tile MIB_R71C9:PICB0
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile R11C23:PLC2
|
|
arc: N1_V02N0401 S3_V06N0203
|
|
|
|
.tile R11C27:PLC2
|
|
arc: N1_V02N0701 S3_V06N0203
|
|
|
|
.tile R11C38:PLC2
|
|
arc: N1_V02N0501 S3_V06N0303
|
|
|
|
.tile R11C39:PLC2
|
|
arc: N1_V02N0201 S3_V06N0103
|
|
arc: N1_V02N0401 S3_V06N0203
|
|
|
|
.tile R11C46:PLC2
|
|
arc: N1_V02N0301 S3_V06N0003
|
|
|
|
.tile R11C62:PLC2
|
|
arc: N1_V02N0601 S3_V06N0303
|
|
|
|
.tile R12C51:PLC2
|
|
arc: N3_V06N0103 S3_V06N0003
|
|
|
|
.tile R12C54:PLC2
|
|
arc: N3_V06N0303 S3_V06N0303
|
|
|
|
.tile R13C25:PLC2
|
|
arc: S1_V02S0001 N3_V06S0003
|
|
arc: S3_V06S0003 N3_V06S0003
|
|
|
|
.tile R13C27:PLC2
|
|
arc: S3_V06S0103 N3_V06S0003
|
|
|
|
.tile R13C28:PLC2
|
|
arc: S3_V06S0103 N3_V06S0003
|
|
|
|
.tile R13C31:PLC2
|
|
arc: N3_V06N0103 S3_V06N0003
|
|
arc: S3_V06S0103 N3_V06S0103
|
|
arc: S3_V06S0303 N3_V06S0203
|
|
|
|
.tile R13C33:PLC2
|
|
arc: S3_V06S0203 N3_V06S0103
|
|
|
|
.tile R13C34:PLC2
|
|
arc: S3_V06S0103 N3_V06S0103
|
|
arc: S3_V06S0203 N3_V06S0103
|
|
|
|
.tile R13C36:PLC2
|
|
arc: S1_V02S0301 N3_V06S0003
|
|
|
|
.tile R13C37:PLC2
|
|
arc: S1_V02S0001 S3_V06N0003
|
|
arc: S1_V02S0101 N3_V06S0103
|
|
arc: S1_V02S0201 S3_V06N0103
|
|
arc: S3_V06S0003 N3_V06S0303
|
|
arc: S3_V06S0103 N3_V06S0103
|
|
arc: V01S0000 S3_V06N0103
|
|
arc: V01S0100 S3_V06N0303
|
|
|
|
.tile R13C38:PLC2
|
|
arc: S1_V02S0601 S3_V06N0303
|
|
arc: S3_V06S0003 N3_V06S0003
|
|
arc: S3_V06S0303 N3_V06S0203
|
|
|
|
.tile R13C40:PLC2
|
|
arc: S1_V02S0401 N3_V06S0203
|
|
arc: S3_V06S0003 N3_V06S0303
|
|
arc: S3_V06S0203 N3_V06S0103
|
|
arc: S3_V06S0303 N3_V06S0303
|
|
|
|
.tile R13C41:PLC2
|
|
arc: S3_V06S0203 N3_V06S0103
|
|
arc: S3_V06S0303 N3_V06S0303
|
|
arc: V01S0100 N3_V06S0303
|
|
|
|
.tile R13C42:PLC2
|
|
arc: N3_V06N0103 S3_V06N0003
|
|
arc: S1_V02S0201 N3_V06S0103
|
|
arc: S1_V02S0601 N3_V06S0303
|
|
|
|
.tile R13C43:PLC2
|
|
arc: S3_V06S0303 N3_V06S0203
|
|
|
|
.tile R13C44:PLC2
|
|
arc: N3_V06N0103 S3_V06N0003
|
|
arc: S1_V02S0101 N3_V06S0103
|
|
arc: S3_V06S0203 N3_V06S0203
|
|
arc: S3_V06S0303 N3_V06S0303
|
|
|
|
.tile R13C46:PLC2
|
|
arc: N3_V06N0103 S3_V06N0003
|
|
|
|
.tile R13C48:PLC2
|
|
arc: N3_V06N0103 S3_V06N0003
|
|
|
|
.tile R13C49:PLC2
|
|
arc: S3_V06S0203 N3_V06S0103
|
|
|
|
.tile R13C52:PLC2
|
|
arc: N3_V06N0103 S3_V06N0103
|
|
arc: S3_V06S0303 N3_V06S0203
|
|
|
|
.tile R13C54:PLC2
|
|
arc: S3_V06S0203 N3_V06S0103
|
|
|
|
.tile R13C55:PLC2
|
|
arc: S3_V06S0303 N3_V06S0303
|
|
|
|
.tile R14C28:PLC2
|
|
arc: N3_V06N0103 H06W0103
|
|
|
|
.tile R14C2:PLC2
|
|
arc: W1_H02W0701 S1_V02N0701
|
|
|
|
.tile R14C31:PLC2
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
|
|
.tile R14C36:PLC2
|
|
arc: E1_H02E0001 S3_V06N0003
|
|
arc: E1_H02E0501 S3_V06N0303
|
|
arc: E1_H02E0601 S3_V06N0303
|
|
arc: S1_V02S0001 S3_V06N0003
|
|
arc: V01S0100 S3_V06N0303
|
|
|
|
.tile R14C37:PLC2
|
|
arc: E1_H02E0101 V02S0101
|
|
arc: E1_H02E0401 N1_V01S0000
|
|
arc: E1_H02E0601 N1_V01S0000
|
|
arc: H00L0000 V02S0001
|
|
arc: H00L0100 E1_H02W0301
|
|
arc: S1_V02S0201 S3_V06N0103
|
|
arc: V00B0100 V02S0101
|
|
arc: A0 H00L0100
|
|
arc: B0 V02N0101
|
|
arc: C0 N1_V01S0100
|
|
arc: CE0 H00L0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H02E0001
|
|
arc: F0 F0_SLICE
|
|
arc: LSR0 V00B0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: W3_H06W0003 Q0
|
|
word: SLICEA.K0.INIT 1100111011111010
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R14C38:PLC2
|
|
arc: E3_H06E0203 S3_V06N0203
|
|
arc: H00L0100 H02W0301
|
|
arc: H00R0000 W1_H02E0601
|
|
arc: H00R0100 V02N0501
|
|
arc: S1_V02S0101 H02E0101
|
|
arc: V00T0100 H02E0101
|
|
arc: V01S0100 S3_V06N0303
|
|
arc: A0 H00L0100
|
|
arc: A1 W1_H02E0501
|
|
arc: B0 E1_H02W0301
|
|
arc: B1 H02W0301
|
|
arc: C0 H02E0401
|
|
arc: C1 H02E0601
|
|
arc: CE3 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H00R0000
|
|
arc: D1 S1_V02N0201
|
|
arc: F0 F5A_SLICE
|
|
arc: LSR0 V00T0100
|
|
arc: M0 V00B0100
|
|
arc: M7 H00L0100
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR3 LSR0
|
|
arc: S1_V02S0201 F0
|
|
arc: V00B0100 Q7
|
|
word: SLICEA.K0.INIT 1010100010101111
|
|
word: SLICEA.K1.INIT 1100110111101111
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R14C39:PLC2
|
|
arc: W1_H02W0301 E1_H02W0201
|
|
|
|
.tile R14C40:PLC2
|
|
arc: N3_V06N0303 S3_V06N0303
|
|
arc: W1_H02W0301 S1_V02N0301
|
|
|
|
.tile R14C41:PLC2
|
|
arc: S3_V06S0103 N1_V01S0100
|
|
arc: W1_H02W0201 E3_H06W0103
|
|
|
|
.tile R14C42:PLC2
|
|
arc: H00L0000 V02S0201
|
|
arc: H00R0000 V02N0401
|
|
arc: V00T0100 S1_V02N0501
|
|
arc: CE3 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E3_H06E0203 Q7
|
|
arc: LSR1 V00T0100
|
|
arc: M7 H00L0000
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR3 LSR1
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R14C44:PLC2
|
|
arc: N3_V06N0203 W3_H06E0203
|
|
|
|
.tile R14C47:PLC2
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
|
|
.tile R14C48:PLC2
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
|
|
.tile R14C53:PLC2
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
|
|
.tile R14C54:PLC2
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
|
|
.tile R14C59:PLC2
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
|
|
.tile R14C60:PLC2
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
|
|
.tile R14C65:PLC2
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
|
|
.tile R14C66:PLC2
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
|
|
.tile R14C71:PLC2
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
|
|
.tile R14C72:PLC2
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
|
|
.tile R14C77:PLC2
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
|
|
.tile R14C78:PLC2
|
|
arc: E1_H01E0101 W3_H06E0203
|
|
|
|
.tile R14C79:PLC2
|
|
arc: E3_H06E0303 H01E0101
|
|
|
|
.tile R14C83:PLC2
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
|
|
.tile R14C85:PLC2
|
|
arc: E1_H02E0601 W3_H06E0303
|
|
|
|
.tile R14C87:PLC2
|
|
arc: E1_H02E0701 W1_H02E0601
|
|
|
|
.tile R15C25:PLC2
|
|
arc: S1_V02S0001 N1_V02S0001
|
|
|
|
.tile R15C35:PLC2
|
|
arc: E1_H02E0501 V01N0101
|
|
arc: S3_V06S0203 E1_H01W0000
|
|
|
|
.tile R15C36:PLC2
|
|
arc: E1_H02E0301 N1_V02S0301
|
|
arc: E1_H02E0501 N1_V01S0100
|
|
arc: E1_H02E0701 N1_V01S0100
|
|
arc: S1_V02S0601 E1_H02W0601
|
|
arc: V00T0100 H02W0101
|
|
arc: A0 S1_V02N0501
|
|
arc: B0 N1_V02S0301
|
|
arc: C0 E1_H01W0000
|
|
arc: CE0 E1_H02W0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02S0001
|
|
arc: E1_H02E0101 F3
|
|
arc: F0 F0_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: H01W0000 F3
|
|
arc: LSR1 V00T0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: N3_V06N0003 Q0
|
|
word: SLICEA.K0.INIT 1111010011101110
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
|
|
.tile R15C37:PLC2
|
|
arc: E1_H02E0101 S1_V02N0101
|
|
arc: E1_H02E0301 V01N0101
|
|
arc: H00L0100 H02E0301
|
|
arc: H00R0000 V02N0601
|
|
arc: H00R0100 H02E0501
|
|
arc: N1_V02N0101 E1_H01W0100
|
|
arc: S1_V02S0101 N1_V02S0101
|
|
arc: V00B0100 N1_V02S0101
|
|
arc: W1_H02W0101 N1_V02S0101
|
|
arc: A6 H02E0701
|
|
arc: A7 W1_H02E0501
|
|
arc: B6 V02N0701
|
|
arc: B7 H02E0301
|
|
arc: C6 S1_V02N0001
|
|
arc: C7 N1_V02S0201
|
|
arc: CE0 H00R0000
|
|
arc: CE1 V02S0201
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D6 H00L0100
|
|
arc: D7 H00R0100
|
|
arc: F6 F5D_SLICE
|
|
arc: H01W0000 Q0
|
|
arc: LSR0 V00B0100
|
|
arc: M0 V00B0000
|
|
arc: M3 H00L0100
|
|
arc: M6 V00T0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR0
|
|
arc: V00B0000 F6
|
|
arc: V00T0100 Q3
|
|
word: SLICED.K0.INIT 1111110100000101
|
|
word: SLICED.K1.INIT 1101110111001111
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R15C38:PLC2
|
|
arc: E1_H02E0001 W1_H02E0501
|
|
arc: E1_H02E0101 N1_V01S0100
|
|
arc: E1_H02E0501 W1_H02E0501
|
|
arc: N1_V02N0501 N1_V01S0100
|
|
arc: V00B0000 V02S0201
|
|
arc: V00B0100 V02S0101
|
|
arc: V00T0000 S1_V02N0401
|
|
arc: W1_H02W0101 S1_V02N0101
|
|
arc: A5 V00T0000
|
|
arc: B0 W1_H02E0101
|
|
arc: B2 V02N0301
|
|
arc: B3 H02E0301
|
|
arc: B4 S1_V02N0701
|
|
arc: B6 H02E0101
|
|
arc: B7 V02N0501
|
|
arc: CE3 N1_V02S0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0100 Q6
|
|
arc: LSR0 V00B0100
|
|
arc: M6 V00B0000
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR3 LSR0
|
|
arc: S1_V02S0401 F4
|
|
arc: S1_V02S0501 F7
|
|
arc: S1_V02S0701 F5
|
|
arc: V01S0000 F3
|
|
arc: W1_H02W0601 F6
|
|
word: SLICEA.K0.INIT 0000000000001100
|
|
word: SLICEA.K1.INIT 1111111111111111
|
|
word: SLICEB.K0.INIT 0110011001101010
|
|
word: SLICEB.K1.INIT 1100110011000000
|
|
word: SLICEC.K0.INIT 1100110011000000
|
|
word: SLICEC.K1.INIT 1010101010100000
|
|
word: SLICED.K0.INIT 1100110011000000
|
|
word: SLICED.K1.INIT 1100110011000000
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 YES
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R15C39:PLC2
|
|
arc: V00B0000 S1_V02N0001
|
|
arc: A2 V00B0000
|
|
arc: A3 H02W0701
|
|
arc: B0 V02N0101
|
|
arc: B1 V02N0301
|
|
arc: B4 E1_H02W0101
|
|
arc: B5 V02N0701
|
|
arc: B6 S1_V02N0501
|
|
arc: B7 H02W0101
|
|
arc: E1_H01E0001 F3
|
|
arc: E1_H01E0101 F4
|
|
arc: E1_H02E0201 F2
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: S1_V02S0601 F6
|
|
arc: S3_V06S0203 F7
|
|
arc: S3_V06S0303 F5
|
|
arc: V01S0000 F1
|
|
arc: V01S0100 F0
|
|
word: SLICEA.K0.INIT 1100110011000000
|
|
word: SLICEA.K1.INIT 1100110011000000
|
|
word: SLICEB.K0.INIT 1010101010100000
|
|
word: SLICEB.K1.INIT 1010101010100000
|
|
word: SLICEC.K0.INIT 1100110011000000
|
|
word: SLICEC.K1.INIT 1100110011000000
|
|
word: SLICED.K0.INIT 1100110011000000
|
|
word: SLICED.K1.INIT 1100110011000000
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
|
|
.tile R15C40:PLC2
|
|
arc: H00L0000 V02N0201
|
|
arc: S1_V02S0401 N1_V02S0401
|
|
arc: S1_V02S0501 N1_V02S0401
|
|
arc: S1_V02S0601 H01E0001
|
|
arc: S1_V02S0701 H01E0101
|
|
arc: S3_V06S0203 N1_V02S0401
|
|
arc: V00B0000 S1_V02N0201
|
|
arc: V00T0000 N1_V02S0401
|
|
arc: W1_H02W0101 V06N0103
|
|
arc: W1_H02W0701 V01N0101
|
|
arc: A2 W1_H02E0501
|
|
arc: A3 H00L0100
|
|
arc: B2 V02N0301
|
|
arc: B3 V02N0101
|
|
arc: C2 H00L0100
|
|
arc: C3 H00L0000
|
|
arc: CE1 W1_H02E0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D2 V02N0201
|
|
arc: D3 W1_H02E0001
|
|
arc: F2 F5B_SLICE
|
|
arc: H00L0100 Q3
|
|
arc: LSR1 V00T0000
|
|
arc: M2 V00B0000
|
|
arc: M3 H00L0000
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXLSR1 LSR1
|
|
arc: S1_V02S0001 F2
|
|
word: SLICEB.K0.INIT 1111110101110101
|
|
word: SLICEB.K1.INIT 1111001011110000
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000001110
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
|
|
.tile R15C41:PLC2
|
|
arc: N3_V06N0103 S3_V06N0003
|
|
arc: S1_V02S0201 W1_H02E0201
|
|
arc: W1_H02W0101 V02N0101
|
|
|
|
.tile R15C42:PLC2
|
|
arc: N1_V02N0401 S1_V02N0101
|
|
arc: S1_V02S0701 N1_V02S0601
|
|
|
|
.tile R15C44:PLC2
|
|
arc: S1_V02S0401 N1_V02S0101
|
|
|
|
.tile R16C27:PLC2
|
|
arc: S1_V02S0101 H02W0101
|
|
arc: S1_V02S0301 S3_V06N0003
|
|
|
|
.tile R16C28:PLC2
|
|
arc: W1_H02W0101 V06S0103
|
|
|
|
.tile R16C2:PLC2
|
|
arc: N1_V02N0701 S1_V02N0701
|
|
|
|
.tile R16C32:PLC2
|
|
arc: N3_V06N0103 H06W0103
|
|
|
|
.tile R16C34:PLC2
|
|
arc: S1_V02S0301 S3_V06N0003
|
|
arc: V00T0000 V02N0401
|
|
arc: A0 V02N0501
|
|
arc: B0 E1_H02W0301
|
|
arc: C0 S1_V02N0601
|
|
arc: CE0 S1_V02N0201
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02N0201
|
|
arc: F0 F0_SLICE
|
|
arc: LSR0 V00T0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: N3_V06N0003 Q0
|
|
word: SLICEA.K0.INIT 1011111110001111
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET SET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
|
|
.tile R16C35:PLC2
|
|
arc: E1_H02E0701 S3_V06N0203
|
|
arc: N1_V01N0101 S3_V06N0203
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
|
|
.tile R16C36:PLC2
|
|
arc: S1_V02S0201 H02W0201
|
|
arc: S1_V02S0701 H02E0701
|
|
arc: V00T0000 H02W0201
|
|
arc: W1_H02W0301 S1_V02N0301
|
|
arc: A0 V01N0101
|
|
arc: B0 V02N0101
|
|
arc: C0 V02N0601
|
|
arc: CE0 S1_V02N0201
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02N0201
|
|
arc: E3_H06E0003 Q0
|
|
arc: F0 F0_SLICE
|
|
arc: LSR1 V00T0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
word: SLICEA.K0.INIT 1110111110101111
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET SET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R16C37:PLC2
|
|
arc: E1_H02E0101 V01N0101
|
|
arc: E1_H02E0201 S1_V02N0201
|
|
arc: E1_H02E0401 V01N0001
|
|
arc: E1_H02E0501 V01N0101
|
|
arc: E1_H02E0601 V01N0001
|
|
arc: E1_H02E0701 V02N0701
|
|
arc: N1_V02N0601 H02W0601
|
|
arc: N1_V02N0701 W1_H02E0701
|
|
arc: S1_V02S0701 W1_H02E0701
|
|
arc: V00B0100 V02S0101
|
|
arc: V00T0100 E1_H02W0301
|
|
arc: W1_H02W0201 V06S0103
|
|
arc: A3 V02N0501
|
|
arc: C0 V02N0601
|
|
arc: C3 V02N0401
|
|
arc: CE0 V02N0201
|
|
arc: CE1 V02N0201
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 Q0
|
|
arc: D3 E1_H02W0201
|
|
arc: E1_H01E0001 Q3
|
|
arc: E1_H01E0101 Q0
|
|
arc: E1_H02E0301 Q3
|
|
arc: F0 F0_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: LSR0 V00B0100
|
|
arc: M2 V00T0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR0
|
|
arc: N1_V01N0101 Q2
|
|
arc: S1_V02S0001 Q2
|
|
arc: S1_V02S0201 Q0
|
|
arc: V01S0000 Q2
|
|
arc: V01S0100 Q0
|
|
word: SLICEA.K0.INIT 0000000000001111
|
|
word: SLICEB.K1.INIT 1010111100000000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R16C38:PLC2
|
|
arc: E1_H02E0201 V02N0201
|
|
arc: E1_H02E0401 N1_V01S0000
|
|
arc: E1_H02E0601 N1_V01S0000
|
|
arc: H00L0000 V02N0001
|
|
arc: N1_V02N0201 H06W0103
|
|
arc: N1_V02N0301 H01E0101
|
|
arc: N1_V02N0501 V01N0101
|
|
arc: S1_V02S0001 H01E0001
|
|
arc: V00B0100 S1_V02N0101
|
|
arc: V00T0000 V02S0401
|
|
arc: W1_H02W0601 V06N0303
|
|
arc: A1 H02E0501
|
|
arc: A3 H02E0501
|
|
arc: C1 H02E0401
|
|
arc: C3 H02E0601
|
|
arc: CE2 H00L0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D1 V02N0201
|
|
arc: D3 H02E0201
|
|
arc: E1_H01E0101 F1
|
|
arc: F0 F5A_SLICE
|
|
arc: F1 FXA_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: LSR0 V00B0100
|
|
arc: M0 V00T0000
|
|
arc: M1 E1_H02W0001
|
|
arc: M2 V00T0000
|
|
arc: M4 E1_H01E0101
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR2 LSR0
|
|
arc: S1_V02S0401 Q4
|
|
arc: V01S0000 Q4
|
|
arc: V01S0100 Q4
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 1111101010101010
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 1111111111111010
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R16C39:PLC2
|
|
arc: E1_H02E0101 V02N0101
|
|
arc: E1_H02E0201 V02N0201
|
|
arc: E1_H02E0301 N1_V01S0100
|
|
arc: H00R0000 V02N0401
|
|
arc: N1_V02N0101 E1_H01W0100
|
|
arc: N1_V02N0301 W1_H02E0301
|
|
arc: N1_V02N0701 S1_V02N0701
|
|
arc: S1_V02S0301 W1_H02E0301
|
|
arc: W1_H02W0201 N1_V01S0000
|
|
arc: A5 W1_H02E0701
|
|
arc: B1 W1_H02E0101
|
|
arc: B3 W1_H02E0101
|
|
arc: B5 W1_H02E0101
|
|
arc: B7 W1_H02E0101
|
|
arc: C1 W1_H02E0601
|
|
arc: C3 W1_H02E0401
|
|
arc: C5 S1_V02N0201
|
|
arc: C7 W1_H02E0601
|
|
arc: D1 H02E0201
|
|
arc: D5 H02E0201
|
|
arc: D7 W1_H02E0201
|
|
arc: F0 F5A_SLICE
|
|
arc: F1 FXA_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F3 FXB_SLICE
|
|
arc: F4 F5C_SLICE
|
|
arc: F5 FXC_SLICE
|
|
arc: F6 F5D_SLICE
|
|
arc: M0 H02E0601
|
|
arc: M1 H02W0001
|
|
arc: M2 H02E0601
|
|
arc: M3 H00R0000
|
|
arc: M4 H02E0401
|
|
arc: M5 H02W0001
|
|
arc: M6 H02E0401
|
|
arc: W1_H02W0301 F3
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 1111110011001100
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 1111110011111100
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 1111111011111100
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 1111111111111100
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A1MUX 1
|
|
|
|
.tile R16C3:PLC2
|
|
arc: W1_H02W0701 V02N0701
|
|
|
|
.tile R16C40:PLC2
|
|
arc: E1_H02E0401 V06S0203
|
|
arc: E1_H02E0501 V02S0501
|
|
arc: E1_H02E0701 V06S0203
|
|
arc: N1_V02N0101 H02W0101
|
|
arc: N1_V02N0201 H02W0201
|
|
arc: N1_V02N0301 H02W0301
|
|
arc: V00T0000 V02S0401
|
|
arc: W1_H02W0001 V02N0001
|
|
arc: A0 V02S0701
|
|
arc: A1 V02N0501
|
|
arc: B2 H02E0301
|
|
arc: C0 V02N0601
|
|
arc: C1 V02S0601
|
|
arc: C2 V02N0601
|
|
arc: CE0 H02E0101
|
|
arc: CE1 H02E0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H02E0201
|
|
arc: D1 H02E0201
|
|
arc: D2 H02E0201
|
|
arc: E1_H01E0101 Q0
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: H01W0100 Q2
|
|
arc: LSR1 V00T0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR1
|
|
arc: N1_V01N0101 Q1
|
|
arc: S1_V02S0001 Q0
|
|
arc: S1_V02S0201 Q0
|
|
arc: V01S0000 Q2
|
|
arc: V01S0100 Q1
|
|
word: SLICEA.K0.INIT 1010101000001010
|
|
word: SLICEB.K0.INIT 1100110000001100
|
|
word: SLICEA.K1.INIT 1111000001010000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R16C41:PLC2
|
|
arc: H00L0000 V02N0201
|
|
arc: N1_V02N0101 H01E0101
|
|
arc: S1_V02S0301 S3_V06N0003
|
|
arc: S1_V02S0701 H02E0701
|
|
arc: V01S0000 S3_V06N0103
|
|
arc: W1_H02W0101 S3_V06N0103
|
|
arc: W1_H02W0201 V06N0103
|
|
arc: W1_H02W0301 S3_V06N0003
|
|
arc: W3_H06W0103 S3_V06N0103
|
|
arc: A0 S1_V02N0501
|
|
arc: A1 H02E0701
|
|
arc: B0 S1_V02N0101
|
|
arc: B1 H00R0100
|
|
arc: C0 V02N0401
|
|
arc: C1 V02N0401
|
|
arc: C6 H02E0401
|
|
arc: CE0 E1_H02W0101
|
|
arc: CE2 V02N0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02N0001
|
|
arc: D1 V02N0001
|
|
arc: D6 H00R0100
|
|
arc: E3_H06E0103 Q1
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: H00R0100 Q5
|
|
arc: LSR0 H02E0501
|
|
arc: LSR1 E1_H02W0501
|
|
arc: M5 H00L0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR2 LSR1
|
|
arc: S1_V02S0401 F6
|
|
arc: W3_H06W0003 Q0
|
|
word: SLICEA.K1.INIT 1100111011111010
|
|
word: SLICEA.K0.INIT 1010111011111100
|
|
word: SLICED.K0.INIT 0000111111110000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R16C42:PLC2
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: N1_V02N0501 H02W0501
|
|
arc: S1_V02S0401 W1_H02E0401
|
|
|
|
.tile R16C43:PLC2
|
|
arc: W1_H02W0101 V02N0101
|
|
arc: W1_H02W0501 V06S0303
|
|
|
|
.tile R16C44:PLC2
|
|
arc: S1_V02S0201 H06W0103
|
|
|
|
.tile R16C47:PLC2
|
|
arc: N3_V06N0103 W3_H06E0103
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
|
|
.tile R16C48:PLC2
|
|
arc: N3_V06N0103 W3_H06E0103
|
|
|
|
.tile R16C53:PLC2
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
|
|
.tile R16C59:PLC2
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
|
|
.tile R16C65:PLC2
|
|
arc: W3_H06W0303 E3_H06W0203
|
|
|
|
.tile R16C71:PLC2
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
|
|
.tile R16C77:PLC2
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
|
|
.tile R16C83:PLC2
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
|
|
.tile R17C10:PLC2
|
|
arc: H01W0100 E3_H06W0303
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
|
|
.tile R17C13:PLC2
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
|
|
.tile R17C14:PLC2
|
|
arc: W3_H06W0303 E3_H06W0203
|
|
|
|
.tile R17C15:PLC2
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
|
|
.tile R17C16:PLC2
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
arc: W3_H06W0303 E3_H06W0203
|
|
|
|
.tile R17C17:PLC2
|
|
arc: S3_V06S0003 E3_H06W0003
|
|
|
|
.tile R17C19:PLC2
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
|
|
.tile R17C20:PLC2
|
|
arc: W3_H06W0203 E3_H06W0203
|
|
|
|
.tile R17C21:PLC2
|
|
arc: E1_H02E0101 E3_H06W0103
|
|
arc: E1_H02E0201 W3_H06E0103
|
|
arc: E1_H02E0401 W3_H06E0203
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
|
|
.tile R17C22:PLC2
|
|
arc: V00T0000 H02E0201
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
arc: CE2 H02E0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: LSR0 H02W0301
|
|
arc: M4 V00T0000
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR2 LSR0
|
|
arc: W3_H06W0203 Q4
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R17C23:PLC2
|
|
arc: W1_H02W0301 E1_H02W0301
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
arc: CE2 E1_H02W0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: LSR1 E1_H02W0301
|
|
arc: M4 W1_H02E0401
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR2 LSR1
|
|
arc: N3_V06N0203 Q4
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R17C25:PLC2
|
|
arc: E1_H02E0201 W3_H06E0103
|
|
arc: E1_H02E0301 S1_V02N0301
|
|
arc: V00B0000 N1_V02S0001
|
|
arc: V00T0000 S1_V02N0401
|
|
arc: W1_H02W0101 E1_H02W0101
|
|
arc: W1_H02W0301 S1_V02N0301
|
|
arc: CE3 E1_H02W0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: LSR0 V00B0000
|
|
arc: M6 V00T0000
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR3 LSR0
|
|
arc: W3_H06W0303 Q6
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R17C26:PLC2
|
|
arc: E1_H02E0401 E3_H06W0203
|
|
arc: E1_H02E0701 E3_H06W0203
|
|
arc: V00B0100 S1_V02N0101
|
|
arc: CE2 H02W0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: LSR0 H02E0301
|
|
arc: M4 V00B0100
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR2 LSR0
|
|
arc: W3_H06W0203 Q4
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R17C27:PLC2
|
|
arc: H00L0000 W1_H02E0201
|
|
arc: H00L0100 V02S0301
|
|
arc: H00R0000 H02E0401
|
|
arc: H00R0100 H02E0701
|
|
arc: V00B0100 V02S0101
|
|
arc: W1_H02W0101 E3_H06W0103
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
arc: CE2 H00R0100
|
|
arc: CE3 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: LSR0 W1_H02E0301
|
|
arc: LSR1 V00B0100
|
|
arc: M5 H00L0000
|
|
arc: M7 H00L0100
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR2 LSR0
|
|
arc: MUXLSR3 LSR1
|
|
arc: N3_V06N0203 Q7
|
|
arc: W3_H06W0303 Q5
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R17C28:PLC2
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
|
|
.tile R17C29:PLC2
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
|
|
.tile R17C2:PLC2
|
|
arc: S3_V06S0003 E3_H06W0003
|
|
arc: W1_H02W0701 S1_V02N0701
|
|
arc: C7 S1_V02N0001
|
|
arc: D0 S1_V02N0001
|
|
arc: E1_H01E0101 F7
|
|
arc: F0 F0_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0100 F0
|
|
word: SLICEA.K0.INIT 0000000011111111
|
|
word: SLICED.K1.INIT 0000111100001111
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
|
|
.tile R17C32:PLC2
|
|
arc: W3_H06W0203 E1_H01W0000
|
|
|
|
.tile R17C33:PLC2
|
|
arc: E1_H02E0201 E3_H06W0103
|
|
arc: H01W0000 E3_H06W0103
|
|
arc: S1_V02S0001 H06W0003
|
|
arc: S1_V02S0301 H06W0003
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
|
|
.tile R17C34:PLC2
|
|
arc: N1_V02N0201 S1_V02N0701
|
|
arc: N1_V02N0401 S1_V02N0401
|
|
arc: N1_V02N0501 H06W0303
|
|
arc: V00T0000 S1_V02N0401
|
|
arc: A0 V02N0501
|
|
arc: B0 H02W0301
|
|
arc: C0 E1_H02W0601
|
|
arc: CE0 V02N0201
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H02E0201
|
|
arc: F0 F0_SLICE
|
|
arc: LSR1 V00T0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: W3_H06W0003 Q0
|
|
word: SLICEA.K0.INIT 1111110111110101
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET SET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R17C35:PLC2
|
|
arc: H00R0000 H02W0401
|
|
arc: S1_V02S0701 H06W0203
|
|
arc: V00T0100 S1_V02N0701
|
|
arc: W1_H02W0301 S1_V02N0301
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
arc: A0 V02N0701
|
|
arc: B0 V01N0001
|
|
arc: C0 V02N0601
|
|
arc: CE0 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 S1_V02N0201
|
|
arc: F0 F0_SLICE
|
|
arc: LSR1 V00T0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: S1_V02S0001 Q0
|
|
word: SLICEA.K0.INIT 1011101110110011
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET SET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R17C36:PLC2
|
|
arc: E1_H02E0501 E1_H01W0100
|
|
arc: E1_H02E0701 S1_V02N0701
|
|
arc: H00L0000 E1_H02W0001
|
|
arc: H00R0000 E1_H02W0601
|
|
arc: H00R0100 E1_H02W0701
|
|
arc: N1_V02N0101 S1_V02N0001
|
|
arc: N1_V02N0201 H06W0103
|
|
arc: N1_V02N0501 S1_V02N0501
|
|
arc: N1_V02N0601 S1_V02N0301
|
|
arc: S1_V02S0201 H06W0103
|
|
arc: S1_V02S0601 E1_H01W0000
|
|
arc: S3_V06S0203 E1_H01W0000
|
|
arc: V00B0000 V02S0201
|
|
arc: W1_H02W0401 V01N0001
|
|
arc: W3_H06W0003 E1_H01W0000
|
|
arc: A6 H02W0501
|
|
arc: B6 V02S0701
|
|
arc: C0 N1_V02S0601
|
|
arc: C4 E1_H02W0601
|
|
arc: C6 S1_V02N0201
|
|
arc: CE0 H00L0000
|
|
arc: CE2 H00L0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H00R0000
|
|
arc: D4 H00R0100
|
|
arc: D6 S1_V02N0601
|
|
arc: E1_H01E0001 Q0
|
|
arc: E1_H01E0101 Q0
|
|
arc: E1_H02E0401 Q4
|
|
arc: F0 F0_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: LSR0 V00B0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR2 LSR0
|
|
arc: N1_V01N0101 F6
|
|
arc: V01S0000 Q0
|
|
arc: V01S0100 Q4
|
|
arc: W1_H02W0601 F6
|
|
word: SLICED.K0.INIT 1111000010000000
|
|
word: SLICEA.K0.INIT 0000000011110000
|
|
word: SLICEC.K0.INIT 0000111100000000
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R17C37:PLC2
|
|
arc: E1_H02E0001 H01E0001
|
|
arc: E1_H02E0101 N1_V01S0100
|
|
arc: E1_H02E0401 N1_V01S0000
|
|
arc: N1_V02N0001 S1_V02N0001
|
|
arc: N1_V02N0101 H01E0101
|
|
arc: N1_V02N0201 E1_H01W0000
|
|
arc: N1_V02N0501 H02W0501
|
|
arc: N1_V02N0601 H02W0601
|
|
arc: S1_V02S0001 E1_H02W0001
|
|
arc: S1_V02S0401 N1_V02S0101
|
|
arc: S1_V02S0501 E1_H01W0100
|
|
arc: V00B0100 V02N0301
|
|
arc: V00T0100 V02S0701
|
|
arc: W1_H02W0501 S3_V06N0303
|
|
arc: W3_H06W0303 E1_H02W0601
|
|
arc: A5 V00T0100
|
|
arc: B0 S1_V02N0101
|
|
arc: B5 V02N0701
|
|
arc: C0 E1_H02W0401
|
|
arc: C3 H02W0401
|
|
arc: C4 V02N0001
|
|
arc: C5 S1_V02N0001
|
|
arc: C6 V02N0201
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D3 S1_V02N0201
|
|
arc: D4 S1_V02N0401
|
|
arc: D5 S1_V02N0401
|
|
arc: D6 H00R0100
|
|
arc: E1_H01E0001 F3
|
|
arc: E1_H01E0101 F4
|
|
arc: E1_H02E0201 Q0
|
|
arc: E1_H02E0301 F3
|
|
arc: E1_H02E0601 F6
|
|
arc: E1_H02E0701 Q7
|
|
arc: E3_H06E0303 F6
|
|
arc: F0 F0_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F5C_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: H00R0100 Q7
|
|
arc: H01W0000 Q7
|
|
arc: H01W0100 Q0
|
|
arc: M4 V00B0100
|
|
arc: M7 E1_H02W0201
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q7
|
|
arc: N1_V01N0101 Q0
|
|
arc: N1_V02N0401 F6
|
|
arc: N1_V02N0701 Q7
|
|
arc: S1_V02S0601 F6
|
|
arc: S1_V02S0701 Q7
|
|
arc: V01S0000 F6
|
|
arc: V01S0100 Q0
|
|
word: SLICEC.K0.INIT 1111111100001111
|
|
word: SLICEC.K1.INIT 1010111100100011
|
|
word: SLICEA.K0.INIT 1111110011111100
|
|
word: SLICEB.K1.INIT 1111000000001111
|
|
word: SLICED.K0.INIT 0000000000001111
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
|
|
.tile R17C38:PLC2
|
|
arc: E1_H02E0101 S1_V02N0101
|
|
arc: E1_H02E0401 N1_V01S0000
|
|
arc: E1_H02E0501 W1_H02E0401
|
|
arc: N1_V02N0101 S1_V02N0101
|
|
arc: N1_V02N0201 H01E0001
|
|
arc: N1_V02N0401 W1_H02E0401
|
|
arc: N1_V02N0701 N1_V01S0100
|
|
arc: N3_V06N0303 E1_H01W0100
|
|
arc: S1_V02S0401 E1_H01W0000
|
|
arc: S3_V06S0103 H01E0101
|
|
arc: V00B0100 V02N0101
|
|
arc: V00T0100 N1_V02S0501
|
|
arc: W1_H02W0401 N1_V01S0000
|
|
arc: W1_H02W0701 N1_V02S0701
|
|
arc: W3_H06W0203 E1_H01W0000
|
|
arc: A0 F7
|
|
arc: A3 E1_H02W0701
|
|
arc: A5 W1_H02E0701
|
|
arc: A7 W1_H02E0501
|
|
arc: B2 V01N0001
|
|
arc: B3 E1_H02W0301
|
|
arc: B7 F3
|
|
arc: C0 H02E0601
|
|
arc: C2 S1_V02N0601
|
|
arc: C3 E1_H02W0601
|
|
arc: C5 F6
|
|
arc: C6 H02E0601
|
|
arc: C7 V02N0201
|
|
arc: CE0 H00L0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V00T0100
|
|
arc: D2 V02N0001
|
|
arc: D3 V02S0001
|
|
arc: D5 F2
|
|
arc: D6 H02E0201
|
|
arc: D7 V02N0401
|
|
arc: E1_H01E0001 F7
|
|
arc: E1_H01E0101 F2
|
|
arc: E1_H02E0201 Q0
|
|
arc: E1_H02E0601 F6
|
|
arc: F0 F0_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00L0000 F2
|
|
arc: H01W0000 F2
|
|
arc: H01W0100 Q0
|
|
arc: LSR0 V00B0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: N1_V01N0101 Q0
|
|
arc: N1_V02N0001 F2
|
|
arc: S1_V02S0101 F3
|
|
arc: S1_V02S0701 F5
|
|
arc: S3_V06S0203 F7
|
|
arc: S3_V06S0303 F6
|
|
arc: V01S0000 F6
|
|
arc: V01S0100 F2
|
|
arc: W1_H02W0001 F2
|
|
arc: W1_H02W0501 F7
|
|
arc: W1_H02W0601 F6
|
|
word: SLICED.K1.INIT 0010101010101010
|
|
word: SLICEB.K1.INIT 0100000000000000
|
|
word: SLICEC.K1.INIT 1010000000000000
|
|
word: SLICEA.K0.INIT 1010111100000000
|
|
word: SLICED.K0.INIT 0000000011110000
|
|
word: SLICEB.K0.INIT 0000110000000000
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R17C39:PLC2
|
|
arc: E1_H02E0101 H01E0101
|
|
arc: E1_H02E0601 N1_V02S0601
|
|
arc: N1_V02N0001 E1_H02W0001
|
|
arc: N1_V02N0101 H01E0101
|
|
arc: N1_V02N0201 H01E0001
|
|
arc: N1_V02N0501 E1_H01W0100
|
|
arc: N3_V06N0203 H06W0203
|
|
arc: S1_V02S0001 H01E0001
|
|
arc: S1_V02S0401 E1_H02W0401
|
|
arc: S1_V02S0501 H02W0501
|
|
arc: S1_V02S0701 W1_H02E0701
|
|
arc: W1_H02W0201 S1_V02N0201
|
|
arc: W1_H02W0401 H01E0001
|
|
arc: A1 F5
|
|
arc: A2 W1_H02E0701
|
|
arc: A3 F5
|
|
arc: A4 E1_H01W0000
|
|
arc: A5 H02E0501
|
|
arc: B1 V02S0301
|
|
arc: B2 W1_H02E0301
|
|
arc: B3 V02S0301
|
|
arc: B4 E1_H02W0301
|
|
arc: B5 W1_H02E0101
|
|
arc: B6 F3
|
|
arc: C1 H02W0601
|
|
arc: C2 H00L0100
|
|
arc: C3 H02W0601
|
|
arc: C4 S1_V02N0001
|
|
arc: C5 W1_H02E0401
|
|
arc: C6 H02E0401
|
|
arc: CE2 H02E0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D1 H02E0201
|
|
arc: D2 H02W0001
|
|
arc: D3 H02E0201
|
|
arc: D4 V02N0601
|
|
arc: D5 W1_H02E0001
|
|
arc: D6 H02W0001
|
|
arc: E1_H01E0001 F0
|
|
arc: E1_H01E0101 F2
|
|
arc: E3_H06E0103 F2
|
|
arc: F0 F5A_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: H00L0100 F3
|
|
arc: H01W0000 F2
|
|
arc: H01W0100 Q4
|
|
arc: LSR1 H02W0501
|
|
arc: M0 E1_H02W0601
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR2 LSR1
|
|
arc: N1_V02N0401 F6
|
|
arc: N3_V06N0103 F2
|
|
arc: S1_V02S0201 F2
|
|
arc: S3_V06S0103 F2
|
|
arc: V01S0000 F6
|
|
arc: V01S0100 F2
|
|
arc: W1_H02W0001 F2
|
|
arc: W1_H02W0601 F6
|
|
arc: W3_H06W0103 F2
|
|
word: SLICEC.K0.INIT 1010111011111100
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000010
|
|
word: SLICEB.K1.INIT 0000000000000010
|
|
word: SLICEB.K0.INIT 0010000000000000
|
|
word: SLICEC.K1.INIT 0000000000000100
|
|
word: SLICED.K0.INIT 1100000000000000
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
|
|
.tile R17C3:PLC2
|
|
arc: E3_H06E0203 W1_H02E0701
|
|
arc: N1_V02N0701 E3_H06W0203
|
|
arc: W1_H02W0101 H01E0101
|
|
arc: W1_H02W0501 E3_H06W0303
|
|
|
|
.tile R17C40:PLC2
|
|
arc: E1_H02E0001 S1_V02N0001
|
|
arc: E1_H02E0101 H01E0101
|
|
arc: E1_H02E0201 S1_V02N0201
|
|
arc: E1_H02E0501 N1_V02S0501
|
|
arc: E1_H02E0601 W1_H02E0601
|
|
arc: H00R0000 W1_H02E0601
|
|
arc: H00R0100 S1_V02N0501
|
|
arc: N1_V02N0001 H01E0001
|
|
arc: N1_V02N0201 S1_V02N0201
|
|
arc: N1_V02N0501 H06E0303
|
|
arc: N1_V02N0601 H06E0303
|
|
arc: S1_V02S0001 N1_V02S0501
|
|
arc: S1_V02S0401 N1_V02S0401
|
|
arc: S1_V02S0501 N1_V02S0501
|
|
arc: S3_V06S0203 N1_V02S0401
|
|
arc: S3_V06S0303 N1_V02S0501
|
|
arc: V00B0000 N1_V02S0001
|
|
arc: V00T0100 N1_V02S0501
|
|
arc: W1_H02W0301 N1_V01S0100
|
|
arc: W1_H02W0501 N1_V02S0501
|
|
arc: W1_H02W0601 N1_V01S0000
|
|
arc: W1_H02W0701 E1_H01W0100
|
|
arc: A1 V01N0101
|
|
arc: B1 E1_H01W0100
|
|
arc: C1 N1_V01S0100
|
|
arc: C2 H02E0601
|
|
arc: C7 V00T0000
|
|
arc: CE1 H02E0101
|
|
arc: CE2 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D1 V02S0201
|
|
arc: D2 H00R0000
|
|
arc: D7 V01N0001
|
|
arc: E1_H01E0001 F0
|
|
arc: E1_H02E0401 Q4
|
|
arc: F0 F5A_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 Q4
|
|
arc: H01W0100 Q2
|
|
arc: LSR0 E1_H02W0501
|
|
arc: LSR1 V00T0100
|
|
arc: M0 V00B0100
|
|
arc: M4 V00B0000
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR0
|
|
arc: S1_V02S0601 Q4
|
|
arc: V00B0100 F7
|
|
arc: V00T0000 Q2
|
|
arc: V01S0000 Q2
|
|
arc: W1_H02W0001 F0
|
|
word: SLICED.K1.INIT 0000000000001111
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000001
|
|
word: SLICEB.K0.INIT 0000000011110000
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R17C41:PLC2
|
|
arc: E1_H01E0001 E3_H06W0003
|
|
arc: E1_H02E0001 E3_H06W0003
|
|
arc: E1_H02E0201 N1_V01S0000
|
|
arc: E1_H02E0401 S1_V02N0401
|
|
arc: E1_H02E0601 V02N0601
|
|
arc: E1_H02E0701 S1_V02N0701
|
|
arc: H00R0000 S1_V02N0601
|
|
arc: H00R0100 V02S0701
|
|
arc: N1_V02N0001 H02W0001
|
|
arc: N1_V02N0401 S1_V02N0401
|
|
arc: N1_V02N0601 S1_V02N0601
|
|
arc: S1_V02S0001 E3_H06W0003
|
|
arc: S1_V02S0401 N1_V01S0000
|
|
arc: S1_V02S0701 E3_H06W0203
|
|
arc: V00B0100 H02W0701
|
|
arc: V00T0000 H02E0201
|
|
arc: W1_H02W0301 S1_V02N0301
|
|
arc: W1_H02W0401 E3_H06W0203
|
|
arc: W1_H02W0601 H01E0001
|
|
arc: A1 S1_V02N0701
|
|
arc: A2 V00B0000
|
|
arc: A3 V00B0000
|
|
arc: B1 S1_V02N0301
|
|
arc: B2 V02S0301
|
|
arc: B3 V02S0301
|
|
arc: C0 H02E0601
|
|
arc: C1 H02E0401
|
|
arc: C2 H00R0100
|
|
arc: C3 H00R0100
|
|
arc: CE0 W1_H02E0101
|
|
arc: CE1 H00R0000
|
|
arc: CE2 V02N0601
|
|
arc: CE3 H02E0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 N1_V02S0201
|
|
arc: D1 V00T0100
|
|
arc: D2 V02N0201
|
|
arc: D3 V02N0201
|
|
arc: E1_H02E0301 Q3
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: H01W0100 Q0
|
|
arc: LSR0 H02E0501
|
|
arc: LSR1 H02E0501
|
|
arc: M2 V00T0000
|
|
arc: M3 H02W0201
|
|
arc: M4 H02W0401
|
|
arc: M6 V00B0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR0
|
|
arc: N1_V02N0201 F2
|
|
arc: S1_V02S0301 Q3
|
|
arc: V00B0000 Q4
|
|
arc: V00T0100 Q3
|
|
arc: V01S0000 F1
|
|
arc: W1_H02W0001 Q0
|
|
arc: W3_H06W0303 Q6
|
|
word: SLICEA.K1.INIT 1100111101000101
|
|
word: SLICEA.K0.INIT 0000111100000000
|
|
word: SLICEB.K0.INIT 1110001011111111
|
|
word: SLICEB.K1.INIT 1111001011110000
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R17C42:PLC2
|
|
arc: H00L0000 H02E0201
|
|
arc: H00R0000 H02E0601
|
|
arc: N1_V02N0101 H06E0103
|
|
arc: V00B0000 S1_V02N0001
|
|
arc: W1_H02W0001 V06N0003
|
|
arc: W1_H02W0401 V02S0401
|
|
arc: W1_H02W0501 S1_V02N0501
|
|
arc: W1_H02W0701 N1_V02S0701
|
|
arc: A0 H00L0000
|
|
arc: A1 H02E0701
|
|
arc: A2 H01E0001
|
|
arc: A3 H01E0001
|
|
arc: B0 S1_V02N0101
|
|
arc: B1 Q1
|
|
arc: B2 H00L0000
|
|
arc: B3 H00L0000
|
|
arc: C0 H00L0100
|
|
arc: C1 H00L0000
|
|
arc: C2 H00R0100
|
|
arc: C3 H00R0100
|
|
arc: CE0 H00R0000
|
|
arc: CE2 V02N0601
|
|
arc: CE3 W1_H02E0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02N0001
|
|
arc: D1 V02N0001
|
|
arc: D2 V02N0001
|
|
arc: D3 V02N0001
|
|
arc: F0 F5A_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: H00L0100 Q1
|
|
arc: H00R0100 Q5
|
|
arc: LSR0 H02W0501
|
|
arc: LSR1 H02W0501
|
|
arc: M0 V00B0000
|
|
arc: M1 W1_H02E0001
|
|
arc: M2 V00B0000
|
|
arc: M5 H02E0001
|
|
arc: M7 E1_H02W0201
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR0
|
|
arc: V01S0000 F2
|
|
arc: W1_H02W0201 F0
|
|
arc: W3_H06W0203 Q7
|
|
word: SLICEA.K0.INIT 1101100011111111
|
|
word: SLICEA.K1.INIT 1010111010101010
|
|
word: SLICEB.K0.INIT 1011100011111111
|
|
word: SLICEB.K1.INIT 1011101010101010
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R17C43:PLC2
|
|
arc: E1_H02E0501 S1_V02N0501
|
|
arc: H00L0000 S1_V02N0001
|
|
arc: N1_V02N0101 S1_V02N0001
|
|
arc: V00T0100 S1_V02N0501
|
|
arc: W1_H02W0501 S1_V02N0501
|
|
arc: A0 W1_H02E0701
|
|
arc: B0 W1_H02E0301
|
|
arc: C0 W1_H02E0401
|
|
arc: CE0 H00L0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02N0001
|
|
arc: E3_H06E0003 Q0
|
|
arc: F0 F0_SLICE
|
|
arc: LSR0 V00T0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
word: SLICEA.K0.INIT 1100111011111010
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R17C44:PLC2
|
|
arc: H00R0000 N1_V02S0401
|
|
arc: W1_H02W0201 V02S0201
|
|
arc: CE0 H02W0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E3_H06E0103 Q1
|
|
arc: LSR1 H02E0501
|
|
arc: M1 H00R0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R17C45:PLC2
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: W1_H02W0101 W3_H06E0103
|
|
|
|
.tile R17C46:PLC2
|
|
arc: N3_V06N0003 H06E0003
|
|
|
|
.tile R17C47:PLC2
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
arc: W3_H06W0203 E3_H06W0203
|
|
|
|
.tile R17C4:PLC2
|
|
arc: W3_H06W0303 E3_H06W0203
|
|
|
|
.tile R17C50:PLC2
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
|
|
.tile R17C51:PLC2
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
|
|
.tile R17C53:PLC2
|
|
arc: W3_H06W0203 E3_H06W0203
|
|
arc: W3_H06W0303 E3_H06W0203
|
|
|
|
.tile R17C55:PLC2
|
|
arc: E1_H02E0501 S1_V02N0501
|
|
arc: V00B0100 E1_H02W0701
|
|
arc: V00T0100 S1_V02N0501
|
|
arc: CE3 E1_H02W0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E3_H06E0303 Q6
|
|
arc: LSR1 V00T0100
|
|
arc: M6 V00B0100
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR3 LSR1
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R17C56:PLC2
|
|
arc: E1_H02E0101 E1_H01W0100
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
arc: H00R0000 H02W0601
|
|
arc: CE3 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E3_H06E0303 Q6
|
|
arc: LSR0 H02E0501
|
|
arc: M6 H02W0401
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR3 LSR0
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R17C57:PLC2
|
|
arc: H01W0100 W3_H06E0303
|
|
arc: V00B0100 S1_V02N0101
|
|
arc: W1_H02W0101 W3_H06E0103
|
|
arc: W1_H02W0401 E1_H02W0401
|
|
arc: W1_H02W0601 W3_H06E0303
|
|
arc: W1_H02W0701 E1_H02W0601
|
|
arc: CE0 H02E0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E3_H06E0003 Q0
|
|
arc: LSR0 W1_H02E0501
|
|
arc: M0 V00B0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R17C59:PLC2
|
|
arc: W1_H02W0401 S3_V06N0203
|
|
arc: W1_H02W0601 S1_V02N0601
|
|
arc: W3_H06W0203 E3_H06W0203
|
|
|
|
.tile R17C61:PLC2
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
|
|
.tile R17C62:PLC2
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
arc: N3_V06N0303 W3_H06E0303
|
|
|
|
.tile R17C63:PLC2
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
|
|
.tile R17C65:PLC2
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
|
|
.tile R17C67:PLC2
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
|
|
.tile R17C68:PLC2
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
|
|
.tile R17C69:PLC2
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
|
|
.tile R17C71:PLC2
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
|
|
.tile R17C73:PLC2
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
|
|
.tile R17C74:PLC2
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
|
|
.tile R17C75:PLC2
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
|
|
.tile R17C77:PLC2
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
|
|
.tile R17C79:PLC2
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
|
|
.tile R17C7:PLC2
|
|
arc: E1_H02E0301 S1_V02N0301
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
|
|
.tile R17C80:PLC2
|
|
arc: E1_H01E0001 W3_H06E0003
|
|
|
|
.tile R17C81:PLC2
|
|
arc: E3_H06E0203 H01E0001
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
|
|
.tile R17C83:PLC2
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
|
|
.tile R17C85:PLC2
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
|
|
.tile R17C87:PLC2
|
|
arc: E1_H02E0501 W3_H06E0303
|
|
arc: E1_H02E0701 W3_H06E0203
|
|
|
|
.tile R17C88:PLC2
|
|
arc: S3_V06S0203 H06E0203
|
|
|
|
.tile R17C8:PLC2
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
|
|
.tile R17C9:PLC2
|
|
arc: E3_H06E0003 W1_H02E0301
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
arc: W3_H06W0303 E1_H01W0100
|
|
|
|
.tile R18C13:PLC2
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
|
|
.tile R18C14:PLC2
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
|
|
.tile R18C19:PLC2
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
|
|
.tile R18C20:PLC2
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
|
|
.tile R18C25:PLC2
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
|
|
.tile R18C26:PLC2
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
|
|
.tile R18C2:PLC2
|
|
arc: N1_V02N0701 E3_H06W0203
|
|
|
|
.tile R18C31:PLC2
|
|
arc: E1_H01E0001 W3_H06E0003
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
|
|
.tile R18C32:PLC2
|
|
arc: E3_H06E0003 H01E0001
|
|
arc: E3_H06E0203 H01E0001
|
|
arc: V00B0000 S1_V02N0001
|
|
arc: V00T0000 S1_V02N0401
|
|
arc: A0 V02N0501
|
|
arc: B0 V00B0000
|
|
arc: C0 V02N0401
|
|
arc: CE0 V02N0201
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 E1_H02W0201
|
|
arc: F0 F0_SLICE
|
|
arc: LSR0 V00T0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: W3_H06W0003 Q0
|
|
word: SLICEA.K0.INIT 1111111000111010
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R18C33:PLC2
|
|
arc: S1_V02S0001 E1_H01W0000
|
|
arc: V00B0000 S1_V02N0201
|
|
arc: V00T0000 E1_H02W0201
|
|
arc: A0 E1_H02W0701
|
|
arc: A2 V00B0000
|
|
arc: B3 V01N0001
|
|
arc: B4 V02N0501
|
|
arc: B5 S1_V02N0501
|
|
arc: B6 H02W0101
|
|
arc: B7 V00T0000
|
|
arc: E1_H01E0001 F7
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: S1_V02S0501 F5
|
|
arc: S1_V02S0601 F4
|
|
arc: V01S0000 F6
|
|
arc: V01S0100 F3
|
|
word: SLICEA.K0.INIT 0000000000001010
|
|
word: SLICEA.K1.INIT 1111111111111111
|
|
word: SLICEB.K0.INIT 0110011001101100
|
|
word: SLICEB.K1.INIT 1100110011000000
|
|
word: SLICEC.K0.INIT 1100110011000000
|
|
word: SLICEC.K1.INIT 1100110011000000
|
|
word: SLICED.K0.INIT 1100110011000000
|
|
word: SLICED.K1.INIT 1100110011000000
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 YES
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
|
|
.tile R18C34:PLC2
|
|
arc: E1_H02E0001 V02N0001
|
|
arc: E1_H02E0301 N1_V02S0301
|
|
arc: E1_H02E0601 H01E0001
|
|
arc: N1_V02N0201 S1_V02N0701
|
|
arc: N1_V02N0501 S1_V02N0401
|
|
arc: N1_V02N0601 S1_V02N0301
|
|
arc: S1_V02S0201 E1_H01W0000
|
|
arc: S1_V02S0601 E1_H01W0000
|
|
arc: V00B0000 V02N0201
|
|
arc: V00T0000 V02N0601
|
|
arc: W1_H02W0101 V01N0101
|
|
arc: B0 V02N0301
|
|
arc: B1 V01N0001
|
|
arc: B2 E1_H01W0100
|
|
arc: CE1 E1_H02W0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0101 F2
|
|
arc: E3_H06E0103 Q2
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: H01W0000 F0
|
|
arc: LSR1 V00B0000
|
|
arc: M2 V00T0000
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXLSR1 LSR1
|
|
arc: V01S0100 F1
|
|
arc: W1_H02W0201 Q2
|
|
word: SLICEA.K0.INIT 1100110011000000
|
|
word: SLICEA.K1.INIT 1100110011000000
|
|
word: SLICEB.K0.INIT 1100110011000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000001110
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R18C35:PLC2
|
|
arc: H00L0100 H02W0301
|
|
arc: H00R0000 V02N0601
|
|
arc: H00R0100 H02W0701
|
|
arc: N1_V02N0601 E1_H02W0601
|
|
arc: N1_V02N0701 H06E0203
|
|
arc: V00B0000 V02N0201
|
|
arc: V00T0100 V02N0701
|
|
arc: W1_H02W0701 V06S0203
|
|
arc: A0 E1_H02W0701
|
|
arc: A1 E1_H02W0701
|
|
arc: A2 V00B0000
|
|
arc: A5 N1_V01N0101
|
|
arc: B1 V00B0000
|
|
arc: B2 H02E0301
|
|
arc: B5 V02N0501
|
|
arc: C0 H02E0601
|
|
arc: C2 E1_H02W0601
|
|
arc: C5 V02N0001
|
|
arc: CE0 H00R0000
|
|
arc: CE1 H00R0100
|
|
arc: CE2 S1_V02N0601
|
|
arc: CE3 S1_V02N0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02N0201
|
|
arc: D1 H01E0101
|
|
arc: D2 S1_V02N0001
|
|
arc: D5 V02N0401
|
|
arc: E1_H02E0101 Q1
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: H01W0000 Q5
|
|
arc: H01W0100 Q1
|
|
arc: LSR0 V00T0100
|
|
arc: LSR1 V00T0100
|
|
arc: M5 H02E0001
|
|
arc: M7 H00L0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR0
|
|
arc: MUXLSR3 LSR1
|
|
arc: N1_V01N0001 F5
|
|
arc: N1_V01N0101 Q7
|
|
arc: S1_V02S0201 Q2
|
|
arc: V01S0000 Q0
|
|
arc: W1_H02W0201 Q0
|
|
word: SLICEC.K1.INIT 0100110001011111
|
|
word: SLICEB.K0.INIT 1100100011111111
|
|
word: SLICEA.K0.INIT 1111000010100000
|
|
word: SLICEA.K1.INIT 1110111000000000
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET SET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET SET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R18C36:PLC2
|
|
arc: E1_H02E0001 N1_V01S0000
|
|
arc: E1_H02E0101 S1_V02N0101
|
|
arc: E1_H02E0701 N1_V01S0100
|
|
arc: H00L0000 V02S0201
|
|
arc: H00R0100 S1_V02N0701
|
|
arc: N1_V02N0201 S1_V02N0701
|
|
arc: N1_V02N0301 E1_H01W0100
|
|
arc: S1_V02S0201 N1_V02S0201
|
|
arc: S1_V02S0501 E1_H01W0100
|
|
arc: V00B0000 S1_V02N0201
|
|
arc: V00B0100 V02N0301
|
|
arc: V00T0100 H02W0101
|
|
arc: W1_H02W0101 E1_H02W0101
|
|
arc: W1_H02W0301 E1_H02W0301
|
|
arc: A1 E1_H01E0001
|
|
arc: A3 E1_H01E0001
|
|
arc: A4 E1_H01W0000
|
|
arc: A5 V00B0000
|
|
arc: B1 V02N0101
|
|
arc: B5 S1_V02N0501
|
|
arc: C1 V02N0401
|
|
arc: C3 V02N0401
|
|
arc: C5 E1_H02W0601
|
|
arc: CE3 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D1 H02W0201
|
|
arc: D3 H02W0201
|
|
arc: D4 S1_V02N0601
|
|
arc: D5 E1_H02W0201
|
|
arc: E1_H01E0001 F4
|
|
arc: E3_H06E0203 Q7
|
|
arc: F0 F5A_SLICE
|
|
arc: F1 FXA_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: H00L0100 F1
|
|
arc: LSR0 V00T0100
|
|
arc: M0 V00B0100
|
|
arc: M1 H00L0000
|
|
arc: M2 V00B0100
|
|
arc: M7 H00L0100
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR3 LSR0
|
|
arc: N1_V01N0001 F5
|
|
arc: W1_H02W0701 F5
|
|
word: SLICEA.K0.INIT 1111111111111111
|
|
word: SLICEA.K1.INIT 1111111111101111
|
|
word: SLICEB.K0.INIT 1111111111111111
|
|
word: SLICEB.K1.INIT 1111111110101111
|
|
word: SLICEC.K1.INIT 0100000000000000
|
|
word: SLICEC.K0.INIT 1010101000000000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET SET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
|
|
.tile R18C37:PLC2
|
|
arc: E1_H02E0001 N1_V01S0000
|
|
arc: E1_H02E0101 V02N0101
|
|
arc: E1_H02E0301 N1_V01S0100
|
|
arc: E1_H02E0501 S1_V02N0501
|
|
arc: E1_H02E0601 N1_V01S0000
|
|
arc: H00L0000 N1_V02S0201
|
|
arc: H00L0100 S1_V02N0101
|
|
arc: H00R0000 V02S0401
|
|
arc: H01W0000 W3_H06E0103
|
|
arc: N1_V02N0001 E1_H01W0000
|
|
arc: N1_V02N0301 V01N0101
|
|
arc: N1_V02N0701 E1_H01W0100
|
|
arc: S1_V02S0101 W1_H02E0101
|
|
arc: V00B0100 S1_V02N0301
|
|
arc: V00T0100 V02N0501
|
|
arc: W1_H02W0101 V02N0101
|
|
arc: W1_H02W0601 S1_V02N0601
|
|
arc: W1_H02W0701 V02S0701
|
|
arc: A0 H00R0000
|
|
arc: A1 F7
|
|
arc: A2 V02N0701
|
|
arc: A5 N1_V01S0100
|
|
arc: A6 F5
|
|
arc: A7 H02E0701
|
|
arc: B0 H01W0100
|
|
arc: B2 H02W0301
|
|
arc: B3 H02E0101
|
|
arc: B6 H02E0101
|
|
arc: B7 V02S0501
|
|
arc: C0 E1_H02W0601
|
|
arc: C1 H00L0000
|
|
arc: C2 V02N0601
|
|
arc: C6 V02N0001
|
|
arc: C7 H02W0401
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V00B0100
|
|
arc: D1 N1_V02S0001
|
|
arc: D2 V02N0001
|
|
arc: D3 V02N0001
|
|
arc: D5 V01N0001
|
|
arc: D6 H00L0100
|
|
arc: D7 H02E0001
|
|
arc: E1_H01E0001 F1
|
|
arc: E1_H02E0201 Q0
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0100 Q0
|
|
arc: M2 V00T0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: N1_V02N0201 Q0
|
|
arc: S3_V06S0303 F5
|
|
arc: V01S0000 F6
|
|
arc: W1_H02W0201 F2
|
|
word: SLICED.K1.INIT 0010000000000000
|
|
word: SLICEA.K1.INIT 1010000000000000
|
|
word: SLICED.K0.INIT 0000000000101010
|
|
word: SLICEA.K0.INIT 0000010001010101
|
|
word: SLICEC.K1.INIT 0000000001010101
|
|
word: SLICEB.K0.INIT 1010100000000000
|
|
word: SLICEB.K1.INIT 1100110000000000
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R18C38:PLC2
|
|
arc: E1_H02E0101 N1_V01S0100
|
|
arc: E1_H02E0201 V02N0201
|
|
arc: H00L0100 H02E0101
|
|
arc: N1_V02N0001 S1_V02N0001
|
|
arc: N1_V02N0101 H02E0101
|
|
arc: N1_V02N0201 H01E0001
|
|
arc: N1_V02N0401 E1_H02W0401
|
|
arc: V00B0000 E1_H02W0401
|
|
arc: V00B0100 H02E0501
|
|
arc: V00T0000 V02S0401
|
|
arc: W1_H02W0101 V01N0101
|
|
arc: W1_H02W0201 N1_V01S0000
|
|
arc: W1_H02W0301 W3_H06E0003
|
|
arc: W1_H02W0401 N1_V02S0401
|
|
arc: A0 H00L0100
|
|
arc: A3 V02N0501
|
|
arc: A4 V02S0101
|
|
arc: B0 H00R0100
|
|
arc: B1 H02E0101
|
|
arc: B3 V01N0001
|
|
arc: B4 H02E0301
|
|
arc: B7 H02E0101
|
|
arc: C0 F4
|
|
arc: C1 F4
|
|
arc: C3 F6
|
|
arc: C4 H01E0001
|
|
arc: C6 V02N0001
|
|
arc: C7 H02W0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02N0201
|
|
arc: D1 V02N0201
|
|
arc: D3 H02E0001
|
|
arc: D4 V00B0000
|
|
arc: D6 H00R0100
|
|
arc: D7 H02E0201
|
|
arc: E1_H01E0001 Q7
|
|
arc: E1_H02E0501 Q7
|
|
arc: F0 F5A_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00R0100 Q7
|
|
arc: H01W0000 Q7
|
|
arc: H01W0100 Q7
|
|
arc: M0 V00T0000
|
|
arc: M2 V00B0100
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 F6
|
|
arc: S1_V02S0001 F2
|
|
arc: S1_V02S0201 F0
|
|
arc: V01S0000 F6
|
|
arc: W1_H02W0601 F6
|
|
word: SLICEA.K0.INIT 0101010001010000
|
|
word: SLICEC.K0.INIT 1000000000000000
|
|
word: SLICEA.K1.INIT 0011001100110000
|
|
word: SLICED.K1.INIT 0011000000000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0100000000000000
|
|
word: SLICED.K0.INIT 0000000000001111
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
|
|
.tile R18C39:PLC2
|
|
arc: E1_H02E0001 V02S0001
|
|
arc: E1_H02E0101 S1_V02N0101
|
|
arc: E1_H02E0401 V06S0203
|
|
arc: E1_H02E0601 V06S0303
|
|
arc: E1_H02E0701 W1_H02E0601
|
|
arc: H00R0100 V02S0701
|
|
arc: N1_V02N0201 W1_H02E0201
|
|
arc: N1_V02N0601 S1_V02N0301
|
|
arc: N1_V02N0701 E1_H01W0100
|
|
arc: V00T0000 H02W0201
|
|
arc: V00T0100 V02N0501
|
|
arc: W1_H02W0601 N1_V01S0000
|
|
arc: A0 H02E0501
|
|
arc: A2 H02W0701
|
|
arc: A3 H02W0701
|
|
arc: A4 V00T0100
|
|
arc: A6 V02N0301
|
|
arc: B2 V02N0101
|
|
arc: B3 V02N0101
|
|
arc: B4 H02W0301
|
|
arc: B5 V02S0501
|
|
arc: B6 H02W0101
|
|
arc: C0 N1_V01S0100
|
|
arc: C2 S1_V02N0601
|
|
arc: C3 S1_V02N0601
|
|
arc: C4 V01N0101
|
|
arc: C5 H01E0001
|
|
arc: C6 S1_V02N0201
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H02E0201
|
|
arc: D2 V00T0100
|
|
arc: D3 V00T0100
|
|
arc: D4 V02S0401
|
|
arc: D5 H00R0100
|
|
arc: D6 E1_H02W0001
|
|
arc: E3_H06E0003 Q0
|
|
arc: F0 F0_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: LSR0 V00B0100
|
|
arc: M2 V00T0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: S1_V02S0001 F2
|
|
arc: S1_V02S0401 F6
|
|
arc: V00B0100 F5
|
|
arc: V01S0100 F4
|
|
word: SLICEC.K0.INIT 1010111100100011
|
|
word: SLICED.K0.INIT 1000110010101111
|
|
word: SLICEC.K1.INIT 1100110011001111
|
|
word: SLICEA.K0.INIT 0000000011111010
|
|
word: SLICEB.K0.INIT 1110111100101111
|
|
word: SLICEB.K1.INIT 1111111100100000
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R18C40:PLC2
|
|
arc: E1_H02E0101 W3_H06E0103
|
|
arc: E1_H02E0201 S1_V02N0201
|
|
arc: E1_H02E0501 V02S0501
|
|
arc: E1_H02E0601 V02N0601
|
|
arc: H00L0100 V02N0301
|
|
arc: H00R0100 V02N0501
|
|
arc: S1_V02S0601 E1_H01W0000
|
|
arc: V00B0000 V02N0201
|
|
arc: V00B0100 H02W0701
|
|
arc: V00T0000 V02S0401
|
|
arc: W1_H02W0201 V02N0201
|
|
arc: A0 H02E0701
|
|
arc: A1 H02E0701
|
|
arc: A4 V02N0101
|
|
arc: A5 H02W0701
|
|
arc: A6 V00T0100
|
|
arc: B4 V00B0100
|
|
arc: B5 H02W0301
|
|
arc: B6 N1_V01S0000
|
|
arc: C0 H02E0601
|
|
arc: C1 H02E0401
|
|
arc: C4 E1_H02W0601
|
|
arc: C5 E1_H02W0601
|
|
arc: C6 N1_V02S0001
|
|
arc: CE0 W1_H02E0101
|
|
arc: CE1 H00R0100
|
|
arc: CE2 H02E0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H02E0001
|
|
arc: D1 H02E0001
|
|
arc: D4 V01N0001
|
|
arc: D5 V01N0001
|
|
arc: D6 H01W0000
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F4 F5C_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: H01W0000 Q0
|
|
arc: H01W0100 Q0
|
|
arc: LSR0 V00T0000
|
|
arc: LSR1 V00T0000
|
|
arc: M3 E1_H02W0201
|
|
arc: M4 V00B0000
|
|
arc: M5 H00L0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR1
|
|
arc: N1_V01N0001 Q1
|
|
arc: N1_V01N0101 Q0
|
|
arc: N3_V06N0103 Q1
|
|
arc: S1_V02S0101 Q3
|
|
arc: S1_V02S0401 F4
|
|
arc: V00T0100 Q1
|
|
arc: W1_H02W0101 Q3
|
|
arc: W1_H02W0301 Q3
|
|
arc: W1_H02W0401 F6
|
|
arc: W1_H02W0701 Q5
|
|
word: SLICED.K0.INIT 0010000000000000
|
|
word: SLICEA.K1.INIT 1111000001010000
|
|
word: SLICEA.K0.INIT 1111000001010000
|
|
word: SLICEC.K0.INIT 1101111110001111
|
|
word: SLICEC.K1.INIT 1011101010101010
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R18C41:PLC2
|
|
arc: E1_H02E0601 S1_V02N0601
|
|
arc: H00R0000 H02E0601
|
|
arc: H00R0100 S1_V02N0501
|
|
arc: N1_V02N0101 S1_V02N0001
|
|
arc: N1_V02N0201 S1_V02N0701
|
|
arc: N1_V02N0601 S1_V02N0601
|
|
arc: V00B0000 S1_V02N0201
|
|
arc: V00B0100 V02N0101
|
|
arc: V00T0000 V02S0401
|
|
arc: W1_H02W0001 V02S0001
|
|
arc: W1_H02W0301 N1_V02S0301
|
|
arc: W1_H02W0701 E3_H06W0203
|
|
arc: A1 H00R0000
|
|
arc: A2 H00L0100
|
|
arc: A3 V00T0000
|
|
arc: B1 H02E0101
|
|
arc: B2 N1_V02S0301
|
|
arc: B3 Q3
|
|
arc: C1 N1_V02S0401
|
|
arc: C2 H02W0601
|
|
arc: C3 H02W0601
|
|
arc: CE1 H00R0100
|
|
arc: CE2 V02N0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D1 N1_V01S0000
|
|
arc: D2 S1_V02N0001
|
|
arc: D3 S1_V02N0001
|
|
arc: F0 F5A_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: H00L0000 F2
|
|
arc: H00L0100 Q3
|
|
arc: H01W0000 Q5
|
|
arc: LSR0 E1_H02W0501
|
|
arc: LSR1 H02E0501
|
|
arc: M0 V00B0000
|
|
arc: M2 V00B0100
|
|
arc: M3 H02E0201
|
|
arc: M5 H00L0000
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR1
|
|
arc: N1_V02N0501 Q5
|
|
arc: V01S0000 F0
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000100100000000
|
|
word: SLICEB.K0.INIT 1110111100101111
|
|
word: SLICEB.K1.INIT 1111111101000000
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R18C42:PLC2
|
|
arc: E1_H02E0001 S1_V02N0001
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
arc: N1_V02N0001 S1_V02N0501
|
|
arc: N1_V02N0601 H02E0601
|
|
arc: W1_H02W0201 N1_V01S0000
|
|
arc: W1_H02W0601 S1_V02N0601
|
|
|
|
.tile R18C43:PLC2
|
|
arc: N1_V02N0001 H02E0001
|
|
arc: W1_H02W0501 V02N0501
|
|
|
|
.tile R18C44:PLC2
|
|
arc: S1_V02S0301 V01N0101
|
|
|
|
.tile R18C45:PLC2
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
|
|
.tile R18C47:PLC2
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
|
|
.tile R18C48:PLC2
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
|
|
.tile R18C51:PLC2
|
|
arc: N3_V06N0003 W3_H06E0003
|
|
|
|
.tile R18C53:PLC2
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
|
|
.tile R18C54:PLC2
|
|
arc: N3_V06N0303 W3_H06E0303
|
|
arc: S1_V02S0701 V01N0101
|
|
|
|
.tile R18C59:PLC2
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
|
|
.tile R18C65:PLC2
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
|
|
.tile R18C71:PLC2
|
|
arc: W3_H06W0303 E3_H06W0203
|
|
|
|
.tile R18C77:PLC2
|
|
arc: W3_H06W0203 E3_H06W0203
|
|
|
|
.tile R18C7:PLC2
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
|
|
.tile R18C83:PLC2
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
|
|
.tile R18C8:PLC2
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
|
|
.tile R19C10:PLC2
|
|
arc: S3_V06S0103 H06W0103
|
|
|
|
.tile R19C13:PLC2
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
|
|
.tile R19C14:PLC2
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
|
|
.tile R19C19:PLC2
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
|
|
.tile R19C20:PLC2
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
|
|
.tile R19C25:PLC2
|
|
arc: E1_H02E0101 S1_V02N0101
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: N1_V02N0301 N3_V06S0003
|
|
arc: N1_V02N0401 W3_H06E0203
|
|
arc: S1_V02S0301 N3_V06S0003
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
|
|
.tile R19C26:PLC2
|
|
arc: N1_V02N0101 H02E0101
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
|
|
.tile R19C27:PLC2
|
|
arc: V01S0000 N3_V06S0103
|
|
|
|
.tile R19C28:PLC2
|
|
arc: S1_V02S0101 N3_V06S0103
|
|
|
|
.tile R19C2:PLC2
|
|
arc: N1_V02N0001 S1_V02N0001
|
|
arc: N1_V02N0701 E3_H06W0203
|
|
|
|
.tile R19C30:PLC2
|
|
arc: E1_H02E0701 E3_H06W0203
|
|
|
|
.tile R19C31:PLC2
|
|
arc: E1_H01E0101 W3_H06E0203
|
|
arc: E1_H02E0501 S3_V06N0303
|
|
arc: E1_H02E0701 W3_H06E0203
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
arc: H00R0000 H02W0401
|
|
arc: S1_V02S0201 N3_V06S0103
|
|
arc: V00B0000 V02N0001
|
|
arc: V01S0000 N3_V06S0103
|
|
arc: V01S0100 N3_V06S0303
|
|
arc: A0 S1_V02N0701
|
|
arc: A2 H02E0701
|
|
arc: B0 V02N0301
|
|
arc: B2 H00R0000
|
|
arc: C0 H02W0401
|
|
arc: C2 V02N0401
|
|
arc: CE0 E1_H02W0101
|
|
arc: CE1 E1_H02W0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02N0201
|
|
arc: D2 V01S0100
|
|
arc: F0 F0_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: LSR0 V00B0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR0
|
|
arc: N3_V06N0003 Q0
|
|
arc: W3_H06W0103 Q2
|
|
word: SLICEA.K0.INIT 1010111011111100
|
|
word: SLICEB.K0.INIT 1011111110101100
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R19C32:PLC2
|
|
arc: E3_H06E0303 H01E0101
|
|
arc: N1_V02N0201 H06W0103
|
|
arc: N1_V02N0401 E3_H06W0203
|
|
arc: N1_V02N0501 H02E0501
|
|
arc: S1_V02S0201 H06W0103
|
|
arc: S1_V02S0401 E3_H06W0203
|
|
arc: V00T0000 V02N0401
|
|
arc: W1_H02W0401 E3_H06W0203
|
|
arc: A0 H02W0701
|
|
arc: B0 V02N0301
|
|
arc: C0 V02N0601
|
|
arc: CE0 E1_H02W0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02N0001
|
|
arc: F0 F0_SLICE
|
|
arc: LSR1 V00T0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: W3_H06W0003 Q0
|
|
word: SLICEA.K0.INIT 1110110010100000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R19C33:PLC2
|
|
arc: E1_H02E0301 N1_V02S0301
|
|
arc: E1_H02E0401 N1_V01S0000
|
|
arc: E1_H02E0601 V02S0601
|
|
arc: H00L0000 N1_V02S0001
|
|
arc: H00R0000 E1_H02W0601
|
|
arc: N1_V02N0501 E1_H01W0100
|
|
arc: S1_V02S0001 N1_V02S0001
|
|
arc: S1_V02S0401 E1_H02W0401
|
|
arc: S1_V02S0701 W1_H02E0701
|
|
arc: V00B0000 H02W0401
|
|
arc: V00T0000 H02W0201
|
|
arc: W1_H02W0101 E1_H02W0101
|
|
arc: W1_H02W0701 N3_V06S0203
|
|
arc: B0 E1_H02W0301
|
|
arc: B2 E1_H02W0301
|
|
arc: B4 V02S0501
|
|
arc: C0 H00L0000
|
|
arc: C2 N1_V01S0100
|
|
arc: C4 N1_V02S0001
|
|
arc: CE0 H00R0000
|
|
arc: CE1 H00R0000
|
|
arc: CE2 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02S0001
|
|
arc: D2 N1_V02S0001
|
|
arc: D4 E1_H02W0201
|
|
arc: E1_H01E0101 Q0
|
|
arc: E3_H06E0003 Q0
|
|
arc: F0 F0_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: LSR0 V00B0000
|
|
arc: LSR1 V00T0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR0
|
|
arc: N1_V01N0001 Q2
|
|
arc: V01S0100 Q4
|
|
word: SLICEB.K0.INIT 1111000011000000
|
|
word: SLICEA.K0.INIT 1111110000000000
|
|
word: SLICEC.K0.INIT 1100110011000000
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R19C34:PLC2
|
|
arc: E1_H02E0601 V02N0601
|
|
arc: E1_H02E0701 N3_V06S0203
|
|
arc: H00R0000 H02W0601
|
|
arc: N1_V02N0001 S1_V02N0501
|
|
arc: N1_V02N0201 N3_V06S0103
|
|
arc: N1_V02N0301 H01E0101
|
|
arc: N1_V02N0401 N3_V06S0203
|
|
arc: N1_V02N0701 E1_H01W0100
|
|
arc: S1_V02S0001 H06W0003
|
|
arc: S1_V02S0101 N3_V06S0103
|
|
arc: S1_V02S0201 N3_V06S0103
|
|
arc: S1_V02S0301 S3_V06N0003
|
|
arc: S1_V02S0601 H06W0303
|
|
arc: S1_V02S0701 N3_V06S0203
|
|
arc: S3_V06S0103 N3_V06S0103
|
|
arc: S3_V06S0203 N3_V06S0203
|
|
arc: V00B0100 H02W0701
|
|
arc: V00T0000 H02W0201
|
|
arc: V00T0100 H02E0301
|
|
arc: W1_H02W0101 V01N0101
|
|
arc: W1_H02W0201 N3_V06S0103
|
|
arc: W1_H02W0401 N3_V06S0203
|
|
arc: A4 S1_V02N0101
|
|
arc: A5 S1_V02N0101
|
|
arc: B0 H02E0301
|
|
arc: B2 H02E0301
|
|
arc: B3 H02W0301
|
|
arc: B4 S1_V02N0501
|
|
arc: B5 S1_V02N0501
|
|
arc: C0 N1_V01S0100
|
|
arc: C2 H02E0401
|
|
arc: C3 H02E0601
|
|
arc: C4 V02S0201
|
|
arc: C5 E1_H02W0401
|
|
arc: CE0 H00R0000
|
|
arc: CE1 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H02W0201
|
|
arc: D2 H02W0201
|
|
arc: D3 V00T0100
|
|
arc: D4 E1_H02W0001
|
|
arc: D5 V02S0601
|
|
arc: E1_H02E0001 Q0
|
|
arc: F0 F0_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F5C_SLICE
|
|
arc: H01W0100 Q3
|
|
arc: LSR0 V00B0100
|
|
arc: M4 V00T0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR0
|
|
arc: N1_V01N0001 Q0
|
|
arc: N1_V01N0101 Q2
|
|
arc: N1_V02N0601 F4
|
|
word: SLICEA.K0.INIT 1111000011000000
|
|
word: SLICEB.K1.INIT 1111000011000000
|
|
word: SLICEB.K0.INIT 1111000011000000
|
|
word: SLICEC.K0.INIT 1101100011111111
|
|
word: SLICEC.K1.INIT 1101110011001100
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R19C35:PLC2
|
|
arc: E1_H02E0001 N1_V02S0001
|
|
arc: E1_H02E0101 V02N0101
|
|
arc: E1_H02E0201 V02S0201
|
|
arc: E1_H02E0601 N1_V01S0000
|
|
arc: E1_H02E0701 V06N0203
|
|
arc: H00L0000 E1_H02W0201
|
|
arc: H00R0100 N1_V02S0701
|
|
arc: N1_V02N0001 S1_V02N0501
|
|
arc: N1_V02N0201 E1_H02W0201
|
|
arc: N1_V02N0301 S1_V02N0201
|
|
arc: N1_V02N0401 H06W0203
|
|
arc: N1_V02N0501 E1_H02W0501
|
|
arc: N1_V02N0701 H02E0701
|
|
arc: S1_V02S0401 H06W0203
|
|
arc: S1_V02S0501 E1_H02W0501
|
|
arc: S1_V02S0601 H06W0303
|
|
arc: S1_V02S0701 H02E0701
|
|
arc: W1_H02W0101 E1_H02W0101
|
|
arc: W1_H02W0201 E1_H02W0201
|
|
arc: W1_H02W0301 E1_H02W0201
|
|
arc: W1_H02W0401 E1_H02W0101
|
|
arc: W1_H02W0701 V02N0701
|
|
arc: W3_H06W0103 E1_H02W0101
|
|
arc: A1 F5
|
|
arc: A3 F5
|
|
arc: A4 E1_H02W0701
|
|
arc: A6 E1_H02W0501
|
|
arc: B1 E1_H01W0100
|
|
arc: B4 H00L0000
|
|
arc: C1 E1_H01W0000
|
|
arc: C3 E1_H01W0000
|
|
arc: C4 H02W0601
|
|
arc: C5 H02E0601
|
|
arc: C6 V02N0201
|
|
arc: D1 S1_V02N0201
|
|
arc: D3 H02W0201
|
|
arc: D4 E1_H02W0001
|
|
arc: D5 V02N0401
|
|
arc: D6 H02W0001
|
|
arc: F0 F5A_SLICE
|
|
arc: F1 FXA_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: H01W0100 F6
|
|
arc: M0 E1_H02W0601
|
|
arc: M1 H00R0100
|
|
arc: M2 E1_H02W0601
|
|
arc: N1_V02N0601 F4
|
|
arc: S1_V02S0301 F1
|
|
arc: V01S0000 F6
|
|
arc: V01S0100 F4
|
|
arc: W1_H02W0601 F4
|
|
word: SLICED.K0.INIT 0000000000000101
|
|
word: SLICEA.K0.INIT 1111111111111111
|
|
word: SLICEA.K1.INIT 1111111111111011
|
|
word: SLICEB.K0.INIT 1111111111111111
|
|
word: SLICEB.K1.INIT 1111101011111111
|
|
word: SLICEC.K0.INIT 0111000000000000
|
|
word: SLICEC.K1.INIT 1111000000000000
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
|
|
.tile R19C36:PLC2
|
|
arc: E1_H02E0001 V02N0001
|
|
arc: E1_H02E0101 W1_H02E0001
|
|
arc: E1_H02E0401 V02N0401
|
|
arc: E1_H02E0501 V01N0101
|
|
arc: E1_H02E0601 V01N0001
|
|
arc: H00L0000 H02W0201
|
|
arc: H00R0000 H02W0401
|
|
arc: H00R0100 E1_H02W0701
|
|
arc: N1_V02N0001 S1_V02N0001
|
|
arc: N1_V02N0101 S1_V02N0001
|
|
arc: N1_V02N0201 H02W0201
|
|
arc: N1_V02N0301 E1_H01W0100
|
|
arc: N1_V02N0501 E1_H02W0501
|
|
arc: N1_V02N0601 E1_H01W0000
|
|
arc: N1_V02N0701 S1_V02N0601
|
|
arc: S1_V02S0001 E1_H02W0001
|
|
arc: S1_V02S0101 H02W0101
|
|
arc: V00B0000 V02S0201
|
|
arc: V00B0100 H02W0701
|
|
arc: V00T0000 H02W0201
|
|
arc: W1_H02W0001 V01N0001
|
|
arc: W1_H02W0401 V01N0001
|
|
arc: A0 S1_V02N0701
|
|
arc: A2 F7
|
|
arc: A3 F7
|
|
arc: A4 F7
|
|
arc: A5 F7
|
|
arc: B0 H02E0101
|
|
arc: B1 V02N0101
|
|
arc: B2 H02E0101
|
|
arc: B3 V02N0101
|
|
arc: B4 H02E0101
|
|
arc: B5 H02E0101
|
|
arc: B6 V02S0501
|
|
arc: B7 V02S0501
|
|
arc: C0 W1_H02E0601
|
|
arc: C2 H00L0000
|
|
arc: C3 H00L0000
|
|
arc: C4 V00T0000
|
|
arc: C5 V00T0000
|
|
arc: C6 E1_H02W0601
|
|
arc: C7 V02N0201
|
|
arc: CE3 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H02W0201
|
|
arc: D1 H02W0201
|
|
arc: D2 H02E0201
|
|
arc: D3 H02E0201
|
|
arc: D4 H02E0001
|
|
arc: D5 H02E0001
|
|
arc: D6 S1_V02N0601
|
|
arc: D7 N1_V02S0601
|
|
arc: E1_H02E0701 Q7
|
|
arc: F0 F5A_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F4 F5C_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 F0
|
|
arc: H01W0100 F2
|
|
arc: LSR1 V00B0000
|
|
arc: M0 V00B0100
|
|
arc: M2 V00B0100
|
|
arc: M4 V00B0100
|
|
arc: M7 H00R0000
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR3 LSR1
|
|
arc: N1_V02N0401 F4
|
|
arc: V01S0100 Q7
|
|
arc: W1_H02W0201 F2
|
|
arc: W1_H02W0601 F6
|
|
arc: W3_H06W0203 Q7
|
|
word: SLICED.K0.INIT 0011000000000000
|
|
word: SLICEA.K0.INIT 1100100000000000
|
|
word: SLICEA.K1.INIT 1100110000000000
|
|
word: SLICEB.K1.INIT 1000101011001111
|
|
word: SLICEB.K0.INIT 1000101011111111
|
|
word: SLICEC.K1.INIT 1000101011001111
|
|
word: SLICED.K1.INIT 0000000000000011
|
|
word: SLICEC.K0.INIT 1000101011111111
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R19C37:PLC2
|
|
arc: E1_H02E0101 N3_V06S0103
|
|
arc: E1_H02E0401 E1_H01W0000
|
|
arc: E1_H02E0701 N1_V02S0701
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
arc: N1_V02N0101 N3_V06S0103
|
|
arc: N1_V02N0201 E1_H02W0201
|
|
arc: N1_V02N0401 S1_V02N0101
|
|
arc: N1_V02N0601 S3_V06N0303
|
|
arc: N1_V02N0701 W1_H02E0701
|
|
arc: N3_V06N0303 E1_H01W0100
|
|
arc: S1_V02S0001 H06W0003
|
|
arc: S1_V02S0301 N3_V06S0003
|
|
arc: S1_V02S0601 E1_H01W0000
|
|
arc: S3_V06S0103 N3_V06S0103
|
|
arc: V00B0000 S1_V02N0001
|
|
arc: W1_H02W0001 N1_V01S0000
|
|
arc: W1_H02W0401 S1_V02N0401
|
|
arc: W3_H06W0303 E1_H01W0100
|
|
arc: A0 V01N0101
|
|
arc: A1 V01N0101
|
|
arc: A2 F7
|
|
arc: A4 V02N0101
|
|
arc: A5 V02S0101
|
|
arc: A6 F5
|
|
arc: A7 F5
|
|
arc: B0 H00R0100
|
|
arc: B2 S1_V02N0301
|
|
arc: B3 V01N0001
|
|
arc: B5 H02E0101
|
|
arc: B6 S1_V02N0701
|
|
arc: B7 W1_H02E0101
|
|
arc: C0 V02N0401
|
|
arc: C1 H00R0100
|
|
arc: C2 N1_V02S0401
|
|
arc: C3 F6
|
|
arc: C4 H02E0401
|
|
arc: C5 W1_H02E0601
|
|
arc: C6 V00T0000
|
|
arc: C7 V00T0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02N0201
|
|
arc: D1 V02N0001
|
|
arc: D2 N1_V02S0001
|
|
arc: D3 H02E0001
|
|
arc: D4 N1_V02S0601
|
|
arc: D5 E1_H02W0001
|
|
arc: E1_H01E0001 F0
|
|
arc: E1_H01E0101 F3
|
|
arc: E1_H02E0201 Q2
|
|
arc: E1_H02E0501 Q7
|
|
arc: E1_H02E0601 F6
|
|
arc: E3_H06E0003 F3
|
|
arc: E3_H06E0103 Q2
|
|
arc: F0 F5A_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00R0100 Q7
|
|
arc: H01W0000 F5
|
|
arc: H01W0100 F4
|
|
arc: M0 V00B0000
|
|
arc: M7 H02W0201
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q7
|
|
arc: N1_V01N0101 F5
|
|
arc: N1_V02N0001 Q2
|
|
arc: N1_V02N0501 F5
|
|
arc: N3_V06N0003 F3
|
|
arc: N3_V06N0103 Q2
|
|
arc: S1_V02S0101 F3
|
|
arc: S1_V02S0201 Q2
|
|
arc: S1_V02S0501 Q7
|
|
arc: S1_V02S0701 F5
|
|
arc: S3_V06S0003 F3
|
|
arc: V00T0000 Q2
|
|
arc: V01S0000 Q7
|
|
arc: V01S0100 Q2
|
|
arc: W1_H02W0101 F3
|
|
arc: W1_H02W0201 Q2
|
|
arc: W1_H02W0501 Q7
|
|
arc: W1_H02W0601 F4
|
|
arc: W1_H02W0701 F5
|
|
arc: W3_H06W0003 F0
|
|
word: SLICEA.K0.INIT 0000111100001011
|
|
word: SLICEA.K1.INIT 1111111110101111
|
|
word: SLICED.K1.INIT 0001000000010000
|
|
word: SLICEB.K0.INIT 0000101100001010
|
|
word: SLICEC.K0.INIT 0000010101010101
|
|
word: SLICEC.K1.INIT 1000000000000000
|
|
word: SLICED.K0.INIT 1110000011100000
|
|
word: SLICEB.K1.INIT 0000000000001100
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R19C38:PLC2
|
|
arc: E1_H02E0101 H01E0101
|
|
arc: E1_H02E0201 W1_H02E0701
|
|
arc: E1_H02E0301 N3_V06S0003
|
|
arc: E1_H02E0401 V06N0203
|
|
arc: E1_H02E0601 H01E0001
|
|
arc: E1_H02E0701 N1_V02S0701
|
|
arc: E3_H06E0103 H01E0101
|
|
arc: N1_V02N0101 H01E0101
|
|
arc: N1_V02N0201 S1_V02N0201
|
|
arc: N1_V02N0501 W1_H02E0501
|
|
arc: N1_V02N0601 H02E0601
|
|
arc: S1_V02S0101 H01E0101
|
|
arc: S1_V02S0201 N1_V01S0000
|
|
arc: S1_V02S0601 W3_H06E0303
|
|
arc: S3_V06S0003 N3_V06S0303
|
|
arc: S3_V06S0303 N3_V06S0303
|
|
arc: V00B0100 V02N0301
|
|
arc: W1_H02W0001 N3_V06S0003
|
|
arc: W1_H02W0201 V02S0201
|
|
arc: W1_H02W0601 N1_V01S0000
|
|
arc: A5 H02E0501
|
|
arc: B0 H02E0101
|
|
arc: C0 H02E0601
|
|
arc: C5 E1_H01E0101
|
|
arc: C7 W1_H02E0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V00B0100
|
|
arc: D5 V02N0401
|
|
arc: D7 H02E0201
|
|
arc: E1_H01E0001 F7
|
|
arc: E1_H01E0101 F7
|
|
arc: E1_H02E0501 F5
|
|
arc: E3_H06E0203 F7
|
|
arc: E3_H06E0303 F5
|
|
arc: F0 F0_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 F5
|
|
arc: H01W0100 F7
|
|
arc: MUXCLK0 CLK0
|
|
arc: N1_V01N0001 F7
|
|
arc: N1_V01N0101 F5
|
|
arc: N1_V02N0001 Q0
|
|
arc: N3_V06N0303 F5
|
|
arc: S1_V02S0501 F7
|
|
arc: S1_V02S0701 F5
|
|
arc: S3_V06S0203 F7
|
|
arc: V01S0000 Q0
|
|
arc: V01S0100 F7
|
|
arc: W1_H02W0501 F7
|
|
arc: W1_H02W0701 F5
|
|
arc: W3_H06W0203 F7
|
|
arc: W3_H06W0303 F5
|
|
word: SLICEC.K1.INIT 1010111100000000
|
|
word: SLICEA.K0.INIT 0011000000000000
|
|
word: SLICED.K1.INIT 0000000000001111
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
|
|
.tile R19C39:PLC2
|
|
arc: E1_H02E0101 V02N0101
|
|
arc: E1_H02E0401 W1_H02E0101
|
|
arc: E1_H02E0601 H01E0001
|
|
arc: H00L0000 V02S0001
|
|
arc: H00L0100 E1_H02W0301
|
|
arc: H00R0000 W1_H02E0401
|
|
arc: H00R0100 H02E0701
|
|
arc: N1_V02N0001 H01E0001
|
|
arc: N1_V02N0101 E1_H02W0101
|
|
arc: N1_V02N0301 H02E0301
|
|
arc: N1_V02N0501 H02W0501
|
|
arc: S1_V02S0001 H01E0001
|
|
arc: S1_V02S0101 W1_H02E0101
|
|
arc: V00B0000 V02N0001
|
|
arc: V00T0000 H02W0001
|
|
arc: W1_H02W0001 W3_H06E0003
|
|
arc: A0 W1_H02E0701
|
|
arc: A2 F7
|
|
arc: A3 H00L0100
|
|
arc: A4 H02W0701
|
|
arc: A5 E1_H02W0501
|
|
arc: A7 N1_V01S0100
|
|
arc: B0 H02W0101
|
|
arc: B2 V01N0001
|
|
arc: B3 H02E0301
|
|
arc: B4 F3
|
|
arc: B5 V02N0501
|
|
arc: B7 S1_V02N0501
|
|
arc: C0 H02E0601
|
|
arc: C2 F4
|
|
arc: C3 H02W0601
|
|
arc: C4 E1_H02W0401
|
|
arc: C5 H02E0401
|
|
arc: CE1 H00R0100
|
|
arc: CE2 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 N1_V02S0201
|
|
arc: D1 H02W0001
|
|
arc: D2 E1_H02W0001
|
|
arc: D3 H02E0201
|
|
arc: D4 E1_H01W0100
|
|
arc: D5 E1_H02W0201
|
|
arc: D7 V02S0401
|
|
arc: F0 F5A_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: LSR1 V00T0000
|
|
arc: M0 V00B0000
|
|
arc: M5 H00L0000
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR1
|
|
arc: N1_V01N0101 Q5
|
|
arc: N1_V02N0201 F0
|
|
arc: S1_V02S0501 F5
|
|
arc: V01S0000 Q5
|
|
arc: W1_H02W0201 Q2
|
|
word: SLICEB.K1.INIT 1111010100110001
|
|
word: SLICED.K1.INIT 1000100000000000
|
|
word: SLICEC.K1.INIT 1111010100110001
|
|
word: SLICEC.K0.INIT 1000000000000000
|
|
word: SLICEB.K0.INIT 1000000000000000
|
|
word: SLICEA.K0.INIT 0000001100100011
|
|
word: SLICEA.K1.INIT 0000000011111111
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R19C3:PLC2
|
|
arc: W1_H02W0701 V02N0701
|
|
|
|
.tile R19C40:PLC2
|
|
arc: E1_H02E0001 N1_V02S0001
|
|
arc: E1_H02E0301 V06N0003
|
|
arc: E1_H02E0501 W1_H02E0501
|
|
arc: E1_H02E0601 V01N0001
|
|
arc: H00L0100 S1_V02N0101
|
|
arc: H00R0100 W1_H02E0501
|
|
arc: N1_V02N0001 E3_H06W0003
|
|
arc: N1_V02N0101 H02W0101
|
|
arc: N1_V02N0201 H06E0103
|
|
arc: N1_V02N0301 N3_V06S0003
|
|
arc: N1_V02N0501 W1_H02E0501
|
|
arc: N1_V02N0601 S3_V06N0303
|
|
arc: S1_V02S0001 N1_V02S0001
|
|
arc: S1_V02S0201 H06E0103
|
|
arc: S1_V02S0501 H06E0303
|
|
arc: S3_V06S0003 N1_V02S0001
|
|
arc: V00B0000 N1_V02S0001
|
|
arc: V00T0000 V02S0401
|
|
arc: V00T0100 S1_V02N0701
|
|
arc: V01S0100 N3_V06S0303
|
|
arc: W1_H02W0001 N1_V02S0001
|
|
arc: W1_H02W0101 V02N0101
|
|
arc: W1_H02W0501 N3_V06S0303
|
|
arc: W1_H02W0601 N1_V02S0601
|
|
arc: W3_H06W0003 E1_H01W0000
|
|
arc: A0 H02W0701
|
|
arc: A1 H00L0000
|
|
arc: A2 F7
|
|
arc: A5 E1_H02W0701
|
|
arc: A7 S1_V02N0101
|
|
arc: B0 V02S0101
|
|
arc: B1 S1_V02N0101
|
|
arc: B5 V02N0501
|
|
arc: B7 V02N0701
|
|
arc: C0 H02E0601
|
|
arc: C1 H02E0601
|
|
arc: C2 V02S0601
|
|
arc: C5 V02N0201
|
|
arc: C7 E1_H01E0101
|
|
arc: CE0 W1_H02E0101
|
|
arc: CE1 H00R0100
|
|
arc: CE2 H02E0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02N0001
|
|
arc: D1 V02N0001
|
|
arc: D2 V02N0201
|
|
arc: D5 V02S0601
|
|
arc: D7 S1_V02N0601
|
|
arc: E1_H01E0101 Q2
|
|
arc: E3_H06E0003 Q0
|
|
arc: E3_H06E0103 Q1
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00L0000 Q2
|
|
arc: H01W0100 F2
|
|
arc: LSR0 V00B0000
|
|
arc: LSR1 V00T0100
|
|
arc: M2 V00T0000
|
|
arc: M5 H00L0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR1
|
|
arc: N1_V01N0001 Q5
|
|
arc: V01S0000 Q2
|
|
arc: W1_H02W0701 F5
|
|
word: SLICEA.K0.INIT 1100111011111010
|
|
word: SLICEA.K1.INIT 1010111011111100
|
|
word: SLICED.K1.INIT 1000110010101111
|
|
word: SLICEB.K0.INIT 1010101000001010
|
|
word: SLICEC.K1.INIT 1101110100001101
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R19C41:PLC2
|
|
arc: E1_H01E0001 E3_H06W0003
|
|
arc: E1_H01E0101 E3_H06W0203
|
|
arc: E1_H02E0101 V02N0101
|
|
arc: E1_H02E0501 W1_H02E0401
|
|
arc: H00R0000 V02N0601
|
|
arc: H00R0100 H02E0501
|
|
arc: N1_V02N0101 E1_H02W0101
|
|
arc: N1_V02N0301 S3_V06N0003
|
|
arc: N1_V02N0401 H06E0203
|
|
arc: N1_V02N0601 H06E0303
|
|
arc: N1_V02N0701 E3_H06W0203
|
|
arc: N3_V06N0103 S3_V06N0003
|
|
arc: S1_V02S0101 E1_H02W0101
|
|
arc: S1_V02S0501 N3_V06S0303
|
|
arc: S3_V06S0303 N3_V06S0203
|
|
arc: V00B0000 W1_H02E0401
|
|
arc: V00T0000 H02E0001
|
|
arc: V00T0100 E1_H02W0101
|
|
arc: W1_H02W0101 V06N0103
|
|
arc: W1_H02W0201 E1_H01W0000
|
|
arc: W1_H02W0301 S3_V06N0003
|
|
arc: W1_H02W0401 N1_V01S0000
|
|
arc: W1_H02W0701 N1_V02S0701
|
|
arc: A1 E1_H01E0001
|
|
arc: A2 H02W0501
|
|
arc: A3 V02N0701
|
|
arc: A4 N1_V02S0301
|
|
arc: A6 S1_V02N0301
|
|
arc: B1 S1_V02N0101
|
|
arc: B2 H02E0301
|
|
arc: B3 H02E0301
|
|
arc: B4 S1_V02N0701
|
|
arc: B6 H02E0301
|
|
arc: C1 F4
|
|
arc: C2 H00L0100
|
|
arc: C3 H00L0100
|
|
arc: C4 E1_H01E0101
|
|
arc: C6 V01N0101
|
|
arc: CE0 H00R0000
|
|
arc: CE3 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D1 V01S0100
|
|
arc: D2 S1_V02N0001
|
|
arc: D3 S1_V02N0001
|
|
arc: D4 V01N0001
|
|
arc: D6 H01W0000
|
|
arc: F0 F5A_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: H00L0000 F2
|
|
arc: H00L0100 Q1
|
|
arc: H01W0000 Q7
|
|
arc: LSR0 V00T0000
|
|
arc: LSR1 V00B0000
|
|
arc: M0 H02E0601
|
|
arc: M1 E1_H02W0001
|
|
arc: M2 V00T0100
|
|
arc: M7 H00L0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR3 LSR0
|
|
arc: V01S0100 F6
|
|
arc: W1_H02W0001 F0
|
|
arc: W1_H02W0501 Q7
|
|
word: SLICED.K0.INIT 1111010100110001
|
|
word: SLICEC.K0.INIT 1100010011110101
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 1001000000000000
|
|
word: SLICEB.K0.INIT 1101110111110101
|
|
word: SLICEB.K1.INIT 1100110011101100
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R19C42:PLC2
|
|
arc: E1_H02E0001 V02N0001
|
|
arc: E1_H02E0601 V02N0601
|
|
arc: H00L0100 V02N0101
|
|
arc: H00R0100 W1_H02E0501
|
|
arc: N1_V02N0001 E1_H01W0000
|
|
arc: N1_V02N0101 H01E0101
|
|
arc: N1_V02N0501 H02E0501
|
|
arc: V00B0100 E1_H02W0501
|
|
arc: V00T0100 H02W0101
|
|
arc: W1_H02W0501 V02N0501
|
|
arc: A0 V02N0701
|
|
arc: A2 E1_H02W0501
|
|
arc: A3 E1_H02W0501
|
|
arc: B0 V01N0001
|
|
arc: B2 V02N0301
|
|
arc: B3 V02N0301
|
|
arc: C0 V02N0601
|
|
arc: C2 V02N0601
|
|
arc: C3 V02N0601
|
|
arc: CE0 H02E0101
|
|
arc: CE2 H00L0100
|
|
arc: CE3 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02N0001
|
|
arc: D2 H00R0000
|
|
arc: D3 H00R0000
|
|
arc: E1_H02E0701 Q7
|
|
arc: F0 F0_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: H00L0000 F2
|
|
arc: H00R0000 Q4
|
|
arc: H01W0000 Q7
|
|
arc: LSR0 H02W0501
|
|
arc: LSR1 H02W0501
|
|
arc: M2 V00T0100
|
|
arc: M4 V00B0100
|
|
arc: M7 H00L0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR2 LSR0
|
|
arc: MUXLSR3 LSR1
|
|
arc: N3_V06N0003 Q0
|
|
arc: W1_H02W0701 Q7
|
|
word: SLICEA.K0.INIT 1110110010100000
|
|
word: SLICEB.K0.INIT 1011111110001111
|
|
word: SLICEB.K1.INIT 1011101010101010
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R19C43:PLC2
|
|
arc: E1_H02E0301 W3_H06E0003
|
|
arc: E1_H02E0501 N3_V06S0303
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: H01W0000 W3_H06E0103
|
|
arc: N1_V02N0001 W3_H06E0003
|
|
arc: N1_V02N0501 N3_V06S0303
|
|
arc: S1_V02S0201 W3_H06E0103
|
|
arc: S1_V02S0601 N3_V06S0303
|
|
arc: V00B0100 H02W0701
|
|
arc: V00T0100 V02N0501
|
|
arc: V01S0100 N3_V06S0303
|
|
arc: W1_H02W0001 V02N0001
|
|
arc: W1_H02W0101 W3_H06E0103
|
|
arc: W1_H02W0501 N3_V06S0303
|
|
arc: A1 S1_V02N0701
|
|
arc: B1 V02N0101
|
|
arc: C1 V02N0401
|
|
arc: CE0 H02W0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D1 V00B0100
|
|
arc: F1 F1_SLICE
|
|
arc: LSR1 V00T0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: V01S0000 Q1
|
|
word: SLICEA.K1.INIT 1100111111101010
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R19C44:PLC2
|
|
arc: E1_H02E0401 W3_H06E0203
|
|
arc: E1_H02E0601 W3_H06E0303
|
|
arc: E1_H02E0701 W1_H02E0701
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
arc: H00L0000 W1_H02E0001
|
|
arc: N1_V01N0101 N3_V06S0203
|
|
arc: V01S0100 N3_V06S0303
|
|
arc: W1_H02W0101 W3_H06E0103
|
|
arc: W1_H02W0501 V02N0501
|
|
arc: W1_H02W0701 W3_H06E0203
|
|
arc: A0 H00L0000
|
|
arc: B0 V02N0301
|
|
arc: C0 W1_H02E0601
|
|
arc: CE0 V02N0201
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V01S0100
|
|
arc: F0 F0_SLICE
|
|
arc: LSR1 H02E0501
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: N3_V06N0003 Q0
|
|
word: SLICEA.K0.INIT 1111100010001000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R19C45:PLC2
|
|
arc: H00L0100 W1_H02E0301
|
|
arc: H00R0100 V02N0501
|
|
arc: A0 H02E0701
|
|
arc: B0 H00R0100
|
|
arc: C0 H02E0401
|
|
arc: CE0 H00L0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02N0201
|
|
arc: E3_H06E0003 Q0
|
|
arc: F0 F0_SLICE
|
|
arc: LSR0 W1_H02E0501
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
word: SLICEA.K0.INIT 1010111011111100
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R19C46:PLC2
|
|
arc: E1_H02E0601 W1_H02E0601
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: N3_V06N0003 W3_H06E0003
|
|
arc: W3_H06W0003 E1_H01W0000
|
|
|
|
.tile R19C47:PLC2
|
|
arc: H01W0000 E3_H06W0103
|
|
arc: W3_H06W0003 E1_H01W0000
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
|
|
.tile R19C48:PLC2
|
|
arc: H00L0000 V02N0001
|
|
arc: H00R0000 W1_H02E0601
|
|
arc: N3_V06N0003 H06E0003
|
|
arc: S1_V02S0701 H02W0701
|
|
arc: V00B0100 H02W0701
|
|
arc: A0 E1_H02W0701
|
|
arc: B0 H00R0100
|
|
arc: C0 S1_V02N0601
|
|
arc: CE0 H02W0101
|
|
arc: CE3 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02N0201
|
|
arc: E3_H06E0003 Q0
|
|
arc: F0 F0_SLICE
|
|
arc: H00R0100 Q7
|
|
arc: H01W0000 Q7
|
|
arc: LSR1 V00B0100
|
|
arc: M7 H00L0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR3 LSR1
|
|
word: SLICEA.K0.INIT 1101110011111010
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R19C49:PLC2
|
|
arc: E1_H02E0401 N3_V06S0203
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
arc: S1_V02S0401 W3_H06E0203
|
|
arc: W1_H02W0101 W3_H06E0103
|
|
arc: W1_H02W0701 N3_V06S0203
|
|
|
|
.tile R19C50:PLC2
|
|
arc: E1_H02E0001 W3_H06E0003
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
arc: W1_H02W0701 W3_H06E0203
|
|
|
|
.tile R19C51:PLC2
|
|
arc: E1_H02E0501 W1_H02E0401
|
|
|
|
.tile R19C52:PLC2
|
|
arc: E1_H02E0101 W1_H02E0001
|
|
arc: E1_H02E0601 V01N0001
|
|
arc: N3_V06N0103 W3_H06E0103
|
|
arc: S1_V02S0601 N3_V06S0303
|
|
|
|
.tile R19C53:PLC2
|
|
arc: E1_H02E0101 V02N0101
|
|
arc: E1_H02E0501 V02N0501
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
arc: A0 V02N0501
|
|
arc: A1 V02N0501
|
|
arc: B0 S1_V02N0101
|
|
arc: B1 S1_V02N0101
|
|
arc: C0 E1_H02W0601
|
|
arc: C1 E1_H02W0601
|
|
arc: CE3 H02E0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02N0001
|
|
arc: D1 V02N0201
|
|
arc: E3_H06E0203 Q7
|
|
arc: F0 F5A_SLICE
|
|
arc: H00L0000 F0
|
|
arc: LSR1 W1_H02E0501
|
|
arc: M0 H02E0601
|
|
arc: M7 H00L0000
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR3 LSR1
|
|
word: SLICEA.K0.INIT 1100100011001111
|
|
word: SLICEA.K1.INIT 1101110111001111
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R19C54:PLC2
|
|
arc: E1_H02E0401 N3_V06S0203
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: H00R0000 V02N0401
|
|
arc: H00R0100 V02S0701
|
|
arc: N1_V01N0101 N3_V06S0203
|
|
arc: A0 H00L0100
|
|
arc: B0 H00R0100
|
|
arc: C0 E1_H02W0601
|
|
arc: CE0 H02W0101
|
|
arc: CE1 E1_H02W0101
|
|
arc: CE3 H02E0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H00R0000
|
|
arc: E1_H02E0501 Q7
|
|
arc: E3_H06E0003 Q0
|
|
arc: F0 F0_SLICE
|
|
arc: H00L0100 Q3
|
|
arc: LSR0 H02W0501
|
|
arc: LSR1 H02W0501
|
|
arc: M3 H02W0201
|
|
arc: M7 H00R0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR3 LSR1
|
|
word: SLICEA.K0.INIT 1010111011111100
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R19C55:PLC2
|
|
arc: E1_H02E0101 W3_H06E0103
|
|
arc: E1_H02E0501 N3_V06S0303
|
|
arc: H01W0100 W3_H06E0303
|
|
arc: N1_V02N0501 N3_V06S0303
|
|
arc: V00B0100 H02E0501
|
|
arc: W1_H02W0101 W3_H06E0103
|
|
arc: W1_H02W0501 N3_V06S0303
|
|
arc: W1_H02W0601 W3_H06E0303
|
|
arc: A2 W1_H02E0501
|
|
arc: A3 W1_H02E0501
|
|
arc: B2 H01W0100
|
|
arc: B3 H01W0100
|
|
arc: C2 H02E0401
|
|
arc: C3 H02E0401
|
|
arc: D2 V02N0001
|
|
arc: D3 V02N0201
|
|
arc: F2 F5B_SLICE
|
|
arc: M2 V00B0100
|
|
arc: W1_H02W0201 F2
|
|
word: SLICEB.K0.INIT 1110000011110011
|
|
word: SLICEB.K1.INIT 1111010111110011
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R19C56:PLC2
|
|
arc: E1_H02E0601 W3_H06E0303
|
|
arc: W1_H02W0101 W3_H06E0103
|
|
arc: W1_H02W0601 W3_H06E0303
|
|
|
|
.tile R19C57:PLC2
|
|
arc: H00R0000 V02N0401
|
|
arc: N1_V02N0101 E1_H02W0101
|
|
arc: A0 E1_H02W0701
|
|
arc: B0 E1_H02W0301
|
|
arc: C0 H02E0601
|
|
arc: CE0 W1_H02E0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H00R0000
|
|
arc: E3_H06E0003 Q0
|
|
arc: F0 F0_SLICE
|
|
arc: LSR1 W1_H02E0501
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
word: SLICEA.K0.INIT 1010111011111100
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R19C59:PLC2
|
|
arc: N1_V02N0601 S3_V06N0303
|
|
arc: W1_H02W0101 S3_V06N0103
|
|
arc: W1_H02W0301 S1_V02N0301
|
|
arc: W1_H02W0701 W3_H06E0203
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
|
|
.tile R19C60:PLC2
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
|
|
.tile R19C63:PLC2
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
|
|
.tile R19C65:PLC2
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
|
|
.tile R19C66:PLC2
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
|
|
.tile R19C69:PLC2
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
|
|
.tile R19C71:PLC2
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
|
|
.tile R19C72:PLC2
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
|
|
.tile R19C75:PLC2
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
|
|
.tile R19C77:PLC2
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
|
|
.tile R19C78:PLC2
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
|
|
.tile R19C7:PLC2
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: N1_V02N0301 W3_H06E0003
|
|
|
|
.tile R19C81:PLC2
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
|
|
.tile R19C83:PLC2
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
|
|
.tile R19C84:PLC2
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
|
|
.tile R19C87:PLC2
|
|
arc: S1_V02S0701 W3_H06E0203
|
|
arc: S3_V06S0003 H06E0003
|
|
arc: S3_V06S0103 H06E0103
|
|
|
|
.tile R19C8:PLC2
|
|
arc: W3_H06W0203 E3_H06W0203
|
|
|
|
.tile R20C10:PLC2
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
|
|
.tile R20C11:PLC2
|
|
arc: W3_H06W0203 E3_H06W0203
|
|
|
|
.tile R20C12:PLC2
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
|
|
.tile R20C13:PLC2
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
|
|
.tile R20C14:PLC2
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
|
|
.tile R20C15:PLC2
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
|
|
.tile R20C16:PLC2
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
|
|
.tile R20C17:PLC2
|
|
arc: W3_H06W0203 E3_H06W0203
|
|
|
|
.tile R20C18:PLC2
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
|
|
.tile R20C19:PLC2
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
|
|
.tile R20C20:PLC2
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
arc: W3_H06W0303 E3_H06W0203
|
|
|
|
.tile R20C21:PLC2
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
|
|
.tile R20C22:PLC2
|
|
arc: W3_H06W0303 E3_H06W0203
|
|
|
|
.tile R20C23:PLC2
|
|
arc: W3_H06W0203 E3_H06W0203
|
|
|
|
.tile R20C24:PLC2
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
|
|
.tile R20C25:PLC2
|
|
arc: E1_H02E0301 V02S0301
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
|
|
.tile R20C26:PLC2
|
|
arc: E1_H02E0501 E3_H06W0303
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
arc: W3_H06W0203 E3_H06W0203
|
|
|
|
.tile R20C27:PLC2
|
|
arc: E1_H02E0001 N1_V01S0000
|
|
arc: H00L0000 V02N0201
|
|
arc: H00R0100 H02E0501
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
arc: A0 H00L0000
|
|
arc: B0 E1_H02W0301
|
|
arc: C0 V02N0401
|
|
arc: CE0 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 E1_H02W0001
|
|
arc: F0 F0_SLICE
|
|
arc: LSR1 W1_H02E0301
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: V01S0000 Q0
|
|
word: SLICEA.K0.INIT 1100000011101010
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R20C28:PLC2
|
|
arc: H00R0000 E1_H02W0601
|
|
arc: V00B0100 V02S0101
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
arc: CE0 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H02E0101 Q1
|
|
arc: LSR1 V00B0100
|
|
arc: M1 H02E0001
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R20C29:PLC2
|
|
arc: E1_H02E0201 E3_H06W0103
|
|
arc: E1_H02E0301 E3_H06W0003
|
|
arc: H00R0100 H02W0501
|
|
arc: S1_V02S0101 E3_H06W0103
|
|
arc: V00B0000 E1_H02W0401
|
|
arc: W1_H02W0001 E1_H02W0501
|
|
arc: W1_H02W0301 E1_H01W0100
|
|
arc: W3_H06W0203 E3_H06W0203
|
|
arc: A0 V02N0701
|
|
arc: B0 H02E0101
|
|
arc: C0 E1_H02W0601
|
|
arc: CE0 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 W1_H02E0001
|
|
arc: E3_H06E0003 Q0
|
|
arc: F0 F0_SLICE
|
|
arc: LSR1 V00B0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
word: SLICEA.K0.INIT 1000111110001000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R20C2:PLC2
|
|
arc: S3_V06S0103 E3_H06W0103
|
|
arc: S3_V06S0303 E3_H06W0303
|
|
arc: D3 V02N0001
|
|
arc: F3 F3_SLICE
|
|
arc: H01W0100 F3
|
|
word: SLICEB.K1.INIT 0000000011111111
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
|
|
.tile R20C30:PLC2
|
|
arc: E1_H01E0001 E3_H06W0003
|
|
arc: H00L0100 H02W0101
|
|
arc: H00R0000 E1_H02W0601
|
|
arc: H00R0100 E1_H02W0701
|
|
arc: S1_V02S0001 E3_H06W0003
|
|
arc: S1_V02S0201 H06W0103
|
|
arc: V00B0000 H02W0401
|
|
arc: V00B0100 V02N0101
|
|
arc: W1_H02W0501 E1_H02W0401
|
|
arc: W1_H02W0601 E1_H02W0601
|
|
arc: A0 E1_H01E0001
|
|
arc: B0 H02W0101
|
|
arc: C0 E1_H01W0000
|
|
arc: CE0 H00R0100
|
|
arc: CE3 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H02E0201
|
|
arc: E1_H02E0701 Q7
|
|
arc: F0 F0_SLICE
|
|
arc: H01W0100 Q6
|
|
arc: LSR0 V00B0000
|
|
arc: M6 V00B0100
|
|
arc: M7 H00L0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR3 LSR0
|
|
arc: W3_H06W0003 Q0
|
|
word: SLICEA.K0.INIT 1110110010100000
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R20C31:PLC2
|
|
arc: E1_H02E0001 W3_H06E0003
|
|
arc: E1_H02E0101 E1_H01W0100
|
|
arc: E1_H02E0401 N1_V01S0000
|
|
arc: E1_H02E0601 W1_H02E0301
|
|
arc: E1_H02E0701 N1_V01S0100
|
|
arc: H00L0100 S1_V02N0101
|
|
arc: H00R0000 H02W0401
|
|
arc: H01W0100 E3_H06W0303
|
|
arc: N1_V02N0001 N1_V01S0000
|
|
arc: N1_V02N0201 H01E0001
|
|
arc: N1_V02N0301 W3_H06E0003
|
|
arc: N1_V02N0401 H01E0001
|
|
arc: S1_V02S0601 E3_H06W0303
|
|
arc: S1_V02S0701 H06W0203
|
|
arc: V00B0000 V02S0201
|
|
arc: W1_H02W0101 S1_V02N0101
|
|
arc: W1_H02W0401 N1_V01S0000
|
|
arc: W1_H02W0501 E3_H06W0303
|
|
arc: W1_H02W0601 E3_H06W0303
|
|
arc: A0 H02E0701
|
|
arc: B0 H01W0100
|
|
arc: C0 H00L0100
|
|
arc: CE0 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02N0001
|
|
arc: F0 F0_SLICE
|
|
arc: H01W0000 Q0
|
|
arc: LSR1 V00B0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
word: SLICEA.K0.INIT 1011101000110000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R20C32:PLC2
|
|
arc: E1_H02E0201 E3_H06W0103
|
|
arc: E1_H02E0401 V02S0401
|
|
arc: E1_H02E0501 E3_H06W0303
|
|
arc: H00L0000 S1_V02N0201
|
|
arc: H00R0000 V02S0401
|
|
arc: H00R0100 S1_V02N0501
|
|
arc: H01W0100 E3_H06W0303
|
|
arc: N1_V02N0001 H06W0003
|
|
arc: N1_V02N0301 H06E0003
|
|
arc: N1_V02N0401 H02E0401
|
|
arc: N1_V02N0601 H06W0303
|
|
arc: S1_V02S0201 H06W0103
|
|
arc: S1_V02S0701 E3_H06W0203
|
|
arc: V00B0000 H02E0401
|
|
arc: W1_H02W0401 E3_H06W0203
|
|
arc: W1_H02W0601 E3_H06W0303
|
|
arc: W1_H02W0701 E1_H02W0601
|
|
arc: W3_H06W0203 E1_H01W0000
|
|
arc: W3_H06W0303 E3_H06W0203
|
|
arc: A1 V02N0501
|
|
arc: B1 H00R0100
|
|
arc: C1 H02E0601
|
|
arc: CE0 V02S0201
|
|
arc: CE1 H02E0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D1 H00R0000
|
|
arc: F1 F1_SLICE
|
|
arc: LSR0 V00B0000
|
|
arc: M3 H00L0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR0
|
|
arc: S1_V02S0301 Q3
|
|
arc: W3_H06W0103 Q1
|
|
word: SLICEA.K1.INIT 1010111111101100
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R20C33:PLC2
|
|
arc: E1_H02E0501 S1_V02N0501
|
|
arc: E3_H06E0203 W1_H02E0701
|
|
arc: H00R0000 V02S0401
|
|
arc: H00R0100 V02S0701
|
|
arc: N1_V02N0501 N1_V01S0100
|
|
arc: S1_V02S0001 W1_H02E0001
|
|
arc: S1_V02S0301 E1_H02W0301
|
|
arc: S1_V02S0601 H06W0303
|
|
arc: V00B0100 H02W0701
|
|
arc: V00T0100 H02W0101
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
arc: W3_H06W0103 E1_H01W0100
|
|
arc: A3 E1_H02W0501
|
|
arc: B0 E1_H02W0301
|
|
arc: B3 H00R0100
|
|
arc: C0 H00L0000
|
|
arc: C3 H02E0401
|
|
arc: CE0 E1_H02W0101
|
|
arc: CE1 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02S0001
|
|
arc: D3 E1_H02W0201
|
|
arc: F0 F0_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: H00L0000 Q0
|
|
arc: H01W0000 Q3
|
|
arc: LSR0 V00B0100
|
|
arc: LSR1 V00T0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR1
|
|
arc: N1_V02N0201 Q0
|
|
word: SLICEB.K1.INIT 1010111011111100
|
|
word: SLICEA.K0.INIT 0000111100001100
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R20C34:PLC2
|
|
arc: E1_H02E0201 W1_H02E0201
|
|
arc: E1_H02E0301 S1_V02N0301
|
|
arc: E1_H02E0701 V02S0701
|
|
arc: H00L0100 S1_V02N0301
|
|
arc: H00R0000 S1_V02N0601
|
|
arc: H00R0100 W1_H02E0501
|
|
arc: N1_V02N0401 E1_H01W0000
|
|
arc: N1_V02N0601 S1_V02N0601
|
|
arc: N1_V02N0701 H02W0701
|
|
arc: S1_V02S0201 H06W0103
|
|
arc: S1_V02S0301 H02W0301
|
|
arc: V00B0000 E1_H02W0401
|
|
arc: V00B0100 H02E0501
|
|
arc: V00T0100 V02S0701
|
|
arc: W1_H02W0101 V02S0101
|
|
arc: W1_H02W0701 V02S0701
|
|
arc: A2 H00L0100
|
|
arc: A3 V00B0000
|
|
arc: A4 H02W0701
|
|
arc: B2 E1_H01W0100
|
|
arc: B3 V02S0301
|
|
arc: C2 V02S0601
|
|
arc: C3 E1_H02W0601
|
|
arc: C4 H02W0601
|
|
arc: CE1 E1_H02W0101
|
|
arc: CE2 H00R0100
|
|
arc: CE3 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D2 E1_H02W0001
|
|
arc: D3 V02S0001
|
|
arc: D4 H01W0000
|
|
arc: E1_H01E0101 F4
|
|
arc: E1_H02E0401 F4
|
|
arc: E3_H06E0203 F4
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: H01W0000 F3
|
|
arc: H01W0100 F4
|
|
arc: LSR0 V00T0100
|
|
arc: LSR1 V00T0100
|
|
arc: M4 V00B0100
|
|
arc: M7 H00R0000
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR0
|
|
arc: MUXLSR3 LSR0
|
|
arc: N1_V01N0101 F4
|
|
arc: N1_V02N0301 F3
|
|
arc: S1_V02S0401 Q4
|
|
arc: S3_V06S0203 F4
|
|
arc: V01S0000 Q7
|
|
arc: V01S0100 F4
|
|
arc: W1_H02W0601 F4
|
|
arc: W3_H06W0103 Q2
|
|
arc: W3_H06W0203 F4
|
|
word: SLICEB.K0.INIT 1100111011111010
|
|
word: SLICEC.K0.INIT 0000101000000000
|
|
word: SLICEB.K1.INIT 0000110100000000
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET SET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R20C35:PLC2
|
|
arc: E1_H02E0101 S1_V02N0101
|
|
arc: E3_H06E0103 H01E0101
|
|
arc: H00L0000 V02N0001
|
|
arc: H00L0100 V02S0301
|
|
arc: H00R0000 H02E0401
|
|
arc: H00R0100 E1_H02W0701
|
|
arc: N1_V02N0001 V01N0001
|
|
arc: N1_V02N0101 S1_V02N0101
|
|
arc: N1_V02N0201 E1_H01W0000
|
|
arc: N1_V02N0401 H02W0401
|
|
arc: N1_V02N0601 H06W0303
|
|
arc: N1_V02N0701 H02E0701
|
|
arc: S1_V02S0301 E1_H02W0301
|
|
arc: S1_V02S0401 H02W0401
|
|
arc: S1_V02S0501 E1_H01W0100
|
|
arc: S1_V02S0601 H06W0303
|
|
arc: V00B0100 H02E0701
|
|
arc: W1_H02W0101 N1_V01S0100
|
|
arc: W1_H02W0201 E1_H01W0000
|
|
arc: W1_H02W0301 E1_H02W0301
|
|
arc: W1_H02W0501 E1_H02W0501
|
|
arc: W1_H02W0601 N1_V01S0000
|
|
arc: W1_H02W0701 E1_H02W0701
|
|
arc: W3_H06W0003 E1_H01W0000
|
|
arc: W3_H06W0103 E1_H01W0100
|
|
arc: W3_H06W0303 E1_H01W0100
|
|
arc: A0 V02S0501
|
|
arc: A1 V02S0501
|
|
arc: A2 H02W0501
|
|
arc: A4 E1_H01W0000
|
|
arc: A6 H02W0701
|
|
arc: B0 E1_H02W0101
|
|
arc: B1 E1_H02W0101
|
|
arc: B3 E1_H01W0100
|
|
arc: B4 E1_H02W0301
|
|
arc: B6 F3
|
|
arc: C1 E1_H01W0000
|
|
arc: C2 V02N0601
|
|
arc: C3 H02W0601
|
|
arc: C4 H02W0401
|
|
arc: C6 F4
|
|
arc: CE0 H00R0100
|
|
arc: CE1 H00R0100
|
|
arc: CE2 V02S0601
|
|
arc: CE3 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 E1_H02W0001
|
|
arc: D1 E1_H02W0001
|
|
arc: D2 F0
|
|
arc: D3 S1_V02N0001
|
|
arc: D4 E1_H02W0201
|
|
arc: D6 F0
|
|
arc: E1_H01E0001 F4
|
|
arc: E1_H02E0501 Q5
|
|
arc: E3_H06E0303 Q5
|
|
arc: F0 F5A_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: H01W0000 F6
|
|
arc: H01W0100 Q5
|
|
arc: LSR0 V00B0100
|
|
arc: LSR1 V00B0100
|
|
arc: M0 E1_H02W0601
|
|
arc: M1 H00L0100
|
|
arc: M5 H00L0000
|
|
arc: M7 H02E0201
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR1
|
|
arc: S3_V06S0103 Q1
|
|
arc: V01S0000 Q2
|
|
arc: W3_H06W0203 Q7
|
|
word: SLICEB.K1.INIT 0000001100001111
|
|
word: SLICED.K0.INIT 1000110000000000
|
|
word: SLICEC.K0.INIT 0000000000000001
|
|
word: SLICEA.K0.INIT 0101010101110111
|
|
word: SLICEA.K1.INIT 0000010100000111
|
|
word: SLICEB.K0.INIT 1111101011111111
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET SET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R20C36:PLC2
|
|
arc: E1_H02E0301 W1_H02E0301
|
|
arc: E1_H02E0701 V02N0701
|
|
arc: E3_H06E0103 N1_V01S0100
|
|
arc: N1_V02N0001 H01E0001
|
|
arc: N1_V02N0101 H02E0101
|
|
arc: N1_V02N0401 H01E0001
|
|
arc: N1_V02N0501 E1_H01W0100
|
|
arc: N1_V02N0701 H02W0701
|
|
arc: S1_V02S0401 H06E0203
|
|
arc: S1_V02S0601 E1_H02W0601
|
|
arc: V00B0100 H02W0701
|
|
arc: V00T0000 H02W0201
|
|
arc: V00T0100 H02W0301
|
|
arc: W1_H02W0101 V02S0101
|
|
arc: W1_H02W0501 N1_V02S0501
|
|
arc: W1_H02W0601 E1_H01W0000
|
|
arc: W1_H02W0701 V06S0203
|
|
arc: W3_H06W0303 E1_H02W0601
|
|
arc: A1 F5
|
|
arc: A2 E1_H02W0501
|
|
arc: A3 E1_H02W0501
|
|
arc: A5 V02N0301
|
|
arc: A6 E1_H01W0000
|
|
arc: B1 V02N0101
|
|
arc: B2 H02E0101
|
|
arc: B3 H02E0101
|
|
arc: B4 H02E0101
|
|
arc: B5 H02W0101
|
|
arc: B6 V00B0100
|
|
arc: C0 E1_H02W0401
|
|
arc: C1 H00L0000
|
|
arc: C2 H02W0401
|
|
arc: C3 H02W0401
|
|
arc: C5 V00T0000
|
|
arc: C6 S1_V02N0201
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 S1_V02N0201
|
|
arc: D1 V02N0201
|
|
arc: D2 H00R0000
|
|
arc: D3 H00R0000
|
|
arc: D4 V00B0000
|
|
arc: D5 H02W0001
|
|
arc: D6 E1_H02W0201
|
|
arc: E1_H01E0001 Q0
|
|
arc: E1_H01E0101 F1
|
|
arc: E1_H02E0001 F2
|
|
arc: E1_H02E0201 Q0
|
|
arc: E1_H02E0401 Q6
|
|
arc: E1_H02E0601 F4
|
|
arc: E3_H06E0003 Q0
|
|
arc: E3_H06E0303 Q6
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: H00L0000 Q0
|
|
arc: H00R0000 Q6
|
|
arc: H01W0000 Q0
|
|
arc: H01W0100 Q6
|
|
arc: M2 V00T0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q6
|
|
arc: N1_V01N0101 Q0
|
|
arc: N1_V02N0201 Q0
|
|
arc: N1_V02N0601 Q6
|
|
arc: N3_V06N0003 Q0
|
|
arc: N3_V06N0303 Q6
|
|
arc: S1_V02S0001 Q0
|
|
arc: S3_V06S0003 Q0
|
|
arc: S3_V06S0303 Q6
|
|
arc: V00B0000 Q6
|
|
arc: V01S0000 Q6
|
|
arc: V01S0100 Q0
|
|
arc: W1_H02W0001 Q0
|
|
arc: W1_H02W0401 Q6
|
|
arc: W3_H06W0003 Q0
|
|
word: SLICED.K0.INIT 0000101100001111
|
|
word: SLICEC.K1.INIT 1110000011000000
|
|
word: SLICEA.K1.INIT 0000000000010101
|
|
word: SLICEA.K0.INIT 0000000011110000
|
|
word: SLICEC.K0.INIT 1100110000000000
|
|
word: SLICEB.K0.INIT 1011100011111111
|
|
word: SLICEB.K1.INIT 1011101010101010
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R20C37:PLC2
|
|
arc: E1_H02E0001 W1_H02E0501
|
|
arc: E1_H02E0301 N1_V01S0100
|
|
arc: E1_H02E0401 N1_V01S0000
|
|
arc: E1_H02E0601 V02N0601
|
|
arc: E1_H02E0701 V02S0701
|
|
arc: H00R0000 H02W0601
|
|
arc: N1_V02N0301 H01E0101
|
|
arc: N1_V02N0401 H01E0001
|
|
arc: N1_V02N0601 H02E0601
|
|
arc: N3_V06N0103 E1_H01W0100
|
|
arc: S1_V02S0201 E1_H01W0000
|
|
arc: S1_V02S0401 E1_H02W0401
|
|
arc: S1_V02S0601 H02W0601
|
|
arc: V00B0000 V02S0201
|
|
arc: V00B0100 H02W0501
|
|
arc: V00T0100 E1_H02W0101
|
|
arc: W1_H02W0201 N1_V01S0000
|
|
arc: W1_H02W0301 N1_V01S0100
|
|
arc: W1_H02W0601 V01N0001
|
|
arc: W3_H06W0103 E1_H01W0100
|
|
arc: A0 H00L0100
|
|
arc: A4 F7
|
|
arc: A5 H02W0701
|
|
arc: A7 H00L0000
|
|
arc: B0 V00T0000
|
|
arc: B1 Q1
|
|
arc: B3 H02W0301
|
|
arc: B4 H02W0301
|
|
arc: B7 V02S0501
|
|
arc: C0 H00L0000
|
|
arc: C1 H00L0000
|
|
arc: C2 H00L0000
|
|
arc: C3 H02E0401
|
|
arc: C4 V02S0201
|
|
arc: C6 H02E0601
|
|
arc: C7 V00T0000
|
|
arc: CE0 H00R0100
|
|
arc: CE1 H00R0100
|
|
arc: CE2 V02S0601
|
|
arc: CE3 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 N1_V01S0000
|
|
arc: D1 N1_V01S0000
|
|
arc: D2 N1_V01S0000
|
|
arc: D3 V02N0201
|
|
arc: D4 H01W0000
|
|
arc: D5 H02W0001
|
|
arc: D6 V00B0000
|
|
arc: D7 H00L0100
|
|
arc: E1_H01E0001 F4
|
|
arc: E1_H01E0101 F4
|
|
arc: E1_H02E0101 Q1
|
|
arc: E1_H02E0201 Q0
|
|
arc: E1_H02E0501 Q5
|
|
arc: E3_H06E0303 F6
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00L0000 Q2
|
|
arc: H00L0100 Q1
|
|
arc: H00R0100 F5
|
|
arc: H01W0000 F3
|
|
arc: H01W0100 F4
|
|
arc: LSR0 V00T0100
|
|
arc: LSR1 V00T0100
|
|
arc: M5 H02E0001
|
|
arc: M6 V00B0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR0
|
|
arc: N1_V01N0001 F4
|
|
arc: N1_V01N0101 Q1
|
|
arc: N1_V02N0001 Q0
|
|
arc: N1_V02N0101 F3
|
|
arc: N1_V02N0201 Q0
|
|
arc: N1_V02N0501 F7
|
|
arc: S1_V02S0001 Q0
|
|
arc: S1_V02S0101 Q1
|
|
arc: S3_V06S0303 F6
|
|
arc: V00T0000 Q0
|
|
arc: V01S0000 Q2
|
|
arc: V01S0100 Q2
|
|
arc: W1_H02W0001 Q0
|
|
arc: W1_H02W0101 Q1
|
|
arc: W1_H02W0401 Q6
|
|
arc: W1_H02W0501 Q5
|
|
arc: W1_H02W0701 F7
|
|
arc: W3_H06W0303 F6
|
|
word: SLICEB.K1.INIT 0000000000110000
|
|
word: SLICEC.K0.INIT 0000000010001010
|
|
word: SLICED.K0.INIT 0000000000001111
|
|
word: SLICEA.K0.INIT 0110110000000000
|
|
word: SLICEA.K1.INIT 0011110000000000
|
|
word: SLICEB.K0.INIT 0000111100000000
|
|
word: SLICEC.K1.INIT 0101010100000000
|
|
word: SLICED.K1.INIT 1111111110111111
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R20C38:PLC2
|
|
arc: E1_H02E0101 V02S0101
|
|
arc: E1_H02E0201 W1_H02E0201
|
|
arc: E1_H02E0401 W1_H02E0401
|
|
arc: E1_H02E0501 W1_H02E0401
|
|
arc: E1_H02E0701 V02S0701
|
|
arc: H00L0100 W1_H02E0301
|
|
arc: H00R0000 E1_H02W0401
|
|
arc: H00R0100 H02E0701
|
|
arc: N1_V02N0001 H01E0001
|
|
arc: N1_V02N0301 S1_V02N0301
|
|
arc: N1_V02N0401 H01E0001
|
|
arc: S1_V02S0201 H02E0201
|
|
arc: V00B0000 H02E0401
|
|
arc: V00T0000 H02E0201
|
|
arc: V00T0100 H02W0101
|
|
arc: W1_H02W0001 N1_V02S0001
|
|
arc: W1_H02W0201 V06S0103
|
|
arc: W1_H02W0301 S1_V02N0301
|
|
arc: W1_H02W0401 N1_V01S0000
|
|
arc: W1_H02W0501 E1_H02W0501
|
|
arc: W1_H02W0701 V06S0203
|
|
arc: W3_H06W0103 E1_H01W0100
|
|
arc: A0 F5
|
|
arc: A2 H00L0100
|
|
arc: A3 H02E0501
|
|
arc: A4 V00T0000
|
|
arc: A5 W1_H02E0701
|
|
arc: A6 S1_V02N0301
|
|
arc: A7 F5
|
|
arc: B0 V00B0000
|
|
arc: B2 E1_H02W0101
|
|
arc: B3 H02E0301
|
|
arc: B4 H02E0101
|
|
arc: B5 H02E0301
|
|
arc: B7 S1_V02N0501
|
|
arc: C0 N1_V01S0100
|
|
arc: C2 H02W0401
|
|
arc: C3 V02S0601
|
|
arc: C4 H02E0401
|
|
arc: C5 S1_V02N0001
|
|
arc: C6 V02N0001
|
|
arc: C7 W1_H02E0401
|
|
arc: CE3 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H01E0101
|
|
arc: D2 H02E0001
|
|
arc: D3 F2
|
|
arc: D4 F0
|
|
arc: D5 H00R0100
|
|
arc: D6 V02N0601
|
|
arc: D7 V02N0401
|
|
arc: E1_H01E0001 F7
|
|
arc: E1_H01E0101 F6
|
|
arc: E1_H02E0301 F3
|
|
arc: E1_H02E0601 F6
|
|
arc: E3_H06E0203 F4
|
|
arc: E3_H06E0303 F6
|
|
arc: F0 F0_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 F0
|
|
arc: H01W0100 F6
|
|
arc: LSR1 V00T0100
|
|
arc: M7 E1_H02W0201
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR3 LSR1
|
|
arc: N3_V06N0203 Q7
|
|
arc: N3_V06N0303 F6
|
|
arc: S1_V02S0401 F6
|
|
arc: S1_V02S0601 F4
|
|
arc: S3_V06S0203 F4
|
|
arc: S3_V06S0303 F6
|
|
arc: V01S0100 F4
|
|
arc: W1_H02W0601 F6
|
|
arc: W3_H06W0203 F4
|
|
arc: W3_H06W0303 F6
|
|
word: SLICEA.K0.INIT 1100010100000000
|
|
word: SLICEC.K0.INIT 1110111100000000
|
|
word: SLICEC.K1.INIT 0000000001000000
|
|
word: SLICEB.K0.INIT 1111001101010001
|
|
word: SLICEB.K1.INIT 1100010000000000
|
|
word: SLICED.K1.INIT 0000000010111010
|
|
word: SLICED.K0.INIT 0000000000001010
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R20C39:PLC2
|
|
arc: E1_H02E0001 W1_H02E0501
|
|
arc: E1_H02E0501 S1_V02N0501
|
|
arc: E3_H06E0103 H01E0101
|
|
arc: H00L0000 E1_H02W0001
|
|
arc: H00R0000 H02E0601
|
|
arc: N1_V02N0001 H01E0001
|
|
arc: N1_V02N0101 H01E0101
|
|
arc: N1_V02N0201 H06E0103
|
|
arc: N1_V02N0301 H06E0003
|
|
arc: N1_V02N0501 E1_H02W0501
|
|
arc: N1_V02N0601 H06E0303
|
|
arc: S1_V02S0001 H06E0003
|
|
arc: S1_V02S0101 H01E0101
|
|
arc: S1_V02S0601 H06E0303
|
|
arc: S1_V02S0701 E1_H02W0701
|
|
arc: V00B0100 E1_H02W0701
|
|
arc: V00T0100 V02S0501
|
|
arc: W1_H02W0101 V02S0101
|
|
arc: W1_H02W0401 N1_V01S0000
|
|
arc: A0 E1_H02W0701
|
|
arc: A2 H02E0501
|
|
arc: A6 H00L0000
|
|
arc: B0 V01N0001
|
|
arc: B2 W1_H02E0101
|
|
arc: B4 H02E0301
|
|
arc: B6 E1_H02W0301
|
|
arc: C0 H02E0401
|
|
arc: C2 V02N0601
|
|
arc: C3 H02E0401
|
|
arc: C4 V00T0100
|
|
arc: C6 V02S0001
|
|
arc: CE2 H00R0000
|
|
arc: CE3 H02E0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H02E0201
|
|
arc: D2 W1_H02E0201
|
|
arc: D3 H02E0201
|
|
arc: D4 E1_H01W0100
|
|
arc: D6 H02E0201
|
|
arc: E1_H01E0001 F2
|
|
arc: E1_H02E0201 F2
|
|
arc: F0 F5A_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: H01W0100 F0
|
|
arc: LSR0 H02W0301
|
|
arc: M0 V00T0000
|
|
arc: M2 W1_H02E0601
|
|
arc: M4 V00B0100
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR2 LSR0
|
|
arc: MUXLSR3 LSR0
|
|
arc: N1_V01N0001 F4
|
|
arc: S1_V02S0201 F2
|
|
arc: V00T0000 F2
|
|
arc: V01S0000 Q4
|
|
arc: W3_H06W0303 Q6
|
|
word: SLICED.K0.INIT 1100111011111010
|
|
word: SLICEC.K0.INIT 1100000000000000
|
|
word: SLICEB.K0.INIT 0000010100000001
|
|
word: SLICEB.K1.INIT 0000000000001111
|
|
word: SLICEA.K0.INIT 1110110010100000
|
|
word: SLICEA.K1.INIT 1111111111111111
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
|
|
.tile R20C3:PLC2
|
|
arc: N1_V02N0701 H06W0203
|
|
arc: W1_H02W0501 E1_H02W0401
|
|
arc: W1_H02W0701 E3_H06W0203
|
|
|
|
.tile R20C40:PLC2
|
|
arc: E1_H01E0101 W3_H06E0203
|
|
arc: E1_H02E0201 W1_H02E0701
|
|
arc: E1_H02E0401 W3_H06E0203
|
|
arc: E1_H02E0501 V01N0101
|
|
arc: E1_H02E0701 W3_H06E0203
|
|
arc: H00R0000 E1_H02W0601
|
|
arc: H00R0100 S1_V02N0501
|
|
arc: N1_V02N0001 E1_H02W0001
|
|
arc: N1_V02N0101 V01N0101
|
|
arc: N1_V02N0201 H02W0201
|
|
arc: N1_V02N0501 H02W0501
|
|
arc: N1_V02N0701 S1_V02N0601
|
|
arc: S1_V02S0601 H06E0303
|
|
arc: V00B0000 V02S0001
|
|
arc: V00B0100 V02N0301
|
|
arc: V00T0100 V02S0501
|
|
arc: W1_H02W0101 N1_V01S0100
|
|
arc: W1_H02W0201 V02N0201
|
|
arc: W1_H02W0301 V01N0101
|
|
arc: W1_H02W0401 W3_H06E0203
|
|
arc: W1_H02W0501 V02S0501
|
|
arc: A0 E1_H02W0501
|
|
arc: A3 H02E0501
|
|
arc: A6 S1_V02N0301
|
|
arc: A7 V02N0101
|
|
arc: B0 V01N0001
|
|
arc: B3 V02N0301
|
|
arc: B6 V00B0100
|
|
arc: B7 N1_V01S0000
|
|
arc: C0 H00R0100
|
|
arc: C3 V02N0601
|
|
arc: C6 E1_H02W0601
|
|
arc: C7 V00T0100
|
|
arc: CE3 H02W0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 E1_H02W0001
|
|
arc: D3 H00R0000
|
|
arc: D6 E1_H01W0100
|
|
arc: D7 H02E0001
|
|
arc: E1_H01E0001 F7
|
|
arc: F0 F5A_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0100 F3
|
|
arc: LSR1 V00B0000
|
|
arc: M0 H01E0001
|
|
arc: M6 V00T0000
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR3 LSR1
|
|
arc: N1_V01N0001 F6
|
|
arc: N3_V06N0303 Q6
|
|
arc: V00T0000 F0
|
|
word: SLICED.K0.INIT 1000101011001111
|
|
word: SLICED.K1.INIT 1101110100001101
|
|
word: SLICEB.K1.INIT 1111010100110001
|
|
word: SLICEA.K0.INIT 1110110010100000
|
|
word: SLICEA.K1.INIT 1111111111111111
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R20C41:PLC2
|
|
arc: E1_H02E0201 N3_V06S0103
|
|
arc: E1_H02E0401 S1_V02N0401
|
|
arc: E1_H02E0701 S1_V02N0701
|
|
arc: E3_H06E0103 H01E0101
|
|
arc: H00L0000 H02E0201
|
|
arc: H00R0000 V02N0601
|
|
arc: H00R0100 H02E0701
|
|
arc: H01W0100 W3_H06E0303
|
|
arc: N1_V02N0001 E3_H06W0003
|
|
arc: N1_V02N0101 H01E0101
|
|
arc: N1_V02N0201 H01E0001
|
|
arc: N1_V02N0501 H06E0303
|
|
arc: N1_V02N0601 H06E0303
|
|
arc: N1_V02N0701 E1_H01W0100
|
|
arc: S1_V02S0001 S3_V06N0003
|
|
arc: S1_V02S0201 W1_H02E0201
|
|
arc: S1_V02S0301 E1_H01W0100
|
|
arc: S1_V02S0501 E1_H01W0100
|
|
arc: S1_V02S0701 H06E0203
|
|
arc: V00B0100 E1_H02W0501
|
|
arc: V01S0100 S3_V06N0303
|
|
arc: W1_H02W0001 S3_V06N0003
|
|
arc: W1_H02W0101 W3_H06E0103
|
|
arc: W1_H02W0201 E3_H06W0103
|
|
arc: W1_H02W0501 E3_H06W0303
|
|
arc: W1_H02W0701 E3_H06W0203
|
|
arc: A0 V02S0501
|
|
arc: B0 H02W0101
|
|
arc: C0 V02N0401
|
|
arc: CE0 V02N0201
|
|
arc: CE1 H00L0000
|
|
arc: CE2 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V00B0100
|
|
arc: E3_H06E0003 Q0
|
|
arc: E3_H06E0303 Q5
|
|
arc: F0 F0_SLICE
|
|
arc: LSR0 H02E0501
|
|
arc: LSR1 E1_H02W0301
|
|
arc: M3 E1_H02W0201
|
|
arc: M5 H00R0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR0
|
|
arc: N1_V01N0001 Q3
|
|
arc: N1_V01N0101 Q3
|
|
arc: W1_H02W0301 Q3
|
|
word: SLICEA.K0.INIT 1100000011101010
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R20C42:PLC2
|
|
arc: E1_H01E0001 W3_H06E0003
|
|
arc: E1_H02E0501 W1_H02E0401
|
|
arc: E1_H02E0601 W3_H06E0303
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: H00L0000 W1_H02E0201
|
|
arc: H00R0000 E1_H02W0401
|
|
arc: H00R0100 E1_H02W0501
|
|
arc: H01W0100 W3_H06E0303
|
|
arc: N1_V02N0001 W3_H06E0003
|
|
arc: N1_V02N0101 H06E0103
|
|
arc: N1_V02N0301 S1_V02N0301
|
|
arc: N1_V02N0501 W3_H06E0303
|
|
arc: N1_V02N0601 W3_H06E0303
|
|
arc: N1_V02N0701 H02E0701
|
|
arc: N3_V06N0003 W3_H06E0003
|
|
arc: S1_V02S0001 W3_H06E0003
|
|
arc: S1_V02S0201 H06E0103
|
|
arc: S1_V02S0301 H02W0301
|
|
arc: S1_V02S0601 W3_H06E0303
|
|
arc: S3_V06S0303 W3_H06E0303
|
|
arc: V00B0000 V02N0001
|
|
arc: W1_H02W0001 W3_H06E0003
|
|
arc: W1_H02W0501 W3_H06E0303
|
|
arc: A0 H02E0701
|
|
arc: B0 E1_H01W0100
|
|
arc: C0 V02N0401
|
|
arc: CE0 H00R0000
|
|
arc: CE1 H00R0100
|
|
arc: CE2 H00R0100
|
|
arc: CE3 H00L0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V01S0100
|
|
arc: E1_H01E0101 Q6
|
|
arc: F0 F0_SLICE
|
|
arc: LSR0 H02W0301
|
|
arc: M3 H02E0201
|
|
arc: M4 H02E0401
|
|
arc: M6 V00B0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR0
|
|
arc: MUXLSR3 LSR0
|
|
arc: N1_V01N0001 Q0
|
|
arc: V01S0100 Q4
|
|
arc: W1_H02W0101 Q3
|
|
arc: W1_H02W0601 Q6
|
|
word: SLICEA.K0.INIT 1111001000100010
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R20C43:PLC2
|
|
arc: E3_H06E0003 N1_V01S0000
|
|
arc: H00R0000 H02W0601
|
|
arc: H00R0100 H02E0501
|
|
arc: H01W0100 W3_H06E0303
|
|
arc: N1_V02N0001 S1_V02N0001
|
|
arc: N1_V02N0101 H01E0101
|
|
arc: N1_V02N0401 H01E0001
|
|
arc: N1_V02N0501 N1_V01S0100
|
|
arc: V00T0000 V02S0601
|
|
arc: V00T0100 V02N0701
|
|
arc: W1_H02W0201 V02N0201
|
|
arc: W1_H02W0301 N1_V01S0100
|
|
arc: W1_H02W0501 W3_H06E0303
|
|
arc: A0 H01E0001
|
|
arc: B0 H02W0301
|
|
arc: C0 H02E0601
|
|
arc: CE0 H00R0100
|
|
arc: CE2 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02N0001
|
|
arc: E1_H01E0001 Q0
|
|
arc: F0 F0_SLICE
|
|
arc: LSR1 V00T0000
|
|
arc: M4 V00T0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR2 LSR1
|
|
arc: V01S0000 Q4
|
|
word: SLICEA.K0.INIT 1110101011000000
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R20C44:PLC2
|
|
arc: E1_H02E0501 W3_H06E0303
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: E3_H06E0203 H01E0001
|
|
arc: N1_V02N0201 H06E0103
|
|
arc: N1_V02N0301 H06E0003
|
|
arc: N1_V02N0501 H06W0303
|
|
arc: W1_H02W0301 N1_V02S0301
|
|
arc: W1_H02W0401 W3_H06E0203
|
|
arc: W1_H02W0501 W3_H06E0303
|
|
arc: W1_H02W0601 W3_H06E0303
|
|
|
|
.tile R20C45:PLC2
|
|
arc: N1_V02N0201 H06E0103
|
|
arc: N1_V02N0501 E1_H02W0501
|
|
|
|
.tile R20C46:PLC2
|
|
arc: E1_H02E0501 W1_H02E0501
|
|
|
|
.tile R20C47:PLC2
|
|
arc: E1_H02E0301 S1_V02N0301
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
arc: W1_H02W0501 E3_H06W0303
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
|
|
.tile R20C48:PLC2
|
|
arc: E1_H01E0001 W3_H06E0003
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: H00R0100 W1_H02E0501
|
|
arc: N1_V02N0201 W3_H06E0103
|
|
arc: V00B0000 H02W0401
|
|
arc: V00T0000 V02N0401
|
|
arc: V00T0100 V02S0701
|
|
arc: A0 E1_H01E0001
|
|
arc: A1 E1_H01E0001
|
|
arc: B0 H02E0301
|
|
arc: B1 H02E0301
|
|
arc: C0 V02N0401
|
|
arc: C1 V02N0401
|
|
arc: CE1 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V01S0100
|
|
arc: D1 V01S0100
|
|
arc: F0 F5A_SLICE
|
|
arc: LSR1 V00T0100
|
|
arc: M0 V00B0000
|
|
arc: M2 V00T0000
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXLSR1 LSR1
|
|
arc: N1_V02N0001 F0
|
|
arc: V01S0100 Q2
|
|
word: SLICEA.K0.INIT 1111011111010101
|
|
word: SLICEA.K1.INIT 1111001011110000
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R20C49:PLC2
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: W1_H02W0401 V02S0401
|
|
|
|
.tile R20C4:PLC2
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
|
|
.tile R20C50:PLC2
|
|
arc: E1_H02E0301 W3_H06E0003
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
|
|
.tile R20C52:PLC2
|
|
arc: H00L0100 W1_H02E0301
|
|
arc: V00T0000 V02S0601
|
|
arc: CE2 H00L0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: LSR0 V00T0000
|
|
arc: M5 H02W0001
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR2 LSR0
|
|
arc: N1_V01N0001 Q5
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R20C53:PLC2
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: N1_V02N0001 E1_H01W0000
|
|
arc: N1_V02N0101 H06E0103
|
|
arc: N1_V02N0201 E1_H01W0000
|
|
arc: N1_V02N0501 S1_V02N0501
|
|
arc: W1_H02W0001 V06N0003
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
arc: W3_H06W0303 E3_H06W0203
|
|
|
|
.tile R20C54:PLC2
|
|
arc: E1_H01E0001 W3_H06E0003
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
arc: H01W0000 W3_H06E0103
|
|
arc: N1_V02N0401 W3_H06E0203
|
|
|
|
.tile R20C55:PLC2
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: N1_V02N0001 H01E0001
|
|
arc: N1_V02N0201 H01E0001
|
|
|
|
.tile R20C56:PLC2
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
|
|
.tile R20C57:PLC2
|
|
arc: N1_V02N0401 H06E0203
|
|
|
|
.tile R20C59:PLC2
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
arc: W3_H06W0303 E3_H06W0203
|
|
|
|
.tile R20C5:PLC2
|
|
arc: W1_H02W0401 E3_H06W0203
|
|
|
|
.tile R20C61:PLC2
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
|
|
.tile R20C62:PLC2
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
|
|
.tile R20C65:PLC2
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
|
|
.tile R20C67:PLC2
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
|
|
.tile R20C68:PLC2
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
|
|
.tile R20C6:PLC2
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
|
|
.tile R20C71:PLC2
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
arc: W3_H06W0303 E3_H06W0203
|
|
|
|
.tile R20C73:PLC2
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
|
|
.tile R20C74:PLC2
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
|
|
.tile R20C77:PLC2
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
|
|
.tile R20C79:PLC2
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
|
|
.tile R20C7:PLC2
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
|
|
.tile R20C80:PLC2
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
|
|
.tile R20C83:PLC2
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
arc: W3_H06W0303 E3_H06W0203
|
|
|
|
.tile R20C85:PLC2
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
|
|
.tile R20C86:PLC2
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
|
|
.tile R20C87:PLC2
|
|
arc: E1_H02E0701 V02S0701
|
|
|
|
.tile R20C88:PLC2
|
|
arc: S3_V06S0203 H06E0203
|
|
arc: D6 V02N0601
|
|
arc: E1_H01E0101 F6
|
|
arc: F6 F6_SLICE
|
|
word: SLICED.K0.INIT 0000000011111111
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
|
|
.tile R20C8:PLC2
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
arc: W3_H06W0303 E3_H06W0203
|
|
|
|
.tile R20C9:PLC2
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
|
|
.tile R21C11:PLC2
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
arc: W3_H06W0103 E1_H01W0100
|
|
|
|
.tile R21C12:PLC2
|
|
arc: H01W0100 E3_H06W0303
|
|
|
|
.tile R21C13:PLC2
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
|
|
.tile R21C15:PLC2
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
|
|
.tile R21C17:PLC2
|
|
arc: S3_V06S0203 E3_H06W0203
|
|
arc: W3_H06W0303 E3_H06W0203
|
|
|
|
.tile R21C18:PLC2
|
|
arc: S3_V06S0003 E3_H06W0003
|
|
arc: W3_H06W0303 E3_H06W0203
|
|
|
|
.tile R21C19:PLC2
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
|
|
.tile R21C21:PLC2
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
|
|
.tile R21C23:PLC2
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
|
|
.tile R21C24:PLC2
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
|
|
.tile R21C25:PLC2
|
|
arc: N1_V02N0101 W3_H06E0103
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
arc: W3_H06W0303 E3_H06W0203
|
|
|
|
.tile R21C27:PLC2
|
|
arc: E1_H02E0101 W3_H06E0103
|
|
arc: E1_H02E0601 N1_V01S0000
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: N1_V02N0201 W3_H06E0103
|
|
arc: N1_V02N0401 E1_H02W0401
|
|
|
|
.tile R21C29:PLC2
|
|
arc: E1_H02E0101 V02S0101
|
|
arc: E1_H02E0401 W1_H02E0101
|
|
arc: E1_H02E0601 W1_H02E0601
|
|
arc: N1_V02N0701 E3_H06W0203
|
|
arc: W1_H02W0401 E3_H06W0203
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
|
|
.tile R21C2:PLC2
|
|
arc: N1_V02N0001 H06W0003
|
|
arc: S3_V06S0003 H06W0003
|
|
|
|
.tile R21C30:PLC2
|
|
arc: E1_H02E0001 V02S0001
|
|
arc: H00R0000 H02E0401
|
|
arc: N1_V02N0101 H06E0103
|
|
arc: V00T0000 H02W0201
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
arc: A0 H00R0000
|
|
arc: B0 H02E0101
|
|
arc: C0 H02E0601
|
|
arc: CE0 V02S0201
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02S0001
|
|
arc: F0 F0_SLICE
|
|
arc: LSR1 V00T0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: W3_H06W0003 Q0
|
|
word: SLICEA.K0.INIT 1111100010001000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R21C31:PLC2
|
|
arc: E1_H02E0201 N1_V02S0201
|
|
arc: E1_H02E0601 V02S0601
|
|
arc: H00R0100 V02S0701
|
|
arc: N1_V02N0001 H06W0003
|
|
arc: N1_V02N0701 H06W0203
|
|
arc: V00B0000 N1_V02S0201
|
|
arc: W1_H02W0201 N1_V02S0201
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
arc: A0 V02N0701
|
|
arc: B0 W1_H02E0101
|
|
arc: C0 E1_H01W0000
|
|
arc: CE0 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H02E0001
|
|
arc: F0 F0_SLICE
|
|
arc: LSR1 V00B0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: W3_H06W0003 Q0
|
|
word: SLICEA.K0.INIT 1111100010001000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R21C32:PLC2
|
|
arc: E1_H02E0201 V02S0201
|
|
arc: H00R0100 V02S0701
|
|
arc: N1_V02N0501 E1_H02W0501
|
|
arc: V00T0000 H02E0201
|
|
arc: A0 V02N0701
|
|
arc: B0 V02S0301
|
|
arc: C0 H02E0601
|
|
arc: CE0 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 E1_H02W0201
|
|
arc: F0 F0_SLICE
|
|
arc: H01W0000 Q0
|
|
arc: LSR0 V00T0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
word: SLICEA.K0.INIT 1100111000001010
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R21C33:PLC2
|
|
arc: E1_H02E0001 V02S0001
|
|
arc: V00B0100 V02S0301
|
|
arc: V00T0000 V02N0401
|
|
arc: V00T0100 H02W0101
|
|
arc: A0 V02N0701
|
|
arc: A1 V02N0701
|
|
arc: A5 E1_H01W0000
|
|
arc: B0 E1_H02W0101
|
|
arc: B1 E1_H02W0101
|
|
arc: B5 V02N0701
|
|
arc: C0 N1_V01N0001
|
|
arc: C1 N1_V01N0001
|
|
arc: C5 V02S0001
|
|
arc: CE2 V02S0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H02E0201
|
|
arc: D1 H02E0201
|
|
arc: D5 E1_H01W0100
|
|
arc: E1_H02E0201 F0
|
|
arc: E3_H06E0303 F5
|
|
arc: F0 F5A_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: LSR0 V00T0100
|
|
arc: M0 V00B0100
|
|
arc: M4 V00T0000
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR2 LSR0
|
|
arc: N1_V01N0001 Q4
|
|
word: SLICEC.K1.INIT 1001000000001001
|
|
word: SLICEA.K0.INIT 1011100011111111
|
|
word: SLICEA.K1.INIT 1011101010101010
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R21C34:PLC2
|
|
arc: E1_H02E0601 N1_V01S0000
|
|
arc: H00L0000 H02E0001
|
|
arc: H00R0100 E1_H02W0701
|
|
arc: N1_V02N0101 H02W0101
|
|
arc: N1_V02N0501 S1_V02N0501
|
|
arc: S3_V06S0103 N1_V01S0100
|
|
arc: V00B0000 N1_V02S0201
|
|
arc: V00B0100 V02S0301
|
|
arc: V00T0100 N1_V02S0701
|
|
arc: W1_H02W0101 N1_V02S0101
|
|
arc: W1_H02W0201 E1_H01W0000
|
|
arc: W3_H06W0003 E1_H01W0000
|
|
arc: A0 H00L0000
|
|
arc: A1 H00L0000
|
|
arc: A2 V02N0501
|
|
arc: A3 V02N0501
|
|
arc: B0 H02W0101
|
|
arc: B1 Q1
|
|
arc: B2 H02W0101
|
|
arc: B3 H02W0101
|
|
arc: C0 H00L0100
|
|
arc: C1 E1_H02W0601
|
|
arc: C2 V02S0401
|
|
arc: C3 V02S0401
|
|
arc: CE0 V02S0201
|
|
arc: CE1 H00R0100
|
|
arc: CE2 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 E1_H02W0201
|
|
arc: D1 H02W0201
|
|
arc: D2 E1_H02W0201
|
|
arc: D3 E1_H02W0201
|
|
arc: E1_H01E0101 F0
|
|
arc: E3_H06E0303 Q5
|
|
arc: F0 F5A_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: H00L0100 Q1
|
|
arc: H01W0000 Q3
|
|
arc: H01W0100 Q4
|
|
arc: LSR0 V00B0000
|
|
arc: LSR1 V00T0100
|
|
arc: M0 V00B0100
|
|
arc: M1 H02E0001
|
|
arc: M2 V00B0100
|
|
arc: M3 H02E0201
|
|
arc: M4 E1_H01E0101
|
|
arc: M5 V01S0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR1
|
|
arc: S3_V06S0003 Q3
|
|
arc: V01S0000 F2
|
|
arc: W1_H02W0501 Q5
|
|
arc: W3_H06W0203 Q4
|
|
word: SLICEA.K0.INIT 1011100011111111
|
|
word: SLICEA.K1.INIT 1010101011101010
|
|
word: SLICEB.K0.INIT 1011100011111111
|
|
word: SLICEB.K1.INIT 1011101010101010
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R21C35:PLC2
|
|
arc: E1_H02E0101 V02N0101
|
|
arc: E1_H02E0501 V02S0501
|
|
arc: E3_H06E0003 N1_V01S0000
|
|
arc: H00L0100 V02N0301
|
|
arc: N1_V02N0201 H06W0103
|
|
arc: N1_V02N0601 E1_H02W0601
|
|
arc: V00B0100 V02S0301
|
|
arc: V00T0100 N1_V02S0701
|
|
arc: W1_H02W0101 V02N0101
|
|
arc: W1_H02W0201 V02N0201
|
|
arc: W3_H06W0003 N1_V01S0000
|
|
arc: A0 H00L0100
|
|
arc: A1 V02S0501
|
|
arc: A4 F7
|
|
arc: B0 V02N0101
|
|
arc: B1 V02N0301
|
|
arc: B4 N1_V02S0501
|
|
arc: C0 H00R0100
|
|
arc: C1 H00R0100
|
|
arc: C4 H02E0601
|
|
arc: C7 V02N0201
|
|
arc: CE3 V02S0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H02W0201
|
|
arc: D1 V02N0201
|
|
arc: D4 N1_V02S0401
|
|
arc: D7 V02S0401
|
|
arc: E3_H06E0203 F7
|
|
arc: F0 F5A_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00R0100 Q7
|
|
arc: H01W0000 F7
|
|
arc: LSR1 V00T0100
|
|
arc: M0 V00B0100
|
|
arc: M7 H00L0100
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR3 LSR1
|
|
arc: N1_V01N0001 F4
|
|
arc: N1_V02N0001 F0
|
|
arc: N1_V02N0501 F7
|
|
arc: S3_V06S0203 F7
|
|
arc: W3_H06W0203 F7
|
|
word: SLICEC.K0.INIT 0100110001011111
|
|
word: SLICED.K1.INIT 0000111100000000
|
|
word: SLICEA.K0.INIT 1011100011111111
|
|
word: SLICEA.K1.INIT 1100110011101100
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R21C36:PLC2
|
|
arc: E1_H02E0001 N1_V01S0000
|
|
arc: E1_H02E0701 N1_V01S0100
|
|
arc: E3_H06E0303 N1_V01S0100
|
|
arc: H00L0000 N1_V02S0001
|
|
arc: H00L0100 H02E0101
|
|
arc: H00R0000 V02S0401
|
|
arc: N1_V02N0001 E1_H02W0001
|
|
arc: N1_V02N0101 E1_H01W0100
|
|
arc: N1_V02N0201 E1_H01W0000
|
|
arc: N1_V02N0301 H02W0301
|
|
arc: N1_V02N0701 H02W0701
|
|
arc: V00B0000 V02N0201
|
|
arc: V00T0000 H02W0201
|
|
arc: W1_H02W0201 N1_V01S0000
|
|
arc: W1_H02W0601 N1_V01S0000
|
|
arc: W1_H02W0701 E1_H02W0701
|
|
arc: A0 E1_H02W0501
|
|
arc: A1 H02W0701
|
|
arc: A2 H02E0501
|
|
arc: A3 H00L0100
|
|
arc: A6 H02W0701
|
|
arc: B0 V02N0101
|
|
arc: B1 H02E0101
|
|
arc: B2 H02E0101
|
|
arc: B3 H00R0100
|
|
arc: B6 N1_V01S0000
|
|
arc: C0 N1_V01S0100
|
|
arc: C1 H02W0401
|
|
arc: C2 H00R0100
|
|
arc: C3 H00L0000
|
|
arc: C6 V02S0001
|
|
arc: CE0 H02W0101
|
|
arc: CE3 V02S0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H02W0001
|
|
arc: D1 N1_V01S0000
|
|
arc: D2 N1_V02S0001
|
|
arc: D3 N1_V01S0000
|
|
arc: D6 E1_H01W0100
|
|
arc: E1_H01E0001 F2
|
|
arc: E1_H02E0101 F1
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: H00R0100 Q7
|
|
arc: LSR0 V00B0000
|
|
arc: M2 V00T0000
|
|
arc: M7 H00R0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR3 LSR0
|
|
arc: N1_V02N0601 F6
|
|
arc: W3_H06W0003 Q0
|
|
word: SLICEA.K0.INIT 1111111001001110
|
|
word: SLICEA.K1.INIT 1011100000000000
|
|
word: SLICED.K0.INIT 0000011101110111
|
|
word: SLICEB.K0.INIT 1111110101110101
|
|
word: SLICEB.K1.INIT 1111010011110000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R21C37:PLC2
|
|
arc: E1_H02E0001 V02S0001
|
|
arc: E1_H02E0101 V02S0101
|
|
arc: E1_H02E0401 N1_V01S0000
|
|
arc: E1_H02E0501 N1_V02S0501
|
|
arc: E1_H02E0601 V06S0303
|
|
arc: H00L0100 N1_V02S0101
|
|
arc: N1_V02N0101 E1_H01W0100
|
|
arc: N1_V02N0201 E1_H01W0000
|
|
arc: N1_V02N0301 E1_H01W0100
|
|
arc: N1_V02N0401 H01E0001
|
|
arc: N1_V02N0601 N1_V01S0000
|
|
arc: N1_V02N0701 S1_V02N0701
|
|
arc: V00B0100 H02W0501
|
|
arc: V00T0000 S1_V02N0601
|
|
arc: V00T0100 E1_H02W0101
|
|
arc: W1_H02W0001 N1_V02S0001
|
|
arc: W1_H02W0101 N1_V02S0101
|
|
arc: W1_H02W0201 N1_V02S0201
|
|
arc: W1_H02W0301 N1_V01S0100
|
|
arc: W1_H02W0701 S1_V02N0701
|
|
arc: A0 S1_V02N0701
|
|
arc: A2 H02E0701
|
|
arc: B0 H02E0101
|
|
arc: B2 N1_V02S0301
|
|
arc: B4 S1_V02N0701
|
|
arc: B7 H02W0301
|
|
arc: C0 H02W0401
|
|
arc: C2 V02S0401
|
|
arc: C4 E1_H01E0101
|
|
arc: CE0 V02S0201
|
|
arc: CE1 H00L0100
|
|
arc: CE2 V02S0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 N1_V02S0201
|
|
arc: D2 V00B0100
|
|
arc: D4 H02E0001
|
|
arc: D7 H02W0201
|
|
arc: E1_H01E0001 F7
|
|
arc: E1_H01E0101 F7
|
|
arc: F0 F0_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 F4
|
|
arc: H01W0100 Q0
|
|
arc: LSR0 V00T0100
|
|
arc: LSR1 V00T0100
|
|
arc: M4 V00T0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR0
|
|
arc: N1_V01N0001 Q0
|
|
arc: N1_V02N0001 Q0
|
|
arc: W1_H02W0401 Q4
|
|
arc: W1_H02W0601 F4
|
|
arc: W3_H06W0103 Q2
|
|
word: SLICEA.K0.INIT 1111111011111100
|
|
word: SLICEB.K0.INIT 1111010111101100
|
|
word: SLICED.K1.INIT 0000000000110011
|
|
word: SLICEC.K0.INIT 0000110000000000
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
|
|
.tile R21C38:PLC2
|
|
arc: E1_H02E0101 N1_V01S0100
|
|
arc: E1_H02E0501 N1_V02S0501
|
|
arc: E3_H06E0103 N1_V01S0100
|
|
arc: H00L0100 V02N0301
|
|
arc: H00R0100 N1_V02S0501
|
|
arc: N1_V02N0401 H01E0001
|
|
arc: N1_V02N0601 H02E0601
|
|
arc: S1_V02S0401 H06E0203
|
|
arc: S3_V06S0103 N1_V01S0100
|
|
arc: S3_V06S0203 H06E0203
|
|
arc: V00T0000 W1_H02E0001
|
|
arc: V00T0100 H02W0101
|
|
arc: W1_H02W0301 V02N0301
|
|
arc: W1_H02W0501 N1_V02S0501
|
|
arc: W1_H02W0701 N1_V02S0701
|
|
arc: A0 H00L0100
|
|
arc: A2 H02E0501
|
|
arc: A4 W1_H02E0701
|
|
arc: B0 V00T0000
|
|
arc: B2 H02E0101
|
|
arc: B4 N1_V02S0501
|
|
arc: B6 H02E0101
|
|
arc: C0 H02E0601
|
|
arc: C2 H02E0401
|
|
arc: C4 N1_V02S0201
|
|
arc: C6 V02S0201
|
|
arc: CE1 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 Q0
|
|
arc: D2 V02S0201
|
|
arc: D4 S1_V02N0601
|
|
arc: D6 H00R0100
|
|
arc: F0 F0_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: H00R0000 F4
|
|
arc: H01W0000 Q0
|
|
arc: H01W0100 Q2
|
|
arc: LSR1 V00T0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR1
|
|
arc: N1_V02N0001 Q0
|
|
arc: N1_V02N0201 Q2
|
|
arc: W1_H02W0001 Q2
|
|
arc: W1_H02W0201 Q0
|
|
arc: W1_H02W0401 F6
|
|
arc: W3_H06W0103 Q2
|
|
word: SLICED.K0.INIT 1111110000000000
|
|
word: SLICEA.K0.INIT 0011001100000010
|
|
word: SLICEB.K0.INIT 1010100010101010
|
|
word: SLICEC.K0.INIT 1011111111111111
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R21C39:PLC2
|
|
arc: E1_H02E0101 V02S0101
|
|
arc: E1_H02E0601 V02S0601
|
|
arc: H00R0100 V02S0701
|
|
arc: N1_V02N0501 W3_H06E0303
|
|
arc: N1_V02N0601 H06E0303
|
|
arc: S3_V06S0103 N1_V02S0101
|
|
arc: V00B0000 V02S0201
|
|
arc: V00B0100 N1_V02S0101
|
|
arc: W1_H02W0101 N1_V02S0101
|
|
arc: A0 F7
|
|
arc: A1 F7
|
|
arc: A2 H02W0701
|
|
arc: A7 H02E0501
|
|
arc: B0 H00R0100
|
|
arc: B2 E1_H01W0100
|
|
arc: B7 W1_H02E0101
|
|
arc: C0 E1_H02W0401
|
|
arc: C1 E1_H02W0401
|
|
arc: C2 V02S0601
|
|
arc: C7 W1_H02E0401
|
|
arc: CE2 H02E0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 N1_V01S0000
|
|
arc: D1 N1_V01S0000
|
|
arc: D2 V02S0001
|
|
arc: D7 W1_H02E0001
|
|
arc: E1_H01E0001 F2
|
|
arc: E1_H01E0101 F7
|
|
arc: E1_H02E0501 F7
|
|
arc: F0 F5A_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: LSR1 V00B0100
|
|
arc: M0 H02W0601
|
|
arc: M2 V00B0000
|
|
arc: M4 V00T0000
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR2 LSR1
|
|
arc: N1_V01N0001 Q4
|
|
arc: V00T0000 F0
|
|
word: SLICEA.K0.INIT 1111111011101110
|
|
word: SLICEA.K1.INIT 1111101010101010
|
|
word: SLICEB.K0.INIT 1110110010100000
|
|
word: SLICEB.K1.INIT 1111111111111111
|
|
word: SLICED.K1.INIT 1010101010100010
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R21C3:PLC2
|
|
arc: E3_H06E0203 W1_H02E0701
|
|
|
|
.tile R21C40:PLC2
|
|
arc: E1_H02E0301 S1_V02N0301
|
|
arc: E1_H02E0501 S1_V02N0501
|
|
arc: E1_H02E0701 E3_H06W0203
|
|
arc: H00L0000 N1_V02S0201
|
|
arc: H00R0100 V02N0501
|
|
arc: N1_V01N0101 N3_V06S0203
|
|
arc: N1_V02N0101 S1_V02N0001
|
|
arc: N1_V02N0201 H01E0001
|
|
arc: N1_V02N0301 E3_H06W0003
|
|
arc: N1_V02N0601 W3_H06E0303
|
|
arc: N1_V02N0701 N3_V06S0203
|
|
arc: S1_V02S0701 N3_V06S0203
|
|
arc: S3_V06S0203 N3_V06S0203
|
|
arc: V00B0000 N1_V02S0001
|
|
arc: V00B0100 S1_V02N0301
|
|
arc: V00T0100 V02N0701
|
|
arc: W1_H02W0601 V02S0601
|
|
arc: W1_H02W0701 V02N0701
|
|
arc: A0 H00L0000
|
|
arc: A1 V02N0701
|
|
arc: A2 V02N0701
|
|
arc: B0 H00R0100
|
|
arc: B1 V00T0000
|
|
arc: B2 V02N0101
|
|
arc: C0 S1_V02N0401
|
|
arc: C1 H00L0000
|
|
arc: C2 H02E0601
|
|
arc: CE0 W1_H02E0101
|
|
arc: CE1 H02E0101
|
|
arc: CE2 H02E0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H01E0101
|
|
arc: D1 H01E0101
|
|
arc: D2 H02W0001
|
|
arc: E1_H02E0601 Q4
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: H01W0100 Q1
|
|
arc: LSR0 V00B0000
|
|
arc: LSR1 V00B0000
|
|
arc: M2 V00T0100
|
|
arc: M4 V00B0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR1
|
|
arc: N1_V01N0001 Q0
|
|
arc: V00T0000 F2
|
|
arc: V01S0100 Q2
|
|
word: SLICEA.K0.INIT 1111111111111000
|
|
word: SLICEB.K0.INIT 1010000011000000
|
|
word: SLICEA.K1.INIT 1111111111101100
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R21C41:PLC2
|
|
arc: E1_H02E0001 V02S0001
|
|
arc: E1_H02E0401 W3_H06E0203
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: H00L0100 H02E0301
|
|
arc: H00R0100 V02S0701
|
|
arc: N1_V02N0001 V01N0001
|
|
arc: N1_V02N0101 E3_H06W0103
|
|
arc: N1_V02N0201 H06E0103
|
|
arc: N1_V02N0301 N1_V01S0100
|
|
arc: N1_V02N0401 W3_H06E0203
|
|
arc: N1_V02N0701 N1_V01S0100
|
|
arc: N3_V06N0003 W3_H06E0003
|
|
arc: V00B0000 V02S0201
|
|
arc: W1_H02W0001 V02N0001
|
|
arc: W1_H02W0401 W3_H06E0203
|
|
arc: A0 W1_H02E0501
|
|
arc: A2 V02S0501
|
|
arc: A4 V02S0301
|
|
arc: B0 N1_V02S0101
|
|
arc: B2 H02E0301
|
|
arc: B4 H02E0301
|
|
arc: C0 H00L0100
|
|
arc: C2 H02E0601
|
|
arc: C4 V00T0000
|
|
arc: CE0 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 F2
|
|
arc: D2 V02N0001
|
|
arc: D4 H02W0001
|
|
arc: F0 F0_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F4 F5C_SLICE
|
|
arc: LSR1 H02E0501
|
|
arc: M4 V00B0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: N1_V02N0601 F4
|
|
arc: V00T0000 Q0
|
|
word: SLICEB.K0.INIT 1000100010100000
|
|
word: SLICEA.K0.INIT 1111111111101010
|
|
word: SLICEC.K0.INIT 1111100010001000
|
|
word: SLICEC.K1.INIT 1111111111111111
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
|
|
.tile R21C42:PLC2
|
|
arc: E1_H02E0001 S1_V02N0001
|
|
arc: E1_H02E0601 V02S0601
|
|
arc: N1_V02N0401 H02E0401
|
|
arc: V00B0100 V02S0301
|
|
arc: W1_H02W0001 V02S0001
|
|
arc: A0 W1_H02E0701
|
|
arc: A1 W1_H02E0701
|
|
arc: B0 V02N0301
|
|
arc: B1 V02N0301
|
|
arc: C0 V02S0601
|
|
arc: C1 V02S0601
|
|
arc: CE0 V02S0201
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H02W0201
|
|
arc: D1 H02W0201
|
|
arc: E1_H01E0001 Q1
|
|
arc: E1_H01E0101 Q1
|
|
arc: F0 F5A_SLICE
|
|
arc: LSR1 V00B0100
|
|
arc: M0 H02W0601
|
|
arc: M1 H02E0001
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: N1_V02N0001 F0
|
|
word: SLICEA.K0.INIT 1010101010001111
|
|
word: SLICEA.K1.INIT 1011101010111111
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R21C43:PLC2
|
|
arc: H00R0000 E1_H02W0601
|
|
arc: N1_V02N0001 H02E0001
|
|
arc: N1_V02N0701 H06W0203
|
|
arc: V00B0000 N1_V02S0201
|
|
arc: V00T0000 W1_H02E0001
|
|
arc: W1_H02W0201 N1_V02S0201
|
|
arc: W1_H02W0601 N1_V01S0000
|
|
arc: A0 H01E0001
|
|
arc: A1 H00R0000
|
|
arc: B0 V02N0301
|
|
arc: B1 V00T0000
|
|
arc: C0 H02E0601
|
|
arc: C1 H02E0601
|
|
arc: D0 W1_H02E0001
|
|
arc: D1 H01E0101
|
|
arc: F0 F5A_SLICE
|
|
arc: M0 V00B0000
|
|
arc: N1_V02N0201 F0
|
|
word: SLICEA.K0.INIT 1110111100101111
|
|
word: SLICEA.K1.INIT 1101110011001100
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R21C45:PLC2
|
|
arc: W1_H02W0601 E1_H02W0301
|
|
|
|
.tile R21C46:PLC2
|
|
arc: W3_H06W0003 E1_H01W0000
|
|
arc: W3_H06W0203 E1_H01W0000
|
|
|
|
.tile R21C47:PLC2
|
|
arc: E1_H01E0001 E3_H06W0003
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: H01W0000 E3_H06W0103
|
|
arc: W1_H02W0301 V02N0301
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
|
|
.tile R21C48:PLC2
|
|
arc: N1_V02N0401 H01E0001
|
|
arc: N1_V02N0601 H01E0001
|
|
|
|
.tile R21C4:PLC2
|
|
arc: W3_H06W0203 E1_H01W0000
|
|
|
|
.tile R21C53:PLC2
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: N1_V02N0101 S1_V02N0001
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
|
|
.tile R21C59:PLC2
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: N1_V02N0301 S1_V02N0301
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
arc: W3_H06W0303 E3_H06W0203
|
|
|
|
.tile R21C5:PLC2
|
|
arc: H01W0000 E3_H06W0103
|
|
arc: S3_V06S0003 E3_H06W0003
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
|
|
.tile R21C65:PLC2
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
|
|
.tile R21C71:PLC2
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
arc: W3_H06W0303 E3_H06W0203
|
|
|
|
.tile R21C77:PLC2
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
|
|
.tile R21C7:PLC2
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
|
|
.tile R21C83:PLC2
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
|
|
.tile R21C88:PLC2
|
|
arc: N1_V02N0601 E1_H01W0000
|
|
|
|
.tile R21C9:PLC2
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
|
|
.tile R23C11:PLC2
|
|
arc: W3_H06W0303 E3_H06W0203
|
|
|
|
.tile R23C13:PLC2
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
|
|
.tile R23C17:PLC2
|
|
arc: S3_V06S0103 N3_V06S0003
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
|
|
.tile R23C19:PLC2
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
|
|
.tile R23C23:PLC2
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
|
|
.tile R23C25:PLC2
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
|
|
.tile R23C29:PLC2
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
|
|
.tile R23C2:PLC2
|
|
arc: S3_V06S0003 N3_V06S0003
|
|
|
|
.tile R23C31:PLC2
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
|
|
.tile R23C34:PLC2
|
|
arc: N1_V02N0501 S3_V06N0303
|
|
arc: S1_V02S0001 H06W0003
|
|
|
|
.tile R23C35:PLC2
|
|
arc: W3_H06W0103 V06S0103
|
|
|
|
.tile R23C37:PLC2
|
|
arc: E1_H02E0201 V02N0201
|
|
arc: E1_H02E0501 V06S0303
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: N1_V02N0601 S1_V02N0601
|
|
arc: N1_V02N0701 S1_V02N0601
|
|
arc: N3_V06N0303 S1_V02N0601
|
|
arc: W3_H06W0003 E1_H01W0000
|
|
|
|
.tile R23C38:PLC2
|
|
arc: E1_H02E0001 S1_V02N0001
|
|
arc: E1_H02E0401 V06S0203
|
|
arc: E1_H02E0501 V06S0303
|
|
arc: E1_H02E0601 V06S0303
|
|
arc: H00R0000 V02S0401
|
|
arc: H00R0100 V02S0701
|
|
arc: N1_V02N0601 N3_V06S0303
|
|
arc: V00B0000 S1_V02N0201
|
|
arc: V00B0100 H02E0501
|
|
arc: V00T0000 H02E0201
|
|
arc: A0 H00L0100
|
|
arc: B0 V00T0000
|
|
arc: C0 N1_V02S0401
|
|
arc: CE0 H00R0100
|
|
arc: CE1 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V00B0100
|
|
arc: F0 F0_SLICE
|
|
arc: H00L0100 Q3
|
|
arc: H01W0000 Q0
|
|
arc: LSR1 V00B0000
|
|
arc: M3 H02E0201
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR1
|
|
word: SLICEA.K0.INIT 1010000011101100
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R23C39:PLC2
|
|
arc: H00R0000 H02E0401
|
|
arc: H00R0100 H02E0501
|
|
arc: S1_V02S0101 N3_V06S0103
|
|
arc: S3_V06S0103 N3_V06S0103
|
|
arc: V00B0000 H02W0401
|
|
arc: V00B0100 W1_H02E0501
|
|
arc: V00T0100 V02S0701
|
|
arc: A0 S1_V02N0501
|
|
arc: B0 H01W0100
|
|
arc: C0 V02N0401
|
|
arc: CE0 H00R0000
|
|
arc: CE2 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V00B0100
|
|
arc: E3_H06E0003 Q0
|
|
arc: F0 F0_SLICE
|
|
arc: H01W0100 Q5
|
|
arc: LSR0 V00T0100
|
|
arc: LSR1 V00B0000
|
|
arc: M5 H02E0001
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR2 LSR1
|
|
word: SLICEA.K0.INIT 1100000011101010
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R23C40:PLC2
|
|
arc: H00R0000 W1_H02E0601
|
|
arc: H00R0100 V02S0501
|
|
arc: N1_V02N0001 E3_H06W0003
|
|
arc: N1_V02N0301 H06E0003
|
|
arc: N1_V02N0501 N3_V06S0303
|
|
arc: V00T0100 N1_V02S0701
|
|
arc: W1_H02W0401 N3_V06S0203
|
|
arc: A4 V02S0301
|
|
arc: B4 V02S0501
|
|
arc: C4 E1_H02W0601
|
|
arc: CE3 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D4 H01W0000
|
|
arc: F4 F4_SLICE
|
|
arc: H01W0000 Q7
|
|
arc: LSR1 V00T0100
|
|
arc: M7 H00R0100
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR3 LSR1
|
|
arc: N1_V02N0401 F4
|
|
word: SLICEC.K0.INIT 1101000010000000
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
|
|
.tile R23C42:PLC2
|
|
arc: N1_V02N0001 H06E0003
|
|
arc: W1_H02W0601 V06S0303
|
|
|
|
.tile R23C46:PLC2
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
|
|
.tile R23C4:PLC2
|
|
arc: W3_H06W0303 E1_H01W0100
|
|
|
|
.tile R23C52:PLC2
|
|
arc: W3_H06W0303 E3_H06W0203
|
|
|
|
.tile R23C53:PLC2
|
|
arc: N1_V02N0001 E3_H06W0003
|
|
arc: N3_V06N0003 E3_H06W0003
|
|
|
|
.tile R23C58:PLC2
|
|
arc: W3_H06W0203 E3_H06W0203
|
|
|
|
.tile R23C59:PLC2
|
|
arc: N1_V02N0301 E3_H06W0003
|
|
arc: N3_V06N0203 S3_V06N0203
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
|
|
.tile R23C5:PLC2
|
|
arc: H01W0100 E3_H06W0303
|
|
|
|
.tile R23C64:PLC2
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
|
|
.tile R23C65:PLC2
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
|
|
.tile R23C70:PLC2
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
|
|
.tile R23C71:PLC2
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
|
|
.tile R23C76:PLC2
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
|
|
.tile R23C77:PLC2
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
|
|
.tile R23C7:PLC2
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
|
|
.tile R23C82:PLC2
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
|
|
.tile R23C83:PLC2
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
|
|
.tile R23C88:PLC2
|
|
arc: S3_V06S0303 N3_V06S0203
|
|
arc: W3_H06W0303 E1_H01W0100
|
|
arc: D0 V02N0201
|
|
arc: E1_H01E0101 F0
|
|
arc: F0 F0_SLICE
|
|
word: SLICEA.K0.INIT 0000000011111111
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
|
|
.tile R24C34:PLC2
|
|
arc: E1_H02E0301 V06S0003
|
|
arc: E1_H02E0501 V01N0101
|
|
arc: H00R0000 S1_V02N0401
|
|
arc: V00T0100 V02N0701
|
|
arc: A0 S1_V02N0701
|
|
arc: B0 S1_V02N0301
|
|
arc: C0 S1_V02N0601
|
|
arc: CE0 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02S0001
|
|
arc: E3_H06E0003 Q0
|
|
arc: F0 F0_SLICE
|
|
arc: LSR0 V00T0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
word: SLICEA.K0.INIT 1110110010100000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R24C35:PLC2
|
|
arc: H00R0000 E1_H02W0401
|
|
arc: A0 V02N0701
|
|
arc: B0 H02E0301
|
|
arc: C0 V02N0401
|
|
arc: CE0 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 S1_V02N0001
|
|
arc: E3_H06E0003 Q0
|
|
arc: F0 F0_SLICE
|
|
arc: LSR1 H02E0501
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
word: SLICEA.K0.INIT 1100111011111010
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R24C37:PLC2
|
|
arc: N1_V02N0201 S1_V02N0701
|
|
arc: W1_H02W0401 V01N0001
|
|
|
|
.tile R24C38:PLC2
|
|
arc: E1_H02E0401 V06S0203
|
|
|
|
.tile R24C39:PLC2
|
|
arc: N1_V02N0401 H02E0401
|
|
|
|
.tile R24C40:PLC2
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
|
|
.tile R24C41:PLC2
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
|
|
.tile R24C46:PLC2
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
|
|
.tile R24C47:PLC2
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
|
|
.tile R24C52:PLC2
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
|
|
.tile R24C53:PLC2
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
|
|
.tile R24C58:PLC2
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
|
|
.tile R24C59:PLC2
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
|
|
.tile R24C64:PLC2
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
|
|
.tile R24C65:PLC2
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
|
|
.tile R24C70:PLC2
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
|
|
.tile R24C71:PLC2
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
|
|
.tile R24C76:PLC2
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
|
|
.tile R24C77:PLC2
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
|
|
.tile R24C82:PLC2
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
|
|
.tile R24C83:PLC2
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
|
|
.tile R24C88:PLC2
|
|
arc: N1_V02N0201 H02W0201
|
|
arc: S3_V06S0203 W3_H06E0203
|
|
|
|
.tile R25C10:PLC2
|
|
arc: S3_V06S0203 N3_V06S0103
|
|
|
|
.tile R25C31:PLC2
|
|
arc: N3_V06N0303 S3_V06N0303
|
|
|
|
.tile R25C33:PLC2
|
|
arc: E1_H02E0701 V06N0203
|
|
|
|
.tile R25C34:PLC2
|
|
arc: E1_H02E0101 V01N0101
|
|
arc: E1_H02E0201 N3_V06S0103
|
|
arc: N1_V01N0101 N3_V06S0203
|
|
arc: N1_V02N0701 N3_V06S0203
|
|
arc: N3_V06N0003 S3_V06N0303
|
|
arc: S1_V02S0701 N3_V06S0203
|
|
|
|
.tile R25C35:PLC2
|
|
arc: N1_V02N0401 H06W0203
|
|
arc: N1_V02N0701 W1_H02E0701
|
|
arc: V00T0000 H02E0201
|
|
arc: A0 V02N0501
|
|
arc: B0 V02N0301
|
|
arc: C0 V02N0601
|
|
arc: CE0 H02E0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02N0001
|
|
arc: E3_H06E0003 Q0
|
|
arc: F0 F0_SLICE
|
|
arc: LSR0 V00T0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
word: SLICEA.K0.INIT 1110110010100000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R25C37:PLC2
|
|
arc: E1_H02E0201 N3_V06S0103
|
|
arc: N1_V01N0001 N3_V06S0003
|
|
arc: N1_V02N0601 S3_V06N0303
|
|
arc: N3_V06N0303 S3_V06N0303
|
|
arc: S1_V02S0201 N3_V06S0103
|
|
|
|
.tile R25C38:PLC2
|
|
arc: E1_H02E0501 N3_V06S0303
|
|
arc: N1_V02N0001 N3_V06S0003
|
|
arc: N1_V02N0201 H02E0201
|
|
arc: S1_V02S0201 H02E0201
|
|
arc: W3_H06W0203 N3_V06S0203
|
|
|
|
.tile R25C39:PLC2
|
|
arc: N1_V02N0501 H02E0501
|
|
arc: S1_V02S0401 N1_V02S0101
|
|
|
|
.tile R25C40:PLC2
|
|
arc: N3_V06N0303 S3_V06N0303
|
|
arc: S1_V02S0301 N3_V06S0003
|
|
|
|
.tile R25C41:PLC2
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: N3_V06N0003 S3_V06N0303
|
|
|
|
.tile R25C47:PLC2
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
|
|
.tile R25C53:PLC2
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
|
|
.tile R25C59:PLC2
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: N3_V06N0103 S3_V06N0103
|
|
arc: N3_V06N0303 E3_H06W0303
|
|
|
|
.tile R25C65:PLC2
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
|
|
.tile R25C71:PLC2
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
|
|
.tile R25C77:PLC2
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
|
|
.tile R25C83:PLC2
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
|
|
.tile R25C87:PLC2
|
|
arc: S3_V06S0103 N3_V06S0003
|
|
arc: S3_V06S0203 N3_V06S0103
|
|
|
|
.tile R26C10:PLC2
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
|
|
.tile R26C13:PLC2
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
|
|
.tile R26C16:PLC2
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
|
|
.tile R26C19:PLC2
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
|
|
.tile R26C22:PLC2
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
|
|
.tile R26C25:PLC2
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
|
|
.tile R26C28:PLC2
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
|
|
.tile R26C2:PLC2
|
|
arc: S3_V06S0203 N3_V06S0103
|
|
arc: W1_H02W0501 N3_V06S0303
|
|
arc: D3 V02N0001
|
|
arc: F3 F3_SLICE
|
|
arc: H01W0100 F3
|
|
word: SLICEB.K1.INIT 0000000011111111
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
|
|
.tile R26C31:PLC2
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
|
|
.tile R26C34:PLC2
|
|
arc: N1_V01N0101 N3_V06S0203
|
|
arc: N1_V02N0301 E1_H02W0301
|
|
arc: N1_V02N0401 N3_V06S0203
|
|
arc: N1_V02N0601 E1_H02W0601
|
|
arc: N1_V02N0701 H06E0203
|
|
arc: S1_V02S0701 N3_V06S0203
|
|
arc: V00T0100 V02S0701
|
|
arc: A0 V02N0701
|
|
arc: B0 S1_V02N0101
|
|
arc: C0 E1_H02W0601
|
|
arc: CE0 V02N0201
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 E1_H02W0001
|
|
arc: F0 F0_SLICE
|
|
arc: LSR0 V00T0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: W3_H06W0003 Q0
|
|
word: SLICEA.K0.INIT 1110101011000000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R26C35:PLC2
|
|
arc: N1_V02N0001 H02W0001
|
|
arc: N1_V02N0301 H06W0003
|
|
arc: N1_V02N0501 E1_H02W0501
|
|
arc: N1_V02N0601 H02W0601
|
|
|
|
.tile R26C36:PLC2
|
|
arc: S3_V06S0103 N3_V06S0003
|
|
arc: S3_V06S0303 N3_V06S0303
|
|
arc: W1_H02W0001 N3_V06S0003
|
|
arc: W1_H02W0301 N3_V06S0003
|
|
arc: W1_H02W0601 N3_V06S0303
|
|
|
|
.tile R26C37:PLC2
|
|
arc: E1_H02E0401 V02N0401
|
|
arc: E1_H02E0501 S1_V02N0501
|
|
arc: E1_H02E0601 N3_V06S0303
|
|
arc: N1_V02N0701 W3_H06E0203
|
|
arc: S1_V02S0601 N3_V06S0303
|
|
arc: S3_V06S0003 N3_V06S0303
|
|
arc: W1_H02W0501 S1_V02N0501
|
|
|
|
.tile R26C38:PLC2
|
|
arc: H00R0000 H02E0601
|
|
arc: S1_V02S0401 N3_V06S0203
|
|
arc: S1_V02S0501 N3_V06S0303
|
|
arc: S1_V02S0701 N3_V06S0203
|
|
arc: S3_V06S0303 N3_V06S0303
|
|
arc: V00B0000 V02S0201
|
|
arc: A0 H02E0501
|
|
arc: B0 V01N0001
|
|
arc: C0 V02N0401
|
|
arc: CE0 V02N0201
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H00R0000
|
|
arc: F0 F0_SLICE
|
|
arc: LSR0 V00B0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: W3_H06W0003 Q0
|
|
word: SLICEA.K0.INIT 1100000011101010
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R26C39:PLC2
|
|
arc: H00R0000 V02S0401
|
|
arc: CE2 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E3_H06E0203 Q4
|
|
arc: LSR1 H02W0301
|
|
arc: M4 W1_H02E0401
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR2 LSR1
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R26C40:PLC2
|
|
arc: W1_H02W0301 V02S0301
|
|
|
|
.tile R26C41:PLC2
|
|
arc: N3_V06N0003 E3_H06W0003
|
|
arc: N3_V06N0303 E3_H06W0303
|
|
|
|
.tile R26C45:PLC2
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
|
|
.tile R26C47:PLC2
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
|
|
.tile R26C4:PLC2
|
|
arc: S3_V06S0203 E3_H06W0203
|
|
|
|
.tile R26C51:PLC2
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
|
|
.tile R26C53:PLC2
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
|
|
.tile R26C57:PLC2
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
|
|
.tile R26C59:PLC2
|
|
arc: W3_H06W0303 E3_H06W0203
|
|
|
|
.tile R26C63:PLC2
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
|
|
.tile R26C65:PLC2
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
|
|
.tile R26C69:PLC2
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
|
|
.tile R26C71:PLC2
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
|
|
.tile R26C75:PLC2
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
|
|
.tile R26C77:PLC2
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
|
|
.tile R26C7:PLC2
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
|
|
.tile R26C81:PLC2
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
|
|
.tile R26C83:PLC2
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
|
|
.tile R26C87:PLC2
|
|
arc: S3_V06S0103 W3_H06E0103
|
|
|
|
.tile R26C88:PLC2
|
|
arc: S3_V06S0303 N3_V06S0203
|
|
|
|
.tile R27C13:PLC2
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
|
|
.tile R27C17:PLC2
|
|
arc: S3_V06S0203 N3_V06S0203
|
|
|
|
.tile R27C18:PLC2
|
|
arc: S3_V06S0003 N3_V06S0003
|
|
|
|
.tile R27C19:PLC2
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
|
|
.tile R27C25:PLC2
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
|
|
.tile R27C2:PLC2
|
|
arc: N1_V02N0001 N3_V06S0003
|
|
arc: S1_V02S0001 N3_V06S0003
|
|
|
|
.tile R27C31:PLC2
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
|
|
.tile R27C34:PLC2
|
|
arc: N1_V02N0201 N3_V06S0103
|
|
arc: N1_V02N0701 H06W0203
|
|
arc: S1_V02S0701 N1_V02S0701
|
|
|
|
.tile R27C35:PLC2
|
|
arc: E1_H02E0401 N3_V06S0203
|
|
|
|
.tile R27C37:PLC2
|
|
arc: E1_H02E0201 N1_V02S0201
|
|
arc: E1_H02E0501 W1_H02E0401
|
|
arc: E1_H02E0601 V02S0601
|
|
arc: N1_V02N0401 W3_H06E0203
|
|
arc: S1_V02S0301 N1_V02S0201
|
|
arc: W3_H06W0203 E1_H01W0000
|
|
|
|
.tile R27C38:PLC2
|
|
arc: H00R0000 V02S0401
|
|
arc: H00R0100 V02S0501
|
|
arc: N1_V02N0201 N3_V06S0103
|
|
arc: N1_V02N0401 N3_V06S0203
|
|
arc: S1_V02S0701 N3_V06S0203
|
|
arc: V00B0000 N1_V02S0201
|
|
arc: V00T0000 H02E0201
|
|
arc: V00T0100 V02N0501
|
|
arc: A0 H02E0501
|
|
arc: B0 V01N0001
|
|
arc: C0 H02E0601
|
|
arc: CE0 H00R0000
|
|
arc: CE1 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02N0001
|
|
arc: F0 F0_SLICE
|
|
arc: H01W0000 Q0
|
|
arc: LSR0 V00T0000
|
|
arc: LSR1 V00B0000
|
|
arc: M2 V00T0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR0
|
|
arc: N1_V01N0001 Q2
|
|
word: SLICEA.K0.INIT 1000111110001000
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R27C39:PLC2
|
|
arc: S1_V02S0101 N3_V06S0103
|
|
arc: S1_V02S0701 H02W0701
|
|
|
|
.tile R27C3:PLC2
|
|
arc: S1_V02S0001 E1_H02W0001
|
|
|
|
.tile R27C40:PLC2
|
|
arc: S1_V02S0301 N1_V02S0301
|
|
arc: W1_H02W0701 N3_V06S0203
|
|
|
|
.tile R27C5:PLC2
|
|
arc: W1_H02W0001 N3_V06S0003
|
|
|
|
.tile R27C7:PLC2
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
|
|
.tile R27C88:PLC2
|
|
arc: E1_H02E0701 V06S0203
|
|
|
|
.tile R28C12:PLC2
|
|
arc: S3_V06S0003 H06W0003
|
|
|
|
.tile R28C13:PLC2
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
|
|
.tile R28C15:PLC2
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
|
|
.tile R28C19:PLC2
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
|
|
.tile R28C21:PLC2
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
|
|
.tile R28C25:PLC2
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
|
|
.tile R28C27:PLC2
|
|
arc: N3_V06N0303 S3_V06N0303
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
|
|
.tile R28C31:PLC2
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
arc: N3_V06N0103 S3_V06N0003
|
|
|
|
.tile R28C32:PLC2
|
|
arc: N3_V06N0103 S3_V06N0103
|
|
arc: N3_V06N0203 S3_V06N0103
|
|
arc: N3_V06N0303 S3_V06N0203
|
|
|
|
.tile R28C33:PLC2
|
|
arc: N3_V06N0203 S3_V06N0103
|
|
arc: W3_H06W0303 E3_H06W0203
|
|
|
|
.tile R28C34:PLC2
|
|
arc: H00R0100 N1_V02S0701
|
|
arc: N1_V02N0101 S3_V06N0103
|
|
arc: N3_V06N0003 S3_V06N0003
|
|
arc: N3_V06N0303 S3_V06N0203
|
|
arc: S1_V02S0201 N1_V02S0701
|
|
arc: V00T0100 V02S0701
|
|
arc: A2 V02N0701
|
|
arc: B2 E1_H02W0301
|
|
arc: C2 V02N0601
|
|
arc: CE1 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D2 V02N0201
|
|
arc: E3_H06E0103 Q2
|
|
arc: F2 F2_SLICE
|
|
arc: LSR0 V00T0100
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXLSR1 LSR0
|
|
word: SLICEB.K0.INIT 1110110010100000
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R28C35:PLC2
|
|
arc: N3_V06N0103 E3_H06W0103
|
|
|
|
.tile R28C36:PLC2
|
|
arc: W1_H02W0301 E1_H02W0201
|
|
|
|
.tile R28C37:PLC2
|
|
arc: E1_H02E0001 S3_V06N0003
|
|
arc: E1_H02E0301 V02S0301
|
|
arc: E1_H02E0501 W3_H06E0303
|
|
arc: E1_H02E0601 N1_V02S0601
|
|
arc: N1_V02N0501 W3_H06E0303
|
|
|
|
.tile R28C38:PLC2
|
|
arc: H00R0000 N1_V02S0401
|
|
arc: H00R0100 N1_V02S0501
|
|
arc: N1_V02N0001 H02E0001
|
|
arc: N1_V02N0501 H02E0501
|
|
arc: S1_V02S0201 N1_V02S0701
|
|
arc: V00T0000 H02E0001
|
|
arc: A0 V02S0701
|
|
arc: B0 V02N0101
|
|
arc: C0 H02E0601
|
|
arc: CE0 H00R0000
|
|
arc: CE1 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02N0001
|
|
arc: F0 F0_SLICE
|
|
arc: LSR1 H02E0301
|
|
arc: M2 V00T0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR1
|
|
arc: N1_V01N0001 Q2
|
|
arc: W1_H02W0201 Q0
|
|
word: SLICEA.K0.INIT 1010111000001100
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R28C39:PLC2
|
|
arc: V00B0000 V02N0001
|
|
arc: V00T0100 V02S0701
|
|
arc: CE2 S1_V02N0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: LSR1 V00T0100
|
|
arc: M4 V00B0000
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR2 LSR1
|
|
arc: W3_H06W0203 Q4
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R28C40:PLC2
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: N3_V06N0203 S3_V06N0103
|
|
|
|
.tile R28C41:PLC2
|
|
arc: N3_V06N0003 E3_H06W0003
|
|
arc: N3_V06N0203 S3_V06N0203
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
|
|
.tile R28C46:PLC2
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
|
|
.tile R28C47:PLC2
|
|
arc: N3_V06N0003 E3_H06W0003
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
|
|
.tile R28C52:PLC2
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
|
|
.tile R28C53:PLC2
|
|
arc: N3_V06N0303 E3_H06W0303
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
|
|
.tile R28C58:PLC2
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
|
|
.tile R28C59:PLC2
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
|
|
.tile R28C64:PLC2
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
|
|
.tile R28C65:PLC2
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
|
|
.tile R28C70:PLC2
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
|
|
.tile R28C71:PLC2
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
|
|
.tile R28C76:PLC2
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
|
|
.tile R28C77:PLC2
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
|
|
.tile R28C7:PLC2
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
|
|
.tile R28C82:PLC2
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
|
|
.tile R28C83:PLC2
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
|
|
.tile R28C88:PLC2
|
|
arc: S3_V06S0203 W3_H06E0203
|
|
|
|
.tile R29C10:PLC2
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
|
|
.tile R29C13:PLC2
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
|
|
.tile R29C16:PLC2
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
|
|
.tile R29C17:PLC2
|
|
arc: S3_V06S0103 N3_V06S0103
|
|
|
|
.tile R29C19:PLC2
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
|
|
.tile R29C22:PLC2
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
|
|
.tile R29C25:PLC2
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
|
|
.tile R29C28:PLC2
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
|
|
.tile R29C2:PLC2
|
|
arc: S3_V06S0003 N3_V06S0003
|
|
arc: W1_H02W0501 E1_H02W0401
|
|
arc: D0 N1_V02S0001
|
|
arc: F0 F0_SLICE
|
|
arc: H01W0100 F0
|
|
word: SLICEA.K0.INIT 0000000011111111
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
|
|
.tile R29C31:PLC2
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
|
|
.tile R29C34:PLC2
|
|
arc: N1_V02N0201 E1_H02W0201
|
|
arc: N1_V02N0601 E1_H02W0601
|
|
arc: N1_V02N0701 H06E0203
|
|
arc: N3_V06N0303 S1_V02N0501
|
|
arc: V00T0100 N1_V02S0701
|
|
arc: A0 V02N0501
|
|
arc: B0 E1_H02W0101
|
|
arc: C0 E1_H02W0601
|
|
arc: CE0 V02S0201
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 E1_H02W0201
|
|
arc: F0 F0_SLICE
|
|
arc: LSR1 V00T0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: W3_H06W0003 Q0
|
|
word: SLICEA.K0.INIT 1110110010100000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R29C36:PLC2
|
|
arc: W1_H02W0101 E1_H02W0001
|
|
arc: W1_H02W0201 V06S0103
|
|
arc: W1_H02W0601 V06S0303
|
|
|
|
.tile R29C37:PLC2
|
|
arc: E1_H01E0101 W3_H06E0203
|
|
arc: E1_H02E0001 V06S0003
|
|
arc: E1_H02E0301 N1_V02S0301
|
|
arc: E1_H02E0401 W3_H06E0203
|
|
|
|
.tile R29C38:PLC2
|
|
arc: E1_H02E0501 V06S0303
|
|
arc: H00L0100 V02N0301
|
|
arc: N1_V02N0001 E1_H01W0000
|
|
arc: N1_V02N0101 H01E0101
|
|
arc: V00B0100 V02N0301
|
|
arc: V00T0100 H02W0101
|
|
arc: A0 N1_V02S0701
|
|
arc: B0 V00B0000
|
|
arc: C0 H00L0100
|
|
arc: CE0 V02S0201
|
|
arc: CE2 V02N0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H02E0001
|
|
arc: F0 F0_SLICE
|
|
arc: LSR0 V00T0100
|
|
arc: LSR1 H02E0301
|
|
arc: M4 V00B0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR2 LSR0
|
|
arc: V00B0000 Q4
|
|
arc: W1_H02W0001 Q0
|
|
word: SLICEA.K0.INIT 1000100011111000
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R29C39:PLC2
|
|
arc: H00R0000 W1_H02E0401
|
|
arc: H00R0100 H02E0501
|
|
arc: N1_V02N0001 E3_H06W0003
|
|
arc: V01S0000 N3_V06S0103
|
|
arc: W1_H02W0101 N1_V02S0101
|
|
arc: CE3 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: H01W0000 Q7
|
|
arc: LSR1 H02W0301
|
|
arc: M7 H00R0000
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR3 LSR1
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R29C3:PLC2
|
|
arc: C7 N1_V02S0001
|
|
arc: F7 F7_SLICE
|
|
arc: W1_H02W0701 F7
|
|
word: SLICED.K1.INIT 0000111100001111
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
|
|
.tile R29C40:PLC2
|
|
arc: W1_H02W0301 N1_V02S0301
|
|
|
|
.tile R29C45:PLC2
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
|
|
.tile R29C4:PLC2
|
|
arc: W1_H02W0401 V06S0203
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
|
|
.tile R29C51:PLC2
|
|
arc: W3_H06W0303 E3_H06W0203
|
|
|
|
.tile R29C57:PLC2
|
|
arc: W3_H06W0203 E3_H06W0203
|
|
|
|
.tile R29C59:PLC2
|
|
arc: N3_V06N0203 E3_H06W0203
|
|
|
|
.tile R29C63:PLC2
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
|
|
.tile R29C65:PLC2
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
|
|
.tile R29C69:PLC2
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
|
|
.tile R29C71:PLC2
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
|
|
.tile R29C75:PLC2
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
|
|
.tile R29C77:PLC2
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
|
|
.tile R29C7:PLC2
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
|
|
.tile R29C81:PLC2
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
|
|
.tile R29C83:PLC2
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
|
|
.tile R29C87:PLC2
|
|
arc: W3_H06W0303 E1_H02W0501
|
|
|
|
.tile R29C88:PLC2
|
|
arc: S3_V06S0303 N3_V06S0303
|
|
arc: D1 H02W0201
|
|
arc: D4 H02W0201
|
|
arc: D7 H02W0201
|
|
arc: E1_H01E0101 F4
|
|
arc: E1_H02E0301 F1
|
|
arc: E1_H02E0501 F7
|
|
arc: F1 F1_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F7 F7_SLICE
|
|
word: SLICEA.K1.INIT 0000000011111111
|
|
word: SLICEC.K0.INIT 0000000011111111
|
|
word: SLICED.K1.INIT 0000000011111111
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
|
|
.tile R2C22:PLC2
|
|
arc: E1_H01E0101 F4
|
|
arc: F4 F4_SLICE
|
|
word: SLICEC.K0.INIT 1111111111111111
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
|
|
.tile R2C23:PLC2
|
|
arc: N1_V02N0701 H01E0101
|
|
|
|
.tile R2C28:PLC2
|
|
arc: N1_V02N0701 S3_V06N0203
|
|
|
|
.tile R2C34:PLC2
|
|
arc: N1_V02N0601 S1_V02N0301
|
|
|
|
.tile R2C40:PLC2
|
|
arc: E3_H06E0303 S3_V06N0303
|
|
|
|
.tile R2C42:PLC2
|
|
arc: D5 V02N0401
|
|
arc: D7 V02N0401
|
|
arc: F5 F5_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: N1_V01N0101 F5
|
|
arc: N1_V02N0701 F7
|
|
word: SLICEC.K1.INIT 0000000011111111
|
|
word: SLICED.K1.INIT 0000000011111111
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
|
|
.tile R2C43:PLC2
|
|
arc: N1_V02N0501 H06E0303
|
|
|
|
.tile R2C44:PLC2
|
|
arc: N1_V02N0701 S3_V06N0203
|
|
arc: C2 V02N0401
|
|
arc: F2 F2_SLICE
|
|
arc: N1_V01N0001 F2
|
|
word: SLICEB.K0.INIT 0000111100001111
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
|
|
.tile R2C45:PLC2
|
|
arc: C1 V02N0401
|
|
arc: F1 F1_SLICE
|
|
arc: N1_V02N0301 F1
|
|
word: SLICEA.K1.INIT 0000111100001111
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
|
|
.tile R2C51:PLC2
|
|
arc: N1_V02N0501 S1_V02N0401
|
|
|
|
.tile R30C34:PLC2
|
|
arc: N1_V02N0501 S1_V02N0401
|
|
|
|
.tile R30C38:PLC2
|
|
arc: N1_V02N0301 S1_V02N0201
|
|
arc: N1_V02N0601 S1_V02N0601
|
|
|
|
.tile R30C39:PLC2
|
|
arc: N1_V02N0601 N1_V01S0000
|
|
|
|
.tile R31C10:PLC2
|
|
arc: S3_V06S0303 N3_V06S0203
|
|
|
|
.tile R31C13:PLC2
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
|
|
.tile R31C19:PLC2
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
|
|
.tile R31C25:PLC2
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
|
|
.tile R31C31:PLC2
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
arc: N3_V06N0303 W3_H06E0303
|
|
|
|
.tile R31C34:PLC2
|
|
arc: N1_V02N0501 H06E0303
|
|
arc: N3_V06N0303 S3_V06N0303
|
|
|
|
.tile R31C37:PLC2
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
arc: N3_V06N0303 S3_V06N0303
|
|
|
|
.tile R31C40:PLC2
|
|
arc: N3_V06N0303 H06E0303
|
|
|
|
.tile R31C41:PLC2
|
|
arc: N3_V06N0303 S3_V06N0303
|
|
|
|
.tile R31C59:PLC2
|
|
arc: N3_V06N0103 E3_H06W0103
|
|
|
|
.tile R31C65:PLC2
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
|
|
.tile R31C71:PLC2
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
|
|
.tile R31C77:PLC2
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
|
|
.tile R31C7:PLC2
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
|
|
.tile R31C83:PLC2
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
|
|
.tile R31C87:PLC2
|
|
arc: E1_H02E0401 N3_V06S0203
|
|
arc: S3_V06S0203 N3_V06S0103
|
|
|
|
.tile R31C88:PLC2
|
|
arc: E1_H02E0701 V06S0203
|
|
|
|
.tile R32C2:PLC2
|
|
arc: S3_V06S0203 N3_V06S0203
|
|
arc: W1_H02W0301 V06S0003
|
|
|
|
.tile R32C34:PLC2
|
|
arc: N1_V02N0401 E1_H01W0000
|
|
|
|
.tile R32C35:PLC2
|
|
arc: H01W0000 E3_H06W0103
|
|
|
|
.tile R32C38:PLC2
|
|
arc: N1_V02N0201 H06W0103
|
|
arc: N1_V02N0601 N3_V06S0303
|
|
|
|
.tile R32C41:PLC2
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
|
|
.tile R32C47:PLC2
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
|
|
.tile R32C53:PLC2
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
|
|
.tile R32C59:PLC2
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
|
|
.tile R32C65:PLC2
|
|
arc: W3_H06W0303 E3_H06W0203
|
|
|
|
.tile R32C71:PLC2
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
|
|
.tile R32C77:PLC2
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
|
|
.tile R32C83:PLC2
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
|
|
.tile R32C87:PLC2
|
|
arc: S3_V06S0203 N3_V06S0103
|
|
|
|
.tile R32C88:PLC2
|
|
arc: E1_H02E0501 V06S0303
|
|
arc: S3_V06S0303 N3_V06S0303
|
|
|
|
.tile R33C17:PLC2
|
|
arc: S3_V06S0303 N3_V06S0203
|
|
|
|
.tile R33C18:PLC2
|
|
arc: S3_V06S0103 N3_V06S0003
|
|
|
|
.tile R35C17:PLC2
|
|
arc: S3_V06S0103 N3_V06S0103
|
|
|
|
.tile R35C2:PLC2
|
|
arc: W1_H02W0701 V06S0203
|
|
|
|
.tile R35C87:PLC2
|
|
arc: E1_H02E0701 V06S0203
|
|
|
|
.tile R37C10:PLC2
|
|
arc: S3_V06S0303 N3_V06S0303
|
|
|
|
.tile R37C13:PLC2
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
|
|
.tile R37C19:PLC2
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
|
|
.tile R37C25:PLC2
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
|
|
.tile R37C31:PLC2
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
|
|
.tile R37C34:PLC2
|
|
arc: N3_V06N0303 H06E0303
|
|
|
|
.tile R37C37:PLC2
|
|
arc: N3_V06N0303 W3_H06E0303
|
|
|
|
.tile R37C41:PLC2
|
|
arc: N3_V06N0303 E3_H06W0303
|
|
|
|
.tile R37C47:PLC2
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
|
|
.tile R37C53:PLC2
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
|
|
.tile R37C59:PLC2
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
|
|
.tile R37C65:PLC2
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
|
|
.tile R37C71:PLC2
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
|
|
.tile R37C77:PLC2
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
|
|
.tile R37C7:PLC2
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
|
|
.tile R37C83:PLC2
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
|
|
.tile R38C88:PLC2
|
|
arc: E1_H02E0501 N3_V06S0303
|
|
|
|
.tile R39C17:PLC2
|
|
arc: S3_V06S0303 N3_V06S0303
|
|
|
|
.tile R39C18:PLC2
|
|
arc: S3_V06S0203 N3_V06S0103
|
|
|
|
.tile R3C20:PLC2
|
|
arc: N1_V02N0701 H06W0203
|
|
|
|
.tile R3C23:PLC2
|
|
arc: W3_H06W0203 S3_V06N0203
|
|
|
|
.tile R3C24:PLC2
|
|
arc: N1_V02N0701 H06W0203
|
|
|
|
.tile R3C27:PLC2
|
|
arc: W3_H06W0203 S3_V06N0203
|
|
|
|
.tile R3C33:PLC2
|
|
arc: N1_V02N0201 H06W0103
|
|
|
|
.tile R3C36:PLC2
|
|
arc: W3_H06W0103 S3_V06N0103
|
|
|
|
.tile R3C38:PLC2
|
|
arc: N1_V02N0501 S3_V06N0303
|
|
|
|
.tile R3C39:PLC2
|
|
arc: N1_V02N0501 S1_V02N0401
|
|
arc: N1_V02N0701 S3_V06N0203
|
|
|
|
.tile R3C41:PLC2
|
|
arc: E1_H02E0401 S3_V06N0203
|
|
arc: E3_H06E0203 S3_V06N0203
|
|
|
|
.tile R3C42:PLC2
|
|
arc: N1_V02N0401 H02E0401
|
|
arc: N1_V02N0501 S1_V02N0401
|
|
|
|
.tile R3C43:PLC2
|
|
arc: E1_H02E0401 W1_H02E0401
|
|
|
|
.tile R3C44:PLC2
|
|
arc: N1_V02N0401 H06E0203
|
|
|
|
.tile R3C45:PLC2
|
|
arc: N1_V02N0401 W1_H02E0401
|
|
|
|
.tile R3C62:PLC2
|
|
arc: N1_V02N0501 S3_V06N0303
|
|
|
|
.tile R40C12:PLC2
|
|
arc: S3_V06S0203 N3_V06S0103
|
|
|
|
.tile R40C13:PLC2
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
|
|
.tile R40C19:PLC2
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
|
|
.tile R40C25:PLC2
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
|
|
.tile R40C27:PLC2
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arc: N3_V06N0303 S3_V06N0203
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.tile R40C31:PLC2
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arc: E3_H06E0103 W3_H06E0103
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.tile R40C32:PLC2
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arc: N3_V06N0103 S3_V06N0003
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.tile R40C33:PLC2
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arc: N3_V06N0103 S3_V06N0103
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.tile R40C34:PLC2
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arc: N3_V06N0003 S3_V06N0003
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arc: N3_V06N0103 H06E0103
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arc: N3_V06N0303 S3_V06N0303
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.tile R40C37:PLC2
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arc: N3_V06N0003 S3_V06N0303
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.tile R40C40:PLC2
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arc: N3_V06N0103 S3_V06N0003
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.tile R40C41:PLC2
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arc: N3_V06N0203 E3_H06W0203
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.tile R40C47:PLC2
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arc: W3_H06W0203 E3_H06W0103
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.tile R40C53:PLC2
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arc: W3_H06W0103 E3_H06W0103
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.tile R40C59:PLC2
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arc: W3_H06W0103 E3_H06W0103
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.tile R40C65:PLC2
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arc: W3_H06W0103 E3_H06W0003
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.tile R40C71:PLC2
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arc: W3_H06W0003 E3_H06W0303
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.tile R40C77:PLC2
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arc: W3_H06W0303 E3_H06W0303
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.tile R40C7:PLC2
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arc: E3_H06E0303 W3_H06E0303
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.tile R40C83:PLC2
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arc: W3_H06W0303 E3_H06W0303
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.tile R41C17:PLC2
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arc: S3_V06S0103 N3_V06S0103
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.tile R43C10:PLC2
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arc: S3_V06S0003 N3_V06S0303
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.tile R45C17:PLC2
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arc: S3_V06S0303 N3_V06S0303
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.tile R45C18:PLC2
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arc: S3_V06S0303 N3_V06S0203
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.tile R47C17:PLC2
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arc: S3_V06S0103 N3_V06S0103
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.tile R49C10:PLC2
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arc: S3_V06S0103 N3_V06S0003
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.tile R4C32:PLC2
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arc: N3_V06N0203 S3_V06N0203
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.tile R4C34:PLC2
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arc: N1_V02N0301 S3_V06N0003
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.tile R4C37:PLC2
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arc: E1_H02E0201 V06S0103
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.tile R4C39:PLC2
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arc: S1_V02S0201 W1_H02E0201
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.tile R4C47:PLC2
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arc: N3_V06N0203 S3_V06N0103
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.tile R4C48:PLC2
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arc: N3_V06N0203 S3_V06N0203
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.tile R4C51:PLC2
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arc: N1_V02N0401 S1_V02N0101
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.tile R4C54:PLC2
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arc: N3_V06N0303 S1_V02N0501
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.tile R51C17:PLC2
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arc: S3_V06S0003 N3_V06S0303
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.tile R51C18:PLC2
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arc: S3_V06S0303 N3_V06S0303
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.tile R52C12:PLC2
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arc: S3_V06S0303 N3_V06S0203
|
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.tile R52C27:PLC2
|
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arc: N3_V06N0203 S3_V06N0103
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.tile R52C32:PLC2
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arc: N3_V06N0303 S3_V06N0303
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.tile R52C33:PLC2
|
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arc: N3_V06N0003 S3_V06N0303
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.tile R52C34:PLC2
|
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arc: N3_V06N0203 S3_V06N0103
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arc: N3_V06N0303 S3_V06N0203
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.tile R52C37:PLC2
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arc: N3_V06N0203 S3_V06N0203
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.tile R52C40:PLC2
|
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arc: N3_V06N0003 S3_V06N0003
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.tile R53C17:PLC2
|
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arc: S3_V06S0203 N3_V06S0103
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.tile R55C10:PLC2
|
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arc: S3_V06S0103 N3_V06S0103
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.tile R57C17:PLC2
|
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arc: S3_V06S0103 N3_V06S0003
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.tile R57C18:PLC2
|
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arc: S3_V06S0303 N3_V06S0303
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.tile R59C17:PLC2
|
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arc: S3_V06S0203 N3_V06S0203
|
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.tile R5C39:PLC2
|
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arc: V00B0000 V02S0201
|
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arc: V00B0100 S1_V02N0301
|
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arc: CE3 S1_V02N0601
|
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arc: CLK0 G_HPBX0000
|
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arc: LSR1 V00B0000
|
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arc: M6 V00B0100
|
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arc: MUXCLK3 CLK0
|
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arc: MUXLSR3 LSR1
|
|
arc: N1_V02N0401 Q6
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
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enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
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enum: LSR1.LSRMUX LSR
|
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enum: CLK0.CLKMUX CLK
|
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.tile R5C42:PLC2
|
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arc: N1_V02N0401 S1_V02N0101
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.tile R61C10:PLC2
|
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arc: S3_V06S0203 N3_V06S0103
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.tile R63C17:PLC2
|
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arc: V01S0000 N3_V06S0103
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.tile R63C18:PLC2
|
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arc: S3_V06S0303 N3_V06S0303
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.tile R64C12:PLC2
|
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arc: S3_V06S0103 N3_V06S0003
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.tile R64C17:PLC2
|
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arc: S3_V06S0003 N1_V01S0000
|
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.tile R64C27:PLC2
|
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arc: N3_V06N0003 S3_V06N0003
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.tile R64C32:PLC2
|
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arc: N3_V06N0203 S3_V06N0103
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.tile R64C33:PLC2
|
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arc: N3_V06N0303 S3_V06N0203
|
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.tile R64C34:PLC2
|
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arc: N3_V06N0003 S3_V06N0003
|
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arc: N3_V06N0103 S3_V06N0103
|
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.tile R64C37:PLC2
|
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arc: N3_V06N0203 S3_V06N0203
|
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.tile R64C40:PLC2
|
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arc: N3_V06N0003 S3_V06N0003
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.tile R65C17:PLC2
|
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arc: S3_V06S0303 N3_V06S0203
|
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.tile R67C10:PLC2
|
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arc: S3_V06S0203 N3_V06S0203
|
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.tile R67C17:PLC2
|
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arc: E1_H02E0001 V06S0003
|
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.tile R67C18:PLC2
|
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arc: D5 H02E0001
|
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arc: F5 F5_SLICE
|
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arc: S1_V02S0701 F5
|
|
word: SLICEC.K1.INIT 0000000011111111
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A1MUX 1
|
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enum: SLICEC.B1MUX 1
|
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enum: SLICEC.C1MUX 1
|
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|
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.tile R68C15:PLC2
|
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arc: S1_V02S0501 E1_H02W0501
|
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.tile R68C17:PLC2
|
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arc: W1_H02W0501 V06S0303
|
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.tile R69C18:PLC2
|
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arc: S1_V02S0201 N1_V02S0701
|
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arc: S1_V02S0501 N3_V06S0303
|
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.tile R6C51:PLC2
|
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arc: N1_V02N0101 S3_V06N0103
|
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.tile R6C54:PLC2
|
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arc: N1_V02N0501 S3_V06N0303
|
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.tile R7C25:PLC2
|
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arc: S3_V06S0003 N3_V06S0003
|
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.tile R7C27:PLC2
|
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arc: S3_V06S0003 N3_V06S0003
|
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.tile R7C28:PLC2
|
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arc: S3_V06S0003 N3_V06S0003
|
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|
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.tile R7C31:PLC2
|
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arc: N3_V06N0203 S3_V06N0103
|
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arc: S3_V06S0103 N3_V06S0003
|
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arc: S3_V06S0203 N3_V06S0103
|
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|
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.tile R7C33:PLC2
|
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arc: S3_V06S0103 N3_V06S0003
|
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|
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.tile R7C34:PLC2
|
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arc: S3_V06S0103 N3_V06S0103
|
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|
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.tile R7C36:PLC2
|
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arc: S3_V06S0003 N3_V06S0003
|
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|
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.tile R7C37:PLC2
|
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arc: S3_V06S0103 N3_V06S0103
|
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arc: S3_V06S0303 N3_V06S0203
|
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|
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.tile R7C38:PLC2
|
|
arc: S3_V06S0003 N3_V06S0003
|
|
arc: S3_V06S0203 N3_V06S0203
|
|
|
|
.tile R7C39:PLC2
|
|
arc: N1_V02N0301 N3_V06S0003
|
|
arc: N1_V02N0601 S1_V02N0301
|
|
|
|
.tile R7C40:PLC2
|
|
arc: S3_V06S0103 N3_V06S0003
|
|
arc: S3_V06S0203 N3_V06S0103
|
|
arc: S3_V06S0303 N3_V06S0203
|
|
|
|
.tile R7C41:PLC2
|
|
arc: S3_V06S0103 N3_V06S0003
|
|
arc: S3_V06S0303 N3_V06S0203
|
|
|
|
.tile R7C42:PLC2
|
|
arc: N1_V02N0101 S3_V06N0103
|
|
arc: S3_V06S0103 N3_V06S0003
|
|
arc: S3_V06S0303 N3_V06S0303
|
|
|
|
.tile R7C43:PLC2
|
|
arc: S3_V06S0203 N3_V06S0103
|
|
|
|
.tile R7C44:PLC2
|
|
arc: N3_V06N0203 S3_V06N0103
|
|
arc: S3_V06S0103 N3_V06S0003
|
|
arc: S3_V06S0203 N3_V06S0103
|
|
arc: S3_V06S0303 N3_V06S0203
|
|
|
|
.tile R7C46:PLC2
|
|
arc: N3_V06N0203 S3_V06N0103
|
|
arc: N3_V06N0303 S1_V02N0601
|
|
|
|
.tile R7C48:PLC2
|
|
arc: N3_V06N0203 S3_V06N0103
|
|
|
|
.tile R7C49:PLC2
|
|
arc: S3_V06S0103 N3_V06S0103
|
|
|
|
.tile R7C52:PLC2
|
|
arc: N3_V06N0203 S3_V06N0103
|
|
arc: S3_V06S0203 N3_V06S0203
|
|
|
|
.tile R7C54:PLC2
|
|
arc: S3_V06S0103 N3_V06S0003
|
|
|
|
.tile R7C55:PLC2
|
|
arc: S3_V06S0303 N3_V06S0203
|
|
|
|
.tile R8C28:PLC2
|
|
arc: N3_V06N0203 S3_V06N0103
|
|
|
|
.tile R8C40:PLC2
|
|
arc: N3_V06N0303 S3_V06N0303
|
|
|
|
.tile R8C44:PLC2
|
|
arc: N3_V06N0203 S3_V06N0203
|
|
|
|
.tile R9C23:PLC2
|
|
arc: N3_V06N0203 S1_V02N0401
|
|
|
|
.tile R9C27:PLC2
|
|
arc: N3_V06N0203 S1_V02N0701
|
|
|
|
.tile R9C36:PLC2
|
|
arc: N3_V06N0103 S3_V06N0003
|
|
|
|
.tile R9C38:PLC2
|
|
arc: N3_V06N0303 S1_V02N0501
|
|
|
|
.tile R9C39:PLC2
|
|
arc: N1_V02N0301 S1_V02N0201
|
|
arc: N3_V06N0203 S1_V02N0401
|
|
|
|
.tile R9C41:PLC2
|
|
arc: N3_V06N0203 S3_V06N0103
|
|
|
|
.tile R9C46:PLC2
|
|
arc: N1_V02N0601 S1_V02N0301
|
|
|
|
.tile R9C62:PLC2
|
|
arc: N3_V06N0303 S1_V02N0601
|
|
|
|
.tile TAP_R14C31:TAP_DRIVE
|
|
arc: R_HPBX0000 G_VPTX0000
|
|
|
|
.tile TAP_R14C51:TAP_DRIVE
|
|
arc: L_HPBX0000 G_VPTX0000
|
|
|
|
.tile TAP_R15C31:TAP_DRIVE
|
|
arc: R_HPBX0000 G_VPTX0000
|
|
|
|
.tile TAP_R16C31:TAP_DRIVE
|
|
arc: R_HPBX0000 G_VPTX0000
|
|
|
|
.tile TAP_R16C51:TAP_DRIVE
|
|
arc: L_HPBX0000 G_VPTX0000
|
|
|
|
.tile TAP_R17C31:TAP_DRIVE
|
|
arc: L_HPBX0000 G_VPTX0000
|
|
arc: R_HPBX0000 G_VPTX0000
|
|
|
|
.tile TAP_R17C51:TAP_DRIVE
|
|
arc: L_HPBX0000 G_VPTX0000
|
|
arc: R_HPBX0000 G_VPTX0000
|
|
|
|
.tile TAP_R18C31:TAP_DRIVE
|
|
arc: R_HPBX0000 G_VPTX0000
|
|
|
|
.tile TAP_R18C51:TAP_DRIVE
|
|
arc: L_HPBX0000 G_VPTX0000
|
|
|
|
.tile TAP_R19C31:TAP_DRIVE
|
|
arc: R_HPBX0000 G_VPTX0000
|
|
|
|
.tile TAP_R19C51:TAP_DRIVE
|
|
arc: L_HPBX0000 G_VPTX0000
|
|
arc: R_HPBX0000 G_VPTX0000
|
|
|
|
.tile TAP_R20C31:TAP_DRIVE
|
|
arc: L_HPBX0000 G_VPTX0000
|
|
arc: R_HPBX0000 G_VPTX0000
|
|
|
|
.tile TAP_R20C51:TAP_DRIVE
|
|
arc: L_HPBX0000 G_VPTX0000
|
|
arc: R_HPBX0000 G_VPTX0000
|
|
|
|
.tile TAP_R21C31:TAP_DRIVE
|
|
arc: L_HPBX0000 G_VPTX0000
|
|
arc: R_HPBX0000 G_VPTX0000
|
|
|
|
.tile TAP_R21C51:TAP_DRIVE
|
|
arc: L_HPBX0000 G_VPTX0000
|
|
|
|
.tile TAP_R23C31:TAP_DRIVE
|
|
arc: R_HPBX0000 G_VPTX0000
|
|
|
|
.tile TAP_R24C31:TAP_DRIVE
|
|
arc: R_HPBX0000 G_VPTX0000
|
|
|
|
.tile TAP_R25C31:TAP_DRIVE
|
|
arc: R_HPBX0000 G_VPTX0000
|
|
|
|
.tile TAP_R26C31:TAP_DRIVE
|
|
arc: R_HPBX0000 G_VPTX0000
|
|
|
|
.tile TAP_R27C31:TAP_DRIVE
|
|
arc: R_HPBX0000 G_VPTX0000
|
|
|
|
.tile TAP_R28C31:TAP_DRIVE
|
|
arc: R_HPBX0000 G_VPTX0000
|
|
|
|
.tile TAP_R29C31:TAP_DRIVE
|
|
arc: R_HPBX0000 G_VPTX0000
|
|
|
|
.tile TAP_R5C31:TAP_DRIVE
|
|
arc: R_HPBX0000 G_VPTX0000
|
|
|