micheleandClaude Sonnet 5
2e4cedc761
Implements M5: neural_director.v dispatches job descriptors to whichever of N_SLOTS (memory_manager, neural_processor) pairs is currently free (first-free scheduling per §9's initial policy), with a parametric-depth ready-queue FIFO for jobs arriving faster than slots can absorb them. Scope for this milestone (see decisions.log DEC-0007): a reduced 4-state FSM (DIR_IDLE/SCAN_READY/ALLOCATE/ERROR) rather than §9's full 8-state baseline -- dependency tracking, the waiting queue, and wake-up are §10's explicit responsibility (Dependency Manager, M6, not yet built), and slot-completion detection runs as an always-active per-slot tracker rather than a dedicated FSM state, for the same reason DEC-0002 already gave for the Neural Processor's own FSM (gating concurrent per-unit progress behind one shared state kills throughput). Verified with Verilator (N_SLOTS=2, each slot backed by its own independent behavioral memory rather than sharing V1's real PSRAM -- M4 already proved that path for one slot; this milestone's own concern is scheduling across multiple slots): 4/4 tests pass -- 3 jobs submitted to 2 slots (first two dispatch immediately, third correctly queues until a slot frees), and a deliberate burst that forces the ready queue to genuinely fill and recover. Real synthesis: 0 CHECK problems, 382 LUT4/366 FF/4 CCU2C/0 DSP. Real place&route (via a synthesis-only timing harness, same TRELLIS_IO pin-budget reason as M2/M4): Fmax 250.50 MHz, PASS at 80MHz. Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
1979 lines
122 KiB
Plaintext
1979 lines
122 KiB
Plaintext
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/----------------------------------------------------------------------------\
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| yosys -- Yosys Open SYnthesis Suite |
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| Copyright (C) 2012 - 2026 Claire Xenia Wolf <claire@yosyshq.com> |
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| Distributed under an ISC-like license, type "license" to see terms |
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\----------------------------------------------------------------------------/
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Yosys 0.68+post (git sha1 c12172fbae8af5e20f6fb52e3d4e92d56ed587b6, Release, AppleClang clang++ 21.0.0.21000101)
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-- Parsing `hardware/v2/rtl/neural_director.v' using frontend ` -vlog2k' --
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1. Executing Verilog-2005 frontend: hardware/v2/rtl/neural_director.v
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Parsing Verilog input from `hardware/v2/rtl/neural_director.v' to AST representation.
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Storing AST representation for module `$abstract\neural_director'.
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Successfully finished Verilog frontend.
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-- Running command `synth_ecp5 -json hardware/v2/synthesis/neural_director_n4/top.json -top neural_director' --
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2. Executing SYNTH_LATTICE pass.
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2.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v
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Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v' to AST representation.
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Generating RTLIL representation for module `\LUT4'.
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Generating RTLIL representation for module `\$__ABC9_LUT5'.
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Generating RTLIL representation for module `\$__ABC9_LUT6'.
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Generating RTLIL representation for module `\$__ABC9_LUT7'.
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Generating RTLIL representation for module `\L6MUX21'.
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Generating RTLIL representation for module `\TRELLIS_RAM16X2'.
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Generating RTLIL representation for module `\PFUMX'.
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Generating RTLIL representation for module `\TRELLIS_DPR16X4'.
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Generating RTLIL representation for module `\DPR16X4C'.
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Generating RTLIL representation for module `\LUT2'.
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Generating RTLIL representation for module `\TRELLIS_FF'.
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Generating RTLIL representation for module `\TRELLIS_IO'.
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Generating RTLIL representation for module `\INV'.
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Generating RTLIL representation for module `\TRELLIS_COMB'.
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Generating RTLIL representation for module `\VLO'.
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Generating RTLIL representation for module `\VHI'.
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Generating RTLIL representation for module `\FD1P3AX'.
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Generating RTLIL representation for module `\FD1P3AY'.
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Generating RTLIL representation for module `\FD1P3BX'.
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Generating RTLIL representation for module `\FD1P3DX'.
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Generating RTLIL representation for module `\FD1P3IX'.
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Generating RTLIL representation for module `\FD1P3JX'.
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Generating RTLIL representation for module `\FD1S3AX'.
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Generating RTLIL representation for module `\FD1S3AY'.
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Generating RTLIL representation for module `\FD1S3BX'.
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Generating RTLIL representation for module `\FD1S3DX'.
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Generating RTLIL representation for module `\FD1S3IX'.
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Generating RTLIL representation for module `\FD1S3JX'.
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Generating RTLIL representation for module `\IFS1P3BX'.
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Generating RTLIL representation for module `\IFS1P3DX'.
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Generating RTLIL representation for module `\IFS1P3IX'.
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Generating RTLIL representation for module `\IFS1P3JX'.
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Generating RTLIL representation for module `\OFS1P3BX'.
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Generating RTLIL representation for module `\OFS1P3DX'.
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Generating RTLIL representation for module `\OFS1P3IX'.
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Generating RTLIL representation for module `\OFS1P3JX'.
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Generating RTLIL representation for module `\IB'.
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Generating RTLIL representation for module `\IBPU'.
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Generating RTLIL representation for module `\IBPD'.
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Generating RTLIL representation for module `\OB'.
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Generating RTLIL representation for module `\OBZ'.
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Generating RTLIL representation for module `\OBZPU'.
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Generating RTLIL representation for module `\OBZPD'.
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Generating RTLIL representation for module `\OBCO'.
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Generating RTLIL representation for module `\BB'.
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Generating RTLIL representation for module `\BBPU'.
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Generating RTLIL representation for module `\BBPD'.
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Generating RTLIL representation for module `\ILVDS'.
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Generating RTLIL representation for module `\OLVDS'.
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Generating RTLIL representation for module `\CCU2C'.
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Generating RTLIL representation for module `\DP16KD'.
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Replacing existing blackbox module `\FD1P3AX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:2.1-2.261.
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Generating RTLIL representation for module `\FD1P3AX'.
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Replacing existing blackbox module `\FD1P3AY' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:3.1-3.261.
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Generating RTLIL representation for module `\FD1P3AY'.
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Replacing existing blackbox module `\FD1P3BX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:4.1-4.261.
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Generating RTLIL representation for module `\FD1P3BX'.
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Replacing existing blackbox module `\FD1P3DX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:5.1-5.261.
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Generating RTLIL representation for module `\FD1P3DX'.
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Replacing existing blackbox module `\FD1P3IX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:6.1-6.261.
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Generating RTLIL representation for module `\FD1P3IX'.
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Replacing existing blackbox module `\FD1P3JX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:7.1-7.261.
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Generating RTLIL representation for module `\FD1P3JX'.
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Replacing existing blackbox module `\FD1S3AX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:8.1-8.261.
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Generating RTLIL representation for module `\FD1S3AX'.
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Replacing existing blackbox module `\FD1S3AY' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:9.1-9.261.
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Generating RTLIL representation for module `\FD1S3AY'.
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Replacing existing blackbox module `\FD1S3BX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:10.1-10.261.
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Generating RTLIL representation for module `\FD1S3BX'.
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Replacing existing blackbox module `\FD1S3DX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:11.1-11.261.
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Generating RTLIL representation for module `\FD1S3DX'.
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Replacing existing blackbox module `\FD1S3IX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:12.1-12.261.
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Generating RTLIL representation for module `\FD1S3IX'.
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Replacing existing blackbox module `\FD1S3JX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:13.1-13.261.
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Generating RTLIL representation for module `\FD1S3JX'.
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Replacing existing blackbox module `\IFS1P3BX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:26.1-26.301.
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Generating RTLIL representation for module `\IFS1P3BX'.
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Replacing existing blackbox module `\IFS1P3DX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:27.1-27.301.
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Generating RTLIL representation for module `\IFS1P3DX'.
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Replacing existing blackbox module `\IFS1P3IX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:28.1-28.301.
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Generating RTLIL representation for module `\IFS1P3IX'.
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Replacing existing blackbox module `\IFS1P3JX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:29.1-29.301.
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Generating RTLIL representation for module `\IFS1P3JX'.
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Replacing existing blackbox module `\OFS1P3BX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:31.1-31.302.
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Generating RTLIL representation for module `\OFS1P3BX'.
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Replacing existing blackbox module `\OFS1P3DX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:32.1-32.302.
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Generating RTLIL representation for module `\OFS1P3DX'.
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Replacing existing blackbox module `\OFS1P3IX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:33.1-33.302.
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Generating RTLIL representation for module `\OFS1P3IX'.
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Replacing existing blackbox module `\OFS1P3JX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:34.1-34.302.
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Generating RTLIL representation for module `\OFS1P3JX'.
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Replacing existing blackbox module `\IB' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:2.1-2.157.
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Generating RTLIL representation for module `\IB'.
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Replacing existing blackbox module `\IBPU' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:3.1-3.157.
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Generating RTLIL representation for module `\IBPU'.
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Replacing existing blackbox module `\IBPD' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:4.1-4.157.
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Generating RTLIL representation for module `\IBPD'.
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Replacing existing blackbox module `\OB' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:5.1-5.157.
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Generating RTLIL representation for module `\OB'.
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Replacing existing blackbox module `\OBZ' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:6.1-6.164.
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Generating RTLIL representation for module `\OBZ'.
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Replacing existing blackbox module `\OBZPU' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:7.1-7.164.
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Generating RTLIL representation for module `\OBZPU'.
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Replacing existing blackbox module `\OBZPD' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:8.1-8.164.
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Generating RTLIL representation for module `\OBZPD'.
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Replacing existing blackbox module `\OBCO' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:9.1-9.90.
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Generating RTLIL representation for module `\OBCO'.
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Replacing existing blackbox module `\BB' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:10.1-10.179.
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Generating RTLIL representation for module `\BB'.
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Replacing existing blackbox module `\BBPU' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:11.1-11.179.
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Generating RTLIL representation for module `\BBPU'.
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Replacing existing blackbox module `\BBPD' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:12.1-12.179.
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Generating RTLIL representation for module `\BBPD'.
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Replacing existing blackbox module `\ILVDS' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:13.1-13.139.
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Generating RTLIL representation for module `\ILVDS'.
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Replacing existing blackbox module `\OLVDS' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:14.1-14.146.
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Generating RTLIL representation for module `\OLVDS'.
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Successfully finished Verilog frontend.
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2.2. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v
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Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v' to AST representation.
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Generating RTLIL representation for module `\GSR'.
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Generating RTLIL representation for module `\PUR'.
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Generating RTLIL representation for module `\SGSR'.
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Generating RTLIL representation for module `\PDPW16KD'.
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Generating RTLIL representation for module `\MULT18X18D'.
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Generating RTLIL representation for module `\ALU54B'.
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Generating RTLIL representation for module `\CLKDIVF'.
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Generating RTLIL representation for module `\PCSCLKDIV'.
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Generating RTLIL representation for module `\DCSC'.
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Generating RTLIL representation for module `\DCCA'.
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Generating RTLIL representation for module `\ECLKSYNCB'.
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Generating RTLIL representation for module `\ECLKBRIDGECS'.
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Generating RTLIL representation for module `\DELAYF'.
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Generating RTLIL representation for module `\DELAYG'.
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Generating RTLIL representation for module `\USRMCLK'.
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Generating RTLIL representation for module `\DQSBUFM'.
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Generating RTLIL representation for module `\DDRDLLA'.
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Generating RTLIL representation for module `\DLLDELD'.
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Generating RTLIL representation for module `\IDDRX1F'.
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Generating RTLIL representation for module `\IDDRX2F'.
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Generating RTLIL representation for module `\IDDR71B'.
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Generating RTLIL representation for module `\IDDRX2DQA'.
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Generating RTLIL representation for module `\ODDRX1F'.
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Generating RTLIL representation for module `\ODDRX2F'.
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Generating RTLIL representation for module `\ODDR71B'.
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Generating RTLIL representation for module `\OSHX2A'.
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Generating RTLIL representation for module `\TSHX2DQA'.
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Generating RTLIL representation for module `\TSHX2DQSA'.
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Generating RTLIL representation for module `\ODDRX2DQA'.
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Generating RTLIL representation for module `\ODDRX2DQSB'.
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Generating RTLIL representation for module `\EHXPLLL'.
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Generating RTLIL representation for module `\DTR'.
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Generating RTLIL representation for module `\OSCG'.
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Generating RTLIL representation for module `\EXTREFB'.
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Generating RTLIL representation for module `\JTAGG'.
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Generating RTLIL representation for module `\DCUA'.
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Successfully finished Verilog frontend.
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2.3. Executing HIERARCHY pass (managing design hierarchy).
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2.4. Executing AST frontend in derive mode using pre-parsed AST for module `\neural_director'.
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Generating RTLIL representation for module `\neural_director'.
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2.4.1. Analyzing design hierarchy..
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Top module: \neural_director
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2.4.2. Analyzing design hierarchy..
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Top module: \neural_director
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Removing unused module `$abstract\neural_director'.
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Removed 1 unused modules.
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2.5. Executing PROC pass (convert processes to netlists).
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2.5.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
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Cleaned up 0 empty switches.
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2.5.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
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Marked 4 switch rules as full_case in process $proc$hardware/v2/rtl/neural_director.v:123$252 in module neural_director.
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Marked 4 switch rules as full_case in process $proc$hardware/v2/rtl/neural_director.v:116$245 in module neural_director.
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Marked 4 switch rules as full_case in process $proc$hardware/v2/rtl/neural_director.v:102$244 in module neural_director.
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Removed a total of 0 dead cases.
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2.5.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
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Removed 2 redundant assignments.
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Promoted 37 assignments to connections.
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2.5.4. Executing PROC_INIT pass (extract init attributes).
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2.5.5. Executing PROC_ARST pass (detect async resets in processes).
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2.5.6. Executing PROC_ROM pass (convert switches to ROMs).
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Converted 0 switches.
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<suppressed ~14 debug messages>
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2.5.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
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Creating decoders for process `\neural_director.$proc$hardware/v2/rtl/neural_director.v:123$252'.
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1/61: $2$lookahead\slot_busy$251[3:0]$340
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2/61: $2$lookahead\slot_result_addr$250[91:0]$339
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3/61: $2$lookahead\slot_n_tiles$249[63:0]$338
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4/61: $2$lookahead\slot_w_base$248[91:0]$337
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5/61: $2$lookahead\slot_x_base$247[91:0]$336
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6/61: $2$lookahead\slot_job_start$246[3:0]$335
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7/61: $2$bitselwrite$pos$hardware/v2/rtl/neural_director.v:195$233[1:0]$334
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8/61: $2$bitselwrite$pos$hardware/v2/rtl/neural_director.v:194$232[31:0]$333
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9/61: $2$bitselwrite$pos$hardware/v2/rtl/neural_director.v:193$231[31:0]$332
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10/61: $2$bitselwrite$pos$hardware/v2/rtl/neural_director.v:192$230[31:0]$331
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11/61: $2$bitselwrite$pos$hardware/v2/rtl/neural_director.v:191$229[31:0]$330
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12/61: $2$bitselwrite$pos$hardware/v2/rtl/neural_director.v:190$228[1:0]$329
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13/61: $2$memwr$\q_node_id$hardware/v2/rtl/neural_director.v:151$238_EN[15:0]$322
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14/61: $2$memwr$\q_node_id$hardware/v2/rtl/neural_director.v:151$238_DATA[15:0]$321
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15/61: $2$memwr$\q_node_id$hardware/v2/rtl/neural_director.v:151$238_ADDR[2:0]$320
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16/61: $2$memwr$\q_result_addr$hardware/v2/rtl/neural_director.v:150$237_EN[22:0]$319
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17/61: $2$memwr$\q_result_addr$hardware/v2/rtl/neural_director.v:150$237_DATA[22:0]$318
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18/61: $2$memwr$\q_result_addr$hardware/v2/rtl/neural_director.v:150$237_ADDR[2:0]$317
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19/61: $2$memwr$\q_n_tiles$hardware/v2/rtl/neural_director.v:149$236_EN[15:0]$316
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20/61: $2$memwr$\q_n_tiles$hardware/v2/rtl/neural_director.v:149$236_DATA[15:0]$315
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21/61: $2$memwr$\q_n_tiles$hardware/v2/rtl/neural_director.v:149$236_ADDR[2:0]$314
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22/61: $2$memwr$\q_w_base$hardware/v2/rtl/neural_director.v:148$235_EN[22:0]$313
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23/61: $2$memwr$\q_w_base$hardware/v2/rtl/neural_director.v:148$235_DATA[22:0]$312
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24/61: $2$memwr$\q_w_base$hardware/v2/rtl/neural_director.v:148$235_ADDR[2:0]$311
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25/61: $2$memwr$\q_x_base$hardware/v2/rtl/neural_director.v:147$234_EN[22:0]$310
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26/61: $2$memwr$\q_x_base$hardware/v2/rtl/neural_director.v:147$234_DATA[22:0]$309
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27/61: $2$memwr$\q_x_base$hardware/v2/rtl/neural_director.v:147$234_ADDR[2:0]$308
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28/61: $0\job_out_done[0:0]
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29/61: $1$lookahead\slot_result_addr$250[91:0]$305
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30/61: $1$lookahead\slot_n_tiles$249[63:0]$304
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31/61: $1$lookahead\slot_w_base$248[91:0]$303
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32/61: $1$lookahead\slot_x_base$247[91:0]$302
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33/61: $1$lookahead\slot_job_start$246[3:0]$301
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34/61: $1$lookahead\slot_busy$251[3:0]$306
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35/61: $0\q_count[3:0]
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36/61: $1$memwr$\q_node_id$hardware/v2/rtl/neural_director.v:151$238_EN[15:0]$300
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37/61: $1$memwr$\q_node_id$hardware/v2/rtl/neural_director.v:151$238_DATA[15:0]$299
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38/61: $1$memwr$\q_node_id$hardware/v2/rtl/neural_director.v:151$238_ADDR[2:0]$298
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39/61: $1$memwr$\q_result_addr$hardware/v2/rtl/neural_director.v:150$237_EN[22:0]$297
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40/61: $1$memwr$\q_result_addr$hardware/v2/rtl/neural_director.v:150$237_DATA[22:0]$296
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41/61: $1$memwr$\q_result_addr$hardware/v2/rtl/neural_director.v:150$237_ADDR[2:0]$295
|
|
42/61: $1$memwr$\q_n_tiles$hardware/v2/rtl/neural_director.v:149$236_EN[15:0]$294
|
|
43/61: $1$memwr$\q_n_tiles$hardware/v2/rtl/neural_director.v:149$236_DATA[15:0]$293
|
|
44/61: $1$memwr$\q_n_tiles$hardware/v2/rtl/neural_director.v:149$236_ADDR[2:0]$292
|
|
45/61: $1$memwr$\q_w_base$hardware/v2/rtl/neural_director.v:148$235_EN[22:0]$291
|
|
46/61: $1$memwr$\q_w_base$hardware/v2/rtl/neural_director.v:148$235_DATA[22:0]$290
|
|
47/61: $1$memwr$\q_w_base$hardware/v2/rtl/neural_director.v:148$235_ADDR[2:0]$289
|
|
48/61: $1$memwr$\q_x_base$hardware/v2/rtl/neural_director.v:147$234_EN[22:0]$288
|
|
49/61: $1$memwr$\q_x_base$hardware/v2/rtl/neural_director.v:147$234_DATA[22:0]$287
|
|
50/61: $1$memwr$\q_x_base$hardware/v2/rtl/neural_director.v:147$234_ADDR[2:0]$286
|
|
51/61: $1$bitselwrite$pos$hardware/v2/rtl/neural_director.v:195$233[1:0]$285
|
|
52/61: $1$bitselwrite$pos$hardware/v2/rtl/neural_director.v:194$232[31:0]$284
|
|
53/61: $1$bitselwrite$pos$hardware/v2/rtl/neural_director.v:193$231[31:0]$283
|
|
54/61: $1$bitselwrite$pos$hardware/v2/rtl/neural_director.v:192$230[31:0]$282
|
|
55/61: $1$bitselwrite$pos$hardware/v2/rtl/neural_director.v:191$229[31:0]$281
|
|
56/61: $1$bitselwrite$pos$hardware/v2/rtl/neural_director.v:190$228[1:0]$280
|
|
57/61: $0\q_tail[2:0]
|
|
58/61: $0\q_head[2:0]
|
|
59/61: $0\dir_error[0:0]
|
|
60/61: $0\dir_state[3:0]
|
|
61/61: $0\job_out_slot[1:0]
|
|
Creating decoders for process `\neural_director.$proc$hardware/v2/rtl/neural_director.v:116$245'.
|
|
1/4: $4\done_slot_idx[1:0]
|
|
2/4: $3\done_slot_idx[1:0]
|
|
3/4: $2\done_slot_idx[1:0]
|
|
4/4: $1\done_slot_idx[1:0]
|
|
Creating decoders for process `\neural_director.$proc$hardware/v2/rtl/neural_director.v:102$244'.
|
|
1/4: $4\free_slot_idx[1:0]
|
|
2/4: $3\free_slot_idx[1:0]
|
|
3/4: $2\free_slot_idx[1:0]
|
|
4/4: $1\free_slot_idx[1:0]
|
|
|
|
2.5.8. Executing PROC_DLATCH pass (convert process syncs to latches).
|
|
No latch inferred for signal `\neural_director.\done_slot_idx' from process `\neural_director.$proc$hardware/v2/rtl/neural_director.v:116$245'.
|
|
No latch inferred for signal `\neural_director.\di' from process `\neural_director.$proc$hardware/v2/rtl/neural_director.v:116$245'.
|
|
No latch inferred for signal `\neural_director.\free_slot_idx' from process `\neural_director.$proc$hardware/v2/rtl/neural_director.v:102$244'.
|
|
No latch inferred for signal `\neural_director.\fi' from process `\neural_director.$proc$hardware/v2/rtl/neural_director.v:102$244'.
|
|
|
|
2.5.9. Executing PROC_DFF pass (convert process syncs to FFs).
|
|
Creating register for signal `\neural_director.\slot_job_start' using process `\neural_director.$proc$hardware/v2/rtl/neural_director.v:123$252'.
|
|
created $dff cell `$procdff$730' with positive edge clock.
|
|
Creating register for signal `\neural_director.\slot_x_base' using process `\neural_director.$proc$hardware/v2/rtl/neural_director.v:123$252'.
|
|
created $dff cell `$procdff$731' with positive edge clock.
|
|
Creating register for signal `\neural_director.\slot_w_base' using process `\neural_director.$proc$hardware/v2/rtl/neural_director.v:123$252'.
|
|
created $dff cell `$procdff$732' with positive edge clock.
|
|
Creating register for signal `\neural_director.\slot_n_tiles' using process `\neural_director.$proc$hardware/v2/rtl/neural_director.v:123$252'.
|
|
created $dff cell `$procdff$733' with positive edge clock.
|
|
Creating register for signal `\neural_director.\slot_result_addr' using process `\neural_director.$proc$hardware/v2/rtl/neural_director.v:123$252'.
|
|
created $dff cell `$procdff$734' with positive edge clock.
|
|
Creating register for signal `\neural_director.\job_out_done' using process `\neural_director.$proc$hardware/v2/rtl/neural_director.v:123$252'.
|
|
created $dff cell `$procdff$735' with positive edge clock.
|
|
Creating register for signal `\neural_director.\job_out_slot' using process `\neural_director.$proc$hardware/v2/rtl/neural_director.v:123$252'.
|
|
created $dff cell `$procdff$736' with positive edge clock.
|
|
Creating register for signal `\neural_director.\dir_state' using process `\neural_director.$proc$hardware/v2/rtl/neural_director.v:123$252'.
|
|
created $dff cell `$procdff$737' with positive edge clock.
|
|
Creating register for signal `\neural_director.\dir_error' using process `\neural_director.$proc$hardware/v2/rtl/neural_director.v:123$252'.
|
|
created $dff cell `$procdff$738' with positive edge clock.
|
|
Creating register for signal `\neural_director.\q_head' using process `\neural_director.$proc$hardware/v2/rtl/neural_director.v:123$252'.
|
|
created $dff cell `$procdff$739' with positive edge clock.
|
|
Creating register for signal `\neural_director.\q_tail' using process `\neural_director.$proc$hardware/v2/rtl/neural_director.v:123$252'.
|
|
created $dff cell `$procdff$740' with positive edge clock.
|
|
Creating register for signal `\neural_director.\q_count' using process `\neural_director.$proc$hardware/v2/rtl/neural_director.v:123$252'.
|
|
created $dff cell `$procdff$741' with positive edge clock.
|
|
Creating register for signal `\neural_director.\slot_busy' using process `\neural_director.$proc$hardware/v2/rtl/neural_director.v:123$252'.
|
|
created $dff cell `$procdff$742' with positive edge clock.
|
|
Creating register for signal `\neural_director.$bitselwrite$pos$hardware/v2/rtl/neural_director.v:190$228' using process `\neural_director.$proc$hardware/v2/rtl/neural_director.v:123$252'.
|
|
created $dff cell `$procdff$743' with positive edge clock.
|
|
Creating register for signal `\neural_director.$bitselwrite$pos$hardware/v2/rtl/neural_director.v:191$229' using process `\neural_director.$proc$hardware/v2/rtl/neural_director.v:123$252'.
|
|
created $dff cell `$procdff$744' with positive edge clock.
|
|
Creating register for signal `\neural_director.$bitselwrite$pos$hardware/v2/rtl/neural_director.v:192$230' using process `\neural_director.$proc$hardware/v2/rtl/neural_director.v:123$252'.
|
|
created $dff cell `$procdff$745' with positive edge clock.
|
|
Creating register for signal `\neural_director.$bitselwrite$pos$hardware/v2/rtl/neural_director.v:193$231' using process `\neural_director.$proc$hardware/v2/rtl/neural_director.v:123$252'.
|
|
created $dff cell `$procdff$746' with positive edge clock.
|
|
Creating register for signal `\neural_director.$bitselwrite$pos$hardware/v2/rtl/neural_director.v:194$232' using process `\neural_director.$proc$hardware/v2/rtl/neural_director.v:123$252'.
|
|
created $dff cell `$procdff$747' with positive edge clock.
|
|
Creating register for signal `\neural_director.$bitselwrite$pos$hardware/v2/rtl/neural_director.v:195$233' using process `\neural_director.$proc$hardware/v2/rtl/neural_director.v:123$252'.
|
|
created $dff cell `$procdff$748' with positive edge clock.
|
|
Creating register for signal `\neural_director.$memwr$\q_x_base$hardware/v2/rtl/neural_director.v:147$234_ADDR' using process `\neural_director.$proc$hardware/v2/rtl/neural_director.v:123$252'.
|
|
created $dff cell `$procdff$749' with positive edge clock.
|
|
Creating register for signal `\neural_director.$memwr$\q_x_base$hardware/v2/rtl/neural_director.v:147$234_DATA' using process `\neural_director.$proc$hardware/v2/rtl/neural_director.v:123$252'.
|
|
created $dff cell `$procdff$750' with positive edge clock.
|
|
Creating register for signal `\neural_director.$memwr$\q_x_base$hardware/v2/rtl/neural_director.v:147$234_EN' using process `\neural_director.$proc$hardware/v2/rtl/neural_director.v:123$252'.
|
|
created $dff cell `$procdff$751' with positive edge clock.
|
|
Creating register for signal `\neural_director.$memwr$\q_w_base$hardware/v2/rtl/neural_director.v:148$235_ADDR' using process `\neural_director.$proc$hardware/v2/rtl/neural_director.v:123$252'.
|
|
created $dff cell `$procdff$752' with positive edge clock.
|
|
Creating register for signal `\neural_director.$memwr$\q_w_base$hardware/v2/rtl/neural_director.v:148$235_DATA' using process `\neural_director.$proc$hardware/v2/rtl/neural_director.v:123$252'.
|
|
created $dff cell `$procdff$753' with positive edge clock.
|
|
Creating register for signal `\neural_director.$memwr$\q_w_base$hardware/v2/rtl/neural_director.v:148$235_EN' using process `\neural_director.$proc$hardware/v2/rtl/neural_director.v:123$252'.
|
|
created $dff cell `$procdff$754' with positive edge clock.
|
|
Creating register for signal `\neural_director.$memwr$\q_n_tiles$hardware/v2/rtl/neural_director.v:149$236_ADDR' using process `\neural_director.$proc$hardware/v2/rtl/neural_director.v:123$252'.
|
|
created $dff cell `$procdff$755' with positive edge clock.
|
|
Creating register for signal `\neural_director.$memwr$\q_n_tiles$hardware/v2/rtl/neural_director.v:149$236_DATA' using process `\neural_director.$proc$hardware/v2/rtl/neural_director.v:123$252'.
|
|
created $dff cell `$procdff$756' with positive edge clock.
|
|
Creating register for signal `\neural_director.$memwr$\q_n_tiles$hardware/v2/rtl/neural_director.v:149$236_EN' using process `\neural_director.$proc$hardware/v2/rtl/neural_director.v:123$252'.
|
|
created $dff cell `$procdff$757' with positive edge clock.
|
|
Creating register for signal `\neural_director.$memwr$\q_result_addr$hardware/v2/rtl/neural_director.v:150$237_ADDR' using process `\neural_director.$proc$hardware/v2/rtl/neural_director.v:123$252'.
|
|
created $dff cell `$procdff$758' with positive edge clock.
|
|
Creating register for signal `\neural_director.$memwr$\q_result_addr$hardware/v2/rtl/neural_director.v:150$237_DATA' using process `\neural_director.$proc$hardware/v2/rtl/neural_director.v:123$252'.
|
|
created $dff cell `$procdff$759' with positive edge clock.
|
|
Creating register for signal `\neural_director.$memwr$\q_result_addr$hardware/v2/rtl/neural_director.v:150$237_EN' using process `\neural_director.$proc$hardware/v2/rtl/neural_director.v:123$252'.
|
|
created $dff cell `$procdff$760' with positive edge clock.
|
|
Creating register for signal `\neural_director.$memwr$\q_node_id$hardware/v2/rtl/neural_director.v:151$238_ADDR' using process `\neural_director.$proc$hardware/v2/rtl/neural_director.v:123$252'.
|
|
created $dff cell `$procdff$761' with positive edge clock.
|
|
Creating register for signal `\neural_director.$memwr$\q_node_id$hardware/v2/rtl/neural_director.v:151$238_DATA' using process `\neural_director.$proc$hardware/v2/rtl/neural_director.v:123$252'.
|
|
created $dff cell `$procdff$762' with positive edge clock.
|
|
Creating register for signal `\neural_director.$memwr$\q_node_id$hardware/v2/rtl/neural_director.v:151$238_EN' using process `\neural_director.$proc$hardware/v2/rtl/neural_director.v:123$252'.
|
|
created $dff cell `$procdff$763' with positive edge clock.
|
|
Creating register for signal `\neural_director.$lookahead\slot_job_start$246' using process `\neural_director.$proc$hardware/v2/rtl/neural_director.v:123$252'.
|
|
created $dff cell `$procdff$764' with positive edge clock.
|
|
Creating register for signal `\neural_director.$lookahead\slot_x_base$247' using process `\neural_director.$proc$hardware/v2/rtl/neural_director.v:123$252'.
|
|
created $dff cell `$procdff$765' with positive edge clock.
|
|
Creating register for signal `\neural_director.$lookahead\slot_w_base$248' using process `\neural_director.$proc$hardware/v2/rtl/neural_director.v:123$252'.
|
|
created $dff cell `$procdff$766' with positive edge clock.
|
|
Creating register for signal `\neural_director.$lookahead\slot_n_tiles$249' using process `\neural_director.$proc$hardware/v2/rtl/neural_director.v:123$252'.
|
|
created $dff cell `$procdff$767' with positive edge clock.
|
|
Creating register for signal `\neural_director.$lookahead\slot_result_addr$250' using process `\neural_director.$proc$hardware/v2/rtl/neural_director.v:123$252'.
|
|
created $dff cell `$procdff$768' with positive edge clock.
|
|
Creating register for signal `\neural_director.$lookahead\slot_busy$251' using process `\neural_director.$proc$hardware/v2/rtl/neural_director.v:123$252'.
|
|
created $dff cell `$procdff$769' with positive edge clock.
|
|
|
|
2.5.10. Executing PROC_MEMWR pass (convert process memory writes to cells).
|
|
|
|
2.5.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
|
|
Found and cleaned up 6 empty switches in `\neural_director.$proc$hardware/v2/rtl/neural_director.v:123$252'.
|
|
Removing empty process `neural_director.$proc$hardware/v2/rtl/neural_director.v:123$252'.
|
|
Found and cleaned up 4 empty switches in `\neural_director.$proc$hardware/v2/rtl/neural_director.v:116$245'.
|
|
Removing empty process `neural_director.$proc$hardware/v2/rtl/neural_director.v:116$245'.
|
|
Found and cleaned up 4 empty switches in `\neural_director.$proc$hardware/v2/rtl/neural_director.v:102$244'.
|
|
Removing empty process `neural_director.$proc$hardware/v2/rtl/neural_director.v:102$244'.
|
|
Cleaned up 14 empty switches.
|
|
|
|
2.5.12. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module neural_director.
|
|
<suppressed ~4 debug messages>
|
|
|
|
2.6. Executing CHECK pass (checking for obvious problems).
|
|
Checking module neural_director...
|
|
Found and reported 0 problems.
|
|
|
|
2.7. Executing FLATTEN pass (flatten design).
|
|
|
|
2.8. Executing TRIBUF pass.
|
|
|
|
2.9. Executing DEMINOUT pass (demote inout ports to input or output).
|
|
|
|
2.10. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module neural_director.
|
|
<suppressed ~6 debug messages>
|
|
|
|
2.11. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \neural_director..
|
|
Removed 64 unused cells and 271 unused wires.
|
|
<suppressed ~70 debug messages>
|
|
|
|
2.12. Executing CHECK pass (checking for obvious problems).
|
|
Checking module neural_director...
|
|
Found and reported 0 problems.
|
|
|
|
2.13. Executing OPT pass (performing simple optimizations).
|
|
|
|
2.13.1. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module neural_director.
|
|
|
|
2.13.2. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\neural_director'.
|
|
Computing hashes of 174 cells of `\neural_director'.
|
|
Finding duplicate cells in `\neural_director'.
|
|
Computing hashes of 156 cells of `\neural_director'.
|
|
Finding duplicate cells in `\neural_director'.
|
|
Computing hashes of 152 cells of `\neural_director'.
|
|
Finding duplicate cells in `\neural_director'.
|
|
Computing hashes of 150 cells of `\neural_director'.
|
|
Finding duplicate cells in `\neural_director'.
|
|
Computing hashes of 148 cells of `\neural_director'.
|
|
Finding duplicate cells in `\neural_director'.
|
|
<suppressed ~78 debug messages>
|
|
Removed a total of 26 cells.
|
|
|
|
2.13.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \neural_director..
|
|
Creating internal representation of mux trees.
|
|
Evaluating internal representation of mux trees.
|
|
Analyzing evaluation results.
|
|
dead port 1/2 on $mux $procmux$579.
|
|
dead port 1/2 on $mux $procmux$573.
|
|
dead port 1/2 on $mux $procmux$567.
|
|
dead port 1/2 on $mux $procmux$561.
|
|
dead port 1/2 on $mux $procmux$555.
|
|
dead port 1/2 on $mux $procmux$549.
|
|
dead port 1/2 on $mux $procmux$543.
|
|
dead port 1/2 on $mux $procmux$537.
|
|
dead port 1/2 on $mux $procmux$531.
|
|
dead port 1/2 on $mux $procmux$525.
|
|
dead port 1/2 on $mux $procmux$519.
|
|
dead port 1/2 on $mux $procmux$513.
|
|
dead port 1/2 on $mux $procmux$447.
|
|
dead port 1/2 on $mux $procmux$440.
|
|
dead port 1/2 on $mux $procmux$433.
|
|
dead port 1/2 on $mux $procmux$426.
|
|
dead port 1/2 on $mux $procmux$419.
|
|
dead port 1/2 on $mux $procmux$412.
|
|
Removed 18 multiplexer ports.
|
|
<suppressed ~104 debug messages>
|
|
|
|
2.13.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \neural_director.
|
|
Consolidated identical input bits for $mux cell $procmux$528:
|
|
Old ports: A=16'0000000000000000, B=16'1111111111111111, Y=$procmux$528_Y
|
|
New ports: A=1'0, B=1'1, Y=$procmux$528_Y [0]
|
|
New connections: $procmux$528_Y [15:1] = { $procmux$528_Y [0] $procmux$528_Y [0] $procmux$528_Y [0] $procmux$528_Y [0] $procmux$528_Y [0] $procmux$528_Y [0] $procmux$528_Y [0] $procmux$528_Y [0] $procmux$528_Y [0] $procmux$528_Y [0] $procmux$528_Y [0] $procmux$528_Y [0] $procmux$528_Y [0] $procmux$528_Y [0] $procmux$528_Y [0] }
|
|
Consolidated identical input bits for $mux cell $procmux$564:
|
|
Old ports: A=23'00000000000000000000000, B=23'11111111111111111111111, Y=$procmux$564_Y
|
|
New ports: A=1'0, B=1'1, Y=$procmux$564_Y [0]
|
|
New connections: $procmux$564_Y [22:1] = { $procmux$564_Y [0] $procmux$564_Y [0] $procmux$564_Y [0] $procmux$564_Y [0] $procmux$564_Y [0] $procmux$564_Y [0] $procmux$564_Y [0] $procmux$564_Y [0] $procmux$564_Y [0] $procmux$564_Y [0] $procmux$564_Y [0] $procmux$564_Y [0] $procmux$564_Y [0] $procmux$564_Y [0] $procmux$564_Y [0] $procmux$564_Y [0] $procmux$564_Y [0] $procmux$564_Y [0] $procmux$564_Y [0] $procmux$564_Y [0] $procmux$564_Y [0] $procmux$564_Y [0] }
|
|
Consolidated identical input bits for $mux cell $procmux$510:
|
|
Old ports: A=23'00000000000000000000000, B=23'11111111111111111111111, Y=$procmux$510_Y
|
|
New ports: A=1'0, B=1'1, Y=$procmux$510_Y [0]
|
|
New connections: $procmux$510_Y [22:1] = { $procmux$510_Y [0] $procmux$510_Y [0] $procmux$510_Y [0] $procmux$510_Y [0] $procmux$510_Y [0] $procmux$510_Y [0] $procmux$510_Y [0] $procmux$510_Y [0] $procmux$510_Y [0] $procmux$510_Y [0] $procmux$510_Y [0] $procmux$510_Y [0] $procmux$510_Y [0] $procmux$510_Y [0] $procmux$510_Y [0] $procmux$510_Y [0] $procmux$510_Y [0] $procmux$510_Y [0] $procmux$510_Y [0] $procmux$510_Y [0] $procmux$510_Y [0] $procmux$510_Y [0] }
|
|
New ctrl vector for $pmux cell $procmux$691: { $procmux$692_CMP $auto$opt_reduce.cc:137:opt_pmux$776 $procmux$696_CMP }
|
|
Consolidated identical input bits for $mux cell $procmux$546:
|
|
Old ports: A=23'00000000000000000000000, B=23'11111111111111111111111, Y=$procmux$546_Y
|
|
New ports: A=1'0, B=1'1, Y=$procmux$546_Y [0]
|
|
New connections: $procmux$546_Y [22:1] = { $procmux$546_Y [0] $procmux$546_Y [0] $procmux$546_Y [0] $procmux$546_Y [0] $procmux$546_Y [0] $procmux$546_Y [0] $procmux$546_Y [0] $procmux$546_Y [0] $procmux$546_Y [0] $procmux$546_Y [0] $procmux$546_Y [0] $procmux$546_Y [0] $procmux$546_Y [0] $procmux$546_Y [0] $procmux$546_Y [0] $procmux$546_Y [0] $procmux$546_Y [0] $procmux$546_Y [0] $procmux$546_Y [0] $procmux$546_Y [0] $procmux$546_Y [0] $procmux$546_Y [0] }
|
|
Optimizing cells in module \neural_director.
|
|
Consolidated identical input bits for $mux cell $procmux$648:
|
|
Old ports: A=$2$memwr$\q_x_base$hardware/v2/rtl/neural_director.v:147$234_EN[22:0]$310, B=23'00000000000000000000000, Y=$0$memwr$\q_x_base$hardware/v2/rtl/neural_director.v:147$234_EN[22:0]$261
|
|
New ports: A=$procmux$564_Y [0], B=1'0, Y=$0$memwr$\q_x_base$hardware/v2/rtl/neural_director.v:147$234_EN[22:0]$261 [0]
|
|
New connections: $0$memwr$\q_x_base$hardware/v2/rtl/neural_director.v:147$234_EN[22:0]$261 [22:1] = { $0$memwr$\q_x_base$hardware/v2/rtl/neural_director.v:147$234_EN[22:0]$261 [0] $0$memwr$\q_x_base$hardware/v2/rtl/neural_director.v:147$234_EN[22:0]$261 [0] $0$memwr$\q_x_base$hardware/v2/rtl/neural_director.v:147$234_EN[22:0]$261 [0] $0$memwr$\q_x_base$hardware/v2/rtl/neural_director.v:147$234_EN[22:0]$261 [0] $0$memwr$\q_x_base$hardware/v2/rtl/neural_director.v:147$234_EN[22:0]$261 [0] $0$memwr$\q_x_base$hardware/v2/rtl/neural_director.v:147$234_EN[22:0]$261 [0] $0$memwr$\q_x_base$hardware/v2/rtl/neural_director.v:147$234_EN[22:0]$261 [0] $0$memwr$\q_x_base$hardware/v2/rtl/neural_director.v:147$234_EN[22:0]$261 [0] $0$memwr$\q_x_base$hardware/v2/rtl/neural_director.v:147$234_EN[22:0]$261 [0] $0$memwr$\q_x_base$hardware/v2/rtl/neural_director.v:147$234_EN[22:0]$261 [0] $0$memwr$\q_x_base$hardware/v2/rtl/neural_director.v:147$234_EN[22:0]$261 [0] $0$memwr$\q_x_base$hardware/v2/rtl/neural_director.v:147$234_EN[22:0]$261 [0] $0$memwr$\q_x_base$hardware/v2/rtl/neural_director.v:147$234_EN[22:0]$261 [0] $0$memwr$\q_x_base$hardware/v2/rtl/neural_director.v:147$234_EN[22:0]$261 [0] $0$memwr$\q_x_base$hardware/v2/rtl/neural_director.v:147$234_EN[22:0]$261 [0] $0$memwr$\q_x_base$hardware/v2/rtl/neural_director.v:147$234_EN[22:0]$261 [0] $0$memwr$\q_x_base$hardware/v2/rtl/neural_director.v:147$234_EN[22:0]$261 [0] $0$memwr$\q_x_base$hardware/v2/rtl/neural_director.v:147$234_EN[22:0]$261 [0] $0$memwr$\q_x_base$hardware/v2/rtl/neural_director.v:147$234_EN[22:0]$261 [0] $0$memwr$\q_x_base$hardware/v2/rtl/neural_director.v:147$234_EN[22:0]$261 [0] $0$memwr$\q_x_base$hardware/v2/rtl/neural_director.v:147$234_EN[22:0]$261 [0] $0$memwr$\q_x_base$hardware/v2/rtl/neural_director.v:147$234_EN[22:0]$261 [0] }
|
|
Consolidated identical input bits for $mux cell $procmux$639:
|
|
Old ports: A=$2$memwr$\q_w_base$hardware/v2/rtl/neural_director.v:148$235_EN[22:0]$313, B=23'00000000000000000000000, Y=$0$memwr$\q_w_base$hardware/v2/rtl/neural_director.v:148$235_EN[22:0]$264
|
|
New ports: A=$procmux$546_Y [0], B=1'0, Y=$0$memwr$\q_w_base$hardware/v2/rtl/neural_director.v:148$235_EN[22:0]$264 [0]
|
|
New connections: $0$memwr$\q_w_base$hardware/v2/rtl/neural_director.v:148$235_EN[22:0]$264 [22:1] = { $0$memwr$\q_w_base$hardware/v2/rtl/neural_director.v:148$235_EN[22:0]$264 [0] $0$memwr$\q_w_base$hardware/v2/rtl/neural_director.v:148$235_EN[22:0]$264 [0] $0$memwr$\q_w_base$hardware/v2/rtl/neural_director.v:148$235_EN[22:0]$264 [0] $0$memwr$\q_w_base$hardware/v2/rtl/neural_director.v:148$235_EN[22:0]$264 [0] $0$memwr$\q_w_base$hardware/v2/rtl/neural_director.v:148$235_EN[22:0]$264 [0] $0$memwr$\q_w_base$hardware/v2/rtl/neural_director.v:148$235_EN[22:0]$264 [0] $0$memwr$\q_w_base$hardware/v2/rtl/neural_director.v:148$235_EN[22:0]$264 [0] $0$memwr$\q_w_base$hardware/v2/rtl/neural_director.v:148$235_EN[22:0]$264 [0] $0$memwr$\q_w_base$hardware/v2/rtl/neural_director.v:148$235_EN[22:0]$264 [0] $0$memwr$\q_w_base$hardware/v2/rtl/neural_director.v:148$235_EN[22:0]$264 [0] $0$memwr$\q_w_base$hardware/v2/rtl/neural_director.v:148$235_EN[22:0]$264 [0] $0$memwr$\q_w_base$hardware/v2/rtl/neural_director.v:148$235_EN[22:0]$264 [0] $0$memwr$\q_w_base$hardware/v2/rtl/neural_director.v:148$235_EN[22:0]$264 [0] $0$memwr$\q_w_base$hardware/v2/rtl/neural_director.v:148$235_EN[22:0]$264 [0] $0$memwr$\q_w_base$hardware/v2/rtl/neural_director.v:148$235_EN[22:0]$264 [0] $0$memwr$\q_w_base$hardware/v2/rtl/neural_director.v:148$235_EN[22:0]$264 [0] $0$memwr$\q_w_base$hardware/v2/rtl/neural_director.v:148$235_EN[22:0]$264 [0] $0$memwr$\q_w_base$hardware/v2/rtl/neural_director.v:148$235_EN[22:0]$264 [0] $0$memwr$\q_w_base$hardware/v2/rtl/neural_director.v:148$235_EN[22:0]$264 [0] $0$memwr$\q_w_base$hardware/v2/rtl/neural_director.v:148$235_EN[22:0]$264 [0] $0$memwr$\q_w_base$hardware/v2/rtl/neural_director.v:148$235_EN[22:0]$264 [0] $0$memwr$\q_w_base$hardware/v2/rtl/neural_director.v:148$235_EN[22:0]$264 [0] }
|
|
Consolidated identical input bits for $mux cell $procmux$630:
|
|
Old ports: A=$2$memwr$\q_n_tiles$hardware/v2/rtl/neural_director.v:149$236_EN[15:0]$316, B=16'0000000000000000, Y=$0$memwr$\q_n_tiles$hardware/v2/rtl/neural_director.v:149$236_EN[15:0]$267
|
|
New ports: A=$procmux$528_Y [0], B=1'0, Y=$0$memwr$\q_n_tiles$hardware/v2/rtl/neural_director.v:149$236_EN[15:0]$267 [0]
|
|
New connections: $0$memwr$\q_n_tiles$hardware/v2/rtl/neural_director.v:149$236_EN[15:0]$267 [15:1] = { $0$memwr$\q_n_tiles$hardware/v2/rtl/neural_director.v:149$236_EN[15:0]$267 [0] $0$memwr$\q_n_tiles$hardware/v2/rtl/neural_director.v:149$236_EN[15:0]$267 [0] $0$memwr$\q_n_tiles$hardware/v2/rtl/neural_director.v:149$236_EN[15:0]$267 [0] $0$memwr$\q_n_tiles$hardware/v2/rtl/neural_director.v:149$236_EN[15:0]$267 [0] $0$memwr$\q_n_tiles$hardware/v2/rtl/neural_director.v:149$236_EN[15:0]$267 [0] $0$memwr$\q_n_tiles$hardware/v2/rtl/neural_director.v:149$236_EN[15:0]$267 [0] $0$memwr$\q_n_tiles$hardware/v2/rtl/neural_director.v:149$236_EN[15:0]$267 [0] $0$memwr$\q_n_tiles$hardware/v2/rtl/neural_director.v:149$236_EN[15:0]$267 [0] $0$memwr$\q_n_tiles$hardware/v2/rtl/neural_director.v:149$236_EN[15:0]$267 [0] $0$memwr$\q_n_tiles$hardware/v2/rtl/neural_director.v:149$236_EN[15:0]$267 [0] $0$memwr$\q_n_tiles$hardware/v2/rtl/neural_director.v:149$236_EN[15:0]$267 [0] $0$memwr$\q_n_tiles$hardware/v2/rtl/neural_director.v:149$236_EN[15:0]$267 [0] $0$memwr$\q_n_tiles$hardware/v2/rtl/neural_director.v:149$236_EN[15:0]$267 [0] $0$memwr$\q_n_tiles$hardware/v2/rtl/neural_director.v:149$236_EN[15:0]$267 [0] $0$memwr$\q_n_tiles$hardware/v2/rtl/neural_director.v:149$236_EN[15:0]$267 [0] }
|
|
Consolidated identical input bits for $mux cell $procmux$621:
|
|
Old ports: A=$2$memwr$\q_result_addr$hardware/v2/rtl/neural_director.v:150$237_EN[22:0]$319, B=23'00000000000000000000000, Y=$0$memwr$\q_result_addr$hardware/v2/rtl/neural_director.v:150$237_EN[22:0]$270
|
|
New ports: A=$procmux$510_Y [0], B=1'0, Y=$0$memwr$\q_result_addr$hardware/v2/rtl/neural_director.v:150$237_EN[22:0]$270 [0]
|
|
New connections: $0$memwr$\q_result_addr$hardware/v2/rtl/neural_director.v:150$237_EN[22:0]$270 [22:1] = { $0$memwr$\q_result_addr$hardware/v2/rtl/neural_director.v:150$237_EN[22:0]$270 [0] $0$memwr$\q_result_addr$hardware/v2/rtl/neural_director.v:150$237_EN[22:0]$270 [0] $0$memwr$\q_result_addr$hardware/v2/rtl/neural_director.v:150$237_EN[22:0]$270 [0] $0$memwr$\q_result_addr$hardware/v2/rtl/neural_director.v:150$237_EN[22:0]$270 [0] $0$memwr$\q_result_addr$hardware/v2/rtl/neural_director.v:150$237_EN[22:0]$270 [0] $0$memwr$\q_result_addr$hardware/v2/rtl/neural_director.v:150$237_EN[22:0]$270 [0] $0$memwr$\q_result_addr$hardware/v2/rtl/neural_director.v:150$237_EN[22:0]$270 [0] $0$memwr$\q_result_addr$hardware/v2/rtl/neural_director.v:150$237_EN[22:0]$270 [0] $0$memwr$\q_result_addr$hardware/v2/rtl/neural_director.v:150$237_EN[22:0]$270 [0] $0$memwr$\q_result_addr$hardware/v2/rtl/neural_director.v:150$237_EN[22:0]$270 [0] $0$memwr$\q_result_addr$hardware/v2/rtl/neural_director.v:150$237_EN[22:0]$270 [0] $0$memwr$\q_result_addr$hardware/v2/rtl/neural_director.v:150$237_EN[22:0]$270 [0] $0$memwr$\q_result_addr$hardware/v2/rtl/neural_director.v:150$237_EN[22:0]$270 [0] $0$memwr$\q_result_addr$hardware/v2/rtl/neural_director.v:150$237_EN[22:0]$270 [0] $0$memwr$\q_result_addr$hardware/v2/rtl/neural_director.v:150$237_EN[22:0]$270 [0] $0$memwr$\q_result_addr$hardware/v2/rtl/neural_director.v:150$237_EN[22:0]$270 [0] $0$memwr$\q_result_addr$hardware/v2/rtl/neural_director.v:150$237_EN[22:0]$270 [0] $0$memwr$\q_result_addr$hardware/v2/rtl/neural_director.v:150$237_EN[22:0]$270 [0] $0$memwr$\q_result_addr$hardware/v2/rtl/neural_director.v:150$237_EN[22:0]$270 [0] $0$memwr$\q_result_addr$hardware/v2/rtl/neural_director.v:150$237_EN[22:0]$270 [0] $0$memwr$\q_result_addr$hardware/v2/rtl/neural_director.v:150$237_EN[22:0]$270 [0] $0$memwr$\q_result_addr$hardware/v2/rtl/neural_director.v:150$237_EN[22:0]$270 [0] }
|
|
Optimizing cells in module \neural_director.
|
|
Performed a total of 9 changes.
|
|
|
|
2.13.5. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\neural_director'.
|
|
Computing hashes of 131 cells of `\neural_director'.
|
|
Finding duplicate cells in `\neural_director'.
|
|
Computing hashes of 125 cells of `\neural_director'.
|
|
Finding duplicate cells in `\neural_director'.
|
|
Computing hashes of 119 cells of `\neural_director'.
|
|
Finding duplicate cells in `\neural_director'.
|
|
<suppressed ~36 debug messages>
|
|
Removed a total of 12 cells.
|
|
|
|
2.13.6. Executing OPT_DFF pass (perform DFF optimizations).
|
|
|
|
2.13.7. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \neural_director..
|
|
Removed 0 unused cells and 56 unused wires.
|
|
<suppressed ~1 debug messages>
|
|
|
|
2.13.8. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module neural_director.
|
|
|
|
2.13.9. Rerunning OPT passes. (Maybe there is more to do..)
|
|
|
|
2.13.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \neural_director..
|
|
Creating internal representation of mux trees.
|
|
Evaluating internal representation of mux trees.
|
|
Analyzing evaluation results.
|
|
Removed 0 multiplexer ports.
|
|
<suppressed ~68 debug messages>
|
|
|
|
2.13.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \neural_director.
|
|
Performed a total of 0 changes.
|
|
|
|
2.13.12. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\neural_director'.
|
|
Computing hashes of 119 cells of `\neural_director'.
|
|
Finding duplicate cells in `\neural_director'.
|
|
Removed a total of 0 cells.
|
|
|
|
2.13.13. Executing OPT_DFF pass (perform DFF optimizations).
|
|
|
|
2.13.14. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \neural_director..
|
|
|
|
2.13.15. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module neural_director.
|
|
|
|
2.13.16. Finished fast OPT passes. (There is nothing left to do.)
|
|
|
|
2.14. Executing FSM pass (extract and optimize FSM).
|
|
|
|
2.14.1. Executing FSM_DETECT pass (finding FSMs in design).
|
|
Not marking neural_director.dir_state as FSM state register:
|
|
Register is connected to module port.
|
|
Users of register don't seem to benefit from recoding.
|
|
Not marking neural_director.job_out_slot as FSM state register:
|
|
Register is connected to module port.
|
|
Users of register don't seem to benefit from recoding.
|
|
|
|
2.14.2. Executing FSM_EXTRACT pass (extracting FSM from design).
|
|
|
|
2.14.3. Executing FSM_OPT pass (simple optimizations of FSMs).
|
|
|
|
2.14.4. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \neural_director..
|
|
|
|
2.14.5. Executing FSM_OPT pass (simple optimizations of FSMs).
|
|
|
|
2.14.6. Executing FSM_RECODE pass (re-assigning FSM state encoding).
|
|
|
|
2.14.7. Executing FSM_INFO pass (dumping all available information on FSM cells).
|
|
|
|
2.14.8. Executing FSM_MAP pass (mapping FSMs to basic logic).
|
|
|
|
2.15. Executing OPT pass (performing simple optimizations).
|
|
|
|
2.15.1. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module neural_director.
|
|
|
|
2.15.2. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\neural_director'.
|
|
Computing hashes of 119 cells of `\neural_director'.
|
|
Finding duplicate cells in `\neural_director'.
|
|
Removed a total of 0 cells.
|
|
|
|
2.15.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \neural_director..
|
|
Creating internal representation of mux trees.
|
|
Evaluating internal representation of mux trees.
|
|
Analyzing evaluation results.
|
|
Removed 0 multiplexer ports.
|
|
<suppressed ~68 debug messages>
|
|
|
|
2.15.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \neural_director.
|
|
Performed a total of 0 changes.
|
|
|
|
2.15.5. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\neural_director'.
|
|
Computing hashes of 119 cells of `\neural_director'.
|
|
Finding duplicate cells in `\neural_director'.
|
|
Removed a total of 0 cells.
|
|
|
|
2.15.6. Executing OPT_DFF pass (perform DFF optimizations).
|
|
Adding SRST signal on $procdff$739 ($dff) from module neural_director (D = $procmux$682_Y, Q = \q_head, rval = 3'000).
|
|
Adding EN signal on $auto$ff.cc:337:slice$777 ($sdff) from module neural_director (D = $ternary$hardware/v2/rtl/neural_director.v:196$399_Y, Q = \q_head).
|
|
Adding EN signal on $procdff$738 ($dff) from module neural_director (D = 1'0, Q = \dir_error).
|
|
Adding SRST signal on $procdff$737 ($dff) from module neural_director (D = $procmux$691_Y, Q = \dir_state, rval = 4'0000).
|
|
Adding EN signal on $auto$ff.cc:337:slice$780 ($sdff) from module neural_director (D = $procmux$691_Y, Q = \dir_state).
|
|
Adding SRST signal on $procdff$731 ($dff) from module neural_director (D = $2$lookahead\slot_x_base$247[91:0]$336, Q = \slot_x_base, rval = 92'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000).
|
|
Adding EN signal on $auto$ff.cc:337:slice$788 ($sdff) from module neural_director (D = $or$hardware/v2/rtl/neural_director.v:191$359_Y, Q = \slot_x_base).
|
|
Adding SRST signal on $procdff$740 ($dff) from module neural_director (D = $procmux$675_Y, Q = \q_tail, rval = 3'000).
|
|
Adding EN signal on $auto$ff.cc:337:slice$790 ($sdff) from module neural_director (D = $ternary$hardware/v2/rtl/neural_director.v:152$325_Y, Q = \q_tail).
|
|
Adding SRST signal on $procdff$732 ($dff) from module neural_director (D = $2$lookahead\slot_w_base$248[91:0]$337, Q = \slot_w_base, rval = 92'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000).
|
|
Adding EN signal on $auto$ff.cc:337:slice$792 ($sdff) from module neural_director (D = $or$hardware/v2/rtl/neural_director.v:192$369_Y, Q = \slot_w_base).
|
|
Adding SRST signal on $procdff$733 ($dff) from module neural_director (D = $2$lookahead\slot_n_tiles$249[63:0]$338, Q = \slot_n_tiles, rval = 64'0000000000000000000000000000000000000000000000000000000000000000).
|
|
Adding EN signal on $auto$ff.cc:337:slice$794 ($sdff) from module neural_director (D = $or$hardware/v2/rtl/neural_director.v:193$379_Y, Q = \slot_n_tiles).
|
|
Adding SRST signal on $procdff$736 ($dff) from module neural_director (D = $procmux$701_Y, Q = \job_out_slot, rval = 2'00).
|
|
Adding EN signal on $auto$ff.cc:337:slice$796 ($sdff) from module neural_director (D = \done_slot_idx, Q = \job_out_slot).
|
|
Adding SRST signal on $procdff$735 ($dff) from module neural_director (D = $procmux$581_Y, Q = \job_out_done, rval = 1'0).
|
|
Adding SRST signal on $procdff$734 ($dff) from module neural_director (D = $2$lookahead\slot_result_addr$250[91:0]$339, Q = \slot_result_addr, rval = 92'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000).
|
|
Adding EN signal on $auto$ff.cc:337:slice$799 ($sdff) from module neural_director (D = $or$hardware/v2/rtl/neural_director.v:194$389_Y, Q = \slot_result_addr).
|
|
Adding SRST signal on $procdff$730 ($dff) from module neural_director (D = $or$hardware/v2/rtl/neural_director.v:190$349_Y, Q = \slot_job_start, rval = 4'0000).
|
|
Adding SRST signal on $procdff$742 ($dff) from module neural_director (D = $2$lookahead\slot_busy$251[3:0]$340, Q = \slot_busy, rval = 4'0000).
|
|
Adding SRST signal on $procdff$741 ($dff) from module neural_director (D = $procmux$605_Y, Q = \q_count, rval = 4'0000).
|
|
Adding EN signal on $auto$ff.cc:337:slice$807 ($sdff) from module neural_director (D = $procmux$605_Y, Q = \q_count).
|
|
Setting constant 0-bit at position 0 on $auto$ff.cc:337:slice$779 ($dffe) from module neural_director.
|
|
|
|
2.15.7. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \neural_director..
|
|
Removed 21 unused cells and 21 unused wires.
|
|
<suppressed ~22 debug messages>
|
|
|
|
2.15.8. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module neural_director.
|
|
<suppressed ~2 debug messages>
|
|
|
|
2.15.9. Rerunning OPT passes. (Maybe there is more to do..)
|
|
|
|
2.15.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \neural_director..
|
|
Creating internal representation of mux trees.
|
|
Evaluating internal representation of mux trees.
|
|
Analyzing evaluation results.
|
|
Removed 0 multiplexer ports.
|
|
<suppressed ~41 debug messages>
|
|
|
|
2.15.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \neural_director.
|
|
Performed a total of 0 changes.
|
|
|
|
2.15.12. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\neural_director'.
|
|
Computing hashes of 103 cells of `\neural_director'.
|
|
Finding duplicate cells in `\neural_director'.
|
|
Removed a total of 0 cells.
|
|
|
|
2.15.13. Executing OPT_DFF pass (perform DFF optimizations).
|
|
|
|
2.15.14. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \neural_director..
|
|
|
|
2.15.15. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module neural_director.
|
|
|
|
2.15.16. Finished fast OPT passes. (There is nothing left to do.)
|
|
|
|
2.16. Executing WREDUCE pass (reducing word size of cells).
|
|
Removed top 26 bits (of 33) from port A of cell neural_director.$neg$hardware/v2/rtl/neural_director.v:193$377 ($neg).
|
|
Converting cell neural_director.$neg$hardware/v2/rtl/neural_director.v:193$377 ($neg) from signed to unsigned.
|
|
Removed top 1 bits (of 7) from port A of cell neural_director.$neg$hardware/v2/rtl/neural_director.v:193$377 ($neg).
|
|
Removed top 27 bits (of 32) from port B of cell neural_director.$mul$hardware/v2/rtl/neural_director.v:194$380 ($mul).
|
|
Removed top 25 bits (of 32) from port Y of cell neural_director.$mul$hardware/v2/rtl/neural_director.v:194$380 ($mul).
|
|
Removed top 25 bits (of 33) from port A of cell neural_director.$neg$hardware/v2/rtl/neural_director.v:194$387 ($neg).
|
|
Converting cell neural_director.$neg$hardware/v2/rtl/neural_director.v:194$387 ($neg) from signed to unsigned.
|
|
Removed top 1 bits (of 8) from port A of cell neural_director.$neg$hardware/v2/rtl/neural_director.v:194$387 ($neg).
|
|
Converting cell neural_director.$neg$hardware/v2/rtl/neural_director.v:195$394 ($neg) from signed to unsigned.
|
|
Removed top 1 bits (of 3) from port A of cell neural_director.$neg$hardware/v2/rtl/neural_director.v:195$394 ($neg).
|
|
Removed top 1 bits (of 2) from port B of cell neural_director.$procmux$606_CMP0 ($eq).
|
|
Removed top 2 bits (of 4) from port B of cell neural_director.$procmux$692_CMP0 ($eq).
|
|
Removed top 2 bits (of 4) from port B of cell neural_director.$procmux$693_CMP0 ($eq).
|
|
Removed top 3 bits (of 4) from port B of cell neural_director.$procmux$696_CMP0 ($eq).
|
|
Removed top 25 bits (of 32) from wire neural_director.$add$hardware/v2/rtl/neural_director.v:191$351_Y.
|
|
|
|
2.17. Executing PEEPOPT pass (run peephole optimizers).
|
|
left shiftmul pattern in neural_director: shift=$shift$hardware/v2/rtl/neural_director.v:194$388, mul=$mul$hardware/v2/rtl/neural_director.v:194$380
|
|
left shiftmul pattern in neural_director: shift=$shift$hardware/v2/rtl/neural_director.v:194$383, mul=$mul$hardware/v2/rtl/neural_director.v:194$380
|
|
left shiftmul pattern in neural_director: shift=$shift$hardware/v2/rtl/neural_director.v:192$368, mul=$mul$hardware/v2/rtl/neural_director.v:194$380
|
|
left shiftmul pattern in neural_director: shift=$shift$hardware/v2/rtl/neural_director.v:191$358, mul=$mul$hardware/v2/rtl/neural_director.v:194$380
|
|
|
|
2.18. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \neural_director..
|
|
Removed 2 unused cells and 3 unused wires.
|
|
<suppressed ~3 debug messages>
|
|
|
|
2.19. Executing SHARE pass (SAT-based resource sharing).
|
|
|
|
2.20. Executing TECHMAP pass (map to technology primitives).
|
|
|
|
2.20.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/cmp2lut.v
|
|
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/cmp2lut.v' to AST representation.
|
|
Generating RTLIL representation for module `\_90_lut_cmp_'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
2.20.2. Continuing TECHMAP pass.
|
|
No more expansions possible.
|
|
<suppressed ~6 debug messages>
|
|
|
|
2.21. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module neural_director.
|
|
|
|
2.22. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \neural_director..
|
|
|
|
2.23. Executing TECHMAP pass (map to technology primitives).
|
|
|
|
2.23.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/mul2dsp.v
|
|
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/mul2dsp.v' to AST representation.
|
|
Generating RTLIL representation for module `\_80_mul'.
|
|
Generating RTLIL representation for module `\_90_soft_mul'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
2.23.2. Continuing TECHMAP pass.
|
|
No more expansions possible.
|
|
<suppressed ~4 debug messages>
|
|
|
|
2.24. Executing TECHMAP pass (map to technology primitives).
|
|
|
|
2.24.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/dsp_map_18x18.v
|
|
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/dsp_map_18x18.v' to AST representation.
|
|
Generating RTLIL representation for module `$__MUL18X18'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
2.24.2. Continuing TECHMAP pass.
|
|
No more expansions possible.
|
|
<suppressed ~3 debug messages>
|
|
|
|
2.25. Executing ALUMACC pass (create $alu and $macc cells).
|
|
Extracting $alu and $macc cells in module neural_director:
|
|
creating $macc model for $auto$peepopt_pm.h:1040:block_9$817 ($neg).
|
|
creating $macc model for $auto$peepopt_pm.h:1040:block_9$814 ($neg).
|
|
creating $macc model for $sub$hardware/v2/rtl/neural_director.v:214$406 ($sub).
|
|
creating $macc model for $add$hardware/v2/rtl/neural_director.v:213$405 ($add).
|
|
creating $macc model for $add$hardware/v2/rtl/neural_director.v:196$398 ($add).
|
|
creating $macc model for $neg$hardware/v2/rtl/neural_director.v:195$394 ($neg).
|
|
creating $macc model for $auto$peepopt_pm.h:1040:block_9$820 ($neg).
|
|
creating $macc model for $auto$peepopt_pm.h:1040:block_9$823 ($neg).
|
|
creating $macc model for $neg$hardware/v2/rtl/neural_director.v:193$377 ($neg).
|
|
creating $macc model for $add$hardware/v2/rtl/neural_director.v:152$324 ($add).
|
|
creating $alu model for $macc $add$hardware/v2/rtl/neural_director.v:152$324.
|
|
creating $alu model for $macc $neg$hardware/v2/rtl/neural_director.v:193$377.
|
|
creating $alu model for $macc $auto$peepopt_pm.h:1040:block_9$823.
|
|
creating $alu model for $macc $auto$peepopt_pm.h:1040:block_9$820.
|
|
creating $alu model for $macc $neg$hardware/v2/rtl/neural_director.v:195$394.
|
|
creating $alu model for $macc $add$hardware/v2/rtl/neural_director.v:196$398.
|
|
creating $alu model for $macc $add$hardware/v2/rtl/neural_director.v:213$405.
|
|
creating $alu model for $macc $sub$hardware/v2/rtl/neural_director.v:214$406.
|
|
creating $alu model for $macc $auto$peepopt_pm.h:1040:block_9$814.
|
|
creating $alu model for $macc $auto$peepopt_pm.h:1040:block_9$817.
|
|
creating $alu cell for $sub$hardware/v2/rtl/neural_director.v:214$406: $auto$alumacc.cc:548:replace_alu$825
|
|
creating $alu cell for $add$hardware/v2/rtl/neural_director.v:213$405: $auto$alumacc.cc:548:replace_alu$828
|
|
creating $alu cell for $add$hardware/v2/rtl/neural_director.v:196$398: $auto$alumacc.cc:548:replace_alu$831
|
|
creating $alu cell for $neg$hardware/v2/rtl/neural_director.v:195$394: $auto$alumacc.cc:548:replace_alu$834
|
|
creating $alu cell for $auto$peepopt_pm.h:1040:block_9$817: $auto$alumacc.cc:548:replace_alu$837
|
|
creating $alu cell for $auto$peepopt_pm.h:1040:block_9$814: $auto$alumacc.cc:548:replace_alu$840
|
|
creating $alu cell for $auto$peepopt_pm.h:1040:block_9$820: $auto$alumacc.cc:548:replace_alu$843
|
|
creating $alu cell for $auto$peepopt_pm.h:1040:block_9$823: $auto$alumacc.cc:548:replace_alu$846
|
|
creating $alu cell for $neg$hardware/v2/rtl/neural_director.v:193$377: $auto$alumacc.cc:548:replace_alu$849
|
|
creating $alu cell for $add$hardware/v2/rtl/neural_director.v:152$324: $auto$alumacc.cc:548:replace_alu$852
|
|
created 10 $alu and 0 $macc cells.
|
|
|
|
2.26. Executing OPT pass (performing simple optimizations).
|
|
|
|
2.26.1. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module neural_director.
|
|
|
|
2.26.2. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\neural_director'.
|
|
Computing hashes of 105 cells of `\neural_director'.
|
|
Finding duplicate cells in `\neural_director'.
|
|
Computing hashes of 102 cells of `\neural_director'.
|
|
Finding duplicate cells in `\neural_director'.
|
|
<suppressed ~15 debug messages>
|
|
Removed a total of 3 cells.
|
|
|
|
2.26.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \neural_director..
|
|
Creating internal representation of mux trees.
|
|
Evaluating internal representation of mux trees.
|
|
Analyzing evaluation results.
|
|
Removed 0 multiplexer ports.
|
|
<suppressed ~41 debug messages>
|
|
|
|
2.26.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \neural_director.
|
|
Performed a total of 0 changes.
|
|
|
|
2.26.5. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\neural_director'.
|
|
Computing hashes of 102 cells of `\neural_director'.
|
|
Finding duplicate cells in `\neural_director'.
|
|
Removed a total of 0 cells.
|
|
|
|
2.26.6. Executing OPT_DFF pass (perform DFF optimizations).
|
|
|
|
2.26.7. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \neural_director..
|
|
Removed 0 unused cells and 9 unused wires.
|
|
<suppressed ~1 debug messages>
|
|
|
|
2.26.8. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module neural_director.
|
|
|
|
2.26.9. Rerunning OPT passes. (Maybe there is more to do..)
|
|
|
|
2.26.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \neural_director..
|
|
Creating internal representation of mux trees.
|
|
Evaluating internal representation of mux trees.
|
|
Analyzing evaluation results.
|
|
Removed 0 multiplexer ports.
|
|
<suppressed ~41 debug messages>
|
|
|
|
2.26.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \neural_director.
|
|
Performed a total of 0 changes.
|
|
|
|
2.26.12. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\neural_director'.
|
|
Computing hashes of 102 cells of `\neural_director'.
|
|
Finding duplicate cells in `\neural_director'.
|
|
Removed a total of 0 cells.
|
|
|
|
2.26.13. Executing OPT_DFF pass (perform DFF optimizations).
|
|
|
|
2.26.14. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \neural_director..
|
|
|
|
2.26.15. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module neural_director.
|
|
|
|
2.26.16. Finished fast OPT passes. (There is nothing left to do.)
|
|
|
|
2.27. Executing MEMORY pass.
|
|
|
|
2.27.1. Executing OPT_MEM pass (optimize memories).
|
|
Performed a total of 0 transformations.
|
|
|
|
2.27.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations).
|
|
Performed a total of 0 transformations.
|
|
|
|
2.27.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths).
|
|
Analyzing neural_director.q_result_addr write port 0.
|
|
Analyzing neural_director.q_n_tiles write port 0.
|
|
Analyzing neural_director.q_w_base write port 0.
|
|
Analyzing neural_director.q_x_base write port 0.
|
|
|
|
2.27.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs).
|
|
|
|
2.27.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd).
|
|
Checking read port `\q_result_addr'[0] in module `\neural_director': no output FF found.
|
|
Checking read port `\q_n_tiles'[0] in module `\neural_director': no output FF found.
|
|
Checking read port `\q_w_base'[0] in module `\neural_director': no output FF found.
|
|
Checking read port `\q_x_base'[0] in module `\neural_director': no output FF found.
|
|
Checking read port address `\q_result_addr'[0] in module `\neural_director': merged address FF to cell.
|
|
Checking read port address `\q_n_tiles'[0] in module `\neural_director': merged address FF to cell.
|
|
Checking read port address `\q_w_base'[0] in module `\neural_director': merged address FF to cell.
|
|
Checking read port address `\q_x_base'[0] in module `\neural_director': merged address FF to cell.
|
|
|
|
2.27.6. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \neural_director..
|
|
|
|
2.27.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells).
|
|
|
|
2.27.8. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide).
|
|
Performed a total of 0 transformations.
|
|
|
|
2.27.9. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \neural_director..
|
|
|
|
2.27.10. Executing MEMORY_COLLECT pass (generating $mem cells).
|
|
|
|
2.28. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \neural_director..
|
|
|
|
2.29. Executing MEMORY_LIBMAP pass (mapping memories to cells).
|
|
mapping memory neural_director.q_result_addr via $__TRELLIS_DPR16X4_
|
|
Extracted addr FF from read port 0 of neural_director.q_result_addr: $\q_result_addr$rdreg[0]
|
|
mapping memory neural_director.q_n_tiles via $__TRELLIS_DPR16X4_
|
|
Extracted addr FF from read port 0 of neural_director.q_n_tiles: $\q_n_tiles$rdreg[0]
|
|
mapping memory neural_director.q_w_base via $__TRELLIS_DPR16X4_
|
|
Extracted addr FF from read port 0 of neural_director.q_w_base: $\q_w_base$rdreg[0]
|
|
mapping memory neural_director.q_x_base via $__TRELLIS_DPR16X4_
|
|
Extracted addr FF from read port 0 of neural_director.q_x_base: $\q_x_base$rdreg[0]
|
|
<suppressed ~1782 debug messages>
|
|
|
|
2.30. Executing TECHMAP pass (map to technology primitives).
|
|
|
|
2.30.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/lutrams_map_trellis.v
|
|
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/lutrams_map_trellis.v' to AST representation.
|
|
Generating RTLIL representation for module `$__TRELLIS_DPR16X4_'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
2.30.2. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/brams_map_16kd.v
|
|
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/brams_map_16kd.v' to AST representation.
|
|
Generating RTLIL representation for module `$__DP16KD_'.
|
|
Generating RTLIL representation for module `$__PDPW16KD_'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
2.30.3. Continuing TECHMAP pass.
|
|
Using template $paramod$04778961cc1285a5efea28f98f28381eb2862208$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
|
|
No more expansions possible.
|
|
<suppressed ~40 debug messages>
|
|
|
|
2.31. Executing OPT pass (performing simple optimizations).
|
|
|
|
2.31.1. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module neural_director.
|
|
<suppressed ~15 debug messages>
|
|
|
|
2.31.2. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\neural_director'.
|
|
Computing hashes of 115 cells of `\neural_director'.
|
|
Finding duplicate cells in `\neural_director'.
|
|
Computing hashes of 112 cells of `\neural_director'.
|
|
Finding duplicate cells in `\neural_director'.
|
|
Computing hashes of 109 cells of `\neural_director'.
|
|
Finding duplicate cells in `\neural_director'.
|
|
Computing hashes of 106 cells of `\neural_director'.
|
|
Finding duplicate cells in `\neural_director'.
|
|
<suppressed ~27 debug messages>
|
|
Removed a total of 9 cells.
|
|
|
|
2.31.3. Executing OPT_DFF pass (perform DFF optimizations).
|
|
|
|
2.31.4. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \neural_director..
|
|
Removed 0 unused cells and 158 unused wires.
|
|
<suppressed ~1 debug messages>
|
|
|
|
2.31.5. Finished fast OPT passes.
|
|
|
|
2.32. Executing MEMORY_MAP pass (converting memories to logic and flip-flops).
|
|
|
|
2.33. Executing OPT pass (performing simple optimizations).
|
|
|
|
2.33.1. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module neural_director.
|
|
|
|
2.33.2. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\neural_director'.
|
|
Computing hashes of 106 cells of `\neural_director'.
|
|
Finding duplicate cells in `\neural_director'.
|
|
Removed a total of 0 cells.
|
|
|
|
2.33.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \neural_director..
|
|
Creating internal representation of mux trees.
|
|
Evaluating internal representation of mux trees.
|
|
Analyzing evaluation results.
|
|
Removed 0 multiplexer ports.
|
|
<suppressed ~25 debug messages>
|
|
|
|
2.33.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \neural_director.
|
|
Consolidated identical input bits for $pmux cell $procmux$691:
|
|
Old ports: A=4'0011, B=8'00010010, Y=$procmux$691_Y
|
|
New ports: A=2'11, B=4'0110, Y=$procmux$691_Y [1:0]
|
|
New connections: $procmux$691_Y [3:2] = 2'00
|
|
Consolidated identical input bits for $mux cell $procmux$716:
|
|
Old ports: A=2'00, B=2'11, Y=$1\done_slot_idx[1:0]
|
|
New ports: A=1'0, B=1'1, Y=$1\done_slot_idx[1:0] [0]
|
|
New connections: $1\done_slot_idx[1:0] [1] = $1\done_slot_idx[1:0] [0]
|
|
Consolidated identical input bits for $mux cell $procmux$728:
|
|
Old ports: A=2'00, B=2'11, Y=$1\free_slot_idx[1:0]
|
|
New ports: A=1'0, B=1'1, Y=$1\free_slot_idx[1:0] [0]
|
|
New connections: $1\free_slot_idx[1:0] [1] = $1\free_slot_idx[1:0] [0]
|
|
Optimizing cells in module \neural_director.
|
|
Performed a total of 3 changes.
|
|
|
|
2.33.5. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\neural_director'.
|
|
Computing hashes of 106 cells of `\neural_director'.
|
|
Finding duplicate cells in `\neural_director'.
|
|
Removed a total of 0 cells.
|
|
|
|
2.33.6. Executing OPT_DFF pass (perform DFF optimizations).
|
|
Adding SRST signal on $\q_result_addr$rdreg[0] ($dff) from module neural_director (D = $auto$rtlil.cc:3402:Mux$861, Q = $\q_n_tiles$rdreg[0]$q, rval = 3'000).
|
|
|
|
2.33.7. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \neural_director..
|
|
Removed 1 unused cells and 1 unused wires.
|
|
<suppressed ~2 debug messages>
|
|
|
|
2.33.8. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module neural_director.
|
|
<suppressed ~2 debug messages>
|
|
|
|
2.33.9. Rerunning OPT passes. (Maybe there is more to do..)
|
|
|
|
2.33.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \neural_director..
|
|
Creating internal representation of mux trees.
|
|
Evaluating internal representation of mux trees.
|
|
Analyzing evaluation results.
|
|
Removed 0 multiplexer ports.
|
|
<suppressed ~22 debug messages>
|
|
|
|
2.33.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \neural_director.
|
|
Performed a total of 0 changes.
|
|
|
|
2.33.12. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\neural_director'.
|
|
Computing hashes of 103 cells of `\neural_director'.
|
|
Finding duplicate cells in `\neural_director'.
|
|
Removed a total of 0 cells.
|
|
|
|
2.33.13. Executing OPT_DFF pass (perform DFF optimizations).
|
|
Setting constant 0-bit at position 2 on $auto$ff.cc:337:slice$781 ($sdffe) from module neural_director.
|
|
Setting constant 0-bit at position 3 on $auto$ff.cc:337:slice$781 ($sdffe) from module neural_director.
|
|
|
|
2.33.14. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \neural_director..
|
|
Removed 0 unused cells and 2 unused wires.
|
|
<suppressed ~1 debug messages>
|
|
|
|
2.33.15. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module neural_director.
|
|
<suppressed ~1 debug messages>
|
|
|
|
2.33.16. Rerunning OPT passes. (Maybe there is more to do..)
|
|
|
|
2.33.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \neural_director..
|
|
Creating internal representation of mux trees.
|
|
Evaluating internal representation of mux trees.
|
|
Analyzing evaluation results.
|
|
Removed 0 multiplexer ports.
|
|
<suppressed ~22 debug messages>
|
|
|
|
2.33.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \neural_director.
|
|
Performed a total of 0 changes.
|
|
|
|
2.33.19. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\neural_director'.
|
|
Computing hashes of 103 cells of `\neural_director'.
|
|
Finding duplicate cells in `\neural_director'.
|
|
Removed a total of 0 cells.
|
|
|
|
2.33.20. Executing OPT_DFF pass (perform DFF optimizations).
|
|
|
|
2.33.21. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \neural_director..
|
|
|
|
2.33.22. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module neural_director.
|
|
|
|
2.33.23. Finished fast OPT passes. (There is nothing left to do.)
|
|
|
|
2.34. Executing TECHMAP pass (map to technology primitives).
|
|
|
|
2.34.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/techmap.v
|
|
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/techmap.v' to AST representation.
|
|
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
|
|
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
|
|
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
|
|
Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
|
|
Generating RTLIL representation for module `\_90_simplemap_various'.
|
|
Generating RTLIL representation for module `\_90_simplemap_registers'.
|
|
Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
|
|
Generating RTLIL representation for module `\_90_shift_shiftx'.
|
|
Generating RTLIL representation for module `\_90_fa'.
|
|
Generating RTLIL representation for module `\_90_lcu_brent_kung'.
|
|
Generating RTLIL representation for module `\_90_alu'.
|
|
Generating RTLIL representation for module `\_90_macc'.
|
|
Generating RTLIL representation for module `\_90_alumacc'.
|
|
Generating RTLIL representation for module `$__div_mod_u'.
|
|
Generating RTLIL representation for module `$__div_mod_trunc'.
|
|
Generating RTLIL representation for module `\_90_div'.
|
|
Generating RTLIL representation for module `\_90_mod'.
|
|
Generating RTLIL representation for module `$__div_mod_floor'.
|
|
Generating RTLIL representation for module `\_90_divfloor'.
|
|
Generating RTLIL representation for module `\_90_modfloor'.
|
|
Generating RTLIL representation for module `\_90_pow'.
|
|
Generating RTLIL representation for module `\_90_demux'.
|
|
Generating RTLIL representation for module `\_90_lut'.
|
|
Generating RTLIL representation for module `$connect'.
|
|
Generating RTLIL representation for module `$input_port'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
2.34.2. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v
|
|
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v' to AST representation.
|
|
Generating RTLIL representation for module `\_80_ccu2c_alu'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
2.34.3. Continuing TECHMAP pass.
|
|
Using extmapper simplemap for cells of type $sdffe.
|
|
Using extmapper simplemap for cells of type $sdff.
|
|
Using extmapper simplemap for cells of type $mux.
|
|
Using template $paramod$3ef7d3dd227da7627a99c5e5a6a4deb817573e39\_90_alu for cells of type $alu.
|
|
Using template $paramod$3ef274a4ad1e446c08416d1cf6cb5ab03146d407\_80_ccu2c_alu for cells of type $alu.
|
|
Using template $paramod$c9d98d2d0793a6d8797b9c088dbedb26a7be7121\_80_ccu2c_alu for cells of type $alu.
|
|
Using template $paramod$ef8fb1849064cca7dc908988762d3374786d9fdb\_90_alu for cells of type $alu.
|
|
Using template $paramod$32a7b7b86c07519b7537abc18e96f0331f97914d\_90_alu for cells of type $alu.
|
|
Using template $paramod$8742280fdebca84e1c87f2a86ed84f62d558f4cc\_90_alu for cells of type $alu.
|
|
Using extmapper simplemap for cells of type $reduce_bool.
|
|
Using extmapper simplemap for cells of type $reduce_or.
|
|
Using extmapper simplemap for cells of type $not.
|
|
Using extmapper simplemap for cells of type $reduce_and.
|
|
Using extmapper simplemap for cells of type $ne.
|
|
Using extmapper simplemap for cells of type $logic_not.
|
|
Using extmapper simplemap for cells of type $eq.
|
|
Using extmapper simplemap for cells of type $and.
|
|
Using extmapper simplemap for cells of type $logic_and.
|
|
Using template $paramod$constmap:f30e016643cdb78b03bc6146a268597b7789262d$paramod$4e33147aa56d8c514f5e3e64af4e016a996d124e\_90_shift_shiftx for cells of type $shift.
|
|
Using extmapper simplemap for cells of type $or.
|
|
Using template $paramod$constmap:decda5b4632abbcf04bf9650a2dac76960d9cb80$paramod$08bf5f0725d292174acacf8edfe87d18d48f6e70\_90_shift_shiftx for cells of type $shift.
|
|
Analyzing pattern of constant bits for this cell:
|
|
Creating constmapped module `$paramod$constmap:5a4bd879cde68fe23882c6a271f9c4bb8714bccb$paramod$08bf5f0725d292174acacf8edfe87d18d48f6e70\_90_shift_shiftx'.
|
|
|
|
2.34.30. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module $paramod$constmap:5a4bd879cde68fe23882c6a271f9c4bb8714bccb$paramod$08bf5f0725d292174acacf8edfe87d18d48f6e70\_90_shift_shiftx..
|
|
Creating internal representation of mux trees.
|
|
Evaluating internal representation of mux trees.
|
|
Analyzing evaluation results.
|
|
dead port 2/2 on $mux $procmux$2186.
|
|
dead port 2/2 on $mux $procmux$2192.
|
|
dead port 2/2 on $mux $procmux$2198.
|
|
dead port 2/2 on $mux $procmux$2204.
|
|
dead port 2/2 on $mux $procmux$2210.
|
|
dead port 2/2 on $mux $procmux$2216.
|
|
dead port 2/2 on $mux $procmux$2222.
|
|
Removed 7 multiplexer ports.
|
|
<suppressed ~1032 debug messages>
|
|
|
|
2.34.31. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module $paramod$constmap:5a4bd879cde68fe23882c6a271f9c4bb8714bccb$paramod$08bf5f0725d292174acacf8edfe87d18d48f6e70\_90_shift_shiftx.
|
|
<suppressed ~27 debug messages>
|
|
Removed 0 unused cells and 12 unused wires.
|
|
Using template $paramod$constmap:5a4bd879cde68fe23882c6a271f9c4bb8714bccb$paramod$08bf5f0725d292174acacf8edfe87d18d48f6e70\_90_shift_shiftx for cells of type $shift.
|
|
Analyzing pattern of constant bits for this cell:
|
|
Constant input on bit 0 of port A: 1'1
|
|
Constant input on bit 1 of port A: 1'1
|
|
Constant input on bit 2 of port A: 1'1
|
|
Constant input on bit 3 of port A: 1'1
|
|
Constant input on bit 4 of port A: 1'1
|
|
Constant input on bit 5 of port A: 1'1
|
|
Constant input on bit 6 of port A: 1'1
|
|
Constant input on bit 7 of port A: 1'1
|
|
Constant input on bit 8 of port A: 1'1
|
|
Constant input on bit 9 of port A: 1'1
|
|
Constant input on bit 10 of port A: 1'1
|
|
Constant input on bit 11 of port A: 1'1
|
|
Constant input on bit 12 of port A: 1'1
|
|
Constant input on bit 13 of port A: 1'1
|
|
Constant input on bit 14 of port A: 1'1
|
|
Constant input on bit 15 of port A: 1'1
|
|
Constant input on bit 16 of port A: 1'1
|
|
Constant input on bit 17 of port A: 1'1
|
|
Constant input on bit 18 of port A: 1'1
|
|
Constant input on bit 19 of port A: 1'1
|
|
Constant input on bit 20 of port A: 1'1
|
|
Constant input on bit 21 of port A: 1'1
|
|
Constant input on bit 22 of port A: 1'1
|
|
Creating constmapped module `$paramod$constmap:fdf1d1b176de14bfd33690c77b41951c8a2dab34$paramod$4e33147aa56d8c514f5e3e64af4e016a996d124e\_90_shift_shiftx'.
|
|
|
|
2.34.32. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module $paramod$constmap:fdf1d1b176de14bfd33690c77b41951c8a2dab34$paramod$4e33147aa56d8c514f5e3e64af4e016a996d124e\_90_shift_shiftx..
|
|
Creating internal representation of mux trees.
|
|
Evaluating internal representation of mux trees.
|
|
Analyzing evaluation results.
|
|
dead port 2/2 on $mux $procmux$1836.
|
|
dead port 2/2 on $mux $procmux$1842.
|
|
dead port 2/2 on $mux $procmux$1848.
|
|
dead port 2/2 on $mux $procmux$1854.
|
|
dead port 2/2 on $mux $procmux$1860.
|
|
dead port 2/2 on $mux $procmux$1866.
|
|
dead port 2/2 on $mux $procmux$1872.
|
|
Removed 7 multiplexer ports.
|
|
<suppressed ~100 debug messages>
|
|
|
|
2.34.33. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module $paramod$constmap:fdf1d1b176de14bfd33690c77b41951c8a2dab34$paramod$4e33147aa56d8c514f5e3e64af4e016a996d124e\_90_shift_shiftx.
|
|
<suppressed ~2 debug messages>
|
|
Removed 0 unused cells and 12 unused wires.
|
|
Using template $paramod$constmap:fdf1d1b176de14bfd33690c77b41951c8a2dab34$paramod$4e33147aa56d8c514f5e3e64af4e016a996d124e\_90_shift_shiftx for cells of type $shift.
|
|
Using template $paramod$constmap:d6fff7a1d5912e7277ff55b9a478b5115760128b$paramod$64b19f47ed5f126636dbd98d727ec46a7ec08d71\_90_shift_shiftx for cells of type $shift.
|
|
Using extmapper simplemap for cells of type $pmux.
|
|
Using extmapper simplemap for cells of type $xor.
|
|
Using template $paramod\_90_fa\WIDTH=32'00000000000000000000000000000011 for cells of type $fa.
|
|
Using template $paramod\_90_lcu_brent_kung\WIDTH=32'00000000000000000000000000000011 for cells of type $lcu.
|
|
Using extmapper simplemap for cells of type $pos.
|
|
Using extmapper simplemap for cells of type $logic_or.
|
|
Using template $paramod\_90_fa\WIDTH=32'00000000000000000000000000000100 for cells of type $fa.
|
|
Using template $paramod\_90_lcu_brent_kung\WIDTH=32'00000000000000000000000000000100 for cells of type $lcu.
|
|
No more expansions possible.
|
|
<suppressed ~762 debug messages>
|
|
|
|
2.35. Executing OPT pass (performing simple optimizations).
|
|
|
|
2.35.1. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module neural_director.
|
|
<suppressed ~8775 debug messages>
|
|
|
|
2.35.2. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\neural_director'.
|
|
Computing hashes of 4808 cells of `\neural_director'.
|
|
Finding duplicate cells in `\neural_director'.
|
|
Computing hashes of 4725 cells of `\neural_director'.
|
|
Finding duplicate cells in `\neural_director'.
|
|
Computing hashes of 4673 cells of `\neural_director'.
|
|
Finding duplicate cells in `\neural_director'.
|
|
Computing hashes of 4625 cells of `\neural_director'.
|
|
Finding duplicate cells in `\neural_director'.
|
|
Computing hashes of 4585 cells of `\neural_director'.
|
|
Finding duplicate cells in `\neural_director'.
|
|
Computing hashes of 4561 cells of `\neural_director'.
|
|
Finding duplicate cells in `\neural_director'.
|
|
Computing hashes of 4560 cells of `\neural_director'.
|
|
Finding duplicate cells in `\neural_director'.
|
|
Computing hashes of 4559 cells of `\neural_director'.
|
|
Finding duplicate cells in `\neural_director'.
|
|
Computing hashes of 4558 cells of `\neural_director'.
|
|
Finding duplicate cells in `\neural_director'.
|
|
Computing hashes of 4557 cells of `\neural_director'.
|
|
Finding duplicate cells in `\neural_director'.
|
|
Computing hashes of 4556 cells of `\neural_director'.
|
|
Finding duplicate cells in `\neural_director'.
|
|
Computing hashes of 4555 cells of `\neural_director'.
|
|
Finding duplicate cells in `\neural_director'.
|
|
Computing hashes of 4554 cells of `\neural_director'.
|
|
Finding duplicate cells in `\neural_director'.
|
|
Computing hashes of 4553 cells of `\neural_director'.
|
|
Finding duplicate cells in `\neural_director'.
|
|
Computing hashes of 4552 cells of `\neural_director'.
|
|
Finding duplicate cells in `\neural_director'.
|
|
Computing hashes of 4551 cells of `\neural_director'.
|
|
Finding duplicate cells in `\neural_director'.
|
|
Computing hashes of 4550 cells of `\neural_director'.
|
|
Finding duplicate cells in `\neural_director'.
|
|
Computing hashes of 4549 cells of `\neural_director'.
|
|
Finding duplicate cells in `\neural_director'.
|
|
Computing hashes of 4548 cells of `\neural_director'.
|
|
Finding duplicate cells in `\neural_director'.
|
|
Computing hashes of 4547 cells of `\neural_director'.
|
|
Finding duplicate cells in `\neural_director'.
|
|
Computing hashes of 4546 cells of `\neural_director'.
|
|
Finding duplicate cells in `\neural_director'.
|
|
Computing hashes of 4545 cells of `\neural_director'.
|
|
Finding duplicate cells in `\neural_director'.
|
|
Computing hashes of 4544 cells of `\neural_director'.
|
|
Finding duplicate cells in `\neural_director'.
|
|
Computing hashes of 4543 cells of `\neural_director'.
|
|
Finding duplicate cells in `\neural_director'.
|
|
Computing hashes of 4542 cells of `\neural_director'.
|
|
Finding duplicate cells in `\neural_director'.
|
|
Computing hashes of 4541 cells of `\neural_director'.
|
|
Finding duplicate cells in `\neural_director'.
|
|
<suppressed ~801 debug messages>
|
|
Removed a total of 267 cells.
|
|
|
|
2.35.3. Executing OPT_DFF pass (perform DFF optimizations).
|
|
|
|
2.35.4. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \neural_director..
|
|
Removed 553 unused cells and 557 unused wires.
|
|
<suppressed ~556 debug messages>
|
|
|
|
2.35.5. Finished fast OPT passes.
|
|
|
|
2.36. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \neural_director..
|
|
|
|
2.37. Executing DFFLEGALIZE pass (convert FFs to types supported by the target).
|
|
|
|
2.38. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\neural_director'.
|
|
Computing hashes of 3988 cells of `\neural_director'.
|
|
Finding duplicate cells in `\neural_director'.
|
|
Removed a total of 0 cells.
|
|
|
|
2.39. Executing TECHMAP pass (map to technology primitives).
|
|
|
|
2.39.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v
|
|
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v' to AST representation.
|
|
Generating RTLIL representation for module `$_DFF_N_'.
|
|
Generating RTLIL representation for module `$_DFF_P_'.
|
|
Generating RTLIL representation for module `$_DFFE_NN_'.
|
|
Generating RTLIL representation for module `$_DFFE_PN_'.
|
|
Generating RTLIL representation for module `$_DFFE_NP_'.
|
|
Generating RTLIL representation for module `$_DFFE_PP_'.
|
|
Generating RTLIL representation for module `$_DFF_NP0_'.
|
|
Generating RTLIL representation for module `$_DFF_NP1_'.
|
|
Generating RTLIL representation for module `$_DFF_PP0_'.
|
|
Generating RTLIL representation for module `$_DFF_PP1_'.
|
|
Generating RTLIL representation for module `$_SDFF_NP0_'.
|
|
Generating RTLIL representation for module `$_SDFF_NP1_'.
|
|
Generating RTLIL representation for module `$_SDFF_PP0_'.
|
|
Generating RTLIL representation for module `$_SDFF_PP1_'.
|
|
Generating RTLIL representation for module `$_DFFE_NP0P_'.
|
|
Generating RTLIL representation for module `$_DFFE_NP1P_'.
|
|
Generating RTLIL representation for module `$_DFFE_PP0P_'.
|
|
Generating RTLIL representation for module `$_DFFE_PP1P_'.
|
|
Generating RTLIL representation for module `$_DFFE_NP0N_'.
|
|
Generating RTLIL representation for module `$_DFFE_NP1N_'.
|
|
Generating RTLIL representation for module `$_DFFE_PP0N_'.
|
|
Generating RTLIL representation for module `$_DFFE_PP1N_'.
|
|
Generating RTLIL representation for module `$_SDFFE_NP0P_'.
|
|
Generating RTLIL representation for module `$_SDFFE_NP1P_'.
|
|
Generating RTLIL representation for module `$_SDFFE_PP0P_'.
|
|
Generating RTLIL representation for module `$_SDFFE_PP1P_'.
|
|
Generating RTLIL representation for module `$_SDFFE_NP0N_'.
|
|
Generating RTLIL representation for module `$_SDFFE_NP1N_'.
|
|
Generating RTLIL representation for module `$_SDFFE_PP0N_'.
|
|
Generating RTLIL representation for module `$_SDFFE_PP1N_'.
|
|
Generating RTLIL representation for module `$_ALDFF_NP_'.
|
|
Generating RTLIL representation for module `$_ALDFF_PP_'.
|
|
Generating RTLIL representation for module `$_ALDFFE_NPN_'.
|
|
Generating RTLIL representation for module `$_ALDFFE_NPP_'.
|
|
Generating RTLIL representation for module `$_ALDFFE_PPN_'.
|
|
Generating RTLIL representation for module `$_ALDFFE_PPP_'.
|
|
Generating RTLIL representation for module `\FD1P3AX'.
|
|
Generating RTLIL representation for module `\FD1P3AY'.
|
|
Generating RTLIL representation for module `\FD1P3BX'.
|
|
Generating RTLIL representation for module `\FD1P3DX'.
|
|
Generating RTLIL representation for module `\FD1P3IX'.
|
|
Generating RTLIL representation for module `\FD1P3JX'.
|
|
Generating RTLIL representation for module `\FD1S3AX'.
|
|
Generating RTLIL representation for module `\FD1S3AY'.
|
|
Generating RTLIL representation for module `\FD1S3BX'.
|
|
Generating RTLIL representation for module `\FD1S3DX'.
|
|
Generating RTLIL representation for module `\FD1S3IX'.
|
|
Generating RTLIL representation for module `\FD1S3JX'.
|
|
Generating RTLIL representation for module `\IFS1P3BX'.
|
|
Generating RTLIL representation for module `\IFS1P3DX'.
|
|
Generating RTLIL representation for module `\IFS1P3IX'.
|
|
Generating RTLIL representation for module `\IFS1P3JX'.
|
|
Generating RTLIL representation for module `\OFS1P3BX'.
|
|
Generating RTLIL representation for module `\OFS1P3DX'.
|
|
Generating RTLIL representation for module `\OFS1P3IX'.
|
|
Generating RTLIL representation for module `\OFS1P3JX'.
|
|
Generating RTLIL representation for module `\IB'.
|
|
Generating RTLIL representation for module `\IBPU'.
|
|
Generating RTLIL representation for module `\IBPD'.
|
|
Generating RTLIL representation for module `\OB'.
|
|
Generating RTLIL representation for module `\OBZ'.
|
|
Generating RTLIL representation for module `\OBZPU'.
|
|
Generating RTLIL representation for module `\OBZPD'.
|
|
Generating RTLIL representation for module `\OBCO'.
|
|
Generating RTLIL representation for module `\BB'.
|
|
Generating RTLIL representation for module `\BBPU'.
|
|
Generating RTLIL representation for module `\BBPD'.
|
|
Generating RTLIL representation for module `\ILVDS'.
|
|
Generating RTLIL representation for module `\OLVDS'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
2.39.2. Continuing TECHMAP pass.
|
|
Using template $_SDFFE_PP0P_ for cells of type $_SDFFE_PP0P_.
|
|
Using template $_SDFF_PP0_ for cells of type $_SDFF_PP0_.
|
|
No more expansions possible.
|
|
<suppressed ~437 debug messages>
|
|
|
|
2.40. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module neural_director.
|
|
<suppressed ~13 debug messages>
|
|
|
|
2.41. Executing SIMPLEMAP pass (map simple cells to gate primitives).
|
|
|
|
2.42. Executing LATTICE_GSR pass (implement FF init values).
|
|
Handling GSR in neural_director.
|
|
|
|
2.43. Executing ATTRMVCP pass (move or copy attributes).
|
|
|
|
2.44. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \neural_director..
|
|
Removed 0 unused cells and 2185 unused wires.
|
|
<suppressed ~1 debug messages>
|
|
|
|
2.45. Executing CHECK pass (checking for obvious problems).
|
|
Checking module neural_director...
|
|
Found and reported 0 problems.
|
|
|
|
2.46. Executing TECHMAP pass (map to technology primitives).
|
|
|
|
2.46.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/latches_map.v
|
|
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/latches_map.v' to AST representation.
|
|
Generating RTLIL representation for module `$_DLATCH_N_'.
|
|
Generating RTLIL representation for module `$_DLATCH_P_'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
2.46.2. Continuing TECHMAP pass.
|
|
No more expansions possible.
|
|
<suppressed ~4 debug messages>
|
|
|
|
2.47. Executing ABC9 pass.
|
|
|
|
2.47.1. Executing ABC9_OPS pass (helper functions for ABC9).
|
|
|
|
2.47.2. Executing ABC9_OPS pass (helper functions for ABC9).
|
|
|
|
2.47.3. Executing PROC pass (convert processes to netlists).
|
|
|
|
2.47.3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
|
|
Found and cleaned up 1 empty switch in `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:151$15730'.
|
|
Cleaned up 1 empty switch.
|
|
|
|
2.47.3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
|
|
Marked 1 switch rules as full_case in process $proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:159$15731 in module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.
|
|
Removed a total of 0 dead cases.
|
|
|
|
2.47.3.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
|
|
Removed 0 redundant assignments.
|
|
Promoted 22 assignments to connections.
|
|
|
|
2.47.3.4. Executing PROC_INIT pass (extract init attributes).
|
|
|
|
2.47.3.5. Executing PROC_ARST pass (detect async resets in processes).
|
|
|
|
2.47.3.6. Executing PROC_ROM pass (convert switches to ROMs).
|
|
Converted 0 switches.
|
|
<suppressed ~1 debug messages>
|
|
|
|
2.47.3.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
|
|
Creating decoders for process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$15755'.
|
|
Creating decoders for process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:159$15731'.
|
|
1/3: $1$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:161$15729_EN[3:0]$15737
|
|
2/3: $1$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:161$15729_DATA[3:0]$15736
|
|
3/3: $1$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:161$15729_ADDR[3:0]$15735
|
|
Creating decoders for process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:151$15730'.
|
|
|
|
2.47.3.8. Executing PROC_DLATCH pass (convert process syncs to latches).
|
|
No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.\i' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$15755'.
|
|
No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:145$15713_EN' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$15755'.
|
|
No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:145$15714_EN' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$15755'.
|
|
No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:145$15715_EN' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$15755'.
|
|
No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:145$15716_EN' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$15755'.
|
|
No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:145$15717_EN' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$15755'.
|
|
No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:145$15718_EN' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$15755'.
|
|
No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:145$15719_EN' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$15755'.
|
|
No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:145$15720_EN' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$15755'.
|
|
No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:145$15721_EN' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$15755'.
|
|
No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:145$15722_EN' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$15755'.
|
|
No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:145$15723_EN' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$15755'.
|
|
No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:145$15724_EN' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$15755'.
|
|
No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:145$15725_EN' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$15755'.
|
|
No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:145$15726_EN' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$15755'.
|
|
No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:145$15727_EN' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$15755'.
|
|
No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:145$15728_EN' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$15755'.
|
|
No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.\muxwre' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:151$15730'.
|
|
|
|
2.47.3.9. Executing PROC_DFF pass (convert process syncs to FFs).
|
|
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:161$15729_ADDR' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:159$15731'.
|
|
created $dff cell `$procdff$15781' with positive edge clock.
|
|
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:161$15729_DATA' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:159$15731'.
|
|
created $dff cell `$procdff$15782' with positive edge clock.
|
|
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:161$15729_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:159$15731'.
|
|
created $dff cell `$procdff$15783' with positive edge clock.
|
|
|
|
2.47.3.10. Executing PROC_MEMWR pass (convert process memory writes to cells).
|
|
|
|
2.47.3.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
|
|
Removing empty process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$15755'.
|
|
Found and cleaned up 1 empty switch in `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:159$15731'.
|
|
Removing empty process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:159$15731'.
|
|
Removing empty process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:151$15730'.
|
|
Cleaned up 1 empty switch.
|
|
|
|
2.47.4. Executing SCC pass (detecting logic loops).
|
|
Found 0 SCCs in module neural_director.
|
|
Found 0 SCCs.
|
|
|
|
2.47.5. Executing ABC9_OPS pass (helper functions for ABC9).
|
|
|
|
2.47.6. Executing TECHMAP pass (map to technology primitives).
|
|
|
|
2.47.6.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/techmap.v
|
|
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/techmap.v' to AST representation.
|
|
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
|
|
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
|
|
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
|
|
Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
|
|
Generating RTLIL representation for module `\_90_simplemap_various'.
|
|
Generating RTLIL representation for module `\_90_simplemap_registers'.
|
|
Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
|
|
Generating RTLIL representation for module `\_90_shift_shiftx'.
|
|
Generating RTLIL representation for module `\_90_fa'.
|
|
Generating RTLIL representation for module `\_90_lcu_brent_kung'.
|
|
Generating RTLIL representation for module `\_90_alu'.
|
|
Generating RTLIL representation for module `\_90_macc'.
|
|
Generating RTLIL representation for module `\_90_alumacc'.
|
|
Generating RTLIL representation for module `$__div_mod_u'.
|
|
Generating RTLIL representation for module `$__div_mod_trunc'.
|
|
Generating RTLIL representation for module `\_90_div'.
|
|
Generating RTLIL representation for module `\_90_mod'.
|
|
Generating RTLIL representation for module `$__div_mod_floor'.
|
|
Generating RTLIL representation for module `\_90_divfloor'.
|
|
Generating RTLIL representation for module `\_90_modfloor'.
|
|
Generating RTLIL representation for module `\_90_pow'.
|
|
Generating RTLIL representation for module `\_90_demux'.
|
|
Generating RTLIL representation for module `\_90_lut'.
|
|
Generating RTLIL representation for module `$connect'.
|
|
Generating RTLIL representation for module `$input_port'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
2.47.6.2. Continuing TECHMAP pass.
|
|
No more expansions possible.
|
|
<suppressed ~168 debug messages>
|
|
|
|
2.47.7. Executing OPT pass (performing simple optimizations).
|
|
|
|
2.47.7.1. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.
|
|
|
|
2.47.7.2. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4'.
|
|
Computing hashes of 2 cells of `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4'.
|
|
Finding duplicate cells in `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4'.
|
|
Removed a total of 0 cells.
|
|
|
|
2.47.7.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4..
|
|
Creating internal representation of mux trees.
|
|
No muxes found in this module.
|
|
Removed 0 multiplexer ports.
|
|
|
|
2.47.7.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.
|
|
Performed a total of 0 changes.
|
|
|
|
2.47.7.5. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4'.
|
|
Computing hashes of 2 cells of `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4'.
|
|
Finding duplicate cells in `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4'.
|
|
Removed a total of 0 cells.
|
|
|
|
2.47.7.6. Executing OPT_DFF pass (perform DFF optimizations).
|
|
|
|
2.47.7.7. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4..
|
|
|
|
2.47.7.8. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.
|
|
|
|
2.47.7.9. Finished fast OPT passes. (There is nothing left to do.)
|
|
|
|
2.47.8. Executing TECHMAP pass (map to technology primitives).
|
|
|
|
2.47.8.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/abc9_map.v
|
|
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/abc9_map.v' to AST representation.
|
|
Successfully finished Verilog frontend.
|
|
|
|
2.47.8.2. Continuing TECHMAP pass.
|
|
Using template $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4 for cells of type $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.
|
|
No more expansions possible.
|
|
<suppressed ~25 debug messages>
|
|
|
|
2.47.9. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/abc9_model.v
|
|
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/abc9_model.v' to AST representation.
|
|
Generating RTLIL representation for module `$__ABC9_DELAY'.
|
|
Generating RTLIL representation for module `$__ABC9_SCC_BREAKER'.
|
|
Generating RTLIL representation for module `$__DFF_N__$abc9_flop'.
|
|
Generating RTLIL representation for module `$__DFF_P__$abc9_flop'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
2.47.10. Executing ABC9_OPS pass (helper functions for ABC9).
|
|
<suppressed ~2 debug messages>
|
|
|
|
2.47.11. Executing ABC9_OPS pass (helper functions for ABC9).
|
|
|
|
2.47.12. Executing ABC9_OPS pass (helper functions for ABC9).
|
|
<suppressed ~2 debug messages>
|
|
|
|
2.47.13. Executing TECHMAP pass (map to technology primitives).
|
|
|
|
2.47.13.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/techmap.v
|
|
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/techmap.v' to AST representation.
|
|
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
|
|
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
|
|
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
|
|
Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
|
|
Generating RTLIL representation for module `\_90_simplemap_various'.
|
|
Generating RTLIL representation for module `\_90_simplemap_registers'.
|
|
Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
|
|
Generating RTLIL representation for module `\_90_shift_shiftx'.
|
|
Generating RTLIL representation for module `\_90_fa'.
|
|
Generating RTLIL representation for module `\_90_lcu_brent_kung'.
|
|
Generating RTLIL representation for module `\_90_alu'.
|
|
Generating RTLIL representation for module `\_90_macc'.
|
|
Generating RTLIL representation for module `\_90_alumacc'.
|
|
Generating RTLIL representation for module `$__div_mod_u'.
|
|
Generating RTLIL representation for module `$__div_mod_trunc'.
|
|
Generating RTLIL representation for module `\_90_div'.
|
|
Generating RTLIL representation for module `\_90_mod'.
|
|
Generating RTLIL representation for module `$__div_mod_floor'.
|
|
Generating RTLIL representation for module `\_90_divfloor'.
|
|
Generating RTLIL representation for module `\_90_modfloor'.
|
|
Generating RTLIL representation for module `\_90_pow'.
|
|
Generating RTLIL representation for module `\_90_demux'.
|
|
Generating RTLIL representation for module `\_90_lut'.
|
|
Generating RTLIL representation for module `$connect'.
|
|
Generating RTLIL representation for module `$input_port'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
2.47.13.2. Continuing TECHMAP pass.
|
|
Using template $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C for cells of type $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C.
|
|
Using extmapper simplemap for cells of type $or.
|
|
Using extmapper simplemap for cells of type $and.
|
|
Using extmapper simplemap for cells of type $not.
|
|
Using extmapper simplemap for cells of type $xor.
|
|
Using template $paramod\LUT2\INIT=4'1010 for cells of type LUT2.
|
|
Using template $paramod\LUT4\INIT=16'1001011010101010 for cells of type LUT4.
|
|
Using extmapper simplemap for cells of type $mux.
|
|
No more expansions possible.
|
|
<suppressed ~207 debug messages>
|
|
|
|
2.47.14. Executing OPT pass (performing simple optimizations).
|
|
|
|
2.47.14.1. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module neural_director.
|
|
<suppressed ~18 debug messages>
|
|
|
|
2.47.14.2. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\neural_director'.
|
|
Computing hashes of 59 cells of `\neural_director'.
|
|
Finding duplicate cells in `\neural_director'.
|
|
Computing hashes of 57 cells of `\neural_director'.
|
|
Finding duplicate cells in `\neural_director'.
|
|
<suppressed ~6 debug messages>
|
|
Removed a total of 2 cells.
|
|
|
|
2.47.14.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \neural_director..
|
|
Creating internal representation of mux trees.
|
|
No muxes found in this module.
|
|
Removed 0 multiplexer ports.
|
|
|
|
2.47.14.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \neural_director.
|
|
Performed a total of 0 changes.
|
|
|
|
2.47.14.5. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\neural_director'.
|
|
Computing hashes of 57 cells of `\neural_director'.
|
|
Finding duplicate cells in `\neural_director'.
|
|
Removed a total of 0 cells.
|
|
|
|
2.47.14.6. Executing OPT_DFF pass (perform DFF optimizations).
|
|
|
|
2.47.14.7. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \neural_director..
|
|
Removed 0 unused cells and 55 unused wires.
|
|
<suppressed ~1 debug messages>
|
|
|
|
2.47.14.8. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module neural_director.
|
|
|
|
2.47.14.9. Rerunning OPT passes. (Maybe there is more to do..)
|
|
|
|
2.47.14.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \neural_director..
|
|
Creating internal representation of mux trees.
|
|
No muxes found in this module.
|
|
Removed 0 multiplexer ports.
|
|
|
|
2.47.14.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \neural_director.
|
|
Performed a total of 0 changes.
|
|
|
|
2.47.14.12. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\neural_director'.
|
|
Computing hashes of 57 cells of `\neural_director'.
|
|
Finding duplicate cells in `\neural_director'.
|
|
Removed a total of 0 cells.
|
|
|
|
2.47.14.13. Executing OPT_DFF pass (perform DFF optimizations).
|
|
|
|
2.47.14.14. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \neural_director..
|
|
|
|
2.47.14.15. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module neural_director.
|
|
|
|
2.47.14.16. Finished fast OPT passes. (There is nothing left to do.)
|
|
|
|
2.47.15. Executing AIGMAP pass (map logic to AIG).
|
|
Module neural_director: replaced 18 cells with 120 new cells, skipped 39 cells.
|
|
replaced 3 cell types:
|
|
14 $_MUX_
|
|
2 $_OR_
|
|
2 $_XOR_
|
|
not replaced 3 cell types:
|
|
4 $_AND_
|
|
4 $_NOT_
|
|
31 $specify2
|
|
|
|
2.47.16. Executing AIGMAP pass (map logic to AIG).
|
|
Module neural_director: replaced 3014 cells with 19910 new cells, skipped 983 cells.
|
|
replaced 3 cell types:
|
|
2582 $_MUX_
|
|
396 $_OR_
|
|
36 $_XOR_
|
|
not replaced 6 cell types:
|
|
360 $_AND_
|
|
192 $_NOT_
|
|
366 TRELLIS_FF
|
|
21 $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C
|
|
22 $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4
|
|
22 $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4_$abc9_byp
|
|
|
|
2.47.16.1. Executing ABC9_OPS pass (helper functions for ABC9).
|
|
|
|
2.47.16.2. Executing ABC9_OPS pass (helper functions for ABC9).
|
|
|
|
2.47.16.3. Executing XAIGER backend.
|
|
<suppressed ~11 debug messages>
|
|
Extracted 8610 AND gates and 21546 wires from module `neural_director' to a netlist network with 562 inputs and 731 outputs.
|
|
|
|
2.47.16.4. Executing ABC9_EXE pass (technology mapping using ABC9).
|
|
|
|
2.47.16.5. Executing ABC9.
|
|
Running ABC command: "<yosys-exe-dir>/yosys-abc" -s -f <abc-temp-dir>/abc.script 2>&1
|
|
ABC: ======== ABC command line "source <abc-temp-dir>/abc.script"
|
|
ABC: + read_lut <abc-temp-dir>/input.lut
|
|
ABC: + read_box <abc-temp-dir>/input.box
|
|
ABC: + &read <abc-temp-dir>/input.xaig
|
|
ABC: + &ps
|
|
ABC: <abc-temp-dir>/input : i/o = 562/ 731 and = 5580 lev = 41 (6.22) mem = 0.09 MB box = 43 bb = 22
|
|
ABC: + &scorr
|
|
ABC: Warning: The network is combinational.
|
|
ABC: + &sweep
|
|
ABC: + &dc2
|
|
ABC: + &dch -f -r
|
|
ABC: + &ps
|
|
ABC: <abc-temp-dir>/input : i/o = 562/ 731 and = 1730 lev = 11 (1.93) mem = 0.05 MB ch = 181 box = 26 bb = 22
|
|
ABC: cst = 0 cls = 180 lit = 181 unused = 2031 proof = 0
|
|
ABC: + &if -W 300 -v
|
|
ABC: K = 7. Memory (bytes): Truth = 0. Cut = 76. Obj = 156. Set = 780. CutMin = no
|
|
ABC: Node = 1730. Ch = 180. Total mem = 0.55 MB. Peak cut mem = 0.07 MB.
|
|
ABC: P: Del = 1991.00. Ar = 751.0. Edge = 2007. Cut = 18688. T = 0.00 sec
|
|
ABC: P: Del = 1991.00. Ar = 749.0. Edge = 2005. Cut = 18688. T = 0.00 sec
|
|
ABC: P: Del = 1991.00. Ar = 637.0. Edge = 1735. Cut = 21114. T = 0.00 sec
|
|
ABC: F: Del = 1991.00. Ar = 634.0. Edge = 1728. Cut = 10809. T = 0.00 sec
|
|
ABC: A: Del = 1991.00. Ar = 634.0. Edge = 1723. Cut = 10810. T = 0.00 sec
|
|
ABC: A: Del = 1991.00. Ar = 634.0. Edge = 1723. Cut = 10810. T = 0.00 sec
|
|
ABC: Total time = 0.01 sec
|
|
ABC: + &write -n <abc-temp-dir>/output.aig
|
|
ABC: + &mfs
|
|
ABC: + &ps -l
|
|
ABC: <abc-temp-dir>/input : i/o = 562/ 731 and = 1663 lev = 10 (1.92) mem = 0.04 MB box = 26 bb = 22
|
|
ABC: Mapping (K=6) : lut = 373 edge = 1382 lev = 3 (0.69) levB = 5 mem = 0.02 MB
|
|
ABC: LUT = 373 : 2=12 3.2 % 3=90 24.1 % 4=268 71.8 % 5=2 0.5 % 6=1 0.3 % Ave = 3.71
|
|
ABC: + &write -n <abc-temp-dir>/output.aig
|
|
ABC: + &verify
|
|
ABC: Networks are equivalent. Time = 0.02 sec
|
|
ABC: + time
|
|
ABC: elapse: 0.08 seconds, total: 0.08 seconds
|
|
|
|
2.47.16.6. Executing AIGER frontend.
|
|
<suppressed ~10 debug messages>
|
|
Removed 2657 unused cells and 3904 unused wires.
|
|
|
|
2.47.16.7. Executing ABC_OPS_REINTEGRATE pass (reintegrate ABC mapped design into module).
|
|
ABC RESULTS: $lut cells: 377
|
|
ABC RESULTS: $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C cells: 4
|
|
ABC RESULTS: $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4_$abc9_byp cells: 22
|
|
ABC RESULTS: input signals: 34
|
|
ABC RESULTS: output signals: 32
|
|
<suppressed ~2603 debug messages>
|
|
Removing temp directory.
|
|
|
|
2.47.17. Executing TECHMAP pass (map to technology primitives).
|
|
|
|
2.47.17.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/abc9_unmap.v
|
|
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/abc9_unmap.v' to AST representation.
|
|
Generating RTLIL representation for module `$__DFF_x__$abc9_flop'.
|
|
Generating RTLIL representation for module `$__ABC9_SCC_BREAKER'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
2.47.17.2. Continuing TECHMAP pass.
|
|
Using template $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4 for cells of type $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.
|
|
Using template $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C for cells of type $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C.
|
|
Using template $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4_$abc9_byp.
|
|
No more expansions possible.
|
|
<suppressed ~56 debug messages>
|
|
Removed 100 unused cells and 22029 unused wires.
|
|
|
|
2.48. Executing TECHMAP pass (map to technology primitives).
|
|
|
|
2.48.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v
|
|
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v' to AST representation.
|
|
Generating RTLIL representation for module `$_DFF_N_'.
|
|
Generating RTLIL representation for module `$_DFF_P_'.
|
|
Generating RTLIL representation for module `$_DFFE_NN_'.
|
|
Generating RTLIL representation for module `$_DFFE_PN_'.
|
|
Generating RTLIL representation for module `$_DFFE_NP_'.
|
|
Generating RTLIL representation for module `$_DFFE_PP_'.
|
|
Generating RTLIL representation for module `$_DFF_NP0_'.
|
|
Generating RTLIL representation for module `$_DFF_NP1_'.
|
|
Generating RTLIL representation for module `$_DFF_PP0_'.
|
|
Generating RTLIL representation for module `$_DFF_PP1_'.
|
|
Generating RTLIL representation for module `$_SDFF_NP0_'.
|
|
Generating RTLIL representation for module `$_SDFF_NP1_'.
|
|
Generating RTLIL representation for module `$_SDFF_PP0_'.
|
|
Generating RTLIL representation for module `$_SDFF_PP1_'.
|
|
Generating RTLIL representation for module `$_DFFE_NP0P_'.
|
|
Generating RTLIL representation for module `$_DFFE_NP1P_'.
|
|
Generating RTLIL representation for module `$_DFFE_PP0P_'.
|
|
Generating RTLIL representation for module `$_DFFE_PP1P_'.
|
|
Generating RTLIL representation for module `$_DFFE_NP0N_'.
|
|
Generating RTLIL representation for module `$_DFFE_NP1N_'.
|
|
Generating RTLIL representation for module `$_DFFE_PP0N_'.
|
|
Generating RTLIL representation for module `$_DFFE_PP1N_'.
|
|
Generating RTLIL representation for module `$_SDFFE_NP0P_'.
|
|
Generating RTLIL representation for module `$_SDFFE_NP1P_'.
|
|
Generating RTLIL representation for module `$_SDFFE_PP0P_'.
|
|
Generating RTLIL representation for module `$_SDFFE_PP1P_'.
|
|
Generating RTLIL representation for module `$_SDFFE_NP0N_'.
|
|
Generating RTLIL representation for module `$_SDFFE_NP1N_'.
|
|
Generating RTLIL representation for module `$_SDFFE_PP0N_'.
|
|
Generating RTLIL representation for module `$_SDFFE_PP1N_'.
|
|
Generating RTLIL representation for module `$_ALDFF_NP_'.
|
|
Generating RTLIL representation for module `$_ALDFF_PP_'.
|
|
Generating RTLIL representation for module `$_ALDFFE_NPN_'.
|
|
Generating RTLIL representation for module `$_ALDFFE_NPP_'.
|
|
Generating RTLIL representation for module `$_ALDFFE_PPN_'.
|
|
Generating RTLIL representation for module `$_ALDFFE_PPP_'.
|
|
Generating RTLIL representation for module `\FD1P3AX'.
|
|
Generating RTLIL representation for module `\FD1P3AY'.
|
|
Generating RTLIL representation for module `\FD1P3BX'.
|
|
Generating RTLIL representation for module `\FD1P3DX'.
|
|
Generating RTLIL representation for module `\FD1P3IX'.
|
|
Generating RTLIL representation for module `\FD1P3JX'.
|
|
Generating RTLIL representation for module `\FD1S3AX'.
|
|
Generating RTLIL representation for module `\FD1S3AY'.
|
|
Generating RTLIL representation for module `\FD1S3BX'.
|
|
Generating RTLIL representation for module `\FD1S3DX'.
|
|
Generating RTLIL representation for module `\FD1S3IX'.
|
|
Generating RTLIL representation for module `\FD1S3JX'.
|
|
Generating RTLIL representation for module `\IFS1P3BX'.
|
|
Generating RTLIL representation for module `\IFS1P3DX'.
|
|
Generating RTLIL representation for module `\IFS1P3IX'.
|
|
Generating RTLIL representation for module `\IFS1P3JX'.
|
|
Generating RTLIL representation for module `\OFS1P3BX'.
|
|
Generating RTLIL representation for module `\OFS1P3DX'.
|
|
Generating RTLIL representation for module `\OFS1P3IX'.
|
|
Generating RTLIL representation for module `\OFS1P3JX'.
|
|
Generating RTLIL representation for module `\IB'.
|
|
Generating RTLIL representation for module `\IBPU'.
|
|
Generating RTLIL representation for module `\IBPD'.
|
|
Generating RTLIL representation for module `\OB'.
|
|
Generating RTLIL representation for module `\OBZ'.
|
|
Generating RTLIL representation for module `\OBZPU'.
|
|
Generating RTLIL representation for module `\OBZPD'.
|
|
Generating RTLIL representation for module `\OBCO'.
|
|
Generating RTLIL representation for module `\BB'.
|
|
Generating RTLIL representation for module `\BBPU'.
|
|
Generating RTLIL representation for module `\BBPD'.
|
|
Generating RTLIL representation for module `\ILVDS'.
|
|
Generating RTLIL representation for module `\OLVDS'.
|
|
Generating RTLIL representation for module `$lut'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
2.48.2. Continuing TECHMAP pass.
|
|
Using template $paramod$e5759512db67494ff77fbdfc66dff4006376568f$lut for cells of type $lut.
|
|
Using template $paramod$aff3a645bb9f572421a4f0f49cf8987ceb4bcdc5$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0010 for cells of type $lut.
|
|
Using template $paramod$d5841602ab17202e972b290147d14b63f75b0ad1$lut for cells of type $lut.
|
|
Using template $paramod$359fe4e746656bf9c72aecaff84fc7bdea9f55a5$lut for cells of type $lut.
|
|
Using template $paramod$849d013d096d73269ca4beb768f8e399745d37f2$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1011 for cells of type $lut.
|
|
Using template $paramod$571404c0889eaf57f492cb5e37f8acb5df5852f9$lut for cells of type $lut.
|
|
Using template $paramod$658b9ed803f0d3d335616d3858b53e0a2522f1e8$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000001 for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1101 for cells of type $lut.
|
|
Using template $paramod$351521e8b01efeb144a39a20c4d973eb0b1643fa$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0110 for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01101010 for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1000 for cells of type $lut.
|
|
Using template $paramod$2aa2400b636d1f2542340d9a48d35a61ec4f2ceb$lut for cells of type $lut.
|
|
Using template $paramod$00e6eb1056d6deeea8a8d38a65ef2ad861705f32$lut for cells of type $lut.
|
|
Using template $paramod$6d6beead1425af15cf78b27fd9b11b41b5d4bce8$lut for cells of type $lut.
|
|
Using template $paramod$cc08dba3aac8677e797984bdf18a09dd37547dd3$lut for cells of type $lut.
|
|
Using template $paramod$2b82ba3dc458afbd78c9b79c233a51eb64b085d6$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11001010 for cells of type $lut.
|
|
Using template $paramod$fccccf8bb2add7667329c686feec7546eb9a3ae3$lut for cells of type $lut.
|
|
Using template $paramod$d6fad69df4b6793100fda03bb83504fe9b335c70$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0100 for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11100010 for cells of type $lut.
|
|
Using template $paramod$cd6c4b4da6d8737b72fd2dc8f5d83d8967445809$lut for cells of type $lut.
|
|
Using template $paramod$f70269f202d4dce0365aebaed07094a4216142a8$lut for cells of type $lut.
|
|
Using template $paramod$7aa8140c7d6de3160b21e7ff84e0f93f69f7fcc6$lut for cells of type $lut.
|
|
Using template $paramod$bba54c1ef87367812b4c15f4aed5ac70773df775$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000001\LUT=2'01 for cells of type $lut.
|
|
No more expansions possible.
|
|
<suppressed ~839 debug messages>
|
|
|
|
2.49. Executing OPT_LUT_INS pass (discard unused LUT inputs).
|
|
Optimizing LUTs in neural_director.
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$56074.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$56074.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$56076.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$56077.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Removed 0 unused cells and 756 unused wires.
|
|
|
|
2.50. Executing AUTONAME pass.
|
|
Renamed 890 objects in module neural_director.
|
|
<suppressed ~890 debug messages>
|
|
|
|
2.51. Executing HIERARCHY pass (managing design hierarchy).
|
|
Attribute `top' found on module `neural_director'. Setting top module to neural_director.
|
|
|
|
2.51.1. Analyzing design hierarchy..
|
|
Top module: \neural_director
|
|
|
|
2.51.2. Analyzing design hierarchy..
|
|
Top module: \neural_director
|
|
Removed 0 unused modules.
|
|
|
|
2.52. Printing statistics.
|
|
|
|
=== neural_director ===
|
|
|
|
+----------Local Count, excluding submodules.
|
|
|
|
|
159 wires
|
|
1318 wire bits
|
|
159 public wires
|
|
1318 public wire bits
|
|
19 ports
|
|
461 port bits
|
|
779 submodules
|
|
4 CCU2C
|
|
1 L6MUX21
|
|
382 LUT4
|
|
4 PFUMX
|
|
22 TRELLIS_DPR16X4
|
|
366 TRELLIS_FF
|
|
|
|
=== design hierarchy ===
|
|
|
|
+----------Count including submodules.
|
|
|
|
|
- neural_director
|
|
|
|
+----------Count including submodules.
|
|
|
|
|
159 wires
|
|
1318 wire bits
|
|
159 public wires
|
|
1318 public wire bits
|
|
19 ports
|
|
461 port bits
|
|
- memories
|
|
- memory bits
|
|
- processes
|
|
- cells
|
|
779 submodules
|
|
4 CCU2C
|
|
1 L6MUX21
|
|
382 LUT4
|
|
4 PFUMX
|
|
22 TRELLIS_DPR16X4
|
|
366 TRELLIS_FF
|
|
|
|
2.53. Executing CHECK pass (checking for obvious problems).
|
|
Checking module neural_director...
|
|
Found and reported 0 problems.
|
|
|
|
2.54. Executing JSON backend.
|
|
|
|
End of script. Logfile hash: b9afbe9818, time: 0.66s, user: 0.58s, system: 0.03s, MEM: 75.19 MB peak
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|
Yosys 0.68+post (git sha1 c12172fbae8af5e20f6fb52e3d4e92d56ed587b6, Release, AppleClang clang++ 21.0.0.21000101)
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|
Time spent: 25% 21x read_verilog (0 sec), 13% 1x abc9_exe (0 sec), ...
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