micheleandClaude Sonnet 5 1e36853072 docs: clear CAS#/WE# false alarm, resolve TLV73325 EN wiring ...

User confirmed the real schematic has SDRAM CAS#=F7/WE#=F9 -- matches
this chapter exactly. The earlier review's "appear swapped" finding
was a misread of the schematic image, not a real error; moved from
"real findings" to a cleared checked-item note.

TLV73325's EN pin resolved: direct wire to +3.3V (VIN), always-enabled
-- no soft-start timing requirement like TLV62568's own R3 pull-up (a
plain LDO, no sequencing note in TI's own datasheet), and no dynamic
enable/disable control exists elsewhere in this design.

Remaining real, open finding: the boot-flash net-name mismatch
(FGPA/FPGA typo + SCLK/CLK) still needs a schematic fix.

Compiled clean (47 pages, 0 errors).

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v

2026-09-07 19:38:48 +02:00

..

architecture

chore: remove root-level V1 duplicates, superseded by hardware/v1/ freeze

2026-09-07 05:30:17 +02:00

benchmarks

test(v2): final benchmark campaign - real end-to-end characterization (EXP-0014)

2026-09-05 19:58:30 +02:00

datasheet

docs: clear CAS#/WE# false alarm, resolve TLV73325 EN wiring

2026-09-07 19:38:48 +02:00

CHIP_READINESS.md

docs: PRE-PCB VERIFICATION FREEZE report + config flash freeze

2026-09-06 18:32:40 +02:00

CLOCK_ARCHITECTURE.md

docs: PRE-PCB VERIFICATION FREEZE report + config flash freeze

2026-09-06 18:32:40 +02:00

FIRST_POWER_ON.md

V2.0.0 hardware freeze - single SDRAM

2026-09-06 13:39:55 +02:00

FPGA_NEURAL_V2_DATASHEET.md

chore: remove root-level V1 duplicates, superseded by hardware/v1/ freeze

2026-09-07 05:30:17 +02:00

FPGA_NEURAL_V2_SCHEMATIC.md

chore: remove root-level V1 duplicates, superseded by hardware/v1/ freeze

2026-09-07 05:30:17 +02:00

FPGA-Neural-V2-Datasheet-EN.pdf

chore: remove root-level V1 duplicates, superseded by hardware/v1/ freeze

2026-09-07 05:30:17 +02:00

HARDWARE_FREEZE.md

docs: memory upgrade writeup (MEMORY_UPGRADE_64MB_N8.md) + supersede stale SDRAM docs

2026-09-07 00:21:05 +02:00

MEMORY_ARCHITECTURE.md

docs: memory upgrade writeup (MEMORY_UPGRADE_64MB_N8.md) + supersede stale SDRAM docs

2026-09-07 00:21:05 +02:00

MEMORY_UPGRADE_64MB_N8.md

fix: ERR-0029 sdram_unified_backend weight-cache hit-index critical path

2026-09-07 03:10:50 +02:00

OPEN_ITEMS.md

docs: PRE-PCB VERIFICATION FREEZE report + config flash freeze

2026-09-06 18:32:40 +02:00

PINOUT.md

docs: PRE-PCB VERIFICATION FREEZE report + config flash freeze

2026-09-06 18:32:40 +02:00

pinouts.md

docs: reflect flash #1 removal and the N=4 8/8 timing recovery

2026-09-07 19:20:57 +02:00

POWER_ARCHITECTURE.md

docs: PRE-PCB VERIFICATION FREEZE report + config flash freeze

2026-09-06 18:32:40 +02:00

PRE_PCB_CLOSURE_4POINT.md

docs: memory upgrade writeup (MEMORY_UPGRADE_64MB_N8.md) + supersede stale SDRAM docs

2026-09-07 00:21:05 +02:00

PRE_PCB_VERIFICATION.md

docs: memory upgrade writeup (MEMORY_UPGRADE_64MB_N8.md) + supersede stale SDRAM docs

2026-09-07 00:21:05 +02:00

ROADMAP.md

perf(v2): shared activation cache - further 1.66-2.00x real speedup (DEC-0016)

2026-09-05 20:59:14 +02:00

SCHEMATIC_READINESS.md

docs: PRE-PCB VERIFICATION FREEZE report + config flash freeze

2026-09-06 18:32:40 +02:00