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FPGA-Neural/hardware/v1/synthesis/p2/top.config
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micheleandClaude Sonnet 5 dc0b331d3e feat(v2): scaffold hardware/v1 frozen baseline + M1 Neural Processor 
Begins the V2 Neural Multiprocessor / Dataflow architecture per
docs/v2-description.md, per explicit user request to freeze V1 and
start V2 development, copying from V1 what's needed.

Scaffold:
- hardware/v1/: byte-exact, read-only copy of the current V1 codebase
  (rtl, testbenches, tools, constraints, a representative subset of
  synthesis results, and reference docs) -- verified identical via
  diff/cmp against the live top-level tree before being made
  filesystem-read-only. The live top-level tree is untouched and
  remains the project's "production" V1 (see hardware/v1/README.md
  and hardware/v2/logs/decisions.log DEC-0001 for why copy-not-move).
- hardware/v2/: mandatory structure (rtl/sim/constraints/synthesis/
  reports/scripts/logs/docs) plus the full logging system required by
  the spec (development/architecture/simulation/synthesis/timing/
  benchmark/decisions/experiments/errors.log).

M1 -- Neural Processor (hardware/v2/rtl/neural_processor.v):
- 8-stage pipelined perceptron unit (P_IN=8): input align, 8
  multipliers, 3-level adder tree, accumulator, bias+activation, INT8
  saturation. Genuine 1-tile/cycle throughput, not just a wider
  combinational datapath.
- 7-state FSM (NP_IDLE..NP_ERROR per docs/v2-description.md §6, with
  4 baseline states merged into NP_WAIT_OPERANDS -- see
  decisions.log DEC-0002); valid/ready/data/last stream interfaces
  per §7.
- Bit-exact vs the frozen hardware/v1/rtl/neuron_parallel.v + mac8.v
  + mac_unit.v: 7/7 tests pass (hardware/v2/sim/tb_neural_processor.v),
  covering regular/mixed-sign/extreme-INT8 vectors, both activations,
  a zero-idle-gap back-to-back-tiles throughput check, and an 8-tile
  job -- verified with Verilator (see below for why).
- Real synthesis + place&route (Yosys + nextpnr-ecp5): 0 CHECK
  problems, Fmax 183.12 MHz at ACC_WIDTH=32 (PASS at 80MHz, ~3x V1's
  isolated PARALLEL=8 Fmax of 61.71 MHz) and 176.21 MHz at ACC_WIDTH=24
  (a user-requested comparison experiment, also bit-exact-verified;
  see experiments.log EXP-0001/EXP-0002 and benchmark.log).

Three real bugs found and resolved during M1 development (full
diagnostic record in errors.log):
- Two independent, reproducible Icarus Verilog v13.0 scheduling
  defects (ERR-0001, ERR-0002) that silently produced wrong simulation
  results for standard sequential Verilog -- confirmed via Verilator
  5.050 giving correct results on the same minimal repros. Verilator
  is now the trusted simulator for hardware/v2/ (decisions.log
  DEC-0004); Icarus's affected protocol-violation check was removed
  from the RTL and deferred architecturally to the Neural Director
  (DEC-0003) rather than chased further.
- One real RTL bug (ERR-0003): last0 wasn't gated like valid0,
  letting a "last tile" tag leak into the pipeline ahead of its
  actual valid tile on back-to-back jobs. Fixed and verified.

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
2026-09-05 14:06:53 +02:00

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.device LFE5U-45F
.comment Part: LFE5U-45F-8CABGA381
.tile CIB_R10C18:CIB_EBR
arc: N3_V06N0103 S3_V06N0003
.tile CIB_R10C3:PVT_COUNT2
unknown: F2B0
unknown: F3B0
unknown: F5B0
unknown: F11B0
unknown: F13B0
.tile CIB_R10C49:CIB_EBR
arc: N3_V06N0303 S3_V06N0203
.tile CIB_R10C51:CIB_EBR
arc: N3_V06N0303 S3_V06N0303
.tile CIB_R13C1:CIB_LR
arc: E3_H06E0303 JQ5
.tile CIB_R19C1:CIB_LR
arc: S1_V02S0701 H06W0203
.tile CIB_R19C89:CIB_LR
arc: W3_H06W0303 JF5
.tile CIB_R1C18:CIB
arc: E1_H02E0701 V06N0203
arc: JA0 S1_V02N0701
enum: CIB.JB0MUX 0
.tile CIB_R1C19:CIB
arc: JA0 H02E0701
enum: CIB.JB0MUX 0
.tile CIB_R1C37:CIB
arc: E3_H06E0303 S3_V06N0303
.tile CIB_R1C38:CIB
arc: E1_H02E0501 V02N0501
arc: JA0 H02W0701
enum: CIB.JB0MUX 0
.tile CIB_R1C39:CIB
arc: JA0 H02E0501
arc: W1_H02W0701 S3_V06N0203
enum: CIB.JB0MUX 0
.tile CIB_R1C41:CIB
arc: E1_H02E0701 S1_V02N0701
.tile CIB_R1C43:CIB
arc: E3_H06E0303 W3_H06E0303
arc: JA0 W1_H02E0701
enum: CIB.JB0MUX 0
.tile CIB_R1C48:CIB
arc: JD7 E1_H01W0100
.tile CIB_R1C49:CIB
arc: H01W0100 W3_H06E0303
arc: JA0 V02N0701
enum: CIB.JB0MUX 0
.tile CIB_R1C51:CIB
arc: JA0 V02N0501
enum: CIB.JB0MUX 0
.tile CIB_R1C60:CIB
arc: JA0 S1_V02N0501
enum: CIB.JB0MUX 0
.tile CIB_R1C62:CIB
arc: JA0 H02W0701
enum: CIB.JB0MUX 0
.tile CIB_R1C63:CIB
arc: W1_H02W0701 S3_V06N0203
.tile CIB_R1C67:CIB
arc: E1_H02E0701 V02N0701
arc: H00L0000 V02N0001
arc: JA0 H00L0000
enum: CIB.JB0MUX 0
.tile CIB_R1C68:CIB
arc: JA0 H02E0701
enum: CIB.JB0MUX 0
.tile CIB_R1C74:CIB
arc: JA0 H02W0501
enum: CIB.JB0MUX 0
.tile CIB_R1C75:CIB
arc: H00L0100 S1_V02N0301
arc: JA0 H00L0100
arc: W1_H02W0501 S1_V02N0501
enum: CIB.JB0MUX 0
.tile CIB_R1C76:CIB
arc: JA0 S1_V02N0701
enum: CIB.JB0MUX 0
.tile CIB_R20C1:CIB_LR
arc: JA0 E1_H02W0701
arc: JA3 V02S0701
arc: S1_V02S0701 H06W0203
enum: CIB.JB3MUX 0
enum: CIB.JB0MUX 0
.tile CIB_R20C89:CIB_LR
arc: JA0 W1_H02E0501
arc: JA3 H02E0701
arc: S1_V02S0701 W1_H02E0701
enum: CIB.JB0MUX 0
enum: CIB.JB3MUX 0
.tile CIB_R21C1:CIB_LR
arc: S1_V02S0701 E3_H06W0203
.tile CIB_R21C89:CIB_LR
arc: S1_V02S0401 W1_H02E0401
arc: S1_V02S0701 H06E0203
.tile CIB_R22C17:CIB_DSP
arc: E1_H01E0101 JQ7
arc: E3_H06E0303 JQ6
arc: N1_V02N0401 JQ4
arc: N1_V02N0701 JQ5
.tile CIB_R22C18:CIB_DSP
arc: E1_H01E0001 JQ7
arc: E3_H06E0203 JQ4
arc: E3_H06E0303 JQ5
arc: N1_V01N0001 JQ3
arc: N1_V01N0101 JQ6
arc: N1_V02N0001 JQ0
arc: N1_V02N0201 JQ2
arc: N1_V02N0301 JQ1
arc: N1_V02N0501 H01E0101
enum: CIB.JC1MUX 0
enum: CIB.JA6MUX 0
enum: CIB.JC7MUX 0
enum: CIB.JA4MUX 0
enum: CIB.JC5MUX 0
enum: CIB.JA2MUX 0
enum: CIB.JC3MUX 0
enum: CIB.JA0MUX 0
.tile CIB_R22C19:CIB_DSP
arc: E3_H06E0003 JQ3
arc: N1_V01N0001 JQ0
arc: N1_V01N0101 JQ2
arc: N1_V02N0301 JQ1
arc: N1_V02N0601 H01E0001
enum: CIB.JC1MUX 0
enum: CIB.JA6MUX 0
enum: CIB.JC7MUX 0
enum: CIB.JA4MUX 0
enum: CIB.JC5MUX 0
enum: CIB.JB6MUX 0
enum: CIB.JD7MUX 0
enum: CIB.JB7MUX 0
enum: CIB.JD6MUX 1
.tile CIB_R22C1:CIB_LR_S
arc: JA0 E1_H02W0501
arc: JA3 N1_V02S0701
enum: CIB.JB3MUX 0
enum: CIB.JB0MUX 0
.tile CIB_R22C20:CIB_DSP
arc: JLSR1 H02W0301
arc: N1_V02N0101 E1_H02W0101
arc: N1_V02N0301 N1_V01S0100
arc: N1_V02N0501 H06E0303
arc: N1_V02N0701 H02W0701
enum: CIB.JB6MUX 0
enum: CIB.JD7MUX 0
enum: CIB.JB4MUX 0
enum: CIB.JD5MUX 0
enum: CIB.JB2MUX 0
enum: CIB.JD3MUX 0
enum: CIB.JB0MUX 0
enum: CIB.JD1MUX 0
enum: CIB.JB7MUX 0
enum: CIB.JD6MUX 0
enum: CIB.JB5MUX 0
enum: CIB.JD4MUX 0
enum: CIB.JB3MUX 0
enum: CIB.JD2MUX 0
enum: CIB.JB1MUX 0
enum: CIB.JD0MUX 0
.tile CIB_R22C21:CIB_DSP
arc: H00L0100 E1_H02W0301
arc: JCE3 H00L0100
arc: JLSR0 V00B0000
arc: JLSR1 V00B0000
arc: N1_V02N0101 E1_H02W0101
arc: N1_V02N0301 E1_H01W0100
arc: N1_V02N0501 H06E0303
arc: N1_V02N0701 H06E0203
arc: V00B0000 V02S0001
arc: W1_H02W0301 E1_H02W0301
arc: W1_H02W0701 N1_V01S0100
enum: CIB.JA3MUX 0
enum: CIB.JC2MUX 0
enum: CIB.JA1MUX 0
enum: CIB.JC0MUX 0
enum: CIB.JA7MUX 0
enum: CIB.JB6MUX 0
enum: CIB.JD7MUX 0
enum: CIB.JB4MUX 0
enum: CIB.JD5MUX 0
enum: CIB.JB2MUX 0
enum: CIB.JD3MUX 0
enum: CIB.JB0MUX 0
enum: CIB.JD1MUX 0
enum: CIB.JB7MUX 0
enum: CIB.JD6MUX 0
enum: CIB.JB5MUX 0
enum: CIB.JD4MUX 0
enum: CIB.JB3MUX 0
enum: CIB.JD2MUX 0
enum: CIB.JB1MUX 0
enum: CIB.JD0MUX 0
.tile CIB_R22C22:CIB_DSP
arc: E1_H01E0101 JF6
arc: H00L0100 H02W0301
arc: H01W0100 JF7
arc: JCE0 H00L0100
arc: JLSR0 V00B0000
arc: JLSR1 V00B0000
arc: N1_V01N0001 JF5
arc: N1_V01N0101 JF0
arc: N1_V02N0001 JF2
arc: N1_V02N0101 E1_H01W0100
arc: N1_V02N0301 H06E0003
arc: N1_V02N0601 JF4
arc: S1_V02S0101 JF1
arc: V00B0000 V02S0001
arc: W1_H02W0101 JF3
enum: CIB.JA3MUX 0
enum: CIB.JC2MUX 0
enum: CIB.JA1MUX 0
enum: CIB.JC0MUX 0
enum: CIB.JA7MUX 0
enum: CIB.JC6MUX 0
enum: CIB.JA5MUX 0
enum: CIB.JC4MUX 0
enum: CIB.JB6MUX 0
enum: CIB.JD7MUX 0
enum: CIB.JB4MUX 0
enum: CIB.JD5MUX 0
enum: CIB.JB2MUX 0
enum: CIB.JD3MUX 0
enum: CIB.JB0MUX 0
enum: CIB.JD1MUX 0
enum: CIB.JB7MUX 0
enum: CIB.JD6MUX 0
enum: CIB.JB5MUX 0
enum: CIB.JD4MUX 0
enum: CIB.JB3MUX 0
enum: CIB.JD2MUX 0
enum: CIB.JB1MUX 0
enum: CIB.JD0MUX 1
.tile CIB_R22C23:CIB_DSP
arc: E1_H01E0001 JF4
arc: E1_H01E0101 JF7
arc: H01W0100 JF6
arc: JLSR1 V00B0100
arc: N1_V01N0101 JF2
arc: N1_V02N0201 JF0
arc: N1_V02N0301 JF3
arc: N1_V02N0501 H01E0101
arc: N1_V02N0701 JF5
arc: V00B0100 N1_V02S0301
arc: W1_H02W0101 JF1
arc: W1_H02W0301 N1_V02S0301
enum: CIB.JA5MUX 0
enum: CIB.JC4MUX 0
enum: CIB.JA3MUX 0
enum: CIB.JC2MUX 0
enum: CIB.JA1MUX 0
enum: CIB.JC0MUX 0
enum: CIB.JA7MUX 0
enum: CIB.JC6MUX 0
enum: CIB.JB0MUX 0
enum: CIB.JD1MUX 0
enum: CIB.JB6MUX 0
enum: CIB.JD7MUX 0
enum: CIB.JB4MUX 0
enum: CIB.JD5MUX 0
enum: CIB.JB2MUX 0
enum: CIB.JD3MUX 0
enum: CIB.JB1MUX 0
enum: CIB.JD0MUX 0
enum: CIB.JB7MUX 0
enum: CIB.JD6MUX 0
enum: CIB.JB5MUX 0
enum: CIB.JD4MUX 0
enum: CIB.JB3MUX 0
enum: CIB.JD2MUX 0
.tile CIB_R22C24:CIB_DSP
arc: N1_V02N0201 H01E0001
arc: N1_V02N0701 H01E0101
enum: CIB.JA5MUX 0
enum: CIB.JC4MUX 0
enum: CIB.JB0MUX 0
enum: CIB.JD1MUX 0
enum: CIB.JB1MUX 0
enum: CIB.JD0MUX 0
.tile CIB_R22C3:CIB_DSP
arc: W1_H02W0501 V06S0303
.tile CIB_R22C49:CIB_DSP
arc: N3_V06N0103 S3_V06N0003
.tile CIB_R22C51:CIB_DSP
arc: N3_V06N0203 S3_V06N0103
.tile CIB_R22C62:CIB_DSP
arc: N1_V02N0101 H06W0103
.tile CIB_R22C63:CIB_DSP
arc: N1_V02N0101 E1_H01W0100
arc: N1_V02N0301 H06W0003
.tile CIB_R22C64:CIB_DSP
arc: E1_H01E0101 JF7
arc: H00R0100 N1_V02S0701
arc: H01W0100 JF6
arc: JCE2 H00R0100
arc: JCE3 H00R0100
arc: JD7 V01N0001
arc: N1_V01N0001 JF5
arc: N1_V01N0101 JQ4
arc: N1_V02N0101 E1_H01W0100
arc: N1_V02N0301 H02W0301
arc: N1_V02N0401 JQ6
arc: N1_V02N0501 JQ7
arc: N1_V02N0601 JF4
arc: N1_V02N0701 JQ5
enum: CIB.JB6MUX 0
enum: CIB.JB4MUX 0
enum: CIB.JD5MUX 0
enum: CIB.JB7MUX 0
enum: CIB.JD6MUX 0
enum: CIB.JB5MUX 0
enum: CIB.JD4MUX 1
.tile CIB_R22C65:CIB_DSP
arc: E1_H01E0001 JF0
arc: E1_H01E0101 JF1
arc: E1_H02E0301 V02S0301
arc: E1_H02E0701 JQ7
arc: H01W0100 JQ0
arc: N1_V01N0001 JF5
arc: N1_V01N0101 JQ4
arc: N1_V02N0001 JQ2
arc: N1_V02N0101 JQ3
arc: N1_V02N0201 JF2
arc: N1_V02N0301 JF3
arc: N1_V02N0401 JF4
arc: N1_V02N0501 JQ5
arc: N1_V02N0601 JF6
arc: N1_V02N0701 JF7
arc: V01S0100 JQ6
arc: W1_H02W0301 H01E0101
arc: W3_H06W0103 JQ1
enum: CIB.JA3MUX 0
enum: CIB.JC2MUX 0
enum: CIB.JA1MUX 0
enum: CIB.JC0MUX 0
enum: CIB.JA7MUX 0
enum: CIB.JC6MUX 0
enum: CIB.JA5MUX 0
enum: CIB.JC4MUX 0
enum: CIB.JB4MUX 0
enum: CIB.JD5MUX 0
enum: CIB.JB2MUX 0
enum: CIB.JD3MUX 0
enum: CIB.JB0MUX 0
enum: CIB.JD1MUX 0
enum: CIB.JB6MUX 0
enum: CIB.JD7MUX 0
enum: CIB.JB5MUX 0
enum: CIB.JD4MUX 0
enum: CIB.JB3MUX 0
enum: CIB.JD2MUX 0
enum: CIB.JB1MUX 0
enum: CIB.JD0MUX 0
enum: CIB.JB7MUX 0
enum: CIB.JD6MUX 0
enum: CIB.JC1MUX 0
enum: CIB.JA6MUX 0
enum: CIB.JC7MUX 0
enum: CIB.JA4MUX 0
enum: CIB.JC5MUX 0
enum: CIB.JA2MUX 0
enum: CIB.JC3MUX 0
enum: CIB.JA0MUX 0
.tile CIB_R22C66:CIB_DSP
arc: E1_H01E0101 JF0
arc: JLSR0 H02E0301
arc: JLSR1 H02E0301
arc: N1_V01N0001 JQ3
arc: N1_V01N0101 JQ1
arc: N1_V02N0001 JF2
arc: N1_V02N0101 JF3
arc: N1_V02N0201 JQ2
arc: N1_V02N0301 JF1
arc: N1_V02N0601 H01E0001
arc: N1_V02N0701 H01E0101
arc: W3_H06W0003 JQ0
enum: CIB.JA5MUX 0
enum: CIB.JC4MUX 0
enum: CIB.JA3MUX 0
enum: CIB.JC2MUX 0
enum: CIB.JA1MUX 0
enum: CIB.JC0MUX 0
enum: CIB.JA7MUX 0
enum: CIB.JC6MUX 0
enum: CIB.JB4MUX 0
enum: CIB.JD5MUX 0
enum: CIB.JB2MUX 0
enum: CIB.JD3MUX 0
enum: CIB.JB0MUX 0
enum: CIB.JD1MUX 0
enum: CIB.JB5MUX 0
enum: CIB.JD4MUX 0
enum: CIB.JB3MUX 0
enum: CIB.JD2MUX 0
enum: CIB.JB1MUX 0
enum: CIB.JD0MUX 0
enum: CIB.JC1MUX 0
enum: CIB.JA6MUX 0
enum: CIB.JC7MUX 0
enum: CIB.JA4MUX 0
enum: CIB.JC5MUX 0
enum: CIB.JB6MUX 0
enum: CIB.JD7MUX 0
enum: CIB.JB7MUX 0
enum: CIB.JD6MUX 1
.tile CIB_R22C67:CIB_DSP
arc: E1_H02E0101 N1_V02S0101
arc: JD1 V02N0001
arc: JLSR1 V00B0100
arc: N1_V02N0501 H01E0101
arc: N1_V02N0701 W1_H02E0701
arc: V00B0100 N1_V02S0101
enum: CIB.JA5MUX 0
enum: CIB.JC4MUX 0
enum: CIB.JB6MUX 0
enum: CIB.JD7MUX 0
enum: CIB.JB4MUX 0
enum: CIB.JD5MUX 0
enum: CIB.JB2MUX 0
enum: CIB.JD3MUX 0
enum: CIB.JB0MUX 0
enum: CIB.JB7MUX 0
enum: CIB.JD6MUX 0
enum: CIB.JB5MUX 0
enum: CIB.JD4MUX 0
enum: CIB.JB3MUX 0
enum: CIB.JD2MUX 0
enum: CIB.JB1MUX 0
enum: CIB.JD0MUX 0
.tile CIB_R22C68:CIB_DSP
arc: JCE3 H02E0101
arc: JLSR0 V00B0100
arc: JLSR1 V00B0100
arc: V00B0100 V02S0101
enum: CIB.JA3MUX 0
enum: CIB.JC2MUX 0
enum: CIB.JA1MUX 0
enum: CIB.JC0MUX 0
enum: CIB.JA7MUX 0
enum: CIB.JB6MUX 0
enum: CIB.JD7MUX 0
enum: CIB.JB4MUX 0
enum: CIB.JD5MUX 0
enum: CIB.JB2MUX 0
enum: CIB.JD3MUX 0
enum: CIB.JB0MUX 0
enum: CIB.JD1MUX 0
enum: CIB.JB7MUX 0
enum: CIB.JD6MUX 0
enum: CIB.JB5MUX 0
enum: CIB.JD4MUX 0
enum: CIB.JB3MUX 0
enum: CIB.JD2MUX 0
enum: CIB.JB1MUX 0
enum: CIB.JD0MUX 0
.tile CIB_R22C69:CIB_DSP
arc: E1_H02E0501 JQ5
arc: E3_H06E0203 JQ7
arc: E3_H06E0303 JQ6
arc: N1_V01N0101 JQ0
arc: N1_V02N0101 JQ1
arc: N1_V02N0201 JQ2
arc: N1_V02N0301 JQ3
arc: N1_V02N0401 JQ4
enum: CIB.JC1MUX 0
enum: CIB.JA6MUX 0
enum: CIB.JC7MUX 0
enum: CIB.JA4MUX 0
enum: CIB.JC5MUX 0
enum: CIB.JA2MUX 0
enum: CIB.JC3MUX 0
enum: CIB.JA0MUX 0
.tile CIB_R22C70:CIB_DSP
arc: E1_H02E0101 JQ1
arc: E3_H06E0203 JQ7
arc: E3_H06E0303 JQ6
arc: N1_V01N0001 JQ2
arc: N1_V01N0101 JQ4
arc: N1_V02N0001 JQ0
arc: N1_V02N0101 JQ3
arc: N1_V02N0501 JQ7
arc: N1_V02N0701 JQ5
enum: CIB.JC1MUX 0
enum: CIB.JA6MUX 0
enum: CIB.JC7MUX 0
enum: CIB.JA4MUX 0
enum: CIB.JC5MUX 0
.tile CIB_R22C71:CIB_DSP
arc: JD3 V02N0001
arc: JLSR0 V00B0100
arc: JLSR1 V00B0100
arc: N1_V02N0101 H06W0103
arc: N1_V02N0301 H06W0003
arc: N1_V02N0501 W1_H02E0501
arc: N1_V02N0701 E1_H02W0701
arc: V00B0100 V02S0101
enum: CIB.JB6MUX 0
enum: CIB.JD7MUX 0
enum: CIB.JB4MUX 0
enum: CIB.JD5MUX 0
enum: CIB.JB2MUX 0
enum: CIB.JB7MUX 0
enum: CIB.JD6MUX 0
enum: CIB.JB5MUX 0
enum: CIB.JD4MUX 0
enum: CIB.JB3MUX 0
enum: CIB.JD2MUX 1
.tile CIB_R22C72:CIB_DSP
arc: E1_H02E0001 V01N0001
arc: N1_V02N0101 W1_H02E0101
arc: N1_V02N0301 H06W0003
arc: N1_V02N0501 H06E0303
arc: N1_V02N0701 H06E0203
enum: CIB.JA3MUX 0
enum: CIB.JC2MUX 0
enum: CIB.JA1MUX 0
enum: CIB.JC0MUX 0
enum: CIB.JA7MUX 0
enum: CIB.JB2MUX 0
enum: CIB.JD3MUX 0
enum: CIB.JB0MUX 0
enum: CIB.JD1MUX 0
enum: CIB.JB6MUX 0
enum: CIB.JD7MUX 0
enum: CIB.JB4MUX 0
enum: CIB.JD5MUX 0
enum: CIB.JB3MUX 0
enum: CIB.JD2MUX 0
enum: CIB.JB1MUX 0
enum: CIB.JD0MUX 0
enum: CIB.JB7MUX 0
enum: CIB.JD6MUX 0
enum: CIB.JB5MUX 0
enum: CIB.JD4MUX 0
.tile CIB_R22C73:CIB_DSP
arc: H00R0000 N1_V02S0601
arc: H00R0100 N1_V02S0701
arc: JCE0 H00R0000
arc: JCE1 H00R0100
arc: JCE2 H00R0100
arc: JCE3 N1_V02S0601
arc: JD5 H02E0001
arc: N1_V01N0101 JF4
arc: N1_V02N0101 N1_V01S0100
arc: N1_V02N0401 H06E0203
arc: N1_V02N0501 H06E0303
arc: N1_V02N0601 JF6
arc: N1_V02N0701 JF7
arc: W1_H02W0701 JF5
enum: CIB.JB2MUX 0
enum: CIB.JD3MUX 0
enum: CIB.JB0MUX 0
enum: CIB.JD1MUX 0
enum: CIB.JB3MUX 0
enum: CIB.JD2MUX 0
enum: CIB.JB1MUX 0
enum: CIB.JD0MUX 0
enum: CIB.JB6MUX 0
enum: CIB.JD7MUX 0
enum: CIB.JB4MUX 0
enum: CIB.JB7MUX 0
enum: CIB.JD6MUX 0
enum: CIB.JB5MUX 0
enum: CIB.JD4MUX 1
.tile CIB_R22C74:CIB_DSP
arc: E1_H01E0001 JF4
arc: N1_V01N0101 JF5
arc: N1_V02N0001 JF2
arc: N1_V02N0101 E1_H01W0100
arc: N1_V02N0301 JF3
arc: N1_V02N0401 JF6
arc: N1_V02N0501 JF7
arc: W3_H06W0003 JF0
arc: W3_H06W0103 JF1
enum: CIB.JA3MUX 0
enum: CIB.JC2MUX 0
enum: CIB.JA1MUX 0
enum: CIB.JC0MUX 0
enum: CIB.JA7MUX 0
enum: CIB.JC6MUX 0
enum: CIB.JA5MUX 0
enum: CIB.JC4MUX 0
enum: CIB.JB4MUX 0
enum: CIB.JD5MUX 0
enum: CIB.JB2MUX 0
enum: CIB.JD3MUX 0
enum: CIB.JB0MUX 0
enum: CIB.JD1MUX 0
enum: CIB.JB6MUX 0
enum: CIB.JD7MUX 0
enum: CIB.JB5MUX 0
enum: CIB.JD4MUX 0
enum: CIB.JB3MUX 0
enum: CIB.JD2MUX 0
enum: CIB.JB1MUX 0
enum: CIB.JD0MUX 0
enum: CIB.JB7MUX 0
enum: CIB.JD6MUX 0
.tile CIB_R22C75:CIB_DSP
arc: H01W0100 JF1
arc: JLSR0 V00B0000
arc: JLSR1 V00B0100
arc: N1_V01N0101 JF2
arc: N1_V02N0301 JF3
arc: N1_V02N0401 H01E0001
arc: V00B0000 V02S0001
arc: V00B0100 V02S0101
arc: W3_H06W0003 JF0
enum: CIB.JA5MUX 0
enum: CIB.JC4MUX 0
enum: CIB.JA3MUX 0
enum: CIB.JC2MUX 0
enum: CIB.JA1MUX 0
enum: CIB.JC0MUX 0
enum: CIB.JA7MUX 0
enum: CIB.JC6MUX 0
enum: CIB.JB4MUX 0
enum: CIB.JD5MUX 0
enum: CIB.JB2MUX 0
enum: CIB.JD3MUX 0
enum: CIB.JB0MUX 0
enum: CIB.JD1MUX 0
enum: CIB.JB5MUX 0
enum: CIB.JD4MUX 0
enum: CIB.JB3MUX 0
enum: CIB.JD2MUX 0
enum: CIB.JB1MUX 0
enum: CIB.JD0MUX 0
.tile CIB_R22C76:CIB_DSP
enum: CIB.JA5MUX 0
enum: CIB.JC4MUX 0
.tile CIB_R22C87:CIB_DSP
arc: E1_H02E0701 V06S0203
.tile CIB_R22C89:CIB_LR_S
arc: JA0 N1_V02S0701
arc: JA3 W1_H02E0701
enum: CIB.JB0MUX 0
enum: CIB.JB3MUX 0
.tile CIB_R23C1:CIB_LR
arc: E3_H06E0303 JQ5
arc: S1_V02S0501 H06W0303
arc: S1_V02S0701 N1_V02S0701
.tile CIB_R23C89:CIB_LR
arc: JA0 N1_V02S0701
arc: S1_V02S0501 N1_V02S0401
enum: CIB.JB0MUX 0
.tile CIB_R25C1:CIB_LR
arc: JA0 N1_V02S0701
arc: JA3 N1_V02S0501
enum: CIB.JB0MUX 0
enum: CIB.JB3MUX 0
.tile CIB_R25C89:CIB_LR
arc: JA3 N1_V02S0501
enum: CIB.JB3MUX 0
.tile CIB_R34C49:CIB_EBR
arc: N3_V06N0003 S3_V06N0003
.tile CIB_R34C51:CIB_EBR
arc: N3_V06N0003 S3_V06N0003
.tile CIB_R41C1:CIB_LR
arc: JA0 E1_H02W0701
arc: S1_V02S0701 H06W0203
enum: CIB.JB0MUX 0
.tile CIB_R41C89:CIB_LR
arc: JA0 V02N0701
arc: S1_V02S0501 W3_H06E0303
arc: S1_V02S0701 W3_H06E0203
enum: CIB.JB0MUX 0
.tile CIB_R42C1:CIB_LR
arc: S1_V02S0701 H06W0203
.tile CIB_R42C89:CIB_LR
arc: N1_V02N0701 W3_H06E0203
.tile CIB_R43C1:CIB_LR
arc: JA0 N1_V02S0701
arc: JA3 V02S0701
enum: CIB.JB0MUX 0
enum: CIB.JB3MUX 0
.tile CIB_R43C89:CIB_LR
arc: JA0 N1_V02S0701
arc: JA3 N1_V02S0501
enum: CIB.JB3MUX 0
enum: CIB.JB0MUX 0
.tile CIB_R46C46:CIB_DSP
arc: N1_V01N0001 JQ7
arc: N1_V01N0101 JQ6
arc: N1_V02N0501 JQ5
arc: N1_V02N0601 JQ4
.tile CIB_R46C47:CIB_DSP
arc: E1_H01E0001 JQ1
arc: E1_H01E0101 JQ0
arc: N1_V01N0001 JQ4
arc: N1_V01N0101 JQ7
arc: N1_V02N0201 JQ2
arc: N1_V02N0301 JQ3
arc: N1_V02N0601 JQ6
arc: N1_V02N0701 JQ5
enum: CIB.JC1MUX 0
enum: CIB.JA6MUX 0
enum: CIB.JC7MUX 0
enum: CIB.JA4MUX 0
enum: CIB.JC5MUX 0
enum: CIB.JA2MUX 0
enum: CIB.JC3MUX 0
enum: CIB.JA0MUX 0
.tile CIB_R46C48:CIB_DSP
arc: N1_V01N0001 JQ2
arc: N1_V01N0101 JQ0
arc: N1_V02N0001 H01E0001
arc: N1_V02N0101 JQ1
arc: N1_V02N0301 JQ3
arc: N1_V02N0501 E1_H02W0501
arc: N1_V02N0701 H01E0101
enum: CIB.JC1MUX 0
enum: CIB.JA6MUX 0
enum: CIB.JC7MUX 0
enum: CIB.JA4MUX 0
enum: CIB.JC5MUX 0
enum: CIB.JB6MUX 1
enum: CIB.JD7MUX 1
enum: CIB.JB7MUX 0
enum: CIB.JD6MUX 1
.tile CIB_R46C49:CIB_DSP
arc: E1_H02E0501 N1_V02S0501
arc: JLSR1 V00T0100
arc: N1_V02N0101 H06W0103
arc: N1_V02N0301 H06W0003
arc: N1_V02N0501 E1_H02W0501
arc: N1_V02N0601 N1_V01S0000
arc: N1_V02N0701 H06W0203
arc: V00T0100 N1_V02S0501
enum: CIB.JB6MUX 1
enum: CIB.JD7MUX 1
enum: CIB.JB4MUX 1
enum: CIB.JD5MUX 1
enum: CIB.JB2MUX 1
enum: CIB.JD3MUX 1
enum: CIB.JB0MUX 1
enum: CIB.JD1MUX 1
enum: CIB.JB7MUX 0
enum: CIB.JD6MUX 0
enum: CIB.JB5MUX 0
enum: CIB.JD4MUX 0
enum: CIB.JB3MUX 0
enum: CIB.JD2MUX 0
enum: CIB.JB1MUX 0
enum: CIB.JD0MUX 0
.tile CIB_R46C50:CIB_DSP
arc: E1_H02E0301 V02S0301
arc: H00R0100 H02E0501
arc: JCE3 H00R0100
arc: JLSR0 V00B0100
arc: JLSR1 V00B0100
arc: V00B0100 V02S0301
arc: W1_H02W0501 E1_H01W0100
enum: CIB.JA3MUX 0
enum: CIB.JC2MUX 0
enum: CIB.JA1MUX 0
enum: CIB.JC0MUX 0
enum: CIB.JA7MUX 0
enum: CIB.JB6MUX 1
enum: CIB.JD7MUX 1
enum: CIB.JB4MUX 1
enum: CIB.JD5MUX 1
enum: CIB.JB2MUX 1
enum: CIB.JD3MUX 1
enum: CIB.JB0MUX 1
enum: CIB.JD1MUX 1
enum: CIB.JB7MUX 0
enum: CIB.JD6MUX 0
enum: CIB.JB5MUX 0
enum: CIB.JD4MUX 0
enum: CIB.JB3MUX 0
enum: CIB.JD2MUX 0
enum: CIB.JB1MUX 0
enum: CIB.JD0MUX 0
.tile CIB_R46C51:CIB_DSP
arc: E1_H01E0001 JF2
arc: E1_H01E0101 JF0
arc: H00R0000 H02W0401
arc: H01W0100 JF3
arc: JCE0 H00R0000
arc: JLSR0 H02E0301
arc: JLSR1 H02E0301
arc: N1_V01N0001 JF7
arc: N1_V01N0101 JF6
arc: N1_V02N0301 JF1
arc: N1_V02N0601 JF4
arc: N1_V02N0701 H02W0701
arc: S1_V02S0501 JF5
arc: W1_H02W0501 E1_H01W0100
enum: CIB.JA3MUX 0
enum: CIB.JC2MUX 0
enum: CIB.JA1MUX 0
enum: CIB.JC0MUX 0
enum: CIB.JA7MUX 0
enum: CIB.JC6MUX 0
enum: CIB.JA5MUX 0
enum: CIB.JC4MUX 0
enum: CIB.JB6MUX 1
enum: CIB.JD7MUX 1
enum: CIB.JB4MUX 1
enum: CIB.JD5MUX 1
enum: CIB.JB2MUX 1
enum: CIB.JD3MUX 1
enum: CIB.JB0MUX 1
enum: CIB.JD1MUX 1
enum: CIB.JB7MUX 0
enum: CIB.JD6MUX 0
enum: CIB.JB5MUX 0
enum: CIB.JD4MUX 0
enum: CIB.JB3MUX 0
enum: CIB.JD2MUX 0
enum: CIB.JB1MUX 0
enum: CIB.JD0MUX 1
.tile CIB_R46C52:CIB_DSP
arc: E1_H01E0001 JF3
arc: H01W0100 JF2
arc: JLSR1 V00T0000
arc: N1_V01N0101 JF6
arc: N1_V02N0001 H01E0001
arc: N1_V02N0501 JF7
arc: N1_V02N0701 H01E0101
arc: V00T0000 N1_V02S0401
arc: W1_H02W0401 N1_V02S0401
arc: W1_H02W0701 JF5
arc: W3_H06W0003 JF0
arc: W3_H06W0103 JF1
arc: W3_H06W0203 JF4
enum: CIB.JA5MUX 0
enum: CIB.JC4MUX 0
enum: CIB.JA3MUX 0
enum: CIB.JC2MUX 0
enum: CIB.JA1MUX 0
enum: CIB.JC0MUX 0
enum: CIB.JA7MUX 0
enum: CIB.JC6MUX 0
enum: CIB.JB0MUX 1
enum: CIB.JD1MUX 1
enum: CIB.JB6MUX 1
enum: CIB.JD7MUX 1
enum: CIB.JB4MUX 1
enum: CIB.JD5MUX 1
enum: CIB.JB2MUX 1
enum: CIB.JD3MUX 1
enum: CIB.JB1MUX 0
enum: CIB.JD0MUX 0
enum: CIB.JB7MUX 0
enum: CIB.JD6MUX 0
enum: CIB.JB5MUX 0
enum: CIB.JD4MUX 0
enum: CIB.JB3MUX 0
enum: CIB.JD2MUX 0
.tile CIB_R46C53:CIB_DSP
arc: N1_V02N0401 H01E0001
enum: CIB.JA5MUX 0
enum: CIB.JC4MUX 0
enum: CIB.JB0MUX 1
enum: CIB.JD1MUX 1
enum: CIB.JB1MUX 0
enum: CIB.JD0MUX 0
.tile CIB_R5C1:CIB_PLL1
enum: CIB.JA3MUX 0
enum: CIB.JB3MUX 0
.tile CIB_R5C89:CIB_PLL1
enum: CIB.JA3MUX 0
enum: CIB.JB3MUX 0
.tile CIB_R70C15:CIB
arc: JA0 E1_H02W0701
enum: CIB.JB0MUX 0
.tile CIB_R70C17:CIB
arc: W1_H02W0701 N1_V01S0100
.tile CIB_R70C18:CIB
arc: JA0 N1_V02S0701
enum: CIB.JB0MUX 0
.tile CIB_R70C3:CIB_PLL3
enum: CIB.JA3MUX 0
enum: CIB.JB3MUX 0
.tile CIB_R70C42:VCIB_DCU0
enum: CIB.JA1MUX 0
enum: CIB.JA3MUX 0
enum: CIB.JA5MUX 0
enum: CIB.JA7MUX 0
enum: CIB.JB1MUX 0
enum: CIB.JB3MUX 0
enum: CIB.JB5MUX 0
enum: CIB.JB7MUX 0
enum: CIB.JC0MUX 0
enum: CIB.JC2MUX 0
enum: CIB.JC4MUX 0
enum: CIB.JC6MUX 0
enum: CIB.JD0MUX 0
enum: CIB.JD2MUX 0
enum: CIB.JD4MUX 0
enum: CIB.JD6MUX 0
.tile CIB_R70C43:VCIB_DCUA
enum: CIB.JA1MUX 0
enum: CIB.JA3MUX 0
enum: CIB.JA5MUX 0
enum: CIB.JA7MUX 0
enum: CIB.JB1MUX 0
enum: CIB.JB3MUX 0
enum: CIB.JB5MUX 0
enum: CIB.JB7MUX 0
enum: CIB.JC0MUX 0
enum: CIB.JC2MUX 0
enum: CIB.JC4MUX 0
enum: CIB.JC6MUX 0
enum: CIB.JD0MUX 0
enum: CIB.JD2MUX 0
enum: CIB.JD4MUX 0
enum: CIB.JD6MUX 0
.tile CIB_R70C44:VCIB_DCUB
enum: CIB.JA1MUX 0
enum: CIB.JA3MUX 0
enum: CIB.JA5MUX 0
enum: CIB.JA7MUX 0
enum: CIB.JB1MUX 0
enum: CIB.JB3MUX 0
enum: CIB.JB5MUX 0
enum: CIB.JB7MUX 0
enum: CIB.JC0MUX 0
enum: CIB.JC2MUX 0
enum: CIB.JC4MUX 0
enum: CIB.JC6MUX 0
enum: CIB.JD0MUX 0
enum: CIB.JD2MUX 0
enum: CIB.JD4MUX 0
enum: CIB.JD6MUX 0
.tile CIB_R70C45:VCIB_DCUC
enum: CIB.JA1MUX 0
enum: CIB.JA3MUX 0
enum: CIB.JA5MUX 0
enum: CIB.JA7MUX 0
enum: CIB.JB1MUX 0
enum: CIB.JB3MUX 0
enum: CIB.JB5MUX 0
enum: CIB.JB7MUX 0
enum: CIB.JC0MUX 0
enum: CIB.JC2MUX 0
enum: CIB.JC4MUX 0
enum: CIB.JC6MUX 0
enum: CIB.JD0MUX 0
enum: CIB.JD2MUX 0
enum: CIB.JD4MUX 0
enum: CIB.JD6MUX 0
.tile CIB_R70C46:VCIB_DCUD
enum: CIB.JA1MUX 0
enum: CIB.JA5MUX 0
enum: CIB.JA7MUX 0
enum: CIB.JB1MUX 0
enum: CIB.JB3MUX 0
enum: CIB.JB5MUX 0
enum: CIB.JB7MUX 0
enum: CIB.JC0MUX 0
enum: CIB.JC2MUX 0
enum: CIB.JC4MUX 0
enum: CIB.JC6MUX 0
enum: CIB.JD0MUX 0
enum: CIB.JD2MUX 0
enum: CIB.JD4MUX 0
enum: CIB.JD6MUX 0
.tile CIB_R70C47:VCIB_DCUF
enum: CIB.JA1MUX 0
enum: CIB.JA3MUX 0
enum: CIB.JA5MUX 0
enum: CIB.JA7MUX 0
enum: CIB.JB1MUX 0
enum: CIB.JB3MUX 0
enum: CIB.JB5MUX 0
enum: CIB.JB7MUX 0
enum: CIB.JC0MUX 0
enum: CIB.JC2MUX 0
enum: CIB.JC4MUX 0
enum: CIB.JC6MUX 0
enum: CIB.JD0MUX 0
enum: CIB.JD2MUX 0
enum: CIB.JD4MUX 0
enum: CIB.JD6MUX 0
.tile CIB_R70C48:VCIB_DCU3
enum: CIB.JA5MUX 0
enum: CIB.JA7MUX 0
enum: CIB.JB1MUX 0
enum: CIB.JB3MUX 0
enum: CIB.JB5MUX 0
enum: CIB.JB7MUX 0
enum: CIB.JC0MUX 0
enum: CIB.JC4MUX 0
enum: CIB.JC6MUX 0
enum: CIB.JD0MUX 0
enum: CIB.JD2MUX 0
enum: CIB.JD4MUX 0
enum: CIB.JD6MUX 0
.tile CIB_R70C49:VCIB_DCU2
enum: CIB.JB1MUX 0
enum: CIB.JB3MUX 0
enum: CIB.JB5MUX 0
enum: CIB.JB7MUX 0
enum: CIB.JD0MUX 0
enum: CIB.JD2MUX 0
enum: CIB.JD4MUX 0
enum: CIB.JD6MUX 0
.tile CIB_R70C50:VCIB_DCUG
enum: CIB.JB1MUX 0
enum: CIB.JB3MUX 0
enum: CIB.JB5MUX 0
enum: CIB.JB7MUX 0
enum: CIB.JD0MUX 0
enum: CIB.JD2MUX 0
enum: CIB.JD4MUX 0
enum: CIB.JD6MUX 0
.tile CIB_R70C51:VCIB_DCUH
enum: CIB.JB1MUX 0
enum: CIB.JB3MUX 0
enum: CIB.JB5MUX 0
enum: CIB.JB7MUX 0
enum: CIB.JD0MUX 0
enum: CIB.JD2MUX 0
enum: CIB.JD4MUX 0
enum: CIB.JD6MUX 0
.tile CIB_R70C52:VCIB_DCUI
enum: CIB.JB1MUX 0
enum: CIB.JB3MUX 0
enum: CIB.JB5MUX 0
enum: CIB.JB7MUX 0
enum: CIB.JD0MUX 0
enum: CIB.JD2MUX 0
enum: CIB.JD4MUX 0
enum: CIB.JD6MUX 0
.tile CIB_R70C53:VCIB_DCU1
enum: CIB.JB1MUX 0
enum: CIB.JB3MUX 0
enum: CIB.JB5MUX 0
enum: CIB.JD0MUX 0
enum: CIB.JD2MUX 0
.tile CIB_R70C69:VCIB_DCU0
enum: CIB.JA1MUX 0
enum: CIB.JA3MUX 0
enum: CIB.JA5MUX 0
enum: CIB.JA7MUX 0
enum: CIB.JB1MUX 0
enum: CIB.JB3MUX 0
enum: CIB.JB5MUX 0
enum: CIB.JB7MUX 0
enum: CIB.JC0MUX 0
enum: CIB.JC2MUX 0
enum: CIB.JC4MUX 0
enum: CIB.JC6MUX 0
enum: CIB.JD0MUX 0
enum: CIB.JD2MUX 0
enum: CIB.JD4MUX 0
enum: CIB.JD6MUX 0
.tile CIB_R70C6:CIB_EFB0
enum: CIB.JB3MUX 0
enum: CIB.JC6MUX 0
enum: CIB.JD6MUX 0
.tile CIB_R70C70:VCIB_DCUA
enum: CIB.JA1MUX 0
enum: CIB.JA3MUX 0
enum: CIB.JA5MUX 0
enum: CIB.JA7MUX 0
enum: CIB.JB1MUX 0
enum: CIB.JB3MUX 0
enum: CIB.JB5MUX 0
enum: CIB.JB7MUX 0
enum: CIB.JC0MUX 0
enum: CIB.JC2MUX 0
enum: CIB.JC4MUX 0
enum: CIB.JC6MUX 0
enum: CIB.JD0MUX 0
enum: CIB.JD2MUX 0
enum: CIB.JD4MUX 0
enum: CIB.JD6MUX 0
.tile CIB_R70C71:VCIB_DCUB
enum: CIB.JA1MUX 0
enum: CIB.JA3MUX 0
enum: CIB.JA5MUX 0
enum: CIB.JA7MUX 0
enum: CIB.JB1MUX 0
enum: CIB.JB3MUX 0
enum: CIB.JB5MUX 0
enum: CIB.JB7MUX 0
enum: CIB.JC0MUX 0
enum: CIB.JC2MUX 0
enum: CIB.JC4MUX 0
enum: CIB.JC6MUX 0
enum: CIB.JD0MUX 0
enum: CIB.JD2MUX 0
enum: CIB.JD4MUX 0
enum: CIB.JD6MUX 0
.tile CIB_R70C72:VCIB_DCUC
enum: CIB.JA1MUX 0
enum: CIB.JA3MUX 0
enum: CIB.JA5MUX 0
enum: CIB.JA7MUX 0
enum: CIB.JB1MUX 0
enum: CIB.JB3MUX 0
enum: CIB.JB5MUX 0
enum: CIB.JB7MUX 0
enum: CIB.JC0MUX 0
enum: CIB.JC2MUX 0
enum: CIB.JC4MUX 0
enum: CIB.JC6MUX 0
enum: CIB.JD0MUX 0
enum: CIB.JD2MUX 0
enum: CIB.JD4MUX 0
enum: CIB.JD6MUX 0
.tile CIB_R70C73:VCIB_DCUD
enum: CIB.JA1MUX 0
enum: CIB.JA5MUX 0
enum: CIB.JA7MUX 0
enum: CIB.JB1MUX 0
enum: CIB.JB3MUX 0
enum: CIB.JB5MUX 0
enum: CIB.JB7MUX 0
enum: CIB.JC0MUX 0
enum: CIB.JC2MUX 0
enum: CIB.JC4MUX 0
enum: CIB.JC6MUX 0
enum: CIB.JD0MUX 0
enum: CIB.JD2MUX 0
enum: CIB.JD4MUX 0
enum: CIB.JD6MUX 0
.tile CIB_R70C74:VCIB_DCUF
enum: CIB.JA1MUX 0
enum: CIB.JA3MUX 0
enum: CIB.JA5MUX 0
enum: CIB.JA7MUX 0
enum: CIB.JB1MUX 0
enum: CIB.JB3MUX 0
enum: CIB.JB5MUX 0
enum: CIB.JB7MUX 0
enum: CIB.JC0MUX 0
enum: CIB.JC2MUX 0
enum: CIB.JC4MUX 0
enum: CIB.JC6MUX 0
enum: CIB.JD0MUX 0
enum: CIB.JD2MUX 0
enum: CIB.JD4MUX 0
enum: CIB.JD6MUX 0
.tile CIB_R70C75:VCIB_DCU3
enum: CIB.JA5MUX 0
enum: CIB.JA7MUX 0
enum: CIB.JB1MUX 0
enum: CIB.JB3MUX 0
enum: CIB.JB5MUX 0
enum: CIB.JB7MUX 0
enum: CIB.JC0MUX 0
enum: CIB.JC4MUX 0
enum: CIB.JC6MUX 0
enum: CIB.JD0MUX 0
enum: CIB.JD2MUX 0
enum: CIB.JD4MUX 0
enum: CIB.JD6MUX 0
.tile CIB_R70C76:VCIB_DCU2
enum: CIB.JB1MUX 0
enum: CIB.JB3MUX 0
enum: CIB.JB5MUX 0
enum: CIB.JB7MUX 0
enum: CIB.JD0MUX 0
enum: CIB.JD2MUX 0
enum: CIB.JD4MUX 0
enum: CIB.JD6MUX 0
.tile CIB_R70C77:VCIB_DCUG
enum: CIB.JB1MUX 0
enum: CIB.JB3MUX 0
enum: CIB.JB5MUX 0
enum: CIB.JB7MUX 0
enum: CIB.JD0MUX 0
enum: CIB.JD2MUX 0
enum: CIB.JD4MUX 0
enum: CIB.JD6MUX 0
.tile CIB_R70C78:VCIB_DCUH
enum: CIB.JB1MUX 0
enum: CIB.JB3MUX 0
enum: CIB.JB5MUX 0
enum: CIB.JB7MUX 0
enum: CIB.JD0MUX 0
enum: CIB.JD2MUX 0
enum: CIB.JD4MUX 0
enum: CIB.JD6MUX 0
.tile CIB_R70C79:VCIB_DCUI
enum: CIB.JB1MUX 0
enum: CIB.JB3MUX 0
enum: CIB.JB5MUX 0
enum: CIB.JB7MUX 0
enum: CIB.JD0MUX 0
enum: CIB.JD2MUX 0
enum: CIB.JD4MUX 0
enum: CIB.JD6MUX 0
.tile CIB_R70C7:CIB_EFB1
enum: CIB.JA3MUX 0
enum: CIB.JA4MUX 0
enum: CIB.JA5MUX 0
enum: CIB.JA6MUX 0
enum: CIB.JB3MUX 0
enum: CIB.JB4MUX 0
enum: CIB.JB5MUX 0
enum: CIB.JB6MUX 0
enum: CIB.JC3MUX 0
enum: CIB.JC4MUX 0
enum: CIB.JC5MUX 0
enum: CIB.JD3MUX 0
enum: CIB.JD4MUX 0
enum: CIB.JD5MUX 0
.tile CIB_R70C80:VCIB_DCU1
enum: CIB.JB1MUX 0
enum: CIB.JB3MUX 0
enum: CIB.JB5MUX 0
enum: CIB.JD0MUX 0
enum: CIB.JD2MUX 0
.tile CIB_R70C87:CIB_PLL3
enum: CIB.JA3MUX 0
enum: CIB.JB3MUX 0
.tile MIB_R0C18:PIOT0
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
.tile MIB_R0C19:PIOT1
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
.tile MIB_R0C38:PIOT0
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
.tile MIB_R0C39:PIOT1
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
.tile MIB_R0C3:BANKREF0
enum: BANK.VCCIO 3V3
.tile MIB_R0C40:TMID_0
arc: G_TDCC0CLKI G_JTRQPCLKCIB1
.tile MIB_R0C43:PIOT1
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
.tile MIB_R0C49:PIOT0
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
.tile MIB_R0C51:PIOT0
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
.tile MIB_R0C60:PIOT0
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
.tile MIB_R0C62:PIOT0
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
.tile MIB_R0C67:PIOT0
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
.tile MIB_R0C68:PIOT1
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
.tile MIB_R0C74:PIOT0
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
.tile MIB_R0C75:PIOT1
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
.tile MIB_R0C76:PIOT0
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
.tile MIB_R0C87:BANKREF1
enum: BANK.VCCIO 3V3
.tile MIB_R10C0:BANKREF7
enum: BANK.VCCIO 3V3
.tile MIB_R10C12:EBR_SPINE_UL1
arc: G_VPTX0000 G_HPRX0000
.tile MIB_R10C30:EBR_SPINE_UL0
arc: G_VPTX0000 G_HPRX0000
.tile MIB_R10C40:CMUX_UL_0
arc: G_DCS0CLK0 G_VPFN0000
arc: G_ULPCLK0 G_VPFS0000
.tile MIB_R10C41:CMUX_UR_0
arc: G_DCS0CLK1 G_VPFN0000
arc: G_URPCLK0 G_VPFS0000
.tile MIB_R10C50:EBR_SPINE_UR0
arc: G_VPTX0000 G_HPRX0000
.tile MIB_R10C77:EBR_SPINE_UR1
arc: G_VPTX0000 G_HPRX0000
.tile MIB_R10C90:BANKREF2
enum: BANK.VCCIO 3V3
.tile MIB_R12C0:PICL1
enum: PIOD.BASE_TYPE INPUT_LVCMOS33
enum: PIOD.HYSTERESIS ON
.tile MIB_R13C0:PICL2
enum: PIOD.BASE_TYPE INPUT_LVCMOS33
.tile MIB_R18C90:PICR1_DQS3
enum: PIOC.BASE_TYPE INPUT_LVCMOS33
enum: PIOC.HYSTERESIS ON
.tile MIB_R19C90:PICR2
enum: PIOC.BASE_TYPE INPUT_LVCMOS33
.tile MIB_R1C18:PICT0
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
.tile MIB_R1C19:PICT1
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
.tile MIB_R1C38:PICT0
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
.tile MIB_R1C39:PICT1
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
.tile MIB_R1C43:PICT1
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
.tile MIB_R1C49:PICT0
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
.tile MIB_R1C51:PICT0
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
.tile MIB_R1C60:PICT0
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
.tile MIB_R1C62:PICT0
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
.tile MIB_R1C67:PICT0
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
.tile MIB_R1C68:PICT1
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
.tile MIB_R1C74:PICT0
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
.tile MIB_R1C75:PICT1
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
.tile MIB_R1C76:PICT0
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
.tile MIB_R20C0:PICL0
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
.tile MIB_R20C90:PICR0
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
.tile MIB_R21C0:PICL1
enum: PIOD.BASE_TYPE OUTPUT_LVCMOS33
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
.tile MIB_R21C90:PICR1
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
enum: PIOD.BASE_TYPE OUTPUT_LVCMOS33
.tile MIB_R22C0:MIB_CIB_LR
enum: PIOD.BASE_TYPE OUTPUT_LVCMOS33
enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33
.tile MIB_R22C90:MIB_CIB_LR_A
enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33
enum: PIOD.BASE_TYPE OUTPUT_LVCMOS33
.tile MIB_R23C0:PICL0
arc: JDIB JPADDIB_PIO
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
.tile MIB_R23C90:PICR0
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
.tile MIB_R24C0:PICL1
enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
enum: PIOB.HYSTERESIS ON
enum: PIOD.BASE_TYPE OUTPUT_LVCMOS33
.tile MIB_R24C90:PICR1
enum: PIOD.BASE_TYPE OUTPUT_LVCMOS33
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
.tile MIB_R25C0:PICL2
enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33
enum: PIOD.BASE_TYPE OUTPUT_LVCMOS33
.tile MIB_R25C90:PICR2
enum: PIOD.BASE_TYPE OUTPUT_LVCMOS33
.tile MIB_R41C0:PICL0_DQS2
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
.tile MIB_R41C90:PICR0_DQS2
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
.tile MIB_R42C0:PICL1_DQS3
enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33
enum: PIOD.BASE_TYPE OUTPUT_LVCMOS33
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
.tile MIB_R42C90:PICR1_DQS3
enum: PIOD.BASE_TYPE OUTPUT_LVCMOS33
enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
.tile MIB_R43C0:PICL2
enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33
enum: PIOD.BASE_TYPE OUTPUT_LVCMOS33
.tile MIB_R43C90:PICR2
enum: PIOD.BASE_TYPE OUTPUT_LVCMOS33
enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33
.tile MIB_R58C40:CMUX_LL_0
arc: G_DCS1CLK0 G_VPFN0000
arc: G_LLPCLK0 G_VPFS0000
.tile MIB_R58C41:CMUX_LR_0
arc: G_DCS1CLK1 G_VPFN0000
arc: G_LRPCLK0 G_VPFS0000
.tile MIB_R58C50:EBR_SPINE_LR0
arc: G_VPTX0000 G_HPRX0000
.tile MIB_R71C15:PICB0
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
.tile MIB_R71C18:SPICB0
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
.tile MIB_R71C1:BANKREF6
enum: BANK.VCCIO 3V3
.tile MIB_R71C3:BANKREF8
enum: BANK.VCCIO 3V3
.tile MIB_R71C4:EFB0_PICB0
unknown: F54B1
unknown: F56B1
unknown: F82B1
unknown: F94B1
.tile MIB_R71C89:BANKREF3
enum: BANK.VCCIO 3V3
.tile R11C41:PLC2
arc: N3_V06N0203 S3_V06N0103
.tile R11C60:PLC2
arc: N1_V02N0601 S3_V06N0303
.tile R13C13:PLC2
arc: E3_H06E0103 W3_H06E0003
.tile R13C19:PLC2
arc: E3_H06E0103 W3_H06E0103
.tile R13C25:PLC2
arc: E3_H06E0203 W3_H06E0103
.tile R13C31:PLC2
arc: E3_H06E0203 W3_H06E0203
.tile R13C37:PLC2
arc: N3_V06N0203 W3_H06E0203
.tile R13C39:PLC2
arc: N3_V06N0203 S3_V06N0203
.tile R13C63:PLC2
arc: N3_V06N0103 S3_V06N0003
.tile R13C7:PLC2
arc: E3_H06E0003 W3_H06E0303
.tile R14C38:PLC2
arc: N3_V06N0303 S3_V06N0303
.tile R14C67:PLC2
arc: N3_V06N0003 S3_V06N0003
arc: N3_V06N0203 S3_V06N0103
.tile R15C18:PLC2
arc: N3_V06N0103 S1_V02N0201
.tile R15C75:PLC2
arc: N3_V06N0003 S3_V06N0303
arc: N3_V06N0203 S3_V06N0103
.tile R15C76:PLC2
arc: N3_V06N0103 S3_V06N0003
.tile R16C18:PLC2
arc: N3_V06N0003 S1_V02N0001
.tile R16C49:PLC2
arc: N3_V06N0203 S3_V06N0103
.tile R16C51:PLC2
arc: N3_V06N0303 S3_V06N0203
.tile R17C16:PLC2
arc: E1_H02E0401 E1_H01W0000
.tile R17C17:PLC2
arc: E1_H02E0201 E3_H06W0103
arc: E1_H02E0501 S1_V02N0501
arc: H01W0000 E3_H06W0103
arc: S1_V02S0101 E3_H06W0103
arc: S1_V02S0201 E3_H06W0103
arc: V00T0000 S1_V02N0601
arc: A0 E1_H02W0701
arc: C0 H02E0401
arc: CE0 S1_V02N0201
arc: CLK0 G_HPBX0000
arc: D0 V02N0001
arc: E3_H06E0003 Q0
arc: F0 F0_SLICE
arc: LSR0 V00T0000
arc: MUXCLK0 CLK0
arc: MUXLSR0 LSR0
word: SLICEA.K0.INIT 0000000010101111
enum: SLICEA.GSR DISABLED
enum: SLICEA.REG0.SD 1
enum: SLICEA.REG0.REGSET RESET
enum: SLICEA.REG0.LSRMODE LSR
enum: SLICEA.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEA.MODE LOGIC
enum: SLICEA.CCU2.INJECT1_0 _NONE_
enum: SLICEA.B0MUX 1
.tile R17C18:PLC2
arc: H00R0000 S1_V02N0601
arc: B0 V02N0101
arc: C0 V02N0601
arc: CE0 H00R0000
arc: CLK0 G_HPBX0000
arc: D0 H02E0201
arc: D5 V02N0401
arc: E1_H02E0701 F5
arc: F0 F0_SLICE
arc: F5 F5_SLICE
arc: LSR1 H02E0501
arc: MUXCLK0 CLK0
arc: MUXLSR0 LSR1
arc: N1_V02N0201 Q0
word: SLICEC.K1.INIT 0000000011111111
word: SLICEA.K0.INIT 0000001100001111
enum: SLICEA.GSR DISABLED
enum: SLICEA.REG0.SD 1
enum: SLICEA.REG0.REGSET RESET
enum: SLICEA.REG0.LSRMODE LSR
enum: SLICEA.CEMUX CE
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEC.MODE LOGIC
enum: SLICEC.CCU2.INJECT1_1 _NONE_
enum: SLICEC.A1MUX 1
enum: SLICEC.B1MUX 1
enum: SLICEC.C1MUX 1
enum: SLICEA.MODE LOGIC
enum: SLICEA.CCU2.INJECT1_0 _NONE_
enum: SLICEA.A0MUX 1
.tile R17C19:PLC2
arc: V00B0000 V02N0201
arc: V00T0000 V02N0401
arc: W1_H02W0701 S1_V02N0701
arc: A3 H02E0701
arc: A4 V02N0301
arc: A5 V00T0000
arc: B0 V00B0000
arc: B2 V02N0101
arc: B6 V02N0701
arc: B7 S1_V02N0701
word: SLICED.K1.INIT 1001100110011100
word: SLICED.K0.INIT 1001100110011100
word: SLICEC.K1.INIT 1001100110011010
word: SLICEC.K0.INIT 1001100110011010
word: SLICEB.K1.INIT 1001100110011010
word: SLICEB.K0.INIT 1001100110011100
word: SLICEA.K1.INIT 1111111111111111
word: SLICEA.K0.INIT 0000000000001100
enum: SLICED.MODE CCU2
enum: SLICED.CCU2.INJECT1_1 NO
enum: SLICED.A1MUX 1
enum: SLICED.C1MUX 1
enum: SLICED.D1MUX 1
enum: SLICED.MODE CCU2
enum: SLICED.CCU2.INJECT1_0 NO
enum: SLICED.A0MUX 1
enum: SLICED.C0MUX 1
enum: SLICED.D0MUX 1
enum: SLICEC.MODE CCU2
enum: SLICEC.CCU2.INJECT1_1 NO
enum: SLICEC.B1MUX 1
enum: SLICEC.C1MUX 1
enum: SLICEC.D1MUX 1
enum: SLICEC.MODE CCU2
enum: SLICEC.CCU2.INJECT1_0 NO
enum: SLICEC.B0MUX 1
enum: SLICEC.C0MUX 1
enum: SLICEC.D0MUX 1
enum: SLICEB.MODE CCU2
enum: SLICEB.CCU2.INJECT1_1 NO
enum: SLICEB.B1MUX 1
enum: SLICEB.C1MUX 1
enum: SLICEB.D1MUX 1
enum: SLICEB.MODE CCU2
enum: SLICEB.CCU2.INJECT1_0 NO
enum: SLICEB.A0MUX 1
enum: SLICEB.C0MUX 1
enum: SLICEB.D0MUX 1
enum: SLICEA.MODE CCU2
enum: SLICEA.CCU2.INJECT1_1 YES
enum: SLICEA.A1MUX 1
enum: SLICEA.B1MUX 1
enum: SLICEA.C1MUX 1
enum: SLICEA.D1MUX 1
enum: SLICEA.MODE CCU2
enum: SLICEA.CCU2.INJECT1_0 NO
enum: SLICEA.A0MUX 1
enum: SLICEA.C0MUX 1
enum: SLICEA.D0MUX 1
.tile R17C20:PLC2
arc: V00T0000 V02N0601
arc: A0 V02N0501
arc: A1 V01N0101
arc: A4 V02N0301
arc: A5 V00T0000
arc: B2 V02N0101
arc: B3 V01N0001
arc: B6 V02N0701
arc: B7 S1_V02N0501
word: SLICED.K1.INIT 0011001100111100
word: SLICED.K0.INIT 0011001100111100
word: SLICEC.K1.INIT 0101010101011010
word: SLICEC.K0.INIT 0101010101011010
word: SLICEB.K1.INIT 0011001100111100
word: SLICEB.K0.INIT 0011001100111100
word: SLICEA.K1.INIT 0101010101011010
word: SLICEA.K0.INIT 1001100110011010
enum: SLICED.MODE CCU2
enum: SLICED.CCU2.INJECT1_1 NO
enum: SLICED.A1MUX 1
enum: SLICED.C1MUX 1
enum: SLICED.D1MUX 1
enum: SLICED.MODE CCU2
enum: SLICED.CCU2.INJECT1_0 NO
enum: SLICED.A0MUX 1
enum: SLICED.C0MUX 1
enum: SLICED.D0MUX 1
enum: SLICEC.MODE CCU2
enum: SLICEC.CCU2.INJECT1_1 NO
enum: SLICEC.B1MUX 1
enum: SLICEC.C1MUX 1
enum: SLICEC.D1MUX 1
enum: SLICEC.MODE CCU2
enum: SLICEC.CCU2.INJECT1_0 NO
enum: SLICEC.B0MUX 1
enum: SLICEC.C0MUX 1
enum: SLICEC.D0MUX 1
enum: SLICEB.MODE CCU2
enum: SLICEB.CCU2.INJECT1_1 NO
enum: SLICEB.A1MUX 1
enum: SLICEB.C1MUX 1
enum: SLICEB.D1MUX 1
enum: SLICEB.MODE CCU2
enum: SLICEB.CCU2.INJECT1_0 NO
enum: SLICEB.A0MUX 1
enum: SLICEB.C0MUX 1
enum: SLICEB.D0MUX 1
enum: SLICEA.MODE CCU2
enum: SLICEA.CCU2.INJECT1_1 NO
enum: SLICEA.B1MUX 1
enum: SLICEA.C1MUX 1
enum: SLICEA.D1MUX 1
enum: SLICEA.MODE CCU2
enum: SLICEA.CCU2.INJECT1_0 NO
enum: SLICEA.B0MUX 1
enum: SLICEA.C0MUX 1
enum: SLICEA.D0MUX 1
.tile R17C21:PLC2
arc: V00B0000 V02N0201
arc: V00T0000 V02N0401
arc: A1 V01N0101
arc: A3 V00B0000
arc: A4 V02N0301
arc: B0 V02N0101
arc: B2 V01N0001
arc: B5 S1_V02N0701
arc: B6 V02N0701
arc: B7 V00T0000
word: SLICED.K1.INIT 0011001100111100
word: SLICED.K0.INIT 0011001100111100
word: SLICEC.K1.INIT 0011001100111100
word: SLICEC.K0.INIT 0101010101011010
word: SLICEB.K1.INIT 0101010101011010
word: SLICEB.K0.INIT 0011001100111100
word: SLICEA.K1.INIT 0101010101011010
word: SLICEA.K0.INIT 0011001100111100
enum: SLICED.MODE CCU2
enum: SLICED.CCU2.INJECT1_1 NO
enum: SLICED.A1MUX 1
enum: SLICED.C1MUX 1
enum: SLICED.D1MUX 1
enum: SLICED.MODE CCU2
enum: SLICED.CCU2.INJECT1_0 NO
enum: SLICED.A0MUX 1
enum: SLICED.C0MUX 1
enum: SLICED.D0MUX 1
enum: SLICEC.MODE CCU2
enum: SLICEC.CCU2.INJECT1_1 NO
enum: SLICEC.A1MUX 1
enum: SLICEC.C1MUX 1
enum: SLICEC.D1MUX 1
enum: SLICEC.MODE CCU2
enum: SLICEC.CCU2.INJECT1_0 NO
enum: SLICEC.B0MUX 1
enum: SLICEC.C0MUX 1
enum: SLICEC.D0MUX 1
enum: SLICEB.MODE CCU2
enum: SLICEB.CCU2.INJECT1_1 NO
enum: SLICEB.B1MUX 1
enum: SLICEB.C1MUX 1
enum: SLICEB.D1MUX 1
enum: SLICEB.MODE CCU2
enum: SLICEB.CCU2.INJECT1_0 NO
enum: SLICEB.A0MUX 1
enum: SLICEB.C0MUX 1
enum: SLICEB.D0MUX 1
enum: SLICEA.MODE CCU2
enum: SLICEA.CCU2.INJECT1_1 NO
enum: SLICEA.B1MUX 1
enum: SLICEA.C1MUX 1
enum: SLICEA.D1MUX 1
enum: SLICEA.MODE CCU2
enum: SLICEA.CCU2.INJECT1_0 NO
enum: SLICEA.A0MUX 1
enum: SLICEA.C0MUX 1
enum: SLICEA.D0MUX 1
.tile R17C22:PLC2
arc: V00B0000 V02N0001
arc: V00T0000 V02N0401
arc: A1 V01N0101
arc: A3 V00B0000
arc: A4 V02N0301
arc: B0 V02N0101
arc: B2 V01N0001
arc: B5 S1_V02N0701
arc: B6 V02N0501
arc: B7 V00T0000
word: SLICED.K1.INIT 0011001100111100
word: SLICED.K0.INIT 0011001100111100
word: SLICEC.K1.INIT 0011001100111100
word: SLICEC.K0.INIT 0101010101011010
word: SLICEB.K1.INIT 0101010101011010
word: SLICEB.K0.INIT 0011001100111100
word: SLICEA.K1.INIT 0101010101011010
word: SLICEA.K0.INIT 0011001100111100
enum: SLICED.MODE CCU2
enum: SLICED.CCU2.INJECT1_1 NO
enum: SLICED.A1MUX 1
enum: SLICED.C1MUX 1
enum: SLICED.D1MUX 1
enum: SLICED.MODE CCU2
enum: SLICED.CCU2.INJECT1_0 NO
enum: SLICED.A0MUX 1
enum: SLICED.C0MUX 1
enum: SLICED.D0MUX 1
enum: SLICEC.MODE CCU2
enum: SLICEC.CCU2.INJECT1_1 NO
enum: SLICEC.A1MUX 1
enum: SLICEC.C1MUX 1
enum: SLICEC.D1MUX 1
enum: SLICEC.MODE CCU2
enum: SLICEC.CCU2.INJECT1_0 NO
enum: SLICEC.B0MUX 1
enum: SLICEC.C0MUX 1
enum: SLICEC.D0MUX 1
enum: SLICEB.MODE CCU2
enum: SLICEB.CCU2.INJECT1_1 NO
enum: SLICEB.B1MUX 1
enum: SLICEB.C1MUX 1
enum: SLICEB.D1MUX 1
enum: SLICEB.MODE CCU2
enum: SLICEB.CCU2.INJECT1_0 NO
enum: SLICEB.A0MUX 1
enum: SLICEB.C0MUX 1
enum: SLICEB.D0MUX 1
enum: SLICEA.MODE CCU2
enum: SLICEA.CCU2.INJECT1_1 NO
enum: SLICEA.B1MUX 1
enum: SLICEA.C1MUX 1
enum: SLICEA.D1MUX 1
enum: SLICEA.MODE CCU2
enum: SLICEA.CCU2.INJECT1_0 NO
enum: SLICEA.A0MUX 1
enum: SLICEA.C0MUX 1
enum: SLICEA.D0MUX 1
.tile R17C23:PLC2
arc: E3_H06E0003 W3_H06E0003
arc: B0 V02N0301
arc: B1 V01N0001
arc: F1 F1_SLICE
arc: W3_H06W0103 F1
word: SLICEB.K1.INIT 0000000000001110
word: SLICEB.K0.INIT 0000000000000000
word: SLICEA.K1.INIT 0011001100111100
word: SLICEA.K0.INIT 0011001100111100
enum: SLICEB.MODE CCU2
enum: SLICEB.CCU2.INJECT1_1 NO
enum: SLICEB.A1MUX 1
enum: SLICEB.B1MUX 1
enum: SLICEB.C1MUX 1
enum: SLICEB.D1MUX 1
enum: SLICEB.MODE CCU2
enum: SLICEB.CCU2.INJECT1_0 NO
enum: SLICEB.A0MUX 1
enum: SLICEB.B0MUX 1
enum: SLICEB.C0MUX 1
enum: SLICEB.D0MUX 1
enum: SLICEA.MODE CCU2
enum: SLICEA.CCU2.INJECT1_1 NO
enum: SLICEA.A1MUX 1
enum: SLICEA.C1MUX 1
enum: SLICEA.D1MUX 1
enum: SLICEA.MODE CCU2
enum: SLICEA.CCU2.INJECT1_0 NO
enum: SLICEA.A0MUX 1
enum: SLICEA.C0MUX 1
enum: SLICEA.D0MUX 1
.tile R17C29:PLC2
arc: E3_H06E0103 W3_H06E0003
.tile R17C35:PLC2
arc: E3_H06E0103 W3_H06E0103
.tile R17C41:PLC2
arc: N3_V06N0103 W3_H06E0103
.tile R17C60:PLC2
arc: N3_V06N0303 S3_V06N0203
.tile R18C17:PLC2
arc: E1_H01E0001 E3_H06W0003
arc: E1_H02E0001 E3_H06W0003
arc: E1_H02E0101 V02S0101
arc: E1_H02E0501 V02N0501
arc: N1_V02N0001 E3_H06W0003
arc: S1_V02S0301 E3_H06W0003
arc: S1_V02S0701 E1_H02W0701
.tile R18C18:PLC2
arc: H00R0000 V02N0601
arc: N1_V02N0101 S1_V02N0101
arc: N1_V02N0401 S1_V02N0101
arc: N1_V02N0601 H01E0001
arc: S1_V02S0601 H01E0001
arc: B0 H02E0101
arc: C0 E1_H01W0000
arc: CE0 H00R0000
arc: CLK0 G_HPBX0000
arc: D0 H02E0001
arc: F0 F0_SLICE
arc: LSR0 H02E0501
arc: MUXCLK0 CLK0
arc: MUXLSR0 LSR0
arc: N1_V02N0001 Q0
word: SLICEA.K0.INIT 0000000011110011
enum: SLICEA.GSR DISABLED
enum: SLICEA.REG0.SD 1
enum: SLICEA.REG0.REGSET RESET
enum: SLICEA.REG0.LSRMODE LSR
enum: SLICEA.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEA.MODE LOGIC
enum: SLICEA.CCU2.INJECT1_0 _NONE_
enum: SLICEA.A0MUX 1
.tile R18C19:PLC2
arc: H00R0000 S1_V02N0401
arc: N1_V02N0101 S1_V02N0001
arc: N1_V02N0201 S1_V02N0201
arc: V00T0000 S1_V02N0601
arc: A3 V00T0000
arc: A4 V02N0101
arc: B0 V02N0301
arc: B2 S1_V02N0301
arc: B5 H00R0000
arc: B6 S1_V02N0501
arc: B7 S1_V02N0701
arc: E1_H01E0101 F7
arc: F3 F3_SLICE
arc: F4 F4_SLICE
arc: F5 F5_SLICE
arc: F6 F6_SLICE
arc: F7 F7_SLICE
arc: H01W0000 F4
arc: N1_V02N0301 F3
arc: N1_V02N0401 F4
arc: N1_V02N0701 F5
arc: S1_V02S0401 F4
arc: S1_V02S0501 F7
arc: S1_V02S0701 F5
arc: S3_V06S0303 F6
arc: V01S0000 F3
arc: V01S0100 F6
arc: W1_H02W0701 F7
word: SLICED.K1.INIT 1100110011000000
word: SLICED.K0.INIT 1100110011000000
word: SLICEC.K1.INIT 1100110011000000
word: SLICEC.K0.INIT 0110011001101100
word: SLICEB.K1.INIT 1010101010100000
word: SLICEB.K0.INIT 0110011001101010
word: SLICEA.K1.INIT 1111111111111111
word: SLICEA.K0.INIT 0000000000001100
enum: SLICED.MODE CCU2
enum: SLICED.CCU2.INJECT1_1 NO
enum: SLICED.A1MUX 1
enum: SLICED.C1MUX 1
enum: SLICED.D1MUX 1
enum: SLICED.MODE CCU2
enum: SLICED.CCU2.INJECT1_0 NO
enum: SLICED.A0MUX 1
enum: SLICED.C0MUX 1
enum: SLICED.D0MUX 1
enum: SLICEC.MODE CCU2
enum: SLICEC.CCU2.INJECT1_1 NO
enum: SLICEC.A1MUX 1
enum: SLICEC.C1MUX 1
enum: SLICEC.D1MUX 1
enum: SLICEC.MODE CCU2
enum: SLICEC.CCU2.INJECT1_0 NO
enum: SLICEC.B0MUX 1
enum: SLICEC.C0MUX 1
enum: SLICEC.D0MUX 1
enum: SLICEB.MODE CCU2
enum: SLICEB.CCU2.INJECT1_1 NO
enum: SLICEB.B1MUX 1
enum: SLICEB.C1MUX 1
enum: SLICEB.D1MUX 1
enum: SLICEB.MODE CCU2
enum: SLICEB.CCU2.INJECT1_0 NO
enum: SLICEB.A0MUX 1
enum: SLICEB.C0MUX 1
enum: SLICEB.D0MUX 1
enum: SLICEA.MODE CCU2
enum: SLICEA.CCU2.INJECT1_1 YES
enum: SLICEA.A1MUX 1
enum: SLICEA.B1MUX 1
enum: SLICEA.C1MUX 1
enum: SLICEA.D1MUX 1
enum: SLICEA.MODE CCU2
enum: SLICEA.CCU2.INJECT1_0 NO
enum: SLICEA.A0MUX 1
enum: SLICEA.C0MUX 1
enum: SLICEA.D0MUX 1
.tile R18C20:PLC2
arc: H00R0000 S1_V02N0401
arc: N1_V02N0501 H01E0101
arc: V00B0000 S1_V02N0001
arc: V00T0000 S1_V02N0601
arc: A5 V00T0000
arc: B0 S1_V02N0101
arc: B1 V00B0000
arc: B2 S1_V02N0301
arc: B3 H00R0000
arc: B4 V02N0701
arc: B6 S1_V02N0501
arc: B7 S1_V02N0701
arc: E1_H01E0001 F0
arc: E1_H01E0101 F7
arc: F0 F0_SLICE
arc: F1 F1_SLICE
arc: F2 F2_SLICE
arc: F3 F3_SLICE
arc: F4 F4_SLICE
arc: F5 F5_SLICE
arc: F6 F6_SLICE
arc: F7 F7_SLICE
arc: N1_V01N0001 F2
arc: N1_V01N0101 F0
arc: N1_V02N0101 F1
arc: N1_V02N0301 F3
arc: N1_V02N0601 F4
arc: N1_V02N0701 F5
arc: S1_V02S0101 F1
arc: S1_V02S0201 F2
arc: S1_V02S0301 F3
arc: S1_V02S0501 F5
arc: S1_V02S0601 F4
arc: S1_V02S0701 F7
arc: V01S0000 F6
arc: V01S0100 F6
word: SLICED.K1.INIT 1100110011000000
word: SLICED.K0.INIT 1100110011000000
word: SLICEC.K1.INIT 1010101010100000
word: SLICEC.K0.INIT 1100110011000000
word: SLICEB.K1.INIT 1100110011000000
word: SLICEB.K0.INIT 1100110011000000
word: SLICEA.K1.INIT 1100110011000000
word: SLICEA.K0.INIT 1100110011000000
enum: SLICED.MODE CCU2
enum: SLICED.CCU2.INJECT1_1 NO
enum: SLICED.A1MUX 1
enum: SLICED.C1MUX 1
enum: SLICED.D1MUX 1
enum: SLICED.MODE CCU2
enum: SLICED.CCU2.INJECT1_0 NO
enum: SLICED.A0MUX 1
enum: SLICED.C0MUX 1
enum: SLICED.D0MUX 1
enum: SLICEC.MODE CCU2
enum: SLICEC.CCU2.INJECT1_1 NO
enum: SLICEC.B1MUX 1
enum: SLICEC.C1MUX 1
enum: SLICEC.D1MUX 1
enum: SLICEC.MODE CCU2
enum: SLICEC.CCU2.INJECT1_0 NO
enum: SLICEC.A0MUX 1
enum: SLICEC.C0MUX 1
enum: SLICEC.D0MUX 1
enum: SLICEB.MODE CCU2
enum: SLICEB.CCU2.INJECT1_1 NO
enum: SLICEB.A1MUX 1
enum: SLICEB.C1MUX 1
enum: SLICEB.D1MUX 1
enum: SLICEB.MODE CCU2
enum: SLICEB.CCU2.INJECT1_0 NO
enum: SLICEB.A0MUX 1
enum: SLICEB.C0MUX 1
enum: SLICEB.D0MUX 1
enum: SLICEA.MODE CCU2
enum: SLICEA.CCU2.INJECT1_1 NO
enum: SLICEA.A1MUX 1
enum: SLICEA.C1MUX 1
enum: SLICEA.D1MUX 1
enum: SLICEA.MODE CCU2
enum: SLICEA.CCU2.INJECT1_0 NO
enum: SLICEA.A0MUX 1
enum: SLICEA.C0MUX 1
enum: SLICEA.D0MUX 1
.tile R18C21:PLC2
arc: H00R0000 S1_V02N0601
arc: N1_V02N0101 H01E0101
arc: S1_V02S0001 H01E0001
arc: V00B0000 S1_V02N0001
arc: V00T0000 S1_V02N0401
arc: A5 V00T0000
arc: B0 S1_V02N0301
arc: B1 V00B0000
arc: B2 S1_V02N0101
arc: B3 H00R0000
arc: B4 V02N0501
arc: B6 S1_V02N0501
arc: B7 S1_V02N0701
arc: E1_H01E0001 F2
arc: E1_H01E0101 F7
arc: F0 F0_SLICE
arc: F1 F1_SLICE
arc: F2 F2_SLICE
arc: F3 F3_SLICE
arc: F4 F4_SLICE
arc: F5 F5_SLICE
arc: F6 F6_SLICE
arc: F7 F7_SLICE
arc: N1_V01N0001 F1
arc: N1_V01N0101 F0
arc: N1_V02N0201 F2
arc: N1_V02N0301 F3
arc: N1_V02N0401 F6
arc: N1_V02N0701 F5
arc: S1_V02S0101 F1
arc: S1_V02S0201 F0
arc: S1_V02S0401 F6
arc: S1_V02S0501 F5
arc: V01S0000 F3
arc: V01S0100 F4
word: SLICED.K1.INIT 1100110011000000
word: SLICED.K0.INIT 1100110011000000
word: SLICEC.K1.INIT 1010101010100000
word: SLICEC.K0.INIT 1100110011000000
word: SLICEB.K1.INIT 1100110011000000
word: SLICEB.K0.INIT 1100110011000000
word: SLICEA.K1.INIT 1100110011000000
word: SLICEA.K0.INIT 1100110011000000
enum: SLICED.MODE CCU2
enum: SLICED.CCU2.INJECT1_1 NO
enum: SLICED.A1MUX 1
enum: SLICED.C1MUX 1
enum: SLICED.D1MUX 1
enum: SLICED.MODE CCU2
enum: SLICED.CCU2.INJECT1_0 NO
enum: SLICED.A0MUX 1
enum: SLICED.C0MUX 1
enum: SLICED.D0MUX 1
enum: SLICEC.MODE CCU2
enum: SLICEC.CCU2.INJECT1_1 NO
enum: SLICEC.B1MUX 1
enum: SLICEC.C1MUX 1
enum: SLICEC.D1MUX 1
enum: SLICEC.MODE CCU2
enum: SLICEC.CCU2.INJECT1_0 NO
enum: SLICEC.A0MUX 1
enum: SLICEC.C0MUX 1
enum: SLICEC.D0MUX 1
enum: SLICEB.MODE CCU2
enum: SLICEB.CCU2.INJECT1_1 NO
enum: SLICEB.A1MUX 1
enum: SLICEB.C1MUX 1
enum: SLICEB.D1MUX 1
enum: SLICEB.MODE CCU2
enum: SLICEB.CCU2.INJECT1_0 NO
enum: SLICEB.A0MUX 1
enum: SLICEB.C0MUX 1
enum: SLICEB.D0MUX 1
enum: SLICEA.MODE CCU2
enum: SLICEA.CCU2.INJECT1_1 NO
enum: SLICEA.A1MUX 1
enum: SLICEA.C1MUX 1
enum: SLICEA.D1MUX 1
enum: SLICEA.MODE CCU2
enum: SLICEA.CCU2.INJECT1_0 NO
enum: SLICEA.A0MUX 1
enum: SLICEA.C0MUX 1
enum: SLICEA.D0MUX 1
.tile R18C22:PLC2
arc: H00R0000 S1_V02N0601
arc: N1_V02N0101 H01E0101
arc: S1_V02S0401 H01E0001
arc: S1_V02S0701 H01E0101
arc: V00B0000 S1_V02N0001
arc: V00T0000 S1_V02N0401
arc: A5 V00T0000
arc: B0 S1_V02N0101
arc: B1 V00B0000
arc: B2 S1_V02N0301
arc: B3 H00R0000
arc: B4 V02N0501
arc: B6 S1_V02N0701
arc: B7 S1_V02N0501
arc: E1_H01E0001 F3
arc: E1_H01E0101 F7
arc: E1_H02E0001 F0
arc: F0 F0_SLICE
arc: F1 F1_SLICE
arc: F2 F2_SLICE
arc: F3 F3_SLICE
arc: F4 F4_SLICE
arc: F5 F5_SLICE
arc: F6 F6_SLICE
arc: F7 F7_SLICE
arc: N1_V01N0001 F1
arc: N1_V01N0101 F0
arc: N1_V02N0001 F2
arc: N1_V02N0301 F3
arc: N1_V02N0401 F6
arc: N1_V02N0501 F5
arc: S1_V02S0201 F2
arc: S1_V02S0301 F1
arc: S1_V02S0501 F5
arc: S1_V02S0601 F6
arc: V01S0000 F7
arc: V01S0100 F4
word: SLICED.K1.INIT 1100110011000000
word: SLICED.K0.INIT 1100110011000000
word: SLICEC.K1.INIT 1010101010100000
word: SLICEC.K0.INIT 1100110011000000
word: SLICEB.K1.INIT 1100110011000000
word: SLICEB.K0.INIT 1100110011000000
word: SLICEA.K1.INIT 1100110011000000
word: SLICEA.K0.INIT 1100110011000000
enum: SLICED.MODE CCU2
enum: SLICED.CCU2.INJECT1_1 NO
enum: SLICED.A1MUX 1
enum: SLICED.C1MUX 1
enum: SLICED.D1MUX 1
enum: SLICED.MODE CCU2
enum: SLICED.CCU2.INJECT1_0 NO
enum: SLICED.A0MUX 1
enum: SLICED.C0MUX 1
enum: SLICED.D0MUX 1
enum: SLICEC.MODE CCU2
enum: SLICEC.CCU2.INJECT1_1 NO
enum: SLICEC.B1MUX 1
enum: SLICEC.C1MUX 1
enum: SLICEC.D1MUX 1
enum: SLICEC.MODE CCU2
enum: SLICEC.CCU2.INJECT1_0 NO
enum: SLICEC.A0MUX 1
enum: SLICEC.C0MUX 1
enum: SLICEC.D0MUX 1
enum: SLICEB.MODE CCU2
enum: SLICEB.CCU2.INJECT1_1 NO
enum: SLICEB.A1MUX 1
enum: SLICEB.C1MUX 1
enum: SLICEB.D1MUX 1
enum: SLICEB.MODE CCU2
enum: SLICEB.CCU2.INJECT1_0 NO
enum: SLICEB.A0MUX 1
enum: SLICEB.C0MUX 1
enum: SLICEB.D0MUX 1
enum: SLICEA.MODE CCU2
enum: SLICEA.CCU2.INJECT1_1 NO
enum: SLICEA.A1MUX 1
enum: SLICEA.C1MUX 1
enum: SLICEA.D1MUX 1
enum: SLICEA.MODE CCU2
enum: SLICEA.CCU2.INJECT1_0 NO
enum: SLICEA.A0MUX 1
enum: SLICEA.C0MUX 1
enum: SLICEA.D0MUX 1
.tile R18C23:PLC2
arc: N1_V02N0301 H01E0101
arc: S1_V02S0201 H01E0001
arc: B0 S1_V02N0101
arc: F0 F0_SLICE
arc: N1_V01N0001 F0
arc: S1_V02S0001 F0
arc: W3_H06W0003 F0
word: SLICEB.K1.INIT 0000000000001110
word: SLICEB.K0.INIT 0000000000000000
word: SLICEA.K1.INIT 0000000000000000
word: SLICEA.K0.INIT 1100110011000000
enum: SLICEB.MODE CCU2
enum: SLICEB.CCU2.INJECT1_1 NO
enum: SLICEB.A1MUX 1
enum: SLICEB.B1MUX 1
enum: SLICEB.C1MUX 1
enum: SLICEB.D1MUX 1
enum: SLICEB.MODE CCU2
enum: SLICEB.CCU2.INJECT1_0 NO
enum: SLICEB.A0MUX 1
enum: SLICEB.B0MUX 1
enum: SLICEB.C0MUX 1
enum: SLICEB.D0MUX 1
enum: SLICEA.MODE CCU2
enum: SLICEA.CCU2.INJECT1_1 NO
enum: SLICEA.A1MUX 1
enum: SLICEA.B1MUX 1
enum: SLICEA.C1MUX 1
enum: SLICEA.D1MUX 1
enum: SLICEA.MODE CCU2
enum: SLICEA.CCU2.INJECT1_0 NO
enum: SLICEA.A0MUX 1
enum: SLICEA.C0MUX 1
enum: SLICEA.D0MUX 1
.tile R18C24:PLC2
arc: S1_V02S0001 W1_H02E0001
.tile R18C64:PLC2
arc: H00R0000 V02N0601
arc: V00T0000 V02N0401
arc: A0 S1_V02N0701
arc: B2 V01N0001
arc: B3 V02N0101
arc: B4 H00R0000
arc: B5 V02N0701
arc: B6 V00T0000
arc: B7 V02N0501
word: SLICED.K1.INIT 1001100110011100
word: SLICED.K0.INIT 1001100110011100
word: SLICEC.K1.INIT 1001100110011100
word: SLICEC.K0.INIT 1001100110011100
word: SLICEB.K1.INIT 1001100110011100
word: SLICEB.K0.INIT 1001100110011100
word: SLICEA.K1.INIT 1111111111111111
word: SLICEA.K0.INIT 0000000000001010
enum: SLICED.MODE CCU2
enum: SLICED.CCU2.INJECT1_1 NO
enum: SLICED.A1MUX 1
enum: SLICED.C1MUX 1
enum: SLICED.D1MUX 1
enum: SLICED.MODE CCU2
enum: SLICED.CCU2.INJECT1_0 NO
enum: SLICED.A0MUX 1
enum: SLICED.C0MUX 1
enum: SLICED.D0MUX 1
enum: SLICEC.MODE CCU2
enum: SLICEC.CCU2.INJECT1_1 NO
enum: SLICEC.A1MUX 1
enum: SLICEC.C1MUX 1
enum: SLICEC.D1MUX 1
enum: SLICEC.MODE CCU2
enum: SLICEC.CCU2.INJECT1_0 NO
enum: SLICEC.A0MUX 1
enum: SLICEC.C0MUX 1
enum: SLICEC.D0MUX 1
enum: SLICEB.MODE CCU2
enum: SLICEB.CCU2.INJECT1_1 NO
enum: SLICEB.A1MUX 1
enum: SLICEB.C1MUX 1
enum: SLICEB.D1MUX 1
enum: SLICEB.MODE CCU2
enum: SLICEB.CCU2.INJECT1_0 NO
enum: SLICEB.A0MUX 1
enum: SLICEB.C0MUX 1
enum: SLICEB.D0MUX 1
enum: SLICEA.MODE CCU2
enum: SLICEA.CCU2.INJECT1_1 YES
enum: SLICEA.A1MUX 1
enum: SLICEA.B1MUX 1
enum: SLICEA.C1MUX 1
enum: SLICEA.D1MUX 1
enum: SLICEA.MODE CCU2
enum: SLICEA.CCU2.INJECT1_0 NO
enum: SLICEA.B0MUX 1
enum: SLICEA.C0MUX 1
enum: SLICEA.D0MUX 1
.tile R18C65:PLC2
arc: V00T0000 V02N0401
arc: A2 V01N0101
arc: B0 V01N0001
arc: B1 V02N0101
arc: B3 V02N0301
arc: B4 S1_V02N0701
arc: B5 V02N0501
arc: B6 V00T0000
arc: B7 V02N0701
word: SLICED.K1.INIT 0011001100111100
word: SLICED.K0.INIT 0011001100111100
word: SLICEC.K1.INIT 0011001100111100
word: SLICEC.K0.INIT 0011001100111100
word: SLICEB.K1.INIT 0011001100111100
word: SLICEB.K0.INIT 0101010101011010
word: SLICEA.K1.INIT 0011001100111100
word: SLICEA.K0.INIT 1001100110011100
enum: SLICED.MODE CCU2
enum: SLICED.CCU2.INJECT1_1 NO
enum: SLICED.A1MUX 1
enum: SLICED.C1MUX 1
enum: SLICED.D1MUX 1
enum: SLICED.MODE CCU2
enum: SLICED.CCU2.INJECT1_0 NO
enum: SLICED.A0MUX 1
enum: SLICED.C0MUX 1
enum: SLICED.D0MUX 1
enum: SLICEC.MODE CCU2
enum: SLICEC.CCU2.INJECT1_1 NO
enum: SLICEC.A1MUX 1
enum: SLICEC.C1MUX 1
enum: SLICEC.D1MUX 1
enum: SLICEC.MODE CCU2
enum: SLICEC.CCU2.INJECT1_0 NO
enum: SLICEC.A0MUX 1
enum: SLICEC.C0MUX 1
enum: SLICEC.D0MUX 1
enum: SLICEB.MODE CCU2
enum: SLICEB.CCU2.INJECT1_1 NO
enum: SLICEB.A1MUX 1
enum: SLICEB.C1MUX 1
enum: SLICEB.D1MUX 1
enum: SLICEB.MODE CCU2
enum: SLICEB.CCU2.INJECT1_0 NO
enum: SLICEB.B0MUX 1
enum: SLICEB.C0MUX 1
enum: SLICEB.D0MUX 1
enum: SLICEA.MODE CCU2
enum: SLICEA.CCU2.INJECT1_1 NO
enum: SLICEA.A1MUX 1
enum: SLICEA.C1MUX 1
enum: SLICEA.D1MUX 1
enum: SLICEA.MODE CCU2
enum: SLICEA.CCU2.INJECT1_0 NO
enum: SLICEA.A0MUX 1
enum: SLICEA.C0MUX 1
enum: SLICEA.D0MUX 1
.tile R18C66:PLC2
arc: V00T0000 V02N0401
arc: A2 V01N0101
arc: A4 V00T0000
arc: B0 V01N0001
arc: B1 V02N0101
arc: B3 V02N0301
arc: B5 V02N0501
arc: B6 S1_V02N0501
arc: B7 V02N0701
word: SLICED.K1.INIT 0011001100111100
word: SLICED.K0.INIT 0011001100111100
word: SLICEC.K1.INIT 0011001100111100
word: SLICEC.K0.INIT 0101010101011010
word: SLICEB.K1.INIT 0011001100111100
word: SLICEB.K0.INIT 0101010101011010
word: SLICEA.K1.INIT 0011001100111100
word: SLICEA.K0.INIT 0011001100111100
enum: SLICED.MODE CCU2
enum: SLICED.CCU2.INJECT1_1 NO
enum: SLICED.A1MUX 1
enum: SLICED.C1MUX 1
enum: SLICED.D1MUX 1
enum: SLICED.MODE CCU2
enum: SLICED.CCU2.INJECT1_0 NO
enum: SLICED.A0MUX 1
enum: SLICED.C0MUX 1
enum: SLICED.D0MUX 1
enum: SLICEC.MODE CCU2
enum: SLICEC.CCU2.INJECT1_1 NO
enum: SLICEC.A1MUX 1
enum: SLICEC.C1MUX 1
enum: SLICEC.D1MUX 1
enum: SLICEC.MODE CCU2
enum: SLICEC.CCU2.INJECT1_0 NO
enum: SLICEC.B0MUX 1
enum: SLICEC.C0MUX 1
enum: SLICEC.D0MUX 1
enum: SLICEB.MODE CCU2
enum: SLICEB.CCU2.INJECT1_1 NO
enum: SLICEB.A1MUX 1
enum: SLICEB.C1MUX 1
enum: SLICEB.D1MUX 1
enum: SLICEB.MODE CCU2
enum: SLICEB.CCU2.INJECT1_0 NO
enum: SLICEB.B0MUX 1
enum: SLICEB.C0MUX 1
enum: SLICEB.D0MUX 1
enum: SLICEA.MODE CCU2
enum: SLICEA.CCU2.INJECT1_1 NO
enum: SLICEA.A1MUX 1
enum: SLICEA.C1MUX 1
enum: SLICEA.D1MUX 1
enum: SLICEA.MODE CCU2
enum: SLICEA.CCU2.INJECT1_0 NO
enum: SLICEA.A0MUX 1
enum: SLICEA.C0MUX 1
enum: SLICEA.D0MUX 1
.tile R18C67:PLC2
arc: V00T0000 V02N0401
arc: A2 V01N0101
arc: A4 V00T0000
arc: B0 V01N0001
arc: B1 V02N0301
arc: B3 V02N0101
arc: B5 V02N0701
arc: B6 S1_V02N0701
arc: B7 V02N0501
word: SLICED.K1.INIT 0011001100111100
word: SLICED.K0.INIT 0011001100111100
word: SLICEC.K1.INIT 0011001100111100
word: SLICEC.K0.INIT 0101010101011010
word: SLICEB.K1.INIT 0011001100111100
word: SLICEB.K0.INIT 0101010101011010
word: SLICEA.K1.INIT 0011001100111100
word: SLICEA.K0.INIT 0011001100111100
enum: SLICED.MODE CCU2
enum: SLICED.CCU2.INJECT1_1 NO
enum: SLICED.A1MUX 1
enum: SLICED.C1MUX 1
enum: SLICED.D1MUX 1
enum: SLICED.MODE CCU2
enum: SLICED.CCU2.INJECT1_0 NO
enum: SLICED.A0MUX 1
enum: SLICED.C0MUX 1
enum: SLICED.D0MUX 1
enum: SLICEC.MODE CCU2
enum: SLICEC.CCU2.INJECT1_1 NO
enum: SLICEC.A1MUX 1
enum: SLICEC.C1MUX 1
enum: SLICEC.D1MUX 1
enum: SLICEC.MODE CCU2
enum: SLICEC.CCU2.INJECT1_0 NO
enum: SLICEC.B0MUX 1
enum: SLICEC.C0MUX 1
enum: SLICEC.D0MUX 1
enum: SLICEB.MODE CCU2
enum: SLICEB.CCU2.INJECT1_1 NO
enum: SLICEB.A1MUX 1
enum: SLICEB.C1MUX 1
enum: SLICEB.D1MUX 1
enum: SLICEB.MODE CCU2
enum: SLICEB.CCU2.INJECT1_0 NO
enum: SLICEB.B0MUX 1
enum: SLICEB.C0MUX 1
enum: SLICEB.D0MUX 1
enum: SLICEA.MODE CCU2
enum: SLICEA.CCU2.INJECT1_1 NO
enum: SLICEA.A1MUX 1
enum: SLICEA.C1MUX 1
enum: SLICEA.D1MUX 1
enum: SLICEA.MODE CCU2
enum: SLICEA.CCU2.INJECT1_0 NO
enum: SLICEA.A0MUX 1
enum: SLICEA.C0MUX 1
enum: SLICEA.D0MUX 1
.tile R18C68:PLC2
arc: F0 F0_SLICE
arc: S1_V02S0201 F0
word: SLICEA.K1.INIT 0000000000001110
word: SLICEA.K0.INIT 0000000000000000
enum: SLICEA.MODE CCU2
enum: SLICEA.CCU2.INJECT1_1 NO
enum: SLICEA.A1MUX 1
enum: SLICEA.B1MUX 1
enum: SLICEA.C1MUX 1
enum: SLICEA.D1MUX 1
enum: SLICEA.MODE CCU2
enum: SLICEA.CCU2.INJECT1_0 NO
enum: SLICEA.A0MUX 1
enum: SLICEA.B0MUX 1
enum: SLICEA.C0MUX 1
enum: SLICEA.D0MUX 1
.tile R19C11:PLC2
arc: W1_H02W0501 E3_H06W0303
arc: W3_H06W0103 E3_H06W0003
.tile R19C16:PLC2
arc: E1_H02E0501 E1_H01W0100
.tile R19C17:PLC2
arc: E1_H02E0201 N1_V02S0201
arc: E1_H02E0501 E3_H06W0303
arc: H00R0000 H02W0401
arc: H01W0100 E3_H06W0303
arc: N1_V02N0201 E1_H01W0000
arc: N1_V02N0501 E3_H06W0303
arc: N1_V02N0601 E3_H06W0303
arc: S1_V02S0201 N1_V02S0201
arc: S1_V02S0401 E1_H01W0000
arc: S1_V02S0601 E3_H06W0303
arc: W3_H06W0303 E1_H01W0100
arc: B0 V02S0301
arc: C0 E1_H02W0401
arc: CE0 H00R0000
arc: CLK0 G_HPBX0000
arc: D0 N1_V02S0201
arc: F0 F0_SLICE
arc: LSR1 H02E0501
arc: MUXCLK0 CLK0
arc: MUXLSR0 LSR1
arc: W3_H06W0003 Q0
word: SLICEA.K0.INIT 0011000000110011
enum: SLICEA.GSR DISABLED
enum: SLICEA.REG0.SD 1
enum: SLICEA.REG0.REGSET RESET
enum: SLICEA.REG0.LSRMODE LSR
enum: SLICEA.CEMUX CE
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEA.MODE LOGIC
enum: SLICEA.CCU2.INJECT1_0 _NONE_
enum: SLICEA.A0MUX 1
.tile R19C18:PLC2
arc: E1_H02E0301 S1_V02N0301
arc: A0 H02W0701
arc: C0 V02S0601
arc: C4 S1_V02N0201
arc: CE0 H00R0000
arc: CLK0 G_HPBX0000
arc: D0 H02E0201
arc: D4 S1_V02N0601
arc: F0 F0_SLICE
arc: F4 F4_SLICE
arc: H00R0000 F4
arc: H01W0000 F4
arc: H01W0100 Q0
arc: LSR0 H02E0501
arc: MUXCLK0 CLK0
arc: MUXLSR0 LSR0
arc: N1_V02N0601 F4
arc: W1_H02W0401 F4
word: SLICEC.K0.INIT 1111000000000000
word: SLICEA.K0.INIT 0000101000001111
enum: SLICEC.MODE LOGIC
enum: SLICEC.CCU2.INJECT1_0 _NONE_
enum: SLICEC.A0MUX 1
enum: SLICEC.B0MUX 1
enum: SLICEA.GSR DISABLED
enum: SLICEA.REG0.SD 1
enum: SLICEA.REG0.REGSET RESET
enum: SLICEA.REG0.LSRMODE LSR
enum: SLICEA.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEA.MODE LOGIC
enum: SLICEA.CCU2.INJECT1_0 _NONE_
enum: SLICEA.B0MUX 1
.tile R19C19:PLC2
arc: E1_H02E0101 S1_V02N0101
arc: E1_H02E0201 S1_V02N0201
arc: H00L0000 S1_V02N0001
arc: N1_V02N0101 V01N0101
arc: N1_V02N0301 H02E0301
arc: N1_V02N0701 N1_V01S0100
arc: S1_V02S0501 W1_H02E0501
arc: V00B0100 S1_V02N0301
arc: W1_H02W0401 N1_V01S0000
arc: W1_H02W0701 V02S0701
arc: A0 V02S0701
arc: B1 S1_V02N0101
arc: B2 V02N0101
arc: B4 N1_V01S0000
arc: C0 V02N0401
arc: C1 E1_H02W0601
arc: C4 S1_V02N0201
arc: CE0 H00L0000
arc: CE1 H00L0000
arc: CE2 H00L0000
arc: CLK0 G_HPBX0000
arc: D0 S1_V02N0201
arc: D1 E1_H02W0001
arc: D2 S1_V02N0201
arc: D4 V02N0601
arc: F0 F0_SLICE
arc: F1 F1_SLICE
arc: F2 F2_SLICE
arc: F4 F4_SLICE
arc: LSR1 V00B0100
arc: MUXCLK0 CLK0
arc: MUXCLK1 CLK0
arc: MUXCLK2 CLK0
arc: MUXLSR0 LSR1
arc: MUXLSR1 LSR1
arc: MUXLSR2 LSR1
arc: S1_V02S0001 Q2
arc: S1_V02S0101 Q1
arc: V01S0000 Q4
arc: V01S0100 Q0
word: SLICEB.K0.INIT 0011001111001100
word: SLICEA.K0.INIT 1010101011110000
word: SLICEC.K0.INIT 1100111111000000
word: SLICEA.K1.INIT 1111001111000000
enum: SLICEA.GSR DISABLED
enum: SLICEA.REG1.SD 1
enum: SLICEA.REG1.REGSET RESET
enum: SLICEA.REG1.LSRMODE LSR
enum: SLICEA.CEMUX CE
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEA.GSR DISABLED
enum: SLICEA.REG0.SD 1
enum: SLICEA.REG0.REGSET RESET
enum: SLICEA.REG0.LSRMODE LSR
enum: SLICEA.CEMUX CE
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEB.MODE LOGIC
enum: SLICEB.CCU2.INJECT1_0 _NONE_
enum: SLICEB.A0MUX 1
enum: SLICEB.C0MUX 1
enum: SLICEA.MODE LOGIC
enum: SLICEA.CCU2.INJECT1_0 _NONE_
enum: SLICEA.B0MUX 1
enum: SLICEC.MODE LOGIC
enum: SLICEC.CCU2.INJECT1_0 _NONE_
enum: SLICEC.A0MUX 1
enum: SLICEA.MODE LOGIC
enum: SLICEA.CCU2.INJECT1_1 _NONE_
enum: SLICEA.A1MUX 1
enum: SLICEC.GSR DISABLED
enum: SLICEC.REG0.SD 1
enum: SLICEC.REG0.REGSET RESET
enum: SLICEC.REG0.LSRMODE LSR
enum: SLICEC.CEMUX CE
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEB.GSR DISABLED
enum: SLICEB.REG0.SD 1
enum: SLICEB.REG0.REGSET RESET
enum: SLICEB.REG0.LSRMODE LSR
enum: SLICEB.CEMUX CE
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
.tile R19C20:PLC2
arc: E1_H02E0101 V02N0101
arc: E1_H02E0401 S1_V02N0401
arc: E1_H02E0501 V02N0501
arc: E1_H02E0601 N1_V01S0000
arc: H00L0000 S1_V02N0001
arc: H00L0100 S1_V02N0101
arc: N1_V02N0501 N1_V01S0100
arc: N1_V02N0701 V01N0101
arc: S1_V02S0501 E1_H01W0100
arc: V00T0000 S1_V02N0401
arc: A0 H02W0501
arc: A2 V02S0501
arc: A4 V02N0301
arc: A7 V02S0301
arc: B1 V02S0101
arc: B5 V02S0701
arc: B6 H02E0101
arc: B7 H02E0101
arc: C0 H02W0401
arc: C1 H00L0100
arc: C2 V02N0601
arc: C4 V02S0201
arc: C5 V02N0201
arc: C6 V01N0101
arc: CE0 H00L0000
arc: CE1 H00L0000
arc: CE2 H00L0000
arc: CE3 H00L0000
arc: CLK0 G_HPBX0000
arc: D0 H02E0201
arc: D1 V02N0001
arc: D2 H02E0201
arc: D4 H02E0201
arc: D5 H02E0201
arc: D6 V02S0601
arc: D7 V01N0001
arc: E1_H01E0101 Q0
arc: F0 F0_SLICE
arc: F1 F1_SLICE
arc: F2 F2_SLICE
arc: F4 F4_SLICE
arc: F5 F5_SLICE
arc: F6 F6_SLICE
arc: F7 F7_SLICE
arc: LSR0 V00T0000
arc: LSR1 V00T0000
arc: MUXCLK0 CLK0
arc: MUXCLK1 CLK0
arc: MUXCLK2 CLK0
arc: MUXCLK3 CLK0
arc: MUXLSR0 LSR0
arc: MUXLSR1 LSR1
arc: MUXLSR2 LSR0
arc: MUXLSR3 LSR1
arc: S1_V02S0001 Q2
arc: S1_V02S0301 Q1
arc: S1_V02S0401 Q4
arc: S1_V02S0601 Q6
arc: V01S0000 Q7
arc: V01S0100 Q5
word: SLICEA.K1.INIT 1100111111000000
word: SLICEA.K0.INIT 1111000010101010
word: SLICEC.K1.INIT 1100110011110000
word: SLICEB.K0.INIT 1010101011110000
word: SLICED.K0.INIT 1111110000110000
word: SLICED.K1.INIT 1011101110001000
word: SLICEC.K0.INIT 1111000010101010
enum: SLICED.GSR DISABLED
enum: SLICED.REG0.SD 1
enum: SLICED.REG0.REGSET RESET
enum: SLICED.REG0.LSRMODE LSR
enum: SLICED.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICED.GSR DISABLED
enum: SLICED.REG1.SD 1
enum: SLICED.REG1.REGSET RESET
enum: SLICED.REG1.LSRMODE LSR
enum: SLICED.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEC.GSR DISABLED
enum: SLICEC.REG0.SD 1
enum: SLICEC.REG0.REGSET RESET
enum: SLICEC.REG0.LSRMODE LSR
enum: SLICEC.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEA.GSR DISABLED
enum: SLICEA.REG1.SD 1
enum: SLICEA.REG1.REGSET RESET
enum: SLICEA.REG1.LSRMODE LSR
enum: SLICEA.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEA.GSR DISABLED
enum: SLICEA.REG0.SD 1
enum: SLICEA.REG0.REGSET RESET
enum: SLICEA.REG0.LSRMODE LSR
enum: SLICEA.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEA.MODE LOGIC
enum: SLICEA.CCU2.INJECT1_1 _NONE_
enum: SLICEA.A1MUX 1
enum: SLICEC.GSR DISABLED
enum: SLICEC.REG1.SD 1
enum: SLICEC.REG1.REGSET RESET
enum: SLICEC.REG1.LSRMODE LSR
enum: SLICEC.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEB.GSR DISABLED
enum: SLICEB.REG0.SD 1
enum: SLICEB.REG0.REGSET RESET
enum: SLICEB.REG0.LSRMODE LSR
enum: SLICEB.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEA.MODE LOGIC
enum: SLICEA.CCU2.INJECT1_0 _NONE_
enum: SLICEA.B0MUX 1
enum: SLICEC.MODE LOGIC
enum: SLICEC.CCU2.INJECT1_1 _NONE_
enum: SLICEC.A1MUX 1
enum: SLICEB.MODE LOGIC
enum: SLICEB.CCU2.INJECT1_0 _NONE_
enum: SLICEB.B0MUX 1
enum: SLICED.MODE LOGIC
enum: SLICED.CCU2.INJECT1_0 _NONE_
enum: SLICED.A0MUX 1
enum: SLICED.MODE LOGIC
enum: SLICED.CCU2.INJECT1_1 _NONE_
enum: SLICED.C1MUX 1
enum: SLICEC.MODE LOGIC
enum: SLICEC.CCU2.INJECT1_0 _NONE_
enum: SLICEC.B0MUX 1
.tile R19C21:PLC2
arc: E1_H02E0101 V02N0101
arc: H00L0000 S1_V02N0001
arc: H00L0100 S1_V02N0101
arc: N1_V02N0501 V01N0101
arc: N1_V02N0701 N1_V01S0100
arc: S1_V02S0301 H01E0101
arc: S1_V02S0501 E1_H01W0100
arc: V00B0000 H02E0401
arc: V00T0100 W1_H02E0101
arc: W1_H02W0001 V01N0001
arc: W1_H02W0401 V02S0401
arc: W1_H02W0501 V02N0501
arc: W1_H02W0601 N1_V01S0000
arc: A6 N1_V01S0100
arc: A7 H02E0501
arc: B0 V02S0101
arc: B1 V02N0301
arc: B4 H02E0101
arc: B5 V02S0501
arc: C0 H00L0100
arc: C1 S1_V02N0401
arc: C4 V02S0001
arc: C5 V00T0100
arc: C6 V01N0101
arc: C7 H02E0601
arc: CE0 H00L0000
arc: CE2 H00L0000
arc: CE3 H00L0000
arc: CLK0 G_HPBX0000
arc: D0 V02N0201
arc: D1 V02S0201
arc: D4 W1_H02E0201
arc: D5 V02N0401
arc: D6 W1_H02E0201
arc: D7 W1_H02E0201
arc: F0 F0_SLICE
arc: F1 F1_SLICE
arc: F4 F4_SLICE
arc: F5 F5_SLICE
arc: F6 F6_SLICE
arc: F7 F7_SLICE
arc: H01W0100 Q4
arc: LSR0 V00B0000
arc: LSR1 V00B0000
arc: MUXCLK0 CLK0
arc: MUXCLK2 CLK0
arc: MUXCLK3 CLK0
arc: MUXLSR0 LSR0
arc: MUXLSR2 LSR1
arc: MUXLSR3 LSR1
arc: S1_V02S0101 Q1
arc: S1_V02S0201 Q0
arc: S1_V02S0701 Q5
arc: V01S0000 Q6
arc: V01S0100 Q7
word: SLICEC.K0.INIT 1111000011001100
word: SLICEC.K1.INIT 1100111111000000
word: SLICED.K0.INIT 1010101011110000
word: SLICEA.K0.INIT 1100111111000000
word: SLICEA.K1.INIT 1111110000001100
word: SLICED.K1.INIT 1111000010101010
enum: SLICED.GSR DISABLED
enum: SLICED.REG1.SD 1
enum: SLICED.REG1.REGSET RESET
enum: SLICED.REG1.LSRMODE LSR
enum: SLICED.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEC.GSR DISABLED
enum: SLICEC.REG0.SD 1
enum: SLICEC.REG0.REGSET RESET
enum: SLICEC.REG0.LSRMODE LSR
enum: SLICEC.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEC.GSR DISABLED
enum: SLICEC.REG1.SD 1
enum: SLICEC.REG1.REGSET RESET
enum: SLICEC.REG1.LSRMODE LSR
enum: SLICEC.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICED.GSR DISABLED
enum: SLICED.REG0.SD 1
enum: SLICED.REG0.REGSET RESET
enum: SLICED.REG0.LSRMODE LSR
enum: SLICED.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEC.MODE LOGIC
enum: SLICEC.CCU2.INJECT1_0 _NONE_
enum: SLICEC.A0MUX 1
enum: SLICEA.GSR DISABLED
enum: SLICEA.REG0.SD 1
enum: SLICEA.REG0.REGSET RESET
enum: SLICEA.REG0.LSRMODE LSR
enum: SLICEA.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEA.GSR DISABLED
enum: SLICEA.REG1.SD 1
enum: SLICEA.REG1.REGSET RESET
enum: SLICEA.REG1.LSRMODE LSR
enum: SLICEA.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEC.MODE LOGIC
enum: SLICEC.CCU2.INJECT1_1 _NONE_
enum: SLICEC.A1MUX 1
enum: SLICED.MODE LOGIC
enum: SLICED.CCU2.INJECT1_0 _NONE_
enum: SLICED.B0MUX 1
enum: SLICEA.MODE LOGIC
enum: SLICEA.CCU2.INJECT1_0 _NONE_
enum: SLICEA.A0MUX 1
enum: SLICEA.MODE LOGIC
enum: SLICEA.CCU2.INJECT1_1 _NONE_
enum: SLICEA.A1MUX 1
enum: SLICED.MODE LOGIC
enum: SLICED.CCU2.INJECT1_1 _NONE_
enum: SLICED.B1MUX 1
.tile R19C22:PLC2
arc: E1_H02E0001 N1_V01S0000
arc: E1_H02E0301 S1_V02N0301
arc: E1_H02E0501 V02S0501
arc: E1_H02E0601 S1_V02N0601
arc: H00R0000 S1_V02N0601
arc: N1_V02N0501 V01N0101
arc: N1_V02N0701 N1_V01S0100
arc: S1_V02S0501 E1_H01W0100
arc: V00B0000 S1_V02N0201
arc: V00B0100 S1_V02N0301
arc: A0 V01N0101
arc: A1 V02S0701
arc: A4 V02N0301
arc: A5 V02S0301
arc: B2 V01N0001
arc: B6 H02E0101
arc: C0 N1_V01S0100
arc: C1 E1_H02W0401
arc: C2 V02S0601
arc: C4 V02S0201
arc: C5 S1_V02N0201
arc: C6 S1_V02N0201
arc: CE0 H00R0000
arc: CE1 H00R0000
arc: CE2 S1_V02N0601
arc: CE3 S1_V02N0601
arc: CLK0 G_HPBX0000
arc: D0 S1_V02N0201
arc: D1 V02N0201
arc: D2 S1_V02N0201
arc: D4 V00B0000
arc: D5 S1_V02N0401
arc: D6 V02S0401
arc: F0 F0_SLICE
arc: F1 F1_SLICE
arc: F2 F2_SLICE
arc: F4 F4_SLICE
arc: F5 F5_SLICE
arc: F6 F6_SLICE
arc: H01W0100 Q6
arc: LSR1 V00B0100
arc: MUXCLK0 CLK0
arc: MUXCLK1 CLK0
arc: MUXCLK2 CLK0
arc: MUXCLK3 CLK0
arc: MUXLSR0 LSR1
arc: MUXLSR1 LSR1
arc: MUXLSR2 LSR1
arc: MUXLSR3 LSR1
arc: S1_V02S0101 Q1
arc: S1_V02S0401 Q4
arc: S1_V02S0701 Q5
arc: V01S0000 Q0
arc: V01S0100 Q2
word: SLICEB.K0.INIT 1111000011001100
word: SLICEA.K0.INIT 1111000010101010
word: SLICEC.K0.INIT 1111000010101010
word: SLICEC.K1.INIT 1010111110100000
word: SLICEA.K1.INIT 1010111110100000
word: SLICED.K0.INIT 1111110000001100
enum: SLICEA.GSR DISABLED
enum: SLICEA.REG0.SD 1
enum: SLICEA.REG0.REGSET RESET
enum: SLICEA.REG0.LSRMODE LSR
enum: SLICEA.CEMUX CE
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEC.GSR DISABLED
enum: SLICEC.REG0.SD 1
enum: SLICEC.REG0.REGSET RESET
enum: SLICEC.REG0.LSRMODE LSR
enum: SLICEC.CEMUX CE
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEC.GSR DISABLED
enum: SLICEC.REG1.SD 1
enum: SLICEC.REG1.REGSET RESET
enum: SLICEC.REG1.LSRMODE LSR
enum: SLICEC.CEMUX CE
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEA.GSR DISABLED
enum: SLICEA.REG1.SD 1
enum: SLICEA.REG1.REGSET RESET
enum: SLICEA.REG1.LSRMODE LSR
enum: SLICEA.CEMUX CE
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEB.MODE LOGIC
enum: SLICEB.CCU2.INJECT1_0 _NONE_
enum: SLICEB.A0MUX 1
enum: SLICED.GSR DISABLED
enum: SLICED.REG0.SD 1
enum: SLICED.REG0.REGSET RESET
enum: SLICED.REG0.LSRMODE LSR
enum: SLICED.CEMUX CE
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEB.GSR DISABLED
enum: SLICEB.REG0.SD 1
enum: SLICEB.REG0.REGSET RESET
enum: SLICEB.REG0.LSRMODE LSR
enum: SLICEB.CEMUX CE
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEA.MODE LOGIC
enum: SLICEA.CCU2.INJECT1_0 _NONE_
enum: SLICEA.B0MUX 1
enum: SLICEC.MODE LOGIC
enum: SLICEC.CCU2.INJECT1_0 _NONE_
enum: SLICEC.B0MUX 1
enum: SLICEC.MODE LOGIC
enum: SLICEC.CCU2.INJECT1_1 _NONE_
enum: SLICEC.B1MUX 1
enum: SLICEA.MODE LOGIC
enum: SLICEA.CCU2.INJECT1_1 _NONE_
enum: SLICEA.B1MUX 1
enum: SLICED.MODE LOGIC
enum: SLICED.CCU2.INJECT1_0 _NONE_
enum: SLICED.A0MUX 1
.tile R19C23:PLC2
arc: H00R0000 H02E0601
arc: S1_V02S0501 E1_H01W0100
arc: V00B0100 H02E0501
arc: W3_H06W0303 E3_H06W0203
arc: A0 V02N0701
arc: B0 S1_V02N0101
arc: B1 S1_V02N0101
arc: C1 V02N0401
arc: CE0 H00R0000
arc: CLK0 G_HPBX0000
arc: D0 V02S0201
arc: D1 V00B0100
arc: F0 F0_SLICE
arc: F1 F1_SLICE
arc: H01W0100 Q0
arc: LSR1 H02E0301
arc: MUXCLK0 CLK0
arc: MUXLSR0 LSR1
arc: V01S0100 Q1
word: SLICEA.K1.INIT 1111110000110000
word: SLICEA.K0.INIT 1110111000100010
enum: SLICEA.GSR DISABLED
enum: SLICEA.REG0.SD 1
enum: SLICEA.REG0.REGSET RESET
enum: SLICEA.REG0.LSRMODE LSR
enum: SLICEA.CEMUX CE
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEA.MODE LOGIC
enum: SLICEA.CCU2.INJECT1_1 _NONE_
enum: SLICEA.A1MUX 1
enum: SLICEA.GSR DISABLED
enum: SLICEA.REG1.SD 1
enum: SLICEA.REG1.REGSET RESET
enum: SLICEA.REG1.LSRMODE LSR
enum: SLICEA.CEMUX CE
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEA.MODE LOGIC
enum: SLICEA.CCU2.INJECT1_0 _NONE_
enum: SLICEA.C0MUX 1
.tile R19C24:PLC2
arc: H00L0100 S1_V02N0301
arc: W1_H02W0401 S1_V02N0401
arc: B1 S1_V02N0101
arc: C1 V02N0401
arc: CE0 H00L0100
arc: CLK0 G_HPBX0000
arc: D1 W1_H02E0001
arc: F1 F1_SLICE
arc: H01W0100 Q1
arc: LSR1 W1_H02E0301
arc: MUXCLK0 CLK0
arc: MUXLSR0 LSR1
word: SLICEA.K1.INIT 1111110000110000
enum: SLICEA.MODE LOGIC
enum: SLICEA.CCU2.INJECT1_1 _NONE_
enum: SLICEA.A1MUX 1
enum: SLICEA.GSR DISABLED
enum: SLICEA.REG1.SD 1
enum: SLICEA.REG1.REGSET RESET
enum: SLICEA.REG1.LSRMODE LSR
enum: SLICEA.CEMUX CE
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
.tile R19C26:PLC2
arc: S1_V02S0401 H06W0203
.tile R19C29:PLC2
arc: W3_H06W0203 E3_H06W0203
.tile R19C35:PLC2
arc: W3_H06W0203 E3_H06W0203
.tile R19C39:PLC2
arc: N3_V06N0203 H06W0203
.tile R19C3:PLC2
arc: S3_V06S0303 E3_H06W0303
.tile R19C41:PLC2
arc: W3_H06W0203 E3_H06W0203
.tile R19C42:PLC2
arc: W3_H06W0203 E3_H06W0103
.tile R19C47:PLC2
arc: S3_V06S0103 E3_H06W0103
arc: W3_H06W0203 E3_H06W0103
.tile R19C48:PLC2
arc: W3_H06W0103 E3_H06W0103
.tile R19C4:PLC2
arc: W3_H06W0203 E1_H01W0000
.tile R19C50:PLC2
arc: S3_V06S0103 H06W0103
.tile R19C53:PLC2
arc: S3_V06S0103 E3_H06W0103
arc: W3_H06W0103 E3_H06W0103
.tile R19C54:PLC2
arc: W3_H06W0103 E3_H06W0103
.tile R19C59:PLC2
arc: W3_H06W0103 E3_H06W0103
.tile R19C5:PLC2
arc: H01W0000 E3_H06W0103
.tile R19C60:PLC2
arc: W3_H06W0103 E3_H06W0003
.tile R19C62:PLC2
arc: E1_H02E0001 S1_V02N0001
arc: E1_H02E0301 S1_V02N0301
arc: S1_V02S0201 H06W0103
arc: S3_V06S0103 H06W0103
.tile R19C63:PLC2
arc: E1_H02E0701 E1_H01W0100
arc: S1_V02S0301 E1_H02W0301
arc: V00T0100 H02E0301
arc: CE0 S1_V02N0201
arc: CLK0 G_HPBX0000
arc: LSR1 E1_H02W0301
arc: M0 V00T0100
arc: MUXCLK0 CLK0
arc: MUXLSR0 LSR1
arc: N3_V06N0003 Q0
enum: SLICEA.GSR DISABLED
enum: SLICEA.REG0.SD 0
enum: SLICEA.REG0.REGSET RESET
enum: SLICEA.REG0.LSRMODE LSR
enum: SLICEA.CEMUX CE
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
.tile R19C64:PLC2
arc: E1_H02E0101 W1_H02E0001
arc: E1_H02E0301 S1_V02N0301
arc: H00R0000 S1_V02N0401
arc: V00B0000 S1_V02N0001
arc: V00T0000 S1_V02N0601
arc: V00T0100 S1_V02N0701
arc: A2 V00B0000
arc: A3 H00L0100
arc: A4 H02E0701
arc: A5 V02N0101
arc: A6 N1_V01N0101
arc: A7 Q7
arc: B0 W1_H02E0301
arc: B2 H00L0000
arc: B3 S1_V02N0101
arc: B4 H00R0000
arc: B5 V00B0100
arc: B6 V00T0000
arc: B7 S1_V02N0501
arc: CE1 E1_H02W0101
arc: CE2 E1_H02W0101
arc: CE3 E1_H02W0101
arc: CLK0 G_HPBX0000
arc: E1_H01E0001 F4
arc: E1_H01E0101 F3
arc: E3_H06E0203 F7
arc: F2 F2_SLICE
arc: F3 F3_SLICE
arc: F4 F4_SLICE
arc: F5 F5_SLICE
arc: F6 F6_SLICE
arc: F7 F7_SLICE
arc: H00L0000 Q2
arc: H00L0100 Q3
arc: H01W0100 Q4
arc: LSR0 V00T0100
arc: LSR1 V00T0100
arc: MUXCLK1 CLK0
arc: MUXCLK2 CLK0
arc: MUXCLK3 CLK0
arc: MUXLSR1 LSR0
arc: MUXLSR2 LSR0
arc: MUXLSR3 LSR1
arc: N1_V01N0001 F2
arc: N1_V01N0101 Q6
arc: N1_V02N0101 F3
arc: N1_V02N0401 F6
arc: N1_V02N0501 F7
arc: N1_V02N0601 F4
arc: N1_V02N0701 F5
arc: S1_V02S0701 F5
arc: V00B0100 Q5
arc: V01S0000 F6
arc: V01S0100 F2
word: SLICED.K1.INIT 0110011001101010
word: SLICED.K0.INIT 0110011001101010
word: SLICEC.K1.INIT 0110011001101100
word: SLICEC.K0.INIT 0110011001101010
word: SLICEB.K1.INIT 0110011001101010
word: SLICEB.K0.INIT 0110011001101100
word: SLICEA.K1.INIT 1111111111111111
word: SLICEA.K0.INIT 0000000000001100
enum: SLICED.MODE CCU2
enum: SLICED.CCU2.INJECT1_1 NO
enum: SLICED.C1MUX 1
enum: SLICED.D1MUX 1
enum: SLICED.MODE CCU2
enum: SLICED.CCU2.INJECT1_0 NO
enum: SLICED.C0MUX 1
enum: SLICED.D0MUX 1
enum: SLICEC.MODE CCU2
enum: SLICEC.CCU2.INJECT1_1 NO
enum: SLICEC.C1MUX 1
enum: SLICEC.D1MUX 1
enum: SLICEC.MODE CCU2
enum: SLICEC.CCU2.INJECT1_0 NO
enum: SLICEC.C0MUX 1
enum: SLICEC.D0MUX 1
enum: SLICEB.MODE CCU2
enum: SLICEB.CCU2.INJECT1_1 NO
enum: SLICEB.C1MUX 1
enum: SLICEB.D1MUX 1
enum: SLICEB.MODE CCU2
enum: SLICEB.CCU2.INJECT1_0 NO
enum: SLICEB.C0MUX 1
enum: SLICEB.D0MUX 1
enum: SLICEA.MODE CCU2
enum: SLICEA.CCU2.INJECT1_1 YES
enum: SLICEA.A1MUX 1
enum: SLICEA.B1MUX 1
enum: SLICEA.C1MUX 1
enum: SLICEA.D1MUX 1
enum: SLICEA.MODE CCU2
enum: SLICEA.CCU2.INJECT1_0 NO
enum: SLICEA.A0MUX 1
enum: SLICEA.C0MUX 1
enum: SLICEA.D0MUX 1
enum: SLICEB.GSR DISABLED
enum: SLICEB.REG1.SD 1
enum: SLICEB.REG1.REGSET RESET
enum: SLICEB.REG1.LSRMODE LSR
enum: SLICEB.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEC.GSR DISABLED
enum: SLICEC.REG0.SD 1
enum: SLICEC.REG0.REGSET RESET
enum: SLICEC.REG0.LSRMODE LSR
enum: SLICEC.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICED.GSR DISABLED
enum: SLICED.REG1.SD 1
enum: SLICED.REG1.REGSET RESET
enum: SLICED.REG1.LSRMODE LSR
enum: SLICED.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEC.GSR DISABLED
enum: SLICEC.REG1.SD 1
enum: SLICEC.REG1.REGSET RESET
enum: SLICEC.REG1.LSRMODE LSR
enum: SLICEC.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEB.GSR DISABLED
enum: SLICEB.REG0.SD 1
enum: SLICEB.REG0.REGSET RESET
enum: SLICEB.REG0.LSRMODE LSR
enum: SLICEB.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICED.GSR DISABLED
enum: SLICED.REG0.SD 1
enum: SLICED.REG0.REGSET RESET
enum: SLICED.REG0.LSRMODE LSR
enum: SLICED.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
.tile R19C65:PLC2
arc: E1_H02E0501 E1_H01W0100
arc: E3_H06E0003 H01E0001
arc: E3_H06E0303 H01E0101
arc: H00R0000 S1_V02N0601
arc: S1_V02S0301 E3_H06W0003
arc: V00B0000 S1_V02N0001
arc: V00T0000 S1_V02N0401
arc: W1_H02W0301 E3_H06W0003
arc: W3_H06W0103 E3_H06W0003
arc: A0 V02N0501
arc: A1 H00L0100
arc: A2 V00B0000
arc: A3 E1_H01E0001
arc: A4 V00T0000
arc: A5 Q5
arc: A6 H00R0000
arc: A7 Q7
arc: B0 H01W0100
arc: B1 S1_V02N0101
arc: B2 H00L0000
arc: B3 S1_V02N0301
arc: B4 V01S0000
arc: B5 S1_V02N0701
arc: B6 H02W0301
arc: B7 S1_V02N0501
arc: CE0 H02E0101
arc: CE1 H02E0101
arc: CE2 H02E0101
arc: CE3 H02E0101
arc: CLK0 G_HPBX0000
arc: E1_H01E0001 Q3
arc: E1_H01E0101 Q6
arc: E1_H02E0201 F0
arc: F0 F0_SLICE
arc: F1 F1_SLICE
arc: F2 F2_SLICE
arc: F3 F3_SLICE
arc: F4 F4_SLICE
arc: F5 F5_SLICE
arc: F6 F6_SLICE
arc: F7 F7_SLICE
arc: H00L0000 Q2
arc: H00L0100 Q1
arc: H01W0100 Q0
arc: LSR0 H02E0301
arc: LSR1 H02E0301
arc: MUXCLK0 CLK0
arc: MUXCLK1 CLK0
arc: MUXCLK2 CLK0
arc: MUXCLK3 CLK0
arc: MUXLSR0 LSR1
arc: MUXLSR1 LSR1
arc: MUXLSR2 LSR0
arc: MUXLSR3 LSR1
arc: N1_V01N0001 F0
arc: N1_V01N0101 F2
arc: N1_V02N0101 F1
arc: N1_V02N0301 F3
arc: N1_V02N0401 F6
arc: N1_V02N0501 F5
arc: N1_V02N0701 F7
arc: V01S0000 Q4
arc: V01S0100 F4
word: SLICED.K1.INIT 0110011001101010
word: SLICED.K0.INIT 0110011001101100
word: SLICEC.K1.INIT 0110011001101010
word: SLICEC.K0.INIT 0110011001101100
word: SLICEB.K1.INIT 0110011001101010
word: SLICEB.K0.INIT 0110011001101100
word: SLICEA.K1.INIT 0110011001101010
word: SLICEA.K0.INIT 0110011001101100
enum: SLICED.MODE CCU2
enum: SLICED.CCU2.INJECT1_1 NO
enum: SLICED.C1MUX 1
enum: SLICED.D1MUX 1
enum: SLICED.MODE CCU2
enum: SLICED.CCU2.INJECT1_0 NO
enum: SLICED.C0MUX 1
enum: SLICED.D0MUX 1
enum: SLICEC.MODE CCU2
enum: SLICEC.CCU2.INJECT1_1 NO
enum: SLICEC.C1MUX 1
enum: SLICEC.D1MUX 1
enum: SLICEC.MODE CCU2
enum: SLICEC.CCU2.INJECT1_0 NO
enum: SLICEC.C0MUX 1
enum: SLICEC.D0MUX 1
enum: SLICEB.MODE CCU2
enum: SLICEB.CCU2.INJECT1_1 NO
enum: SLICEB.C1MUX 1
enum: SLICEB.D1MUX 1
enum: SLICEB.MODE CCU2
enum: SLICEB.CCU2.INJECT1_0 NO
enum: SLICEB.C0MUX 1
enum: SLICEB.D0MUX 1
enum: SLICEA.MODE CCU2
enum: SLICEA.CCU2.INJECT1_1 NO
enum: SLICEA.C1MUX 1
enum: SLICEA.D1MUX 1
enum: SLICEA.MODE CCU2
enum: SLICEA.CCU2.INJECT1_0 NO
enum: SLICEA.C0MUX 1
enum: SLICEA.D0MUX 1
enum: SLICED.GSR DISABLED
enum: SLICED.REG1.SD 1
enum: SLICED.REG1.REGSET RESET
enum: SLICED.REG1.LSRMODE LSR
enum: SLICED.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEC.GSR DISABLED
enum: SLICEC.REG1.SD 1
enum: SLICEC.REG1.REGSET RESET
enum: SLICEC.REG1.LSRMODE LSR
enum: SLICEC.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEC.GSR DISABLED
enum: SLICEC.REG0.SD 1
enum: SLICEC.REG0.REGSET RESET
enum: SLICEC.REG0.LSRMODE LSR
enum: SLICEC.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEB.GSR DISABLED
enum: SLICEB.REG1.SD 1
enum: SLICEB.REG1.REGSET RESET
enum: SLICEB.REG1.LSRMODE LSR
enum: SLICEB.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEB.GSR DISABLED
enum: SLICEB.REG0.SD 1
enum: SLICEB.REG0.REGSET RESET
enum: SLICEB.REG0.LSRMODE LSR
enum: SLICEB.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICED.GSR DISABLED
enum: SLICED.REG0.SD 1
enum: SLICED.REG0.REGSET RESET
enum: SLICED.REG0.LSRMODE LSR
enum: SLICED.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEA.GSR DISABLED
enum: SLICEA.REG1.SD 1
enum: SLICEA.REG1.REGSET RESET
enum: SLICEA.REG1.LSRMODE LSR
enum: SLICEA.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEA.GSR DISABLED
enum: SLICEA.REG0.SD 1
enum: SLICEA.REG0.REGSET RESET
enum: SLICEA.REG0.LSRMODE LSR
enum: SLICEA.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
.tile R19C66:PLC2
arc: H00L0000 S1_V02N0001
arc: V00B0000 S1_V02N0201
arc: V00T0000 H02W0001
arc: W1_H02W0101 E1_H02W0001
arc: W1_H02W0301 H01E0101
arc: W3_H06W0003 E3_H06W0003
arc: A0 E1_H01E0001
arc: A1 H00L0100
arc: A2 H02E0501
arc: A3 V00B0000
arc: A4 H02W0501
arc: A5 V00B0000
arc: A6 H00R0000
arc: A7 Q7
arc: B0 V02N0101
arc: B1 S1_V02N0301
arc: B2 H00L0000
arc: B3 Q3
arc: B4 H00L0000
arc: B5 V00B0100
arc: B6 V00B0000
arc: B7 V00B0000
arc: CE0 W1_H02E0101
arc: CE1 W1_H02E0101
arc: CE2 W1_H02E0101
arc: CE3 W1_H02E0101
arc: CLK0 G_HPBX0000
arc: E1_H01E0001 Q0
arc: E1_H01E0101 Q4
arc: F0 F0_SLICE
arc: F1 F1_SLICE
arc: F2 F2_SLICE
arc: F3 F3_SLICE
arc: F4 F4_SLICE
arc: F5 F5_SLICE
arc: F6 F6_SLICE
arc: F7 F7_SLICE
arc: H00L0100 Q1
arc: H00R0000 Q6
arc: H01W0100 Q2
arc: LSR0 V00T0000
arc: LSR1 V00T0000
arc: MUXCLK0 CLK0
arc: MUXCLK1 CLK0
arc: MUXCLK2 CLK0
arc: MUXCLK3 CLK0
arc: MUXLSR0 LSR0
arc: MUXLSR1 LSR0
arc: MUXLSR2 LSR1
arc: MUXLSR3 LSR1
arc: N1_V01N0001 F0
arc: N1_V01N0101 F2
arc: N1_V02N0101 F1
arc: N1_V02N0301 F3
arc: N1_V02N0401 F4
arc: N1_V02N0501 F5
arc: N1_V02N0701 F7
arc: V00B0100 Q5
arc: V01S0100 F6
word: SLICED.K1.INIT 0110011001101010
word: SLICED.K0.INIT 0110011001101010
word: SLICEC.K1.INIT 0110011001101100
word: SLICEC.K0.INIT 0110011001101010
word: SLICEB.K1.INIT 0110011001101100
word: SLICEB.K0.INIT 0110011001101010
word: SLICEA.K1.INIT 0110011001101010
word: SLICEA.K0.INIT 0110011001101010
enum: SLICED.MODE CCU2
enum: SLICED.CCU2.INJECT1_1 NO
enum: SLICED.C1MUX 1
enum: SLICED.D1MUX 1
enum: SLICED.MODE CCU2
enum: SLICED.CCU2.INJECT1_0 NO
enum: SLICED.C0MUX 1
enum: SLICED.D0MUX 1
enum: SLICEC.MODE CCU2
enum: SLICEC.CCU2.INJECT1_1 NO
enum: SLICEC.C1MUX 1
enum: SLICEC.D1MUX 1
enum: SLICEC.MODE CCU2
enum: SLICEC.CCU2.INJECT1_0 NO
enum: SLICEC.C0MUX 1
enum: SLICEC.D0MUX 1
enum: SLICEB.MODE CCU2
enum: SLICEB.CCU2.INJECT1_1 NO
enum: SLICEB.C1MUX 1
enum: SLICEB.D1MUX 1
enum: SLICEB.MODE CCU2
enum: SLICEB.CCU2.INJECT1_0 NO
enum: SLICEB.C0MUX 1
enum: SLICEB.D0MUX 1
enum: SLICEA.MODE CCU2
enum: SLICEA.CCU2.INJECT1_1 NO
enum: SLICEA.C1MUX 1
enum: SLICEA.D1MUX 1
enum: SLICEA.MODE CCU2
enum: SLICEA.CCU2.INJECT1_0 NO
enum: SLICEA.C0MUX 1
enum: SLICEA.D0MUX 1
enum: SLICEB.GSR DISABLED
enum: SLICEB.REG1.SD 1
enum: SLICEB.REG1.REGSET RESET
enum: SLICEB.REG1.LSRMODE LSR
enum: SLICEB.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEC.GSR DISABLED
enum: SLICEC.REG0.SD 1
enum: SLICEC.REG0.REGSET RESET
enum: SLICEC.REG0.LSRMODE LSR
enum: SLICEC.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEB.GSR DISABLED
enum: SLICEB.REG0.SD 1
enum: SLICEB.REG0.REGSET RESET
enum: SLICEB.REG0.LSRMODE LSR
enum: SLICEB.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEC.GSR DISABLED
enum: SLICEC.REG1.SD 1
enum: SLICEC.REG1.REGSET RESET
enum: SLICEC.REG1.LSRMODE LSR
enum: SLICEC.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEA.GSR DISABLED
enum: SLICEA.REG1.SD 1
enum: SLICEA.REG1.REGSET RESET
enum: SLICEA.REG1.LSRMODE LSR
enum: SLICEA.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICED.GSR DISABLED
enum: SLICED.REG1.SD 1
enum: SLICED.REG1.REGSET RESET
enum: SLICED.REG1.LSRMODE LSR
enum: SLICED.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEA.GSR DISABLED
enum: SLICEA.REG0.SD 1
enum: SLICEA.REG0.REGSET RESET
enum: SLICEA.REG0.LSRMODE LSR
enum: SLICEA.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICED.GSR DISABLED
enum: SLICED.REG0.SD 1
enum: SLICED.REG0.REGSET RESET
enum: SLICED.REG0.LSRMODE LSR
enum: SLICED.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
.tile R19C67:PLC2
arc: E1_H02E0101 S1_V02N0101
arc: E1_H02E0301 W1_H02E0201
arc: E1_H02E0501 E1_H01W0100
arc: H00L0000 H02W0001
arc: S1_V02S0401 H06E0203
arc: V00B0000 S1_V02N0001
arc: W1_H02W0001 S1_V02N0001
arc: W1_H02W0501 H01E0101
arc: A0 E1_H01E0001
arc: A1 H00L0100
arc: A2 S1_V02N0501
arc: A3 S1_V02N0701
arc: A4 S1_V02N0301
arc: A5 Q5
arc: A6 S1_V02N0301
arc: A7 S1_V02N0101
arc: B0 S1_V02N0301
arc: B1 S1_V02N0101
arc: B2 H01W0100
arc: B3 Q3
arc: B4 H00R0000
arc: B5 S1_V02N0501
arc: B6 V01S0000
arc: B7 V00B0100
arc: CE0 H00L0000
arc: CE1 H00L0000
arc: CE2 H00L0000
arc: CE3 H00L0000
arc: CLK0 G_HPBX0000
arc: E1_H01E0001 Q0
arc: F0 F0_SLICE
arc: F1 F1_SLICE
arc: F2 F2_SLICE
arc: F3 F3_SLICE
arc: F4 F4_SLICE
arc: F5 F5_SLICE
arc: F6 F6_SLICE
arc: F7 F7_SLICE
arc: H00L0100 Q1
arc: H00R0000 Q4
arc: H01W0100 Q2
arc: LSR0 V00B0000
arc: LSR1 V00B0000
arc: MUXCLK0 CLK0
arc: MUXCLK1 CLK0
arc: MUXCLK2 CLK0
arc: MUXCLK3 CLK0
arc: MUXLSR0 LSR1
arc: MUXLSR1 LSR1
arc: MUXLSR2 LSR1
arc: MUXLSR3 LSR0
arc: N1_V01N0001 F0
arc: N1_V01N0101 F2
arc: N1_V02N0101 F3
arc: N1_V02N0301 F1
arc: N1_V02N0401 F4
arc: N1_V02N0501 F7
arc: N1_V02N0701 F5
arc: V00B0100 Q7
arc: V01S0000 Q6
arc: V01S0100 F6
word: SLICED.K1.INIT 0110011001101100
word: SLICED.K0.INIT 0110011001101100
word: SLICEC.K1.INIT 0110011001101010
word: SLICEC.K0.INIT 0110011001101100
word: SLICEB.K1.INIT 0110011001101100
word: SLICEB.K0.INIT 0110011001101100
word: SLICEA.K1.INIT 0110011001101010
word: SLICEA.K0.INIT 0110011001101010
enum: SLICED.MODE CCU2
enum: SLICED.CCU2.INJECT1_1 NO
enum: SLICED.C1MUX 1
enum: SLICED.D1MUX 1
enum: SLICED.MODE CCU2
enum: SLICED.CCU2.INJECT1_0 NO
enum: SLICED.C0MUX 1
enum: SLICED.D0MUX 1
enum: SLICEC.MODE CCU2
enum: SLICEC.CCU2.INJECT1_1 NO
enum: SLICEC.C1MUX 1
enum: SLICEC.D1MUX 1
enum: SLICEC.MODE CCU2
enum: SLICEC.CCU2.INJECT1_0 NO
enum: SLICEC.C0MUX 1
enum: SLICEC.D0MUX 1
enum: SLICEB.MODE CCU2
enum: SLICEB.CCU2.INJECT1_1 NO
enum: SLICEB.C1MUX 1
enum: SLICEB.D1MUX 1
enum: SLICEB.MODE CCU2
enum: SLICEB.CCU2.INJECT1_0 NO
enum: SLICEB.C0MUX 1
enum: SLICEB.D0MUX 1
enum: SLICEA.MODE CCU2
enum: SLICEA.CCU2.INJECT1_1 NO
enum: SLICEA.C1MUX 1
enum: SLICEA.D1MUX 1
enum: SLICEA.MODE CCU2
enum: SLICEA.CCU2.INJECT1_0 NO
enum: SLICEA.C0MUX 1
enum: SLICEA.D0MUX 1
enum: SLICEA.GSR DISABLED
enum: SLICEA.REG0.SD 1
enum: SLICEA.REG0.REGSET RESET
enum: SLICEA.REG0.LSRMODE LSR
enum: SLICEA.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEA.GSR DISABLED
enum: SLICEA.REG1.SD 1
enum: SLICEA.REG1.REGSET RESET
enum: SLICEA.REG1.LSRMODE LSR
enum: SLICEA.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEB.GSR DISABLED
enum: SLICEB.REG0.SD 1
enum: SLICEB.REG0.REGSET RESET
enum: SLICEB.REG0.LSRMODE LSR
enum: SLICEB.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEB.GSR DISABLED
enum: SLICEB.REG1.SD 1
enum: SLICEB.REG1.REGSET RESET
enum: SLICEB.REG1.LSRMODE LSR
enum: SLICEB.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICED.GSR DISABLED
enum: SLICED.REG1.SD 1
enum: SLICED.REG1.REGSET RESET
enum: SLICED.REG1.LSRMODE LSR
enum: SLICED.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEC.GSR DISABLED
enum: SLICEC.REG0.SD 1
enum: SLICEC.REG0.REGSET RESET
enum: SLICEC.REG0.LSRMODE LSR
enum: SLICEC.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICED.GSR DISABLED
enum: SLICED.REG0.SD 1
enum: SLICED.REG0.REGSET RESET
enum: SLICED.REG0.LSRMODE LSR
enum: SLICED.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEC.GSR DISABLED
enum: SLICEC.REG1.SD 1
enum: SLICEC.REG1.REGSET RESET
enum: SLICEC.REG1.LSRMODE LSR
enum: SLICEC.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
.tile R19C68:PLC2
arc: H00L0000 S1_V02N0001
arc: S1_V02S0301 H06E0003
arc: S1_V02S0601 H06E0303
arc: W1_H02W0001 S1_V02N0001
arc: A0 H02E0501
arc: A1 H00L0100
arc: B0 H02E0101
arc: B1 H02E0101
arc: CE0 H00L0000
arc: CLK0 G_HPBX0000
arc: E1_H01E0001 F1
arc: F0 F0_SLICE
arc: F1 F1_SLICE
arc: H00L0100 Q1
arc: H01W0100 Q0
arc: LSR0 E1_H02W0301
arc: MUXCLK0 CLK0
arc: MUXLSR0 LSR0
arc: S1_V02S0001 F0
arc: S1_V02S0101 F1
arc: V01S0000 F1
arc: V01S0100 F1
word: SLICEB.K1.INIT 0000000000001110
word: SLICEB.K0.INIT 0000000000000000
word: SLICEA.K1.INIT 0110011001101010
word: SLICEA.K0.INIT 0110011001101010
enum: SLICEB.MODE CCU2
enum: SLICEB.CCU2.INJECT1_1 NO
enum: SLICEB.A1MUX 1
enum: SLICEB.B1MUX 1
enum: SLICEB.C1MUX 1
enum: SLICEB.D1MUX 1
enum: SLICEB.MODE CCU2
enum: SLICEB.CCU2.INJECT1_0 NO
enum: SLICEB.A0MUX 1
enum: SLICEB.B0MUX 1
enum: SLICEB.C0MUX 1
enum: SLICEB.D0MUX 1
enum: SLICEA.MODE CCU2
enum: SLICEA.CCU2.INJECT1_1 NO
enum: SLICEA.C1MUX 1
enum: SLICEA.D1MUX 1
enum: SLICEA.MODE CCU2
enum: SLICEA.CCU2.INJECT1_0 NO
enum: SLICEA.C0MUX 1
enum: SLICEA.D0MUX 1
enum: SLICEA.GSR DISABLED
enum: SLICEA.REG1.SD 1
enum: SLICEA.REG1.REGSET RESET
enum: SLICEA.REG1.LSRMODE LSR
enum: SLICEA.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEA.GSR DISABLED
enum: SLICEA.REG0.SD 1
enum: SLICEA.REG0.REGSET RESET
enum: SLICEA.REG0.LSRMODE LSR
enum: SLICEA.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: CLK0.CLKMUX CLK
.tile R19C69:PLC2
arc: H00R0000 V02N0601
arc: A0 H01E0001
arc: B0 W1_H02E0301
arc: CE0 H00R0000
arc: CLK0 G_HPBX0000
arc: D0 V02N0001
arc: E3_H06E0003 Q0
arc: F0 F0_SLICE
arc: LSR1 E1_H02W0301
arc: MUXCLK0 CLK0
arc: MUXLSR0 LSR1
word: SLICEA.K0.INIT 0100010001010101
enum: SLICEA.MODE LOGIC
enum: SLICEA.CCU2.INJECT1_0 _NONE_
enum: SLICEA.C0MUX 1
enum: SLICEA.GSR DISABLED
enum: SLICEA.REG0.SD 1
enum: SLICEA.REG0.REGSET RESET
enum: SLICEA.REG0.LSRMODE LSR
enum: SLICEA.CEMUX CE
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
.tile R19C70:PLC2
arc: W1_H02W0301 S1_V02N0301
.tile R19C71:PLC2
arc: E1_H02E0301 E3_H06W0003
arc: S1_V02S0301 E3_H06W0003
arc: S3_V06S0003 E3_H06W0003
arc: V00T0000 V02N0601
arc: W1_H02W0301 E3_H06W0003
arc: W3_H06W0003 E3_H06W0003
arc: A2 V01N0101
arc: A4 V00T0000
arc: A6 S1_V02N0101
arc: B0 V02N0301
arc: B3 V01N0001
arc: B5 V02N0701
arc: B7 V02N0501
word: SLICED.K1.INIT 1001100110011100
word: SLICED.K0.INIT 1001100110011010
word: SLICEC.K1.INIT 1001100110011100
word: SLICEC.K0.INIT 1001100110011010
word: SLICEB.K1.INIT 1001100110011100
word: SLICEB.K0.INIT 1001100110011010
word: SLICEA.K1.INIT 1111111111111111
word: SLICEA.K0.INIT 0000000000001100
enum: SLICED.MODE CCU2
enum: SLICED.CCU2.INJECT1_1 NO
enum: SLICED.A1MUX 1
enum: SLICED.C1MUX 1
enum: SLICED.D1MUX 1
enum: SLICED.MODE CCU2
enum: SLICED.CCU2.INJECT1_0 NO
enum: SLICED.B0MUX 1
enum: SLICED.C0MUX 1
enum: SLICED.D0MUX 1
enum: SLICEC.MODE CCU2
enum: SLICEC.CCU2.INJECT1_1 NO
enum: SLICEC.A1MUX 1
enum: SLICEC.C1MUX 1
enum: SLICEC.D1MUX 1
enum: SLICEC.MODE CCU2
enum: SLICEC.CCU2.INJECT1_0 NO
enum: SLICEC.B0MUX 1
enum: SLICEC.C0MUX 1
enum: SLICEC.D0MUX 1
enum: SLICEB.MODE CCU2
enum: SLICEB.CCU2.INJECT1_1 NO
enum: SLICEB.A1MUX 1
enum: SLICEB.C1MUX 1
enum: SLICEB.D1MUX 1
enum: SLICEB.MODE CCU2
enum: SLICEB.CCU2.INJECT1_0 NO
enum: SLICEB.B0MUX 1
enum: SLICEB.C0MUX 1
enum: SLICEB.D0MUX 1
enum: SLICEA.MODE CCU2
enum: SLICEA.CCU2.INJECT1_1 YES
enum: SLICEA.A1MUX 1
enum: SLICEA.B1MUX 1
enum: SLICEA.C1MUX 1
enum: SLICEA.D1MUX 1
enum: SLICEA.MODE CCU2
enum: SLICEA.CCU2.INJECT1_0 NO
enum: SLICEA.A0MUX 1
enum: SLICEA.C0MUX 1
enum: SLICEA.D0MUX 1
.tile R19C72:PLC2
arc: H00R0000 V02N0401
arc: V00B0000 S1_V02N0201
arc: V00T0000 V02N0601
arc: A0 V01N0101
arc: B1 V02N0301
arc: B2 V01N0001
arc: B3 V02N0101
arc: B4 H00R0000
arc: B5 V02N0701
arc: B6 V00T0000
arc: B7 V02N0501
arc: CE0 H02W0101
arc: CLK0 G_HPBX0000
arc: LSR1 H02E0301
arc: M0 V00B0000
arc: MUXCLK0 CLK0
arc: MUXLSR0 LSR1
arc: W3_H06W0003 Q0
word: SLICED.K1.INIT 0011001100111100
word: SLICED.K0.INIT 0011001100111100
word: SLICEC.K1.INIT 0011001100111100
word: SLICEC.K0.INIT 0011001100111100
word: SLICEB.K1.INIT 0011001100111100
word: SLICEB.K0.INIT 0011001100111100
word: SLICEA.K1.INIT 0011001100111100
word: SLICEA.K0.INIT 1001100110011010
enum: SLICED.MODE CCU2
enum: SLICED.CCU2.INJECT1_1 NO
enum: SLICED.A1MUX 1
enum: SLICED.C1MUX 1
enum: SLICED.D1MUX 1
enum: SLICED.MODE CCU2
enum: SLICED.CCU2.INJECT1_0 NO
enum: SLICED.A0MUX 1
enum: SLICED.C0MUX 1
enum: SLICED.D0MUX 1
enum: SLICEC.MODE CCU2
enum: SLICEC.CCU2.INJECT1_1 NO
enum: SLICEC.A1MUX 1
enum: SLICEC.C1MUX 1
enum: SLICEC.D1MUX 1
enum: SLICEC.MODE CCU2
enum: SLICEC.CCU2.INJECT1_0 NO
enum: SLICEC.A0MUX 1
enum: SLICEC.C0MUX 1
enum: SLICEC.D0MUX 1
enum: SLICEB.MODE CCU2
enum: SLICEB.CCU2.INJECT1_1 NO
enum: SLICEB.A1MUX 1
enum: SLICEB.C1MUX 1
enum: SLICEB.D1MUX 1
enum: SLICEB.MODE CCU2
enum: SLICEB.CCU2.INJECT1_0 NO
enum: SLICEB.A0MUX 1
enum: SLICEB.C0MUX 1
enum: SLICEB.D0MUX 1
enum: SLICEA.MODE CCU2
enum: SLICEA.CCU2.INJECT1_1 NO
enum: SLICEA.A1MUX 1
enum: SLICEA.C1MUX 1
enum: SLICEA.D1MUX 1
enum: SLICEA.MODE CCU2
enum: SLICEA.CCU2.INJECT1_0 NO
enum: SLICEA.B0MUX 1
enum: SLICEA.C0MUX 1
enum: SLICEA.D0MUX 1
enum: SLICEA.GSR DISABLED
enum: SLICEA.REG0.SD 0
enum: SLICEA.REG0.REGSET RESET
enum: SLICEA.REG0.LSRMODE LSR
enum: SLICEA.CEMUX CE
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
.tile R19C73:PLC2
arc: V00T0000 V02N0601
arc: W1_H02W0101 S1_V02N0101
arc: A0 V01N0101
arc: B1 V02N0301
arc: B2 V01N0001
arc: B3 V02N0101
arc: B4 S1_V02N0701
arc: B5 V02N0701
arc: B6 V00T0000
arc: B7 V02N0501
word: SLICED.K1.INIT 0011001100111100
word: SLICED.K0.INIT 0011001100111100
word: SLICEC.K1.INIT 0011001100111100
word: SLICEC.K0.INIT 0011001100111100
word: SLICEB.K1.INIT 0011001100111100
word: SLICEB.K0.INIT 0011001100111100
word: SLICEA.K1.INIT 0011001100111100
word: SLICEA.K0.INIT 0101010101011010
enum: SLICED.MODE CCU2
enum: SLICED.CCU2.INJECT1_1 NO
enum: SLICED.A1MUX 1
enum: SLICED.C1MUX 1
enum: SLICED.D1MUX 1
enum: SLICED.MODE CCU2
enum: SLICED.CCU2.INJECT1_0 NO
enum: SLICED.A0MUX 1
enum: SLICED.C0MUX 1
enum: SLICED.D0MUX 1
enum: SLICEC.MODE CCU2
enum: SLICEC.CCU2.INJECT1_1 NO
enum: SLICEC.A1MUX 1
enum: SLICEC.C1MUX 1
enum: SLICEC.D1MUX 1
enum: SLICEC.MODE CCU2
enum: SLICEC.CCU2.INJECT1_0 NO
enum: SLICEC.A0MUX 1
enum: SLICEC.C0MUX 1
enum: SLICEC.D0MUX 1
enum: SLICEB.MODE CCU2
enum: SLICEB.CCU2.INJECT1_1 NO
enum: SLICEB.A1MUX 1
enum: SLICEB.C1MUX 1
enum: SLICEB.D1MUX 1
enum: SLICEB.MODE CCU2
enum: SLICEB.CCU2.INJECT1_0 NO
enum: SLICEB.A0MUX 1
enum: SLICEB.C0MUX 1
enum: SLICEB.D0MUX 1
enum: SLICEA.MODE CCU2
enum: SLICEA.CCU2.INJECT1_1 NO
enum: SLICEA.A1MUX 1
enum: SLICEA.C1MUX 1
enum: SLICEA.D1MUX 1
enum: SLICEA.MODE CCU2
enum: SLICEA.CCU2.INJECT1_0 NO
enum: SLICEA.B0MUX 1
enum: SLICEA.C0MUX 1
enum: SLICEA.D0MUX 1
.tile R19C74:PLC2
arc: H00R0000 V02N0601
arc: S1_V02S0001 H06W0003
arc: V00T0000 V02N0401
arc: A0 V01N0101
arc: A4 V00T0000
arc: A6 H00R0000
arc: B1 V02N0101
arc: B2 V01N0001
arc: B3 V02N0301
arc: B5 V02N0701
arc: B7 V02N0501
word: SLICED.K1.INIT 0011001100111100
word: SLICED.K0.INIT 0101010101011010
word: SLICEC.K1.INIT 0011001100111100
word: SLICEC.K0.INIT 0101010101011010
word: SLICEB.K1.INIT 0011001100111100
word: SLICEB.K0.INIT 0011001100111100
word: SLICEA.K1.INIT 0011001100111100
word: SLICEA.K0.INIT 0101010101011010
enum: SLICED.MODE CCU2
enum: SLICED.CCU2.INJECT1_1 NO
enum: SLICED.A1MUX 1
enum: SLICED.C1MUX 1
enum: SLICED.D1MUX 1
enum: SLICED.MODE CCU2
enum: SLICED.CCU2.INJECT1_0 NO
enum: SLICED.B0MUX 1
enum: SLICED.C0MUX 1
enum: SLICED.D0MUX 1
enum: SLICEC.MODE CCU2
enum: SLICEC.CCU2.INJECT1_1 NO
enum: SLICEC.A1MUX 1
enum: SLICEC.C1MUX 1
enum: SLICEC.D1MUX 1
enum: SLICEC.MODE CCU2
enum: SLICEC.CCU2.INJECT1_0 NO
enum: SLICEC.B0MUX 1
enum: SLICEC.C0MUX 1
enum: SLICEC.D0MUX 1
enum: SLICEB.MODE CCU2
enum: SLICEB.CCU2.INJECT1_1 NO
enum: SLICEB.A1MUX 1
enum: SLICEB.C1MUX 1
enum: SLICEB.D1MUX 1
enum: SLICEB.MODE CCU2
enum: SLICEB.CCU2.INJECT1_0 NO
enum: SLICEB.A0MUX 1
enum: SLICEB.C0MUX 1
enum: SLICEB.D0MUX 1
enum: SLICEA.MODE CCU2
enum: SLICEA.CCU2.INJECT1_1 NO
enum: SLICEA.A1MUX 1
enum: SLICEA.C1MUX 1
enum: SLICEA.D1MUX 1
enum: SLICEA.MODE CCU2
enum: SLICEA.CCU2.INJECT1_0 NO
enum: SLICEA.B0MUX 1
enum: SLICEA.C0MUX 1
enum: SLICEA.D0MUX 1
.tile R19C75:PLC2
arc: E3_H06E0103 W3_H06E0003
arc: F0 F0_SLICE
arc: S1_V02S0201 F0
word: SLICEA.K1.INIT 0000000000001110
word: SLICEA.K0.INIT 0000000000000000
enum: SLICEA.MODE CCU2
enum: SLICEA.CCU2.INJECT1_1 NO
enum: SLICEA.A1MUX 1
enum: SLICEA.B1MUX 1
enum: SLICEA.C1MUX 1
enum: SLICEA.D1MUX 1
enum: SLICEA.MODE CCU2
enum: SLICEA.CCU2.INJECT1_0 NO
enum: SLICEA.A0MUX 1
enum: SLICEA.B0MUX 1
enum: SLICEA.C0MUX 1
enum: SLICEA.D0MUX 1
.tile R19C77:PLC2
arc: S1_V02S0301 E3_H06W0003
arc: W3_H06W0003 E3_H06W0003
.tile R19C81:PLC2
arc: E3_H06E0203 W3_H06E0103
.tile R19C83:PLC2
arc: W3_H06W0003 E3_H06W0303
.tile R19C87:PLC2
arc: S3_V06S0203 W3_H06E0203
.tile R19C9:PLC2
arc: W3_H06W0303 E1_H02W0501
.tile R20C10:PLC2
arc: W3_H06W0203 E3_H06W0103
.tile R20C11:PLC2
arc: W3_H06W0203 E3_H06W0103
.tile R20C16:PLC2
arc: W3_H06W0103 E1_H01W0100
.tile R20C17:PLC2
arc: E1_H02E0401 S1_V02N0401
arc: H00L0000 E1_H02W0201
arc: H00R0000 V02S0401
arc: V00T0000 V02S0601
arc: A1 N1_V02S0701
arc: B0 N1_V02S0301
arc: B1 N1_V02S0301
arc: C0 H00L0000
arc: CE0 H00R0000
arc: CLK0 G_HPBX0000
arc: D0 V02S0201
arc: D1 V02S0201
arc: F0 F0_SLICE
arc: F1 F1_SLICE
arc: H01W0100 Q0
arc: LSR0 V00T0000
arc: MUXCLK0 CLK0
arc: MUXLSR0 LSR0
arc: W3_H06W0103 Q1
word: SLICEA.K1.INIT 0010001000110011
word: SLICEA.K0.INIT 0011000000110011
enum: SLICEA.GSR DISABLED
enum: SLICEA.REG0.SD 1
enum: SLICEA.REG0.REGSET RESET
enum: SLICEA.REG0.LSRMODE LSR
enum: SLICEA.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEA.GSR DISABLED
enum: SLICEA.REG1.SD 1
enum: SLICEA.REG1.REGSET RESET
enum: SLICEA.REG1.LSRMODE LSR
enum: SLICEA.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEA.MODE LOGIC
enum: SLICEA.CCU2.INJECT1_1 _NONE_
enum: SLICEA.C1MUX 1
enum: SLICEA.MODE LOGIC
enum: SLICEA.CCU2.INJECT1_0 _NONE_
enum: SLICEA.A0MUX 1
.tile R20C18:PLC2
arc: E1_H02E0301 V02N0301
arc: E1_H02E0501 V02N0501
arc: E1_H02E0701 V02N0701
arc: N1_V02N0101 E1_H01W0100
arc: S1_V02S0501 H02W0501
arc: S3_V06S0003 E3_H06W0003
arc: V00B0000 E1_H02W0401
arc: A0 H02W0701
arc: C0 H02W0401
arc: CE0 V02N0201
arc: CLK0 G_HPBX0000
arc: D0 V02N0001
arc: E1_H01E0101 Q0
arc: F0 F0_SLICE
arc: LSR1 V00B0000
arc: MUXCLK0 CLK0
arc: MUXLSR0 LSR1
word: SLICEA.K0.INIT 1111000010101010
enum: SLICEA.GSR DISABLED
enum: SLICEA.REG0.SD 1
enum: SLICEA.REG0.REGSET RESET
enum: SLICEA.REG0.LSRMODE LSR
enum: SLICEA.CEMUX CE
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEA.MODE LOGIC
enum: SLICEA.CCU2.INJECT1_0 _NONE_
enum: SLICEA.B0MUX 1
.tile R20C19:PLC2
arc: E1_H02E0101 V02S0101
arc: E1_H02E0501 W1_H02E0401
arc: H00L0000 V02N0001
arc: H00R0000 V02N0401
arc: N1_V02N0201 E3_H06W0103
arc: N1_V02N0701 E1_H01W0100
arc: S1_V02S0001 N1_V02S0501
arc: S1_V02S0501 E1_H01W0100
arc: V00B0000 V02S0001
arc: V00B0100 V02N0301
arc: W1_H02W0401 N1_V02S0401
arc: A2 V00T0000
arc: A3 V00B0000
arc: A4 E1_H02W0501
arc: A5 H02E0501
arc: A6 N1_V01S0100
arc: A7 H02W0701
arc: B0 H02E0301
arc: B2 H02W0301
arc: B3 H00R0000
arc: B4 N1_V01S0000
arc: B5 H01E0101
arc: B6 V02N0501
arc: B7 V02N0701
arc: CE1 H00L0000
arc: CLK0 G_HPBX0000
arc: F2 F2_SLICE
arc: F3 F3_SLICE
arc: F4 F4_SLICE
arc: F5 F5_SLICE
arc: F6 F6_SLICE
arc: F7 F7_SLICE
arc: H01W0100 F3
arc: LSR0 V00B0100
arc: MUXCLK1 CLK0
arc: MUXLSR1 LSR0
arc: N1_V01N0101 F5
arc: N1_V02N0001 F2
arc: N1_V02N0101 F3
arc: N1_V02N0301 F3
arc: N1_V02N0401 F6
arc: N1_V02N0501 F7
arc: N1_V02N0601 F4
arc: V00T0000 Q2
arc: W1_H02W0201 F2
arc: W1_H02W0501 F7
arc: W1_H02W0701 F5
word: SLICED.K1.INIT 0110011001101100
word: SLICED.K0.INIT 0110011001101010
word: SLICEC.K1.INIT 0110011001101100
word: SLICEC.K0.INIT 0110011001101100
word: SLICEB.K1.INIT 0110011001101010
word: SLICEB.K0.INIT 0110011001101010
word: SLICEA.K1.INIT 1111111111111111
word: SLICEA.K0.INIT 0000000000001100
enum: SLICED.MODE CCU2
enum: SLICED.CCU2.INJECT1_1 NO
enum: SLICED.C1MUX 1
enum: SLICED.D1MUX 1
enum: SLICED.MODE CCU2
enum: SLICED.CCU2.INJECT1_0 NO
enum: SLICED.C0MUX 1
enum: SLICED.D0MUX 1
enum: SLICEC.MODE CCU2
enum: SLICEC.CCU2.INJECT1_1 NO
enum: SLICEC.C1MUX 1
enum: SLICEC.D1MUX 1
enum: SLICEC.MODE CCU2
enum: SLICEC.CCU2.INJECT1_0 NO
enum: SLICEC.C0MUX 1
enum: SLICEC.D0MUX 1
enum: SLICEB.MODE CCU2
enum: SLICEB.CCU2.INJECT1_1 NO
enum: SLICEB.C1MUX 1
enum: SLICEB.D1MUX 1
enum: SLICEB.MODE CCU2
enum: SLICEB.CCU2.INJECT1_0 NO
enum: SLICEB.C0MUX 1
enum: SLICEB.D0MUX 1
enum: SLICEA.MODE CCU2
enum: SLICEA.CCU2.INJECT1_1 YES
enum: SLICEA.A1MUX 1
enum: SLICEA.B1MUX 1
enum: SLICEA.C1MUX 1
enum: SLICEA.D1MUX 1
enum: SLICEA.MODE CCU2
enum: SLICEA.CCU2.INJECT1_0 NO
enum: SLICEA.A0MUX 1
enum: SLICEA.C0MUX 1
enum: SLICEA.D0MUX 1
enum: SLICEB.GSR DISABLED
enum: SLICEB.REG0.SD 1
enum: SLICEB.REG0.REGSET RESET
enum: SLICEB.REG0.LSRMODE LSR
enum: SLICEB.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: CLK0.CLKMUX CLK
.tile R20C20:PLC2
arc: E1_H02E0101 N1_V01S0100
arc: H00L0000 V02N0201
arc: H00R0000 V02S0601
arc: N1_V02N0201 E1_H01W0000
arc: N1_V02N0701 E1_H01W0100
arc: S1_V02S0501 H02E0501
arc: V00B0000 V02S0001
arc: V00T0000 V02S0401
arc: V00T0100 V02N0701
arc: W1_H02W0301 S1_V02N0301
arc: W1_H02W0401 V02N0401
arc: W1_H02W0701 V01N0101
arc: A0 V02N0501
arc: A1 V02S0501
arc: A2 S1_V02N0701
arc: A3 V00T0000
arc: A4 W1_H02E0701
arc: A5 H02W0701
arc: A6 E1_H02W0701
arc: A7 V00T0100
arc: B0 V02N0301
arc: B1 E1_H02W0101
arc: B2 V02S0301
arc: B3 H00L0000
arc: B4 N1_V01S0000
arc: B5 H00R0000
arc: B6 V00B0000
arc: B7 H02W0301
arc: F0 F0_SLICE
arc: F1 F1_SLICE
arc: F2 F2_SLICE
arc: F3 F3_SLICE
arc: F4 F4_SLICE
arc: F5 F5_SLICE
arc: F6 F6_SLICE
arc: F7 F7_SLICE
arc: H01W0100 F0
arc: N1_V01N0001 F4
arc: N1_V01N0101 F5
arc: N1_V02N0001 F2
arc: N1_V02N0101 F1
arc: N1_V02N0301 F3
arc: N1_V02N0401 F4
arc: N1_V02N0501 F7
arc: N1_V02N0601 F6
word: SLICED.K1.INIT 0110011001101100
word: SLICED.K0.INIT 0110011001101100
word: SLICEC.K1.INIT 0110011001101100
word: SLICEC.K0.INIT 0110011001101100
word: SLICEB.K1.INIT 0110011001101010
word: SLICEB.K0.INIT 0110011001101100
word: SLICEA.K1.INIT 0110011001101010
word: SLICEA.K0.INIT 0110011001101100
enum: SLICED.MODE CCU2
enum: SLICED.CCU2.INJECT1_1 NO
enum: SLICED.C1MUX 1
enum: SLICED.D1MUX 1
enum: SLICED.MODE CCU2
enum: SLICED.CCU2.INJECT1_0 NO
enum: SLICED.C0MUX 1
enum: SLICED.D0MUX 1
enum: SLICEC.MODE CCU2
enum: SLICEC.CCU2.INJECT1_1 NO
enum: SLICEC.C1MUX 1
enum: SLICEC.D1MUX 1
enum: SLICEC.MODE CCU2
enum: SLICEC.CCU2.INJECT1_0 NO
enum: SLICEC.C0MUX 1
enum: SLICEC.D0MUX 1
enum: SLICEB.MODE CCU2
enum: SLICEB.CCU2.INJECT1_1 NO
enum: SLICEB.C1MUX 1
enum: SLICEB.D1MUX 1
enum: SLICEB.MODE CCU2
enum: SLICEB.CCU2.INJECT1_0 NO
enum: SLICEB.C0MUX 1
enum: SLICEB.D0MUX 1
enum: SLICEA.MODE CCU2
enum: SLICEA.CCU2.INJECT1_1 NO
enum: SLICEA.C1MUX 1
enum: SLICEA.D1MUX 1
enum: SLICEA.MODE CCU2
enum: SLICEA.CCU2.INJECT1_0 NO
enum: SLICEA.C0MUX 1
enum: SLICEA.D0MUX 1
.tile R20C21:PLC2
arc: H00R0000 V02N0601
arc: N1_V02N0701 E1_H01W0100
arc: V00B0000 V02S0201
arc: V00T0100 H02W0301
arc: W1_H02W0301 N1_V01S0100
arc: W1_H02W0501 V02N0501
arc: W1_H02W0701 V01N0101
arc: A0 H00R0000
arc: A1 V02N0701
arc: A2 V00B0000
arc: A3 V02S0501
arc: A4 E1_H02W0501
arc: A5 V00T0100
arc: A6 V00T0100
arc: A7 V02S0301
arc: B0 H02E0101
arc: B1 V02S0101
arc: B2 H02W0301
arc: B3 E1_H02W0301
arc: B4 W1_H02E0101
arc: B5 N1_V01S0000
arc: B6 V02S0701
arc: B7 E1_H02W0301
arc: F0 F0_SLICE
arc: F1 F1_SLICE
arc: F2 F2_SLICE
arc: F3 F3_SLICE
arc: F4 F4_SLICE
arc: F5 F5_SLICE
arc: F6 F6_SLICE
arc: F7 F7_SLICE
arc: H01W0000 F0
arc: H01W0100 F0
arc: N1_V01N0001 F4
arc: N1_V01N0101 F5
arc: N1_V02N0001 F2
arc: N1_V02N0101 F3
arc: N1_V02N0201 F2
arc: N1_V02N0301 F1
arc: N1_V02N0401 F6
arc: N1_V02N0501 F7
arc: N1_V02N0601 F4
word: SLICED.K1.INIT 0110011001101010
word: SLICED.K0.INIT 0110011001101100
word: SLICEC.K1.INIT 0110011001101100
word: SLICEC.K0.INIT 0110011001101100
word: SLICEB.K1.INIT 0110011001101010
word: SLICEB.K0.INIT 0110011001101010
word: SLICEA.K1.INIT 0110011001101100
word: SLICEA.K0.INIT 0110011001101100
enum: SLICED.MODE CCU2
enum: SLICED.CCU2.INJECT1_1 NO
enum: SLICED.C1MUX 1
enum: SLICED.D1MUX 1
enum: SLICED.MODE CCU2
enum: SLICED.CCU2.INJECT1_0 NO
enum: SLICED.C0MUX 1
enum: SLICED.D0MUX 1
enum: SLICEC.MODE CCU2
enum: SLICEC.CCU2.INJECT1_1 NO
enum: SLICEC.C1MUX 1
enum: SLICEC.D1MUX 1
enum: SLICEC.MODE CCU2
enum: SLICEC.CCU2.INJECT1_0 NO
enum: SLICEC.C0MUX 1
enum: SLICEC.D0MUX 1
enum: SLICEB.MODE CCU2
enum: SLICEB.CCU2.INJECT1_1 NO
enum: SLICEB.C1MUX 1
enum: SLICEB.D1MUX 1
enum: SLICEB.MODE CCU2
enum: SLICEB.CCU2.INJECT1_0 NO
enum: SLICEB.C0MUX 1
enum: SLICEB.D0MUX 1
enum: SLICEA.MODE CCU2
enum: SLICEA.CCU2.INJECT1_1 NO
enum: SLICEA.C1MUX 1
enum: SLICEA.D1MUX 1
enum: SLICEA.MODE CCU2
enum: SLICEA.CCU2.INJECT1_0 NO
enum: SLICEA.C0MUX 1
enum: SLICEA.D0MUX 1
.tile R20C22:PLC2
arc: E1_H02E0301 V02N0301
arc: H00R0000 V02S0401
arc: N1_V02N0501 E1_H01W0100
arc: V00B0000 V02N0001
arc: V00T0000 E1_H02W0201
arc: W1_H02W0101 V02N0101
arc: W1_H02W0301 V01N0101
arc: W1_H02W0701 V02N0701
arc: A0 V01N0101
arc: A1 V01N0101
arc: A2 V02S0701
arc: A3 V01N0101
arc: A4 V00B0000
arc: A5 V00B0000
arc: A6 H02W0501
arc: A7 N1_V01S0100
arc: B0 V02S0101
arc: B1 V00T0000
arc: B2 V01N0001
arc: B3 H00R0000
arc: B4 V02S0501
arc: B5 N1_V01S0000
arc: B6 H02W0101
arc: B7 V00B0000
arc: E1_H01E0001 F6
arc: E1_H01E0101 F4
arc: E1_H02E0101 F1
arc: F0 F0_SLICE
arc: F1 F1_SLICE
arc: F2 F2_SLICE
arc: F3 F3_SLICE
arc: F4 F4_SLICE
arc: F5 F5_SLICE
arc: F6 F6_SLICE
arc: F7 F7_SLICE
arc: H01W0100 F0
arc: N1_V01N0001 F7
arc: N1_V01N0101 F5
arc: N1_V02N0001 F2
arc: N1_V02N0101 F1
arc: N1_V02N0201 F0
arc: N1_V02N0301 F3
arc: N1_V02N0401 F6
arc: N1_V02N0601 F4
arc: N1_V02N0701 F7
arc: V01S0000 F2
word: SLICED.K1.INIT 0110011001101010
word: SLICED.K0.INIT 0110011001101100
word: SLICEC.K1.INIT 0110011001101100
word: SLICEC.K0.INIT 0110011001101100
word: SLICEB.K1.INIT 0110011001101100
word: SLICEB.K0.INIT 0110011001101010
word: SLICEA.K1.INIT 0110011001101100
word: SLICEA.K0.INIT 0110011001101100
enum: SLICED.MODE CCU2
enum: SLICED.CCU2.INJECT1_1 NO
enum: SLICED.C1MUX 1
enum: SLICED.D1MUX 1
enum: SLICED.MODE CCU2
enum: SLICED.CCU2.INJECT1_0 NO
enum: SLICED.C0MUX 1
enum: SLICED.D0MUX 1
enum: SLICEC.MODE CCU2
enum: SLICEC.CCU2.INJECT1_1 NO
enum: SLICEC.C1MUX 1
enum: SLICEC.D1MUX 1
enum: SLICEC.MODE CCU2
enum: SLICEC.CCU2.INJECT1_0 NO
enum: SLICEC.C0MUX 1
enum: SLICEC.D0MUX 1
enum: SLICEB.MODE CCU2
enum: SLICEB.CCU2.INJECT1_1 NO
enum: SLICEB.C1MUX 1
enum: SLICEB.D1MUX 1
enum: SLICEB.MODE CCU2
enum: SLICEB.CCU2.INJECT1_0 NO
enum: SLICEB.C0MUX 1
enum: SLICEB.D0MUX 1
enum: SLICEA.MODE CCU2
enum: SLICEA.CCU2.INJECT1_1 NO
enum: SLICEA.C1MUX 1
enum: SLICEA.D1MUX 1
enum: SLICEA.MODE CCU2
enum: SLICEA.CCU2.INJECT1_0 NO
enum: SLICEA.C0MUX 1
enum: SLICEA.D0MUX 1
.tile R20C23:PLC2
arc: N1_V02N0401 H01E0001
arc: N1_V02N0701 H01E0101
arc: S1_V02S0001 N1_V02S0001
arc: S1_V02S0301 E1_H02W0301
arc: W1_H02W0101 N1_V01S0100
arc: W1_H02W0301 V02N0301
arc: W1_H02W0501 V02N0501
arc: A0 V02S0501
arc: A1 V02N0501
arc: B0 V02N0301
arc: B1 V01N0001
arc: E1_H01E0001 F0
arc: F0 F0_SLICE
arc: F1 F1_SLICE
arc: H01W0100 F0
arc: N1_V02N0101 F1
arc: V01S0100 F1
word: SLICEB.K1.INIT 0000000000001110
word: SLICEB.K0.INIT 0000000000000000
word: SLICEA.K1.INIT 0110011001101100
word: SLICEA.K0.INIT 0110011001101010
enum: SLICEB.MODE CCU2
enum: SLICEB.CCU2.INJECT1_1 NO
enum: SLICEB.A1MUX 1
enum: SLICEB.B1MUX 1
enum: SLICEB.C1MUX 1
enum: SLICEB.D1MUX 1
enum: SLICEB.MODE CCU2
enum: SLICEB.CCU2.INJECT1_0 NO
enum: SLICEB.A0MUX 1
enum: SLICEB.B0MUX 1
enum: SLICEB.C0MUX 1
enum: SLICEB.D0MUX 1
enum: SLICEA.MODE CCU2
enum: SLICEA.CCU2.INJECT1_1 NO
enum: SLICEA.C1MUX 1
enum: SLICEA.D1MUX 1
enum: SLICEA.MODE CCU2
enum: SLICEA.CCU2.INJECT1_0 NO
enum: SLICEA.C0MUX 1
enum: SLICEA.D0MUX 1
.tile R20C24:PLC2
arc: H00L0100 V02N0301
arc: N1_V02N0401 H01E0001
arc: W3_H06W0003 E3_H06W0303
arc: B0 W1_H02E0101
arc: C0 V02N0401
arc: CE0 H00L0100
arc: CLK0 G_HPBX0000
arc: D0 N1_V02S0001
arc: F0 F0_SLICE
arc: LSR1 W1_H02E0301
arc: MUXCLK0 CLK0
arc: MUXLSR0 LSR1
arc: W1_H02W0201 Q0
word: SLICEA.K0.INIT 1111110000001100
enum: SLICEA.GSR DISABLED
enum: SLICEA.REG0.SD 1
enum: SLICEA.REG0.REGSET RESET
enum: SLICEA.REG0.LSRMODE LSR
enum: SLICEA.CEMUX CE
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEA.MODE LOGIC
enum: SLICEA.CCU2.INJECT1_0 _NONE_
enum: SLICEA.A0MUX 1
.tile R20C25:PLC2
arc: W1_H02W0301 E3_H06W0003
arc: W3_H06W0103 E3_H06W0003
.tile R20C30:PLC2
arc: W3_H06W0303 E3_H06W0303
.tile R20C31:PLC2
arc: W3_H06W0003 E3_H06W0303
.tile R20C36:PLC2
arc: W3_H06W0303 E3_H06W0203
.tile R20C37:PLC2
arc: W3_H06W0303 E3_H06W0203
.tile R20C38:PLC2
arc: N3_V06N0303 E3_H06W0303
.tile R20C3:PLC2
arc: W1_H02W0701 E1_H02W0701
.tile R20C42:PLC2
arc: W3_H06W0203 E3_H06W0103
.tile R20C43:PLC2
arc: W3_H06W0203 E3_H06W0203
.tile R20C44:PLC2
arc: W3_H06W0303 E3_H06W0203
.tile R20C48:PLC2
arc: W3_H06W0103 E3_H06W0103
.tile R20C49:PLC2
arc: S3_V06S0103 E3_H06W0103
arc: W3_H06W0203 E3_H06W0103
.tile R20C4:PLC2
arc: W3_H06W0203 E3_H06W0203
.tile R20C50:PLC2
arc: W3_H06W0203 E3_H06W0203
.tile R20C52:PLC2
arc: S3_V06S0103 H06W0103
.tile R20C54:PLC2
arc: W3_H06W0103 E3_H06W0003
.tile R20C55:PLC2
arc: E3_H06E0103 F2
arc: F2 F2_SLICE
arc: W3_H06W0103 F2
word: SLICEB.K0.INIT 1111111111111111
enum: SLICEB.MODE LOGIC
enum: SLICEB.CCU2.INJECT1_0 _NONE_
enum: SLICEB.A0MUX 1
enum: SLICEB.B0MUX 1
enum: SLICEB.C0MUX 1
enum: SLICEB.D0MUX 1
.tile R20C56:PLC2
arc: W3_H06W0203 E3_H06W0103
.tile R20C5:PLC2
arc: W1_H02W0701 E3_H06W0203
.tile R20C60:PLC2
arc: W3_H06W0003 E3_H06W0003
.tile R20C61:PLC2
arc: E3_H06E0103 W3_H06E0103
arc: E3_H06E0203 W3_H06E0103
.tile R20C62:PLC2
arc: W3_H06W0103 E3_H06W0003
.tile R20C63:PLC2
arc: C6 V02N0001
arc: D6 V02N0401
arc: E3_H06E0303 F6
arc: F6 F6_SLICE
arc: V01S0000 F6
word: SLICED.K0.INIT 1111000000000000
enum: SLICED.MODE LOGIC
enum: SLICED.CCU2.INJECT1_0 _NONE_
enum: SLICED.A0MUX 1
enum: SLICED.B0MUX 1
.tile R20C64:PLC2
arc: E1_H02E0601 N1_V01S0000
arc: E1_H02E0701 V02S0701
arc: E3_H06E0103 N1_V01S0100
arc: N1_V02N0101 V01N0101
arc: N1_V02N0701 H06E0203
arc: S1_V02S0701 H06E0203
.tile R20C65:PLC2
arc: E1_H02E0301 V02S0301
arc: N1_V02N0501 V01N0101
arc: N1_V02N0701 N1_V01S0100
.tile R20C66:PLC2
arc: E1_H02E0201 W1_H02E0701
arc: N1_V02N0101 V01N0101
arc: N1_V02N0501 N1_V01S0100
arc: V00B0100 E1_H02W0701
arc: B0 E1_H02W0301
arc: C0 W1_H02E0601
arc: CE0 E1_H02W0101
arc: CLK0 G_HPBX0000
arc: D0 V00B0100
arc: F0 F0_SLICE
arc: LSR0 H02E0301
arc: MUXCLK0 CLK0
arc: MUXLSR0 LSR0
arc: W3_H06W0003 Q0
word: SLICEA.K0.INIT 0011000000110011
enum: SLICEA.MODE LOGIC
enum: SLICEA.CCU2.INJECT1_0 _NONE_
enum: SLICEA.A0MUX 1
enum: SLICEA.GSR DISABLED
enum: SLICEA.REG0.SD 1
enum: SLICEA.REG0.REGSET RESET
enum: SLICEA.REG0.LSRMODE LSR
enum: SLICEA.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: CLK0.CLKMUX CLK
.tile R20C67:PLC2
arc: E1_H02E0201 W3_H06E0103
arc: E1_H02E0301 W1_H02E0301
arc: E3_H06E0203 W3_H06E0103
arc: E3_H06E0303 W3_H06E0203
arc: H00R0000 V02S0401
arc: H00R0100 E1_H02W0501
arc: N1_V02N0701 N1_V01S0100
arc: S1_V02S0101 W3_H06E0103
arc: B0 H02W0301
arc: B1 H02W0301
arc: C0 E1_H01W0000
arc: C1 E1_H01W0000
arc: CE0 H00R0100
arc: CLK0 G_HPBX0000
arc: D0 H02E0201
arc: D1 H00R0000
arc: F0 F0_SLICE
arc: F1 F1_SLICE
arc: LSR0 W1_H02E0301
arc: MUXCLK0 CLK0
arc: MUXLSR0 LSR0
arc: N3_V06N0003 Q0
arc: N3_V06N0103 Q1
word: SLICEA.K0.INIT 0011001100000011
word: SLICEA.K1.INIT 0011001100000011
enum: SLICEA.MODE LOGIC
enum: SLICEA.CCU2.INJECT1_0 _NONE_
enum: SLICEA.A0MUX 1
enum: SLICEA.MODE LOGIC
enum: SLICEA.CCU2.INJECT1_1 _NONE_
enum: SLICEA.A1MUX 1
enum: SLICEA.GSR DISABLED
enum: SLICEA.REG1.SD 1
enum: SLICEA.REG1.REGSET RESET
enum: SLICEA.REG1.LSRMODE LSR
enum: SLICEA.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEA.GSR DISABLED
enum: SLICEA.REG0.SD 1
enum: SLICEA.REG0.REGSET RESET
enum: SLICEA.REG0.LSRMODE LSR
enum: SLICEA.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: CLK0.CLKMUX CLK
.tile R20C68:PLC2
arc: E1_H02E0101 E1_H01W0100
arc: E1_H02E0401 N1_V01S0000
arc: H00R0100 H02W0501
arc: V00B0000 V02S0001
arc: W1_H02W0101 E1_H01W0100
arc: W1_H02W0301 N1_V01S0100
arc: B0 V02S0301
arc: B1 V02S0101
arc: C0 N1_V01S0100
arc: C1 V02S0601
arc: C7 N1_V02S0201
arc: CE0 H00R0100
arc: CLK0 G_HPBX0000
arc: D0 V00B0100
arc: D1 V01S0100
arc: D7 V00B0000
arc: E1_H01E0001 F7
arc: E1_H01E0101 F7
arc: E3_H06E0103 Q1
arc: F0 F0_SLICE
arc: F1 F1_SLICE
arc: F7 F7_SLICE
arc: H01W0000 F7
arc: LSR1 H02E0301
arc: MUXCLK0 CLK0
arc: MUXLSR0 LSR1
arc: V00B0100 F7
arc: V01S0100 F7
arc: W1_H02W0701 F7
arc: W3_H06W0003 Q0
word: SLICED.K1.INIT 0000000000001111
word: SLICEA.K1.INIT 0011000000110011
word: SLICEA.K0.INIT 0000110000001111
enum: SLICED.MODE LOGIC
enum: SLICED.CCU2.INJECT1_1 _NONE_
enum: SLICED.A1MUX 1
enum: SLICED.B1MUX 1
enum: SLICEA.MODE LOGIC
enum: SLICEA.CCU2.INJECT1_1 _NONE_
enum: SLICEA.A1MUX 1
enum: SLICEA.MODE LOGIC
enum: SLICEA.CCU2.INJECT1_0 _NONE_
enum: SLICEA.A0MUX 1
enum: SLICEA.GSR DISABLED
enum: SLICEA.REG0.SD 1
enum: SLICEA.REG0.REGSET RESET
enum: SLICEA.REG0.LSRMODE LSR
enum: SLICEA.CEMUX CE
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEA.GSR DISABLED
enum: SLICEA.REG1.SD 1
enum: SLICEA.REG1.REGSET RESET
enum: SLICEA.REG1.LSRMODE LSR
enum: SLICEA.CEMUX CE
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
.tile R20C69:PLC2
arc: E1_H02E0301 W1_H02E0201
arc: H01W0100 W3_H06E0303
arc: N1_V02N0001 H01E0001
arc: N1_V02N0601 W3_H06E0303
arc: W1_H02W0501 W3_H06E0303
arc: B0 H02W0101
arc: C0 H02E0401
arc: CE0 H02E0101
arc: CLK0 G_HPBX0000
arc: D0 H01E0101
arc: E3_H06E0003 Q0
arc: F0 F0_SLICE
arc: LSR0 E1_H02W0301
arc: MUXCLK0 CLK0
arc: MUXLSR0 LSR0
word: SLICEA.K0.INIT 0000110000001111
enum: SLICEA.MODE LOGIC
enum: SLICEA.CCU2.INJECT1_0 _NONE_
enum: SLICEA.A0MUX 1
enum: SLICEA.GSR DISABLED
enum: SLICEA.REG0.SD 1
enum: SLICEA.REG0.REGSET RESET
enum: SLICEA.REG0.LSRMODE LSR
enum: SLICEA.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: CLK0.CLKMUX CLK
.tile R20C70:PLC2
arc: E1_H02E0101 E1_H01W0100
arc: E1_H02E0301 V01N0101
arc: W1_H02W0101 W3_H06E0103
.tile R20C71:PLC2
arc: E1_H02E0201 V02N0201
arc: H00R0000 V02N0601
arc: H00R0100 E1_H02W0701
arc: N1_V02N0301 W1_H02E0301
arc: V00T0000 V02N0401
arc: W1_H02W0301 V02S0301
arc: A2 V01N0101
arc: A3 H00L0100
arc: A4 V00T0000
arc: A5 Q5
arc: A6 H00R0000
arc: A7 Q7
arc: B0 V02N0301
arc: B2 H00L0000
arc: B3 V01N0001
arc: B4 H02E0101
arc: B5 V02N0501
arc: B6 V00B0000
arc: B7 V02N0701
arc: CE1 H00R0100
arc: CE2 H00R0100
arc: CE3 H00R0100
arc: CLK0 G_HPBX0000
arc: E1_H01E0001 F3
arc: E1_H01E0101 F4
arc: E3_H06E0203 F7
arc: F2 F2_SLICE
arc: F3 F3_SLICE
arc: F4 F4_SLICE
arc: F5 F5_SLICE
arc: F6 F6_SLICE
arc: F7 F7_SLICE
arc: H00L0000 Q2
arc: H00L0100 Q3
arc: H01W0100 Q4
arc: LSR0 H02E0301
arc: LSR1 H02E0301
arc: MUXCLK1 CLK0
arc: MUXCLK2 CLK0
arc: MUXCLK3 CLK0
arc: MUXLSR1 LSR1
arc: MUXLSR2 LSR1
arc: MUXLSR3 LSR0
arc: N1_V01N0001 F3
arc: N1_V01N0101 F2
arc: N1_V02N0501 F7
arc: N1_V02N0601 F4
arc: N1_V02N0701 F5
arc: S1_V02S0501 F5
arc: V00B0000 Q6
arc: V01S0000 F2
arc: V01S0100 F6
word: SLICED.K1.INIT 0110011001101010
word: SLICED.K0.INIT 0110011001101100
word: SLICEC.K1.INIT 0110011001101010
word: SLICEC.K0.INIT 0110011001101100
word: SLICEB.K1.INIT 0110011001101010
word: SLICEB.K0.INIT 0110011001101100
word: SLICEA.K1.INIT 1111111111111111
word: SLICEA.K0.INIT 0000000000001100
enum: SLICED.MODE CCU2
enum: SLICED.CCU2.INJECT1_1 NO
enum: SLICED.C1MUX 1
enum: SLICED.D1MUX 1
enum: SLICED.MODE CCU2
enum: SLICED.CCU2.INJECT1_0 NO
enum: SLICED.C0MUX 1
enum: SLICED.D0MUX 1
enum: SLICEC.MODE CCU2
enum: SLICEC.CCU2.INJECT1_1 NO
enum: SLICEC.C1MUX 1
enum: SLICEC.D1MUX 1
enum: SLICEC.MODE CCU2
enum: SLICEC.CCU2.INJECT1_0 NO
enum: SLICEC.C0MUX 1
enum: SLICEC.D0MUX 1
enum: SLICEB.MODE CCU2
enum: SLICEB.CCU2.INJECT1_1 NO
enum: SLICEB.C1MUX 1
enum: SLICEB.D1MUX 1
enum: SLICEB.MODE CCU2
enum: SLICEB.CCU2.INJECT1_0 NO
enum: SLICEB.C0MUX 1
enum: SLICEB.D0MUX 1
enum: SLICEA.MODE CCU2
enum: SLICEA.CCU2.INJECT1_1 YES
enum: SLICEA.A1MUX 1
enum: SLICEA.B1MUX 1
enum: SLICEA.C1MUX 1
enum: SLICEA.D1MUX 1
enum: SLICEA.MODE CCU2
enum: SLICEA.CCU2.INJECT1_0 NO
enum: SLICEA.A0MUX 1
enum: SLICEA.C0MUX 1
enum: SLICEA.D0MUX 1
enum: SLICED.GSR DISABLED
enum: SLICED.REG1.SD 1
enum: SLICED.REG1.REGSET RESET
enum: SLICED.REG1.LSRMODE LSR
enum: SLICED.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICED.GSR DISABLED
enum: SLICED.REG0.SD 1
enum: SLICED.REG0.REGSET RESET
enum: SLICED.REG0.LSRMODE LSR
enum: SLICED.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEC.GSR DISABLED
enum: SLICEC.REG1.SD 1
enum: SLICEC.REG1.REGSET RESET
enum: SLICEC.REG1.LSRMODE LSR
enum: SLICEC.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEC.GSR DISABLED
enum: SLICEC.REG0.SD 1
enum: SLICEC.REG0.REGSET RESET
enum: SLICEC.REG0.LSRMODE LSR
enum: SLICEC.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEB.GSR DISABLED
enum: SLICEB.REG1.SD 1
enum: SLICEB.REG1.REGSET RESET
enum: SLICEB.REG1.LSRMODE LSR
enum: SLICEB.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEB.GSR DISABLED
enum: SLICEB.REG0.SD 1
enum: SLICEB.REG0.REGSET RESET
enum: SLICEB.REG0.LSRMODE LSR
enum: SLICEB.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
.tile R20C72:PLC2
arc: E3_H06E0103 H01E0101
arc: E3_H06E0203 H01E0001
arc: H00R0000 V02N0401
arc: H00R0100 H02W0701
arc: V00T0000 V02N0601
arc: A0 V01N0101
arc: A1 H02W0501
arc: A2 E1_H01E0001
arc: A3 H00L0100
arc: A4 V00T0000
arc: A5 Q5
arc: A6 H00R0000
arc: A7 Q7
arc: B0 H01W0100
arc: B1 V02N0301
arc: B2 V01N0001
arc: B3 V02N0101
arc: B4 V01S0000
arc: B5 V02N0701
arc: B6 V00B0000
arc: B7 V02N0501
arc: CE0 H00R0100
arc: CE1 H00R0100
arc: CE2 H00R0100
arc: CE3 H00R0100
arc: CLK0 G_HPBX0000
arc: E1_H01E0001 Q2
arc: E1_H01E0101 Q1
arc: E3_H06E0003 F0
arc: F0 F0_SLICE
arc: F1 F1_SLICE
arc: F2 F2_SLICE
arc: F3 F3_SLICE
arc: F4 F4_SLICE
arc: F5 F5_SLICE
arc: F6 F6_SLICE
arc: F7 F7_SLICE
arc: H00L0100 Q3
arc: H01W0100 Q0
arc: LSR0 W1_H02E0301
arc: LSR1 W1_H02E0301
arc: MUXCLK0 CLK0
arc: MUXCLK1 CLK0
arc: MUXCLK2 CLK0
arc: MUXCLK3 CLK0
arc: MUXLSR0 LSR1
arc: MUXLSR1 LSR0
arc: MUXLSR2 LSR0
arc: MUXLSR3 LSR0
arc: N1_V01N0001 F2
arc: N1_V01N0101 F0
arc: N1_V02N0101 F3
arc: N1_V02N0301 F1
arc: N1_V02N0401 F4
arc: N1_V02N0501 F7
arc: N1_V02N0601 F6
arc: N1_V02N0701 F5
arc: V00B0000 Q6
arc: V01S0000 Q4
word: SLICED.K1.INIT 0110011001101010
word: SLICED.K0.INIT 0110011001101100
word: SLICEC.K1.INIT 0110011001101010
word: SLICEC.K0.INIT 0110011001101100
word: SLICEB.K1.INIT 0110011001101010
word: SLICEB.K0.INIT 0110011001101010
word: SLICEA.K1.INIT 0110011001101010
word: SLICEA.K0.INIT 0110011001101100
enum: SLICED.MODE CCU2
enum: SLICED.CCU2.INJECT1_1 NO
enum: SLICED.C1MUX 1
enum: SLICED.D1MUX 1
enum: SLICED.MODE CCU2
enum: SLICED.CCU2.INJECT1_0 NO
enum: SLICED.C0MUX 1
enum: SLICED.D0MUX 1
enum: SLICEC.MODE CCU2
enum: SLICEC.CCU2.INJECT1_1 NO
enum: SLICEC.C1MUX 1
enum: SLICEC.D1MUX 1
enum: SLICEC.MODE CCU2
enum: SLICEC.CCU2.INJECT1_0 NO
enum: SLICEC.C0MUX 1
enum: SLICEC.D0MUX 1
enum: SLICEB.MODE CCU2
enum: SLICEB.CCU2.INJECT1_1 NO
enum: SLICEB.C1MUX 1
enum: SLICEB.D1MUX 1
enum: SLICEB.MODE CCU2
enum: SLICEB.CCU2.INJECT1_0 NO
enum: SLICEB.C0MUX 1
enum: SLICEB.D0MUX 1
enum: SLICEA.MODE CCU2
enum: SLICEA.CCU2.INJECT1_1 NO
enum: SLICEA.C1MUX 1
enum: SLICEA.D1MUX 1
enum: SLICEA.MODE CCU2
enum: SLICEA.CCU2.INJECT1_0 NO
enum: SLICEA.C0MUX 1
enum: SLICEA.D0MUX 1
enum: SLICED.GSR DISABLED
enum: SLICED.REG1.SD 1
enum: SLICED.REG1.REGSET RESET
enum: SLICED.REG1.LSRMODE LSR
enum: SLICED.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICED.GSR DISABLED
enum: SLICED.REG0.SD 1
enum: SLICED.REG0.REGSET RESET
enum: SLICED.REG0.LSRMODE LSR
enum: SLICED.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEC.GSR DISABLED
enum: SLICEC.REG1.SD 1
enum: SLICEC.REG1.REGSET RESET
enum: SLICEC.REG1.LSRMODE LSR
enum: SLICEC.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEC.GSR DISABLED
enum: SLICEC.REG0.SD 1
enum: SLICEC.REG0.REGSET RESET
enum: SLICEC.REG0.LSRMODE LSR
enum: SLICEC.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEB.GSR DISABLED
enum: SLICEB.REG1.SD 1
enum: SLICEB.REG1.REGSET RESET
enum: SLICEB.REG1.LSRMODE LSR
enum: SLICEB.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEB.GSR DISABLED
enum: SLICEB.REG0.SD 1
enum: SLICEB.REG0.REGSET RESET
enum: SLICEB.REG0.LSRMODE LSR
enum: SLICEB.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEA.GSR DISABLED
enum: SLICEA.REG1.SD 1
enum: SLICEA.REG1.REGSET RESET
enum: SLICEA.REG1.LSRMODE LSR
enum: SLICEA.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEA.GSR DISABLED
enum: SLICEA.REG0.SD 1
enum: SLICEA.REG0.REGSET RESET
enum: SLICEA.REG0.LSRMODE LSR
enum: SLICEA.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
.tile R20C73:PLC2
arc: E1_H02E0301 W1_H02E0201
arc: H00R0000 E1_H02W0601
arc: S1_V02S0601 W3_H06E0303
arc: S1_V02S0701 W3_H06E0203
arc: V00B0000 V02N0201
arc: V00T0000 W1_H02E0201
arc: W1_H02W0501 H01E0101
arc: W1_H02W0701 E1_H02W0601
arc: A0 H00L0000
arc: A1 H00L0100
arc: A2 V01N0101
arc: A3 V01N0101
arc: A4 S1_V02N0101
arc: A5 V00B0000
arc: A6 H02W0501
arc: A7 Q7
arc: B0 V01N0001
arc: B1 V02N0301
arc: B2 H01W0100
arc: B3 Q3
arc: B4 V01S0000
arc: B5 V00B0100
arc: B6 V00B0000
arc: B7 V00B0000
arc: CE0 H00R0000
arc: CE1 H00R0000
arc: CE2 H00R0000
arc: CE3 H00R0000
arc: CLK0 G_HPBX0000
arc: E1_H01E0101 Q6
arc: F0 F0_SLICE
arc: F1 F1_SLICE
arc: F2 F2_SLICE
arc: F3 F3_SLICE
arc: F4 F4_SLICE
arc: F5 F5_SLICE
arc: F6 F6_SLICE
arc: F7 F7_SLICE
arc: H00L0000 Q0
arc: H00L0100 Q1
arc: H01W0100 Q2
arc: LSR0 V00T0000
arc: LSR1 V00T0000
arc: MUXCLK0 CLK0
arc: MUXCLK1 CLK0
arc: MUXCLK2 CLK0
arc: MUXCLK3 CLK0
arc: MUXLSR0 LSR1
arc: MUXLSR1 LSR1
arc: MUXLSR2 LSR1
arc: MUXLSR3 LSR0
arc: N1_V01N0001 F2
arc: N1_V01N0101 F0
arc: N1_V02N0101 F3
arc: N1_V02N0301 F1
arc: N1_V02N0501 F7
arc: N1_V02N0601 F6
arc: N1_V02N0701 F5
arc: V00B0100 Q5
arc: V01S0000 Q4
arc: V01S0100 F4
word: SLICED.K1.INIT 0110011001101010
word: SLICED.K0.INIT 0110011001101010
word: SLICEC.K1.INIT 0110011001101100
word: SLICEC.K0.INIT 0110011001101100
word: SLICEB.K1.INIT 0110011001101100
word: SLICEB.K0.INIT 0110011001101100
word: SLICEA.K1.INIT 0110011001101010
word: SLICEA.K0.INIT 0110011001101010
enum: SLICED.MODE CCU2
enum: SLICED.CCU2.INJECT1_1 NO
enum: SLICED.C1MUX 1
enum: SLICED.D1MUX 1
enum: SLICED.MODE CCU2
enum: SLICED.CCU2.INJECT1_0 NO
enum: SLICED.C0MUX 1
enum: SLICED.D0MUX 1
enum: SLICEC.MODE CCU2
enum: SLICEC.CCU2.INJECT1_1 NO
enum: SLICEC.C1MUX 1
enum: SLICEC.D1MUX 1
enum: SLICEC.MODE CCU2
enum: SLICEC.CCU2.INJECT1_0 NO
enum: SLICEC.C0MUX 1
enum: SLICEC.D0MUX 1
enum: SLICEB.MODE CCU2
enum: SLICEB.CCU2.INJECT1_1 NO
enum: SLICEB.C1MUX 1
enum: SLICEB.D1MUX 1
enum: SLICEB.MODE CCU2
enum: SLICEB.CCU2.INJECT1_0 NO
enum: SLICEB.C0MUX 1
enum: SLICEB.D0MUX 1
enum: SLICEA.MODE CCU2
enum: SLICEA.CCU2.INJECT1_1 NO
enum: SLICEA.C1MUX 1
enum: SLICEA.D1MUX 1
enum: SLICEA.MODE CCU2
enum: SLICEA.CCU2.INJECT1_0 NO
enum: SLICEA.C0MUX 1
enum: SLICEA.D0MUX 1
enum: SLICEC.GSR DISABLED
enum: SLICEC.REG1.SD 1
enum: SLICEC.REG1.REGSET RESET
enum: SLICEC.REG1.LSRMODE LSR
enum: SLICEC.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEC.GSR DISABLED
enum: SLICEC.REG0.SD 1
enum: SLICEC.REG0.REGSET RESET
enum: SLICEC.REG0.LSRMODE LSR
enum: SLICEC.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEB.GSR DISABLED
enum: SLICEB.REG1.SD 1
enum: SLICEB.REG1.REGSET RESET
enum: SLICEB.REG1.LSRMODE LSR
enum: SLICEB.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEB.GSR DISABLED
enum: SLICEB.REG0.SD 1
enum: SLICEB.REG0.REGSET RESET
enum: SLICEB.REG0.LSRMODE LSR
enum: SLICEB.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEA.GSR DISABLED
enum: SLICEA.REG1.SD 1
enum: SLICEA.REG1.REGSET RESET
enum: SLICEA.REG1.LSRMODE LSR
enum: SLICEA.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEA.GSR DISABLED
enum: SLICEA.REG0.SD 1
enum: SLICEA.REG0.REGSET RESET
enum: SLICEA.REG0.LSRMODE LSR
enum: SLICEA.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICED.GSR DISABLED
enum: SLICED.REG1.SD 1
enum: SLICED.REG1.REGSET RESET
enum: SLICED.REG1.LSRMODE LSR
enum: SLICED.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICED.GSR DISABLED
enum: SLICED.REG0.SD 1
enum: SLICED.REG0.REGSET RESET
enum: SLICED.REG0.LSRMODE LSR
enum: SLICED.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
.tile R20C74:PLC2
arc: E1_H02E0301 V02N0301
arc: E3_H06E0103 W3_H06E0103
arc: H00R0000 H02W0601
arc: S1_V02S0701 H06E0203
arc: W1_H02W0501 H01E0101
arc: A0 H00L0000
arc: A1 H00L0100
arc: A2 V02N0501
arc: A3 V02N0701
arc: A4 V00B0000
arc: A5 Q5
arc: A6 V02N0101
arc: A7 V02N0301
arc: B0 V02N0101
arc: B1 V02N0301
arc: B2 H01W0100
arc: B3 Q3
arc: B4 V02N0701
arc: B5 V02N0501
arc: B6 V01S0000
arc: B7 V00B0100
arc: CE0 H00R0000
arc: CE1 H00R0000
arc: CE2 H00R0000
arc: CE3 H00R0000
arc: CLK0 G_HPBX0000
arc: F0 F0_SLICE
arc: F1 F1_SLICE
arc: F2 F2_SLICE
arc: F3 F3_SLICE
arc: F4 F4_SLICE
arc: F5 F5_SLICE
arc: F6 F6_SLICE
arc: F7 F7_SLICE
arc: H00L0000 Q0
arc: H00L0100 Q1
arc: H01W0100 Q2
arc: LSR0 H02E0301
arc: LSR1 H02E0301
arc: MUXCLK0 CLK0
arc: MUXCLK1 CLK0
arc: MUXCLK2 CLK0
arc: MUXCLK3 CLK0
arc: MUXLSR0 LSR1
arc: MUXLSR1 LSR0
arc: MUXLSR2 LSR0
arc: MUXLSR3 LSR0
arc: N1_V01N0001 F2
arc: N1_V01N0101 F0
arc: N1_V02N0101 F1
arc: N1_V02N0301 F3
arc: N1_V02N0401 F4
arc: N1_V02N0501 F7
arc: N1_V02N0601 F6
arc: N1_V02N0701 F5
arc: V00B0000 Q4
arc: V00B0100 Q7
arc: V01S0000 Q6
word: SLICED.K1.INIT 0110011001101100
word: SLICED.K0.INIT 0110011001101100
word: SLICEC.K1.INIT 0110011001101010
word: SLICEC.K0.INIT 0110011001101010
word: SLICEB.K1.INIT 0110011001101100
word: SLICEB.K0.INIT 0110011001101100
word: SLICEA.K1.INIT 0110011001101010
word: SLICEA.K0.INIT 0110011001101010
enum: SLICED.MODE CCU2
enum: SLICED.CCU2.INJECT1_1 NO
enum: SLICED.C1MUX 1
enum: SLICED.D1MUX 1
enum: SLICED.MODE CCU2
enum: SLICED.CCU2.INJECT1_0 NO
enum: SLICED.C0MUX 1
enum: SLICED.D0MUX 1
enum: SLICEC.MODE CCU2
enum: SLICEC.CCU2.INJECT1_1 NO
enum: SLICEC.C1MUX 1
enum: SLICEC.D1MUX 1
enum: SLICEC.MODE CCU2
enum: SLICEC.CCU2.INJECT1_0 NO
enum: SLICEC.C0MUX 1
enum: SLICEC.D0MUX 1
enum: SLICEB.MODE CCU2
enum: SLICEB.CCU2.INJECT1_1 NO
enum: SLICEB.C1MUX 1
enum: SLICEB.D1MUX 1
enum: SLICEB.MODE CCU2
enum: SLICEB.CCU2.INJECT1_0 NO
enum: SLICEB.C0MUX 1
enum: SLICEB.D0MUX 1
enum: SLICEA.MODE CCU2
enum: SLICEA.CCU2.INJECT1_1 NO
enum: SLICEA.C1MUX 1
enum: SLICEA.D1MUX 1
enum: SLICEA.MODE CCU2
enum: SLICEA.CCU2.INJECT1_0 NO
enum: SLICEA.C0MUX 1
enum: SLICEA.D0MUX 1
enum: SLICED.GSR DISABLED
enum: SLICED.REG0.SD 1
enum: SLICED.REG0.REGSET RESET
enum: SLICED.REG0.LSRMODE LSR
enum: SLICED.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEC.GSR DISABLED
enum: SLICEC.REG1.SD 1
enum: SLICEC.REG1.REGSET RESET
enum: SLICEC.REG1.LSRMODE LSR
enum: SLICEC.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEC.GSR DISABLED
enum: SLICEC.REG0.SD 1
enum: SLICEC.REG0.REGSET RESET
enum: SLICEC.REG0.LSRMODE LSR
enum: SLICEC.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEB.GSR DISABLED
enum: SLICEB.REG1.SD 1
enum: SLICEB.REG1.REGSET RESET
enum: SLICEB.REG1.LSRMODE LSR
enum: SLICEB.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEB.GSR DISABLED
enum: SLICEB.REG0.SD 1
enum: SLICEB.REG0.REGSET RESET
enum: SLICEB.REG0.LSRMODE LSR
enum: SLICEB.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEA.GSR DISABLED
enum: SLICEA.REG1.SD 1
enum: SLICEA.REG1.REGSET RESET
enum: SLICEA.REG1.LSRMODE LSR
enum: SLICEA.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEA.GSR DISABLED
enum: SLICEA.REG0.SD 1
enum: SLICEA.REG0.REGSET RESET
enum: SLICEA.REG0.LSRMODE LSR
enum: SLICEA.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICED.GSR DISABLED
enum: SLICED.REG1.SD 1
enum: SLICED.REG1.REGSET RESET
enum: SLICED.REG1.LSRMODE LSR
enum: SLICED.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
.tile R20C75:PLC2
arc: E3_H06E0103 W3_H06E0003
arc: E3_H06E0203 V01N0001
arc: H00R0000 V02N0601
arc: S1_V02S0001 H06E0003
arc: S1_V02S0101 H06E0103
arc: S1_V02S0401 H06E0203
arc: W1_H02W0601 V02N0601
arc: A0 H00L0000
arc: A1 H00L0100
arc: B0 H02E0301
arc: B1 H02E0301
arc: CE0 H00R0000
arc: CLK0 G_HPBX0000
arc: F0 F0_SLICE
arc: F1 F1_SLICE
arc: H00L0000 Q0
arc: H00L0100 Q1
arc: LSR0 E1_H02W0301
arc: MUXCLK0 CLK0
arc: MUXLSR0 LSR0
arc: S1_V02S0201 F0
arc: S1_V02S0301 F1
arc: V01S0000 F1
arc: V01S0100 F1
word: SLICEB.K1.INIT 0000000000001110
word: SLICEB.K0.INIT 0000000000000000
word: SLICEA.K1.INIT 0110011001101010
word: SLICEA.K0.INIT 0110011001101010
enum: SLICEB.MODE CCU2
enum: SLICEB.CCU2.INJECT1_1 NO
enum: SLICEB.A1MUX 1
enum: SLICEB.B1MUX 1
enum: SLICEB.C1MUX 1
enum: SLICEB.D1MUX 1
enum: SLICEB.MODE CCU2
enum: SLICEB.CCU2.INJECT1_0 NO
enum: SLICEB.A0MUX 1
enum: SLICEB.B0MUX 1
enum: SLICEB.C0MUX 1
enum: SLICEB.D0MUX 1
enum: SLICEA.MODE CCU2
enum: SLICEA.CCU2.INJECT1_1 NO
enum: SLICEA.C1MUX 1
enum: SLICEA.D1MUX 1
enum: SLICEA.MODE CCU2
enum: SLICEA.CCU2.INJECT1_0 NO
enum: SLICEA.C0MUX 1
enum: SLICEA.D0MUX 1
enum: SLICEA.GSR DISABLED
enum: SLICEA.REG1.SD 1
enum: SLICEA.REG1.REGSET RESET
enum: SLICEA.REG1.LSRMODE LSR
enum: SLICEA.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEA.GSR DISABLED
enum: SLICEA.REG0.SD 1
enum: SLICEA.REG0.REGSET RESET
enum: SLICEA.REG0.LSRMODE LSR
enum: SLICEA.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: CLK0.CLKMUX CLK
.tile R20C77:PLC2
arc: W1_H02W0301 V02N0301
.tile R20C80:PLC2
arc: E3_H06E0203 W3_H06E0103
.tile R20C81:PLC2
arc: E3_H06E0203 W3_H06E0103
arc: E3_H06E0303 W3_H06E0203
.tile R20C86:PLC2
arc: E1_H02E0701 W3_H06E0203
.tile R20C87:PLC2
arc: E1_H02E0501 W3_H06E0303
arc: E1_H02E0701 W3_H06E0203
.tile R20C88:PLC2
arc: E1_H02E0701 W1_H02E0701
.tile R21C14:PLC2
arc: W3_H06W0103 E1_H01W0100
.tile R21C15:PLC2
arc: H01W0100 E3_H06W0303
.tile R21C17:PLC2
arc: E1_H02E0701 V02N0701
arc: H00R0000 N1_V02S0401
arc: V00T0000 N1_V02S0601
arc: CE0 H00R0000
arc: CLK0 G_HPBX0000
arc: E1_H01E0101 F0
arc: E3_H06E0003 F0
arc: F0 F0_SLICE
arc: LSR0 V00T0000
arc: MUXCLK0 CLK0
arc: MUXLSR0 LSR0
arc: S3_V06S0003 Q0
word: SLICEA.K0.INIT 0000000000000000
enum: SLICEA.GSR DISABLED
enum: SLICEA.REG0.SD 1
enum: SLICEA.REG0.REGSET RESET
enum: SLICEA.REG0.LSRMODE LSR
enum: SLICEA.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEA.MODE LOGIC
enum: SLICEA.CCU2.INJECT1_0 _NONE_
enum: SLICEA.A0MUX 1
enum: SLICEA.B0MUX 1
enum: SLICEA.C0MUX 1
enum: SLICEA.D0MUX 1
.tile R21C18:PLC2
arc: E1_H02E0001 V02N0001
arc: E1_H02E0101 H01E0101
arc: E1_H02E0201 V02N0201
arc: E1_H02E0301 V02N0301
arc: E1_H02E0401 V01N0001
arc: E1_H02E0501 V02N0501
arc: E1_H02E0601 E1_H01W0000
arc: E1_H02E0701 V01N0101
arc: N1_V02N0001 E1_H01W0000
arc: N1_V02N0201 H06W0103
arc: N1_V02N0301 H01E0101
arc: N1_V02N0501 E1_H02W0501
arc: N1_V02N0601 E1_H01W0000
arc: N1_V02N0701 H06W0203
arc: A0 V02S0501
arc: C0 H02W0601
arc: CE0 H02W0101
arc: CLK0 G_HPBX0000
arc: D0 H02W0201
arc: E1_H01E0101 Q0
arc: F0 F0_SLICE
arc: LSR0 H02W0301
arc: MUXCLK0 CLK0
arc: MUXLSR0 LSR0
word: SLICEA.K0.INIT 1111000010101010
enum: SLICEA.GSR DISABLED
enum: SLICEA.REG0.SD 1
enum: SLICEA.REG0.REGSET RESET
enum: SLICEA.REG0.LSRMODE LSR
enum: SLICEA.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEA.MODE LOGIC
enum: SLICEA.CCU2.INJECT1_0 _NONE_
enum: SLICEA.B0MUX 1
.tile R21C19:PLC2
arc: E1_H02E0101 E3_H06W0103
arc: E1_H02E0301 V02N0301
arc: E1_H02E0401 V01N0001
arc: E1_H02E0501 V01N0101
arc: E1_H02E0601 V02N0601
arc: E1_H02E0701 W1_H02E0701
arc: H00L0000 E1_H02W0001
arc: H01W0000 E3_H06W0103
arc: N1_V02N0001 E1_H02W0001
arc: N1_V02N0101 E3_H06W0103
arc: N1_V02N0201 E3_H06W0103
arc: N1_V02N0401 E1_H01W0000
arc: N1_V02N0501 E1_H01W0100
arc: N1_V02N0701 H01E0101
arc: W1_H02W0101 E1_H02W0001
arc: W1_H02W0201 E3_H06W0103
arc: W1_H02W0601 V06S0303
arc: A0 V02S0501
arc: A3 N1_V02S0501
arc: B3 S1_V02N0301
arc: C0 H02E0601
arc: CE0 H00L0000
arc: CLK0 G_HPBX0000
arc: D0 V02S0001
arc: D3 E1_H02W0001
arc: E1_H01E0001 F3
arc: E1_H01E0101 Q0
arc: E3_H06E0003 F3
arc: F0 F0_SLICE
arc: F3 F3_SLICE
arc: LSR1 V00T0100
arc: MUXCLK0 CLK0
arc: MUXLSR0 LSR1
arc: N1_V02N0301 F3
arc: V00T0100 F3
arc: W1_H02W0301 F3
word: SLICEA.K0.INIT 1111101000001010
word: SLICEB.K1.INIT 1010101011101110
enum: SLICEA.GSR DISABLED
enum: SLICEA.REG0.SD 1
enum: SLICEA.REG0.REGSET RESET
enum: SLICEA.REG0.LSRMODE LSR
enum: SLICEA.CEMUX CE
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEA.MODE LOGIC
enum: SLICEA.CCU2.INJECT1_0 _NONE_
enum: SLICEA.B0MUX 1
enum: SLICEB.MODE LOGIC
enum: SLICEB.CCU2.INJECT1_1 _NONE_
enum: SLICEB.C1MUX 1
.tile R21C20:PLC2
arc: E1_H02E0301 W1_H02E0201
arc: E1_H02E0501 W1_H02E0401
arc: E1_H02E0701 W1_H02E0701
arc: H00L0000 W1_H02E0001
arc: H00R0000 E1_H02W0401
arc: N1_V02N0001 H02W0001
arc: N1_V02N0101 H02E0101
arc: N1_V02N0201 E1_H01W0000
arc: N1_V02N0301 H01E0101
arc: N1_V02N0401 H01E0001
arc: N1_V02N0501 E1_H01W0100
arc: N1_V02N0701 H02W0701
arc: V00B0000 E1_H02W0601
arc: V00B0100 W1_H02E0501
arc: V00T0000 E1_H02W0001
arc: A2 V02S0501
arc: A3 H02E0701
arc: A4 V00T0000
arc: A5 V02N0101
arc: A6 H00L0000
arc: A7 H00R0000
arc: B0 W1_H02E0101
arc: B2 E1_H02W0101
arc: B3 S1_V02N0101
arc: B4 V02N0501
arc: B5 V00B0100
arc: B6 V00B0000
arc: B7 W1_H02E0301
arc: E1_H01E0101 F4
arc: F2 F2_SLICE
arc: F3 F3_SLICE
arc: F4 F4_SLICE
arc: F5 F5_SLICE
arc: F6 F6_SLICE
arc: F7 F7_SLICE
arc: H01W0000 F3
arc: H01W0100 F6
arc: N1_V01N0101 F7
arc: V01S0100 F2
arc: W1_H02W0501 F5
word: SLICED.K1.INIT 0110011001101100
word: SLICED.K0.INIT 0110011001101010
word: SLICEC.K1.INIT 0110011001101100
word: SLICEC.K0.INIT 0110011001101100
word: SLICEB.K1.INIT 0110011001101010
word: SLICEB.K0.INIT 0110011001101010
word: SLICEA.K1.INIT 1111111111111111
word: SLICEA.K0.INIT 0000000000001100
enum: SLICED.MODE CCU2
enum: SLICED.CCU2.INJECT1_1 NO
enum: SLICED.C1MUX 1
enum: SLICED.D1MUX 1
enum: SLICED.MODE CCU2
enum: SLICED.CCU2.INJECT1_0 NO
enum: SLICED.C0MUX 1
enum: SLICED.D0MUX 1
enum: SLICEC.MODE CCU2
enum: SLICEC.CCU2.INJECT1_1 NO
enum: SLICEC.C1MUX 1
enum: SLICEC.D1MUX 1
enum: SLICEC.MODE CCU2
enum: SLICEC.CCU2.INJECT1_0 NO
enum: SLICEC.C0MUX 1
enum: SLICEC.D0MUX 1
enum: SLICEB.MODE CCU2
enum: SLICEB.CCU2.INJECT1_1 NO
enum: SLICEB.C1MUX 1
enum: SLICEB.D1MUX 1
enum: SLICEB.MODE CCU2
enum: SLICEB.CCU2.INJECT1_0 NO
enum: SLICEB.C0MUX 1
enum: SLICEB.D0MUX 1
enum: SLICEA.MODE CCU2
enum: SLICEA.CCU2.INJECT1_1 YES
enum: SLICEA.A1MUX 1
enum: SLICEA.B1MUX 1
enum: SLICEA.C1MUX 1
enum: SLICEA.D1MUX 1
enum: SLICEA.MODE CCU2
enum: SLICEA.CCU2.INJECT1_0 NO
enum: SLICEA.A0MUX 1
enum: SLICEA.C0MUX 1
enum: SLICEA.D0MUX 1
.tile R21C21:PLC2
arc: E1_H01E0001 E3_H06W0003
arc: E1_H02E0501 W1_H02E0501
arc: H00L0000 E1_H02W0201
arc: H00R0000 W1_H02E0401
arc: N1_V02N0001 E3_H06W0003
arc: N1_V02N0101 H06W0103
arc: N1_V02N0401 E1_H02W0401
arc: N1_V02N0501 H01E0101
arc: N1_V02N0601 E1_H01W0000
arc: N1_V02N0701 E1_H01W0100
arc: S1_V02S0001 E1_H02W0001
arc: V00B0000 W1_H02E0601
arc: W1_H02W0001 E3_H06W0003
arc: W3_H06W0103 E3_H06W0003
arc: W3_H06W0303 E3_H06W0203
arc: A0 E1_H02W0501
arc: A1 H02E0501
arc: A2 V02N0701
arc: A3 V02N0501
arc: A4 H02E0701
arc: A5 V00B0000
arc: A6 H00R0000
arc: A7 E1_H02W0701
arc: B0 H02E0301
arc: B1 V02N0301
arc: B2 H00L0000
arc: B3 V02N0101
arc: B4 E1_H02W0101
arc: B5 E1_H02W0301
arc: B6 H02W0301
arc: B7 W1_H02E0301
arc: E1_H01E0101 F6
arc: E1_H02E0101 F1
arc: F0 F0_SLICE
arc: F1 F1_SLICE
arc: F2 F2_SLICE
arc: F3 F3_SLICE
arc: F4 F4_SLICE
arc: F5 F5_SLICE
arc: F6 F6_SLICE
arc: F7 F7_SLICE
arc: H01W0000 F3
arc: H01W0100 F0
arc: N1_V01N0101 F5
arc: V01S0100 F2
arc: W1_H02W0701 F7
arc: W3_H06W0203 F4
word: SLICED.K1.INIT 0110011001101100
word: SLICED.K0.INIT 0110011001101010
word: SLICEC.K1.INIT 0110011001101010
word: SLICEC.K0.INIT 0110011001101010
word: SLICEB.K1.INIT 0110011001101010
word: SLICEB.K0.INIT 0110011001101010
word: SLICEA.K1.INIT 0110011001101010
word: SLICEA.K0.INIT 0110011001101100
enum: SLICED.MODE CCU2
enum: SLICED.CCU2.INJECT1_1 NO
enum: SLICED.C1MUX 1
enum: SLICED.D1MUX 1
enum: SLICED.MODE CCU2
enum: SLICED.CCU2.INJECT1_0 NO
enum: SLICED.C0MUX 1
enum: SLICED.D0MUX 1
enum: SLICEC.MODE CCU2
enum: SLICEC.CCU2.INJECT1_1 NO
enum: SLICEC.C1MUX 1
enum: SLICEC.D1MUX 1
enum: SLICEC.MODE CCU2
enum: SLICEC.CCU2.INJECT1_0 NO
enum: SLICEC.C0MUX 1
enum: SLICEC.D0MUX 1
enum: SLICEB.MODE CCU2
enum: SLICEB.CCU2.INJECT1_1 NO
enum: SLICEB.C1MUX 1
enum: SLICEB.D1MUX 1
enum: SLICEB.MODE CCU2
enum: SLICEB.CCU2.INJECT1_0 NO
enum: SLICEB.C0MUX 1
enum: SLICEB.D0MUX 1
enum: SLICEA.MODE CCU2
enum: SLICEA.CCU2.INJECT1_1 NO
enum: SLICEA.C1MUX 1
enum: SLICEA.D1MUX 1
enum: SLICEA.MODE CCU2
enum: SLICEA.CCU2.INJECT1_0 NO
enum: SLICEA.C0MUX 1
enum: SLICEA.D0MUX 1
.tile R21C22:PLC2
arc: N1_V02N0101 H02E0101
arc: N1_V02N0201 H06W0103
arc: N1_V02N0301 H06E0003
arc: N1_V02N0401 N1_V01S0000
arc: N1_V02N0601 H01E0001
arc: N1_V02N0701 H01E0101
arc: S1_V02S0001 H02W0001
arc: W1_H02W0001 V02N0001
arc: W1_H02W0101 V01N0101
arc: W1_H02W0301 E1_H02W0201
arc: W1_H02W0401 V01N0001
arc: W1_H02W0601 V02N0601
arc: A0 H02E0501
arc: A1 E1_H02W0701
arc: A2 E1_H02W0701
arc: B0 V02N0101
arc: B1 V02N0301
arc: B2 V02N0301
arc: E1_H01E0101 F2
arc: F0 F0_SLICE
arc: F1 F1_SLICE
arc: F2 F2_SLICE
arc: H01W0000 F0
arc: H01W0100 F1
arc: N1_V01N0001 F2
arc: N1_V01N0101 F2
arc: N1_V02N0001 F2
word: SLICEC.K1.INIT 0000000000001110
word: SLICEC.K0.INIT 0000000000000000
word: SLICEB.K1.INIT 0000000000000000
word: SLICEB.K0.INIT 0110011001101100
word: SLICEA.K1.INIT 0110011001101100
word: SLICEA.K0.INIT 0110011001101010
enum: SLICEC.MODE CCU2
enum: SLICEC.CCU2.INJECT1_1 NO
enum: SLICEC.A1MUX 1
enum: SLICEC.B1MUX 1
enum: SLICEC.C1MUX 1
enum: SLICEC.D1MUX 1
enum: SLICEC.MODE CCU2
enum: SLICEC.CCU2.INJECT1_0 NO
enum: SLICEC.A0MUX 1
enum: SLICEC.B0MUX 1
enum: SLICEC.C0MUX 1
enum: SLICEC.D0MUX 1
enum: SLICEB.MODE CCU2
enum: SLICEB.CCU2.INJECT1_1 NO
enum: SLICEB.A1MUX 1
enum: SLICEB.B1MUX 1
enum: SLICEB.C1MUX 1
enum: SLICEB.D1MUX 1
enum: SLICEB.MODE CCU2
enum: SLICEB.CCU2.INJECT1_0 NO
enum: SLICEB.C0MUX 1
enum: SLICEB.D0MUX 1
enum: SLICEA.MODE CCU2
enum: SLICEA.CCU2.INJECT1_1 NO
enum: SLICEA.C1MUX 1
enum: SLICEA.D1MUX 1
enum: SLICEA.MODE CCU2
enum: SLICEA.CCU2.INJECT1_0 NO
enum: SLICEA.C0MUX 1
enum: SLICEA.D0MUX 1
.tile R21C23:PLC2
arc: E1_H02E0301 W3_H06E0003
arc: E3_H06E0003 W3_H06E0003
arc: H00L0000 E1_H02W0001
arc: H00R0000 E1_H02W0401
arc: N1_V02N0101 E1_H02W0101
arc: N1_V02N0301 H01E0101
arc: N1_V02N0501 H01E0101
arc: W1_H02W0001 W3_H06E0003
arc: W1_H02W0101 V01N0101
arc: W1_H02W0201 V02N0201
arc: W1_H02W0301 V02N0301
arc: W1_H02W0401 E1_H02W0101
arc: W1_H02W0501 V02N0501
arc: W1_H02W0701 V02N0701
arc: B0 E1_H02W0101
arc: C0 N1_V01S0100
arc: CE0 H00L0000
arc: CE1 H00R0000
arc: CLK0 G_HPBX0000
arc: D0 V02S0001
arc: D2 Q2
arc: E1_H01E0001 Q2
arc: F0 F0_SLICE
arc: F2 F2_SLICE
arc: LSR0 E1_H02W0301
arc: MUXCLK0 CLK0
arc: MUXCLK1 CLK0
arc: MUXLSR0 LSR0
arc: MUXLSR1 LSR0
arc: N1_V01N0001 Q0
word: SLICEB.K0.INIT 0000000011111111
word: SLICEA.K0.INIT 1111110000110000
enum: SLICEB.MODE LOGIC
enum: SLICEB.CCU2.INJECT1_0 _NONE_
enum: SLICEB.A0MUX 1
enum: SLICEB.B0MUX 1
enum: SLICEB.C0MUX 1
enum: SLICEB.GSR DISABLED
enum: SLICEB.REG0.SD 1
enum: SLICEB.REG0.REGSET RESET
enum: SLICEB.REG0.LSRMODE LSR
enum: SLICEB.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEA.GSR DISABLED
enum: SLICEA.REG0.SD 1
enum: SLICEA.REG0.REGSET RESET
enum: SLICEA.REG0.LSRMODE LSR
enum: SLICEA.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEA.MODE LOGIC
enum: SLICEA.CCU2.INJECT1_0 _NONE_
enum: SLICEA.A0MUX 1
.tile R21C24:PLC2
arc: N1_V02N0101 E1_H01W0100
arc: N1_V02N0301 H06W0003
arc: N1_V02N0401 E1_H01W0000
arc: W1_H02W0201 V02N0201
arc: W1_H02W0701 V02N0701
arc: W3_H06W0103 E1_H01W0100
arc: A2 H01E0001
arc: A4 V00B0000
arc: A5 Q5
arc: A6 H00R0000
arc: A7 Q7
arc: B0 H02E0301
arc: B3 Q3
arc: CE1 E1_H02W0101
arc: CE2 E1_H02W0101
arc: CE3 E1_H02W0101
arc: CLK0 G_HPBX0000
arc: F3 F3_SLICE
arc: F4 F4_SLICE
arc: F5 F5_SLICE
arc: F6 F6_SLICE
arc: F7 F7_SLICE
arc: H00R0000 Q6
arc: LSR0 H02W0301
arc: LSR1 H02W0301
arc: MUXCLK1 CLK0
arc: MUXCLK2 CLK0
arc: MUXCLK3 CLK0
arc: MUXLSR1 LSR1
arc: MUXLSR2 LSR0
arc: MUXLSR3 LSR0
arc: V00B0000 Q4
word: SLICED.K1.INIT 1010101010100000
word: SLICED.K0.INIT 1010101010100000
word: SLICEC.K1.INIT 1010101010100000
word: SLICEC.K0.INIT 1010101010100000
word: SLICEB.K1.INIT 1100110011000000
word: SLICEB.K0.INIT 0110011001101100
word: SLICEA.K1.INIT 1111111111111111
word: SLICEA.K0.INIT 0000000000001100
enum: SLICED.MODE CCU2
enum: SLICED.CCU2.INJECT1_1 NO
enum: SLICED.B1MUX 1
enum: SLICED.C1MUX 1
enum: SLICED.D1MUX 1
enum: SLICED.MODE CCU2
enum: SLICED.CCU2.INJECT1_0 NO
enum: SLICED.B0MUX 1
enum: SLICED.C0MUX 1
enum: SLICED.D0MUX 1
enum: SLICEC.MODE CCU2
enum: SLICEC.CCU2.INJECT1_1 NO
enum: SLICEC.B1MUX 1
enum: SLICEC.C1MUX 1
enum: SLICEC.D1MUX 1
enum: SLICEC.MODE CCU2
enum: SLICEC.CCU2.INJECT1_0 NO
enum: SLICEC.B0MUX 1
enum: SLICEC.C0MUX 1
enum: SLICEC.D0MUX 1
enum: SLICEB.MODE CCU2
enum: SLICEB.CCU2.INJECT1_1 NO
enum: SLICEB.A1MUX 1
enum: SLICEB.C1MUX 1
enum: SLICEB.D1MUX 1
enum: SLICEB.MODE CCU2
enum: SLICEB.CCU2.INJECT1_0 NO
enum: SLICEB.B0MUX 1
enum: SLICEB.C0MUX 1
enum: SLICEB.D0MUX 1
enum: SLICEA.MODE CCU2
enum: SLICEA.CCU2.INJECT1_1 YES
enum: SLICEA.A1MUX 1
enum: SLICEA.B1MUX 1
enum: SLICEA.C1MUX 1
enum: SLICEA.D1MUX 1
enum: SLICEA.MODE CCU2
enum: SLICEA.CCU2.INJECT1_0 NO
enum: SLICEA.A0MUX 1
enum: SLICEA.C0MUX 1
enum: SLICEA.D0MUX 1
enum: SLICED.GSR DISABLED
enum: SLICED.REG1.SD 1
enum: SLICED.REG1.REGSET RESET
enum: SLICED.REG1.LSRMODE LSR
enum: SLICED.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICED.GSR DISABLED
enum: SLICED.REG0.SD 1
enum: SLICED.REG0.REGSET RESET
enum: SLICED.REG0.LSRMODE LSR
enum: SLICED.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEC.GSR DISABLED
enum: SLICEC.REG1.SD 1
enum: SLICEC.REG1.REGSET RESET
enum: SLICEC.REG1.LSRMODE LSR
enum: SLICEC.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEC.GSR DISABLED
enum: SLICEC.REG0.SD 1
enum: SLICEC.REG0.REGSET RESET
enum: SLICEC.REG0.LSRMODE LSR
enum: SLICEC.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEB.GSR DISABLED
enum: SLICEB.REG1.SD 1
enum: SLICEB.REG1.REGSET RESET
enum: SLICEB.REG1.LSRMODE LSR
enum: SLICEB.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
.tile R21C25:PLC2
arc: E1_H01E0001 W3_H06E0003
arc: V00B0000 H02W0401
arc: W1_H02W0001 E1_H02W0001
arc: W1_H02W0301 W3_H06E0003
arc: B0 V00T0000
arc: B4 F1
arc: CE0 H00R0000
arc: CLK0 G_HPBX0000
arc: D4 E1_H02W0001
arc: E1_H01E0101 F4
arc: E1_H02E0101 F1
arc: E3_H06E0103 F1
arc: F0 F0_SLICE
arc: F1 F1_SLICE
arc: F4 F4_SLICE
arc: H00R0000 F4
arc: H01W0000 F1
arc: H01W0100 F1
arc: LSR1 V00B0000
arc: MUXCLK0 CLK0
arc: MUXLSR0 LSR1
arc: V00T0000 Q0
arc: W1_H02W0101 F1
arc: W1_H02W0401 F4
arc: W3_H06W0103 F1
word: SLICEB.K1.INIT 0000000000001110
word: SLICEB.K0.INIT 0000000000000000
word: SLICEA.K1.INIT 0000000000000000
word: SLICEA.K0.INIT 1100110011000000
word: SLICEC.K0.INIT 0011001100000000
enum: SLICEB.MODE CCU2
enum: SLICEB.CCU2.INJECT1_1 NO
enum: SLICEB.A1MUX 1
enum: SLICEB.B1MUX 1
enum: SLICEB.C1MUX 1
enum: SLICEB.D1MUX 1
enum: SLICEB.MODE CCU2
enum: SLICEB.CCU2.INJECT1_0 NO
enum: SLICEB.A0MUX 1
enum: SLICEB.B0MUX 1
enum: SLICEB.C0MUX 1
enum: SLICEB.D0MUX 1
enum: SLICEA.MODE CCU2
enum: SLICEA.CCU2.INJECT1_1 NO
enum: SLICEA.A1MUX 1
enum: SLICEA.B1MUX 1
enum: SLICEA.C1MUX 1
enum: SLICEA.D1MUX 1
enum: SLICEA.MODE CCU2
enum: SLICEA.CCU2.INJECT1_0 NO
enum: SLICEA.A0MUX 1
enum: SLICEA.C0MUX 1
enum: SLICEA.D0MUX 1
enum: SLICEC.MODE LOGIC
enum: SLICEC.CCU2.INJECT1_0 _NONE_
enum: SLICEC.A0MUX 1
enum: SLICEC.C0MUX 1
enum: SLICEA.GSR DISABLED
enum: SLICEA.REG0.SD 1
enum: SLICEA.REG0.REGSET RESET
enum: SLICEA.REG0.LSRMODE LSR
enum: SLICEA.CEMUX CE
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
.tile R21C26:PLC2
arc: E1_H02E0401 N1_V02S0401
arc: E1_H02E0601 S1_V02N0601
arc: W1_H02W0101 H01E0101
arc: W1_H02W0401 H01E0001
.tile R21C27:PLC2
arc: V00B0000 H02E0401
arc: W3_H06W0203 E3_H06W0103
arc: B0 W1_H02E0101
arc: C0 H02E0601
arc: CLK0 G_HPBX0000
arc: D0 Q0
arc: E3_H06E0003 Q0
arc: F0 F0_SLICE
arc: LSR1 V00B0000
arc: MUXCLK0 CLK0
arc: MUXLSR0 LSR1
arc: W1_H02W0001 Q0
arc: W3_H06W0003 Q0
word: SLICEA.K0.INIT 0011001111110000
enum: SLICEA.MODE LOGIC
enum: SLICEA.CCU2.INJECT1_0 _NONE_
enum: SLICEA.A0MUX 1
enum: SLICEA.GSR DISABLED
enum: SLICEA.REG0.SD 1
enum: SLICEA.REG0.REGSET RESET
enum: SLICEA.REG0.LSRMODE LSR
enum: SLICEA.CEMUX 1
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
.tile R21C29:PLC2
arc: E3_H06E0003 W3_H06E0003
.tile R21C31:PLC2
arc: E3_H06E0203 W3_H06E0103
.tile R21C33:PLC2
arc: E3_H06E0003 W3_H06E0003
arc: W3_H06W0103 E3_H06W0003
.tile R21C35:PLC2
arc: E3_H06E0103 W3_H06E0003
.tile R21C37:PLC2
arc: E3_H06E0203 W3_H06E0203
.tile R21C39:PLC2
arc: E3_H06E0103 W3_H06E0003
arc: W3_H06W0003 E3_H06W0003
.tile R21C41:PLC2
arc: E3_H06E0203 W3_H06E0103
.tile R21C43:PLC2
arc: E3_H06E0303 W3_H06E0203
.tile R21C45:PLC2
arc: E3_H06E0203 W3_H06E0103
arc: W3_H06W0003 E3_H06W0303
.tile R21C47:PLC2
arc: E3_H06E0303 W3_H06E0203
.tile R21C49:PLC2
arc: E3_H06E0003 W3_H06E0303
.tile R21C50:PLC2
arc: S3_V06S0303 H06E0303
.tile R21C51:PLC2
arc: E1_H02E0701 W3_H06E0203
arc: E3_H06E0303 W3_H06E0203
arc: W3_H06W0303 E3_H06W0303
.tile R21C52:PLC2
arc: S1_V02S0001 H06E0003
.tile R21C53:PLC2
arc: E3_H06E0303 W3_H06E0303
arc: S1_V02S0701 W1_H02E0701
arc: S3_V06S0303 W3_H06E0303
.tile R21C57:PLC2
arc: E3_H06E0003 W3_H06E0303
arc: W3_H06W0303 E3_H06W0303
.tile R21C59:PLC2
arc: E3_H06E0003 W3_H06E0303
.tile R21C60:PLC2
arc: S1_V02S0301 H06E0003
.tile R21C61:PLC2
arc: E1_H02E0601 S1_V02N0601
.tile R21C62:PLC2
arc: E1_H02E0101 V02N0101
arc: N1_V02N0301 H06E0003
arc: S1_V02S0301 H06E0003
arc: V00B0000 N1_V02S0201
arc: B0 V00T0000
arc: C0 H02E0601
arc: CLK0 G_HPBX0000
arc: D0 S1_V02N0201
arc: E1_H02E0001 Q0
arc: E3_H06E0003 Q0
arc: F0 F0_SLICE
arc: LSR0 V00B0000
arc: MUXCLK0 CLK0
arc: MUXLSR0 LSR0
arc: N1_V02N0001 Q0
arc: S3_V06S0003 Q0
arc: V00T0000 Q0
word: SLICEA.K0.INIT 0011000011111100
enum: SLICEA.MODE LOGIC
enum: SLICEA.CCU2.INJECT1_0 _NONE_
enum: SLICEA.A0MUX 1
enum: SLICEA.GSR DISABLED
enum: SLICEA.REG0.SD 1
enum: SLICEA.REG0.REGSET RESET
enum: SLICEA.REG0.LSRMODE LSR
enum: SLICEA.CEMUX 1
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: CLK0.CLKMUX CLK
.tile R21C63:PLC2
arc: E1_H02E0101 V02N0101
arc: E1_H02E0301 V02N0301
arc: N1_V02N0001 H02E0001
arc: N1_V02N0201 N1_V01S0000
arc: N1_V02N0401 S1_V02N0101
arc: W3_H06W0303 E3_H06W0203
arc: B2 N1_V02S0301
arc: C2 W1_H02E0601
arc: D2 H02E0001
arc: E1_H01E0001 F2
arc: E1_H01E0101 F2
arc: F2 F2_SLICE
arc: S1_V02S0201 F2
word: SLICEB.K0.INIT 1100110011111100
enum: SLICEB.MODE LOGIC
enum: SLICEB.CCU2.INJECT1_0 _NONE_
enum: SLICEB.A0MUX 1
.tile R21C64:PLC2
arc: E3_H06E0003 H01E0001
arc: H00R0000 V02N0601
arc: N1_V02N0301 H01E0101
arc: N1_V02N0701 H01E0101
arc: S1_V02S0301 H01E0101
arc: S3_V06S0303 H01E0101
arc: V00B0000 E1_H02W0601
arc: V00T0000 V02N0401
arc: A2 V01N0101
arc: A3 V02N0701
arc: A4 V00T0000
arc: A5 V02N0301
arc: A6 V02N0101
arc: A7 E1_H02W0701
arc: B0 H02W0301
arc: B2 H00R0000
arc: B3 V01N0001
arc: B4 H02E0101
arc: B5 V02N0501
arc: B6 V00B0000
arc: B7 W1_H02E0101
arc: F2 F2_SLICE
arc: F3 F3_SLICE
arc: F4 F4_SLICE
arc: F5 F5_SLICE
arc: F6 F6_SLICE
arc: F7 F7_SLICE
arc: N1_V01N0101 F5
arc: N1_V02N0001 F2
arc: N1_V02N0101 F3
arc: N1_V02N0401 F4
arc: N1_V02N0501 F7
arc: N1_V02N0601 F6
word: SLICED.K1.INIT 0110011001101100
word: SLICED.K0.INIT 0110011001101010
word: SLICEC.K1.INIT 0110011001101100
word: SLICEC.K0.INIT 0110011001101010
word: SLICEB.K1.INIT 0110011001101010
word: SLICEB.K0.INIT 0110011001101010
word: SLICEA.K1.INIT 1111111111111111
word: SLICEA.K0.INIT 0000000000001100
enum: SLICED.MODE CCU2
enum: SLICED.CCU2.INJECT1_1 NO
enum: SLICED.C1MUX 1
enum: SLICED.D1MUX 1
enum: SLICED.MODE CCU2
enum: SLICED.CCU2.INJECT1_0 NO
enum: SLICED.C0MUX 1
enum: SLICED.D0MUX 1
enum: SLICEC.MODE CCU2
enum: SLICEC.CCU2.INJECT1_1 NO
enum: SLICEC.C1MUX 1
enum: SLICEC.D1MUX 1
enum: SLICEC.MODE CCU2
enum: SLICEC.CCU2.INJECT1_0 NO
enum: SLICEC.C0MUX 1
enum: SLICEC.D0MUX 1
enum: SLICEB.MODE CCU2
enum: SLICEB.CCU2.INJECT1_1 NO
enum: SLICEB.C1MUX 1
enum: SLICEB.D1MUX 1
enum: SLICEB.MODE CCU2
enum: SLICEB.CCU2.INJECT1_0 NO
enum: SLICEB.C0MUX 1
enum: SLICEB.D0MUX 1
enum: SLICEA.MODE CCU2
enum: SLICEA.CCU2.INJECT1_1 YES
enum: SLICEA.A1MUX 1
enum: SLICEA.B1MUX 1
enum: SLICEA.C1MUX 1
enum: SLICEA.D1MUX 1
enum: SLICEA.MODE CCU2
enum: SLICEA.CCU2.INJECT1_0 NO
enum: SLICEA.A0MUX 1
enum: SLICEA.C0MUX 1
enum: SLICEA.D0MUX 1
.tile R21C65:PLC2
arc: E3_H06E0003 W3_H06E0003
arc: E3_H06E0103 W3_H06E0003
arc: H00L0000 V02N0201
arc: H00L0100 V02N0101
arc: H00R0000 V02N0401
arc: S1_V02S0301 W3_H06E0003
arc: S1_V02S0601 N1_V02S0301
arc: V00B0000 V02N0001
arc: V00T0000 V02N0601
arc: W1_H02W0301 W3_H06E0003
arc: A0 H00L0000
arc: A1 H00L0100
arc: A2 V01N0101
arc: A3 V02N0501
arc: A4 V00T0000
arc: A5 E1_H02W0701
arc: A6 E1_H02W0501
arc: A7 H02W0501
arc: B0 V00B0000
arc: B1 V02N0301
arc: B2 H00R0000
arc: B3 V01N0001
arc: B4 S1_V02N0501
arc: B5 V02N0701
arc: B6 W1_H02E0301
arc: B7 H02W0301
arc: F0 F0_SLICE
arc: F1 F1_SLICE
arc: F2 F2_SLICE
arc: F3 F3_SLICE
arc: F4 F4_SLICE
arc: F5 F5_SLICE
arc: F6 F6_SLICE
arc: F7 F7_SLICE
arc: N1_V01N0101 F0
arc: N1_V02N0001 F2
arc: N1_V02N0101 F1
arc: N1_V02N0301 F3
arc: N1_V02N0401 F4
arc: N1_V02N0501 F7
arc: N1_V02N0601 F6
arc: N1_V02N0701 F5
word: SLICED.K1.INIT 0110011001101010
word: SLICED.K0.INIT 0110011001101100
word: SLICEC.K1.INIT 0110011001101010
word: SLICEC.K0.INIT 0110011001101100
word: SLICEB.K1.INIT 0110011001101010
word: SLICEB.K0.INIT 0110011001101010
word: SLICEA.K1.INIT 0110011001101010
word: SLICEA.K0.INIT 0110011001101100
enum: SLICED.MODE CCU2
enum: SLICED.CCU2.INJECT1_1 NO
enum: SLICED.C1MUX 1
enum: SLICED.D1MUX 1
enum: SLICED.MODE CCU2
enum: SLICED.CCU2.INJECT1_0 NO
enum: SLICED.C0MUX 1
enum: SLICED.D0MUX 1
enum: SLICEC.MODE CCU2
enum: SLICEC.CCU2.INJECT1_1 NO
enum: SLICEC.C1MUX 1
enum: SLICEC.D1MUX 1
enum: SLICEC.MODE CCU2
enum: SLICEC.CCU2.INJECT1_0 NO
enum: SLICEC.C0MUX 1
enum: SLICEC.D0MUX 1
enum: SLICEB.MODE CCU2
enum: SLICEB.CCU2.INJECT1_1 NO
enum: SLICEB.C1MUX 1
enum: SLICEB.D1MUX 1
enum: SLICEB.MODE CCU2
enum: SLICEB.CCU2.INJECT1_0 NO
enum: SLICEB.C0MUX 1
enum: SLICEB.D0MUX 1
enum: SLICEA.MODE CCU2
enum: SLICEA.CCU2.INJECT1_1 NO
enum: SLICEA.C1MUX 1
enum: SLICEA.D1MUX 1
enum: SLICEA.MODE CCU2
enum: SLICEA.CCU2.INJECT1_0 NO
enum: SLICEA.C0MUX 1
enum: SLICEA.D0MUX 1
.tile R21C66:PLC2
arc: H00L0000 V02N0201
arc: H00L0100 V02N0101
arc: V00B0000 V02N0001
arc: W1_H02W0301 V02N0301
arc: W1_H02W0501 V01N0101
arc: W1_H02W0601 V02N0601
arc: W1_H02W0701 V02N0701
arc: A0 H00L0000
arc: A1 H00L0100
arc: A2 H00L0100
arc: B0 V00B0000
arc: B1 V01N0001
arc: B2 V01N0001
arc: E1_H01E0101 F2
arc: F0 F0_SLICE
arc: F1 F1_SLICE
arc: F2 F2_SLICE
arc: N1_V01N0101 F0
arc: N1_V02N0001 F2
arc: N1_V02N0201 F2
arc: N1_V02N0301 F1
word: SLICEC.K1.INIT 0000000000001110
word: SLICEC.K0.INIT 0000000000000000
word: SLICEB.K1.INIT 0000000000000000
word: SLICEB.K0.INIT 0110011001101100
word: SLICEA.K1.INIT 0110011001101100
word: SLICEA.K0.INIT 0110011001101010
enum: SLICEC.MODE CCU2
enum: SLICEC.CCU2.INJECT1_1 NO
enum: SLICEC.A1MUX 1
enum: SLICEC.B1MUX 1
enum: SLICEC.C1MUX 1
enum: SLICEC.D1MUX 1
enum: SLICEC.MODE CCU2
enum: SLICEC.CCU2.INJECT1_0 NO
enum: SLICEC.A0MUX 1
enum: SLICEC.B0MUX 1
enum: SLICEC.C0MUX 1
enum: SLICEC.D0MUX 1
enum: SLICEB.MODE CCU2
enum: SLICEB.CCU2.INJECT1_1 NO
enum: SLICEB.A1MUX 1
enum: SLICEB.B1MUX 1
enum: SLICEB.C1MUX 1
enum: SLICEB.D1MUX 1
enum: SLICEB.MODE CCU2
enum: SLICEB.CCU2.INJECT1_0 NO
enum: SLICEB.C0MUX 1
enum: SLICEB.D0MUX 1
enum: SLICEA.MODE CCU2
enum: SLICEA.CCU2.INJECT1_1 NO
enum: SLICEA.C1MUX 1
enum: SLICEA.D1MUX 1
enum: SLICEA.MODE CCU2
enum: SLICEA.CCU2.INJECT1_0 NO
enum: SLICEA.C0MUX 1
enum: SLICEA.D0MUX 1
.tile R21C67:PLC2
arc: N1_V02N0001 H06E0003
arc: N1_V02N0101 H01E0101
arc: N1_V02N0301 H01E0101
arc: N1_V02N0501 H01E0101
arc: N1_V02N0701 H01E0101
arc: W1_H02W0501 V02N0501
arc: W1_H02W0701 V02N0701
.tile R21C68:PLC2
arc: N1_V02N0001 W3_H06E0003
arc: S1_V02S0101 H06E0103
.tile R21C69:PLC2
arc: E1_H02E0001 S1_V02N0001
arc: E1_H02E0101 V02N0101
arc: E1_H02E0201 V02N0201
arc: E1_H02E0301 V02N0301
arc: E1_H02E0401 V02N0401
arc: E1_H02E0701 V01N0101
arc: W3_H06W0203 E3_H06W0203
.tile R21C70:PLC2
arc: E1_H02E0001 V02N0001
arc: E1_H02E0101 V02N0101
arc: E1_H02E0301 V01N0101
arc: E1_H02E0501 V02N0501
arc: E1_H02E0601 V01N0001
arc: E1_H02E0701 V02N0701
arc: H00L0100 H02W0301
arc: N1_V02N0301 W3_H06E0003
arc: B3 S1_V02N0301
arc: C3 H00L0100
arc: D3 H02E0001
arc: E1_H01E0001 F3
arc: F3 F3_SLICE
arc: N1_V01N0101 F3
arc: S3_V06S0003 F3
word: SLICEB.K1.INIT 1111000011111100
enum: SLICEB.MODE LOGIC
enum: SLICEB.CCU2.INJECT1_1 _NONE_
enum: SLICEB.A1MUX 1
.tile R21C71:PLC2
arc: E1_H01E0001 W3_H06E0003
arc: E1_H02E0101 W3_H06E0103
arc: E1_H02E0501 V02S0501
arc: E3_H06E0003 H01E0001
arc: E3_H06E0203 N1_V01S0000
arc: E3_H06E0303 N1_V01S0100
arc: H00R0000 E1_H02W0601
arc: N1_V02N0101 N1_V01S0100
arc: N1_V02N0201 H01E0001
arc: N1_V02N0301 W3_H06E0003
arc: S1_V02S0101 W3_H06E0103
arc: S1_V02S0401 H01E0001
arc: V00B0000 W1_H02E0401
arc: V00T0000 W1_H02E0201
arc: W1_H02W0301 N1_V02S0301
arc: A0 E1_H01E0001
arc: A2 W1_H02E0701
arc: A3 V02N0701
arc: A4 V00T0000
arc: A5 E1_H02W0701
arc: A6 V02N0301
arc: A7 V02N0101
arc: B2 E1_H02W0101
arc: B3 W1_H02E0101
arc: B4 H00R0000
arc: B5 W1_H02E0301
arc: B6 V00B0000
arc: B7 V02N0501
arc: F2 F2_SLICE
arc: F3 F3_SLICE
arc: F4 F4_SLICE
arc: F5 F5_SLICE
arc: F6 F6_SLICE
arc: F7 F7_SLICE
arc: N1_V01N0001 F3
arc: N1_V01N0101 F2
arc: N1_V02N0401 F4
arc: N1_V02N0501 F5
arc: N1_V02N0601 F6
arc: N1_V02N0701 F7
word: SLICED.K1.INIT 0110011001101100
word: SLICED.K0.INIT 0110011001101100
word: SLICEC.K1.INIT 0110011001101100
word: SLICEC.K0.INIT 0110011001101010
word: SLICEB.K1.INIT 0110011001101100
word: SLICEB.K0.INIT 0110011001101010
word: SLICEA.K1.INIT 1111111111111111
word: SLICEA.K0.INIT 0000000000001010
enum: SLICED.MODE CCU2
enum: SLICED.CCU2.INJECT1_1 NO
enum: SLICED.C1MUX 1
enum: SLICED.D1MUX 1
enum: SLICED.MODE CCU2
enum: SLICED.CCU2.INJECT1_0 NO
enum: SLICED.C0MUX 1
enum: SLICED.D0MUX 1
enum: SLICEC.MODE CCU2
enum: SLICEC.CCU2.INJECT1_1 NO
enum: SLICEC.C1MUX 1
enum: SLICEC.D1MUX 1
enum: SLICEC.MODE CCU2
enum: SLICEC.CCU2.INJECT1_0 NO
enum: SLICEC.C0MUX 1
enum: SLICEC.D0MUX 1
enum: SLICEB.MODE CCU2
enum: SLICEB.CCU2.INJECT1_1 NO
enum: SLICEB.C1MUX 1
enum: SLICEB.D1MUX 1
enum: SLICEB.MODE CCU2
enum: SLICEB.CCU2.INJECT1_0 NO
enum: SLICEB.C0MUX 1
enum: SLICEB.D0MUX 1
enum: SLICEA.MODE CCU2
enum: SLICEA.CCU2.INJECT1_1 YES
enum: SLICEA.A1MUX 1
enum: SLICEA.B1MUX 1
enum: SLICEA.C1MUX 1
enum: SLICEA.D1MUX 1
enum: SLICEA.MODE CCU2
enum: SLICEA.CCU2.INJECT1_0 NO
enum: SLICEA.B0MUX 1
enum: SLICEA.C0MUX 1
enum: SLICEA.D0MUX 1
.tile R21C72:PLC2
arc: E1_H02E0501 W1_H02E0501
arc: E3_H06E0003 H01E0001
arc: H00L0000 W1_H02E0001
arc: H00R0000 W1_H02E0601
arc: N1_V02N0201 H01E0001
arc: V00B0000 E1_H02W0401
arc: V00T0000 E1_H02W0001
arc: A0 V02N0501
arc: A1 V02N0701
arc: A2 H02W0501
arc: A3 E1_H02W0701
arc: A4 V00B0000
arc: A5 E1_H02W0501
arc: A6 V02N0301
arc: A7 W1_H02E0701
arc: B0 V00T0000
arc: B1 E1_H02W0301
arc: B2 H00L0000
arc: B3 V02N0101
arc: B4 H00R0000
arc: B5 W1_H02E0101
arc: B6 W1_H02E0301
arc: B7 E1_H02W0101
arc: F0 F0_SLICE
arc: F1 F1_SLICE
arc: F2 F2_SLICE
arc: F3 F3_SLICE
arc: F4 F4_SLICE
arc: F5 F5_SLICE
arc: F6 F6_SLICE
arc: F7 F7_SLICE
arc: N1_V01N0001 F2
arc: N1_V01N0101 F0
arc: N1_V02N0101 F3
arc: N1_V02N0301 F1
arc: N1_V02N0401 F6
arc: N1_V02N0501 F7
arc: N1_V02N0601 F4
arc: N1_V02N0701 F5
word: SLICED.K1.INIT 0110011001101010
word: SLICED.K0.INIT 0110011001101100
word: SLICEC.K1.INIT 0110011001101100
word: SLICEC.K0.INIT 0110011001101100
word: SLICEB.K1.INIT 0110011001101100
word: SLICEB.K0.INIT 0110011001101100
word: SLICEA.K1.INIT 0110011001101010
word: SLICEA.K0.INIT 0110011001101010
enum: SLICED.MODE CCU2
enum: SLICED.CCU2.INJECT1_1 NO
enum: SLICED.C1MUX 1
enum: SLICED.D1MUX 1
enum: SLICED.MODE CCU2
enum: SLICED.CCU2.INJECT1_0 NO
enum: SLICED.C0MUX 1
enum: SLICED.D0MUX 1
enum: SLICEC.MODE CCU2
enum: SLICEC.CCU2.INJECT1_1 NO
enum: SLICEC.C1MUX 1
enum: SLICEC.D1MUX 1
enum: SLICEC.MODE CCU2
enum: SLICEC.CCU2.INJECT1_0 NO
enum: SLICEC.C0MUX 1
enum: SLICEC.D0MUX 1
enum: SLICEB.MODE CCU2
enum: SLICEB.CCU2.INJECT1_1 NO
enum: SLICEB.C1MUX 1
enum: SLICEB.D1MUX 1
enum: SLICEB.MODE CCU2
enum: SLICEB.CCU2.INJECT1_0 NO
enum: SLICEB.C0MUX 1
enum: SLICEB.D0MUX 1
enum: SLICEA.MODE CCU2
enum: SLICEA.CCU2.INJECT1_1 NO
enum: SLICEA.C1MUX 1
enum: SLICEA.D1MUX 1
enum: SLICEA.MODE CCU2
enum: SLICEA.CCU2.INJECT1_0 NO
enum: SLICEA.C0MUX 1
enum: SLICEA.D0MUX 1
.tile R21C73:PLC2
arc: E1_H02E0001 W1_H02E0501
arc: E1_H02E0101 W1_H02E0101
arc: E1_H02E0601 S1_V02N0601
arc: N1_V02N0101 S1_V02N0001
arc: N1_V02N0701 N1_V01S0100
arc: V00T0000 V02N0401
arc: W1_H02W0101 V01N0101
arc: W1_H02W0501 E1_H02W0401
arc: W1_H02W0601 V02N0601
arc: W1_H02W0701 V02N0701
arc: A0 V02N0501
arc: A1 H02E0501
arc: A2 V00T0000
arc: B0 E1_H02W0101
arc: B1 E1_H02W0301
arc: B2 E1_H02W0301
arc: E1_H01E0101 F2
arc: F0 F0_SLICE
arc: F1 F1_SLICE
arc: F2 F2_SLICE
arc: N1_V01N0001 F0
arc: N1_V01N0101 F2
arc: N1_V02N0201 F2
arc: N1_V02N0301 F1
arc: V01S0100 F2
word: SLICEC.K1.INIT 0000000000001110
word: SLICEC.K0.INIT 0000000000000000
word: SLICEB.K1.INIT 0000000000000000
word: SLICEB.K0.INIT 0110011001101010
word: SLICEA.K1.INIT 0110011001101010
word: SLICEA.K0.INIT 0110011001101010
enum: SLICEC.MODE CCU2
enum: SLICEC.CCU2.INJECT1_1 NO
enum: SLICEC.A1MUX 1
enum: SLICEC.B1MUX 1
enum: SLICEC.C1MUX 1
enum: SLICEC.D1MUX 1
enum: SLICEC.MODE CCU2
enum: SLICEC.CCU2.INJECT1_0 NO
enum: SLICEC.A0MUX 1
enum: SLICEC.B0MUX 1
enum: SLICEC.C0MUX 1
enum: SLICEC.D0MUX 1
enum: SLICEB.MODE CCU2
enum: SLICEB.CCU2.INJECT1_1 NO
enum: SLICEB.A1MUX 1
enum: SLICEB.B1MUX 1
enum: SLICEB.C1MUX 1
enum: SLICEB.D1MUX 1
enum: SLICEB.MODE CCU2
enum: SLICEB.CCU2.INJECT1_0 NO
enum: SLICEB.C0MUX 1
enum: SLICEB.D0MUX 1
enum: SLICEA.MODE CCU2
enum: SLICEA.CCU2.INJECT1_1 NO
enum: SLICEA.C1MUX 1
enum: SLICEA.D1MUX 1
enum: SLICEA.MODE CCU2
enum: SLICEA.CCU2.INJECT1_0 NO
enum: SLICEA.C0MUX 1
enum: SLICEA.D0MUX 1
.tile R21C74:PLC2
arc: H00R0000 H02E0601
arc: N1_V02N0101 H01E0101
arc: N1_V02N0301 H01E0101
arc: N1_V02N0501 H01E0101
arc: N1_V02N0701 H01E0101
arc: V00B0000 N1_V02S0001
arc: V00B0100 H02W0501
arc: W1_H02W0001 V02N0001
arc: W1_H02W0101 V02N0101
arc: W1_H02W0301 V02N0301
arc: W1_H02W0401 V02N0401
arc: W1_H02W0501 V02N0501
arc: W1_H02W0701 V01N0101
arc: A0 V02S0701
arc: C0 H02W0601
arc: CE0 H00R0000
arc: CLK0 G_HPBX0000
arc: D0 V00B0100
arc: E3_H06E0003 Q0
arc: F0 F0_SLICE
arc: LSR1 V00B0000
arc: MUXCLK0 CLK0
arc: MUXLSR0 LSR1
word: SLICEA.K0.INIT 0000101000001111
enum: SLICEA.MODE LOGIC
enum: SLICEA.CCU2.INJECT1_0 _NONE_
enum: SLICEA.B0MUX 1
enum: SLICEA.GSR DISABLED
enum: SLICEA.REG0.SD 1
enum: SLICEA.REG0.REGSET RESET
enum: SLICEA.REG0.LSRMODE LSR
enum: SLICEA.CEMUX CE
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
.tile R21C75:PLC2
arc: E1_H02E0101 V02S0101
arc: E1_H02E0401 N1_V01S0000
arc: H00R0000 S1_V02N0601
arc: N1_V02N0601 S1_V02N0301
arc: S1_V02S0001 H06E0003
arc: S1_V02S0101 W1_H02E0101
arc: V00B0000 V02S0201
arc: V00B0100 V02S0301
arc: W1_H02W0101 V01N0101
arc: W1_H02W0301 V02N0301
arc: W1_H02W0401 V02N0401
arc: W1_H02W0601 N1_V01S0000
arc: A0 F5
arc: A1 F5
arc: A2 F5
arc: A6 F5
arc: A7 F5
arc: C0 E1_H02W0401
arc: C1 E1_H02W0601
arc: C2 N1_V01S0100
arc: C5 N1_V02S0201
arc: C6 V00B0100
arc: C7 V00B0100
arc: CE0 H00R0000
arc: CE1 H00R0000
arc: CE3 S1_V02N0601
arc: CLK0 G_HPBX0000
arc: D0 N1_V01S0000
arc: D1 N1_V01S0000
arc: D2 V02S0001
arc: D5 V00B0000
arc: D6 V02S0401
arc: D7 W1_H02E0001
arc: E1_H01E0101 F5
arc: E3_H06E0103 Q1
arc: F0 F0_SLICE
arc: F1 F1_SLICE
arc: F2 F2_SLICE
arc: F5 F5_SLICE
arc: F6 F6_SLICE
arc: F7 F7_SLICE
arc: LSR0 E1_H02W0301
arc: LSR1 E1_H02W0301
arc: MUXCLK0 CLK0
arc: MUXCLK1 CLK0
arc: MUXCLK3 CLK0
arc: MUXLSR0 LSR0
arc: MUXLSR1 LSR1
arc: MUXLSR3 LSR0
arc: N1_V01N0001 Q0
arc: N3_V06N0103 Q2
arc: N3_V06N0303 Q6
arc: W1_H02W0501 F5
arc: W3_H06W0203 Q7
word: SLICEA.K1.INIT 0000000011110101
word: SLICED.K1.INIT 0000111100000101
word: SLICEA.K0.INIT 0000000011110101
word: SLICEB.K0.INIT 0000111100000101
word: SLICEC.K1.INIT 0000000000001111
word: SLICED.K0.INIT 0000111100000101
enum: SLICEA.MODE LOGIC
enum: SLICEA.CCU2.INJECT1_1 _NONE_
enum: SLICEA.B1MUX 1
enum: SLICEA.GSR DISABLED
enum: SLICEA.REG0.SD 1
enum: SLICEA.REG0.REGSET RESET
enum: SLICEA.REG0.LSRMODE LSR
enum: SLICEA.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICED.MODE LOGIC
enum: SLICED.CCU2.INJECT1_1 _NONE_
enum: SLICED.B1MUX 1
enum: SLICEA.MODE LOGIC
enum: SLICEA.CCU2.INJECT1_0 _NONE_
enum: SLICEA.B0MUX 1
enum: SLICEB.MODE LOGIC
enum: SLICEB.CCU2.INJECT1_0 _NONE_
enum: SLICEB.B0MUX 1
enum: SLICEC.MODE LOGIC
enum: SLICEC.CCU2.INJECT1_1 _NONE_
enum: SLICEC.A1MUX 1
enum: SLICEC.B1MUX 1
enum: SLICEB.GSR DISABLED
enum: SLICEB.REG0.SD 1
enum: SLICEB.REG0.REGSET RESET
enum: SLICEB.REG0.LSRMODE LSR
enum: SLICEB.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICED.MODE LOGIC
enum: SLICED.CCU2.INJECT1_0 _NONE_
enum: SLICED.B0MUX 1
enum: SLICEA.GSR DISABLED
enum: SLICEA.REG1.SD 1
enum: SLICEA.REG1.REGSET RESET
enum: SLICEA.REG1.LSRMODE LSR
enum: SLICEA.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICED.GSR DISABLED
enum: SLICED.REG1.SD 1
enum: SLICED.REG1.REGSET RESET
enum: SLICED.REG1.LSRMODE LSR
enum: SLICED.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICED.GSR DISABLED
enum: SLICED.REG0.SD 1
enum: SLICED.REG0.REGSET RESET
enum: SLICED.REG0.LSRMODE LSR
enum: SLICED.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
.tile R21C76:PLC2
arc: H00R0000 S1_V02N0401
arc: B0 H02E0101
arc: C0 H02E0401
arc: CE0 H00R0000
arc: CLK0 G_HPBX0000
arc: D0 H01E0101
arc: F0 F0_SLICE
arc: LSR0 H02W0301
arc: MUXCLK0 CLK0
arc: MUXLSR0 LSR0
arc: N3_V06N0003 Q0
word: SLICEA.K0.INIT 0000110000001111
enum: SLICEA.MODE LOGIC
enum: SLICEA.CCU2.INJECT1_0 _NONE_
enum: SLICEA.A0MUX 1
enum: SLICEA.GSR DISABLED
enum: SLICEA.REG0.SD 1
enum: SLICEA.REG0.REGSET RESET
enum: SLICEA.REG0.LSRMODE LSR
enum: SLICEA.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: CLK0.CLKMUX CLK
.tile R21C77:PLC2
arc: N1_V02N0301 W3_H06E0003
arc: W1_H02W0301 N1_V02S0301
arc: W1_H02W0401 W3_H06E0203
arc: W1_H02W0601 W3_H06E0303
.tile R21C7:PLC2
arc: W3_H06W0203 E1_H01W0000
.tile R21C80:PLC2
arc: E3_H06E0103 W3_H06E0003
.tile R21C81:PLC2
arc: E3_H06E0203 W3_H06E0103
.tile R21C86:PLC2
arc: E3_H06E0203 W3_H06E0103
.tile R21C87:PLC2
arc: E1_H02E0401 W3_H06E0203
.tile R21C8:PLC2
arc: H01W0000 E3_H06W0103
.tile R23C11:PLC2
arc: W3_H06W0303 E3_H06W0203
.tile R23C13:PLC2
arc: E3_H06E0003 W3_H06E0003
.tile R23C17:PLC2
arc: W3_H06W0203 E3_H06W0203
.tile R23C19:PLC2
arc: E3_H06E0003 W3_H06E0003
arc: N1_V02N0301 W3_H06E0003
.tile R23C20:PLC2
arc: N1_V02N0101 E1_H02W0101
.tile R23C22:PLC2
arc: W1_H02W0101 V02S0101
.tile R23C23:PLC2
arc: W3_H06W0203 E3_H06W0203
.tile R23C25:PLC2
arc: E1_H01E0001 W3_H06E0003
arc: E3_H06E0003 W3_H06E0003
.tile R23C26:PLC2
arc: N1_V02N0601 H01E0001
.tile R23C29:PLC2
arc: W3_H06W0203 E3_H06W0103
.tile R23C31:PLC2
arc: E3_H06E0103 W3_H06E0003
.tile R23C35:PLC2
arc: W3_H06W0103 E3_H06W0003
.tile R23C37:PLC2
arc: E3_H06E0203 W3_H06E0103
.tile R23C41:PLC2
arc: W3_H06W0003 E3_H06W0003
.tile R23C43:PLC2
arc: E3_H06E0303 W3_H06E0203
.tile R23C47:PLC2
arc: W3_H06W0003 E3_H06W0003
.tile R23C49:PLC2
arc: E3_H06E0303 W3_H06E0303
.tile R23C4:PLC2
arc: W3_H06W0303 E1_H01W0100
.tile R23C52:PLC2
arc: E1_H02E0001 N1_V02S0001
arc: S1_V02S0501 H06E0303
.tile R23C53:PLC2
arc: V00T0100 N1_V02S0701
arc: A0 H00L0100
arc: B0 H02W0101
arc: B2 S1_V02N0101
arc: C0 H02W0601
arc: CLK0 G_HPBX0000
arc: D0 S1_V02N0201
arc: D2 V00T0100
arc: F0 F0_SLICE
arc: F2 F2_SLICE
arc: H00L0100 Q1
arc: LSR0 V00T0000
arc: M1 H02E0001
arc: MUXCLK0 CLK0
arc: MUXLSR0 LSR0
arc: V00T0000 F2
arc: W3_H06W0003 F0
word: SLICEB.K0.INIT 1100110011111111
word: SLICEA.K0.INIT 1000000000000000
enum: SLICEB.MODE LOGIC
enum: SLICEB.CCU2.INJECT1_0 _NONE_
enum: SLICEB.A0MUX 1
enum: SLICEB.C0MUX 1
enum: SLICEA.GSR DISABLED
enum: SLICEA.REG1.SD 0
enum: SLICEA.REG1.REGSET RESET
enum: SLICEA.REG1.LSRMODE LSR
enum: SLICEA.CEMUX 1
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEA.MODE LOGIC
enum: SLICEA.CCU2.INJECT1_0 _NONE_
.tile R23C54:PLC2
arc: W1_H02W0101 E3_H06W0103
arc: W1_H02W0601 E3_H06W0303
.tile R23C55:PLC2
arc: E3_H06E0303 W3_H06E0303
.tile R23C58:PLC2
arc: E1_H02E0601 V02N0601
.tile R23C5:PLC2
arc: H01W0100 E3_H06W0303
.tile R23C60:PLC2
arc: H00L0000 V02N0001
arc: W3_H06W0303 E3_H06W0203
arc: A4 N1_V02S0301
arc: B4 H00L0000
arc: C4 W1_H02E0601
arc: C5 V02N0001
arc: CLK0 G_HPBX0000
arc: D4 E1_H02W0001
arc: D5 E1_H02W0201
arc: F4 F4_SLICE
arc: F5 F5_SLICE
arc: LSR1 V00B0100
arc: M2 E1_H02W0601
arc: MUXCLK1 CLK0
arc: MUXLSR1 LSR1
arc: N3_V06N0203 F4
arc: V00B0100 F5
arc: W3_H06W0103 Q2
word: SLICEC.K1.INIT 1111111100001111
word: SLICEC.K0.INIT 1111111111111110
enum: SLICEC.MODE LOGIC
enum: SLICEC.CCU2.INJECT1_1 _NONE_
enum: SLICEC.A1MUX 1
enum: SLICEC.B1MUX 1
enum: SLICEB.GSR DISABLED
enum: SLICEB.REG0.SD 0
enum: SLICEB.REG0.REGSET RESET
enum: SLICEB.REG0.LSRMODE LSR
enum: SLICEB.CEMUX 1
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEC.MODE LOGIC
enum: SLICEC.CCU2.INJECT1_0 _NONE_
.tile R23C61:PLC2
arc: E3_H06E0003 W3_H06E0303
arc: N1_V02N0601 W3_H06E0303
.tile R23C62:PLC2
arc: N1_V02N0201 E1_H01W0000
arc: V00T0000 H02W0201
arc: W1_H02W0001 E3_H06W0003
arc: W1_H02W0201 S1_V02N0201
arc: W1_H02W0601 E1_H01W0000
arc: A4 V00B0000
arc: A5 Q5
arc: A6 H00R0000
arc: A7 Q7
arc: B0 N1_V02S0301
arc: B2 V01N0001
arc: B3 Q3
arc: CE1 V02N0201
arc: CE2 V02N0601
arc: CE3 V02N0601
arc: CLK0 G_HPBX0000
arc: E1_H01E0101 F7
arc: E1_H02E0401 F6
arc: E1_H02E0501 Q7
arc: E1_H02E0601 Q6
arc: F3 F3_SLICE
arc: F4 F4_SLICE
arc: F5 F5_SLICE
arc: F6 F6_SLICE
arc: F7 F7_SLICE
arc: H00R0000 Q6
arc: LSR0 V00T0000
arc: LSR1 V00T0000
arc: MUXCLK1 CLK0
arc: MUXCLK2 CLK0
arc: MUXCLK3 CLK0
arc: MUXLSR1 LSR1
arc: MUXLSR2 LSR1
arc: MUXLSR3 LSR0
arc: V00B0000 Q4
word: SLICED.K1.INIT 1010101010100000
word: SLICED.K0.INIT 1010101010100000
word: SLICEC.K1.INIT 1010101010100000
word: SLICEC.K0.INIT 1010101010100000
word: SLICEB.K1.INIT 1100110011000000
word: SLICEB.K0.INIT 0110011001101010
word: SLICEA.K1.INIT 1111111111111111
word: SLICEA.K0.INIT 0000000000001100
enum: SLICED.MODE CCU2
enum: SLICED.CCU2.INJECT1_1 NO
enum: SLICED.B1MUX 1
enum: SLICED.C1MUX 1
enum: SLICED.D1MUX 1
enum: SLICED.MODE CCU2
enum: SLICED.CCU2.INJECT1_0 NO
enum: SLICED.B0MUX 1
enum: SLICED.C0MUX 1
enum: SLICED.D0MUX 1
enum: SLICEC.MODE CCU2
enum: SLICEC.CCU2.INJECT1_1 NO
enum: SLICEC.B1MUX 1
enum: SLICEC.C1MUX 1
enum: SLICEC.D1MUX 1
enum: SLICEC.MODE CCU2
enum: SLICEC.CCU2.INJECT1_0 NO
enum: SLICEC.B0MUX 1
enum: SLICEC.C0MUX 1
enum: SLICEC.D0MUX 1
enum: SLICEB.MODE CCU2
enum: SLICEB.CCU2.INJECT1_1 NO
enum: SLICEB.A1MUX 1
enum: SLICEB.C1MUX 1
enum: SLICEB.D1MUX 1
enum: SLICEB.MODE CCU2
enum: SLICEB.CCU2.INJECT1_0 NO
enum: SLICEB.A0MUX 1
enum: SLICEB.C0MUX 1
enum: SLICEB.D0MUX 1
enum: SLICEA.MODE CCU2
enum: SLICEA.CCU2.INJECT1_1 YES
enum: SLICEA.A1MUX 1
enum: SLICEA.B1MUX 1
enum: SLICEA.C1MUX 1
enum: SLICEA.D1MUX 1
enum: SLICEA.MODE CCU2
enum: SLICEA.CCU2.INJECT1_0 NO
enum: SLICEA.A0MUX 1
enum: SLICEA.C0MUX 1
enum: SLICEA.D0MUX 1
enum: SLICEB.GSR DISABLED
enum: SLICEB.REG1.SD 1
enum: SLICEB.REG1.REGSET RESET
enum: SLICEB.REG1.LSRMODE LSR
enum: SLICEB.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICED.GSR DISABLED
enum: SLICED.REG1.SD 1
enum: SLICED.REG1.REGSET RESET
enum: SLICED.REG1.LSRMODE LSR
enum: SLICED.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICED.GSR DISABLED
enum: SLICED.REG0.SD 1
enum: SLICED.REG0.REGSET RESET
enum: SLICED.REG0.LSRMODE LSR
enum: SLICED.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEC.GSR DISABLED
enum: SLICEC.REG1.SD 1
enum: SLICEC.REG1.REGSET RESET
enum: SLICEC.REG1.LSRMODE LSR
enum: SLICEC.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEC.GSR DISABLED
enum: SLICEC.REG0.SD 1
enum: SLICEC.REG0.REGSET RESET
enum: SLICEC.REG0.LSRMODE LSR
enum: SLICEC.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
.tile R23C63:PLC2
arc: E1_H02E0201 V01N0001
arc: V00B0000 N1_V02S0201
arc: W1_H02W0201 N1_V02S0201
arc: A4 H02E0501
arc: A7 V02N0101
arc: B0 V00T0000
arc: B4 H00L0000
arc: B7 H01E0101
arc: C4 E1_H01E0101
arc: C7 N1_V02S0201
arc: CE0 S1_V02N0201
arc: CLK0 G_HPBX0000
arc: D4 V01N0001
arc: D7 F0
arc: E1_H01E0101 F7
arc: E1_H02E0401 F4
arc: F0 F0_SLICE
arc: F1 F1_SLICE
arc: F4 F4_SLICE
arc: F7 F7_SLICE
arc: H00L0000 Q0
arc: H01W0000 F1
arc: LSR0 V00B0000
arc: MUXCLK0 CLK0
arc: MUXLSR0 LSR0
arc: N1_V02N0101 F1
arc: V00T0000 Q0
arc: V01S0100 F1
word: SLICEB.K1.INIT 0000000000001110
word: SLICEB.K0.INIT 0000000000000000
word: SLICEA.K1.INIT 0000000000000000
word: SLICEA.K0.INIT 1100110011000000
word: SLICED.K1.INIT 0000111100001101
word: SLICEC.K0.INIT 1111000011100000
enum: SLICEB.MODE CCU2
enum: SLICEB.CCU2.INJECT1_1 NO
enum: SLICEB.A1MUX 1
enum: SLICEB.B1MUX 1
enum: SLICEB.C1MUX 1
enum: SLICEB.D1MUX 1
enum: SLICEB.MODE CCU2
enum: SLICEB.CCU2.INJECT1_0 NO
enum: SLICEB.A0MUX 1
enum: SLICEB.B0MUX 1
enum: SLICEB.C0MUX 1
enum: SLICEB.D0MUX 1
enum: SLICEA.MODE CCU2
enum: SLICEA.CCU2.INJECT1_1 NO
enum: SLICEA.A1MUX 1
enum: SLICEA.B1MUX 1
enum: SLICEA.C1MUX 1
enum: SLICEA.D1MUX 1
enum: SLICEA.MODE CCU2
enum: SLICEA.CCU2.INJECT1_0 NO
enum: SLICEA.A0MUX 1
enum: SLICEA.C0MUX 1
enum: SLICEA.D0MUX 1
enum: SLICEA.GSR DISABLED
enum: SLICEA.REG0.SD 1
enum: SLICEA.REG0.REGSET RESET
enum: SLICEA.REG0.LSRMODE LSR
enum: SLICEA.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICED.MODE LOGIC
enum: SLICED.CCU2.INJECT1_1 _NONE_
enum: SLICEC.MODE LOGIC
enum: SLICEC.CCU2.INJECT1_0 _NONE_
.tile R23C64:PLC2
arc: H00R0000 W1_H02E0601
arc: V00B0000 H02E0401
arc: A0 H00R0000
arc: B0 N1_V02S0301
arc: C0 W1_H02E0401
arc: CLK0 G_HPBX0000
arc: D0 H02E0201
arc: E3_H06E0003 Q0
arc: F0 F0_SLICE
arc: LSR1 V00B0000
arc: MUXCLK0 CLK0
arc: MUXLSR0 LSR1
arc: N1_V01N0001 Q0
word: SLICEA.K0.INIT 1100111111011101
enum: SLICEA.MODE LOGIC
enum: SLICEA.CCU2.INJECT1_0 _NONE_
enum: SLICEA.GSR DISABLED
enum: SLICEA.REG0.SD 1
enum: SLICEA.REG0.REGSET RESET
enum: SLICEA.REG0.LSRMODE LSR
enum: SLICEA.CEMUX 1
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
.tile R23C65:PLC2
arc: E1_H02E0601 N1_V02S0601
arc: N1_V02N0501 N1_V01S0100
.tile R23C66:PLC2
arc: H00L0000 V02N0201
arc: C5 H02E0601
arc: CLK0 G_HPBX0000
arc: D5 E1_H02W0001
arc: F5 F5_SLICE
arc: LSR1 V00B0100
arc: M7 H00L0000
arc: MUXCLK3 CLK0
arc: MUXLSR3 LSR1
arc: V00B0100 F5
arc: W3_H06W0203 Q7
word: SLICEC.K1.INIT 1111000011111111
enum: SLICEC.MODE LOGIC
enum: SLICEC.CCU2.INJECT1_1 _NONE_
enum: SLICEC.A1MUX 1
enum: SLICEC.B1MUX 1
enum: SLICED.GSR DISABLED
enum: SLICED.REG1.SD 0
enum: SLICED.REG1.REGSET RESET
enum: SLICED.REG1.LSRMODE LSR
enum: SLICED.CEMUX 1
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
.tile R23C67:PLC2
arc: E1_H02E0301 W3_H06E0003
arc: E3_H06E0003 W3_H06E0003
arc: N1_V02N0001 H06E0003
.tile R23C68:PLC2
arc: W1_H02W0001 E1_H01W0000
arc: W3_H06W0003 E1_H01W0000
.tile R23C69:PLC2
arc: B0 W1_H02E0301
arc: C0 H00L0000
arc: CLK0 G_HPBX0000
arc: D0 V02N0201
arc: E1_H02E0201 Q0
arc: E3_H06E0003 Q0
arc: F0 F0_SLICE
arc: H00L0000 Q0
arc: H01W0000 Q0
arc: LSR1 E1_H02W0301
arc: MUXCLK0 CLK0
arc: MUXLSR0 LSR1
arc: N1_V02N0001 Q0
word: SLICEA.K0.INIT 0000110011111100
enum: SLICEA.MODE LOGIC
enum: SLICEA.CCU2.INJECT1_0 _NONE_
enum: SLICEA.A0MUX 1
enum: SLICEA.GSR DISABLED
enum: SLICEA.REG0.SD 1
enum: SLICEA.REG0.REGSET RESET
enum: SLICEA.REG0.LSRMODE LSR
enum: SLICEA.CEMUX 1
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
.tile R23C70:PLC2
arc: N1_V02N0301 H06E0003
.tile R23C71:PLC2
arc: E1_H02E0201 W1_H02E0201
arc: E1_H02E0501 V01N0101
arc: H00R0100 H02W0501
arc: N1_V02N0001 E1_H01W0000
arc: S1_V02S0101 N1_V02S0101
arc: V00T0000 N1_V02S0401
arc: W1_H02W0301 S1_V02N0301
arc: CE0 H00R0100
arc: CLK0 G_HPBX0000
arc: D0 Q0
arc: F0 F0_SLICE
arc: LSR1 V00T0000
arc: MUXCLK0 CLK0
arc: MUXLSR0 LSR1
arc: S1_V02S0001 Q0
word: SLICEA.K0.INIT 0000000011111111
enum: SLICEA.GSR DISABLED
enum: SLICEA.REG0.SD 1
enum: SLICEA.REG0.REGSET RESET
enum: SLICEA.REG0.LSRMODE LSR
enum: SLICEA.CEMUX CE
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEA.MODE LOGIC
enum: SLICEA.CCU2.INJECT1_0 _NONE_
enum: SLICEA.A0MUX 1
enum: SLICEA.B0MUX 1
enum: SLICEA.C0MUX 1
.tile R23C72:PLC2
arc: H00R0100 H02E0501
arc: V00T0000 V02N0601
arc: A0 F7
arc: B0 V02N0301
arc: C0 H00R0100
arc: C6 V01N0101
arc: C7 V01N0101
arc: CLK0 G_HPBX0000
arc: D0 V02N0001
arc: D6 H02E0201
arc: D7 H02E0201
arc: E1_H01E0001 F6
arc: E3_H06E0303 F6
arc: F0 F0_SLICE
arc: F6 F6_SLICE
arc: F7 F7_SLICE
arc: H01W0000 Q0
arc: LSR1 V00T0000
arc: MUXCLK0 CLK0
arc: MUXLSR0 LSR1
arc: N1_V01N0001 Q0
arc: S1_V02S0701 F7
arc: V01S0000 F7
arc: W1_H02W0501 F7
word: SLICED.K1.INIT 0000111100000000
word: SLICED.K0.INIT 1111000000000000
word: SLICEA.K0.INIT 1111111100100111
enum: SLICEA.GSR DISABLED
enum: SLICEA.REG0.SD 1
enum: SLICEA.REG0.REGSET RESET
enum: SLICEA.REG0.LSRMODE LSR
enum: SLICEA.CEMUX 1
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICED.MODE LOGIC
enum: SLICED.CCU2.INJECT1_1 _NONE_
enum: SLICED.A1MUX 1
enum: SLICED.B1MUX 1
enum: SLICED.MODE LOGIC
enum: SLICED.CCU2.INJECT1_0 _NONE_
enum: SLICED.A0MUX 1
enum: SLICED.B0MUX 1
enum: SLICEA.MODE LOGIC
enum: SLICEA.CCU2.INJECT1_0 _NONE_
.tile R23C73:PLC2
arc: E3_H06E0203 H01E0001
arc: N1_V02N0001 H01E0001
arc: N1_V02N0601 H01E0001
.tile R23C75:PLC2
arc: N1_V02N0301 W3_H06E0003
arc: N1_V02N0601 H06E0303
.tile R23C76:PLC2
arc: N1_V02N0401 H06E0203
.tile R23C7:PLC2
arc: E3_H06E0003 W3_H06E0303
.tile R24C58:PLC2
arc: N1_V02N0601 S1_V02N0301
.tile R24C60:PLC2
arc: N1_V02N0001 E1_H02W0001
.tile R24C62:PLC2
arc: E1_H02E0001 V06S0003
arc: N1_V02N0201 E1_H01W0000
arc: N1_V02N0601 E1_H01W0000
arc: W1_H02W0001 V06S0003
arc: CE0 H02W0101
arc: CLK0 G_HPBX0000
arc: D0 Q0
arc: F0 F0_SLICE
arc: LSR0 E1_H02W0501
arc: MUXCLK0 CLK0
arc: MUXLSR0 LSR0
arc: N1_V01N0001 Q0
word: SLICEA.K0.INIT 0000000011111111
enum: SLICEA.GSR DISABLED
enum: SLICEA.REG0.SD 1
enum: SLICEA.REG0.REGSET RESET
enum: SLICEA.REG0.LSRMODE LSR
enum: SLICEA.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEA.MODE LOGIC
enum: SLICEA.CCU2.INJECT1_0 _NONE_
enum: SLICEA.A0MUX 1
enum: SLICEA.B0MUX 1
enum: SLICEA.C0MUX 1
.tile R24C63:PLC2
arc: C3 N1_V01S0100
arc: D3 H02E0001
arc: F3 F3_SLICE
arc: H01W0000 F3
arc: N1_V01N0001 F3
arc: N1_V02N0101 F3
arc: V01S0000 F3
arc: W1_H02W0101 F3
word: SLICEB.K1.INIT 0000111100000000
enum: SLICEB.MODE LOGIC
enum: SLICEB.CCU2.INJECT1_1 _NONE_
enum: SLICEB.A1MUX 1
enum: SLICEB.B1MUX 1
.tile R24C64:PLC2
arc: W1_H02W0501 V06S0303
.tile R24C66:PLC2
arc: N1_V02N0201 E3_H06W0103
.tile R24C69:PLC2
arc: N1_V02N0201 H06W0103
.tile R24C70:PLC2
arc: E1_H02E0001 V06S0003
arc: E1_H02E0301 V06S0003
.tile R24C71:PLC2
arc: H00R0000 H02W0601
arc: V00B0000 V02S0001
arc: A2 V00B0000
arc: A5 Q5
arc: A6 N1_V01N0101
arc: A7 Q7
arc: B0 V02S0101
arc: B3 Q3
arc: B4 V01S0000
arc: CE1 H00R0000
arc: CE2 H00R0000
arc: CE3 H00R0000
arc: CLK0 G_HPBX0000
arc: E1_H01E0001 F7
arc: E1_H01E0101 F6
arc: E1_H02E0501 Q7
arc: F3 F3_SLICE
arc: F4 F4_SLICE
arc: F5 F5_SLICE
arc: F6 F6_SLICE
arc: F7 F7_SLICE
arc: LSR1 H02E0301
arc: MUXCLK1 CLK0
arc: MUXCLK2 CLK0
arc: MUXCLK3 CLK0
arc: MUXLSR1 LSR1
arc: MUXLSR2 LSR1
arc: MUXLSR3 LSR1
arc: N1_V01N0101 Q6
arc: V01S0000 Q4
word: SLICED.K1.INIT 1010101010100000
word: SLICED.K0.INIT 1010101010100000
word: SLICEC.K1.INIT 1010101010100000
word: SLICEC.K0.INIT 1100110011000000
word: SLICEB.K1.INIT 1100110011000000
word: SLICEB.K0.INIT 0110011001101100
word: SLICEA.K1.INIT 1111111111111111
word: SLICEA.K0.INIT 0000000000001100
enum: SLICED.MODE CCU2
enum: SLICED.CCU2.INJECT1_1 NO
enum: SLICED.B1MUX 1
enum: SLICED.C1MUX 1
enum: SLICED.D1MUX 1
enum: SLICED.MODE CCU2
enum: SLICED.CCU2.INJECT1_0 NO
enum: SLICED.B0MUX 1
enum: SLICED.C0MUX 1
enum: SLICED.D0MUX 1
enum: SLICEC.MODE CCU2
enum: SLICEC.CCU2.INJECT1_1 NO
enum: SLICEC.B1MUX 1
enum: SLICEC.C1MUX 1
enum: SLICEC.D1MUX 1
enum: SLICEC.MODE CCU2
enum: SLICEC.CCU2.INJECT1_0 NO
enum: SLICEC.A0MUX 1
enum: SLICEC.C0MUX 1
enum: SLICEC.D0MUX 1
enum: SLICEB.MODE CCU2
enum: SLICEB.CCU2.INJECT1_1 NO
enum: SLICEB.A1MUX 1
enum: SLICEB.C1MUX 1
enum: SLICEB.D1MUX 1
enum: SLICEB.MODE CCU2
enum: SLICEB.CCU2.INJECT1_0 NO
enum: SLICEB.B0MUX 1
enum: SLICEB.C0MUX 1
enum: SLICEB.D0MUX 1
enum: SLICEA.MODE CCU2
enum: SLICEA.CCU2.INJECT1_1 YES
enum: SLICEA.A1MUX 1
enum: SLICEA.B1MUX 1
enum: SLICEA.C1MUX 1
enum: SLICEA.D1MUX 1
enum: SLICEA.MODE CCU2
enum: SLICEA.CCU2.INJECT1_0 NO
enum: SLICEA.A0MUX 1
enum: SLICEA.C0MUX 1
enum: SLICEA.D0MUX 1
enum: SLICED.GSR DISABLED
enum: SLICED.REG1.SD 1
enum: SLICED.REG1.REGSET RESET
enum: SLICED.REG1.LSRMODE LSR
enum: SLICED.CEMUX CE
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICED.GSR DISABLED
enum: SLICED.REG0.SD 1
enum: SLICED.REG0.REGSET RESET
enum: SLICED.REG0.LSRMODE LSR
enum: SLICED.CEMUX CE
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEC.GSR DISABLED
enum: SLICEC.REG1.SD 1
enum: SLICEC.REG1.REGSET RESET
enum: SLICEC.REG1.LSRMODE LSR
enum: SLICEC.CEMUX CE
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEC.GSR DISABLED
enum: SLICEC.REG0.SD 1
enum: SLICEC.REG0.REGSET RESET
enum: SLICEC.REG0.LSRMODE LSR
enum: SLICEC.CEMUX CE
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEB.GSR DISABLED
enum: SLICEB.REG1.SD 1
enum: SLICEB.REG1.REGSET RESET
enum: SLICEB.REG1.LSRMODE LSR
enum: SLICEB.CEMUX CE
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
.tile R24C72:PLC2
arc: H00R0100 V02S0701
arc: N1_V02N0001 W1_H02E0001
arc: N1_V02N0301 H01E0101
arc: V00T0000 W1_H02E0001
arc: W1_H02W0601 N1_V01S0000
arc: A0 H00L0000
arc: A4 H02E0501
arc: A6 H00R0000
arc: B4 N1_V01S0000
arc: B6 N1_V01S0000
arc: C4 E1_H01E0101
arc: C6 H01E0001
arc: CE0 H00R0100
arc: CLK0 G_HPBX0000
arc: D4 W1_H02E0001
arc: D6 F0
arc: E1_H01E0101 Q0
arc: F0 F0_SLICE
arc: F1 F1_SLICE
arc: F4 F4_SLICE
arc: F6 F6_SLICE
arc: H00L0000 Q0
arc: H00R0000 F4
arc: LSR1 V00T0000
arc: MUXCLK0 CLK0
arc: MUXLSR0 LSR1
arc: N1_V01N0101 F1
arc: N1_V02N0601 F6
arc: W3_H06W0103 F1
word: SLICEB.K1.INIT 0000000000001110
word: SLICEB.K0.INIT 0000000000000000
word: SLICEA.K1.INIT 0000000000000000
word: SLICEA.K0.INIT 1010101010100000
word: SLICEC.K0.INIT 0000000011111110
word: SLICED.K0.INIT 1010101010100010
enum: SLICEB.MODE CCU2
enum: SLICEB.CCU2.INJECT1_1 NO
enum: SLICEB.A1MUX 1
enum: SLICEB.B1MUX 1
enum: SLICEB.C1MUX 1
enum: SLICEB.D1MUX 1
enum: SLICEB.MODE CCU2
enum: SLICEB.CCU2.INJECT1_0 NO
enum: SLICEB.A0MUX 1
enum: SLICEB.B0MUX 1
enum: SLICEB.C0MUX 1
enum: SLICEB.D0MUX 1
enum: SLICEA.MODE CCU2
enum: SLICEA.CCU2.INJECT1_1 NO
enum: SLICEA.A1MUX 1
enum: SLICEA.B1MUX 1
enum: SLICEA.C1MUX 1
enum: SLICEA.D1MUX 1
enum: SLICEA.MODE CCU2
enum: SLICEA.CCU2.INJECT1_0 NO
enum: SLICEA.B0MUX 1
enum: SLICEA.C0MUX 1
enum: SLICEA.D0MUX 1
enum: SLICEA.GSR DISABLED
enum: SLICEA.REG0.SD 1
enum: SLICEA.REG0.REGSET RESET
enum: SLICEA.REG0.LSRMODE LSR
enum: SLICEA.CEMUX CE
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEC.MODE LOGIC
enum: SLICEC.CCU2.INJECT1_0 _NONE_
enum: SLICED.MODE LOGIC
enum: SLICED.CCU2.INJECT1_0 _NONE_
.tile R25C47:PLC2
arc: S3_V06S0103 N3_V06S0103
.tile R25C50:PLC2
arc: S1_V02S0201 N3_V06S0103
arc: S1_V02S0501 E1_H02W0501
arc: S3_V06S0103 N3_V06S0103
.tile R25C52:PLC2
arc: E1_H02E0601 S1_V02N0601
arc: S1_V02S0501 N1_V02S0501
arc: W1_H02W0501 N1_V02S0501
.tile R25C53:PLC2
arc: N1_V02N0101 N3_V06S0103
arc: S3_V06S0203 N3_V06S0103
arc: V01S0000 N3_V06S0103
arc: B5 V01S0000
arc: C5 V02N0001
arc: CLK0 G_HPBX0000
arc: F5 F5_SLICE
arc: LSR0 V00B0100
arc: M0 H02E0601
arc: MUXCLK0 CLK0
arc: MUXLSR0 LSR0
arc: N1_V02N0201 Q0
arc: V00B0100 F5
word: SLICEC.K1.INIT 1100111111001111
enum: SLICEC.MODE LOGIC
enum: SLICEC.CCU2.INJECT1_1 _NONE_
enum: SLICEC.A1MUX 1
enum: SLICEC.D1MUX 1
enum: SLICEA.GSR DISABLED
enum: SLICEA.REG0.SD 0
enum: SLICEA.REG0.REGSET RESET
enum: SLICEA.REG0.LSRMODE LSR
enum: SLICEA.CEMUX 1
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: CLK0.CLKMUX CLK
.tile R25C62:PLC2
arc: N1_V02N0201 N3_V06S0103
.tile R25C63:PLC2
arc: N1_V02N0201 N1_V01S0000
.tile R25C71:PLC2
arc: N1_V02N0301 N3_V06S0003
.tile R26C18:PLC2
arc: S3_V06S0103 N3_V06S0003
.tile R26C48:PLC2
arc: S3_V06S0303 H06W0303
.tile R26C49:PLC2
arc: S3_V06S0203 N3_V06S0103
.tile R26C51:PLC2
arc: W3_H06W0303 E1_H01W0100
.tile R26C52:PLC2
arc: S3_V06S0203 N3_V06S0103
arc: V00B0000 H02W0401
arc: A0 V02S0501
arc: C0 V02N0601
arc: CLK0 G_HPBX0000
arc: D0 Q0
arc: E1_H02E0001 Q0
arc: E3_H06E0003 Q0
arc: F0 F0_SLICE
arc: H01W0100 Q0
arc: LSR1 V00B0000
arc: MUXCLK0 CLK0
arc: MUXLSR0 LSR1
arc: S3_V06S0003 Q0
arc: V01S0000 Q0
word: SLICEA.K0.INIT 0000111110101010
enum: SLICEA.MODE LOGIC
enum: SLICEA.CCU2.INJECT1_0 _NONE_
enum: SLICEA.B0MUX 1
enum: SLICEA.GSR DISABLED
enum: SLICEA.REG0.SD 1
enum: SLICEA.REG0.REGSET RESET
enum: SLICEA.REG0.LSRMODE LSR
enum: SLICEA.CEMUX 1
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
.tile R26C53:PLC2
arc: N1_V02N0001 H02E0001
arc: W1_H02W0401 N1_V01S0000
.tile R26C58:PLC2
arc: N1_V02N0301 W3_H06E0003
.tile R27C17:PLC2
arc: S3_V06S0003 N3_V06S0003
.tile R27C50:PLC2
arc: S3_V06S0303 N3_V06S0303
arc: B4 N1_V02S0501
arc: C4 N1_V02S0201
arc: D4 E1_H02W0001
arc: E1_H01E0001 F4
arc: E1_H02E0401 F4
arc: F4 F4_SLICE
arc: S3_V06S0203 F4
word: SLICEC.K0.INIT 1111000011111100
enum: SLICEC.MODE LOGIC
enum: SLICEC.CCU2.INJECT1_0 _NONE_
enum: SLICEC.A0MUX 1
.tile R27C51:PLC2
arc: S1_V02S0401 H01E0001
.tile R27C52:PLC2
arc: N1_V02N0601 S1_V02N0301
arc: S1_V02S0401 W1_H02E0401
arc: S1_V02S0601 N1_V01S0000
arc: W1_H02W0001 N1_V01S0000
.tile R27C53:PLC2
arc: S3_V06S0003 N3_V06S0303
.tile R28C49:PLC2
arc: N3_V06N0003 S3_V06N0003
.tile R28C51:PLC2
arc: H00R0000 H02W0401
arc: N3_V06N0103 S3_V06N0003
arc: S1_V02S0601 E1_H01W0000
arc: V00T0000 V02S0401
arc: CE0 H00R0000
arc: CLK0 G_HPBX0000
arc: D0 Q0
arc: F0 F0_SLICE
arc: LSR0 V00T0000
arc: MUXCLK0 CLK0
arc: MUXLSR0 LSR0
arc: S1_V02S0201 Q0
word: SLICEA.K0.INIT 0000000011111111
enum: SLICEA.GSR DISABLED
enum: SLICEA.REG0.SD 1
enum: SLICEA.REG0.REGSET RESET
enum: SLICEA.REG0.LSRMODE LSR
enum: SLICEA.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEA.MODE LOGIC
enum: SLICEA.CCU2.INJECT1_0 _NONE_
enum: SLICEA.A0MUX 1
enum: SLICEA.B0MUX 1
enum: SLICEA.C0MUX 1
.tile R28C52:PLC2
arc: A4 V02N0101
arc: D4 V02S0601
arc: F4 F4_SLICE
arc: H01W0000 F4
arc: S1_V02S0601 F4
arc: W1_H02W0401 F4
word: SLICEC.K0.INIT 0101010100000000
enum: SLICEC.MODE LOGIC
enum: SLICEC.CCU2.INJECT1_0 _NONE_
enum: SLICEC.B0MUX 1
enum: SLICEC.C0MUX 1
.tile R29C51:PLC2
arc: H00R0000 V02S0601
arc: V00B0000 V02S0201
arc: V00T0000 N1_V02S0401
arc: A0 V02N0501
arc: A2 V00B0000
arc: A5 Q5
arc: A6 N1_V01N0101
arc: A7 Q7
arc: B3 Q3
arc: B4 V01S0000
arc: CE1 H00R0000
arc: CE2 V02S0601
arc: CE3 V02S0601
arc: CLK0 G_HPBX0000
arc: F3 F3_SLICE
arc: F4 F4_SLICE
arc: F5 F5_SLICE
arc: F6 F6_SLICE
arc: F7 F7_SLICE
arc: LSR1 V00T0000
arc: MUXCLK1 CLK0
arc: MUXCLK2 CLK0
arc: MUXCLK3 CLK0
arc: MUXLSR1 LSR1
arc: MUXLSR2 LSR1
arc: MUXLSR3 LSR1
arc: N1_V01N0101 Q6
arc: V01S0000 Q4
word: SLICED.K1.INIT 1010101010100000
word: SLICED.K0.INIT 1010101010100000
word: SLICEC.K1.INIT 1010101010100000
word: SLICEC.K0.INIT 1100110011000000
word: SLICEB.K1.INIT 1100110011000000
word: SLICEB.K0.INIT 0110011001101100
word: SLICEA.K1.INIT 1111111111111111
word: SLICEA.K0.INIT 0000000000001010
enum: SLICED.MODE CCU2
enum: SLICED.CCU2.INJECT1_1 NO
enum: SLICED.B1MUX 1
enum: SLICED.C1MUX 1
enum: SLICED.D1MUX 1
enum: SLICED.MODE CCU2
enum: SLICED.CCU2.INJECT1_0 NO
enum: SLICED.B0MUX 1
enum: SLICED.C0MUX 1
enum: SLICED.D0MUX 1
enum: SLICEC.MODE CCU2
enum: SLICEC.CCU2.INJECT1_1 NO
enum: SLICEC.B1MUX 1
enum: SLICEC.C1MUX 1
enum: SLICEC.D1MUX 1
enum: SLICEC.MODE CCU2
enum: SLICEC.CCU2.INJECT1_0 NO
enum: SLICEC.A0MUX 1
enum: SLICEC.C0MUX 1
enum: SLICEC.D0MUX 1
enum: SLICEB.MODE CCU2
enum: SLICEB.CCU2.INJECT1_1 NO
enum: SLICEB.A1MUX 1
enum: SLICEB.C1MUX 1
enum: SLICEB.D1MUX 1
enum: SLICEB.MODE CCU2
enum: SLICEB.CCU2.INJECT1_0 NO
enum: SLICEB.B0MUX 1
enum: SLICEB.C0MUX 1
enum: SLICEB.D0MUX 1
enum: SLICEA.MODE CCU2
enum: SLICEA.CCU2.INJECT1_1 YES
enum: SLICEA.A1MUX 1
enum: SLICEA.B1MUX 1
enum: SLICEA.C1MUX 1
enum: SLICEA.D1MUX 1
enum: SLICEA.MODE CCU2
enum: SLICEA.CCU2.INJECT1_0 NO
enum: SLICEA.B0MUX 1
enum: SLICEA.C0MUX 1
enum: SLICEA.D0MUX 1
enum: SLICED.GSR DISABLED
enum: SLICED.REG1.SD 1
enum: SLICED.REG1.REGSET RESET
enum: SLICED.REG1.LSRMODE LSR
enum: SLICED.CEMUX CE
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEC.GSR DISABLED
enum: SLICEC.REG0.SD 1
enum: SLICEC.REG0.REGSET RESET
enum: SLICEC.REG0.LSRMODE LSR
enum: SLICEC.CEMUX CE
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEB.GSR DISABLED
enum: SLICEB.REG1.SD 1
enum: SLICEB.REG1.REGSET RESET
enum: SLICEB.REG1.LSRMODE LSR
enum: SLICEB.CEMUX CE
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICED.GSR DISABLED
enum: SLICED.REG0.SD 1
enum: SLICED.REG0.REGSET RESET
enum: SLICED.REG0.LSRMODE LSR
enum: SLICED.CEMUX CE
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEC.GSR DISABLED
enum: SLICEC.REG1.SD 1
enum: SLICEC.REG1.REGSET RESET
enum: SLICEC.REG1.LSRMODE LSR
enum: SLICEC.CEMUX CE
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
.tile R29C52:PLC2
arc: H00R0000 V02S0601
arc: V00T0000 N1_V02S0401
arc: A0 H00L0000
arc: CE0 H00R0000
arc: CLK0 G_HPBX0000
arc: F0 F0_SLICE
arc: F1 F1_SLICE
arc: H00L0000 Q0
arc: LSR1 V00T0000
arc: MUXCLK0 CLK0
arc: MUXLSR0 LSR1
arc: N1_V02N0101 F1
arc: N1_V02N0301 F1
arc: S3_V06S0103 F1
word: SLICEB.K1.INIT 0000000000001110
word: SLICEB.K0.INIT 0000000000000000
word: SLICEA.K1.INIT 0000000000000000
word: SLICEA.K0.INIT 1010101010100000
enum: SLICEB.MODE CCU2
enum: SLICEB.CCU2.INJECT1_1 NO
enum: SLICEB.A1MUX 1
enum: SLICEB.B1MUX 1
enum: SLICEB.C1MUX 1
enum: SLICEB.D1MUX 1
enum: SLICEB.MODE CCU2
enum: SLICEB.CCU2.INJECT1_0 NO
enum: SLICEB.A0MUX 1
enum: SLICEB.B0MUX 1
enum: SLICEB.C0MUX 1
enum: SLICEB.D0MUX 1
enum: SLICEA.MODE CCU2
enum: SLICEA.CCU2.INJECT1_1 NO
enum: SLICEA.A1MUX 1
enum: SLICEA.B1MUX 1
enum: SLICEA.C1MUX 1
enum: SLICEA.D1MUX 1
enum: SLICEA.MODE CCU2
enum: SLICEA.CCU2.INJECT1_0 NO
enum: SLICEA.B0MUX 1
enum: SLICEA.C0MUX 1
enum: SLICEA.D0MUX 1
enum: SLICEA.GSR DISABLED
enum: SLICEA.REG0.SD 1
enum: SLICEA.REG0.REGSET RESET
enum: SLICEA.REG0.LSRMODE LSR
enum: SLICEA.CEMUX CE
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
.tile R2C38:PLC2
arc: N1_V02N0501 S3_V06N0303
.tile R2C49:PLC2
arc: N1_V02N0701 S1_V02N0601
.tile R2C51:PLC2
arc: N1_V02N0501 S1_V02N0501
.tile R2C67:PLC2
arc: N1_V02N0001 S3_V06N0003
arc: N1_V02N0701 S3_V06N0203
.tile R30C50:PLC2
arc: E1_H02E0501 V06S0303
.tile R30C51:PLC2
arc: N1_V02N0501 H02E0501
.tile R31C47:PLC2
arc: S3_V06S0203 N3_V06S0103
.tile R31C50:PLC2
arc: S3_V06S0203 N3_V06S0103
.tile R31C53:PLC2
arc: S3_V06S0203 N3_V06S0203
.tile R32C18:PLC2
arc: S3_V06S0203 N3_V06S0103
.tile R32C48:PLC2
arc: S3_V06S0303 N3_V06S0303
.tile R32C49:PLC2
arc: S3_V06S0203 N3_V06S0203
.tile R32C52:PLC2
arc: S3_V06S0103 N3_V06S0003
arc: S3_V06S0203 N3_V06S0203
.tile R33C17:PLC2
arc: S3_V06S0103 N3_V06S0003
.tile R33C50:PLC2
arc: S3_V06S0203 N3_V06S0203
arc: S3_V06S0303 N3_V06S0303
.tile R33C53:PLC2
arc: S3_V06S0003 N3_V06S0003
.tile R35C52:PLC2
arc: S3_V06S0203 N3_V06S0103
.tile R37C47:PLC2
arc: S3_V06S0303 N3_V06S0203
.tile R37C50:PLC2
arc: S3_V06S0303 N3_V06S0203
.tile R37C53:PLC2
arc: S1_V02S0701 N3_V06S0203
.tile R38C18:PLC2
arc: S3_V06S0203 N3_V06S0203
.tile R38C48:PLC2
arc: S3_V06S0303 N3_V06S0303
.tile R38C49:PLC2
arc: S3_V06S0303 N3_V06S0203
.tile R38C52:PLC2
arc: S1_V02S0201 N3_V06S0103
arc: S3_V06S0103 N3_V06S0103
arc: S3_V06S0203 N3_V06S0203
.tile R39C17:PLC2
arc: S3_V06S0203 N3_V06S0103
.tile R39C48:PLC2
arc: S1_V02S0601 S3_V06N0303
.tile R39C49:PLC2
arc: S1_V02S0601 S3_V06N0303
.tile R39C50:PLC2
arc: S1_V02S0701 N3_V06S0203
arc: S3_V06S0003 N3_V06S0303
arc: S3_V06S0303 N3_V06S0203
.tile R39C53:PLC2
arc: S1_V02S0001 N3_V06S0003
arc: S1_V02S0701 N1_V02S0701
.tile R3C18:PLC2
arc: N1_V02N0701 S3_V06N0203
.tile R3C41:PLC2
arc: N1_V02N0701 S1_V02N0701
.tile R3C60:PLC2
arc: N1_V02N0501 S3_V06N0303
.tile R3C75:PLC2
arc: N1_V02N0301 S3_V06N0003
arc: N1_V02N0501 S3_V06N0303
.tile R3C76:PLC2
arc: N1_V02N0701 S3_V06N0203
.tile R40C12:PLC2
arc: W3_H06W0203 E3_H06W0103
.tile R40C18:PLC2
arc: W3_H06W0103 E3_H06W0103
.tile R40C24:PLC2
arc: W3_H06W0103 E3_H06W0003
.tile R40C30:PLC2
arc: W3_H06W0003 E3_H06W0003
.tile R40C36:PLC2
arc: W3_H06W0003 E3_H06W0003
.tile R40C3:PLC2
arc: S1_V02S0701 H06W0203
.tile R40C42:PLC2
arc: W3_H06W0003 E3_H06W0003
.tile R40C47:PLC2
arc: E1_H02E0501 V06S0303
.tile R40C48:PLC2
arc: E1_H02E0401 V02N0401
arc: S1_V02S0101 H06W0103
arc: B0 S1_V02N0101
arc: C0 V02N0401
arc: CE0 E1_H02W0101
arc: CLK0 G_HPBX0000
arc: D0 S1_V02N0201
arc: F0 F0_SLICE
arc: LSR0 H02E0501
arc: MUXCLK0 CLK0
arc: MUXLSR0 LSR0
arc: W3_H06W0003 Q0
word: SLICEA.K0.INIT 0000000011001111
enum: SLICEA.MODE LOGIC
enum: SLICEA.CCU2.INJECT1_0 _NONE_
enum: SLICEA.A0MUX 1
enum: SLICEA.GSR DISABLED
enum: SLICEA.REG0.SD 1
enum: SLICEA.REG0.REGSET RESET
enum: SLICEA.REG0.LSRMODE LSR
enum: SLICEA.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: CLK0.CLKMUX CLK
.tile R40C49:PLC2
arc: B0 S1_V02N0301
arc: C0 H02E0401
arc: CE0 H02W0101
arc: CLK0 G_HPBX0000
arc: D0 S1_V02N0201
arc: F0 F0_SLICE
arc: LSR1 H02W0501
arc: MUXCLK0 CLK0
arc: MUXLSR0 LSR1
arc: N3_V06N0003 Q0
word: SLICEA.K0.INIT 0000000011001111
enum: SLICEA.MODE LOGIC
enum: SLICEA.CCU2.INJECT1_0 _NONE_
enum: SLICEA.A0MUX 1
enum: SLICEA.GSR DISABLED
enum: SLICEA.REG0.SD 1
enum: SLICEA.REG0.REGSET RESET
enum: SLICEA.REG0.LSRMODE LSR
enum: SLICEA.CEMUX CE
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
.tile R40C50:PLC2
arc: E1_H02E0501 V06S0303
arc: W1_H02W0101 E1_H02W0101
arc: W1_H02W0501 V06S0303
.tile R40C51:PLC2
arc: W3_H06W0103 E1_H01W0100
arc: B0 S1_V02N0301
arc: C0 S1_V02N0601
arc: CE0 H02W0101
arc: CLK0 G_HPBX0000
arc: D0 V02N0201
arc: F0 F0_SLICE
arc: LSR1 H02E0501
arc: MUXCLK0 CLK0
arc: MUXLSR0 LSR1
arc: N3_V06N0003 Q0
word: SLICEA.K0.INIT 0011000000110011
enum: SLICEA.MODE LOGIC
enum: SLICEA.CCU2.INJECT1_0 _NONE_
enum: SLICEA.A0MUX 1
enum: SLICEA.GSR DISABLED
enum: SLICEA.REG0.SD 1
enum: SLICEA.REG0.REGSET RESET
enum: SLICEA.REG0.LSRMODE LSR
enum: SLICEA.CEMUX CE
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
.tile R40C52:PLC2
arc: C1 V02N0401
arc: D1 N1_V02S0201
arc: F1 F1_SLICE
arc: H01W0100 F1
arc: S1_V02S0101 F1
arc: W1_H02W0101 F1
word: SLICEA.K1.INIT 1111000000000000
enum: SLICEA.MODE LOGIC
enum: SLICEA.CCU2.INJECT1_1 _NONE_
enum: SLICEA.A1MUX 1
enum: SLICEA.B1MUX 1
.tile R40C6:PLC2
arc: W3_H06W0203 E3_H06W0203
.tile R41C11:PLC2
arc: W3_H06W0103 E3_H06W0003
.tile R41C17:PLC2
arc: W3_H06W0003 E3_H06W0303
.tile R41C23:PLC2
arc: W3_H06W0303 E3_H06W0203
.tile R41C29:PLC2
arc: W3_H06W0203 E3_H06W0203
.tile R41C35:PLC2
arc: W3_H06W0203 E3_H06W0103
.tile R41C3:PLC2
arc: W1_H02W0701 V02S0701
.tile R41C41:PLC2
arc: W3_H06W0103 E3_H06W0003
.tile R41C46:PLC2
arc: E1_H02E0601 E3_H06W0303
arc: S1_V02S0601 E3_H06W0303
.tile R41C47:PLC2
arc: V00T0100 S1_V02N0501
arc: A0 H02W0701
arc: C0 H02E0601
arc: CE0 H02W0101
arc: CLK0 G_HPBX0000
arc: D0 V02N0201
arc: F0 F0_SLICE
arc: LSR1 V00T0100
arc: MUXCLK0 CLK0
arc: MUXLSR0 LSR1
arc: W3_H06W0003 Q0
word: SLICEA.K0.INIT 0000000010101111
enum: SLICEA.MODE LOGIC
enum: SLICEA.CCU2.INJECT1_0 _NONE_
enum: SLICEA.B0MUX 1
enum: SLICEA.GSR DISABLED
enum: SLICEA.REG0.SD 1
enum: SLICEA.REG0.REGSET RESET
enum: SLICEA.REG0.LSRMODE LSR
enum: SLICEA.CEMUX CE
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
.tile R41C48:PLC2
arc: N1_V02N0401 H06W0203
arc: S1_V02S0701 N1_V02S0601
arc: V00T0000 V02N0601
arc: W1_H02W0101 V02S0101
arc: W1_H02W0701 V01N0101
arc: A0 H02W0501
arc: A2 V01N0101
arc: B3 V01N0001
arc: B4 S1_V02N0501
arc: B5 V02N0501
arc: B6 V00T0000
arc: B7 V02N0701
word: SLICED.K1.INIT 1001100110011100
word: SLICED.K0.INIT 1001100110011100
word: SLICEC.K1.INIT 1001100110011100
word: SLICEC.K0.INIT 1001100110011100
word: SLICEB.K1.INIT 1001100110011100
word: SLICEB.K0.INIT 1001100110011010
word: SLICEA.K1.INIT 1111111111111111
word: SLICEA.K0.INIT 0000000000001010
enum: SLICED.MODE CCU2
enum: SLICED.CCU2.INJECT1_1 NO
enum: SLICED.A1MUX 1
enum: SLICED.C1MUX 1
enum: SLICED.D1MUX 1
enum: SLICED.MODE CCU2
enum: SLICED.CCU2.INJECT1_0 NO
enum: SLICED.A0MUX 1
enum: SLICED.C0MUX 1
enum: SLICED.D0MUX 1
enum: SLICEC.MODE CCU2
enum: SLICEC.CCU2.INJECT1_1 NO
enum: SLICEC.A1MUX 1
enum: SLICEC.C1MUX 1
enum: SLICEC.D1MUX 1
enum: SLICEC.MODE CCU2
enum: SLICEC.CCU2.INJECT1_0 NO
enum: SLICEC.A0MUX 1
enum: SLICEC.C0MUX 1
enum: SLICEC.D0MUX 1
enum: SLICEB.MODE CCU2
enum: SLICEB.CCU2.INJECT1_1 NO
enum: SLICEB.A1MUX 1
enum: SLICEB.C1MUX 1
enum: SLICEB.D1MUX 1
enum: SLICEB.MODE CCU2
enum: SLICEB.CCU2.INJECT1_0 NO
enum: SLICEB.B0MUX 1
enum: SLICEB.C0MUX 1
enum: SLICEB.D0MUX 1
enum: SLICEA.MODE CCU2
enum: SLICEA.CCU2.INJECT1_1 YES
enum: SLICEA.A1MUX 1
enum: SLICEA.B1MUX 1
enum: SLICEA.C1MUX 1
enum: SLICEA.D1MUX 1
enum: SLICEA.MODE CCU2
enum: SLICEA.CCU2.INJECT1_0 NO
enum: SLICEA.B0MUX 1
enum: SLICEA.C0MUX 1
enum: SLICEA.D0MUX 1
.tile R41C49:PLC2
arc: H00R0000 V02N0601
arc: S1_V02S0701 N1_V02S0601
arc: V00B0000 V02N0001
arc: V00T0000 V02N0401
arc: W1_H02W0501 V06S0303
arc: A2 V00B0000
arc: A3 V01N0101
arc: A4 V00T0000
arc: A6 H00R0000
arc: B0 S1_V02N0101
arc: B1 V01N0001
arc: B5 V02N0701
arc: B7 V02N0501
word: SLICED.K1.INIT 0011001100111100
word: SLICED.K0.INIT 0101010101011010
word: SLICEC.K1.INIT 0011001100111100
word: SLICEC.K0.INIT 0101010101011010
word: SLICEB.K1.INIT 0101010101011010
word: SLICEB.K0.INIT 0101010101011010
word: SLICEA.K1.INIT 0011001100111100
word: SLICEA.K0.INIT 1001100110011100
enum: SLICED.MODE CCU2
enum: SLICED.CCU2.INJECT1_1 NO
enum: SLICED.A1MUX 1
enum: SLICED.C1MUX 1
enum: SLICED.D1MUX 1
enum: SLICED.MODE CCU2
enum: SLICED.CCU2.INJECT1_0 NO
enum: SLICED.B0MUX 1
enum: SLICED.C0MUX 1
enum: SLICED.D0MUX 1
enum: SLICEC.MODE CCU2
enum: SLICEC.CCU2.INJECT1_1 NO
enum: SLICEC.A1MUX 1
enum: SLICEC.C1MUX 1
enum: SLICEC.D1MUX 1
enum: SLICEC.MODE CCU2
enum: SLICEC.CCU2.INJECT1_0 NO
enum: SLICEC.B0MUX 1
enum: SLICEC.C0MUX 1
enum: SLICEC.D0MUX 1
enum: SLICEB.MODE CCU2
enum: SLICEB.CCU2.INJECT1_1 NO
enum: SLICEB.B1MUX 1
enum: SLICEB.C1MUX 1
enum: SLICEB.D1MUX 1
enum: SLICEB.MODE CCU2
enum: SLICEB.CCU2.INJECT1_0 NO
enum: SLICEB.B0MUX 1
enum: SLICEB.C0MUX 1
enum: SLICEB.D0MUX 1
enum: SLICEA.MODE CCU2
enum: SLICEA.CCU2.INJECT1_1 NO
enum: SLICEA.A1MUX 1
enum: SLICEA.C1MUX 1
enum: SLICEA.D1MUX 1
enum: SLICEA.MODE CCU2
enum: SLICEA.CCU2.INJECT1_0 NO
enum: SLICEA.A0MUX 1
enum: SLICEA.C0MUX 1
enum: SLICEA.D0MUX 1
.tile R41C4:PLC2
arc: W3_H06W0203 E1_H01W0000
.tile R41C50:PLC2
arc: H00L0000 V02N0201
arc: S1_V02S0201 N1_V02S0701
arc: V00B0000 V02N0001
arc: V00T0000 V02N0601
arc: A0 H00L0000
arc: A1 V01N0101
arc: A2 V00B0000
arc: B3 V01N0001
arc: B4 S1_V02N0701
arc: B5 V02N0501
arc: B6 V00T0000
arc: B7 V02N0701
word: SLICED.K1.INIT 0011001100111100
word: SLICED.K0.INIT 0011001100111100
word: SLICEC.K1.INIT 0011001100111100
word: SLICEC.K0.INIT 0011001100111100
word: SLICEB.K1.INIT 0011001100111100
word: SLICEB.K0.INIT 0101010101011010
word: SLICEA.K1.INIT 0101010101011010
word: SLICEA.K0.INIT 0101010101011010
enum: SLICED.MODE CCU2
enum: SLICED.CCU2.INJECT1_1 NO
enum: SLICED.A1MUX 1
enum: SLICED.C1MUX 1
enum: SLICED.D1MUX 1
enum: SLICED.MODE CCU2
enum: SLICED.CCU2.INJECT1_0 NO
enum: SLICED.A0MUX 1
enum: SLICED.C0MUX 1
enum: SLICED.D0MUX 1
enum: SLICEC.MODE CCU2
enum: SLICEC.CCU2.INJECT1_1 NO
enum: SLICEC.A1MUX 1
enum: SLICEC.C1MUX 1
enum: SLICEC.D1MUX 1
enum: SLICEC.MODE CCU2
enum: SLICEC.CCU2.INJECT1_0 NO
enum: SLICEC.A0MUX 1
enum: SLICEC.C0MUX 1
enum: SLICEC.D0MUX 1
enum: SLICEB.MODE CCU2
enum: SLICEB.CCU2.INJECT1_1 NO
enum: SLICEB.A1MUX 1
enum: SLICEB.C1MUX 1
enum: SLICEB.D1MUX 1
enum: SLICEB.MODE CCU2
enum: SLICEB.CCU2.INJECT1_0 NO
enum: SLICEB.B0MUX 1
enum: SLICEB.C0MUX 1
enum: SLICEB.D0MUX 1
enum: SLICEA.MODE CCU2
enum: SLICEA.CCU2.INJECT1_1 NO
enum: SLICEA.B1MUX 1
enum: SLICEA.C1MUX 1
enum: SLICEA.D1MUX 1
enum: SLICEA.MODE CCU2
enum: SLICEA.CCU2.INJECT1_0 NO
enum: SLICEA.B0MUX 1
enum: SLICEA.C0MUX 1
enum: SLICEA.D0MUX 1
.tile R41C51:PLC2
arc: H00L0000 V02N0001
arc: N1_V02N0201 E1_H01W0000
arc: V00B0000 V02N0201
arc: V00T0000 V02N0401
arc: W3_H06W0203 E1_H01W0000
arc: A0 H00L0000
arc: A2 V00B0000
arc: A3 V01N0101
arc: A4 V00T0000
arc: B1 V01N0001
arc: B5 V02N0701
arc: B6 S1_V02N0701
arc: B7 V02N0501
word: SLICED.K1.INIT 0011001100111100
word: SLICED.K0.INIT 0011001100111100
word: SLICEC.K1.INIT 0011001100111100
word: SLICEC.K0.INIT 0101010101011010
word: SLICEB.K1.INIT 0101010101011010
word: SLICEB.K0.INIT 0101010101011010
word: SLICEA.K1.INIT 0011001100111100
word: SLICEA.K0.INIT 0101010101011010
enum: SLICED.MODE CCU2
enum: SLICED.CCU2.INJECT1_1 NO
enum: SLICED.A1MUX 1
enum: SLICED.C1MUX 1
enum: SLICED.D1MUX 1
enum: SLICED.MODE CCU2
enum: SLICED.CCU2.INJECT1_0 NO
enum: SLICED.A0MUX 1
enum: SLICED.C0MUX 1
enum: SLICED.D0MUX 1
enum: SLICEC.MODE CCU2
enum: SLICEC.CCU2.INJECT1_1 NO
enum: SLICEC.A1MUX 1
enum: SLICEC.C1MUX 1
enum: SLICEC.D1MUX 1
enum: SLICEC.MODE CCU2
enum: SLICEC.CCU2.INJECT1_0 NO
enum: SLICEC.B0MUX 1
enum: SLICEC.C0MUX 1
enum: SLICEC.D0MUX 1
enum: SLICEB.MODE CCU2
enum: SLICEB.CCU2.INJECT1_1 NO
enum: SLICEB.B1MUX 1
enum: SLICEB.C1MUX 1
enum: SLICEB.D1MUX 1
enum: SLICEB.MODE CCU2
enum: SLICEB.CCU2.INJECT1_0 NO
enum: SLICEB.B0MUX 1
enum: SLICEB.C0MUX 1
enum: SLICEB.D0MUX 1
enum: SLICEA.MODE CCU2
enum: SLICEA.CCU2.INJECT1_1 NO
enum: SLICEA.A1MUX 1
enum: SLICEA.C1MUX 1
enum: SLICEA.D1MUX 1
enum: SLICEA.MODE CCU2
enum: SLICEA.CCU2.INJECT1_0 NO
enum: SLICEA.B0MUX 1
enum: SLICEA.C0MUX 1
enum: SLICEA.D0MUX 1
.tile R41C52:PLC2
arc: E1_H02E0101 V02S0101
arc: N1_V02N0401 N3_V06S0203
arc: C6 V02N0201
arc: D6 F0
arc: E1_H02E0601 F6
arc: F0 F0_SLICE
arc: F6 F6_SLICE
arc: H01W0000 F6
arc: V01S0000 F6
arc: W3_H06W0303 F6
word: SLICEA.K1.INIT 0000000000001110
word: SLICEA.K0.INIT 0000000000000000
word: SLICED.K0.INIT 0000000000001111
enum: SLICEA.MODE CCU2
enum: SLICEA.CCU2.INJECT1_1 NO
enum: SLICEA.A1MUX 1
enum: SLICEA.B1MUX 1
enum: SLICEA.C1MUX 1
enum: SLICEA.D1MUX 1
enum: SLICEA.MODE CCU2
enum: SLICEA.CCU2.INJECT1_0 NO
enum: SLICEA.A0MUX 1
enum: SLICEA.B0MUX 1
enum: SLICEA.C0MUX 1
enum: SLICEA.D0MUX 1
enum: SLICED.MODE LOGIC
enum: SLICED.CCU2.INJECT1_0 _NONE_
enum: SLICED.A0MUX 1
enum: SLICED.B0MUX 1
.tile R41C53:PLC2
arc: H00L0000 N1_V02S0001
arc: S1_V02S0201 N1_V02S0701
arc: V00T0100 N1_V02S0701
arc: B0 V02N0101
arc: C0 H02E0601
arc: CE0 H02E0101
arc: CLK0 G_HPBX0000
arc: D0 V02N0001
arc: E3_H06E0003 Q0
arc: E3_H06E0103 Q1
arc: F0 F0_SLICE
arc: LSR0 V00T0100
arc: M1 H00L0000
arc: MUXCLK0 CLK0
arc: MUXLSR0 LSR0
word: SLICEA.K0.INIT 0011001100000011
enum: SLICEA.MODE LOGIC
enum: SLICEA.CCU2.INJECT1_0 _NONE_
enum: SLICEA.A0MUX 1
enum: SLICEA.GSR DISABLED
enum: SLICEA.REG1.SD 0
enum: SLICEA.REG1.REGSET RESET
enum: SLICEA.REG1.LSRMODE LSR
enum: SLICEA.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEA.GSR DISABLED
enum: SLICEA.REG0.SD 1
enum: SLICEA.REG0.REGSET RESET
enum: SLICEA.REG0.LSRMODE LSR
enum: SLICEA.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: CLK0.CLKMUX CLK
.tile R41C59:PLC2
arc: E3_H06E0003 W3_H06E0003
arc: E3_H06E0203 W3_H06E0103
.tile R41C5:PLC2
arc: H01W0000 E3_H06W0103
.tile R41C65:PLC2
arc: E3_H06E0003 W3_H06E0003
arc: E3_H06E0203 W3_H06E0203
.tile R41C71:PLC2
arc: E3_H06E0103 W3_H06E0003
arc: E3_H06E0303 W3_H06E0203
.tile R41C77:PLC2
arc: E3_H06E0103 W3_H06E0103
arc: E3_H06E0303 W3_H06E0303
.tile R41C83:PLC2
arc: E3_H06E0203 W3_H06E0103
arc: E3_H06E0303 W3_H06E0303
.tile R42C11:PLC2
arc: W3_H06W0103 E3_H06W0103
.tile R42C17:PLC2
arc: W3_H06W0103 E3_H06W0103
.tile R42C23:PLC2
arc: W3_H06W0103 E3_H06W0103
.tile R42C29:PLC2
arc: W3_H06W0103 E3_H06W0103
.tile R42C35:PLC2
arc: W3_H06W0103 E3_H06W0103
.tile R42C41:PLC2
arc: W3_H06W0103 E3_H06W0003
.tile R42C46:PLC2
arc: E1_H02E0201 E3_H06W0103
arc: E1_H02E0601 V02S0601
.tile R42C47:PLC2
arc: N1_V02N0201 H02E0201
arc: V00T0100 V02N0501
arc: B0 E1_H01W0100
arc: C0 H02E0601
arc: CE0 H02W0101
arc: CLK0 G_HPBX0000
arc: D0 H02E0201
arc: F0 F0_SLICE
arc: LSR1 V00T0100
arc: MUXCLK0 CLK0
arc: MUXLSR0 LSR1
arc: W3_H06W0003 Q0
word: SLICEA.K0.INIT 0000000011001111
enum: SLICEA.MODE LOGIC
enum: SLICEA.CCU2.INJECT1_0 _NONE_
enum: SLICEA.A0MUX 1
enum: SLICEA.GSR DISABLED
enum: SLICEA.REG0.SD 1
enum: SLICEA.REG0.REGSET RESET
enum: SLICEA.REG0.LSRMODE LSR
enum: SLICEA.CEMUX CE
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
.tile R42C48:PLC2
arc: E1_H02E0601 S1_V02N0601
arc: H00L0000 S1_V02N0201
arc: H00R0100 S1_V02N0501
arc: N1_V02N0101 E1_H01W0100
arc: N1_V02N0201 W1_H02E0201
arc: W1_H02W0101 N1_V02S0101
arc: A2 V00T0000
arc: A3 S1_V02N0701
arc: A4 V00B0000
arc: A5 Q5
arc: A6 H00R0000
arc: A7 Q7
arc: B0 E1_H02W0301
arc: B2 V02N0301
arc: B3 Q3
arc: B4 H00L0000
arc: B5 V02S0701
arc: B6 H02W0101
arc: B7 V02N0701
arc: CE1 H00R0100
arc: CE2 S1_V02N0601
arc: CE3 S1_V02N0601
arc: CLK0 G_HPBX0000
arc: E1_H01E0101 F4
arc: E3_H06E0003 F3
arc: E3_H06E0203 F7
arc: E3_H06E0303 F5
arc: F2 F2_SLICE
arc: F3 F3_SLICE
arc: F4 F4_SLICE
arc: F5 F5_SLICE
arc: F6 F6_SLICE
arc: F7 F7_SLICE
arc: H00R0000 Q6
arc: H01W0100 F6
arc: LSR0 E1_H02W0501
arc: LSR1 E1_H02W0501
arc: MUXCLK1 CLK0
arc: MUXCLK2 CLK0
arc: MUXCLK3 CLK0
arc: MUXLSR1 LSR0
arc: MUXLSR2 LSR0
arc: MUXLSR3 LSR1
arc: N1_V01N0001 F3
arc: N1_V01N0101 F2
arc: N1_V02N0501 F5
arc: N1_V02N0601 F6
arc: N1_V02N0701 F7
arc: V00B0000 Q4
arc: V00T0000 Q2
arc: V01S0100 F4
word: SLICED.K1.INIT 0110011001101010
word: SLICED.K0.INIT 0110011001101010
word: SLICEC.K1.INIT 0110011001101010
word: SLICEC.K0.INIT 0110011001101010
word: SLICEB.K1.INIT 0110011001101100
word: SLICEB.K0.INIT 0110011001101010
word: SLICEA.K1.INIT 1111111111111111
word: SLICEA.K0.INIT 0000000000001100
enum: SLICED.MODE CCU2
enum: SLICED.CCU2.INJECT1_1 NO
enum: SLICED.C1MUX 1
enum: SLICED.D1MUX 1
enum: SLICED.MODE CCU2
enum: SLICED.CCU2.INJECT1_0 NO
enum: SLICED.C0MUX 1
enum: SLICED.D0MUX 1
enum: SLICEC.MODE CCU2
enum: SLICEC.CCU2.INJECT1_1 NO
enum: SLICEC.C1MUX 1
enum: SLICEC.D1MUX 1
enum: SLICEC.MODE CCU2
enum: SLICEC.CCU2.INJECT1_0 NO
enum: SLICEC.C0MUX 1
enum: SLICEC.D0MUX 1
enum: SLICEB.MODE CCU2
enum: SLICEB.CCU2.INJECT1_1 NO
enum: SLICEB.C1MUX 1
enum: SLICEB.D1MUX 1
enum: SLICEB.MODE CCU2
enum: SLICEB.CCU2.INJECT1_0 NO
enum: SLICEB.C0MUX 1
enum: SLICEB.D0MUX 1
enum: SLICEA.MODE CCU2
enum: SLICEA.CCU2.INJECT1_1 YES
enum: SLICEA.A1MUX 1
enum: SLICEA.B1MUX 1
enum: SLICEA.C1MUX 1
enum: SLICEA.D1MUX 1
enum: SLICEA.MODE CCU2
enum: SLICEA.CCU2.INJECT1_0 NO
enum: SLICEA.A0MUX 1
enum: SLICEA.C0MUX 1
enum: SLICEA.D0MUX 1
enum: SLICED.GSR DISABLED
enum: SLICED.REG0.SD 1
enum: SLICED.REG0.REGSET RESET
enum: SLICED.REG0.LSRMODE LSR
enum: SLICED.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEB.GSR DISABLED
enum: SLICEB.REG1.SD 1
enum: SLICEB.REG1.REGSET RESET
enum: SLICEB.REG1.LSRMODE LSR
enum: SLICEB.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEB.GSR DISABLED
enum: SLICEB.REG0.SD 1
enum: SLICEB.REG0.REGSET RESET
enum: SLICEB.REG0.LSRMODE LSR
enum: SLICEB.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEC.GSR DISABLED
enum: SLICEC.REG0.SD 1
enum: SLICEC.REG0.REGSET RESET
enum: SLICEC.REG0.LSRMODE LSR
enum: SLICEC.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEC.GSR DISABLED
enum: SLICEC.REG1.SD 1
enum: SLICEC.REG1.REGSET RESET
enum: SLICEC.REG1.LSRMODE LSR
enum: SLICEC.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICED.GSR DISABLED
enum: SLICED.REG1.SD 1
enum: SLICED.REG1.REGSET RESET
enum: SLICED.REG1.LSRMODE LSR
enum: SLICED.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
.tile R42C49:PLC2
arc: H00L0100 V02N0301
arc: H00R0000 H02E0601
arc: N1_V02N0201 H06W0103
arc: N1_V02N0301 H01E0101
arc: W1_H02W0101 V06N0103
arc: A0 H02W0701
arc: A1 S1_V02N0701
arc: A2 S1_V02N0501
arc: A3 H00L0100
arc: A4 V00B0000
arc: A5 Q5
arc: A6 S1_V02N0301
arc: A7 Q7
arc: B0 V00T0000
arc: B1 Q1
arc: B2 H00L0000
arc: B3 Q3
arc: B4 V02N0701
arc: B5 V02S0701
arc: B6 V01S0000
arc: B7 V02N0501
arc: CE0 H00R0000
arc: CE1 H00R0000
arc: CE2 H00R0000
arc: CE3 H00R0000
arc: CLK0 G_HPBX0000
arc: F0 F0_SLICE
arc: F1 F1_SLICE
arc: F2 F2_SLICE
arc: F3 F3_SLICE
arc: F4 F4_SLICE
arc: F5 F5_SLICE
arc: F6 F6_SLICE
arc: F7 F7_SLICE
arc: H00L0000 Q2
arc: H01W0100 F0
arc: LSR1 H02W0501
arc: MUXCLK0 CLK0
arc: MUXCLK1 CLK0
arc: MUXCLK2 CLK0
arc: MUXCLK3 CLK0
arc: MUXLSR0 LSR1
arc: MUXLSR1 LSR1
arc: MUXLSR2 LSR1
arc: MUXLSR3 LSR1
arc: N1_V01N0001 F1
arc: N1_V01N0101 F3
arc: N1_V02N0001 F2
arc: N1_V02N0401 F4
arc: N1_V02N0501 F7
arc: N1_V02N0601 F6
arc: N1_V02N0701 F5
arc: V00B0000 Q4
arc: V00T0000 Q0
arc: V01S0000 Q6
arc: V01S0100 F0
word: SLICED.K1.INIT 0110011001101010
word: SLICED.K0.INIT 0110011001101100
word: SLICEC.K1.INIT 0110011001101010
word: SLICEC.K0.INIT 0110011001101010
word: SLICEB.K1.INIT 0110011001101100
word: SLICEB.K0.INIT 0110011001101100
word: SLICEA.K1.INIT 0110011001101100
word: SLICEA.K0.INIT 0110011001101100
enum: SLICED.MODE CCU2
enum: SLICED.CCU2.INJECT1_1 NO
enum: SLICED.C1MUX 1
enum: SLICED.D1MUX 1
enum: SLICED.MODE CCU2
enum: SLICED.CCU2.INJECT1_0 NO
enum: SLICED.C0MUX 1
enum: SLICED.D0MUX 1
enum: SLICEC.MODE CCU2
enum: SLICEC.CCU2.INJECT1_1 NO
enum: SLICEC.C1MUX 1
enum: SLICEC.D1MUX 1
enum: SLICEC.MODE CCU2
enum: SLICEC.CCU2.INJECT1_0 NO
enum: SLICEC.C0MUX 1
enum: SLICEC.D0MUX 1
enum: SLICEB.MODE CCU2
enum: SLICEB.CCU2.INJECT1_1 NO
enum: SLICEB.C1MUX 1
enum: SLICEB.D1MUX 1
enum: SLICEB.MODE CCU2
enum: SLICEB.CCU2.INJECT1_0 NO
enum: SLICEB.C0MUX 1
enum: SLICEB.D0MUX 1
enum: SLICEA.MODE CCU2
enum: SLICEA.CCU2.INJECT1_1 NO
enum: SLICEA.C1MUX 1
enum: SLICEA.D1MUX 1
enum: SLICEA.MODE CCU2
enum: SLICEA.CCU2.INJECT1_0 NO
enum: SLICEA.C0MUX 1
enum: SLICEA.D0MUX 1
enum: SLICEC.GSR DISABLED
enum: SLICEC.REG1.SD 1
enum: SLICEC.REG1.REGSET RESET
enum: SLICEC.REG1.LSRMODE LSR
enum: SLICEC.CEMUX CE
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICED.GSR DISABLED
enum: SLICED.REG0.SD 1
enum: SLICED.REG0.REGSET RESET
enum: SLICED.REG0.LSRMODE LSR
enum: SLICED.CEMUX CE
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEA.GSR DISABLED
enum: SLICEA.REG0.SD 1
enum: SLICEA.REG0.REGSET RESET
enum: SLICEA.REG0.LSRMODE LSR
enum: SLICEA.CEMUX CE
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEB.GSR DISABLED
enum: SLICEB.REG1.SD 1
enum: SLICEB.REG1.REGSET RESET
enum: SLICEB.REG1.LSRMODE LSR
enum: SLICEB.CEMUX CE
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICED.GSR DISABLED
enum: SLICED.REG1.SD 1
enum: SLICED.REG1.REGSET RESET
enum: SLICED.REG1.LSRMODE LSR
enum: SLICED.CEMUX CE
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEA.GSR DISABLED
enum: SLICEA.REG1.SD 1
enum: SLICEA.REG1.REGSET RESET
enum: SLICEA.REG1.LSRMODE LSR
enum: SLICEA.CEMUX CE
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEC.GSR DISABLED
enum: SLICEC.REG0.SD 1
enum: SLICEC.REG0.REGSET RESET
enum: SLICEC.REG0.LSRMODE LSR
enum: SLICEC.CEMUX CE
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEB.GSR DISABLED
enum: SLICEB.REG0.SD 1
enum: SLICEB.REG0.REGSET RESET
enum: SLICEB.REG0.LSRMODE LSR
enum: SLICEB.CEMUX CE
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
.tile R42C4:PLC2
arc: W3_H06W0203 E1_H01W0000
.tile R42C50:PLC2
arc: E1_H02E0501 V06S0303
arc: H00L0000 S1_V02N0201
arc: H00L0100 V02N0301
arc: V00B0000 V02S0201
arc: V00B0100 H02W0501
arc: W1_H02W0301 V06S0003
arc: W1_H02W0501 V06S0303
arc: W1_H02W0701 V06N0203
arc: A0 S1_V02N0501
arc: A1 H00L0100
arc: A2 H02W0501
arc: A3 H02W0501
arc: A4 H02W0501
arc: A5 Q5
arc: A6 H02W0501
arc: A7 Q7
arc: B0 V00T0000
arc: B1 Q1
arc: B2 H01W0100
arc: B3 Q3
arc: B4 H00R0000
arc: B5 V00B0100
arc: B6 V01S0000
arc: B7 V00B0100
arc: CE0 S1_V02N0201
arc: CE1 S1_V02N0201
arc: CE2 H00L0000
arc: CE3 H00L0000
arc: CLK0 G_HPBX0000
arc: F0 F0_SLICE
arc: F1 F1_SLICE
arc: F2 F2_SLICE
arc: F3 F3_SLICE
arc: F4 F4_SLICE
arc: F5 F5_SLICE
arc: F6 F6_SLICE
arc: F7 F7_SLICE
arc: H00R0000 Q4
arc: H01W0100 Q2
arc: LSR0 V00B0000
arc: LSR1 V00B0000
arc: MUXCLK0 CLK0
arc: MUXCLK1 CLK0
arc: MUXCLK2 CLK0
arc: MUXCLK3 CLK0
arc: MUXLSR0 LSR0
arc: MUXLSR1 LSR0
arc: MUXLSR2 LSR1
arc: MUXLSR3 LSR0
arc: N1_V01N0001 F3
arc: N1_V01N0101 F1
arc: N1_V02N0001 F2
arc: N1_V02N0201 F0
arc: N1_V02N0501 F5
arc: N1_V02N0601 F6
arc: N1_V02N0701 F7
arc: V00T0000 Q0
arc: V01S0000 Q6
arc: V01S0100 F4
word: SLICED.K1.INIT 0110011001101010
word: SLICED.K0.INIT 0110011001101100
word: SLICEC.K1.INIT 0110011001101010
word: SLICEC.K0.INIT 0110011001101100
word: SLICEB.K1.INIT 0110011001101100
word: SLICEB.K0.INIT 0110011001101100
word: SLICEA.K1.INIT 0110011001101100
word: SLICEA.K0.INIT 0110011001101100
enum: SLICED.MODE CCU2
enum: SLICED.CCU2.INJECT1_1 NO
enum: SLICED.C1MUX 1
enum: SLICED.D1MUX 1
enum: SLICED.MODE CCU2
enum: SLICED.CCU2.INJECT1_0 NO
enum: SLICED.C0MUX 1
enum: SLICED.D0MUX 1
enum: SLICEC.MODE CCU2
enum: SLICEC.CCU2.INJECT1_1 NO
enum: SLICEC.C1MUX 1
enum: SLICEC.D1MUX 1
enum: SLICEC.MODE CCU2
enum: SLICEC.CCU2.INJECT1_0 NO
enum: SLICEC.C0MUX 1
enum: SLICEC.D0MUX 1
enum: SLICEB.MODE CCU2
enum: SLICEB.CCU2.INJECT1_1 NO
enum: SLICEB.C1MUX 1
enum: SLICEB.D1MUX 1
enum: SLICEB.MODE CCU2
enum: SLICEB.CCU2.INJECT1_0 NO
enum: SLICEB.C0MUX 1
enum: SLICEB.D0MUX 1
enum: SLICEA.MODE CCU2
enum: SLICEA.CCU2.INJECT1_1 NO
enum: SLICEA.C1MUX 1
enum: SLICEA.D1MUX 1
enum: SLICEA.MODE CCU2
enum: SLICEA.CCU2.INJECT1_0 NO
enum: SLICEA.C0MUX 1
enum: SLICEA.D0MUX 1
enum: SLICEC.GSR DISABLED
enum: SLICEC.REG1.SD 1
enum: SLICEC.REG1.REGSET RESET
enum: SLICEC.REG1.LSRMODE LSR
enum: SLICEC.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEC.GSR DISABLED
enum: SLICEC.REG0.SD 1
enum: SLICEC.REG0.REGSET RESET
enum: SLICEC.REG0.LSRMODE LSR
enum: SLICEC.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICED.GSR DISABLED
enum: SLICED.REG1.SD 1
enum: SLICED.REG1.REGSET RESET
enum: SLICED.REG1.LSRMODE LSR
enum: SLICED.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEA.GSR DISABLED
enum: SLICEA.REG1.SD 1
enum: SLICEA.REG1.REGSET RESET
enum: SLICEA.REG1.LSRMODE LSR
enum: SLICEA.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEB.GSR DISABLED
enum: SLICEB.REG0.SD 1
enum: SLICEB.REG0.REGSET RESET
enum: SLICEB.REG0.LSRMODE LSR
enum: SLICEB.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEA.GSR DISABLED
enum: SLICEA.REG0.SD 1
enum: SLICEA.REG0.REGSET RESET
enum: SLICEA.REG0.LSRMODE LSR
enum: SLICEA.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICED.GSR DISABLED
enum: SLICED.REG0.SD 1
enum: SLICED.REG0.REGSET RESET
enum: SLICED.REG0.LSRMODE LSR
enum: SLICED.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEB.GSR DISABLED
enum: SLICEB.REG1.SD 1
enum: SLICEB.REG1.REGSET RESET
enum: SLICEB.REG1.LSRMODE LSR
enum: SLICEB.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
.tile R42C51:PLC2
arc: E1_H02E0501 V02N0501
arc: H00L0000 S1_V02N0201
arc: N1_V02N0301 E1_H01W0100
arc: N1_V02N0601 H06E0303
arc: W1_H02W0501 V02N0501
arc: A0 V02N0501
arc: A1 V02N0501
arc: A2 V02N0501
arc: A3 V02N0501
arc: A4 V00B0000
arc: A5 Q5
arc: A6 H00R0000
arc: A7 Q7
arc: B0 V00T0000
arc: B1 Q1
arc: B2 H01W0100
arc: B3 Q3
arc: B4 V02N0501
arc: B5 V02N0501
arc: B6 V02N0501
arc: B7 V02N0501
arc: CE0 S1_V02N0201
arc: CE1 S1_V02N0201
arc: CE2 H00L0000
arc: CE3 H00L0000
arc: CLK0 G_HPBX0000
arc: F0 F0_SLICE
arc: F1 F1_SLICE
arc: F2 F2_SLICE
arc: F3 F3_SLICE
arc: F4 F4_SLICE
arc: F5 F5_SLICE
arc: F6 F6_SLICE
arc: F7 F7_SLICE
arc: H00R0000 Q6
arc: H01W0100 Q2
arc: LSR1 H02E0501
arc: MUXCLK0 CLK0
arc: MUXCLK1 CLK0
arc: MUXCLK2 CLK0
arc: MUXCLK3 CLK0
arc: MUXLSR0 LSR1
arc: MUXLSR1 LSR1
arc: MUXLSR2 LSR1
arc: MUXLSR3 LSR1
arc: N1_V01N0001 F1
arc: N1_V01N0101 F3
arc: N1_V02N0001 F0
arc: N1_V02N0201 F2
arc: N1_V02N0401 F4
arc: N1_V02N0501 F7
arc: N1_V02N0701 F5
arc: V00B0000 Q4
arc: V00T0000 Q0
arc: V01S0100 F6
word: SLICED.K1.INIT 0110011001101010
word: SLICED.K0.INIT 0110011001101010
word: SLICEC.K1.INIT 0110011001101010
word: SLICEC.K0.INIT 0110011001101010
word: SLICEB.K1.INIT 0110011001101100
word: SLICEB.K0.INIT 0110011001101100
word: SLICEA.K1.INIT 0110011001101100
word: SLICEA.K0.INIT 0110011001101100
enum: SLICED.MODE CCU2
enum: SLICED.CCU2.INJECT1_1 NO
enum: SLICED.C1MUX 1
enum: SLICED.D1MUX 1
enum: SLICED.MODE CCU2
enum: SLICED.CCU2.INJECT1_0 NO
enum: SLICED.C0MUX 1
enum: SLICED.D0MUX 1
enum: SLICEC.MODE CCU2
enum: SLICEC.CCU2.INJECT1_1 NO
enum: SLICEC.C1MUX 1
enum: SLICEC.D1MUX 1
enum: SLICEC.MODE CCU2
enum: SLICEC.CCU2.INJECT1_0 NO
enum: SLICEC.C0MUX 1
enum: SLICEC.D0MUX 1
enum: SLICEB.MODE CCU2
enum: SLICEB.CCU2.INJECT1_1 NO
enum: SLICEB.C1MUX 1
enum: SLICEB.D1MUX 1
enum: SLICEB.MODE CCU2
enum: SLICEB.CCU2.INJECT1_0 NO
enum: SLICEB.C0MUX 1
enum: SLICEB.D0MUX 1
enum: SLICEA.MODE CCU2
enum: SLICEA.CCU2.INJECT1_1 NO
enum: SLICEA.C1MUX 1
enum: SLICEA.D1MUX 1
enum: SLICEA.MODE CCU2
enum: SLICEA.CCU2.INJECT1_0 NO
enum: SLICEA.C0MUX 1
enum: SLICEA.D0MUX 1
enum: SLICEC.GSR DISABLED
enum: SLICEC.REG0.SD 1
enum: SLICEC.REG0.REGSET RESET
enum: SLICEC.REG0.LSRMODE LSR
enum: SLICEC.CEMUX CE
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEA.GSR DISABLED
enum: SLICEA.REG0.SD 1
enum: SLICEA.REG0.REGSET RESET
enum: SLICEA.REG0.LSRMODE LSR
enum: SLICEA.CEMUX CE
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEB.GSR DISABLED
enum: SLICEB.REG0.SD 1
enum: SLICEB.REG0.REGSET RESET
enum: SLICEB.REG0.LSRMODE LSR
enum: SLICEB.CEMUX CE
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEA.GSR DISABLED
enum: SLICEA.REG1.SD 1
enum: SLICEA.REG1.REGSET RESET
enum: SLICEA.REG1.LSRMODE LSR
enum: SLICEA.CEMUX CE
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEB.GSR DISABLED
enum: SLICEB.REG1.SD 1
enum: SLICEB.REG1.REGSET RESET
enum: SLICEB.REG1.LSRMODE LSR
enum: SLICEB.CEMUX CE
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICED.GSR DISABLED
enum: SLICED.REG0.SD 1
enum: SLICED.REG0.REGSET RESET
enum: SLICED.REG0.LSRMODE LSR
enum: SLICED.CEMUX CE
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEC.GSR DISABLED
enum: SLICEC.REG1.SD 1
enum: SLICEC.REG1.REGSET RESET
enum: SLICEC.REG1.LSRMODE LSR
enum: SLICEC.CEMUX CE
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICED.GSR DISABLED
enum: SLICED.REG1.SD 1
enum: SLICED.REG1.REGSET RESET
enum: SLICED.REG1.LSRMODE LSR
enum: SLICED.CEMUX CE
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
.tile R42C52:PLC2
arc: E1_H02E0001 N1_V01S0000
arc: E1_H02E0101 N1_V02S0101
arc: A0 H02E0501
arc: A1 H02E0501
arc: B0 V00T0000
arc: B1 Q1
arc: CE0 S1_V02N0201
arc: CLK0 G_HPBX0000
arc: E1_H01E0101 F1
arc: E1_H02E0301 F1
arc: F0 F0_SLICE
arc: F1 F1_SLICE
arc: H01W0100 F1
arc: LSR1 W1_H02E0501
arc: MUXCLK0 CLK0
arc: MUXLSR0 LSR1
arc: N1_V02N0201 F0
arc: V00T0000 Q0
arc: W3_H06W0103 F1
word: SLICEB.K1.INIT 0000000000001110
word: SLICEB.K0.INIT 0000000000000000
word: SLICEA.K1.INIT 0110011001101100
word: SLICEA.K0.INIT 0110011001101100
enum: SLICEB.MODE CCU2
enum: SLICEB.CCU2.INJECT1_1 NO
enum: SLICEB.A1MUX 1
enum: SLICEB.B1MUX 1
enum: SLICEB.C1MUX 1
enum: SLICEB.D1MUX 1
enum: SLICEB.MODE CCU2
enum: SLICEB.CCU2.INJECT1_0 NO
enum: SLICEB.A0MUX 1
enum: SLICEB.B0MUX 1
enum: SLICEB.C0MUX 1
enum: SLICEB.D0MUX 1
enum: SLICEA.MODE CCU2
enum: SLICEA.CCU2.INJECT1_1 NO
enum: SLICEA.C1MUX 1
enum: SLICEA.D1MUX 1
enum: SLICEA.MODE CCU2
enum: SLICEA.CCU2.INJECT1_0 NO
enum: SLICEA.C0MUX 1
enum: SLICEA.D0MUX 1
enum: SLICEA.GSR DISABLED
enum: SLICEA.REG0.SD 1
enum: SLICEA.REG0.REGSET RESET
enum: SLICEA.REG0.LSRMODE LSR
enum: SLICEA.CEMUX CE
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEA.GSR DISABLED
enum: SLICEA.REG1.SD 1
enum: SLICEA.REG1.REGSET RESET
enum: SLICEA.REG1.LSRMODE LSR
enum: SLICEA.CEMUX CE
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
.tile R42C53:PLC2
arc: N1_V02N0001 H02W0001
arc: N1_V02N0101 H01E0101
arc: V00B0000 V02S0201
arc: B0 H02E0301
arc: C0 H02W0401
arc: CE0 H02E0101
arc: CLK0 G_HPBX0000
arc: D0 H02E0001
arc: E3_H06E0003 Q0
arc: F0 F0_SLICE
arc: LSR1 V00B0000
arc: MUXCLK0 CLK0
arc: MUXLSR0 LSR1
word: SLICEA.K0.INIT 0011000000110011
enum: SLICEA.MODE LOGIC
enum: SLICEA.CCU2.INJECT1_0 _NONE_
enum: SLICEA.A0MUX 1
enum: SLICEA.GSR DISABLED
enum: SLICEA.REG0.SD 1
enum: SLICEA.REG0.REGSET RESET
enum: SLICEA.REG0.LSRMODE LSR
enum: SLICEA.CEMUX CE
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
.tile R42C54:PLC2
arc: W1_H02W0001 W3_H06E0003
arc: W1_H02W0401 W3_H06E0203
.tile R42C59:PLC2
arc: E3_H06E0003 W3_H06E0003
.tile R42C5:PLC2
arc: H01W0000 E3_H06W0103
.tile R42C65:PLC2
arc: E3_H06E0103 W3_H06E0003
.tile R42C71:PLC2
arc: E3_H06E0103 W3_H06E0103
.tile R42C77:PLC2
arc: E3_H06E0203 W3_H06E0103
.tile R42C83:PLC2
arc: E3_H06E0203 W3_H06E0203
.tile R43C47:PLC2
arc: N1_V02N0501 N3_V06S0303
.tile R43C48:PLC2
arc: N1_V02N0301 S1_V02N0201
arc: N1_V02N0501 N1_V01S0100
arc: N1_V02N0701 S1_V02N0701
.tile R43C49:PLC2
arc: N1_V02N0101 N1_V01S0100
arc: N1_V02N0301 S1_V02N0301
arc: N1_V02N0501 S1_V02N0501
arc: N1_V02N0701 S1_V02N0601
.tile R43C50:PLC2
arc: N1_V02N0301 S1_V02N0301
arc: N1_V02N0701 N1_V01S0100
.tile R43C51:PLC2
arc: N1_V02N0501 S1_V02N0501
arc: N1_V02N0701 N1_V01S0100
.tile R44C18:PLC2
arc: S3_V06S0303 N3_V06S0203
.tile R44C48:PLC2
arc: N1_V02N0201 V01N0001
arc: N1_V02N0501 N3_V06S0303
arc: N1_V02N0601 N3_V06S0303
arc: N1_V02N0701 V01N0101
.tile R44C49:PLC2
arc: N1_V02N0301 V01N0101
arc: N1_V02N0501 H02W0501
arc: N1_V02N0701 S1_V02N0601
arc: S1_V02S0501 N3_V06S0303
.tile R44C50:PLC2
arc: N1_V02N0201 E1_H02W0201
arc: N1_V02N0501 V01N0101
arc: W1_H02W0501 V02N0501
.tile R44C51:PLC2
arc: N1_V02N0201 H02W0201
.tile R44C52:PLC2
arc: N1_V02N0201 N3_V06S0103
arc: S1_V02S0401 N3_V06S0203
arc: W1_H02W0201 N3_V06S0103
.tile R45C17:PLC2
arc: S3_V06S0303 N3_V06S0203
.tile R45C46:PLC2
arc: E1_H02E0201 V01N0001
arc: E1_H02E0501 V02N0501
arc: E1_H02E0601 V02N0601
arc: E1_H02E0701 V01N0101
.tile R45C47:PLC2
arc: E1_H02E0001 V01N0001
arc: E1_H02E0101 V01N0101
arc: E1_H02E0201 V02N0201
arc: E1_H02E0301 V02N0301
arc: E1_H02E0601 V02N0601
arc: E1_H02E0701 V02N0701
.tile R45C48:PLC2
arc: E1_H02E0101 V02N0101
arc: E1_H02E0301 V02N0301
arc: E1_H02E0401 V01N0001
arc: E1_H02E0501 V01N0101
arc: H00R0000 W1_H02E0601
arc: V00B0000 V02N0001
arc: V00T0000 W1_H02E0201
arc: A2 E1_H02W0701
arc: A3 W1_H02E0501
arc: A4 W1_H02E0701
arc: A5 V00T0000
arc: A6 H02W0701
arc: A7 E1_H02W0501
arc: B0 E1_H02W0301
arc: B2 H00R0000
arc: B3 H02W0301
arc: B4 E1_H02W0101
arc: B5 V02N0501
arc: B6 V02N0701
arc: B7 V00B0000
arc: E1_H01E0101 F6
arc: F2 F2_SLICE
arc: F3 F3_SLICE
arc: F4 F4_SLICE
arc: F5 F5_SLICE
arc: F6 F6_SLICE
arc: F7 F7_SLICE
arc: N1_V01N0001 F4
arc: N1_V01N0101 F3
arc: N1_V02N0201 F2
arc: N1_V02N0701 F7
arc: N3_V06N0303 F5
word: SLICED.K1.INIT 0110011001101100
word: SLICED.K0.INIT 0110011001101100
word: SLICEC.K1.INIT 0110011001101010
word: SLICEC.K0.INIT 0110011001101010
word: SLICEB.K1.INIT 0110011001101010
word: SLICEB.K0.INIT 0110011001101100
word: SLICEA.K1.INIT 1111111111111111
word: SLICEA.K0.INIT 0000000000001100
enum: SLICED.MODE CCU2
enum: SLICED.CCU2.INJECT1_1 NO
enum: SLICED.C1MUX 1
enum: SLICED.D1MUX 1
enum: SLICED.MODE CCU2
enum: SLICED.CCU2.INJECT1_0 NO
enum: SLICED.C0MUX 1
enum: SLICED.D0MUX 1
enum: SLICEC.MODE CCU2
enum: SLICEC.CCU2.INJECT1_1 NO
enum: SLICEC.C1MUX 1
enum: SLICEC.D1MUX 1
enum: SLICEC.MODE CCU2
enum: SLICEC.CCU2.INJECT1_0 NO
enum: SLICEC.C0MUX 1
enum: SLICEC.D0MUX 1
enum: SLICEB.MODE CCU2
enum: SLICEB.CCU2.INJECT1_1 NO
enum: SLICEB.C1MUX 1
enum: SLICEB.D1MUX 1
enum: SLICEB.MODE CCU2
enum: SLICEB.CCU2.INJECT1_0 NO
enum: SLICEB.C0MUX 1
enum: SLICEB.D0MUX 1
enum: SLICEA.MODE CCU2
enum: SLICEA.CCU2.INJECT1_1 YES
enum: SLICEA.A1MUX 1
enum: SLICEA.B1MUX 1
enum: SLICEA.C1MUX 1
enum: SLICEA.D1MUX 1
enum: SLICEA.MODE CCU2
enum: SLICEA.CCU2.INJECT1_0 NO
enum: SLICEA.A0MUX 1
enum: SLICEA.C0MUX 1
enum: SLICEA.D0MUX 1
.tile R45C49:PLC2
arc: H00L0000 W1_H02E0201
arc: H00R0000 E1_H02W0401
arc: N3_V06N0103 H01E0101
arc: V00B0000 W1_H02E0601
arc: V00T0000 W1_H02E0001
arc: W1_H02W0301 E1_H02W0301
arc: W1_H02W0701 E1_H02W0601
arc: A0 H00L0000
arc: A1 H00R0000
arc: A2 V00T0000
arc: A3 W1_H02E0701
arc: A4 V00B0000
arc: A5 E1_H02W0501
arc: A6 H02E0501
arc: A7 E1_H02W0701
arc: B0 E1_H02W0101
arc: B1 W1_H02E0301
arc: B2 V02N0301
arc: B3 V02N0101
arc: B4 V02N0501
arc: B5 W1_H02E0101
arc: B6 V02N0701
arc: B7 H02E0101
arc: E1_H01E0001 F0
arc: E1_H01E0101 F2
arc: F0 F0_SLICE
arc: F1 F1_SLICE
arc: F2 F2_SLICE
arc: F3 F3_SLICE
arc: F4 F4_SLICE
arc: F5 F5_SLICE
arc: F6 F6_SLICE
arc: F7 F7_SLICE
arc: N1_V01N0101 F6
arc: N1_V02N0301 F3
arc: N1_V02N0501 F7
arc: N1_V02N0601 F4
arc: N3_V06N0303 F5
arc: V01S0000 F1
word: SLICED.K1.INIT 0110011001101100
word: SLICED.K0.INIT 0110011001101010
word: SLICEC.K1.INIT 0110011001101100
word: SLICEC.K0.INIT 0110011001101010
word: SLICEB.K1.INIT 0110011001101010
word: SLICEB.K0.INIT 0110011001101010
word: SLICEA.K1.INIT 0110011001101100
word: SLICEA.K0.INIT 0110011001101010
enum: SLICED.MODE CCU2
enum: SLICED.CCU2.INJECT1_1 NO
enum: SLICED.C1MUX 1
enum: SLICED.D1MUX 1
enum: SLICED.MODE CCU2
enum: SLICED.CCU2.INJECT1_0 NO
enum: SLICED.C0MUX 1
enum: SLICED.D0MUX 1
enum: SLICEC.MODE CCU2
enum: SLICEC.CCU2.INJECT1_1 NO
enum: SLICEC.C1MUX 1
enum: SLICEC.D1MUX 1
enum: SLICEC.MODE CCU2
enum: SLICEC.CCU2.INJECT1_0 NO
enum: SLICEC.C0MUX 1
enum: SLICEC.D0MUX 1
enum: SLICEB.MODE CCU2
enum: SLICEB.CCU2.INJECT1_1 NO
enum: SLICEB.C1MUX 1
enum: SLICEB.D1MUX 1
enum: SLICEB.MODE CCU2
enum: SLICEB.CCU2.INJECT1_0 NO
enum: SLICEB.C0MUX 1
enum: SLICEB.D0MUX 1
enum: SLICEA.MODE CCU2
enum: SLICEA.CCU2.INJECT1_1 NO
enum: SLICEA.C1MUX 1
enum: SLICEA.D1MUX 1
enum: SLICEA.MODE CCU2
enum: SLICEA.CCU2.INJECT1_0 NO
enum: SLICEA.C0MUX 1
enum: SLICEA.D0MUX 1
.tile R45C50:PLC2
arc: H00R0000 W1_H02E0401
arc: N1_V02N0501 H01E0101
arc: N3_V06N0203 H01E0001
arc: S1_V02S0301 N3_V06S0003
arc: W1_H02W0101 E1_H02W0001
arc: W1_H02W0301 N3_V06S0003
arc: W1_H02W0501 S1_V02N0501
arc: W1_H02W0701 E1_H02W0701
arc: A0 H00R0000
arc: A1 E1_H02W0501
arc: A2 E1_H02W0501
arc: B0 E1_H02W0101
arc: B1 W1_H02E0301
arc: B2 W1_H02E0301
arc: E1_H01E0101 F2
arc: F0 F0_SLICE
arc: F1 F1_SLICE
arc: F2 F2_SLICE
arc: N1_V01N0101 F0
arc: N1_V02N0301 F1
word: SLICEC.K1.INIT 0000000000001110
word: SLICEC.K0.INIT 0000000000000000
word: SLICEB.K1.INIT 0000000000000000
word: SLICEB.K0.INIT 0110011001101100
word: SLICEA.K1.INIT 0110011001101100
word: SLICEA.K0.INIT 0110011001101010
enum: SLICEC.MODE CCU2
enum: SLICEC.CCU2.INJECT1_1 NO
enum: SLICEC.A1MUX 1
enum: SLICEC.B1MUX 1
enum: SLICEC.C1MUX 1
enum: SLICEC.D1MUX 1
enum: SLICEC.MODE CCU2
enum: SLICEC.CCU2.INJECT1_0 NO
enum: SLICEC.A0MUX 1
enum: SLICEC.B0MUX 1
enum: SLICEC.C0MUX 1
enum: SLICEC.D0MUX 1
enum: SLICEB.MODE CCU2
enum: SLICEB.CCU2.INJECT1_1 NO
enum: SLICEB.A1MUX 1
enum: SLICEB.B1MUX 1
enum: SLICEB.C1MUX 1
enum: SLICEB.D1MUX 1
enum: SLICEB.MODE CCU2
enum: SLICEB.CCU2.INJECT1_0 NO
enum: SLICEB.C0MUX 1
enum: SLICEB.D0MUX 1
enum: SLICEA.MODE CCU2
enum: SLICEA.CCU2.INJECT1_1 NO
enum: SLICEA.C1MUX 1
enum: SLICEA.D1MUX 1
enum: SLICEA.MODE CCU2
enum: SLICEA.CCU2.INJECT1_0 NO
enum: SLICEA.C0MUX 1
enum: SLICEA.D0MUX 1
.tile R45C51:PLC2
arc: N1_V02N0501 H01E0101
arc: W1_H02W0101 V01N0101
arc: W1_H02W0301 V02N0301
arc: W1_H02W0401 V01N0001
arc: W1_H02W0501 E1_H02W0401
arc: W1_H02W0601 V02N0601
arc: W1_H02W0701 V02N0701
.tile R45C52:PLC2
arc: W1_H02W0001 V02N0001
arc: W1_H02W0101 V01N0101
arc: W1_H02W0501 V02N0501
arc: W1_H02W0701 V02N0701
.tile R45C53:PLC2
arc: W1_H02W0401 V02N0401
.tile R47C50:PLC2
arc: N1_V02N0501 H02W0501
.tile R47C51:PLC2
arc: W1_H02W0501 V02S0501
.tile R4C18:PLC2
arc: N3_V06N0203 S3_V06N0103
.tile R4C49:PLC2
arc: N1_V02N0601 S3_V06N0303
.tile R4C51:PLC2
arc: N1_V02N0501 S3_V06N0303
.tile R50C18:PLC2
arc: S3_V06S0003 N3_V06S0303
.tile R51C17:PLC2
arc: S3_V06S0303 N3_V06S0303
.tile R56C18:PLC2
arc: S3_V06S0103 N3_V06S0003
.tile R57C17:PLC2
arc: S3_V06S0303 N3_V06S0303
.tile R5C41:PLC2
arc: N1_V02N0701 S3_V06N0203
.tile R62C18:PLC2
arc: S3_V06S0203 N3_V06S0103
.tile R63C17:PLC2
arc: S3_V06S0303 N3_V06S0303
.tile R68C18:PLC2
arc: S1_V02S0701 N3_V06S0203
.tile R69C17:PLC2
arc: V01S0100 N3_V06S0303
.tile R7C37:PLC2
arc: N3_V06N0303 S3_V06N0203
.tile R7C39:PLC2
arc: N3_V06N0203 S3_V06N0203
.tile R7C63:PLC2
arc: N3_V06N0203 S3_V06N0103
.tile R8C38:PLC2
arc: N3_V06N0303 S3_V06N0303
.tile R8C67:PLC2
arc: N3_V06N0003 S3_V06N0003
arc: N3_V06N0203 S3_V06N0203
.tile R9C18:PLC2
arc: N3_V06N0203 S3_V06N0103
.tile R9C60:PLC2
arc: N3_V06N0303 S1_V02N0601
.tile R9C75:PLC2
arc: N3_V06N0003 S3_V06N0003
arc: N3_V06N0303 S3_V06N0203
.tile R9C76:PLC2
arc: N3_V06N0203 S3_V06N0103
.tile TAP_R17C13:TAP_DRIVE
arc: R_HPBX0000 G_VPTX0000
.tile TAP_R18C13:TAP_DRIVE
arc: R_HPBX0000 G_VPTX0000
.tile TAP_R19C13:TAP_DRIVE
arc: R_HPBX0000 G_VPTX0000
.tile TAP_R19C31:TAP_DRIVE
arc: L_HPBX0000 G_VPTX0000
.tile TAP_R19C51:TAP_DRIVE
arc: R_HPBX0000 G_VPTX0000
.tile TAP_R19C78:TAP_DRIVE
arc: L_HPBX0000 G_VPTX0000
.tile TAP_R20C13:TAP_DRIVE
arc: R_HPBX0000 G_VPTX0000
.tile TAP_R20C31:TAP_DRIVE
arc: L_HPBX0000 G_VPTX0000
.tile TAP_R20C78:TAP_DRIVE
arc: L_HPBX0000 G_VPTX0000
.tile TAP_R21C13:TAP_DRIVE
arc: R_HPBX0000 G_VPTX0000
.tile TAP_R21C31:TAP_DRIVE
arc: L_HPBX0000 G_VPTX0000
.tile TAP_R21C51:TAP_DRIVE
arc: R_HPBX0000 G_VPTX0000
.tile TAP_R21C78:TAP_DRIVE
arc: L_HPBX0000 G_VPTX0000
.tile TAP_R23C51:TAP_DRIVE
arc: R_HPBX0000 G_VPTX0000
.tile TAP_R23C78:TAP_DRIVE
arc: L_HPBX0000 G_VPTX0000
.tile TAP_R24C51:TAP_DRIVE
arc: R_HPBX0000 G_VPTX0000
.tile TAP_R24C78:TAP_DRIVE
arc: L_HPBX0000 G_VPTX0000
.tile TAP_R25C51:TAP_DRIVE
arc: R_HPBX0000 G_VPTX0000
.tile TAP_R26C51:TAP_DRIVE
arc: R_HPBX0000 G_VPTX0000
.tile TAP_R28C51:TAP_DRIVE
arc: R_HPBX0000 G_VPTX0000
.tile TAP_R29C51:TAP_DRIVE
arc: R_HPBX0000 G_VPTX0000
.tile TAP_R40C51:TAP_DRIVE
arc: L_HPBX0000 G_VPTX0000
arc: R_HPBX0000 G_VPTX0000
.tile TAP_R41C51:TAP_DRIVE
arc: L_HPBX0000 G_VPTX0000
arc: R_HPBX0000 G_VPTX0000
.tile TAP_R42C51:TAP_DRIVE
arc: L_HPBX0000 G_VPTX0000
arc: R_HPBX0000 G_VPTX0000
.tile_group MIB_R22C64:MIB_DSP4 MIB_R22C64:MIB2_DSP4 MIB_R22C65:MIB_DSP5 MIB_R22C65:MIB2_DSP5 MIB_R22C66:MIB_DSP6 MIB_R22C66:MIB2_DSP6 MIB_R22C67:MIB_DSP7 MIB_R22C67:MIB2_DSP7 MIB_R22C68:MIB_DSP8 MIB_R22C68:MIB2_DSP8
enum: MULT18_4.REG_INPUTA_CLK NONE
enum: MULT18_4.REG_INPUTA_CE CE0
enum: MULT18_4.REG_INPUTA_RST RST0
enum: MULT18_4.REG_INPUTB_CLK NONE
enum: MULT18_4.REG_INPUTB_CE CE0
enum: MULT18_4.REG_INPUTB_RST RST0
enum: MULT18_4.REG_INPUTC_CLK NONE
enum: MULT18_4.REG_PIPELINE_CLK NONE
enum: MULT18_4.REG_PIPELINE_CE CE0
enum: MULT18_4.REG_PIPELINE_RST RST0
enum: MULT18_4.REG_OUTPUT_CLK NONE
enum: MULT18_4.REG_OUTPUT_RST RST0
enum: MULT18_4.CLK0_DIV ENABLED
enum: MULT18_4.CLK1_DIV ENABLED
enum: MULT18_4.CLK2_DIV ENABLED
enum: MULT18_4.CLK3_DIV ENABLED
enum: MULT18_4.GSR ENABLED
enum: MULT18_4.SOURCEB_MODE B_SHIFT
enum: MULT18_4.RESETMODE SYNC
enum: MULT18_4.MODE MULT18X18D
enum: MULT18_4.CIBOUT_BYP ON
enum: DSP_RIGHT.CIBOUT ON
enum: MULT18_4.CLK0MUX CLK0
enum: MULT18_4.CLK1MUX CLK1
enum: MULT18_4.CLK2MUX CLK2
enum: MULT18_4.CLK3MUX CLK3
enum: MULT18_4.CE0MUX CE0
enum: MULT18_4.CE1MUX CE1
enum: MULT18_4.CE2MUX CE2
enum: MULT18_4.CE3MUX CE3
enum: MULT18_4.RST0MUX RST0
enum: MULT18_4.RST1MUX RST1
enum: MULT18_4.RST2MUX RST2
enum: MULT18_4.RST3MUX RST3
.tile_group MIB_R22C69:MIB_DSP0 MIB_R22C69:MIB2_DSP0 MIB_R22C70:MIB_DSP1 MIB_R22C70:MIB2_DSP1 MIB_R22C71:MIB_DSP2 MIB_R22C71:MIB2_DSP2 MIB_R22C72:MIB_DSP3 MIB_R22C72:MIB2_DSP3 MIB_R22C73:MIB_DSP4 MIB_R22C73:MIB2_DSP4
enum: MULT18_1.REG_INPUTA_CLK NONE
enum: MULT18_1.REG_INPUTA_CE CE0
enum: MULT18_1.REG_INPUTA_RST RST0
enum: MULT18_1.REG_INPUTB_CLK NONE
enum: MULT18_1.REG_INPUTB_CE CE0
enum: MULT18_1.REG_INPUTB_RST RST0
enum: MULT18_1.REG_INPUTC_CLK NONE
enum: MULT18_1.REG_PIPELINE_CLK NONE
enum: MULT18_1.REG_PIPELINE_CE CE0
enum: MULT18_1.REG_PIPELINE_RST RST0
enum: MULT18_1.REG_OUTPUT_CLK NONE
enum: MULT18_1.CLK0_DIV ENABLED
enum: MULT18_1.CLK1_DIV ENABLED
enum: MULT18_1.CLK2_DIV ENABLED
enum: MULT18_1.CLK3_DIV ENABLED
enum: MULT18_1.GSR ENABLED
enum: MULT18_1.SOURCEB_MODE B_SHIFT
enum: MULT18_1.RESETMODE SYNC
enum: MULT18_1.MODE MULT18X18D
enum: MULT18_1.CIBOUT_BYP ON
enum: DSP_LEFT.CIBOUT ON
enum: MULT18_1.CLK0MUX CLK0
enum: MULT18_1.CLK1MUX CLK1
enum: MULT18_1.CLK2MUX CLK2
enum: MULT18_1.CLK3MUX CLK3
enum: MULT18_1.CE0MUX CE0
enum: MULT18_1.CE1MUX CE1
enum: MULT18_1.CE2MUX CE2
enum: MULT18_1.CE3MUX CE3
enum: MULT18_1.RST0MUX RST0
enum: MULT18_1.RST1MUX RST1
enum: MULT18_1.RST2MUX RST2
enum: MULT18_1.RST3MUX RST3
.tile_group MIB_R46C51:MIB_DSP0 MIB_R46C51:MIB2_DSP0 MIB_R46C52:MIB_DSP1 MIB_R46C52:MIB2_DSP1 MIB_R46C53:MIB_DSP2 MIB_R46C53:MIB2_DSP2 MIB_R46C54:MIB_DSP3 MIB_R46C54:MIB2_DSP3 MIB_R46C55:MIB_DSP4 MIB_R46C55:MIB2_DSP4
enum: MULT18_0.REG_INPUTA_CLK NONE
enum: MULT18_0.REG_INPUTA_CE CE0
enum: MULT18_0.REG_INPUTA_RST RST0
enum: MULT18_0.REG_INPUTB_CLK NONE
enum: MULT18_0.REG_INPUTB_CE CE0
enum: MULT18_0.REG_INPUTB_RST RST0
enum: MULT18_0.REG_INPUTC_CLK NONE
enum: MULT18_0.REG_PIPELINE_CLK NONE
enum: MULT18_0.REG_PIPELINE_CE CE0
enum: MULT18_0.REG_PIPELINE_RST RST0
enum: MULT18_0.REG_OUTPUT_CLK NONE
enum: MULT18_0.REG_OUTPUT_RST RST0
enum: MULT18_0.CLK0_DIV ENABLED
enum: MULT18_0.CLK1_DIV ENABLED
enum: MULT18_0.CLK2_DIV ENABLED
enum: MULT18_0.CLK3_DIV ENABLED
enum: MULT18_0.GSR ENABLED
enum: MULT18_0.SOURCEB_MODE B_SHIFT
enum: MULT18_0.RESETMODE SYNC
enum: MULT18_0.MODE MULT18X18D
enum: MULT18_0.CIBOUT_BYP ON
enum: DSP_LEFT.CIBOUT ON
enum: MULT18_0.CLK0MUX CLK0
enum: MULT18_0.CLK1MUX CLK1
enum: MULT18_0.CLK2MUX CLK2
enum: MULT18_0.CLK3MUX CLK3
enum: MULT18_0.CE0MUX CE0
enum: MULT18_0.CE1MUX CE1
enum: MULT18_0.CE2MUX CE2
enum: MULT18_0.CE3MUX CE3
enum: MULT18_0.RST0MUX RST0
enum: MULT18_0.RST1MUX RST1
enum: MULT18_0.RST2MUX RST2
enum: MULT18_0.RST3MUX RST3
.tile_group MIB_R22C17:MIB_DSP4 MIB_R22C17:MIB2_DSP4 MIB_R22C18:MIB_DSP5 MIB_R22C18:MIB2_DSP5 MIB_R22C19:MIB_DSP6 MIB_R22C19:MIB2_DSP6 MIB_R22C20:MIB_DSP7 MIB_R22C20:MIB2_DSP7 MIB_R22C21:MIB_DSP8 MIB_R22C21:MIB2_DSP8
enum: MULT18_5.REG_INPUTA_CLK NONE
enum: MULT18_5.REG_INPUTA_CE CE0
enum: MULT18_5.REG_INPUTA_RST RST0
enum: MULT18_5.REG_INPUTB_CLK NONE
enum: MULT18_5.REG_INPUTB_CE CE0
enum: MULT18_5.REG_INPUTB_RST RST0
enum: MULT18_5.REG_INPUTC_CLK NONE
enum: MULT18_5.REG_PIPELINE_CLK NONE
enum: MULT18_5.REG_PIPELINE_CE CE0
enum: MULT18_5.REG_PIPELINE_RST RST0
enum: MULT18_5.REG_OUTPUT_CLK NONE
enum: MULT18_5.CLK0_DIV ENABLED
enum: MULT18_5.CLK1_DIV ENABLED
enum: MULT18_5.CLK2_DIV ENABLED
enum: MULT18_5.CLK3_DIV ENABLED
enum: MULT18_5.GSR ENABLED
enum: MULT18_5.SOURCEB_MODE B_SHIFT
enum: MULT18_5.RESETMODE SYNC
enum: MULT18_5.MODE MULT18X18D
enum: MULT18_5.CIBOUT_BYP ON
enum: DSP_RIGHT.CIBOUT ON
enum: MULT18_5.CLK0MUX CLK0
enum: MULT18_5.CLK1MUX CLK1
enum: MULT18_5.CLK2MUX CLK2
enum: MULT18_5.CLK3MUX CLK3
enum: MULT18_5.CE0MUX CE0
enum: MULT18_5.CE1MUX CE1
enum: MULT18_5.CE2MUX CE2
enum: MULT18_5.CE3MUX CE3
enum: MULT18_5.RST0MUX RST0
enum: MULT18_5.RST1MUX RST1
enum: MULT18_5.RST2MUX RST2
enum: MULT18_5.RST3MUX RST3
.tile_group MIB_R22C64:MIB_DSP4 MIB_R22C64:MIB2_DSP4 MIB_R22C65:MIB_DSP5 MIB_R22C65:MIB2_DSP5 MIB_R22C66:MIB_DSP6 MIB_R22C66:MIB2_DSP6 MIB_R22C67:MIB_DSP7 MIB_R22C67:MIB2_DSP7 MIB_R22C68:MIB_DSP8 MIB_R22C68:MIB2_DSP8
enum: MULT18_5.REG_INPUTA_CLK NONE
enum: MULT18_5.REG_INPUTA_CE CE0
enum: MULT18_5.REG_INPUTA_RST RST0
enum: MULT18_5.REG_INPUTB_CLK NONE
enum: MULT18_5.REG_INPUTB_CE CE0
enum: MULT18_5.REG_INPUTB_RST RST0
enum: MULT18_5.REG_INPUTC_CLK NONE
enum: MULT18_5.REG_PIPELINE_CLK NONE
enum: MULT18_5.REG_PIPELINE_CE CE0
enum: MULT18_5.REG_PIPELINE_RST RST0
enum: MULT18_5.REG_OUTPUT_CLK NONE
enum: MULT18_5.CLK0_DIV ENABLED
enum: MULT18_5.CLK1_DIV ENABLED
enum: MULT18_5.CLK2_DIV ENABLED
enum: MULT18_5.CLK3_DIV ENABLED
enum: MULT18_5.GSR ENABLED
enum: MULT18_5.SOURCEB_MODE B_SHIFT
enum: MULT18_5.RESETMODE SYNC
enum: MULT18_5.MODE MULT18X18D
enum: MULT18_5.CIBOUT_BYP ON
enum: DSP_RIGHT.CIBOUT ON
enum: MULT18_5.CLK0MUX CLK0
enum: MULT18_5.CLK1MUX CLK1
enum: MULT18_5.CLK2MUX CLK2
enum: MULT18_5.CLK3MUX CLK3
enum: MULT18_5.CE0MUX CE0
enum: MULT18_5.CE1MUX CE1
enum: MULT18_5.CE2MUX CE2
enum: MULT18_5.CE3MUX CE3
enum: MULT18_5.RST0MUX RST0
enum: MULT18_5.RST1MUX RST1
enum: MULT18_5.RST2MUX RST2
enum: MULT18_5.RST3MUX RST3
.tile_group MIB_R22C73:MIB_DSP4 MIB_R22C73:MIB2_DSP4 MIB_R22C74:MIB_DSP5 MIB_R22C74:MIB2_DSP5 MIB_R22C75:MIB_DSP6 MIB_R22C75:MIB2_DSP6 MIB_R22C76:MIB_DSP7 MIB_R22C76:MIB2_DSP7 MIB_R22C77:MIB_DSP8 MIB_R22C77:MIB2_DSP8
enum: MULT18_4.REG_INPUTA_CLK NONE
enum: MULT18_4.REG_INPUTA_CE CE0
enum: MULT18_4.REG_INPUTA_RST RST0
enum: MULT18_4.REG_INPUTB_CLK NONE
enum: MULT18_4.REG_INPUTB_CE CE0
enum: MULT18_4.REG_INPUTB_RST RST0
enum: MULT18_4.REG_INPUTC_CLK NONE
enum: MULT18_4.REG_PIPELINE_CLK NONE
enum: MULT18_4.REG_PIPELINE_CE CE0
enum: MULT18_4.REG_PIPELINE_RST RST0
enum: MULT18_4.REG_OUTPUT_CLK NONE
enum: MULT18_4.REG_OUTPUT_RST RST0
enum: MULT18_4.CLK0_DIV ENABLED
enum: MULT18_4.CLK1_DIV ENABLED
enum: MULT18_4.CLK2_DIV ENABLED
enum: MULT18_4.CLK3_DIV ENABLED
enum: MULT18_4.GSR ENABLED
enum: MULT18_4.SOURCEB_MODE B_SHIFT
enum: MULT18_4.RESETMODE SYNC
enum: MULT18_4.MODE MULT18X18D
enum: MULT18_4.CIBOUT_BYP ON
enum: DSP_RIGHT.CIBOUT ON
enum: MULT18_4.CLK0MUX CLK0
enum: MULT18_4.CLK1MUX CLK1
enum: MULT18_4.CLK2MUX CLK2
enum: MULT18_4.CLK3MUX CLK3
enum: MULT18_4.CE0MUX CE0
enum: MULT18_4.CE1MUX CE1
enum: MULT18_4.CE2MUX CE2
enum: MULT18_4.CE3MUX CE3
enum: MULT18_4.RST0MUX RST0
enum: MULT18_4.RST1MUX RST1
enum: MULT18_4.RST2MUX RST2
enum: MULT18_4.RST3MUX RST3
.tile_group MIB_R22C22:MIB_DSP0 MIB_R22C22:MIB2_DSP0 MIB_R22C23:MIB_DSP1 MIB_R22C23:MIB2_DSP1 MIB_R22C24:MIB_DSP2 MIB_R22C24:MIB2_DSP2 MIB_R22C25:MIB_DSP3 MIB_R22C25:MIB2_DSP3 MIB_R22C26:MIB_DSP4 MIB_R22C26:MIB2_DSP4
enum: MULT18_0.REG_INPUTA_CLK NONE
enum: MULT18_0.REG_INPUTA_CE CE0
enum: MULT18_0.REG_INPUTA_RST RST0
enum: MULT18_0.REG_INPUTB_CLK NONE
enum: MULT18_0.REG_INPUTB_CE CE0
enum: MULT18_0.REG_INPUTB_RST RST0
enum: MULT18_0.REG_INPUTC_CLK NONE
enum: MULT18_0.REG_PIPELINE_CLK NONE
enum: MULT18_0.REG_PIPELINE_CE CE0
enum: MULT18_0.REG_PIPELINE_RST RST0
enum: MULT18_0.REG_OUTPUT_CLK NONE
enum: MULT18_0.REG_OUTPUT_RST RST0
enum: MULT18_0.CLK0_DIV ENABLED
enum: MULT18_0.CLK1_DIV ENABLED
enum: MULT18_0.CLK2_DIV ENABLED
enum: MULT18_0.CLK3_DIV ENABLED
enum: MULT18_0.GSR ENABLED
enum: MULT18_0.SOURCEB_MODE B_SHIFT
enum: MULT18_0.RESETMODE SYNC
enum: MULT18_0.MODE MULT18X18D
enum: MULT18_0.CIBOUT_BYP ON
enum: DSP_LEFT.CIBOUT ON
enum: MULT18_0.CLK0MUX CLK0
enum: MULT18_0.CLK1MUX CLK1
enum: MULT18_0.CLK2MUX CLK2
enum: MULT18_0.CLK3MUX CLK3
enum: MULT18_0.CE0MUX CE0
enum: MULT18_0.CE1MUX CE1
enum: MULT18_0.CE2MUX CE2
enum: MULT18_0.CE3MUX CE3
enum: MULT18_0.RST0MUX RST0
enum: MULT18_0.RST1MUX RST1
enum: MULT18_0.RST2MUX RST2
enum: MULT18_0.RST3MUX RST3
.tile_group MIB_R46C46:MIB_DSP4 MIB_R46C46:MIB2_DSP4 MIB_R46C47:MIB_DSP5 MIB_R46C47:MIB2_DSP5 MIB_R46C48:MIB_DSP6 MIB_R46C48:MIB2_DSP6 MIB_R46C49:MIB_DSP7 MIB_R46C49:MIB2_DSP7 MIB_R46C50:MIB_DSP8 MIB_R46C50:MIB2_DSP8
enum: MULT18_5.REG_INPUTA_CLK NONE
enum: MULT18_5.REG_INPUTA_CE CE0
enum: MULT18_5.REG_INPUTA_RST RST0
enum: MULT18_5.REG_INPUTB_CLK NONE
enum: MULT18_5.REG_INPUTB_CE CE0
enum: MULT18_5.REG_INPUTB_RST RST0
enum: MULT18_5.REG_INPUTC_CLK NONE
enum: MULT18_5.REG_PIPELINE_CLK NONE
enum: MULT18_5.REG_PIPELINE_CE CE0
enum: MULT18_5.REG_PIPELINE_RST RST0
enum: MULT18_5.REG_OUTPUT_CLK NONE
enum: MULT18_5.CLK0_DIV ENABLED
enum: MULT18_5.CLK1_DIV ENABLED
enum: MULT18_5.CLK2_DIV ENABLED
enum: MULT18_5.CLK3_DIV ENABLED
enum: MULT18_5.GSR ENABLED
enum: MULT18_5.SOURCEB_MODE B_SHIFT
enum: MULT18_5.RESETMODE SYNC
enum: MULT18_5.MODE MULT18X18D
enum: MULT18_5.CIBOUT_BYP ON
enum: DSP_RIGHT.CIBOUT ON
enum: MULT18_5.CLK0MUX CLK0
enum: MULT18_5.CLK1MUX CLK1
enum: MULT18_5.CLK2MUX CLK2
enum: MULT18_5.CLK3MUX CLK3
enum: MULT18_5.CE0MUX CE0
enum: MULT18_5.CE1MUX CE1
enum: MULT18_5.CE2MUX CE2
enum: MULT18_5.CE3MUX CE3
enum: MULT18_5.RST0MUX RST0
enum: MULT18_5.RST1MUX RST1
enum: MULT18_5.RST2MUX RST2
enum: MULT18_5.RST3MUX RST3
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