micheleandClaude Sonnet 5
8af16d3a12
Implements M6: dependency_manager.v tracks a table of node
descriptors (node_id/state/required_dependencies/resolved_
dependencies/producer_ids -- §10's exact field list), incrementing a
waiting node's resolved count whenever one of its listed producers
completes, transitioning it to READY once resolved==required, and
dispatching ready nodes to the Neural Director (M5) one at a time via
a backpressure-safe valid/ready interface.
Verified with Verilator on a small hand-built DAG: node0/node1 have no
dependencies (dispatch immediately); node2 depends on BOTH node0 AND
node1 ("dipendenze multiple") and stays WAITING until both complete,
confirmed via an explicit negative check after only one resolves;
node3 depends on node0 ALONE, demonstrating a single producer
("node0") satisfying two different consumers' dependencies
("risultati condivisi... piu' consumer") -- node3 fully, node2
partially. 4/4 tests pass.
Scope for this milestone (decisions.log DEC-0008): dependency
COUNTING/readiness only, no direct producer-to-consumer value
forwarding (§11 frames that as a "quando possibile" optimization, not
a correctness requirement -- deferred until real bandwidth
measurements justify it) and no node-slot reclamation after dispatch
(not exercised by any scenario built so far).
Real synthesis: 0 CHECK problems, 763 LUT4/474 FF/0 DSP/0 CCU2C. Real
place&route (module fits the TRELLIS_IO budget as a bare top-level
this time, no harness needed): Fmax 155.30 MHz, PASS at 80MHz.
Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
25340 lines
552 KiB
Plaintext
25340 lines
552 KiB
Plaintext
.device LFE5U-45F
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.comment Part: LFE5U-45F-8CABGA381
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.tile CIB_R10C3:PVT_COUNT2
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unknown: F2B0
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unknown: F3B0
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unknown: F5B0
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unknown: F11B0
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unknown: F13B0
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.tile CIB_R10C50:CIB_EBR
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arc: JCLK1 V02N0701
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.tile CIB_R11C89:CIB_LR
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arc: W3_H06W0303 JQ5
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.tile CIB_R13C1:CIB_LR
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arc: S3_V06S0303 JF5
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.tile CIB_R14C1:CIB_LR
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arc: E3_H06E0303 JF5
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arc: JA3 V02N0501
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enum: CIB.JB3MUX 0
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.tile CIB_R14C89:CIB_LR
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arc: JA0 H02E0701
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arc: W3_H06W0303 JQ5
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enum: CIB.JB0MUX 0
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.tile CIB_R15C1:CIB_LR
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arc: N1_V02N0501 S3_V06N0303
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.tile CIB_R16C1:CIB_LR
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arc: E3_H06E0303 JQ5
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arc: S3_V06S0303 JF5
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.tile CIB_R16C89:CIB_LR
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arc: W3_H06W0303 JF5
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.tile CIB_R17C1:CIB_LR
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arc: JA3 S1_V02N0501
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enum: CIB.JB3MUX 0
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.tile CIB_R17C89:CIB_LR
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arc: JA0 S1_V02N0701
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arc: W3_H06W0303 JQ5
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enum: CIB.JB0MUX 0
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.tile CIB_R19C1:CIB_LR
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arc: E1_H01E0001 JQ5
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arc: E3_H06E0303 N3_V06S0303
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arc: JA0 H02W0701
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arc: N1_V02N0501 S1_V02N0501
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arc: S3_V06S0303 JQ5
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enum: CIB.JB0MUX 0
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.tile CIB_R19C89:CIB_LR
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arc: JA3 V00B0000
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arc: N1_V02N0701 H06E0203
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arc: V00B0000 S1_V02N0001
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arc: W3_H06W0303 JF5
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enum: CIB.JB3MUX 0
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.tile CIB_R1C11:CIB
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arc: E1_H01E0001 JQ0
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arc: E3_H06E0003 W3_H06E0003
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.tile CIB_R1C12:CIB
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arc: E1_H02E0201 JQ0
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arc: E3_H06E0003 H01E0001
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.tile CIB_R1C13:CIB
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arc: E1_H02E0701 S1_V02N0701
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arc: E3_H06E0003 JQ0
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.tile CIB_R1C14:CIB
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arc: E3_H06E0103 W1_H02E0201
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arc: JA0 H02E0701
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enum: CIB.JB0MUX 0
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.tile CIB_R1C15:CIB
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arc: JA0 H02W0501
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arc: S3_V06S0003 W3_H06E0003
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enum: CIB.JB0MUX 0
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.tile CIB_R1C16:CIB
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arc: JA0 E1_H02W0701
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arc: S3_V06S0003 H06E0003
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arc: W1_H02W0501 S1_V02N0501
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enum: CIB.JB0MUX 0
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.tile CIB_R1C17:CIB
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arc: E3_H06E0003 W3_H06E0003
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arc: S3_V06S0103 H06E0103
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.tile CIB_R1C18:CIB
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arc: E3_H06E0103 W3_H06E0003
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arc: JA0 H02W0501
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arc: S3_V06S0103 H06W0103
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arc: W1_H02W0701 S1_V02N0701
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enum: CIB.JB0MUX 0
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.tile CIB_R1C19:CIB
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arc: W1_H02W0501 S1_V02N0501
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.tile CIB_R1C20:CIB
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arc: E3_H06E0003 JQ0
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.tile CIB_R1C21:CIB
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arc: E3_H06E0003 JQ0
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arc: W3_H06W0103 E3_H06W0003
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.tile CIB_R1C22:CIB
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arc: E1_H02E0701 S1_V02N0701
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arc: H00L0000 S1_V02N0001
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arc: JA0 H00L0000
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enum: CIB.JB0MUX 0
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.tile CIB_R1C23:CIB
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arc: E1_H02E0501 S1_V02N0501
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arc: JA0 H02E0701
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arc: S3_V06S0003 W3_H06E0003
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enum: CIB.JB0MUX 0
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.tile CIB_R1C24:CIB
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arc: E3_H06E0203 W3_H06E0103
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arc: JA0 H02E0501
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arc: S3_V06S0003 H06W0003
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enum: CIB.JB0MUX 0
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.tile CIB_R1C25:CIB
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arc: E3_H06E0003 JQ0
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.tile CIB_R1C26:CIB
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arc: E3_H06E0103 W3_H06E0003
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arc: S3_V06S0103 E3_H06W0103
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.tile CIB_R1C27:CIB
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arc: E1_H02E0701 S1_V02N0701
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arc: E3_H06E0003 JQ0
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arc: E3_H06E0103 W3_H06E0003
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arc: S3_V06S0003 JQ0
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arc: S3_V06S0103 H06W0103
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arc: S3_V06S0203 H06E0203
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arc: W3_H06W0003 JQ0
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.tile CIB_R1C28:CIB
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arc: JA0 H02E0701
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enum: CIB.JB0MUX 0
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.tile CIB_R1C30:CIB
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arc: W3_H06W0103 E3_H06W0103
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.tile CIB_R1C31:CIB
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arc: E1_H02E0501 S1_V02N0501
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arc: E3_H06E0003 JQ0
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arc: E3_H06E0103 W3_H06E0003
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.tile CIB_R1C32:CIB
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arc: E3_H06E0203 W3_H06E0103
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arc: JA0 H02E0501
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arc: W3_H06W0103 E3_H06W0003
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enum: CIB.JB0MUX 0
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.tile CIB_R1C33:CIB
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arc: E3_H06E0003 JQ0
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arc: E3_H06E0103 W3_H06E0003
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arc: E3_H06E0203 W3_H06E0103
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arc: S3_V06S0003 W3_H06E0003
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.tile CIB_R1C34:CIB
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arc: JA0 V02N0501
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arc: S3_V06S0003 H06E0003
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arc: S3_V06S0103 H06W0103
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arc: S3_V06S0203 E3_H06W0203
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enum: CIB.JB0MUX 0
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.tile CIB_R1C35:CIB
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arc: E1_H02E0701 V02N0701
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arc: S3_V06S0103 H06W0103
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arc: S3_V06S0303 H06W0303
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.tile CIB_R1C36:CIB
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arc: JA0 H02E0701
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arc: S3_V06S0103 H06E0103
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arc: S3_V06S0303 E3_H06W0303
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arc: W3_H06W0103 E3_H06W0003
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enum: CIB.JB0MUX 0
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.tile CIB_R1C37:CIB
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arc: E3_H06E0003 JQ0
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arc: S3_V06S0003 E3_H06W0003
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arc: S3_V06S0103 W3_H06E0103
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arc: W3_H06W0103 E3_H06W0103
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.tile CIB_R1C38:CIB
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arc: E3_H06E0003 JQ0
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arc: S3_V06S0203 W3_H06E0203
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arc: W3_H06W0003 E3_H06W0003
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arc: W3_H06W0103 E3_H06W0103
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arc: W3_H06W0303 E3_H06W0203
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.tile CIB_R1C39:CIB
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arc: E1_H01E0001 W3_H06E0003
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arc: E3_H06E0003 JQ0
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arc: E3_H06E0103 W3_H06E0003
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arc: E3_H06E0203 W3_H06E0103
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arc: S3_V06S0003 E3_H06W0003
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arc: S3_V06S0103 E3_H06W0103
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arc: S3_V06S0203 W3_H06E0203
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.tile CIB_R1C40:CIB
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arc: E3_H06E0003 H01E0001
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arc: S3_V06S0103 E3_H06W0103
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arc: S3_V06S0203 H01E0001
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arc: W3_H06W0203 E3_H06W0203
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.tile CIB_R1C41:CIB
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arc: E1_H02E0701 S1_V02N0701
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arc: S3_V06S0003 H06E0003
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.tile CIB_R1C42:CIB
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arc: JA0 H02E0701
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arc: S3_V06S0003 H06E0003
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arc: S3_V06S0103 H06E0103
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arc: S3_V06S0203 H06E0203
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arc: W3_H06W0003 E1_H02W0301
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arc: W3_H06W0303 E3_H06W0203
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enum: CIB.JB0MUX 0
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.tile CIB_R1C43:CIB
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arc: E3_H06E0003 W3_H06E0003
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arc: S3_V06S0003 H06E0003
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arc: S3_V06S0103 H06W0103
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arc: W3_H06W0003 JQ0
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arc: W3_H06W0103 E3_H06W0103
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.tile CIB_R1C44:CIB
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arc: E3_H06E0103 W3_H06E0003
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arc: S3_V06S0003 W3_H06E0003
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arc: W1_H02W0301 E3_H06W0003
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arc: W3_H06W0003 JQ0
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arc: W3_H06W0103 E1_H01W0100
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arc: W3_H06W0203 E3_H06W0203
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.tile CIB_R1C45:CIB
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arc: E3_H06E0103 W3_H06E0003
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arc: E3_H06E0203 W3_H06E0203
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arc: H01W0100 JQ0
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arc: S1_V02S0101 E3_H06W0103
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arc: S3_V06S0003 E3_H06W0003
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arc: S3_V06S0103 W3_H06E0103
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arc: S3_V06S0203 W3_H06E0203
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arc: W3_H06W0003 E3_H06W0003
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arc: W3_H06W0103 E3_H06W0103
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.tile CIB_R1C46:CIB
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arc: E1_H02E0501 S3_V06N0303
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arc: S1_V02S0001 E3_H06W0003
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arc: S3_V06S0003 H06W0003
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arc: W3_H06W0103 E3_H06W0003
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arc: W3_H06W0203 E3_H06W0103
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.tile CIB_R1C47:CIB
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arc: JA0 H02E0501
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arc: S3_V06S0103 H06E0103
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enum: CIB.JB0MUX 0
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.tile CIB_R1C48:CIB
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arc: JA0 S1_V02N0501
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arc: S1_V02S0201 H06W0103
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arc: S3_V06S0003 H06W0003
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arc: S3_V06S0103 H06E0103
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arc: W3_H06W0203 E3_H06W0103
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enum: CIB.JB0MUX 0
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.tile CIB_R1C49:CIB
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arc: E3_H06E0003 W3_H06E0003
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arc: S1_V02S0301 H06W0003
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arc: S3_V06S0003 JQ0
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arc: W3_H06W0003 JQ0
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arc: W3_H06W0103 E3_H06W0003
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.tile CIB_R1C4:CIB
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arc: JA0 E1_H02W0501
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enum: CIB.JB0MUX 0
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.tile CIB_R1C50:CIB
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arc: S3_V06S0003 E1_H01W0000
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arc: S3_V06S0103 W3_H06E0103
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arc: W3_H06W0003 JQ0
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arc: W3_H06W0203 E3_H06W0103
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.tile CIB_R1C51:CIB
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arc: E3_H06E0203 W3_H06E0203
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arc: H01W0000 JQ0
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arc: S1_V02S0001 JQ0
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arc: S3_V06S0003 E3_H06W0003
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arc: S3_V06S0103 W3_H06E0103
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arc: S3_V06S0203 W3_H06E0203
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arc: W3_H06W0003 JQ0
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arc: W3_H06W0103 E3_H06W0003
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.tile CIB_R1C52:CIB
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arc: S1_V02S0201 JQ0
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arc: S3_V06S0003 E3_H06W0003
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arc: W3_H06W0003 E3_H06W0003
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arc: W3_H06W0103 E3_H06W0103
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.tile CIB_R1C53:CIB
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arc: E1_H02E0501 S1_V02N0501
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arc: S3_V06S0003 H06W0003
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.tile CIB_R1C54:CIB
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arc: JA0 H02E0501
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arc: S3_V06S0003 E3_H06W0003
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arc: S3_V06S0203 H06E0203
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arc: W3_H06W0103 E3_H06W0103
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enum: CIB.JB0MUX 0
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.tile CIB_R1C55:CIB
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arc: E3_H06E0003 W3_H06E0003
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arc: W3_H06W0003 E3_H06W0003
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.tile CIB_R1C56:CIB
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arc: JA0 S1_V02N0701
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arc: W3_H06W0003 E1_H02W0001
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arc: W3_H06W0103 E3_H06W0103
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enum: CIB.JB0MUX 0
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.tile CIB_R1C57:CIB
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arc: E3_H06E0303 W3_H06E0203
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arc: W3_H06W0003 JQ0
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.tile CIB_R1C58:CIB
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arc: E1_H02E0701 S1_V02N0701
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arc: W1_H02W0001 E1_H02W0001
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arc: W3_H06W0003 JQ0
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arc: W3_H06W0103 E3_H06W0003
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.tile CIB_R1C59:CIB
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arc: JA0 H02E0701
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enum: CIB.JB0MUX 0
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.tile CIB_R1C5:CIB
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arc: E1_H02E0501 S1_V02N0501
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arc: E3_H06E0003 JQ0
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.tile CIB_R1C60:CIB
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arc: S3_V06S0303 H06E0303
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arc: W1_H02W0001 E3_H06W0003
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arc: W3_H06W0003 JQ0
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arc: W3_H06W0103 E3_H06W0103
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.tile CIB_R1C61:CIB
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arc: S3_V06S0003 W3_H06E0003
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arc: W3_H06W0003 E3_H06W0003
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.tile CIB_R1C62:CIB
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arc: S3_V06S0103 E3_H06W0103
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arc: W3_H06W0103 E3_H06W0003
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.tile CIB_R1C63:CIB
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arc: S3_V06S0303 W3_H06E0303
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.tile CIB_R1C64:CIB
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arc: W3_H06W0003 E3_H06W0003
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.tile CIB_R1C65:CIB
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arc: JA0 S1_V02N0701
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enum: CIB.JB0MUX 0
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.tile CIB_R1C66:CIB
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arc: W3_H06W0003 JQ0
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arc: W3_H06W0103 E3_H06W0103
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.tile CIB_R1C67:CIB
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arc: E1_H02E0701 S1_V02N0701
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arc: W3_H06W0003 JQ0
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.tile CIB_R1C68:CIB
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arc: E1_H02E0501 S1_V02N0501
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arc: JA0 H02E0701
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arc: W3_H06W0003 E3_H06W0003
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arc: W3_H06W0103 E3_H06W0103
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enum: CIB.JB0MUX 0
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.tile CIB_R1C69:CIB
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arc: E1_H02E0701 S1_V02N0701
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arc: JA0 H02E0501
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enum: CIB.JB0MUX 0
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.tile CIB_R1C6:CIB
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arc: JA0 H02E0501
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arc: W1_H02W0501 S1_V02N0501
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enum: CIB.JB0MUX 0
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.tile CIB_R1C70:CIB
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arc: JA0 H02E0701
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arc: W3_H06W0003 E3_H06W0003
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enum: CIB.JB0MUX 0
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.tile CIB_R1C72:CIB
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arc: W3_H06W0103 E3_H06W0003
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.tile CIB_R1C73:CIB
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arc: E1_H02E0701 S1_V02N0701
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.tile CIB_R1C74:CIB
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arc: W3_H06W0003 JQ0
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arc: W3_H06W0103 E3_H06W0003
|
|
|
|
.tile CIB_R1C75:CIB
|
|
arc: E1_H02E0501 S1_V02N0501
|
|
arc: JA0 W1_H02E0701
|
|
enum: CIB.JB0MUX 0
|
|
|
|
.tile CIB_R1C76:CIB
|
|
arc: W3_H06W0003 JQ0
|
|
|
|
.tile CIB_R1C77:CIB
|
|
arc: E1_H02E0501 V02N0501
|
|
arc: JA0 W1_H02E0501
|
|
enum: CIB.JB0MUX 0
|
|
|
|
.tile CIB_R1C78:CIB
|
|
arc: W3_H06W0003 JQ0
|
|
|
|
.tile CIB_R1C79:CIB
|
|
arc: JA0 W1_H02E0501
|
|
enum: CIB.JB0MUX 0
|
|
|
|
.tile CIB_R1C7:CIB
|
|
arc: JA0 H02W0701
|
|
enum: CIB.JB0MUX 0
|
|
|
|
.tile CIB_R1C80:CIB
|
|
arc: E1_H02E0501 S1_V02N0501
|
|
arc: W3_H06W0003 JQ0
|
|
|
|
.tile CIB_R1C81:CIB
|
|
arc: JA0 H02E0501
|
|
enum: CIB.JB0MUX 0
|
|
|
|
.tile CIB_R1C83:CIB
|
|
arc: E1_H02E0701 S1_V02N0701
|
|
arc: JA0 V02N0701
|
|
enum: CIB.JB0MUX 0
|
|
|
|
.tile CIB_R1C84:CIB
|
|
arc: JA0 H02E0701
|
|
enum: CIB.JB0MUX 0
|
|
|
|
.tile CIB_R1C8:CIB
|
|
arc: W1_H02W0701 S1_V02N0701
|
|
|
|
.tile CIB_R1C9:CIB
|
|
arc: E3_H06E0003 JQ0
|
|
|
|
.tile CIB_R20C1:CIB_LR
|
|
arc: JA0 E1_H02W0501
|
|
arc: JA3 E1_H02W0701
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB0MUX 0
|
|
|
|
.tile CIB_R20C89:CIB_LR
|
|
arc: JA0 V02N0501
|
|
arc: W3_H06W0303 JQ5
|
|
enum: CIB.JB0MUX 0
|
|
|
|
.tile CIB_R21C1:CIB_LR
|
|
arc: N1_V02N0501 H06W0303
|
|
arc: N3_V06N0303 S3_V06N0303
|
|
arc: S1_V02S0501 E3_H06W0303
|
|
|
|
.tile CIB_R21C89:CIB_LR
|
|
arc: N1_V02N0001 S3_V06N0003
|
|
arc: N1_V02N0501 H06E0303
|
|
arc: S1_V02S0501 S3_V06N0303
|
|
arc: S1_V02S0701 H06E0203
|
|
|
|
.tile CIB_R22C13:CIB_DSP
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
|
|
.tile CIB_R22C17:CIB_DSP
|
|
arc: S3_V06S0203 N3_V06S0203
|
|
|
|
.tile CIB_R22C19:CIB_DSP
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
|
|
.tile CIB_R22C1:CIB_LR_S
|
|
arc: E3_H06E0303 N3_V06S0303
|
|
arc: JA3 V02S0501
|
|
arc: S3_V06S0303 JF5
|
|
enum: CIB.JB3MUX 0
|
|
|
|
.tile CIB_R22C25:CIB_DSP
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
|
|
.tile CIB_R22C31:CIB_DSP
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
|
|
.tile CIB_R22C37:CIB_DSP
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
arc: S3_V06S0303 N3_V06S0203
|
|
|
|
.tile CIB_R22C39:CIB_DSP
|
|
arc: N1_V02N0601 E1_H02W0601
|
|
arc: N1_V02N0701 E1_H02W0701
|
|
arc: S1_V02S0001 S3_V06N0003
|
|
arc: S1_V02S0101 E1_H02W0101
|
|
arc: S1_V02S0201 H02W0201
|
|
arc: S1_V02S0601 S3_V06N0303
|
|
arc: V01S0100 S3_V06N0303
|
|
|
|
.tile CIB_R22C40:CIB_DSP
|
|
arc: E1_H02E0501 S1_V02N0501
|
|
arc: N1_V02N0301 S1_V02N0201
|
|
arc: N1_V02N0501 S1_V02N0501
|
|
arc: S1_V02S0501 E1_H02W0501
|
|
arc: W1_H02W0201 V06S0103
|
|
|
|
.tile CIB_R22C41:CIB_DSP
|
|
arc: N1_V02N0001 E3_H06W0003
|
|
arc: N1_V02N0101 E1_H02W0101
|
|
arc: N1_V02N0201 S3_V06N0103
|
|
arc: N1_V02N0401 N1_V01S0000
|
|
arc: N1_V02N0501 H02E0501
|
|
arc: S1_V02S0101 S3_V06N0103
|
|
arc: S1_V02S0301 N1_V01S0100
|
|
arc: S1_V02S0501 S3_V06N0303
|
|
arc: S3_V06S0003 E3_H06W0003
|
|
arc: V01S0000 S3_V06N0103
|
|
arc: V01S0100 S3_V06N0303
|
|
arc: W1_H02W0101 E1_H02W0101
|
|
arc: W1_H02W0601 V06S0303
|
|
arc: W1_H02W0701 S3_V06N0203
|
|
|
|
.tile CIB_R22C42:CIB_DSP
|
|
arc: E1_H02E0701 V06S0203
|
|
arc: N1_V02N0001 H02W0001
|
|
arc: N1_V02N0201 S1_V02N0701
|
|
arc: N1_V02N0701 S1_V02N0701
|
|
arc: S1_V02S0601 N1_V02S0601
|
|
arc: V01S0100 S3_V06N0303
|
|
arc: W1_H02W0501 S1_V02N0501
|
|
|
|
.tile CIB_R22C43:CIB_DSP
|
|
arc: E1_H02E0101 S3_V06N0103
|
|
arc: E1_H02E0201 V01N0001
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
arc: N1_V02N0001 S1_V02N0501
|
|
arc: N1_V02N0201 S1_V02N0701
|
|
arc: N1_V02N0401 S1_V02N0101
|
|
arc: N1_V02N0701 V01N0101
|
|
arc: S1_V02S0301 E1_H02W0301
|
|
arc: S1_V02S0501 N1_V02S0501
|
|
arc: W1_H02W0001 V06S0003
|
|
arc: W1_H02W0101 S3_V06N0103
|
|
|
|
.tile CIB_R22C44:CIB_DSP
|
|
arc: N1_V02N0001 H06W0003
|
|
arc: N1_V02N0201 H02E0201
|
|
arc: N1_V02N0301 S1_V02N0201
|
|
arc: N1_V02N0401 S1_V02N0401
|
|
arc: N1_V02N0601 S1_V02N0601
|
|
arc: S1_V02S0001 H06W0003
|
|
arc: S1_V02S0201 H06W0103
|
|
arc: S1_V02S0701 W1_H02E0701
|
|
arc: S3_V06S0003 H06W0003
|
|
arc: S3_V06S0103 H06W0103
|
|
|
|
.tile CIB_R22C45:CIB_DSP
|
|
arc: E1_H02E0501 V06S0303
|
|
arc: N1_V02N0101 W1_H02E0101
|
|
arc: N1_V02N0201 S1_V02N0701
|
|
arc: N1_V02N0301 S1_V02N0301
|
|
arc: N1_V02N0401 H02W0401
|
|
arc: N1_V02N0501 S1_V02N0401
|
|
arc: N1_V02N0601 N1_V01S0000
|
|
arc: N1_V02N0701 S1_V02N0701
|
|
arc: S1_V02S0101 N1_V02S0101
|
|
arc: W1_H02W0301 V06S0003
|
|
|
|
.tile CIB_R22C46:CIB_DSP
|
|
arc: N1_V02N0001 S3_V06N0003
|
|
arc: N1_V02N0401 S1_V02N0401
|
|
arc: S1_V02S0201 N1_V02S0201
|
|
arc: S1_V02S0301 N1_V02S0201
|
|
arc: S1_V02S0401 H02W0401
|
|
arc: V01S0100 S3_V06N0303
|
|
arc: W1_H02W0401 S3_V06N0203
|
|
|
|
.tile CIB_R22C47:CIB_DSP
|
|
arc: E1_H02E0001 E3_H06W0003
|
|
arc: E1_H02E0301 S3_V06N0003
|
|
arc: N1_V02N0001 H02W0001
|
|
arc: N1_V02N0301 S3_V06N0003
|
|
arc: N1_V02N0601 H02W0601
|
|
arc: S1_V02S0301 E1_H02W0301
|
|
arc: S1_V02S0501 W1_H02E0501
|
|
arc: S1_V02S0601 H02W0601
|
|
arc: S1_V02S0701 E3_H06W0203
|
|
arc: V01S0000 S3_V06N0103
|
|
arc: V01S0100 S3_V06N0303
|
|
arc: W1_H02W0401 E3_H06W0203
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
|
|
.tile CIB_R22C48:CIB_DSP
|
|
arc: E1_H02E0001 V06S0003
|
|
arc: N1_V02N0001 S1_V02N0001
|
|
arc: N1_V02N0201 S1_V02N0201
|
|
arc: N1_V02N0301 H02E0301
|
|
arc: N1_V02N0501 S3_V06N0303
|
|
arc: N1_V02N0601 V01N0001
|
|
arc: S1_V02S0001 H02E0001
|
|
arc: V01S0100 S3_V06N0303
|
|
arc: W1_H02W0001 V06S0003
|
|
arc: W1_H02W0601 V06S0303
|
|
|
|
.tile CIB_R22C49:CIB_DSP
|
|
arc: E1_H02E0101 S3_V06N0103
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
arc: N1_V02N0201 S1_V02N0701
|
|
arc: N1_V02N0501 S1_V02N0501
|
|
arc: S1_V02S0001 H02E0001
|
|
arc: S1_V02S0301 W1_H02E0301
|
|
arc: W1_H02W0301 V06S0003
|
|
|
|
.tile CIB_R22C50:CIB_DSP
|
|
arc: N1_V02N0101 H02E0101
|
|
arc: N1_V02N0201 H06W0103
|
|
arc: N1_V02N0701 S1_V02N0601
|
|
arc: S3_V06S0003 H06W0003
|
|
|
|
.tile CIB_R22C51:CIB_DSP
|
|
arc: N1_V02N0001 V01N0001
|
|
arc: N1_V02N0101 S3_V06N0103
|
|
arc: S1_V02S0401 N1_V02S0101
|
|
|
|
.tile CIB_R22C53:CIB_DSP
|
|
arc: S1_V02S0001 E3_H06W0003
|
|
arc: S3_V06S0103 E3_H06W0103
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
|
|
.tile CIB_R22C55:CIB_DSP
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
|
|
.tile CIB_R22C59:CIB_DSP
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
|
|
.tile CIB_R22C61:CIB_DSP
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
|
|
.tile CIB_R22C65:CIB_DSP
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
|
|
.tile CIB_R22C67:CIB_DSP
|
|
arc: S3_V06S0103 W3_H06E0103
|
|
|
|
.tile CIB_R22C71:CIB_DSP
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
|
|
.tile CIB_R22C77:CIB_DSP
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
|
|
.tile CIB_R22C7:CIB_DSP
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
|
|
.tile CIB_R22C83:CIB_DSP
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
|
|
.tile CIB_R22C89:CIB_LR_S
|
|
arc: JA0 V02S0701
|
|
arc: W3_H06W0303 JQ5
|
|
enum: CIB.JB0MUX 0
|
|
|
|
.tile CIB_R23C1:CIB_LR
|
|
arc: E1_H01E0001 E3_H06W0003
|
|
arc: JA0 E1_H02W0501
|
|
arc: JA3 E1_H01E0001
|
|
enum: CIB.JB0MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
|
|
.tile CIB_R23C89:CIB_LR
|
|
arc: JA3 N1_V02S0501
|
|
arc: W3_H06W0303 JF5
|
|
enum: CIB.JB3MUX 0
|
|
|
|
.tile CIB_R24C1:CIB_LR
|
|
arc: S1_V02S0701 E3_H06W0203
|
|
|
|
.tile CIB_R25C1:CIB_LR
|
|
arc: E1_H01E0101 JQ5
|
|
arc: E3_H06E0103 S3_V06N0103
|
|
arc: E3_H06E0303 N3_V06S0303
|
|
arc: JA0 V02S0701
|
|
enum: CIB.JB0MUX 0
|
|
|
|
.tile CIB_R25C89:CIB_LR
|
|
arc: JA0 V02N0701
|
|
arc: W3_H06W0303 JQ5
|
|
enum: CIB.JB0MUX 0
|
|
|
|
.tile CIB_R26C1:CIB_LR
|
|
arc: E1_H01E0101 JQ5
|
|
arc: E3_H06E0303 S3_V06N0303
|
|
arc: JA0 E1_H02W0701
|
|
arc: S3_V06S0303 H06W0303
|
|
enum: CIB.JB0MUX 0
|
|
|
|
.tile CIB_R26C89:CIB_LR
|
|
arc: JA0 W1_H02E0701
|
|
arc: N1_V02N0701 W3_H06E0203
|
|
arc: S1_V02S0501 W3_H06E0303
|
|
arc: W3_H06W0303 JQ5
|
|
enum: CIB.JB0MUX 0
|
|
|
|
.tile CIB_R27C1:CIB_LR
|
|
arc: E1_H02E0501 S1_V02N0501
|
|
arc: E3_H06E0003 V01N0001
|
|
arc: E3_H06E0203 S3_V06N0203
|
|
arc: N3_V06N0303 E3_H06W0303
|
|
arc: S1_V02S0501 H06W0303
|
|
arc: S1_V02S0701 H06W0203
|
|
arc: S3_V06S0103 H06W0103
|
|
arc: S3_V06S0203 E3_H06W0203
|
|
|
|
.tile CIB_R27C89:CIB_LR
|
|
arc: N3_V06N0003 H06E0003
|
|
arc: N3_V06N0303 W3_H06E0303
|
|
arc: S1_V02S0701 H06E0203
|
|
arc: S3_V06S0103 W3_H06E0103
|
|
|
|
.tile CIB_R28C1:CIB_LR
|
|
arc: E3_H06E0303 S3_V06N0303
|
|
arc: JA3 V02S0701
|
|
arc: N1_V01N0001 JF5
|
|
arc: S3_V06S0003 E3_H06W0003
|
|
arc: S3_V06S0203 E3_H06W0203
|
|
arc: S3_V06S0303 H06W0303
|
|
arc: V01S0100 N3_V06S0303
|
|
enum: CIB.JB3MUX 0
|
|
|
|
.tile CIB_R28C89:CIB_LR
|
|
arc: JA0 N1_V02S0501
|
|
arc: S1_V02S0401 W3_H06E0203
|
|
arc: S1_V02S0501 W1_H02E0501
|
|
arc: S3_V06S0103 W3_H06E0103
|
|
arc: S3_V06S0203 H06E0203
|
|
arc: S3_V06S0303 H06E0303
|
|
arc: V01S0100 S3_V06N0303
|
|
arc: W3_H06W0303 JQ5
|
|
enum: CIB.JB0MUX 0
|
|
|
|
.tile CIB_R29C1:CIB_LR
|
|
arc: E3_H06E0003 S3_V06N0003
|
|
arc: E3_H06E0103 N1_V01S0100
|
|
arc: E3_H06E0303 S3_V06N0303
|
|
arc: JA0 E1_H02W0501
|
|
arc: N1_V02N0501 JQ5
|
|
arc: S1_V02S0501 N1_V02S0501
|
|
enum: CIB.JB0MUX 0
|
|
|
|
.tile CIB_R29C89:CIB_LR
|
|
arc: H01W0100 JQ5
|
|
arc: JA0 N1_V02S0701
|
|
arc: S1_V02S0501 W1_H02E0501
|
|
arc: V01S0100 S3_V06N0303
|
|
arc: W3_H06W0303 N1_V01S0100
|
|
enum: CIB.JB0MUX 0
|
|
|
|
.tile CIB_R30C1:CIB_LR
|
|
arc: E3_H06E0103 S3_V06N0103
|
|
arc: E3_H06E0303 S3_V06N0303
|
|
|
|
.tile CIB_R30C89:CIB_LR
|
|
arc: S1_V02S0301 W3_H06E0003
|
|
arc: S1_V02S0501 N1_V02S0501
|
|
arc: S3_V06S0203 N1_V02S0401
|
|
arc: W3_H06W0103 N1_V01S0100
|
|
|
|
.tile CIB_R31C1:CIB_LR
|
|
arc: E3_H06E0003 S3_V06N0003
|
|
arc: E3_H06E0103 V01N0101
|
|
arc: E3_H06E0303 S3_V06N0303
|
|
arc: JA0 H02W0701
|
|
arc: JA3 N1_V02S0501
|
|
arc: N3_V06N0103 S3_V06N0003
|
|
enum: CIB.JB0MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
|
|
.tile CIB_R31C89:CIB_LR
|
|
arc: H01W0100 JQ5
|
|
arc: JA0 N1_V02S0501
|
|
arc: W3_H06W0303 S3_V06N0303
|
|
enum: CIB.JB0MUX 0
|
|
|
|
.tile CIB_R32C1:CIB_LR
|
|
arc: E3_H06E0103 S3_V06N0103
|
|
arc: E3_H06E0303 S3_V06N0303
|
|
arc: JA3 E1_H02W0501
|
|
arc: N1_V01N0101 JF5
|
|
arc: N3_V06N0303 S3_V06N0303
|
|
arc: S3_V06S0003 N3_V06S0303
|
|
enum: CIB.JB3MUX 0
|
|
|
|
.tile CIB_R32C89:CIB_LR
|
|
arc: H00L0100 N1_V02S0301
|
|
arc: JA0 H00L0100
|
|
arc: JA3 N1_V02S0501
|
|
arc: W3_H06W0303 S3_V06N0303
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB0MUX 0
|
|
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.tile CIB_R33C1:CIB_LR
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arc: N3_V06N0203 S1_V02N0701
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arc: S1_V02S0701 E3_H06W0203
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arc: S3_V06S0203 N3_V06S0103
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arc: S3_V06S0303 N3_V06S0203
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.tile CIB_R33C89:CIB_LR
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arc: S1_V02S0201 N3_V06S0103
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arc: S1_V02S0501 W3_H06E0303
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arc: S3_V06S0203 H06E0203
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.tile CIB_R34C16:CIB_EBR
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arc: N3_V06N0203 S3_V06N0103
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.tile CIB_R34C17:CIB_EBR
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arc: N3_V06N0003 S3_V06N0303
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.tile CIB_R34C1:CIB_LR_S
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arc: E3_H06E0303 JQ5
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arc: JA0 V02S0701
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arc: N3_V06N0303 S3_V06N0303
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arc: S3_V06S0003 N3_V06S0303
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arc: S3_V06S0103 N3_V06S0003
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arc: S3_V06S0303 N3_V06S0203
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enum: CIB.JB0MUX 0
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.tile CIB_R34C20:CIB_EBR
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arc: S3_V06S0103 N3_V06S0003
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.tile CIB_R34C22:CIB_EBR
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arc: N3_V06N0203 S3_V06N0203
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.tile CIB_R34C23:CIB_EBR
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arc: N3_V06N0003 S3_V06N0303
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.tile CIB_R34C24:CIB_EBR
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arc: N3_V06N0203 S3_V06N0103
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.tile CIB_R34C25:CIB_EBR
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arc: N3_V06N0303 S3_V06N0203
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.tile CIB_R34C26:CIB_EBR
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arc: N3_V06N0003 S3_V06N0303
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.tile CIB_R34C2:CIB_EBR
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arc: S3_V06S0103 N3_V06S0103
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.tile CIB_R34C30:CIB_EBR
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arc: N3_V06N0103 S3_V06N0103
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.tile CIB_R34C31:CIB_EBR
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arc: N3_V06N0203 S3_V06N0103
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.tile CIB_R34C32:CIB_EBR
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arc: N3_V06N0003 S3_V06N0003
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.tile CIB_R34C34:CIB_EBR
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arc: N3_V06N0003 S3_V06N0003
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arc: N3_V06N0203 S3_V06N0103
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.tile CIB_R34C35:CIB_EBR
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arc: N3_V06N0003 S3_V06N0003
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arc: N3_V06N0303 S3_V06N0203
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.tile CIB_R34C36:CIB_EBR
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arc: N3_V06N0303 S3_V06N0303
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.tile CIB_R34C37:CIB_EBR
|
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arc: N3_V06N0003 S3_V06N0003
|
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arc: N3_V06N0203 S3_V06N0103
|
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.tile CIB_R34C38:CIB_EBR
|
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arc: N3_V06N0003 S3_V06N0303
|
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arc: N3_V06N0103 S1_V02N0101
|
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.tile CIB_R34C39:CIB_EBR
|
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arc: N1_V01N0101 S3_V06N0203
|
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arc: N1_V02N0401 S3_V06N0203
|
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arc: N3_V06N0203 S3_V06N0203
|
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arc: N3_V06N0303 S3_V06N0203
|
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|
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.tile CIB_R34C40:CIB_EBR
|
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arc: N1_V02N0001 S1_V02N0501
|
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arc: N1_V02N0201 S3_V06N0103
|
|
arc: N1_V02N0301 S3_V06N0003
|
|
arc: N1_V02N0601 S1_V02N0601
|
|
arc: N3_V06N0003 S3_V06N0003
|
|
arc: N3_V06N0103 S3_V06N0003
|
|
arc: N3_V06N0203 S3_V06N0103
|
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arc: N3_V06N0303 S3_V06N0303
|
|
|
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.tile CIB_R34C41:CIB_EBR
|
|
arc: N1_V02N0101 S3_V06N0103
|
|
arc: N1_V02N0401 S3_V06N0203
|
|
arc: N1_V02N0701 S3_V06N0203
|
|
arc: N3_V06N0103 S3_V06N0103
|
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arc: N3_V06N0203 S3_V06N0203
|
|
arc: V01S0000 S3_V06N0103
|
|
|
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.tile CIB_R34C42:CIB_EBR
|
|
arc: E1_H02E0701 S3_V06N0203
|
|
arc: N1_V02N0101 E1_H02W0101
|
|
arc: N1_V02N0401 S3_V06N0203
|
|
arc: N3_V06N0303 S3_V06N0203
|
|
|
|
.tile CIB_R34C43:CIB_EBR
|
|
arc: N1_V02N0101 H02W0101
|
|
arc: N1_V02N0701 H02E0701
|
|
arc: N3_V06N0003 S3_V06N0003
|
|
|
|
.tile CIB_R34C44:CIB_EBR
|
|
arc: N3_V06N0203 S3_V06N0103
|
|
arc: W1_H02W0101 S3_V06N0103
|
|
|
|
.tile CIB_R34C45:CIB_EBR
|
|
arc: N1_V02N0101 S3_V06N0103
|
|
arc: N1_V02N0201 S3_V06N0103
|
|
arc: N1_V02N0501 E1_H02W0501
|
|
|
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.tile CIB_R34C46:CIB_EBR
|
|
arc: N3_V06N0103 S3_V06N0103
|
|
arc: N3_V06N0203 S3_V06N0103
|
|
|
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.tile CIB_R34C47:CIB_EBR
|
|
arc: N1_V02N0401 S3_V06N0203
|
|
arc: N1_V02N0501 S3_V06N0303
|
|
arc: N1_V02N0701 S3_V06N0203
|
|
arc: N3_V06N0003 S3_V06N0303
|
|
arc: N3_V06N0303 S3_V06N0303
|
|
arc: W1_H02W0501 S3_V06N0303
|
|
|
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.tile CIB_R34C48:CIB_EBR
|
|
arc: E1_H02E0101 S3_V06N0103
|
|
arc: E1_H02E0701 S3_V06N0203
|
|
arc: N1_V02N0101 S3_V06N0103
|
|
arc: N1_V02N0701 S3_V06N0203
|
|
arc: N3_V06N0103 S3_V06N0103
|
|
arc: N3_V06N0203 S3_V06N0203
|
|
|
|
.tile CIB_R34C49:CIB_EBR
|
|
arc: N1_V02N0101 S3_V06N0103
|
|
arc: N1_V02N0201 S3_V06N0103
|
|
arc: N1_V02N0701 H02E0701
|
|
arc: N3_V06N0003 S3_V06N0303
|
|
|
|
.tile CIB_R34C50:CIB_EBR
|
|
arc: E1_H02E0201 S3_V06N0103
|
|
arc: N1_V02N0101 W1_H02E0101
|
|
arc: N1_V02N0201 N3_V06S0103
|
|
arc: N1_V02N0301 H06W0003
|
|
arc: N1_V02N0401 S1_V02N0401
|
|
arc: N1_V02N0701 H02W0701
|
|
arc: N3_V06N0103 S3_V06N0103
|
|
|
|
.tile CIB_R34C51:CIB_EBR
|
|
arc: N1_V02N0101 S3_V06N0103
|
|
arc: N1_V02N0201 H02E0201
|
|
arc: N3_V06N0103 S3_V06N0103
|
|
arc: N3_V06N0203 S3_V06N0103
|
|
arc: N3_V06N0303 S3_V06N0203
|
|
arc: W1_H02W0701 S3_V06N0203
|
|
|
|
.tile CIB_R34C52:CIB_EBR
|
|
arc: N3_V06N0203 S3_V06N0103
|
|
|
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.tile CIB_R34C53:CIB_EBR
|
|
arc: N1_V02N0501 S3_V06N0303
|
|
arc: N3_V06N0103 S3_V06N0003
|
|
arc: N3_V06N0203 S3_V06N0203
|
|
arc: N3_V06N0303 S3_V06N0303
|
|
arc: W3_H06W0003 S3_V06N0003
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|
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.tile CIB_R34C55:CIB_EBR
|
|
arc: N3_V06N0003 S3_V06N0003
|
|
|
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.tile CIB_R34C58:CIB_EBR
|
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arc: N3_V06N0103 S3_V06N0003
|
|
arc: N3_V06N0203 S3_V06N0103
|
|
|
|
.tile CIB_R34C61:CIB_EBR
|
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arc: N3_V06N0003 S3_V06N0003
|
|
|
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.tile CIB_R34C64:CIB_EBR
|
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arc: N3_V06N0203 S3_V06N0203
|
|
|
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.tile CIB_R34C65:CIB_EBR
|
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arc: N3_V06N0103 S3_V06N0003
|
|
|
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.tile CIB_R34C7:CIB_EBR
|
|
arc: N3_V06N0303 W3_H06E0303
|
|
|
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.tile CIB_R34C87:CIB_EBR
|
|
arc: S3_V06S0003 N3_V06S0303
|
|
arc: S3_V06S0303 N3_V06S0203
|
|
|
|
.tile CIB_R34C88:CIB_EBR
|
|
arc: S1_V02S0701 N3_V06S0203
|
|
arc: S3_V06S0003 N3_V06S0303
|
|
arc: S3_V06S0103 N3_V06S0003
|
|
arc: S3_V06S0303 N1_V01S0100
|
|
|
|
.tile CIB_R34C89:CIB_LR_S
|
|
arc: JA3 V02S0501
|
|
arc: N3_V06N0303 JF5
|
|
arc: S3_V06S0003 N3_V06S0303
|
|
arc: S3_V06S0203 N3_V06S0103
|
|
arc: S3_V06S0303 N3_V06S0203
|
|
enum: CIB.JB3MUX 0
|
|
|
|
.tile CIB_R35C1:CIB_LR
|
|
arc: E3_H06E0303 S3_V06N0303
|
|
arc: N1_V02N0701 JQ5
|
|
arc: N3_V06N0003 S3_V06N0303
|
|
arc: N3_V06N0303 JF5
|
|
|
|
.tile CIB_R35C89:CIB_LR
|
|
arc: H00L0000 N1_V02S0201
|
|
arc: JA0 H00L0000
|
|
arc: N3_V06N0303 JQ5
|
|
arc: W3_H06W0303 S3_V06N0303
|
|
enum: CIB.JB0MUX 0
|
|
|
|
.tile CIB_R36C1:CIB_LR
|
|
arc: E3_H06E0103 V01N0101
|
|
arc: N3_V06N0103 V01N0101
|
|
arc: N3_V06N0303 S1_V02N0501
|
|
|
|
.tile CIB_R36C89:CIB_LR
|
|
arc: S1_V02S0701 H02E0701
|
|
arc: S3_V06S0203 N3_V06S0203
|
|
|
|
.tile CIB_R37C1:CIB_LR
|
|
arc: E3_H06E0303 JQ5
|
|
arc: N1_V01N0101 JF5
|
|
arc: N3_V06N0003 S3_V06N0303
|
|
arc: N3_V06N0303 JQ5
|
|
|
|
.tile CIB_R37C89:CIB_LR
|
|
arc: H00L0100 H02E0101
|
|
arc: JA3 H00L0100
|
|
arc: N3_V06N0303 JF5
|
|
arc: W3_H06W0303 S3_V06N0303
|
|
enum: CIB.JB3MUX 0
|
|
|
|
.tile CIB_R38C1:CIB_LR
|
|
arc: E3_H06E0003 S3_V06N0003
|
|
arc: E3_H06E0303 S3_V06N0303
|
|
arc: N1_V02N0501 JQ5
|
|
arc: N3_V06N0103 S3_V06N0003
|
|
arc: N3_V06N0303 JF5
|
|
arc: S3_V06S0103 N3_V06S0003
|
|
|
|
.tile CIB_R38C89:CIB_LR
|
|
arc: JA3 N1_V02S0701
|
|
arc: N3_V06N0303 JF5
|
|
enum: CIB.JB3MUX 0
|
|
|
|
.tile CIB_R39C1:CIB_LR
|
|
arc: S1_V02S0701 N3_V06S0203
|
|
arc: S3_V06S0303 N3_V06S0303
|
|
|
|
.tile CIB_R39C89:CIB_LR
|
|
arc: S3_V06S0203 N3_V06S0203
|
|
|
|
.tile CIB_R40C1:CIB_LR
|
|
arc: E1_H02E0701 JF5
|
|
arc: E3_H06E0303 JQ5
|
|
arc: N3_V06N0303 S3_V06N0303
|
|
arc: S1_V02S0101 N3_V06S0103
|
|
arc: S3_V06S0003 N3_V06S0003
|
|
arc: S3_V06S0303 N3_V06S0303
|
|
|
|
.tile CIB_R40C89:CIB_LR
|
|
arc: JA0 H02E0501
|
|
arc: S1_V02S0301 N3_V06S0003
|
|
arc: S1_V02S0701 N3_V06S0203
|
|
arc: S3_V06S0303 N3_V06S0303
|
|
arc: W3_H06W0303 JQ5
|
|
enum: CIB.JB0MUX 0
|
|
|
|
.tile CIB_R41C1:CIB_LR
|
|
arc: E3_H06E0303 JQ5
|
|
arc: N3_V06N0303 JF5
|
|
arc: S1_V02S0701 N1_V02S0701
|
|
|
|
.tile CIB_R41C89:CIB_LR
|
|
arc: H01W0100 JQ5
|
|
arc: N3_V06N0303 JF5
|
|
arc: W3_H06W0003 S3_V06N0003
|
|
arc: W3_H06W0303 S3_V06N0303
|
|
|
|
.tile CIB_R42C1:CIB_LR
|
|
arc: E3_H06E0303 S3_V06N0303
|
|
arc: S1_V02S0401 N1_V02S0101
|
|
|
|
.tile CIB_R42C89:CIB_LR
|
|
arc: S1_V02S0401 N3_V06S0203
|
|
arc: S1_V02S0501 W1_H02E0501
|
|
arc: S1_V02S0601 N1_V02S0301
|
|
arc: S1_V02S0701 N1_V02S0701
|
|
|
|
.tile CIB_R43C1:CIB_LR
|
|
arc: E3_H06E0303 S3_V06N0303
|
|
arc: JA3 N1_V02S0701
|
|
arc: N3_V06N0303 JF5
|
|
enum: CIB.JB3MUX 0
|
|
|
|
.tile CIB_R43C89:CIB_LR
|
|
arc: H00R0000 V02S0401
|
|
arc: JA0 H00R0000
|
|
arc: N3_V06N0303 JQ5
|
|
arc: W3_H06W0303 S3_V06N0303
|
|
enum: CIB.JB0MUX 0
|
|
|
|
.tile CIB_R44C1:CIB_LR
|
|
arc: E3_H06E0303 JQ5
|
|
arc: N3_V06N0003 S3_V06N0303
|
|
arc: N3_V06N0303 JF5
|
|
arc: S1_V02S0501 N1_V02S0401
|
|
arc: V01S0000 N3_V06S0103
|
|
|
|
.tile CIB_R44C89:CIB_LR
|
|
arc: H00R0000 N1_V02S0601
|
|
arc: JA0 H00R0000
|
|
arc: JA3 N1_V02S0501
|
|
arc: S1_V02S0701 N1_V02S0701
|
|
arc: W3_H06W0303 S3_V06N0303
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB0MUX 0
|
|
|
|
.tile CIB_R45C1:CIB_LR
|
|
arc: S1_V02S0601 N1_V01S0000
|
|
arc: S3_V06S0003 N3_V06S0303
|
|
|
|
.tile CIB_R45C89:CIB_LR
|
|
arc: S3_V06S0303 N3_V06S0203
|
|
|
|
.tile CIB_R46C13:CIB_DSP
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
|
|
.tile CIB_R46C16:CIB_DSP
|
|
arc: N3_V06N0103 S3_V06N0103
|
|
|
|
.tile CIB_R46C17:CIB_DSP
|
|
arc: N3_V06N0303 S3_V06N0203
|
|
|
|
.tile CIB_R46C19:CIB_DSP
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
|
|
.tile CIB_R46C1:CIB_LR_S
|
|
arc: E3_H06E0303 S3_V06N0303
|
|
arc: JA0 N1_V02S0501
|
|
arc: N3_V06N0303 JQ5
|
|
arc: S3_V06S0103 N3_V06S0003
|
|
arc: S3_V06S0303 N3_V06S0303
|
|
enum: CIB.JB0MUX 0
|
|
|
|
.tile CIB_R46C20:CIB_DSP
|
|
arc: S3_V06S0303 N3_V06S0203
|
|
|
|
.tile CIB_R46C22:CIB_DSP
|
|
arc: N3_V06N0203 S3_V06N0103
|
|
|
|
.tile CIB_R46C23:CIB_DSP
|
|
arc: N3_V06N0203 S3_V06N0203
|
|
|
|
.tile CIB_R46C25:CIB_DSP
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: N3_V06N0203 S3_V06N0103
|
|
|
|
.tile CIB_R46C26:CIB_DSP
|
|
arc: N3_V06N0203 S3_V06N0103
|
|
|
|
.tile CIB_R46C2:CIB_DSP
|
|
arc: S3_V06S0203 N3_V06S0203
|
|
|
|
.tile CIB_R46C30:CIB_DSP
|
|
arc: N3_V06N0003 S3_V06N0003
|
|
|
|
.tile CIB_R46C31:CIB_DSP
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: N3_V06N0003 S3_V06N0303
|
|
|
|
.tile CIB_R46C32:CIB_DSP
|
|
arc: N3_V06N0303 S3_V06N0303
|
|
|
|
.tile CIB_R46C34:CIB_DSP
|
|
arc: N3_V06N0003 S3_V06N0003
|
|
|
|
.tile CIB_R46C35:CIB_DSP
|
|
arc: N3_V06N0103 S3_V06N0003
|
|
arc: N3_V06N0303 S3_V06N0303
|
|
|
|
.tile CIB_R46C36:CIB_DSP
|
|
arc: N3_V06N0303 S3_V06N0303
|
|
|
|
.tile CIB_R46C37:CIB_DSP
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: N3_V06N0003 S3_V06N0003
|
|
arc: N3_V06N0303 S3_V06N0303
|
|
|
|
.tile CIB_R46C38:CIB_DSP
|
|
arc: N3_V06N0303 S3_V06N0203
|
|
|
|
.tile CIB_R46C39:CIB_DSP
|
|
arc: N3_V06N0203 S3_V06N0203
|
|
|
|
.tile CIB_R46C40:CIB_DSP
|
|
arc: N3_V06N0003 H06E0003
|
|
arc: N3_V06N0203 S3_V06N0203
|
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.tile CIB_R46C41:CIB_DSP
|
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arc: N1_V02N0301 S3_V06N0003
|
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arc: N3_V06N0003 S3_V06N0303
|
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arc: N3_V06N0103 S3_V06N0103
|
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.tile CIB_R46C42:CIB_DSP
|
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arc: N3_V06N0103 S3_V06N0003
|
|
|
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.tile CIB_R46C43:CIB_DSP
|
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arc: E3_H06E0103 W3_H06E0003
|
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arc: N3_V06N0003 S3_V06N0003
|
|
|
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.tile CIB_R46C44:CIB_DSP
|
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arc: N3_V06N0003 S3_V06N0303
|
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.tile CIB_R46C45:CIB_DSP
|
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arc: N3_V06N0003 S3_V06N0003
|
|
|
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.tile CIB_R46C46:CIB_DSP
|
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arc: N1_V02N0101 H06E0103
|
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arc: N3_V06N0103 S3_V06N0003
|
|
|
|
.tile CIB_R46C47:CIB_DSP
|
|
arc: N3_V06N0103 S3_V06N0003
|
|
arc: N3_V06N0303 S3_V06N0303
|
|
|
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.tile CIB_R46C48:CIB_DSP
|
|
arc: N3_V06N0103 S3_V06N0103
|
|
|
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.tile CIB_R46C49:CIB_DSP
|
|
arc: N3_V06N0103 W3_H06E0103
|
|
arc: N3_V06N0203 S3_V06N0103
|
|
|
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.tile CIB_R46C50:CIB_DSP
|
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arc: N3_V06N0003 S3_V06N0003
|
|
|
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.tile CIB_R46C51:CIB_DSP
|
|
arc: N3_V06N0103 S3_V06N0103
|
|
|
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.tile CIB_R46C52:CIB_DSP
|
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arc: N3_V06N0003 S3_V06N0003
|
|
|
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.tile CIB_R46C53:CIB_DSP
|
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arc: N3_V06N0103 S3_V06N0003
|
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arc: N3_V06N0303 S3_V06N0203
|
|
|
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.tile CIB_R46C55:CIB_DSP
|
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arc: N3_V06N0003 S3_V06N0303
|
|
|
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.tile CIB_R46C58:CIB_DSP
|
|
arc: N3_V06N0003 S3_V06N0303
|
|
arc: N3_V06N0103 S3_V06N0103
|
|
|
|
.tile CIB_R46C61:CIB_DSP
|
|
arc: N3_V06N0003 S3_V06N0003
|
|
|
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.tile CIB_R46C64:CIB_DSP
|
|
arc: N3_V06N0103 S3_V06N0003
|
|
|
|
.tile CIB_R46C65:CIB_DSP
|
|
arc: N3_V06N0003 E3_H06W0003
|
|
|
|
.tile CIB_R46C71:CIB_DSP
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
|
|
.tile CIB_R46C77:CIB_DSP
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
|
|
.tile CIB_R46C7:CIB_DSP
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
|
|
.tile CIB_R46C83:CIB_DSP
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
|
|
.tile CIB_R46C87:CIB_DSP
|
|
arc: E1_H02E0501 N3_V06S0303
|
|
arc: S3_V06S0203 N3_V06S0103
|
|
|
|
.tile CIB_R46C88:CIB_DSP
|
|
arc: S3_V06S0203 N3_V06S0103
|
|
|
|
.tile CIB_R46C89:CIB_LR_S
|
|
arc: JA0 N1_V02S0701
|
|
arc: JA3 W1_H02E0501
|
|
arc: S3_V06S0303 N3_V06S0303
|
|
arc: W3_H06W0303 S3_V06N0303
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB0MUX 0
|
|
|
|
.tile CIB_R47C1:CIB_LR
|
|
arc: E3_H06E0303 JQ5
|
|
arc: H00R0000 N1_V02S0601
|
|
arc: JA0 H00R0000
|
|
enum: CIB.JB0MUX 0
|
|
|
|
.tile CIB_R47C89:CIB_LR
|
|
arc: N3_V06N0003 S3_V06N0303
|
|
arc: N3_V06N0303 JF5
|
|
arc: W3_H06W0303 JQ5
|
|
|
|
.tile CIB_R48C1:CIB_LR
|
|
arc: N3_V06N0303 S1_V02N0501
|
|
|
|
.tile CIB_R49C1:CIB_LR
|
|
arc: E3_H06E0303 JQ5
|
|
arc: N3_V06N0303 JF5
|
|
|
|
.tile CIB_R49C89:CIB_LR
|
|
arc: H01W0100 JQ5
|
|
arc: N3_V06N0303 JF5
|
|
arc: W3_H06W0303 S3_V06N0303
|
|
|
|
.tile CIB_R50C1:CIB_LR
|
|
arc: E3_H06E0303 S3_V06N0303
|
|
arc: N1_V02N0501 JQ5
|
|
arc: N3_V06N0303 JF5
|
|
|
|
.tile CIB_R50C89:CIB_LR
|
|
arc: JA3 H02E0701
|
|
arc: N3_V06N0303 JF5
|
|
arc: W3_H06W0303 S3_V06N0303
|
|
enum: CIB.JB3MUX 0
|
|
|
|
.tile CIB_R51C1:CIB_LR
|
|
arc: S1_V02S0601 H02W0601
|
|
arc: S3_V06S0103 N3_V06S0003
|
|
|
|
.tile CIB_R51C89:CIB_LR
|
|
arc: S1_V02S0501 N3_V06S0303
|
|
|
|
.tile CIB_R52C1:CIB_LR
|
|
arc: E3_H06E0303 S3_V06N0303
|
|
arc: JA3 H02W0701
|
|
arc: N3_V06N0303 JF5
|
|
arc: S1_V02S0501 N3_V06S0303
|
|
arc: S3_V06S0203 N3_V06S0103
|
|
enum: CIB.JB3MUX 0
|
|
|
|
.tile CIB_R52C89:CIB_LR
|
|
arc: JA0 V02S0501
|
|
arc: N3_V06N0303 S3_V06N0303
|
|
arc: S1_V02S0501 N3_V06S0303
|
|
arc: W3_H06W0303 JQ5
|
|
enum: CIB.JB0MUX 0
|
|
|
|
.tile CIB_R53C1:CIB_LR
|
|
arc: E3_H06E0303 JQ5
|
|
arc: JA0 V02S0501
|
|
arc: S1_V02S0701 N1_V02S0601
|
|
enum: CIB.JB0MUX 0
|
|
|
|
.tile CIB_R53C89:CIB_LR
|
|
arc: N3_V06N0303 JF5
|
|
arc: W3_H06W0303 JQ5
|
|
|
|
.tile CIB_R54C89:CIB_LR
|
|
arc: S1_V02S0501 N1_V02S0501
|
|
|
|
.tile CIB_R55C1:CIB_LR
|
|
arc: E3_H06E0303 JQ5
|
|
arc: JA0 N1_V02S0701
|
|
enum: CIB.JB0MUX 0
|
|
|
|
.tile CIB_R55C89:CIB_LR
|
|
arc: JA0 W1_H02E0701
|
|
arc: N3_V06N0303 JQ5
|
|
arc: W3_H06W0303 S3_V06N0303
|
|
enum: CIB.JB0MUX 0
|
|
|
|
.tile CIB_R56C1:CIB_LR
|
|
arc: E3_H06E0303 S3_V06N0303
|
|
arc: H00L0100 V02N0101
|
|
arc: JA3 H00L0100
|
|
arc: N3_V06N0303 S1_V02N0501
|
|
enum: CIB.JB3MUX 0
|
|
|
|
.tile CIB_R56C89:CIB_LR
|
|
arc: JA3 N1_V02S0501
|
|
arc: N3_V06N0303 JF5
|
|
enum: CIB.JB3MUX 0
|
|
|
|
.tile CIB_R57C1:CIB_LR
|
|
arc: N1_V02N0101 N3_V06S0103
|
|
arc: S1_V02S0601 E1_H02W0601
|
|
arc: S1_V02S0701 E1_H02W0701
|
|
|
|
.tile CIB_R57C89:CIB_LR
|
|
arc: S1_V02S0601 H02E0601
|
|
|
|
.tile CIB_R58C13:CIB_EBR
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
|
|
.tile CIB_R58C16:CIB_EBR
|
|
arc: N3_V06N0103 S3_V06N0103
|
|
|
|
.tile CIB_R58C17:CIB_EBR
|
|
arc: N3_V06N0203 S3_V06N0103
|
|
|
|
.tile CIB_R58C19:CIB_EBR
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
|
|
.tile CIB_R58C1:CIB_LR_S
|
|
arc: E3_H06E0303 S3_V06N0303
|
|
arc: N1_V02N0501 JQ5
|
|
arc: N3_V06N0303 JF5
|
|
arc: S1_V02S0701 N3_V06S0203
|
|
|
|
.tile CIB_R58C20:CIB_EBR
|
|
arc: S3_V06S0103 N3_V06S0003
|
|
|
|
.tile CIB_R58C22:CIB_EBR
|
|
arc: N3_V06N0103 S3_V06N0103
|
|
|
|
.tile CIB_R58C23:CIB_EBR
|
|
arc: N3_V06N0103 S3_V06N0103
|
|
|
|
.tile CIB_R58C25:CIB_EBR
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
arc: N3_V06N0103 S3_V06N0103
|
|
|
|
.tile CIB_R58C26:CIB_EBR
|
|
arc: N3_V06N0003 S3_V06N0003
|
|
|
|
.tile CIB_R58C30:CIB_EBR
|
|
arc: N3_V06N0303 S3_V06N0203
|
|
|
|
.tile CIB_R58C31:CIB_EBR
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
arc: N3_V06N0303 S3_V06N0203
|
|
|
|
.tile CIB_R58C32:CIB_EBR
|
|
arc: N3_V06N0203 S3_V06N0103
|
|
|
|
.tile CIB_R58C34:CIB_EBR
|
|
arc: N3_V06N0003 S3_V06N0303
|
|
|
|
.tile CIB_R58C35:CIB_EBR
|
|
arc: N3_V06N0203 S3_V06N0103
|
|
arc: N3_V06N0303 S3_V06N0203
|
|
|
|
.tile CIB_R58C36:CIB_EBR
|
|
arc: N3_V06N0203 S3_V06N0103
|
|
|
|
.tile CIB_R58C37:CIB_EBR
|
|
arc: N3_V06N0203 W3_H06E0203
|
|
arc: N3_V06N0303 S3_V06N0203
|
|
|
|
.tile CIB_R58C38:CIB_EBR
|
|
arc: N3_V06N0203 S3_V06N0103
|
|
|
|
.tile CIB_R58C39:CIB_EBR
|
|
arc: N3_V06N0203 S3_V06N0103
|
|
|
|
.tile CIB_R58C40:CIB_EBR
|
|
arc: N3_V06N0203 S3_V06N0203
|
|
|
|
.tile CIB_R58C41:CIB_EBR
|
|
arc: N3_V06N0003 E3_H06W0003
|
|
arc: N3_V06N0303 S3_V06N0203
|
|
|
|
.tile CIB_R58C42:CIB_EBR
|
|
arc: N3_V06N0303 S3_V06N0303
|
|
|
|
.tile CIB_R58C43:CIB_EBR
|
|
arc: N3_V06N0303 S3_V06N0303
|
|
|
|
.tile CIB_R58C45:CIB_EBR
|
|
arc: N3_V06N0303 S3_V06N0203
|
|
|
|
.tile CIB_R58C46:CIB_EBR
|
|
arc: N3_V06N0003 S3_V06N0303
|
|
|
|
.tile CIB_R58C47:CIB_EBR
|
|
arc: N3_V06N0003 E3_H06W0003
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
|
|
.tile CIB_R58C48:CIB_EBR
|
|
arc: N3_V06N0003 S3_V06N0003
|
|
|
|
.tile CIB_R58C49:CIB_EBR
|
|
arc: N3_V06N0003 S3_V06N0303
|
|
|
|
.tile CIB_R58C50:CIB_EBR
|
|
arc: N3_V06N0003 H06W0003
|
|
|
|
.tile CIB_R58C51:CIB_EBR
|
|
arc: N3_V06N0003 S3_V06N0003
|
|
|
|
.tile CIB_R58C52:CIB_EBR
|
|
arc: N3_V06N0303 S3_V06N0203
|
|
|
|
.tile CIB_R58C53:CIB_EBR
|
|
arc: N3_V06N0003 E3_H06W0003
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
|
|
.tile CIB_R58C55:CIB_EBR
|
|
arc: N3_V06N0203 S3_V06N0103
|
|
|
|
.tile CIB_R58C58:CIB_EBR
|
|
arc: N3_V06N0103 S3_V06N0003
|
|
|
|
.tile CIB_R58C59:CIB_EBR
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
|
|
.tile CIB_R58C61:CIB_EBR
|
|
arc: N3_V06N0003 S3_V06N0003
|
|
|
|
.tile CIB_R58C64:CIB_EBR
|
|
arc: N3_V06N0003 S3_V06N0303
|
|
|
|
.tile CIB_R58C65:CIB_EBR
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
|
|
.tile CIB_R58C71:CIB_EBR
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
|
|
.tile CIB_R58C77:CIB_EBR
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
|
|
.tile CIB_R58C7:CIB_EBR
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
|
|
.tile CIB_R58C83:CIB_EBR
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
|
|
.tile CIB_R58C89:CIB_LR_S
|
|
arc: N3_V06N0303 JF5
|
|
arc: W3_H06W0303 S3_V06N0303
|
|
|
|
.tile CIB_R59C1:CIB_LR
|
|
arc: E3_H06E0303 S3_V06N0303
|
|
arc: JA0 V02S0701
|
|
arc: JA3 N1_V02S0701
|
|
arc: S1_V02S0701 N1_V02S0601
|
|
enum: CIB.JB0MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
|
|
.tile CIB_R59C89:CIB_LR
|
|
arc: S1_V02S0701 N1_V02S0601
|
|
arc: W3_H06W0303 JQ5
|
|
|
|
.tile CIB_R5C1:CIB_PLL1
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
|
|
.tile CIB_R5C89:CIB_PLL1
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
|
|
.tile CIB_R61C1:CIB_LR
|
|
arc: E3_H06E0303 S3_V06N0303
|
|
arc: JA3 N1_V02S0701
|
|
enum: CIB.JB3MUX 0
|
|
|
|
.tile CIB_R61C89:CIB_LR
|
|
arc: JA0 N1_V02S0701
|
|
arc: N3_V06N0303 JQ5
|
|
arc: W3_H06W0303 S3_V06N0303
|
|
enum: CIB.JB0MUX 0
|
|
|
|
.tile CIB_R62C1:CIB_LR
|
|
arc: E3_H06E0303 JQ5
|
|
arc: N3_V06N0303 JF5
|
|
|
|
.tile CIB_R62C89:CIB_LR
|
|
arc: W3_H06W0303 JF5
|
|
|
|
.tile CIB_R63C1:CIB_LR
|
|
arc: S1_V02S0301 E1_H02W0301
|
|
arc: S1_V02S0701 E1_H02W0701
|
|
|
|
.tile CIB_R64C1:CIB_LR
|
|
arc: JA3 H02W0701
|
|
arc: N3_V06N0303 JF5
|
|
enum: CIB.JB3MUX 0
|
|
|
|
.tile CIB_R64C89:CIB_LR
|
|
arc: N3_V06N0303 JF5
|
|
arc: W3_H06W0303 JQ5
|
|
|
|
.tile CIB_R65C1:CIB_LR
|
|
arc: H00L0100 N1_V02S0301
|
|
arc: JA3 H00L0100
|
|
arc: N3_V06N0303 JF5
|
|
arc: S1_V02S0701 N1_V02S0701
|
|
enum: CIB.JB3MUX 0
|
|
|
|
.tile CIB_R67C1:CIB_LR
|
|
arc: JA3 N1_V02S0701
|
|
arc: N3_V06N0303 JF5
|
|
enum: CIB.JB3MUX 0
|
|
|
|
.tile CIB_R67C89:CIB_LR
|
|
arc: N3_V06N0303 JF5
|
|
arc: W3_H06W0303 JQ5
|
|
|
|
.tile CIB_R70C10:CIB
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
|
|
.tile CIB_R70C11:CIB
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: JA0 V02S0701
|
|
enum: CIB.JB0MUX 0
|
|
|
|
.tile CIB_R70C12:CIB
|
|
arc: E3_H06E0003 JQ0
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
|
|
.tile CIB_R70C13:CIB
|
|
arc: E3_H06E0003 JQ0
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
|
|
.tile CIB_R70C14:CIB
|
|
arc: E1_H02E0701 N1_V01S0100
|
|
arc: JA0 H02W0501
|
|
enum: CIB.JB0MUX 0
|
|
|
|
.tile CIB_R70C15:CIB
|
|
arc: E3_H06E0003 JQ0
|
|
arc: W1_H02W0501 N1_V01S0100
|
|
|
|
.tile CIB_R70C16:CIB
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: JA0 W1_H02E0701
|
|
arc: N3_V06N0103 H06E0103
|
|
enum: CIB.JB0MUX 0
|
|
|
|
.tile CIB_R70C17:CIB
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: N3_V06N0003 W3_H06E0003
|
|
|
|
.tile CIB_R70C18:CIB
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: JA0 E1_H02W0701
|
|
enum: CIB.JB0MUX 0
|
|
|
|
.tile CIB_R70C19:CIB
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
|
|
.tile CIB_R70C20:CIB
|
|
arc: W1_H02W0701 N3_V06S0203
|
|
|
|
.tile CIB_R70C21:CIB
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
|
|
.tile CIB_R70C22:CIB
|
|
arc: N3_V06N0103 W3_H06E0103
|
|
|
|
.tile CIB_R70C23:CIB
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: N3_V06N0003 W3_H06E0003
|
|
|
|
.tile CIB_R70C24:CIB
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
|
|
.tile CIB_R70C25:CIB
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: N3_V06N0103 W3_H06E0103
|
|
|
|
.tile CIB_R70C26:CIB
|
|
arc: N3_V06N0003 H06E0003
|
|
|
|
.tile CIB_R70C27:CIB
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
|
|
.tile CIB_R70C29:CIB
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
|
|
.tile CIB_R70C30:CIB
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: N3_V06N0203 W3_H06E0203
|
|
|
|
.tile CIB_R70C31:CIB
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: N3_V06N0103 W3_H06E0103
|
|
|
|
.tile CIB_R70C32:CIB
|
|
arc: N3_V06N0103 H06E0103
|
|
|
|
.tile CIB_R70C33:CIB
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
|
|
.tile CIB_R70C34:CIB
|
|
arc: N3_V06N0203 H06E0203
|
|
|
|
.tile CIB_R70C35:CIB
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: N3_V06N0103 W3_H06E0103
|
|
|
|
.tile CIB_R70C36:CIB
|
|
arc: N3_V06N0103 W3_H06E0103
|
|
|
|
.tile CIB_R70C37:CIB
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
arc: N3_V06N0203 W3_H06E0203
|
|
|
|
.tile CIB_R70C38:CIB
|
|
arc: N3_V06N0103 H06E0103
|
|
|
|
.tile CIB_R70C39:CIB
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: N3_V06N0103 W3_H06E0103
|
|
|
|
.tile CIB_R70C3:CIB_PLL3
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
|
|
.tile CIB_R70C40:CIB
|
|
arc: N3_V06N0203 H06E0203
|
|
|
|
.tile CIB_R70C41:CIB
|
|
arc: N3_V06N0103 W3_H06E0103
|
|
|
|
.tile CIB_R70C42:VCIB_DCU0
|
|
arc: N3_V06N0203 H06E0203
|
|
enum: CIB.JA1MUX 0
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JC2MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
enum: CIB.JC6MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C43:VCIB_DCUA
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
arc: N3_V06N0203 W3_H06E0203
|
|
enum: CIB.JA1MUX 0
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JC2MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
enum: CIB.JC6MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C44:VCIB_DCUB
|
|
enum: CIB.JA1MUX 0
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JC2MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
enum: CIB.JC6MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C45:VCIB_DCUC
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
arc: N3_V06N0203 W3_H06E0203
|
|
enum: CIB.JA1MUX 0
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JC2MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
enum: CIB.JC6MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C46:VCIB_DCUD
|
|
arc: N3_V06N0203 H06E0203
|
|
enum: CIB.JA1MUX 0
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JC2MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
enum: CIB.JC6MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C47:VCIB_DCUF
|
|
enum: CIB.JA1MUX 0
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JC2MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
enum: CIB.JC6MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C48:VCIB_DCU3
|
|
arc: N3_V06N0303 H06E0303
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
enum: CIB.JC6MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C49:VCIB_DCU2
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
arc: N3_V06N0203 W3_H06E0203
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C4:CIB
|
|
arc: E3_H06E0003 JQ0
|
|
|
|
.tile CIB_R70C50:VCIB_DCUG
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C51:VCIB_DCUH
|
|
arc: N3_V06N0303 W3_H06E0303
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C52:VCIB_DCUI
|
|
arc: N3_V06N0203 H06E0203
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C53:VCIB_DCU1
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
|
|
.tile CIB_R70C55:CIB
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
arc: N3_V06N0103 W3_H06E0103
|
|
|
|
.tile CIB_R70C58:CIB
|
|
arc: N3_V06N0303 H06E0303
|
|
|
|
.tile CIB_R70C5:CIB
|
|
arc: E3_H06E0003 JQ0
|
|
|
|
.tile CIB_R70C61:CIB
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
arc: N3_V06N0303 W3_H06E0303
|
|
|
|
.tile CIB_R70C64:CIB
|
|
arc: N3_V06N0303 H06E0303
|
|
|
|
.tile CIB_R70C69:VCIB_DCU0
|
|
enum: CIB.JA1MUX 0
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JC2MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
enum: CIB.JC6MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C6:CIB_EFB0
|
|
arc: E3_H06E0003 JQ0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JC6MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C70:VCIB_DCUA
|
|
enum: CIB.JA1MUX 0
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JC2MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
enum: CIB.JC6MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C71:VCIB_DCUB
|
|
enum: CIB.JA1MUX 0
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JC2MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
enum: CIB.JC6MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C72:VCIB_DCUC
|
|
enum: CIB.JA1MUX 0
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JC2MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
enum: CIB.JC6MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C73:VCIB_DCUD
|
|
enum: CIB.JA1MUX 0
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JC2MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
enum: CIB.JC6MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C74:VCIB_DCUF
|
|
enum: CIB.JA1MUX 0
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JC2MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
enum: CIB.JC6MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C75:VCIB_DCU3
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
enum: CIB.JC6MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C76:VCIB_DCU2
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C77:VCIB_DCUG
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C78:VCIB_DCUH
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C79:VCIB_DCUI
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C7:CIB_EFB1
|
|
arc: E3_H06E0003 JQ0
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JA4MUX 0
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JA6MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB4MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB6MUX 0
|
|
enum: CIB.JC3MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
enum: CIB.JC5MUX 0
|
|
enum: CIB.JD3MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD5MUX 0
|
|
|
|
.tile CIB_R70C80:VCIB_DCU1
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
|
|
.tile CIB_R70C87:CIB_PLL3
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
|
|
.tile MIB_R0C11:PIOT0
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOA.HYSTERESIS ON
|
|
|
|
.tile MIB_R0C12:PIOT1
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOB.HYSTERESIS ON
|
|
|
|
.tile MIB_R0C13:PIOT0
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOA.HYSTERESIS ON
|
|
|
|
.tile MIB_R0C14:PIOT1
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R0C15:PIOT0
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R0C16:PIOT1
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R0C18:PIOT0
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R0C20:PIOT0
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOA.HYSTERESIS ON
|
|
|
|
.tile MIB_R0C21:PIOT1
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOB.HYSTERESIS ON
|
|
|
|
.tile MIB_R0C22:PIOT0
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R0C23:PIOT1
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R0C24:PIOT0
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R0C25:PIOT1
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOB.HYSTERESIS ON
|
|
|
|
.tile MIB_R0C27:PIOT0
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOA.HYSTERESIS ON
|
|
|
|
.tile MIB_R0C28:PIOT1
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R0C31:PIOT0
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOA.HYSTERESIS ON
|
|
|
|
.tile MIB_R0C32:PIOT1
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R0C33:PIOT0
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOA.HYSTERESIS ON
|
|
|
|
.tile MIB_R0C34:PIOT1
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R0C36:PIOT0
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R0C37:PIOT1
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOB.HYSTERESIS ON
|
|
|
|
.tile MIB_R0C38:PIOT0
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOA.HYSTERESIS ON
|
|
|
|
.tile MIB_R0C39:PIOT1
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOB.HYSTERESIS ON
|
|
|
|
.tile MIB_R0C3:BANKREF0
|
|
enum: BANK.VCCIO 3V3
|
|
|
|
.tile MIB_R0C40:TMID_0
|
|
arc: G_TDCC0CLKI G_JURMPCLKCIB1
|
|
|
|
.tile MIB_R0C42:PIOT0
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R0C43:PIOT1
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOB.HYSTERESIS ON
|
|
|
|
.tile MIB_R0C44:PIOT0
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOA.HYSTERESIS ON
|
|
|
|
.tile MIB_R0C45:PIOT1
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOB.HYSTERESIS ON
|
|
|
|
.tile MIB_R0C47:PIOT0
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R0C48:PIOT1
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R0C49:PIOT0
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOA.HYSTERESIS ON
|
|
|
|
.tile MIB_R0C4:PIOT0
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R0C50:PIOT1
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOB.HYSTERESIS ON
|
|
|
|
.tile MIB_R0C51:PIOT0
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOA.HYSTERESIS ON
|
|
|
|
.tile MIB_R0C52:PIOT1
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOB.HYSTERESIS ON
|
|
|
|
.tile MIB_R0C54:PIOT1
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R0C56:PIOT0
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R0C57:PIOT1
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOB.HYSTERESIS ON
|
|
|
|
.tile MIB_R0C58:PIOT0
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOA.HYSTERESIS ON
|
|
|
|
.tile MIB_R0C59:PIOT1
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R0C5:PIOT1
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOB.HYSTERESIS ON
|
|
|
|
.tile MIB_R0C60:PIOT0
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOA.HYSTERESIS ON
|
|
|
|
.tile MIB_R0C65:PIOT0
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R0C66:PIOT1
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOB.HYSTERESIS ON
|
|
|
|
.tile MIB_R0C67:PIOT0
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOA.HYSTERESIS ON
|
|
|
|
.tile MIB_R0C68:PIOT1
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R0C69:PIOT0
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R0C6:PIOT0
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R0C70:PIOT1
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R0C74:PIOT0
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOA.HYSTERESIS ON
|
|
|
|
.tile MIB_R0C75:PIOT1
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R0C76:PIOT0
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOA.HYSTERESIS ON
|
|
|
|
.tile MIB_R0C77:PIOT1
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R0C78:PIOT0
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOA.HYSTERESIS ON
|
|
|
|
.tile MIB_R0C79:PIOT1
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R0C7:PIOT1
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R0C80:PIOT0
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOA.HYSTERESIS ON
|
|
|
|
.tile MIB_R0C81:PIOT1
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R0C83:PIOT0
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R0C84:PIOT1
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R0C87:BANKREF1
|
|
enum: BANK.VCCIO 3V3
|
|
|
|
.tile MIB_R0C9:PIOT0
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOA.HYSTERESIS ON
|
|
|
|
.tile MIB_R10C0:BANKREF7
|
|
enum: BANK.VCCIO 3V3
|
|
|
|
.tile MIB_R10C12:EBR_SPINE_UL1
|
|
arc: G_VPTX0000 G_HPRX0000
|
|
|
|
.tile MIB_R10C30:EBR_SPINE_UL0
|
|
arc: G_VPTX0000 G_HPRX0000
|
|
|
|
.tile MIB_R10C40:CMUX_UL_0
|
|
arc: G_DCS0CLK0 G_VPFN0000
|
|
arc: G_ULPCLK0 G_VPFS0000
|
|
|
|
.tile MIB_R10C41:CMUX_UR_0
|
|
arc: G_DCS0CLK1 G_VPFN0000
|
|
arc: G_URPCLK0 G_VPFS0000
|
|
|
|
.tile MIB_R10C50:EBR_SPINE_UR0
|
|
arc: G_VPTX0000 G_HPRX0000
|
|
|
|
.tile MIB_R10C77:EBR_SPINE_UR1
|
|
arc: G_VPTX0000 G_HPRX0000
|
|
|
|
.tile MIB_R10C90:BANKREF2
|
|
enum: BANK.VCCIO 3V3
|
|
|
|
.tile MIB_R11C90:PICR0
|
|
arc: JDIB JPADDIB_PIO
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R12C0:PICL1
|
|
enum: PIOC.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOC.HYSTERESIS ON
|
|
|
|
.tile MIB_R12C90:PICR1
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOB.HYSTERESIS ON
|
|
|
|
.tile MIB_R13C0:PICL2
|
|
enum: PIOC.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R14C0:PICL0
|
|
arc: JDIA JPADDIA_PIO
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R14C90:PICR0
|
|
arc: JDIB JPADDIB_PIO
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R15C0:PICL1_DQS0
|
|
enum: PIOD.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOD.HYSTERESIS ON
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOA.HYSTERESIS ON
|
|
enum: PIOC.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOC.HYSTERESIS ON
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R15C90:PICR1_DQS0
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOB.HYSTERESIS ON
|
|
enum: PIOC.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOC.HYSTERESIS ON
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R16C0:PICL2_DQS1
|
|
enum: PIOD.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOC.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R16C90:PICR2_DQS1
|
|
enum: PIOC.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R17C0:PICL0_DQS2
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R17C90:PICR0_DQS2
|
|
arc: JDIB JPADDIB_PIO
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R18C0:PICL1_DQS3
|
|
enum: PIOD.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOD.HYSTERESIS ON
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R18C90:PICR1_DQS3
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOB.HYSTERESIS ON
|
|
enum: PIOC.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOC.HYSTERESIS ON
|
|
enum: PIOD.BASE_TYPE OUTPUT_LVCMOS33
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R19C0:PICL2
|
|
enum: PIOD.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R19C90:PICR2
|
|
enum: PIOC.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOD.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C11:PICT0
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C12:PICT1
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C13:PICT0
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C14:PICT1
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C15:PICT0
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C16:PICT1
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C18:PICT0
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C20:PICT0
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C21:PICT1
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C22:PICT0
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C23:PICT1
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C24:PICT0
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C25:PICT1
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C27:PICT0
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C28:PICT1
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C31:PICT0
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C32:PICT1
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C33:PICT0
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C34:PICT1
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C36:PICT0
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C37:PICT1
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C38:PICT0
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C39:PICT1
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C42:PICT0
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C43:PICT1
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C44:PICT0
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C45:PICT1
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C47:PICT0
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C48:PICT1
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C49:PICT0
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C4:PICT0
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C50:PICT1
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C51:PICT0
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C52:PICT1
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C54:PICT1
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C56:PICT0
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C57:PICT1
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C58:PICT0
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C59:PICT1
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C5:PICT1
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C60:PICT0
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C65:PICT0
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C66:PICT1
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C67:PICT0
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C68:PICT1
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C69:PICT0
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C6:PICT0
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C70:PICT1
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C74:PICT0
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C75:PICT1
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C76:PICT0
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C77:PICT1
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C78:PICT0
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C79:PICT1
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C7:PICT1
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C80:PICT0
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C81:PICT1
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C83:PICT0
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C84:PICT1
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C9:PICT0
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R20C0:PICL0
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R20C90:PICR0
|
|
arc: JDIB JPADDIB_PIO
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R21C0:PICL1
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
enum: PIOC.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOC.HYSTERESIS ON
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
enum: PIOD.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R21C90:PICR1
|
|
enum: PIOD.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOD.HYSTERESIS ON
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOB.HYSTERESIS ON
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R22C0:MIB_CIB_LR
|
|
enum: PIOC.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOD.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R22C90:MIB_CIB_LR_A
|
|
enum: PIOD.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R23C0:PICL0
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R23C90:PICR0
|
|
arc: JDIA JPADDIA_PIO
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R24C0:PICL1
|
|
enum: PIOD.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOD.HYSTERESIS ON
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R24C90:PICR1
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOA.HYSTERESIS ON
|
|
enum: PIOD.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOD.HYSTERESIS ON
|
|
enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R25C0:PICL2
|
|
enum: PIOD.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R25C90:PICR2
|
|
enum: PIOD.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R26C0:PICL0
|
|
arc: JDIB JPADDIB_PIO
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R26C90:PICR0
|
|
arc: JDIB JPADDIB_PIO
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R27C0:PICL1_DQS0
|
|
enum: PIOC.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOC.HYSTERESIS ON
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOB.HYSTERESIS ON
|
|
enum: PIOD.BASE_TYPE OUTPUT_LVCMOS33
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R27C90:PICR1_DQS0
|
|
enum: PIOD.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOD.HYSTERESIS ON
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOB.HYSTERESIS ON
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R28C0:PICL2_DQS1
|
|
enum: PIOC.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOD.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R28C90:PICR2_DQS1
|
|
enum: PIOD.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R29C0:PICL0_DQS2
|
|
arc: JDIB JPADDIB_PIO
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R29C90:PICR0_DQS2
|
|
arc: JDIB JPADDIB_PIO
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R30C0:PICL1_DQS3
|
|
enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOB.HYSTERESIS ON
|
|
enum: PIOD.BASE_TYPE OUTPUT_LVCMOS33
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R30C90:PICR1_DQS3
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOB.HYSTERESIS ON
|
|
enum: PIOD.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOD.HYSTERESIS ON
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R31C0:PICL2
|
|
enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33
|
|
enum: PIOD.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R31C90:PICR2
|
|
enum: PIOD.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R32C0:PICL0
|
|
arc: JDIA JPADDIA_PIO
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R32C90:PICR0
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R33C0:PICL1
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOA.HYSTERESIS ON
|
|
enum: PIOD.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOD.HYSTERESIS ON
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R33C90:PICR1
|
|
enum: PIOC.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOC.HYSTERESIS ON
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
enum: PIOD.BASE_TYPE OUTPUT_LVCMOS33
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R34C0:MIB_CIB_LR
|
|
enum: PIOD.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R34C90:MIB_CIB_LR_A
|
|
enum: PIOC.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOD.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R35C0:PICL0
|
|
arc: JDIA JPADDIA_PIO
|
|
arc: JDIB JPADDIB_PIO
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R35C90:PICR0
|
|
arc: JDIB JPADDIB_PIO
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R36C0:PICL1
|
|
enum: PIOC.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOC.HYSTERESIS ON
|
|
enum: PIOD.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOD.HYSTERESIS ON
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOA.HYSTERESIS ON
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOB.HYSTERESIS ON
|
|
|
|
.tile MIB_R36C90:PICR1
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOB.HYSTERESIS ON
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
enum: PIOD.BASE_TYPE OUTPUT_LVCMOS33
|
|
enum: PIOC.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOC.HYSTERESIS ON
|
|
|
|
.tile MIB_R37C0:PICL2
|
|
enum: PIOC.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOD.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R37C90:PICR2
|
|
enum: PIOD.BASE_TYPE OUTPUT_LVCMOS33
|
|
enum: PIOC.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R38C0:PICL0
|
|
arc: JDIA JPADDIA_PIO
|
|
arc: JDIB JPADDIB_PIO
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R38C90:PICR0
|
|
arc: JDIA JPADDIA_PIO
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R39C0:PICL1_DQS0
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOA.HYSTERESIS ON
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOB.HYSTERESIS ON
|
|
enum: PIOD.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOD.HYSTERESIS ON
|
|
enum: PIOC.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOC.HYSTERESIS ON
|
|
|
|
.tile MIB_R39C90:PICR1_DQS0
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOA.HYSTERESIS ON
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
enum: PIOD.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOD.HYSTERESIS ON
|
|
enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R40C0:PICL2_DQS1
|
|
enum: PIOD.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOC.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R40C90:PICR2_DQS1
|
|
enum: PIOD.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R41C0:PICL0_DQS2
|
|
arc: JDIA JPADDIA_PIO
|
|
arc: JDIB JPADDIB_PIO
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R41C90:PICR0_DQS2
|
|
arc: JDIA JPADDIA_PIO
|
|
arc: JDIB JPADDIB_PIO
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R42C0:PICL1_DQS3
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOA.HYSTERESIS ON
|
|
enum: PIOC.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOC.HYSTERESIS ON
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOB.HYSTERESIS ON
|
|
enum: PIOD.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R42C90:PICR1_DQS3
|
|
enum: PIOD.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOD.HYSTERESIS ON
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOA.HYSTERESIS ON
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOB.HYSTERESIS ON
|
|
enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R43C0:PICL2
|
|
enum: PIOC.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOD.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R43C90:PICR2
|
|
enum: PIOD.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R44C0:PICL0
|
|
arc: JDIA JPADDIA_PIO
|
|
arc: JDIB JPADDIB_PIO
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R44C90:PICR0
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R45C0:PICL1
|
|
enum: PIOD.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOD.HYSTERESIS ON
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOA.HYSTERESIS ON
|
|
enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOB.HYSTERESIS ON
|
|
|
|
.tile MIB_R45C90:PICR1
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
enum: PIOD.BASE_TYPE OUTPUT_LVCMOS33
|
|
enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R46C0:MIB_CIB_LR
|
|
enum: PIOD.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R46C90:MIB_CIB_LR_A
|
|
enum: PIOD.BASE_TYPE OUTPUT_LVCMOS33
|
|
enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R47C0:PICL0
|
|
arc: JDIB JPADDIB_PIO
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R47C90:PICR0
|
|
arc: JDIA JPADDIA_PIO
|
|
arc: JDIB JPADDIB_PIO
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R48C0:PICL1
|
|
enum: PIOC.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOC.HYSTERESIS ON
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOB.HYSTERESIS ON
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
enum: PIOD.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOD.HYSTERESIS ON
|
|
|
|
.tile MIB_R48C90:PICR1
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOB.HYSTERESIS ON
|
|
enum: PIOC.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOC.HYSTERESIS ON
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOA.HYSTERESIS ON
|
|
enum: PIOD.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOD.HYSTERESIS ON
|
|
|
|
.tile MIB_R49C0:PICL2
|
|
enum: PIOC.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOD.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R49C90:PICR2
|
|
enum: PIOC.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOD.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R50C0:PICL0
|
|
arc: JDIA JPADDIA_PIO
|
|
arc: JDIB JPADDIB_PIO
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R50C90:PICR0
|
|
arc: JDIA JPADDIA_PIO
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R51C0:PICL1_DQS0
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOA.HYSTERESIS ON
|
|
enum: PIOC.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOC.HYSTERESIS ON
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOB.HYSTERESIS ON
|
|
enum: PIOD.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R51C90:PICR1_DQS0
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOA.HYSTERESIS ON
|
|
enum: PIOD.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOD.HYSTERESIS ON
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R52C0:PICL2_DQS1
|
|
enum: PIOC.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOD.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R52C90:PICR2_DQS1
|
|
enum: PIOD.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R53C0:PICL0_DQS2
|
|
arc: JDIB JPADDIB_PIO
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R53C90:PICR0_DQS2
|
|
arc: JDIA JPADDIA_PIO
|
|
arc: JDIB JPADDIB_PIO
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R54C0:PICL1_DQS3
|
|
enum: PIOD.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOD.HYSTERESIS ON
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOB.HYSTERESIS ON
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R54C90:PICR1_DQS3
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOA.HYSTERESIS ON
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOB.HYSTERESIS ON
|
|
enum: PIOD.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOD.HYSTERESIS ON
|
|
enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R55C0:PICL2
|
|
enum: PIOD.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R55C90:PICR2
|
|
enum: PIOD.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R56C0:PICL0
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R56C90:PICR0
|
|
arc: JDIA JPADDIA_PIO
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R57C0:PICL1
|
|
enum: PIOD.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOD.HYSTERESIS ON
|
|
enum: PIOC.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOC.HYSTERESIS ON
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R57C90:PICR1
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOA.HYSTERESIS ON
|
|
enum: PIOC.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOC.HYSTERESIS ON
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R58C0:MIB_CIB_LR
|
|
enum: PIOD.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOC.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R58C40:CMUX_LL_0
|
|
arc: G_DCS1CLK0 G_VPFN0000
|
|
arc: G_LLPCLK0 G_VPFS0000
|
|
|
|
.tile MIB_R58C41:CMUX_LR_0
|
|
arc: G_DCS1CLK1 G_VPFN0000
|
|
arc: G_LRPCLK0 G_VPFS0000
|
|
|
|
.tile MIB_R58C90:MIB_CIB_LR_A
|
|
enum: PIOC.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R59C0:PICL0
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R59C90:PICR0
|
|
arc: JDIB JPADDIB_PIO
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R60C0:PICL1
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
enum: PIOD.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R60C90:PICR1
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOB.HYSTERESIS ON
|
|
enum: PIOD.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOD.HYSTERESIS ON
|
|
enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R61C0:PICL2
|
|
enum: PIOD.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R61C90:PICR2
|
|
enum: PIOD.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R62C0:PICL0
|
|
arc: JDIA JPADDIA_PIO
|
|
arc: JDIB JPADDIB_PIO
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R62C90:PICR0
|
|
arc: JDIA JPADDIA_PIO
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R63C0:PICL1_DQS0
|
|
enum: PIOC.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOC.HYSTERESIS ON
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOA.HYSTERESIS ON
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOB.HYSTERESIS ON
|
|
enum: PIOD.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R63C90:PICR1_DQS0
|
|
enum: PIOC.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOC.HYSTERESIS ON
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOA.HYSTERESIS ON
|
|
enum: PIOD.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOD.HYSTERESIS ON
|
|
|
|
.tile MIB_R64C0:PICL2_DQS1
|
|
enum: PIOC.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOD.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R64C90:PICR2_DQS1
|
|
enum: PIOC.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOD.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R65C0:PICL0_DQS2
|
|
arc: JDIA JPADDIA_PIO
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R66C0:PICL1_DQS3
|
|
enum: PIOC.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOC.HYSTERESIS ON
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOA.HYSTERESIS ON
|
|
enum: PIOD.BASE_TYPE OUTPUT_LVCMOS33
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R66C90:PICR1_DQS3
|
|
enum: PIOD.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOD.HYSTERESIS ON
|
|
enum: PIOC.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOC.HYSTERESIS ON
|
|
|
|
.tile MIB_R67C0:PICL2
|
|
enum: PIOC.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOD.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R67C90:PICR2
|
|
enum: PIOD.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOC.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R71C11:PICB0
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R71C12:PICB1
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOB.HYSTERESIS ON
|
|
|
|
.tile MIB_R71C13:PICB0
|
|
arc: JDIA JPADDIA_PIO
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOA.HYSTERESIS ON
|
|
|
|
.tile MIB_R71C14:PICB1
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R71C15:PICB0
|
|
arc: JDIA JPADDIA_PIO
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOA.HYSTERESIS ON
|
|
|
|
.tile MIB_R71C16:PICB1
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R71C18:SPICB0
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R71C1:BANKREF6
|
|
enum: BANK.VCCIO 3V3
|
|
|
|
.tile MIB_R71C3:BANKREF8
|
|
enum: BANK.VCCIO 3V3
|
|
|
|
.tile MIB_R71C4:EFB0_PICB0
|
|
arc: JDIA JPADDIA_PIO
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOA.HYSTERESIS ON
|
|
unknown: F54B1
|
|
unknown: F56B1
|
|
unknown: F82B1
|
|
unknown: F94B1
|
|
|
|
.tile MIB_R71C5:EFB1_PICB1
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOB.HYSTERESIS ON
|
|
|
|
.tile MIB_R71C6:EFB2_PICB0
|
|
arc: JDIA JPADDIA_PIO
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOA.HYSTERESIS ON
|
|
|
|
.tile MIB_R71C7:EFB3_PICB1
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOB.HYSTERESIS ON
|
|
|
|
.tile MIB_R71C89:BANKREF3
|
|
enum: BANK.VCCIO 3V3
|
|
|
|
.tile R11C50:PLC2
|
|
arc: N1_V02N0701 H06W0203
|
|
|
|
.tile R11C53:PLC2
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
|
|
.tile R11C59:PLC2
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
|
|
.tile R11C65:PLC2
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
|
|
.tile R11C71:PLC2
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
|
|
.tile R11C77:PLC2
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
|
|
.tile R11C83:PLC2
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
|
|
.tile R13C15:PLC2
|
|
arc: S3_V06S0103 N3_V06S0003
|
|
|
|
.tile R13C16:PLC2
|
|
arc: S3_V06S0103 N3_V06S0103
|
|
|
|
.tile R13C17:PLC2
|
|
arc: S3_V06S0103 N3_V06S0103
|
|
|
|
.tile R13C18:PLC2
|
|
arc: S3_V06S0303 N3_V06S0203
|
|
|
|
.tile R13C23:PLC2
|
|
arc: S3_V06S0003 N3_V06S0003
|
|
|
|
.tile R13C24:PLC2
|
|
arc: S3_V06S0003 N3_V06S0003
|
|
|
|
.tile R13C26:PLC2
|
|
arc: S3_V06S0203 N3_V06S0203
|
|
|
|
.tile R13C27:PLC2
|
|
arc: S3_V06S0003 N3_V06S0303
|
|
arc: S3_V06S0203 N3_V06S0103
|
|
arc: S3_V06S0303 N3_V06S0203
|
|
|
|
.tile R13C33:PLC2
|
|
arc: S3_V06S0103 N3_V06S0103
|
|
|
|
.tile R13C34:PLC2
|
|
arc: S3_V06S0003 N3_V06S0003
|
|
arc: S3_V06S0103 N3_V06S0103
|
|
arc: S3_V06S0203 N3_V06S0203
|
|
|
|
.tile R13C35:PLC2
|
|
arc: S3_V06S0003 N3_V06S0303
|
|
arc: S3_V06S0203 N3_V06S0103
|
|
|
|
.tile R13C36:PLC2
|
|
arc: S3_V06S0103 N3_V06S0003
|
|
arc: S3_V06S0203 N3_V06S0103
|
|
|
|
.tile R13C37:PLC2
|
|
arc: S3_V06S0103 N3_V06S0003
|
|
arc: S3_V06S0203 N3_V06S0103
|
|
|
|
.tile R13C38:PLC2
|
|
arc: S3_V06S0303 N3_V06S0303
|
|
|
|
.tile R13C39:PLC2
|
|
arc: S3_V06S0003 N3_V06S0303
|
|
arc: S3_V06S0203 N3_V06S0103
|
|
arc: S3_V06S0303 N3_V06S0203
|
|
|
|
.tile R13C40:PLC2
|
|
arc: S3_V06S0003 N3_V06S0303
|
|
arc: S3_V06S0203 N3_V06S0203
|
|
|
|
.tile R13C41:PLC2
|
|
arc: S3_V06S0203 N3_V06S0103
|
|
|
|
.tile R13C42:PLC2
|
|
arc: S3_V06S0103 N3_V06S0003
|
|
arc: S3_V06S0203 N3_V06S0103
|
|
arc: S3_V06S0303 N3_V06S0203
|
|
|
|
.tile R13C43:PLC2
|
|
arc: S3_V06S0103 N3_V06S0003
|
|
arc: S3_V06S0303 N3_V06S0203
|
|
|
|
.tile R13C44:PLC2
|
|
arc: S3_V06S0103 N3_V06S0103
|
|
|
|
.tile R13C45:PLC2
|
|
arc: E3_H06E0203 N3_V06S0203
|
|
arc: S3_V06S0003 N3_V06S0003
|
|
arc: S3_V06S0203 N3_V06S0203
|
|
arc: S3_V06S0303 N3_V06S0303
|
|
|
|
.tile R13C46:PLC2
|
|
arc: N3_V06N0303 S3_V06N0203
|
|
arc: S3_V06S0103 N3_V06S0003
|
|
|
|
.tile R13C47:PLC2
|
|
arc: S3_V06S0203 N3_V06S0103
|
|
|
|
.tile R13C48:PLC2
|
|
arc: S3_V06S0003 N3_V06S0003
|
|
arc: S3_V06S0103 N3_V06S0103
|
|
arc: S3_V06S0203 H06E0203
|
|
|
|
.tile R13C49:PLC2
|
|
arc: S3_V06S0003 N3_V06S0003
|
|
|
|
.tile R13C50:PLC2
|
|
arc: S3_V06S0003 N3_V06S0003
|
|
arc: S3_V06S0103 N3_V06S0103
|
|
|
|
.tile R13C51:PLC2
|
|
arc: S1_V02S0701 W3_H06E0203
|
|
arc: S3_V06S0103 N3_V06S0103
|
|
arc: S3_V06S0203 N3_V06S0203
|
|
|
|
.tile R13C52:PLC2
|
|
arc: S3_V06S0203 N3_V06S0103
|
|
|
|
.tile R13C53:PLC2
|
|
arc: S3_V06S0103 N3_V06S0003
|
|
|
|
.tile R13C54:PLC2
|
|
arc: S3_V06S0103 N3_V06S0003
|
|
arc: S3_V06S0303 N3_V06S0203
|
|
|
|
.tile R13C56:PLC2
|
|
arc: N3_V06N0203 S3_V06N0103
|
|
|
|
.tile R13C60:PLC2
|
|
arc: S3_V06S0003 N3_V06S0303
|
|
|
|
.tile R13C61:PLC2
|
|
arc: S3_V06S0103 N3_V06S0103
|
|
|
|
.tile R13C62:PLC2
|
|
arc: S3_V06S0203 N3_V06S0203
|
|
|
|
.tile R13C63:PLC2
|
|
arc: S3_V06S0103 N3_V06S0003
|
|
|
|
.tile R14C13:PLC2
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
|
|
.tile R14C19:PLC2
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
|
|
.tile R14C25:PLC2
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
|
|
.tile R14C31:PLC2
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
|
|
.tile R14C34:PLC2
|
|
arc: N3_V06N0303 S3_V06N0303
|
|
|
|
.tile R14C35:PLC2
|
|
arc: N3_V06N0203 S3_V06N0103
|
|
|
|
.tile R14C37:PLC2
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
|
|
.tile R14C43:PLC2
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
|
|
.tile R14C49:PLC2
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
|
|
.tile R14C51:PLC2
|
|
arc: S3_V06S0103 N3_V06S0003
|
|
|
|
.tile R14C55:PLC2
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
|
|
.tile R14C59:PLC2
|
|
arc: S3_V06S0003 E3_H06W0003
|
|
|
|
.tile R14C61:PLC2
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
|
|
.tile R14C64:PLC2
|
|
arc: S3_V06S0203 H06E0203
|
|
|
|
.tile R14C65:PLC2
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
|
|
.tile R14C71:PLC2
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
|
|
.tile R14C77:PLC2
|
|
arc: N3_V06N0203 S3_V06N0203
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
|
|
.tile R14C7:PLC2
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
|
|
.tile R14C83:PLC2
|
|
arc: N3_V06N0203 S3_V06N0203
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
|
|
.tile R14C88:PLC2
|
|
arc: E1_H02E0701 S3_V06N0203
|
|
|
|
.tile R15C13:PLC2
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arc: N3_V06N0103 S3_V06N0003
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.tile R15C16:PLC2
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arc: N3_V06N0203 S3_V06N0203
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.tile R15C18:PLC2
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arc: N3_V06N0103 S3_V06N0003
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.tile R15C19:PLC2
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arc: N3_V06N0303 S3_V06N0303
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.tile R15C22:PLC2
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arc: N3_V06N0103 S3_V06N0003
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.tile R15C23:PLC2
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arc: N3_V06N0203 S3_V06N0103
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.tile R15C25:PLC2
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arc: N3_V06N0003 S3_V06N0003
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.tile R15C27:PLC2
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arc: N3_V06N0103 S3_V06N0003
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.tile R15C31:PLC2
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arc: N3_V06N0203 S3_V06N0103
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.tile R15C41:PLC2
|
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arc: N3_V06N0203 S3_V06N0103
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.tile R15C45:PLC2
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arc: S3_V06S0103 N3_V06S0103
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.tile R15C46:PLC2
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arc: S3_V06S0003 N3_V06S0003
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.tile R15C48:PLC2
|
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arc: N3_V06N0303 S3_V06N0203
|
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arc: S3_V06S0303 N3_V06S0203
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.tile R15C49:PLC2
|
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arc: S3_V06S0103 N3_V06S0103
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.tile R15C51:PLC2
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arc: S3_V06S0103 N3_V06S0103
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arc: S3_V06S0203 N1_V02S0701
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.tile R15C52:PLC2
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arc: S3_V06S0203 N3_V06S0203
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.tile R15C53:PLC2
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arc: N3_V06N0303 S3_V06N0203
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.tile R15C58:PLC2
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arc: N3_V06N0203 S3_V06N0203
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.tile R15C5:PLC2
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arc: N3_V06N0303 S3_V06N0203
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.tile R15C65:PLC2
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arc: N3_V06N0203 S3_V06N0103
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.tile R15C67:PLC2
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arc: N3_V06N0103 S3_V06N0103
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.tile R15C68:PLC2
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arc: N3_V06N0303 S3_V06N0303
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.tile R15C69:PLC2
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arc: N3_V06N0103 S3_V06N0103
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.tile R15C6:PLC2
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arc: N3_V06N0203 S3_V06N0203
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.tile R15C73:PLC2
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arc: N3_V06N0103 S3_V06N0103
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.tile R15C75:PLC2
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arc: N3_V06N0303 S3_V06N0203
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.tile R15C80:PLC2
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arc: N3_V06N0303 S3_V06N0303
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.tile R15C83:PLC2
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arc: N3_V06N0203 S3_V06N0203
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.tile R15C8:PLC2
|
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arc: N3_V06N0103 S3_V06N0103
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.tile R16C13:PLC2
|
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arc: E3_H06E0003 W3_H06E0003
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.tile R16C17:PLC2
|
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arc: S3_V06S0203 E3_H06W0203
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.tile R16C19:PLC2
|
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arc: E3_H06E0103 W3_H06E0003
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.tile R16C23:PLC2
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arc: W3_H06W0203 E3_H06W0203
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.tile R16C25:PLC2
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arc: E3_H06E0203 W3_H06E0103
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.tile R16C29:PLC2
|
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arc: W3_H06W0203 E3_H06W0203
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.tile R16C31:PLC2
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arc: E3_H06E0203 W3_H06E0203
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.tile R16C35:PLC2
|
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arc: W3_H06W0203 E3_H06W0203
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.tile R16C37:PLC2
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arc: S3_V06S0203 W3_H06E0203
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.tile R16C41:PLC2
|
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arc: W3_H06W0203 E3_H06W0103
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.tile R16C47:PLC2
|
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arc: W3_H06W0103 E3_H06W0103
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.tile R16C53:PLC2
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arc: W3_H06W0103 E3_H06W0103
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.tile R16C59:PLC2
|
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arc: W3_H06W0103 E3_H06W0103
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.tile R16C65:PLC2
|
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arc: W3_H06W0103 E3_H06W0003
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.tile R16C71:PLC2
|
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arc: W3_H06W0003 E3_H06W0003
|
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.tile R16C77:PLC2
|
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arc: W3_H06W0003 E3_H06W0003
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.tile R16C7:PLC2
|
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arc: E3_H06E0003 W3_H06E0303
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.tile R16C83:PLC2
|
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arc: W3_H06W0003 E3_H06W0303
|
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.tile R17C53:PLC2
|
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arc: S3_V06S0103 E3_H06W0103
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.tile R17C59:PLC2
|
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arc: W3_H06W0103 E3_H06W0003
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.tile R17C65:PLC2
|
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arc: W3_H06W0003 E3_H06W0003
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.tile R17C71:PLC2
|
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arc: W3_H06W0003 E3_H06W0303
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.tile R17C77:PLC2
|
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arc: W3_H06W0303 E3_H06W0303
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.tile R17C83:PLC2
|
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arc: W3_H06W0303 E3_H06W0303
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.tile R18C41:PLC2
|
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arc: S1_V02S0501 V01N0101
|
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.tile R18C42:PLC2
|
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arc: S1_V02S0301 S3_V06N0003
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.tile R19C13:PLC2
|
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arc: E3_H06E0103 W3_H06E0003
|
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.tile R19C14:PLC2
|
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arc: E3_H06E0203 W3_H06E0103
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.tile R19C15:PLC2
|
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arc: S3_V06S0103 N3_V06S0103
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.tile R19C16:PLC2
|
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arc: S3_V06S0203 N3_V06S0103
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.tile R19C17:PLC2
|
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arc: S3_V06S0103 N3_V06S0103
|
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.tile R19C18:PLC2
|
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arc: S3_V06S0303 N3_V06S0303
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.tile R19C19:PLC2
|
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arc: E3_H06E0203 W3_H06E0103
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.tile R19C20:PLC2
|
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arc: E3_H06E0203 W3_H06E0203
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.tile R19C23:PLC2
|
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arc: S3_V06S0103 N3_V06S0003
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.tile R19C24:PLC2
|
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arc: S3_V06S0003 N3_V06S0003
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.tile R19C25:PLC2
|
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arc: E3_H06E0203 W3_H06E0203
|
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.tile R19C26:PLC2
|
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arc: E3_H06E0203 W3_H06E0203
|
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arc: S3_V06S0203 N3_V06S0203
|
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.tile R19C27:PLC2
|
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arc: S3_V06S0103 N3_V06S0003
|
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arc: S3_V06S0203 N3_V06S0203
|
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arc: S3_V06S0303 N3_V06S0303
|
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.tile R19C2:PLC2
|
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arc: E3_H06E0003 H01E0001
|
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arc: W1_H02W0701 S1_V02N0701
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.tile R19C31:PLC2
|
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arc: E3_H06E0203 W3_H06E0203
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.tile R19C32:PLC2
|
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arc: E3_H06E0303 W3_H06E0203
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.tile R19C33:PLC2
|
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arc: S3_V06S0203 N3_V06S0103
|
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.tile R19C34:PLC2
|
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arc: S3_V06S0003 N3_V06S0003
|
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arc: S3_V06S0103 N3_V06S0103
|
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arc: S3_V06S0203 N3_V06S0203
|
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.tile R19C35:PLC2
|
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arc: S3_V06S0103 N3_V06S0003
|
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arc: S3_V06S0303 N3_V06S0203
|
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.tile R19C36:PLC2
|
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arc: S3_V06S0103 N3_V06S0103
|
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arc: S3_V06S0203 N3_V06S0203
|
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.tile R19C37:PLC2
|
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arc: E3_H06E0303 W3_H06E0203
|
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arc: S3_V06S0103 N3_V06S0103
|
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arc: S3_V06S0203 W3_H06E0203
|
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arc: S3_V06S0303 N3_V06S0203
|
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.tile R19C38:PLC2
|
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arc: E3_H06E0003 W3_H06E0303
|
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arc: E3_H06E0103 S3_V06N0103
|
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arc: S3_V06S0303 N3_V06S0303
|
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.tile R19C39:PLC2
|
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arc: E3_H06E0203 N3_V06S0203
|
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arc: S3_V06S0003 N3_V06S0303
|
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arc: S3_V06S0103 N3_V06S0003
|
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arc: S3_V06S0303 N3_V06S0203
|
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.tile R19C40:PLC2
|
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arc: S1_V02S0001 N3_V06S0003
|
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arc: S3_V06S0103 N3_V06S0003
|
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arc: S3_V06S0303 N3_V06S0203
|
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.tile R19C41:PLC2
|
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arc: N1_V01N0101 N3_V06S0203
|
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arc: S1_V02S0001 H06E0003
|
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arc: S3_V06S0303 N3_V06S0203
|
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.tile R19C42:PLC2
|
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arc: E1_H02E0201 N3_V06S0103
|
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arc: S1_V02S0101 N3_V06S0103
|
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arc: S1_V02S0401 N3_V06S0203
|
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arc: S1_V02S0701 H06E0203
|
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arc: S3_V06S0003 N3_V06S0303
|
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arc: S3_V06S0103 N3_V06S0103
|
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arc: S3_V06S0203 N3_V06S0103
|
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arc: S3_V06S0303 N3_V06S0203
|
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arc: V01S0000 N3_V06S0103
|
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.tile R19C43:PLC2
|
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arc: E3_H06E0003 W3_H06E0303
|
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arc: S1_V02S0201 S3_V06N0103
|
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arc: S3_V06S0003 N3_V06S0303
|
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arc: S3_V06S0203 N3_V06S0103
|
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arc: S3_V06S0303 W3_H06E0303
|
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arc: V01S0100 S3_V06N0303
|
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|
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.tile R19C44:PLC2
|
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arc: E3_H06E0203 W3_H06E0103
|
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arc: S1_V02S0201 W1_H02E0201
|
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arc: S3_V06S0003 W3_H06E0003
|
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arc: S3_V06S0103 N3_V06S0103
|
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|
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.tile R19C45:PLC2
|
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arc: S3_V06S0003 N3_V06S0003
|
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arc: S3_V06S0303 N3_V06S0203
|
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arc: V01S0100 N3_V06S0303
|
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|
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.tile R19C46:PLC2
|
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arc: N3_V06N0203 S3_V06N0203
|
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arc: S3_V06S0003 H06E0003
|
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arc: S3_V06S0203 N3_V06S0103
|
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|
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.tile R19C47:PLC2
|
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arc: S1_V02S0701 N3_V06S0203
|
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arc: S3_V06S0203 N3_V06S0203
|
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|
|
.tile R19C48:PLC2
|
|
arc: E1_H02E0201 N3_V06S0103
|
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arc: S1_V02S0401 N3_V06S0203
|
|
arc: S3_V06S0003 N3_V06S0003
|
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arc: S3_V06S0103 N3_V06S0103
|
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arc: S3_V06S0303 N3_V06S0203
|
|
|
|
.tile R19C49:PLC2
|
|
arc: S1_V02S0001 W3_H06E0003
|
|
arc: S3_V06S0003 W3_H06E0003
|
|
arc: S3_V06S0103 N3_V06S0003
|
|
|
|
.tile R19C50:PLC2
|
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arc: E3_H06E0303 W3_H06E0203
|
|
arc: S1_V02S0001 N3_V06S0003
|
|
arc: S1_V02S0101 N3_V06S0103
|
|
arc: S1_V02S0201 W1_H02E0201
|
|
arc: S3_V06S0103 N3_V06S0003
|
|
|
|
.tile R19C51:PLC2
|
|
arc: S3_V06S0103 N3_V06S0103
|
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arc: S3_V06S0203 N3_V06S0203
|
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|
|
.tile R19C52:PLC2
|
|
arc: S1_V02S0401 N3_V06S0203
|
|
arc: S3_V06S0203 E1_H01W0000
|
|
|
|
.tile R19C53:PLC2
|
|
arc: H01W0000 E3_H06W0103
|
|
arc: S3_V06S0103 N3_V06S0103
|
|
|
|
.tile R19C54:PLC2
|
|
arc: S3_V06S0203 N3_V06S0103
|
|
arc: S3_V06S0303 N3_V06S0303
|
|
|
|
.tile R19C56:PLC2
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
arc: N3_V06N0103 S3_V06N0103
|
|
|
|
.tile R19C59:PLC2
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
|
|
.tile R19C60:PLC2
|
|
arc: S3_V06S0103 N3_V06S0003
|
|
|
|
.tile R19C61:PLC2
|
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arc: S3_V06S0103 N3_V06S0103
|
|
|
|
.tile R19C62:PLC2
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: S3_V06S0203 N3_V06S0203
|
|
|
|
.tile R19C63:PLC2
|
|
arc: S3_V06S0203 N3_V06S0103
|
|
|
|
.tile R19C65:PLC2
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
|
|
.tile R19C68:PLC2
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
|
|
.tile R19C71:PLC2
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
|
|
.tile R19C74:PLC2
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
|
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.tile R19C77:PLC2
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
|
|
.tile R19C7:PLC2
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
|
|
.tile R19C80:PLC2
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
|
|
.tile R19C83:PLC2
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
|
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.tile R19C86:PLC2
|
|
arc: E3_H06E0203 W3_H06E0103
|
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|
|
.tile R19C8:PLC2
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
|
|
.tile R20C10:PLC2
|
|
arc: H01W0000 E3_H06W0103
|
|
|
|
.tile R20C16:PLC2
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
|
|
.tile R20C22:PLC2
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
|
|
.tile R20C28:PLC2
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
|
|
.tile R20C34:PLC2
|
|
arc: N3_V06N0303 S3_V06N0203
|
|
arc: W3_H06W0303 E3_H06W0203
|
|
|
|
.tile R20C35:PLC2
|
|
arc: E3_H06E0003 S3_V06N0003
|
|
arc: N3_V06N0103 S3_V06N0103
|
|
|
|
.tile R20C3:PLC2
|
|
arc: W1_H02W0501 V02N0501
|
|
arc: W1_H02W0701 E3_H06W0203
|
|
|
|
.tile R20C40:PLC2
|
|
arc: W3_H06W0203 E3_H06W0203
|
|
|
|
.tile R20C41:PLC2
|
|
arc: E1_H02E0001 V02S0001
|
|
arc: E1_H02E0201 S1_V02N0201
|
|
arc: E1_H02E0601 V02N0601
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: S1_V02S0001 N1_V02S0501
|
|
|
|
.tile R20C42:PLC2
|
|
arc: E1_H02E0401 N1_V01S0000
|
|
arc: E1_H02E0701 S1_V02N0701
|
|
arc: H00R0100 V02S0701
|
|
arc: S1_V02S0001 E1_H01W0000
|
|
arc: V00B0000 H02E0601
|
|
arc: V00T0000 H02E0201
|
|
arc: A2 V00T0000
|
|
arc: A3 V01N0101
|
|
arc: B2 V01N0001
|
|
arc: B3 N1_V02S0301
|
|
arc: C2 V02S0401
|
|
arc: C3 H00R0100
|
|
arc: C4 Q4
|
|
arc: CE2 V02N0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D2 V00B0100
|
|
arc: D3 V02N0201
|
|
arc: D4 H02E0201
|
|
arc: E1_H01E0001 F3
|
|
arc: E1_H02E0201 F2
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: M4 V00B0000
|
|
arc: M5 H02E0001
|
|
arc: MUXCLK2 CLK0
|
|
arc: S1_V02S0601 F4
|
|
arc: V00B0100 Q5
|
|
arc: V01S0000 F4
|
|
word: SLICEC.K0.INIT 0000111111110000
|
|
word: SLICEB.K1.INIT 1000010000100001
|
|
word: SLICEB.K0.INIT 1001000000001001
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R20C43:PLC2
|
|
arc: E1_H02E0001 S1_V02N0001
|
|
arc: E1_H02E0201 S1_V02N0201
|
|
arc: H00R0000 H02E0401
|
|
arc: V00B0000 V02S0201
|
|
arc: V00T0000 S1_V02N0401
|
|
arc: V00T0100 S1_V02N0701
|
|
arc: A0 H01E0001
|
|
arc: A3 H02E0701
|
|
arc: B0 H01W0100
|
|
arc: B1 Q1
|
|
arc: B3 E1_H02W0101
|
|
arc: C0 H00R0100
|
|
arc: C3 N1_V01S0100
|
|
arc: CE0 H00L0100
|
|
arc: CE1 H00L0100
|
|
arc: CE3 H00L0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H02E0201
|
|
arc: D1 V00B0100
|
|
arc: D3 V02N0001
|
|
arc: E1_H01E0001 Q3
|
|
arc: E3_H06E0003 Q3
|
|
arc: F0 F5A_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: H00L0100 F3
|
|
arc: H00R0100 Q7
|
|
arc: H01W0000 Q7
|
|
arc: H01W0100 Q1
|
|
arc: LSR0 V00B0000
|
|
arc: LSR1 V00T0000
|
|
arc: M0 V00T0100
|
|
arc: M1 H02W0001
|
|
arc: M3 H00R0000
|
|
arc: M7 H02W0201
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR3 LSR0
|
|
arc: S1_V02S0101 Q3
|
|
arc: S1_V02S0501 Q7
|
|
arc: V00B0100 Q7
|
|
arc: V01S0000 F0
|
|
arc: V01S0100 Q1
|
|
word: SLICEB.K1.INIT 1111100011110000
|
|
word: SLICEA.K0.INIT 1010100000000000
|
|
word: SLICEA.K1.INIT 1111111111001100
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
|
|
.tile R20C44:PLC2
|
|
arc: H00R0000 S1_V02N0401
|
|
arc: S1_V02S0601 H01E0001
|
|
arc: V00B0100 S1_V02N0301
|
|
arc: W1_H02W0001 S1_V02N0001
|
|
arc: W1_H02W0201 V06N0103
|
|
arc: A2 V02N0501
|
|
arc: B0 V02N0301
|
|
arc: B2 V02N0101
|
|
arc: C0 S1_V02N0601
|
|
arc: C1 S1_V02N0601
|
|
arc: C2 S1_V02N0601
|
|
arc: C3 S1_V02N0601
|
|
arc: D0 H02E0001
|
|
arc: D1 V02N0001
|
|
arc: D2 H02E0201
|
|
arc: D3 V02N0201
|
|
arc: E1_H01E0001 F1
|
|
arc: F0 F5A_SLICE
|
|
arc: F1 FXA_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: M0 V00B0100
|
|
arc: M1 H00R0000
|
|
arc: M2 V00B0100
|
|
word: SLICEB.K0.INIT 1100000010000000
|
|
word: SLICEA.K1.INIT 1111000000000000
|
|
word: SLICEA.K0.INIT 1100000000000000
|
|
word: SLICEB.K1.INIT 1111000000000000
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
|
|
.tile R20C45:PLC2
|
|
arc: E1_H02E0601 H01E0001
|
|
arc: S1_V02S0101 N1_V01S0100
|
|
arc: S3_V06S0103 N1_V01S0100
|
|
arc: S3_V06S0303 N1_V01S0100
|
|
arc: V00B0000 V02N0001
|
|
arc: V00B0100 V02N0101
|
|
arc: W1_H02W0101 V02N0101
|
|
arc: A1 S1_V02N0701
|
|
arc: B1 S1_V02N0101
|
|
arc: C0 S1_V02N0401
|
|
arc: C1 H02W0601
|
|
arc: D1 V00B0100
|
|
arc: F0 F5A_SLICE
|
|
arc: M0 V00B0000
|
|
arc: S1_V02S0001 F0
|
|
word: SLICEA.K1.INIT 0000101100001111
|
|
word: SLICEA.K0.INIT 0000111100001111
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
|
|
.tile R20C46:PLC2
|
|
arc: S1_V02S0301 H06E0003
|
|
arc: S1_V02S0401 S3_V06N0203
|
|
arc: V01S0100 S3_V06N0303
|
|
arc: W1_H02W0601 S3_V06N0303
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
arc: A0 V02N0501
|
|
arc: B0 V02N0101
|
|
arc: C0 V02N0401
|
|
arc: D0 V02N0001
|
|
arc: F0 F5A_SLICE
|
|
arc: M0 H02E0601
|
|
arc: S1_V02S0201 F0
|
|
word: SLICEA.K1.INIT 1111111111111111
|
|
word: SLICEA.K0.INIT 1110101010101010
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
|
|
.tile R20C47:PLC2
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
|
|
.tile R20C49:PLC2
|
|
arc: S1_V02S0701 S3_V06N0203
|
|
|
|
.tile R20C50:PLC2
|
|
arc: E3_H06E0303 S3_V06N0303
|
|
arc: S1_V02S0101 H06W0103
|
|
|
|
.tile R20C51:PLC2
|
|
arc: S1_V02S0101 N3_V06S0103
|
|
arc: S1_V02S0701 V01N0101
|
|
|
|
.tile R20C52:PLC2
|
|
arc: W3_H06W0103 S3_V06N0103
|
|
|
|
.tile R20C53:PLC2
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: W3_H06W0103 S3_V06N0103
|
|
|
|
.tile R20C56:PLC2
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
|
|
.tile R20C59:PLC2
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: S3_V06S0003 N3_V06S0003
|
|
|
|
.tile R20C62:PLC2
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
|
|
.tile R20C64:PLC2
|
|
arc: S3_V06S0303 N3_V06S0203
|
|
|
|
.tile R20C65:PLC2
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: S3_V06S0103 E3_H06W0103
|
|
|
|
.tile R20C68:PLC2
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
|
|
.tile R20C71:PLC2
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
|
|
.tile R20C74:PLC2
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
|
|
.tile R20C77:PLC2
|
|
arc: N3_V06N0203 W3_H06E0203
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
|
|
.tile R20C80:PLC2
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
|
|
.tile R20C83:PLC2
|
|
arc: N3_V06N0203 H06E0203
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
|
|
.tile R20C88:PLC2
|
|
arc: N3_V06N0203 V01N0001
|
|
|
|
.tile R20C9:PLC2
|
|
arc: W3_H06W0203 E1_H01W0000
|
|
|
|
.tile R21C11:PLC2
|
|
arc: W3_H06W0303 E3_H06W0203
|
|
|
|
.tile R21C13:PLC2
|
|
arc: N3_V06N0003 E3_H06W0003
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
|
|
.tile R21C14:PLC2
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
arc: W3_H06W0203 E3_H06W0203
|
|
|
|
.tile R21C16:PLC2
|
|
arc: N3_V06N0203 E3_H06W0203
|
|
|
|
.tile R21C17:PLC2
|
|
arc: W3_H06W0203 S3_V06N0203
|
|
|
|
.tile R21C18:PLC2
|
|
arc: N3_V06N0003 E3_H06W0003
|
|
|
|
.tile R21C19:PLC2
|
|
arc: N3_V06N0303 H06W0303
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
|
|
.tile R21C20:PLC2
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
arc: W3_H06W0203 E3_H06W0203
|
|
|
|
.tile R21C22:PLC2
|
|
arc: N3_V06N0003 E3_H06W0003
|
|
arc: W3_H06W0203 E3_H06W0203
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
|
|
.tile R21C23:PLC2
|
|
arc: E3_H06E0103 S3_V06N0103
|
|
arc: N3_V06N0103 E3_H06W0103
|
|
|
|
.tile R21C24:PLC2
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
|
|
.tile R21C25:PLC2
|
|
arc: N3_V06N0003 E3_H06W0003
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
arc: W3_H06W0303 E3_H06W0203
|
|
|
|
.tile R21C26:PLC2
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
arc: W3_H06W0203 E3_H06W0203
|
|
|
|
.tile R21C27:PLC2
|
|
arc: N3_V06N0003 S3_V06N0003
|
|
|
|
.tile R21C28:PLC2
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
arc: W3_H06W0203 E3_H06W0203
|
|
arc: W3_H06W0303 S3_V06N0303
|
|
|
|
.tile R21C29:PLC2
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
|
|
.tile R21C2:PLC2
|
|
arc: N1_V02N0701 E3_H06W0203
|
|
|
|
.tile R21C30:PLC2
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
|
|
.tile R21C31:PLC2
|
|
arc: N3_V06N0103 S3_V06N0003
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
arc: W3_H06W0303 E3_H06W0203
|
|
|
|
.tile R21C32:PLC2
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
|
|
.tile R21C34:PLC2
|
|
arc: W3_H06W0003 S3_V06N0003
|
|
arc: W3_H06W0203 S3_V06N0203
|
|
|
|
.tile R21C35:PLC2
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
arc: W3_H06W0103 S3_V06N0103
|
|
|
|
.tile R21C36:PLC2
|
|
arc: W3_H06W0003 S3_V06N0003
|
|
|
|
.tile R21C37:PLC2
|
|
arc: W3_H06W0003 S3_V06N0003
|
|
arc: W3_H06W0103 S3_V06N0103
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
|
|
.tile R21C38:PLC2
|
|
arc: E1_H02E0001 S1_V02N0001
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
arc: W3_H06W0103 S3_V06N0103
|
|
|
|
.tile R21C39:PLC2
|
|
arc: E1_H02E0001 S1_V02N0001
|
|
arc: E1_H02E0301 S1_V02N0301
|
|
arc: H00L0000 H02W0001
|
|
arc: H00R0000 V02N0601
|
|
arc: H00R0100 H02W0501
|
|
arc: S1_V02S0001 H02W0001
|
|
arc: V00T0000 E1_H02W0001
|
|
arc: A0 V02N0701
|
|
arc: A2 S1_V02N0501
|
|
arc: A3 V02N0701
|
|
arc: B2 S1_V02N0101
|
|
arc: B3 Q3
|
|
arc: C2 H00L0100
|
|
arc: C3 H00L0000
|
|
arc: CE0 S1_V02N0201
|
|
arc: CE1 S1_V02N0201
|
|
arc: CE3 S1_V02N0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 Q0
|
|
arc: D2 V00B0100
|
|
arc: D3 V01S0100
|
|
arc: E1_H02E0101 F3
|
|
arc: E1_H02E0201 F2
|
|
arc: F0 F0_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: H00L0100 Q1
|
|
arc: M0 E1_H02W0601
|
|
arc: M1 H02E0001
|
|
arc: M2 V00T0000
|
|
arc: M3 H00R0000
|
|
arc: M7 H00R0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: S1_V02S0201 F0
|
|
arc: V00B0100 Q7
|
|
arc: V01S0100 Q2
|
|
word: SLICEB.K1.INIT 1001000000001001
|
|
word: SLICEB.K0.INIT 1000001001000001
|
|
word: SLICEA.K0.INIT 0101010110101010
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
|
|
.tile R21C3:PLC2
|
|
arc: N1_V02N0501 E1_H02W0501
|
|
|
|
.tile R21C40:PLC2
|
|
arc: E1_H02E0001 S3_V06N0003
|
|
arc: E1_H02E0301 V02N0301
|
|
arc: E1_H02E0501 V02N0501
|
|
arc: E1_H02E0601 S1_V02N0601
|
|
arc: H00R0000 S1_V02N0401
|
|
arc: S1_V02S0101 N1_V02S0001
|
|
arc: S1_V02S0201 E1_H01W0000
|
|
arc: S1_V02S0401 E3_H06W0203
|
|
arc: W1_H02W0001 N1_V02S0001
|
|
arc: W1_H02W0501 S1_V02N0501
|
|
arc: A0 V02N0501
|
|
arc: A1 V02N0501
|
|
arc: A2 V02N0501
|
|
arc: A3 H02W0701
|
|
arc: A6 H00L0000
|
|
arc: A7 H00L0000
|
|
arc: B0 V00T0000
|
|
arc: B3 H01W0100
|
|
arc: B6 H02W0301
|
|
arc: B7 V01S0000
|
|
arc: C0 H00L0100
|
|
arc: C1 H00L0100
|
|
arc: C3 E1_H01W0000
|
|
arc: C6 V00T0000
|
|
arc: C7 V00T0000
|
|
arc: CE0 H00R0000
|
|
arc: CE1 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V01S0100
|
|
arc: D1 V01S0100
|
|
arc: D2 Q2
|
|
arc: D3 V01S0100
|
|
arc: D6 H00L0100
|
|
arc: D7 E1_H01W0100
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F6 F5D_SLICE
|
|
arc: H00L0000 Q2
|
|
arc: H00L0100 Q1
|
|
arc: H01W0100 Q1
|
|
arc: LSR0 H02E0301
|
|
arc: M6 V00T0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR0
|
|
arc: S3_V06S0303 F6
|
|
arc: V00T0000 Q0
|
|
arc: V00T0100 F3
|
|
arc: V01S0000 Q1
|
|
arc: V01S0100 Q2
|
|
word: SLICEA.K0.INIT 0001010001000100
|
|
word: SLICEA.K1.INIT 0000010101010000
|
|
word: SLICEB.K0.INIT 0000000001010101
|
|
word: SLICEB.K1.INIT 1110100000100010
|
|
word: SLICED.K0.INIT 0111101111110011
|
|
word: SLICED.K1.INIT 0000000001111000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R21C41:PLC2
|
|
arc: E1_H02E0001 V02S0001
|
|
arc: E1_H02E0101 S3_V06N0103
|
|
arc: E1_H02E0401 S1_V02N0401
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: H00L0000 V02N0001
|
|
arc: N1_V02N0601 S1_V02N0601
|
|
arc: N3_V06N0103 S3_V06N0003
|
|
arc: S1_V02S0101 H02W0101
|
|
arc: S3_V06S0003 N1_V02S0001
|
|
arc: V00T0100 H02W0101
|
|
arc: V01S0000 S3_V06N0103
|
|
arc: W1_H02W0001 N1_V02S0001
|
|
arc: W1_H02W0601 S1_V02N0601
|
|
arc: A0 H00L0100
|
|
arc: A4 V02N0101
|
|
arc: B0 W1_H02E0101
|
|
arc: B1 Q1
|
|
arc: B4 V02N0501
|
|
arc: C0 H00R0100
|
|
arc: C4 E1_H02W0601
|
|
arc: CE0 H00R0000
|
|
arc: CE3 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 W1_H02E0201
|
|
arc: D1 V00B0100
|
|
arc: D4 V02N0401
|
|
arc: F0 F5A_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: H00L0100 Q1
|
|
arc: H00R0000 F4
|
|
arc: H00R0100 Q7
|
|
arc: H01W0000 Q6
|
|
arc: H01W0100 Q1
|
|
arc: LSR0 H02E0501
|
|
arc: LSR1 H02E0301
|
|
arc: M0 H02E0601
|
|
arc: M1 W1_H02E0001
|
|
arc: M6 V00T0100
|
|
arc: M7 H00L0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR3 LSR1
|
|
arc: S1_V02S0001 F0
|
|
arc: S1_V02S0201 F0
|
|
arc: S1_V02S0701 Q7
|
|
arc: S3_V06S0103 Q1
|
|
arc: V00B0100 Q7
|
|
arc: V01S0100 Q6
|
|
arc: W1_H02W0301 Q1
|
|
arc: W1_H02W0701 Q7
|
|
word: SLICEC.K0.INIT 1110110011001100
|
|
word: SLICEA.K1.INIT 1111111111001100
|
|
word: SLICEA.K0.INIT 1100100000000000
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
|
|
.tile R21C42:PLC2
|
|
arc: H00R0100 S1_V02N0701
|
|
arc: V00B0000 V02N0001
|
|
arc: V00B0100 S1_V02N0301
|
|
arc: V00T0000 H02W0201
|
|
arc: V00T0100 H02W0101
|
|
arc: W1_H02W0101 N1_V02S0101
|
|
arc: A2 H02W0501
|
|
arc: A3 V00T0000
|
|
arc: A5 H02W0701
|
|
arc: B2 E1_H01W0100
|
|
arc: B3 E1_H01W0100
|
|
arc: B5 N1_V01S0000
|
|
arc: B6 H02E0101
|
|
arc: C2 E1_H01W0000
|
|
arc: C3 E1_H01W0000
|
|
arc: C5 V00B0100
|
|
arc: C6 V02N0201
|
|
arc: CE0 H00R0000
|
|
arc: CE1 H00R0000
|
|
arc: CE2 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D2 H02W0201
|
|
arc: D3 V02S0001
|
|
arc: D5 H00L0100
|
|
arc: D6 H02W0001
|
|
arc: E1_H01E0101 F4
|
|
arc: E1_H02E0001 F2
|
|
arc: E1_H02E0201 F2
|
|
arc: E1_H02E0601 F6
|
|
arc: F2 F5B_SLICE
|
|
arc: F4 F5C_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: H00L0100 Q3
|
|
arc: H00R0000 F6
|
|
arc: M0 V00B0000
|
|
arc: M1 W1_H02E0001
|
|
arc: M2 V00T0100
|
|
arc: M3 H00R0100
|
|
arc: M4 H02E0401
|
|
arc: M5 H02E0001
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: N1_V01N0001 Q5
|
|
arc: N1_V01N0101 Q1
|
|
arc: N1_V02N0201 Q0
|
|
arc: N1_V02N0601 F6
|
|
arc: S1_V02S0101 Q3
|
|
arc: S1_V02S0601 F6
|
|
word: SLICED.K0.INIT 1100000000000000
|
|
word: SLICEB.K0.INIT 0111111111010101
|
|
word: SLICEB.K1.INIT 0000000001101010
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0010000000000010
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R21C43:PLC2
|
|
arc: E1_H02E0001 N1_V01S0000
|
|
arc: E1_H02E0601 N1_V01S0000
|
|
arc: H00R0000 V02N0401
|
|
arc: N1_V02N0001 E1_H02W0001
|
|
arc: S3_V06S0203 H06W0203
|
|
arc: V00B0000 H02E0601
|
|
arc: W1_H02W0001 E1_H02W0001
|
|
arc: W1_H02W0501 V02S0501
|
|
arc: W1_H02W0601 E1_H02W0301
|
|
arc: W1_H02W0701 N1_V01S0100
|
|
arc: W3_H06W0103 S3_V06N0103
|
|
arc: A0 H00R0000
|
|
arc: A3 V00T0000
|
|
arc: B0 H01W0100
|
|
arc: B1 Q1
|
|
arc: B3 V02S0101
|
|
arc: B7 H01E0101
|
|
arc: C0 H00L0000
|
|
arc: C1 V02N0401
|
|
arc: C2 V02N0401
|
|
arc: C3 N1_V01S0100
|
|
arc: C7 S1_V02N0001
|
|
arc: CE0 E1_H02W0101
|
|
arc: CE1 E1_H02W0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V01S0100
|
|
arc: D1 V01S0100
|
|
arc: D2 Q2
|
|
arc: D3 V00T0100
|
|
arc: E1_H01E0001 F7
|
|
arc: E1_H02E0701 F7
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00L0000 Q0
|
|
arc: H01W0000 Q2
|
|
arc: H01W0100 Q1
|
|
arc: LSR0 V00B0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR0
|
|
arc: V00T0000 Q2
|
|
arc: V00T0100 Q1
|
|
arc: V01S0100 Q2
|
|
arc: W1_H02W0101 F3
|
|
arc: W1_H02W0201 Q0
|
|
word: SLICEA.K0.INIT 0001010001010000
|
|
word: SLICEA.K1.INIT 0000001100001100
|
|
word: SLICEB.K0.INIT 0000000000001111
|
|
word: SLICEB.K1.INIT 1010100011010000
|
|
word: SLICED.K1.INIT 0000001100000011
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
|
|
.tile R21C44:PLC2
|
|
arc: E1_H02E0201 H01E0001
|
|
arc: E1_H02E0601 S1_V02N0601
|
|
arc: E3_H06E0003 S3_V06N0003
|
|
arc: E3_H06E0203 S3_V06N0203
|
|
arc: H00R0100 H02E0701
|
|
arc: N1_V02N0001 S1_V02N0001
|
|
arc: N1_V02N0101 S1_V02N0001
|
|
arc: N1_V02N0201 S1_V02N0201
|
|
arc: N1_V02N0301 S1_V02N0201
|
|
arc: N1_V02N0501 S1_V02N0401
|
|
arc: S1_V02S0201 N1_V02S0201
|
|
arc: S3_V06S0103 E1_H01W0100
|
|
arc: W3_H06W0303 S3_V06N0303
|
|
arc: A0 E1_H02W0501
|
|
arc: A1 E1_H02W0701
|
|
arc: A2 E1_H02W0701
|
|
arc: A3 E1_H02W0701
|
|
arc: B0 S1_V02N0101
|
|
arc: B2 S1_V02N0301
|
|
arc: C2 V02S0601
|
|
arc: C7 V02N0201
|
|
arc: D0 W1_H02E0201
|
|
arc: D1 W1_H02E0001
|
|
arc: D2 W1_H02E0201
|
|
arc: D3 W1_H02E0001
|
|
arc: D7 H02E0001
|
|
arc: E1_H02E0101 F1
|
|
arc: E1_H02E0501 F7
|
|
arc: F0 F5A_SLICE
|
|
arc: F1 FXA_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: M0 H02E0601
|
|
arc: M1 H00R0100
|
|
arc: M2 H02E0601
|
|
word: SLICEA.K0.INIT 1000100000000000
|
|
word: SLICED.K1.INIT 0000000000001111
|
|
word: SLICEB.K1.INIT 1010101000000000
|
|
word: SLICEB.K0.INIT 1010100000000000
|
|
word: SLICEA.K1.INIT 1010101000000000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
|
|
.tile R21C45:PLC2
|
|
arc: E1_H02E0001 S3_V06N0003
|
|
arc: E3_H06E0003 S3_V06N0003
|
|
arc: H00L0000 V02S0001
|
|
arc: H00R0000 V02N0401
|
|
arc: N1_V01N0001 S3_V06N0003
|
|
arc: N1_V02N0001 S3_V06N0003
|
|
arc: N1_V02N0101 E1_H02W0101
|
|
arc: S3_V06S0203 N3_V06S0103
|
|
arc: V00B0100 V02N0301
|
|
arc: V00T0000 S1_V02N0401
|
|
arc: V00T0100 H02E0101
|
|
arc: W1_H02W0001 S3_V06N0003
|
|
arc: W1_H02W0101 E1_H01W0100
|
|
arc: W1_H02W0301 S3_V06N0003
|
|
arc: A0 H00R0000
|
|
arc: A2 V02N0501
|
|
arc: A4 V02N0101
|
|
arc: B0 V02N0101
|
|
arc: B2 E1_H02W0101
|
|
arc: B4 E1_H02W0101
|
|
arc: C0 N1_V01N0001
|
|
arc: C2 N1_V01N0001
|
|
arc: C4 V02N0201
|
|
arc: CE2 V02N0601
|
|
arc: CE3 V02N0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 E1_H02W0201
|
|
arc: D2 H02W0001
|
|
arc: D4 S1_V02N0601
|
|
arc: E1_H02E0401 Q4
|
|
arc: E1_H02E0501 Q7
|
|
arc: F0 F5A_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: H01W0100 F2
|
|
arc: LSR0 V00T0000
|
|
arc: M0 V00B0100
|
|
arc: M2 V00T0100
|
|
arc: M7 H00L0000
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR2 LSR0
|
|
arc: MUXLSR3 LSR0
|
|
arc: S1_V02S0201 F2
|
|
arc: S1_V02S0401 Q4
|
|
arc: S1_V02S0501 Q7
|
|
arc: S1_V02S0601 Q4
|
|
arc: S1_V02S0701 Q7
|
|
arc: V01S0000 F0
|
|
word: SLICEC.K0.INIT 0000100000000000
|
|
word: SLICEA.K1.INIT 1111111111111111
|
|
word: SLICEB.K1.INIT 1111111111111111
|
|
word: SLICEB.K0.INIT 1111111110000000
|
|
word: SLICEA.K0.INIT 1110101010101010
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET SET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET SET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
|
|
.tile R21C46:PLC2
|
|
arc: E1_H02E0601 E1_H01W0000
|
|
arc: E3_H06E0203 S3_V06N0203
|
|
arc: H00R0100 H02E0501
|
|
arc: N1_V02N0001 H02E0001
|
|
arc: N1_V02N0101 H02W0101
|
|
arc: N1_V02N0401 S1_V02N0101
|
|
arc: N1_V02N0501 N1_V01S0100
|
|
arc: S3_V06S0003 N3_V06S0003
|
|
arc: V00B0100 W1_H02E0501
|
|
arc: W1_H02W0001 V02N0001
|
|
arc: A0 F5
|
|
arc: A1 F5
|
|
arc: B1 V02S0301
|
|
arc: B4 S1_V02N0701
|
|
arc: B5 S1_V02N0701
|
|
arc: C1 V02S0401
|
|
arc: C4 H02E0401
|
|
arc: C5 W1_H02E0601
|
|
arc: D0 V02N0001
|
|
arc: D1 W1_H02E0201
|
|
arc: D4 H00R0100
|
|
arc: D5 V02N0401
|
|
arc: F0 F5A_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: H01W0100 F0
|
|
arc: M0 V00B0100
|
|
arc: W1_H02W0501 F5
|
|
arc: W1_H02W0701 F5
|
|
arc: W3_H06W0203 F4
|
|
word: SLICEA.K0.INIT 1111111110101010
|
|
word: SLICEA.K1.INIT 1111000011111000
|
|
word: SLICEC.K1.INIT 0000110000000000
|
|
word: SLICEC.K0.INIT 0000000011000000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
|
|
.tile R21C47:PLC2
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: H00R0000 S1_V02N0601
|
|
arc: S1_V02S0201 N1_V02S0701
|
|
arc: V00B0000 V02N0001
|
|
arc: W1_H02W0101 S3_V06N0103
|
|
arc: W1_H02W0201 S3_V06N0103
|
|
arc: A1 F7
|
|
arc: A7 S1_V02N0301
|
|
arc: B1 V02N0301
|
|
arc: B7 V00B0000
|
|
arc: C1 E1_H01W0000
|
|
arc: C7 S1_V02N0001
|
|
arc: D1 H00R0000
|
|
arc: D7 V02N0601
|
|
arc: F1 F1_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 F1
|
|
word: SLICED.K1.INIT 1100001101000001
|
|
word: SLICEA.K1.INIT 1000000000100000
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R21C48:PLC2
|
|
arc: H00R0000 E1_H02W0401
|
|
arc: N3_V06N0203 S3_V06N0103
|
|
arc: S1_V02S0501 N1_V02S0401
|
|
arc: S3_V06S0303 N3_V06S0303
|
|
arc: V00B0000 E1_H02W0601
|
|
arc: V00T0000 N1_V02S0401
|
|
arc: V00T0100 E1_H02W0301
|
|
arc: A0 H00L0100
|
|
arc: A2 S1_V02N0701
|
|
arc: A5 V00T0000
|
|
arc: A7 F5
|
|
arc: B0 V02N0301
|
|
arc: B1 V02N0301
|
|
arc: B2 S1_V02N0301
|
|
arc: B5 S1_V02N0501
|
|
arc: B7 V02N0501
|
|
arc: C0 E1_H02W0601
|
|
arc: C2 S1_V02N0401
|
|
arc: C5 E1_H02W0401
|
|
arc: CE0 S1_V02N0201
|
|
arc: CE3 V02N0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H00R0000
|
|
arc: D1 V01S0100
|
|
arc: D2 V02N0201
|
|
arc: D3 V02N0001
|
|
arc: D5 V00B0000
|
|
arc: D7 H00R0100
|
|
arc: E1_H01E0101 F2
|
|
arc: E1_H02E0201 F2
|
|
arc: F0 F5A_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00L0100 Q1
|
|
arc: H00R0100 Q7
|
|
arc: H01W0000 F7
|
|
arc: M0 V00T0100
|
|
arc: M1 H02W0001
|
|
arc: M2 W1_H02E0601
|
|
arc: M7 H02W0201
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: S1_V02S0001 F0
|
|
arc: S3_V06S0103 F2
|
|
arc: V01S0100 Q1
|
|
word: SLICEA.K0.INIT 1001100110010000
|
|
word: SLICEA.K1.INIT 1100110000110011
|
|
word: SLICEC.K1.INIT 1101110111010000
|
|
word: SLICED.K1.INIT 1000100000100010
|
|
word: SLICEB.K1.INIT 1111111100000000
|
|
word: SLICEB.K0.INIT 1111111000000000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R21C49:PLC2
|
|
arc: E1_H02E0501 V02N0501
|
|
arc: E1_H02E0601 S1_V02N0601
|
|
arc: E1_H02E0701 V02S0701
|
|
arc: S1_V02S0401 H02W0401
|
|
arc: S1_V02S0601 E1_H01W0000
|
|
arc: S3_V06S0103 N3_V06S0103
|
|
arc: V00T0100 S1_V02N0501
|
|
arc: W1_H02W0001 N1_V02S0001
|
|
arc: W1_H02W0201 N3_V06S0103
|
|
arc: A0 H00L0100
|
|
arc: A1 H00L0100
|
|
arc: A2 V00B0000
|
|
arc: A3 V00B0000
|
|
arc: A7 E1_H01W0000
|
|
arc: B0 V00T0000
|
|
arc: B1 V00T0000
|
|
arc: B2 H00L0000
|
|
arc: B7 V01S0000
|
|
arc: C0 H02W0401
|
|
arc: C1 H02W0401
|
|
arc: C2 H00L0100
|
|
arc: C3 H00L0100
|
|
arc: C4 V02N0201
|
|
arc: C6 Q6
|
|
arc: C7 H02W0601
|
|
arc: CE1 H00R0000
|
|
arc: CE3 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V01S0100
|
|
arc: D1 V01S0100
|
|
arc: D2 H01E0101
|
|
arc: D3 H02E0201
|
|
arc: D4 H02E0201
|
|
arc: D6 H02E0201
|
|
arc: D7 V00B0000
|
|
arc: F0 F5A_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00L0000 Q2
|
|
arc: H00L0100 Q3
|
|
arc: H00R0000 F4
|
|
arc: LSR0 V00T0100
|
|
arc: M0 V00B0100
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR3 LSR0
|
|
arc: S1_V02S0001 F0
|
|
arc: V00B0000 Q6
|
|
arc: V00B0100 F7
|
|
arc: V00T0000 Q2
|
|
arc: V01S0000 Q3
|
|
arc: V01S0100 Q6
|
|
word: SLICED.K0.INIT 0000111100000000
|
|
word: SLICEB.K0.INIT 0110110000000000
|
|
word: SLICEB.K1.INIT 0101101000000000
|
|
word: SLICEC.K0.INIT 1111111111110000
|
|
word: SLICED.K1.INIT 1110100000110000
|
|
word: SLICEA.K0.INIT 0110111111001111
|
|
word: SLICEA.K1.INIT 0000011000001100
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R21C4:PLC2
|
|
arc: W3_H06W0303 E1_H01W0100
|
|
|
|
.tile R21C50:PLC2
|
|
arc: E1_H02E0001 N1_V02S0001
|
|
arc: E1_H02E0101 N1_V02S0101
|
|
arc: E1_H02E0201 S1_V02N0201
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
arc: H00L0000 N1_V02S0201
|
|
arc: S1_V02S0201 W1_H02E0201
|
|
arc: S3_V06S0103 N1_V02S0101
|
|
arc: V00B0000 V02N0201
|
|
arc: V00B0100 H02E0701
|
|
arc: V00T0000 S1_V02N0401
|
|
arc: A1 V02N0701
|
|
arc: A5 V02S0101
|
|
arc: B1 V02N0101
|
|
arc: B5 S1_V02N0701
|
|
arc: C1 H02E0601
|
|
arc: C5 N1_V02S0001
|
|
arc: CE1 H00L0100
|
|
arc: CE2 H00L0100
|
|
arc: CE3 H00L0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D1 H02W0001
|
|
arc: D5 E1_H01W0100
|
|
arc: E1_H02E0701 F5
|
|
arc: F1 F1_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: H00L0100 F1
|
|
arc: H01W0000 Q3
|
|
arc: LSR0 H02E0501
|
|
arc: LSR1 V00B0100
|
|
arc: M3 H00L0000
|
|
arc: M4 V00B0000
|
|
arc: M6 V00T0000
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR0
|
|
arc: S1_V02S0401 Q4
|
|
arc: S1_V02S0601 Q6
|
|
arc: W1_H02W0301 Q3
|
|
arc: W1_H02W0401 Q6
|
|
arc: W1_H02W0601 Q4
|
|
word: SLICEC.K1.INIT 1010001001010001
|
|
word: SLICEA.K1.INIT 1110110011001100
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R21C51:PLC2
|
|
arc: H00R0000 H02W0401
|
|
arc: H00R0100 S1_V02N0501
|
|
arc: N1_V01N0101 N3_V06S0203
|
|
arc: S1_V02S0701 N3_V06S0203
|
|
arc: S3_V06S0103 N3_V06S0103
|
|
arc: S3_V06S0203 N3_V06S0103
|
|
arc: S3_V06S0303 N3_V06S0203
|
|
arc: V00B0100 H02E0701
|
|
arc: V00T0000 H02E0001
|
|
arc: V00T0100 H02E0101
|
|
arc: W1_H02W0001 W3_H06E0003
|
|
arc: A1 F5
|
|
arc: A5 S1_V02N0301
|
|
arc: B1 V02N0101
|
|
arc: B5 V02S0701
|
|
arc: C1 H00L0100
|
|
arc: C5 V00T0000
|
|
arc: CE1 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D1 V02N0001
|
|
arc: D5 H02E0201
|
|
arc: F0 F5A_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: H00L0100 Q3
|
|
arc: H01W0100 Q2
|
|
arc: M0 V00B0100
|
|
arc: M2 V00T0100
|
|
arc: M3 H00R0000
|
|
arc: MUXCLK1 CLK0
|
|
arc: S1_V02S0001 F0
|
|
word: SLICEC.K1.INIT 1101110100001101
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 1000001000000000
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R21C52:PLC2
|
|
arc: E3_H06E0103 S3_V06N0103
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
arc: S1_V02S0401 N3_V06S0203
|
|
arc: S3_V06S0203 N1_V02S0401
|
|
arc: W1_H02W0401 N1_V02S0401
|
|
|
|
.tile R21C53:PLC2
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: N3_V06N0203 S3_V06N0103
|
|
|
|
.tile R21C56:PLC2
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
|
|
.tile R21C58:PLC2
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: N3_V06N0203 W3_H06E0203
|
|
|
|
.tile R21C59:PLC2
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
|
|
.tile R21C5:PLC2
|
|
arc: H01W0100 E3_H06W0303
|
|
arc: N3_V06N0203 S3_V06N0103
|
|
arc: W1_H02W0501 S3_V06N0303
|
|
|
|
.tile R21C62:PLC2
|
|
arc: E3_H06E0103 S3_V06N0103
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
|
|
.tile R21C64:PLC2
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
|
|
.tile R21C65:PLC2
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: N3_V06N0103 S3_V06N0003
|
|
|
|
.tile R21C67:PLC2
|
|
arc: N3_V06N0103 H06E0103
|
|
|
|
.tile R21C68:PLC2
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
arc: N3_V06N0303 W3_H06E0303
|
|
|
|
.tile R21C69:PLC2
|
|
arc: N3_V06N0103 S3_V06N0103
|
|
|
|
.tile R21C6:PLC2
|
|
arc: N3_V06N0203 S3_V06N0203
|
|
|
|
.tile R21C71:PLC2
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
|
|
.tile R21C73:PLC2
|
|
arc: N3_V06N0103 S3_V06N0003
|
|
|
|
.tile R21C74:PLC2
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
|
|
.tile R21C75:PLC2
|
|
arc: N3_V06N0203 S3_V06N0103
|
|
|
|
.tile R21C77:PLC2
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
|
|
.tile R21C7:PLC2
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
|
|
.tile R21C80:PLC2
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
arc: N3_V06N0303 S3_V06N0303
|
|
|
|
.tile R21C83:PLC2
|
|
arc: N3_V06N0203 W3_H06E0203
|
|
|
|
.tile R21C86:PLC2
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
|
|
.tile R21C88:PLC2
|
|
arc: N1_V01N0001 S3_V06N0003
|
|
|
|
.tile R21C8:PLC2
|
|
arc: N3_V06N0103 E3_H06W0103
|
|
arc: W3_H06W0203 E3_H06W0203
|
|
|
|
.tile R23C11:PLC2
|
|
arc: W3_H06W0303 E3_H06W0203
|
|
|
|
.tile R23C13:PLC2
|
|
arc: W3_H06W0303 E3_H06W0203
|
|
|
|
.tile R23C17:PLC2
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
|
|
.tile R23C19:PLC2
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
|
|
.tile R23C23:PLC2
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
|
|
.tile R23C25:PLC2
|
|
arc: W3_H06W0103 E1_H02W0201
|
|
|
|
.tile R23C27:PLC2
|
|
arc: W1_H02W0201 S1_V02N0201
|
|
|
|
.tile R23C29:PLC2
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
|
|
.tile R23C35:PLC2
|
|
arc: W3_H06W0103 E1_H02W0101
|
|
|
|
.tile R23C37:PLC2
|
|
arc: W1_H02W0101 S1_V02N0101
|
|
|
|
.tile R23C38:PLC2
|
|
arc: N1_V02N0001 S1_V02N0501
|
|
|
|
.tile R23C39:PLC2
|
|
arc: E1_H02E0101 V01N0101
|
|
arc: E1_H02E0201 N1_V02S0201
|
|
arc: E1_H02E0401 V02N0401
|
|
arc: E1_H02E0501 S1_V02N0501
|
|
arc: E1_H02E0601 V02S0601
|
|
arc: H00L0000 N1_V02S0201
|
|
arc: H00L0100 H02W0301
|
|
arc: H00R0000 E1_H02W0401
|
|
arc: H00R0100 V02N0501
|
|
arc: N1_V02N0001 E1_H02W0001
|
|
arc: N1_V02N0101 N1_V01S0100
|
|
arc: N1_V02N0201 V01N0001
|
|
arc: N1_V02N0301 V01N0101
|
|
arc: N1_V02N0501 S1_V02N0501
|
|
arc: N1_V02N0601 V01N0001
|
|
arc: V00B0000 V02S0201
|
|
arc: A4 S1_V02N0101
|
|
arc: A5 N1_V01S0100
|
|
arc: A6 S1_V02N0101
|
|
arc: A7 N1_V01S0100
|
|
arc: B4 S1_V02N0501
|
|
arc: B5 S1_V02N0501
|
|
arc: B6 S1_V02N0501
|
|
arc: B7 V00B0000
|
|
arc: C4 V02S0001
|
|
arc: C5 N1_V02S0001
|
|
arc: C6 V02S0001
|
|
arc: C7 V02N0001
|
|
arc: CE3 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D4 E1_H01W0100
|
|
arc: D5 E1_H01W0100
|
|
arc: D6 E1_H01W0100
|
|
arc: D7 E1_H01W0100
|
|
arc: E1_H01E0101 Q7
|
|
arc: F0 F5A_SLICE
|
|
arc: F1 FXA_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F3 FXB_SLICE
|
|
arc: F4 F5C_SLICE
|
|
arc: F5 FXC_SLICE
|
|
arc: F6 F5D_SLICE
|
|
arc: M0 V00B0100
|
|
arc: M1 H00L0100
|
|
arc: M2 V00B0100
|
|
arc: M3 H00L0000
|
|
arc: M4 V00B0100
|
|
arc: M5 H00L0100
|
|
arc: M6 V00B0100
|
|
arc: M7 H00R0000
|
|
arc: MUXCLK3 CLK0
|
|
arc: S1_V02S0301 F3
|
|
arc: V00B0100 Q7
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 0010000000010000
|
|
word: SLICEC.K1.INIT 1000000000001000
|
|
word: SLICED.K0.INIT 0000001000000001
|
|
word: SLICED.K1.INIT 0100000000010000
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R23C3:PLC2
|
|
arc: W1_H02W0501 E1_H02W0501
|
|
|
|
.tile R23C40:PLC2
|
|
arc: E1_H02E0401 V02N0401
|
|
arc: E1_H02E0501 V02S0501
|
|
arc: E1_H02E0601 V01N0001
|
|
arc: H00R0100 S1_V02N0501
|
|
arc: N1_V02N0501 S3_V06N0303
|
|
arc: N1_V02N0601 S1_V02N0601
|
|
arc: S1_V02S0401 N1_V02S0101
|
|
arc: V00B0000 S1_V02N0001
|
|
arc: V00B0100 V02N0301
|
|
arc: V01S0000 S3_V06N0103
|
|
arc: A1 H02W0701
|
|
arc: A3 H02E0501
|
|
arc: A5 F7
|
|
arc: B1 Q1
|
|
arc: B3 N1_V02S0101
|
|
arc: B5 V00B0100
|
|
arc: C1 H02E0601
|
|
arc: C3 H00L0000
|
|
arc: C4 V02N0201
|
|
arc: C5 N1_V02S0201
|
|
arc: C7 V00T0000
|
|
arc: CE0 H02E0101
|
|
arc: CE1 H02E0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D1 H02E0201
|
|
arc: D3 H01E0101
|
|
arc: D4 N1_V02S0401
|
|
arc: D5 N1_V02S0401
|
|
arc: D7 S1_V02N0601
|
|
arc: E1_H01E0101 F7
|
|
arc: F0 F5A_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F5C_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00L0000 Q2
|
|
arc: H01W0100 Q2
|
|
arc: M0 V00T0100
|
|
arc: M1 H00R0100
|
|
arc: M2 V00B0000
|
|
arc: M4 E1_H02W0401
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: N1_V02N0401 F4
|
|
arc: V00T0000 F0
|
|
arc: V00T0100 F3
|
|
arc: W1_H02W0301 Q1
|
|
word: SLICEC.K0.INIT 1111111111110000
|
|
word: SLICEC.K1.INIT 1101110011001100
|
|
word: SLICEB.K1.INIT 1000001001000001
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000010000010
|
|
word: SLICED.K1.INIT 0000000000001111
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
|
|
.tile R23C41:PLC2
|
|
arc: E1_H02E0001 W1_H02E0501
|
|
arc: E1_H02E0201 S3_V06N0103
|
|
arc: E1_H02E0501 V02N0501
|
|
arc: H00R0000 H02W0601
|
|
arc: H00R0100 S1_V02N0501
|
|
arc: N1_V02N0601 S1_V02N0601
|
|
arc: S1_V02S0101 N1_V02S0101
|
|
arc: S1_V02S0201 N1_V02S0201
|
|
arc: S1_V02S0301 N1_V01S0100
|
|
arc: S1_V02S0501 W1_H02E0501
|
|
arc: S1_V02S0701 H01E0101
|
|
arc: V00B0100 W1_H02E0501
|
|
arc: V00T0100 V02S0501
|
|
arc: W1_H02W0001 S3_V06N0003
|
|
arc: W1_H02W0401 V02N0401
|
|
arc: W1_H02W0701 N1_V02S0701
|
|
arc: A4 H02W0501
|
|
arc: A5 H02E0501
|
|
arc: B4 V00B0100
|
|
arc: B5 N1_V01S0000
|
|
arc: C1 H02E0401
|
|
arc: C4 Q4
|
|
arc: C5 V00T0000
|
|
arc: CE0 H00R0000
|
|
arc: CE1 H00R0000
|
|
arc: CE2 H00R0000
|
|
arc: CE3 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D1 N1_V02S0001
|
|
arc: D4 V00B0000
|
|
arc: D5 H00L0100
|
|
arc: E1_H01E0001 F1
|
|
arc: E1_H01E0101 Q6
|
|
arc: E1_H02E0401 Q4
|
|
arc: E1_H02E0601 Q4
|
|
arc: E1_H02E0701 F5
|
|
arc: F1 F1_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: H00L0100 Q1
|
|
arc: M1 H00R0100
|
|
arc: M2 H02E0601
|
|
arc: M4 V00T0100
|
|
arc: M6 W1_H02E0401
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V02N0401 F4
|
|
arc: V00B0000 Q6
|
|
arc: V00T0000 Q2
|
|
word: SLICEA.K1.INIT 0000000000001111
|
|
word: SLICEC.K0.INIT 1000001001000001
|
|
word: SLICEC.K1.INIT 1000010000100001
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R23C42:PLC2
|
|
arc: E1_H02E0101 V01N0101
|
|
arc: E1_H02E0401 V01N0001
|
|
arc: E1_H02E0501 S1_V02N0501
|
|
arc: E1_H02E0601 N1_V02S0601
|
|
arc: H00L0100 N1_V02S0101
|
|
arc: H00R0000 V02S0601
|
|
arc: N1_V02N0301 N1_V01S0100
|
|
arc: N1_V02N0701 H02W0701
|
|
arc: S1_V02S0001 E1_H01W0000
|
|
arc: S1_V02S0401 E1_H02W0401
|
|
arc: S1_V02S0501 E1_H02W0501
|
|
arc: S1_V02S0601 N1_V02S0601
|
|
arc: S1_V02S0701 N1_V02S0601
|
|
arc: V00T0000 S1_V02N0601
|
|
arc: V00T0100 V02N0501
|
|
arc: W1_H02W0401 H01E0001
|
|
arc: W1_H02W0501 S1_V02N0501
|
|
arc: W1_H02W0601 N1_V02S0601
|
|
arc: A4 V00T0000
|
|
arc: A5 V00T0000
|
|
arc: A6 V00T0100
|
|
arc: A7 V00T0100
|
|
arc: B4 H01E0101
|
|
arc: B5 H01E0101
|
|
arc: B6 H01E0101
|
|
arc: B7 H01E0101
|
|
arc: C4 V00T0100
|
|
arc: C5 V00T0100
|
|
arc: C6 V00T0000
|
|
arc: C7 V00T0000
|
|
arc: CE3 N1_V02S0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D4 H02E0001
|
|
arc: D5 H02E0001
|
|
arc: D6 H02E0001
|
|
arc: D7 H02E0001
|
|
arc: E1_H01E0001 F3
|
|
arc: E1_H02E0701 Q7
|
|
arc: F0 F5A_SLICE
|
|
arc: F1 FXA_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F3 FXB_SLICE
|
|
arc: F4 F5C_SLICE
|
|
arc: F5 FXC_SLICE
|
|
arc: F6 F5D_SLICE
|
|
arc: M0 H02E0601
|
|
arc: M1 H00L0100
|
|
arc: M2 H02E0601
|
|
arc: M3 H00R0000
|
|
arc: M4 H02E0401
|
|
arc: M5 H00L0100
|
|
arc: M6 H02E0401
|
|
arc: M7 H02E0201
|
|
arc: MUXCLK3 CLK0
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 0000000010010000
|
|
word: SLICEC.K1.INIT 1001000000000000
|
|
word: SLICED.K0.INIT 0000000001000001
|
|
word: SLICED.K1.INIT 0100000100000000
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R23C43:PLC2
|
|
arc: E1_H02E0301 S1_V02N0301
|
|
arc: E1_H02E0501 V01N0101
|
|
arc: E1_H02E0601 V01N0001
|
|
arc: E1_H02E0701 S1_V02N0701
|
|
arc: E3_H06E0303 S3_V06N0303
|
|
arc: H00R0000 H02E0601
|
|
arc: H00R0100 W1_H02E0501
|
|
arc: S3_V06S0203 H06W0203
|
|
arc: V00B0100 W1_H02E0701
|
|
arc: V00T0000 S1_V02N0601
|
|
arc: V00T0100 S1_V02N0501
|
|
arc: W1_H02W0701 S1_V02N0701
|
|
arc: A3 H02E0501
|
|
arc: A4 H02E0701
|
|
arc: A5 V00B0000
|
|
arc: B3 V02S0301
|
|
arc: B4 H02E0101
|
|
arc: B5 V02S0501
|
|
arc: C3 H02E0401
|
|
arc: C4 V00T0000
|
|
arc: C5 H01E0001
|
|
arc: CE2 V02N0601
|
|
arc: CE3 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D3 V01S0100
|
|
arc: D4 E1_H02W0001
|
|
arc: D5 V02N0401
|
|
arc: E1_H01E0101 F5
|
|
arc: F2 F5B_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: H01W0000 Q5
|
|
arc: M2 V00B0100
|
|
arc: M5 H00R0100
|
|
arc: M6 V00T0100
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 F5
|
|
arc: N1_V01N0101 F2
|
|
arc: N1_V02N0001 F2
|
|
arc: V00B0000 F4
|
|
arc: V01S0100 Q6
|
|
word: SLICEC.K1.INIT 1100100011000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 1000010000100001
|
|
word: SLICEC.K0.INIT 1000010000100001
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R23C44:PLC2
|
|
arc: H00L0000 H02W0201
|
|
arc: N1_V02N0101 H01E0101
|
|
arc: N1_V02N0301 H01E0101
|
|
arc: N1_V02N0601 S1_V02N0301
|
|
arc: N3_V06N0103 S3_V06N0103
|
|
arc: S1_V02S0101 S3_V06N0103
|
|
arc: V00B0000 N1_V02S0201
|
|
arc: V00B0100 V02N0101
|
|
arc: V00T0000 E1_H02W0201
|
|
arc: V00T0100 V02N0501
|
|
arc: A0 S1_V02N0501
|
|
arc: A2 V02N0701
|
|
arc: A3 H02E0501
|
|
arc: A4 V00T0000
|
|
arc: B0 V00T0000
|
|
arc: B2 H00R0100
|
|
arc: B3 V02N0301
|
|
arc: B4 H02E0301
|
|
arc: C0 H02W0601
|
|
arc: C2 H02E0601
|
|
arc: C3 H00R0100
|
|
arc: C4 H02W0401
|
|
arc: CE2 H00R0000
|
|
arc: CE3 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 S1_V02N0001
|
|
arc: D2 V02N0001
|
|
arc: D3 V02N0001
|
|
arc: D4 S1_V02N0401
|
|
arc: E1_H01E0101 F0
|
|
arc: F0 F5A_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: H00R0000 F4
|
|
arc: H00R0100 Q5
|
|
arc: LSR1 H02E0301
|
|
arc: M0 V00B0100
|
|
arc: M2 V00T0100
|
|
arc: M4 V00B0000
|
|
arc: M5 H00L0000
|
|
arc: M6 E1_H02W0401
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR1
|
|
arc: N1_V02N0001 F2
|
|
arc: N1_V02N0201 F2
|
|
arc: N1_V02N0401 Q4
|
|
arc: S1_V02S0401 Q6
|
|
arc: V01S0000 Q5
|
|
arc: V01S0100 Q4
|
|
arc: W1_H02W0401 Q6
|
|
arc: W1_H02W0501 Q5
|
|
word: SLICEA.K0.INIT 1110101010101010
|
|
word: SLICEA.K1.INIT 1111111111111111
|
|
word: SLICEC.K0.INIT 1110110011001100
|
|
word: SLICEB.K0.INIT 0111111110110011
|
|
word: SLICEB.K1.INIT 0000011100001000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R23C45:PLC2
|
|
arc: E1_H02E0101 H01E0101
|
|
arc: E1_H02E0201 W1_H02E0701
|
|
arc: E1_H02E0301 S1_V02N0301
|
|
arc: E1_H02E0401 N1_V02S0401
|
|
arc: E1_H02E0501 N1_V02S0501
|
|
arc: E1_H02E0701 V02N0701
|
|
arc: N1_V02N0401 S1_V02N0101
|
|
arc: N1_V02N0601 S1_V02N0601
|
|
arc: S1_V02S0201 N1_V02S0201
|
|
arc: S1_V02S0601 E1_H02W0601
|
|
arc: V00T0000 V02N0601
|
|
arc: V00T0100 H02W0301
|
|
arc: W1_H02W0001 S1_V02N0001
|
|
arc: W1_H02W0201 E1_H02W0701
|
|
arc: W1_H02W0401 E1_H02W0101
|
|
arc: W1_H02W0601 E1_H02W0601
|
|
arc: A4 V02S0101
|
|
arc: A5 V02S0101
|
|
arc: A6 V02S0101
|
|
arc: A7 V02S0101
|
|
arc: B4 N1_V02S0501
|
|
arc: B5 N1_V02S0701
|
|
arc: B6 N1_V02S0701
|
|
arc: B7 N1_V02S0501
|
|
arc: C4 V00T0100
|
|
arc: C5 V00T0100
|
|
arc: C6 V00T0100
|
|
arc: C7 V00T0100
|
|
arc: D4 N1_V02S0401
|
|
arc: D5 N1_V02S0601
|
|
arc: D6 N1_V02S0401
|
|
arc: D7 N1_V02S0601
|
|
arc: E1_H01E0101 F3
|
|
arc: F0 F5A_SLICE
|
|
arc: F1 FXA_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F3 FXB_SLICE
|
|
arc: F4 F5C_SLICE
|
|
arc: F5 FXC_SLICE
|
|
arc: F6 F5D_SLICE
|
|
arc: M0 V00T0000
|
|
arc: M1 E1_H02W0001
|
|
arc: M2 V00T0000
|
|
arc: M3 E1_H02W0201
|
|
arc: M4 V00T0000
|
|
arc: M5 E1_H02W0001
|
|
arc: M6 V00T0000
|
|
arc: S3_V06S0003 F3
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 1010010110110101
|
|
word: SLICEC.K1.INIT 1010111110111111
|
|
word: SLICED.K0.INIT 1010000010110000
|
|
word: SLICED.K1.INIT 1010101010111010
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R23C46:PLC2
|
|
arc: E1_H02E0601 S3_V06N0303
|
|
arc: N1_V02N0101 H02W0101
|
|
arc: N1_V02N0701 S1_V02N0701
|
|
arc: S1_V02S0001 S3_V06N0003
|
|
arc: S1_V02S0101 H02W0101
|
|
arc: S1_V02S0501 H01E0101
|
|
arc: V00T0000 V02N0601
|
|
arc: V00T0100 V02N0701
|
|
arc: W1_H02W0201 V02N0201
|
|
arc: W1_H02W0301 N1_V01S0100
|
|
arc: W1_H02W0401 V02S0401
|
|
arc: A0 H02E0501
|
|
arc: A2 H02E0701
|
|
arc: A6 H02E0501
|
|
arc: B0 H01W0100
|
|
arc: B2 H02E0301
|
|
arc: B6 V00B0000
|
|
arc: B7 S1_V02N0701
|
|
arc: C0 H02E0401
|
|
arc: C1 H00L0000
|
|
arc: C2 H02W0601
|
|
arc: C6 H02E0401
|
|
arc: C7 E1_H01E0101
|
|
arc: CE1 H02E0101
|
|
arc: CE3 H02E0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H00R0000
|
|
arc: D1 H00R0000
|
|
arc: D2 V02N0201
|
|
arc: D6 H01W0000
|
|
arc: D7 V00B0000
|
|
arc: E1_H01E0101 Q2
|
|
arc: E1_H02E0001 Q2
|
|
arc: E1_H02E0401 Q6
|
|
arc: F0 F5A_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00L0000 Q2
|
|
arc: H00R0000 Q6
|
|
arc: H01W0000 Q2
|
|
arc: H01W0100 Q2
|
|
arc: LSR1 H02W0501
|
|
arc: M0 V00T0000
|
|
arc: M6 V00T0100
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR3 LSR1
|
|
arc: S1_V02S0201 F0
|
|
arc: S1_V02S0401 F6
|
|
arc: S3_V06S0303 F6
|
|
arc: V00B0000 Q6
|
|
arc: W3_H06W0203 F7
|
|
word: SLICEB.K0.INIT 0100000000000000
|
|
word: SLICED.K0.INIT 1111010100110001
|
|
word: SLICEA.K0.INIT 0000100000001010
|
|
word: SLICEA.K1.INIT 1111000011111111
|
|
word: SLICED.K1.INIT 0000000011000000
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET SET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET SET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A1MUX 1
|
|
|
|
.tile R23C47:PLC2
|
|
arc: E1_H02E0001 N1_V01S0000
|
|
arc: E1_H02E0101 E1_H01W0100
|
|
arc: E1_H02E0401 S3_V06N0203
|
|
arc: E1_H02E0501 V02N0501
|
|
arc: E1_H02E0701 N1_V01S0100
|
|
arc: E3_H06E0103 S3_V06N0103
|
|
arc: H00L0100 S1_V02N0101
|
|
arc: H00R0100 S1_V02N0701
|
|
arc: N1_V02N0301 E1_H02W0301
|
|
arc: S1_V02S0201 W1_H02E0201
|
|
arc: S1_V02S0301 N1_V01S0100
|
|
arc: S1_V02S0601 E1_H01W0000
|
|
arc: V00B0000 N1_V02S0201
|
|
arc: V00B0100 S1_V02N0301
|
|
arc: V00T0000 V02N0401
|
|
arc: V01S0000 S3_V06N0103
|
|
arc: V01S0100 S3_V06N0303
|
|
arc: W1_H02W0101 S3_V06N0103
|
|
arc: W1_H02W0201 V02N0201
|
|
arc: W1_H02W0501 S1_V02N0501
|
|
arc: W1_H02W0601 E1_H02W0601
|
|
arc: W1_H02W0701 S3_V06N0203
|
|
arc: A1 F7
|
|
arc: A7 V02N0101
|
|
arc: B1 H02W0301
|
|
arc: B7 V02S0501
|
|
arc: C1 H00L0000
|
|
arc: C2 H02E0401
|
|
arc: C7 V00T0100
|
|
arc: CE0 E1_H02W0101
|
|
arc: CE1 E1_H02W0101
|
|
arc: CE2 E1_H02W0101
|
|
arc: CE3 E1_H02W0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D1 H02W0001
|
|
arc: D2 H02E0001
|
|
arc: D7 V02N0601
|
|
arc: E1_H01E0001 F1
|
|
arc: E1_H01E0101 Q6
|
|
arc: E1_H02E0301 Q3
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00L0000 Q0
|
|
arc: M0 H02E0601
|
|
arc: M1 H00L0100
|
|
arc: M2 V00B0100
|
|
arc: M3 H00R0100
|
|
arc: M4 V00B0000
|
|
arc: M6 V00T0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V02N0001 Q2
|
|
arc: N1_V02N0601 Q4
|
|
arc: V00T0100 Q1
|
|
arc: W1_H02W0001 F2
|
|
word: SLICEB.K0.INIT 0000000000001111
|
|
word: SLICED.K1.INIT 1000010000100001
|
|
word: SLICEA.K1.INIT 1000001000000000
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R23C48:PLC2
|
|
arc: E1_H02E0301 S1_V02N0301
|
|
arc: N1_V02N0401 H01E0001
|
|
arc: N1_V02N0501 E1_H01W0100
|
|
arc: S1_V02S0501 N1_V01S0100
|
|
arc: V00B0000 V02S0001
|
|
arc: V00B0100 S1_V02N0101
|
|
arc: V00T0000 V02N0401
|
|
arc: V00T0100 H02E0301
|
|
arc: W1_H02W0001 N1_V02S0001
|
|
arc: W1_H02W0301 S1_V02N0301
|
|
arc: A0 V02N0701
|
|
arc: A1 N1_V02S0501
|
|
arc: A3 H02E0701
|
|
arc: A4 S1_V02N0301
|
|
arc: A6 H02E0501
|
|
arc: A7 V02N0101
|
|
arc: B1 F3
|
|
arc: B3 V01N0001
|
|
arc: B4 N1_V02S0501
|
|
arc: B6 V02N0701
|
|
arc: B7 V00T0000
|
|
arc: C0 H02W0601
|
|
arc: C1 E1_H01W0000
|
|
arc: C3 N1_V01S0100
|
|
arc: C4 V01N0101
|
|
arc: C6 H02W0401
|
|
arc: C7 F4
|
|
arc: CE1 H00R0000
|
|
arc: CE2 H00R0000
|
|
arc: CE3 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 S1_V02N0001
|
|
arc: D1 H01E0101
|
|
arc: D3 V00T0100
|
|
arc: D4 V02N0601
|
|
arc: D6 S1_V02N0601
|
|
arc: D7 H02W0001
|
|
arc: E1_H01E0101 F0
|
|
arc: E1_H02E0001 Q2
|
|
arc: E1_H02E0201 F0
|
|
arc: E1_H02E0401 Q6
|
|
arc: E1_H02E0601 Q4
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00R0000 F6
|
|
arc: H01W0000 F0
|
|
arc: H01W0100 F0
|
|
arc: LSR0 H02E0501
|
|
arc: LSR1 H02E0501
|
|
arc: M2 V00B0000
|
|
arc: M4 H02E0401
|
|
arc: M6 V00B0100
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR0
|
|
arc: MUXLSR3 LSR0
|
|
arc: N1_V01N0001 F0
|
|
arc: N1_V02N0201 F0
|
|
arc: N1_V02N0301 F1
|
|
arc: N1_V02N0701 F7
|
|
arc: S1_V02S0001 Q2
|
|
arc: S1_V02S0201 F0
|
|
arc: S1_V02S0401 Q6
|
|
arc: S1_V02S0601 Q4
|
|
arc: S3_V06S0203 Q4
|
|
arc: V01S0000 Q2
|
|
arc: V01S0100 Q4
|
|
word: SLICEA.K0.INIT 1010000000000000
|
|
word: SLICED.K0.INIT 1110101010101010
|
|
word: SLICEC.K0.INIT 1000010000100001
|
|
word: SLICEB.K1.INIT 1001100100001001
|
|
word: SLICEA.K1.INIT 1000000001000000
|
|
word: SLICED.K1.INIT 1001000000000000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R23C49:PLC2
|
|
arc: E1_H02E0001 N1_V02S0001
|
|
arc: E1_H02E0501 V02N0501
|
|
arc: E1_H02E0601 W3_H06E0303
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: H00L0000 H02E0201
|
|
arc: H00R0000 N1_V02S0401
|
|
arc: H00R0100 S1_V02N0701
|
|
arc: N1_V02N0501 H01E0101
|
|
arc: N1_V02N0601 W3_H06E0303
|
|
arc: S1_V02S0001 N1_V02S0001
|
|
arc: S1_V02S0501 W3_H06E0303
|
|
arc: V00T0000 N1_V02S0601
|
|
arc: V00T0100 W1_H02E0301
|
|
arc: W1_H02W0101 H01E0101
|
|
arc: W1_H02W0401 V02N0401
|
|
arc: W1_H02W0601 W3_H06E0303
|
|
arc: A0 H00L0100
|
|
arc: A1 H00L0100
|
|
arc: A3 V00B0000
|
|
arc: A4 S1_V02N0101
|
|
arc: A5 S1_V02N0301
|
|
arc: A7 S1_V02N0101
|
|
arc: B1 V02S0301
|
|
arc: B2 H02E0301
|
|
arc: B3 V02N0101
|
|
arc: B4 S1_V02N0501
|
|
arc: B5 S1_V02N0501
|
|
arc: B7 S1_V02N0501
|
|
arc: C0 H02W0601
|
|
arc: C1 H02W0401
|
|
arc: C2 H02W0601
|
|
arc: C3 H02W0601
|
|
arc: C4 H02E0601
|
|
arc: C5 H02E0601
|
|
arc: C7 H02E0401
|
|
arc: CE0 W1_H02E0101
|
|
arc: CE1 W1_H02E0101
|
|
arc: CE3 H00L0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 W1_H02E0001
|
|
arc: D1 H00R0000
|
|
arc: D2 V01S0100
|
|
arc: D3 V02S0001
|
|
arc: D4 S1_V02N0601
|
|
arc: D5 S1_V02N0601
|
|
arc: D7 H02E0001
|
|
arc: E1_H01E0101 F7
|
|
arc: F0 F5A_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F4 F5C_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00L0100 Q3
|
|
arc: H01W0000 F2
|
|
arc: H01W0100 Q1
|
|
arc: M0 V00T0000
|
|
arc: M1 H00R0100
|
|
arc: M2 V00T0100
|
|
arc: M3 H02W0201
|
|
arc: M4 E1_H01E0101
|
|
arc: M6 E1_H02W0401
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: S1_V02S0601 F4
|
|
arc: V00B0000 Q6
|
|
arc: V01S0000 F4
|
|
arc: V01S0100 Q6
|
|
arc: W1_H02W0001 F0
|
|
arc: W1_H02W0301 Q1
|
|
word: SLICED.K1.INIT 1011100110000000
|
|
word: SLICEC.K0.INIT 0111111110001111
|
|
word: SLICEC.K1.INIT 0000011100001000
|
|
word: SLICEA.K0.INIT 1010000001010000
|
|
word: SLICEA.K1.INIT 1001100110010000
|
|
word: SLICEB.K0.INIT 1100000000110000
|
|
word: SLICEB.K1.INIT 1000000001000000
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R23C50:PLC2
|
|
arc: H00R0000 H02E0601
|
|
arc: N1_V02N0201 S1_V02N0701
|
|
arc: N1_V02N0401 H06W0203
|
|
arc: N1_V02N0701 S1_V02N0701
|
|
arc: V00B0000 N1_V02S0201
|
|
arc: V00T0000 V02N0601
|
|
arc: V00T0100 V02N0701
|
|
arc: W1_H02W0201 S1_V02N0201
|
|
arc: W1_H02W0401 N1_V02S0401
|
|
arc: W1_H02W0601 N1_V02S0601
|
|
arc: A0 H00R0000
|
|
arc: A1 V02N0701
|
|
arc: B1 V00T0000
|
|
arc: C0 V02N0601
|
|
arc: C1 H02E0601
|
|
arc: D0 V00T0100
|
|
arc: D1 H02E0001
|
|
arc: D3 H02E0001
|
|
arc: F0 F5A_SLICE
|
|
arc: F1 FXA_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: M0 V00B0000
|
|
arc: M1 H02W0001
|
|
arc: M2 V00B0000
|
|
arc: S1_V02S0101 F1
|
|
word: SLICEA.K0.INIT 1010000000000000
|
|
word: SLICEA.K1.INIT 1111111110000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 1111111100000000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
|
|
.tile R23C51:PLC2
|
|
arc: H00R0000 E1_H02W0601
|
|
arc: N1_V02N0301 S1_V02N0301
|
|
arc: N1_V02N0501 S1_V02N0401
|
|
arc: S1_V02S0001 N1_V02S0001
|
|
arc: S1_V02S0701 N1_V02S0701
|
|
arc: V00T0000 V02S0401
|
|
arc: W1_H02W0001 S1_V02N0001
|
|
arc: W1_H02W0401 S3_V06N0203
|
|
arc: A0 V01N0101
|
|
arc: A1 V01N0101
|
|
arc: A2 W1_H02E0501
|
|
arc: A5 S1_V02N0101
|
|
arc: A6 V02N0301
|
|
arc: B0 V02N0101
|
|
arc: B1 V01N0001
|
|
arc: B2 E1_H02W0101
|
|
arc: B5 N1_V02S0701
|
|
arc: B6 S1_V02N0701
|
|
arc: C0 H00L0100
|
|
arc: C1 H00L0100
|
|
arc: C2 V02N0601
|
|
arc: C5 V00B0100
|
|
arc: C6 Q6
|
|
arc: CE1 H00L0000
|
|
arc: CE2 H00L0000
|
|
arc: CE3 H00L0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02N0001
|
|
arc: D1 V02N0201
|
|
arc: D2 S1_V02N0001
|
|
arc: D5 H01W0000
|
|
arc: D6 H00R0100
|
|
arc: F0 F5A_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: H00L0000 F2
|
|
arc: H00L0100 Q3
|
|
arc: H00R0100 Q5
|
|
arc: H01W0000 Q3
|
|
arc: LSR0 W1_H02E0501
|
|
arc: LSR1 W1_H02E0501
|
|
arc: M0 V00B0000
|
|
arc: M3 H00R0000
|
|
arc: M5 E1_H02W0001
|
|
arc: M6 V00T0000
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR0
|
|
arc: MUXLSR3 LSR1
|
|
arc: N1_V01N0001 F5
|
|
arc: S1_V02S0101 Q3
|
|
arc: S1_V02S0501 Q5
|
|
arc: S1_V02S0601 Q6
|
|
arc: S3_V06S0003 F0
|
|
arc: V00B0000 F6
|
|
arc: V00B0100 Q5
|
|
word: SLICEB.K0.INIT 1110101010101010
|
|
word: SLICEC.K1.INIT 1011101110110000
|
|
word: SLICED.K0.INIT 1011100110000000
|
|
word: SLICEA.K0.INIT 0110111110101111
|
|
word: SLICEA.K1.INIT 0000011000001010
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R23C52:PLC2
|
|
arc: S1_V02S0301 H06E0003
|
|
arc: S1_V02S0501 N1_V02S0401
|
|
arc: V00T0000 H02W0201
|
|
arc: CE1 S1_V02N0201
|
|
arc: CLK0 G_HPBX0000
|
|
arc: M2 V00T0000
|
|
arc: MUXCLK1 CLK0
|
|
arc: S1_V02S0201 Q2
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R23C53:PLC2
|
|
arc: S3_V06S0203 N3_V06S0103
|
|
arc: W1_H02W0001 V02S0001
|
|
arc: W1_H02W0101 W3_H06E0103
|
|
arc: W1_H02W0201 S3_V06N0103
|
|
arc: W1_H02W0601 S1_V02N0601
|
|
arc: W3_H06W0203 S3_V06N0203
|
|
|
|
.tile R23C59:PLC2
|
|
arc: S3_V06S0103 E3_H06W0103
|
|
|
|
.tile R23C5:PLC2
|
|
arc: W1_H02W0501 E3_H06W0303
|
|
|
|
.tile R23C65:PLC2
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
|
|
.tile R23C71:PLC2
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
|
|
.tile R23C77:PLC2
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
|
|
.tile R23C7:PLC2
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
|
|
.tile R23C83:PLC2
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
|
|
.tile R24C13:PLC2
|
|
arc: W3_H06W0103 V06N0103
|
|
|
|
.tile R24C37:PLC2
|
|
arc: S1_V02S0601 S3_V06N0303
|
|
|
|
.tile R24C38:PLC2
|
|
arc: S1_V02S0001 E1_H02W0001
|
|
|
|
.tile R24C39:PLC2
|
|
arc: E1_H02E0601 S1_V02N0601
|
|
arc: H00L0000 H02W0201
|
|
arc: H00R0000 E1_H02W0401
|
|
arc: N1_V02N0001 S1_V02N0501
|
|
arc: N1_V02N0401 V01N0001
|
|
arc: V00B0000 S1_V02N0201
|
|
arc: A4 V02S0301
|
|
arc: A5 N1_V02S0101
|
|
arc: B4 E1_H02W0101
|
|
arc: B5 E1_H02W0301
|
|
arc: C0 H00L0000
|
|
arc: C4 V02N0201
|
|
arc: CE0 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 Q0
|
|
arc: D4 V02N0401
|
|
arc: D5 V02N0601
|
|
arc: E1_H01E0001 F4
|
|
arc: E1_H01E0101 Q0
|
|
arc: E1_H02E0001 Q0
|
|
arc: E1_H02E0201 Q0
|
|
arc: F0 F0_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: LSR0 V00B0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: N1_V01N0001 F5
|
|
arc: N1_V01N0101 F5
|
|
arc: N1_V02N0501 F5
|
|
arc: S1_V02S0501 F5
|
|
arc: S1_V02S0701 F5
|
|
word: SLICEC.K1.INIT 1000100000000000
|
|
word: SLICEA.K0.INIT 0000000000001111
|
|
word: SLICEC.K0.INIT 1100100010001000
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
|
|
.tile R24C40:PLC2
|
|
arc: E1_H02E0001 H01E0001
|
|
arc: E1_H02E0201 H01E0001
|
|
arc: E1_H02E0301 S3_V06N0003
|
|
arc: E1_H02E0401 N1_V01S0000
|
|
arc: E1_H02E0501 V06S0303
|
|
arc: E1_H02E0601 V06S0303
|
|
arc: H00R0000 H02W0401
|
|
arc: N1_V01N0001 S3_V06N0003
|
|
arc: N1_V02N0201 S1_V02N0201
|
|
arc: N1_V02N0301 S1_V02N0201
|
|
arc: N1_V02N0401 H01E0001
|
|
arc: N1_V02N0501 S1_V02N0501
|
|
arc: S1_V02S0001 H02E0001
|
|
arc: V00B0100 S1_V02N0301
|
|
arc: W1_H02W0001 N1_V01S0000
|
|
arc: W1_H02W0201 S1_V02N0201
|
|
arc: A0 S1_V02N0501
|
|
arc: A3 V01N0101
|
|
arc: A4 V02N0301
|
|
arc: A5 H02W0701
|
|
arc: B0 V01N0001
|
|
arc: B3 V02N0101
|
|
arc: B4 H00L0000
|
|
arc: B5 H01E0101
|
|
arc: C0 H00L0000
|
|
arc: C3 V02N0401
|
|
arc: C4 V02N0201
|
|
arc: C5 V00T0000
|
|
arc: CE0 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H02E0201
|
|
arc: D3 H02E0001
|
|
arc: D4 H02E0201
|
|
arc: D5 V01N0001
|
|
arc: E1_H01E0001 F4
|
|
arc: E1_H01E0101 F3
|
|
arc: F0 F0_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F5C_SLICE
|
|
arc: H00L0000 Q0
|
|
arc: LSR1 V00B0100
|
|
arc: M4 E1_H01E0101
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: V00T0000 Q0
|
|
word: SLICEA.K0.INIT 0001010001010000
|
|
word: SLICEB.K1.INIT 1110100001010000
|
|
word: SLICEC.K0.INIT 0111110111011101
|
|
word: SLICEC.K1.INIT 0001010001010000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R24C41:PLC2
|
|
arc: E1_H02E0201 S1_V02N0201
|
|
arc: E1_H02E0501 S3_V06N0303
|
|
arc: E1_H02E0701 E3_H06W0203
|
|
arc: H00L0000 V02N0201
|
|
arc: H00L0100 S1_V02N0301
|
|
arc: H00R0000 W1_H02E0601
|
|
arc: H00R0100 V02S0701
|
|
arc: N1_V02N0401 S3_V06N0203
|
|
arc: N1_V02N0501 S3_V06N0303
|
|
arc: S1_V02S0001 H01E0001
|
|
arc: S1_V02S0101 N1_V02S0101
|
|
arc: S1_V02S0201 H01E0001
|
|
arc: S1_V02S0301 H02E0301
|
|
arc: S1_V02S0501 H02W0501
|
|
arc: V00B0000 V02S0201
|
|
arc: V00B0100 H02E0501
|
|
arc: V00T0000 H02W0001
|
|
arc: W1_H02W0101 V06S0103
|
|
arc: W1_H02W0301 V02N0301
|
|
arc: W1_H02W0401 V01N0001
|
|
arc: W1_H02W0701 V01N0101
|
|
arc: A0 H02E0501
|
|
arc: A2 E1_H02W0701
|
|
arc: A7 Q7
|
|
arc: B2 N1_V02S0301
|
|
arc: B7 V02S0501
|
|
arc: C0 E1_H02W0401
|
|
arc: C1 E1_H02W0401
|
|
arc: C2 H02E0601
|
|
arc: C3 E1_H02W0401
|
|
arc: C7 V00T0000
|
|
arc: CE1 E1_H02W0101
|
|
arc: CE2 S1_V02N0601
|
|
arc: CE3 S1_V02N0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H02E0201
|
|
arc: D1 V00B0100
|
|
arc: D2 H02E0001
|
|
arc: D3 V00B0100
|
|
arc: D7 H01W0000
|
|
arc: E1_H01E0001 F1
|
|
arc: E1_H01E0101 F7
|
|
arc: E1_H02E0301 Q3
|
|
arc: F0 F5A_SLICE
|
|
arc: F1 FXA_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 Q5
|
|
arc: M0 V00B0000
|
|
arc: M1 H00R0100
|
|
arc: M2 V00B0000
|
|
arc: M3 H00R0000
|
|
arc: M4 H02E0401
|
|
arc: M5 H00L0000
|
|
arc: M7 H00L0100
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: V01S0000 Q4
|
|
word: SLICEB.K0.INIT 1010000010000000
|
|
word: SLICEA.K1.INIT 1111000000000000
|
|
word: SLICEA.K0.INIT 1010000000000000
|
|
word: SLICED.K1.INIT 1000010000100001
|
|
word: SLICEB.K1.INIT 1111000000000000
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
|
|
.tile R24C42:PLC2
|
|
arc: E1_H02E0001 V02N0001
|
|
arc: E1_H02E0501 S3_V06N0303
|
|
arc: E1_H02E0601 S1_V02N0601
|
|
arc: E3_H06E0003 H01E0001
|
|
arc: H00L0000 S1_V02N0201
|
|
arc: H00R0000 S1_V02N0601
|
|
arc: H00R0100 V02S0701
|
|
arc: N1_V02N0501 S3_V06N0303
|
|
arc: N1_V02N0701 H02E0701
|
|
arc: N3_V06N0003 S3_V06N0303
|
|
arc: S1_V02S0101 E1_H02W0101
|
|
arc: S1_V02S0501 E1_H02W0501
|
|
arc: S1_V02S0601 S3_V06N0303
|
|
arc: V00B0000 V02N0001
|
|
arc: V00B0100 H02E0501
|
|
arc: V00T0000 V02S0401
|
|
arc: V00T0100 V02N0701
|
|
arc: W1_H02W0001 S1_V02N0001
|
|
arc: W1_H02W0501 S3_V06N0303
|
|
arc: A0 V02S0501
|
|
arc: A2 V02N0501
|
|
arc: A3 V02N0701
|
|
arc: A4 S1_V02N0101
|
|
arc: A6 H00L0000
|
|
arc: A7 S1_V02N0301
|
|
arc: B0 V00T0000
|
|
arc: B2 H00L0000
|
|
arc: B3 Q3
|
|
arc: B4 H02E0301
|
|
arc: B6 V02N0501
|
|
arc: B7 V01S0000
|
|
arc: C0 F4
|
|
arc: C1 E1_H02W0401
|
|
arc: C2 H00L0100
|
|
arc: C3 V02N0601
|
|
arc: C4 V00T0100
|
|
arc: C6 V01N0101
|
|
arc: C7 E1_H02W0601
|
|
arc: CE0 H00R0000
|
|
arc: CE1 H00R0100
|
|
arc: CE3 V02S0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H01E0101
|
|
arc: D1 E1_H02W0001
|
|
arc: D2 V02S0001
|
|
arc: D3 V01S0100
|
|
arc: D4 S1_V02N0401
|
|
arc: D6 V02N0401
|
|
arc: D7 V01N0001
|
|
arc: E1_H01E0001 F3
|
|
arc: E1_H01E0101 F7
|
|
arc: E1_H02E0201 F0
|
|
arc: E1_H02E0401 F6
|
|
arc: E1_H02E0701 F7
|
|
arc: F0 F5A_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00L0100 Q1
|
|
arc: M0 V00B0000
|
|
arc: M1 H02W0001
|
|
arc: M2 H02W0601
|
|
arc: M3 H02E0201
|
|
arc: M6 V00B0100
|
|
arc: M7 H02W0201
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q7
|
|
arc: N1_V01N0101 Q2
|
|
arc: V01S0000 F2
|
|
arc: V01S0100 Q6
|
|
word: SLICED.K0.INIT 1000010000100001
|
|
word: SLICEA.K0.INIT 1110000000000000
|
|
word: SLICEA.K1.INIT 1111111111110000
|
|
word: SLICED.K1.INIT 1111000010000000
|
|
word: SLICEC.K0.INIT 1000001001000001
|
|
word: SLICEB.K0.INIT 1000001001000001
|
|
word: SLICEB.K1.INIT 1001000000001001
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R24C43:PLC2
|
|
arc: E1_H02E0001 S1_V02N0001
|
|
arc: E1_H02E0701 S1_V02N0701
|
|
arc: N1_V02N0101 S3_V06N0103
|
|
arc: N1_V02N0401 H01E0001
|
|
arc: N1_V02N0501 H01E0101
|
|
arc: N1_V02N0601 H02E0601
|
|
arc: N1_V02N0701 H01E0101
|
|
arc: S1_V02S0601 N1_V02S0301
|
|
arc: S1_V02S0701 W1_H02E0701
|
|
arc: V00B0000 H02W0401
|
|
arc: V00B0100 H02E0501
|
|
arc: V00T0100 S1_V02N0501
|
|
arc: W1_H02W0001 E1_H02W0501
|
|
arc: W1_H02W0101 S1_V02N0101
|
|
arc: W1_H02W0201 S1_V02N0201
|
|
arc: W1_H02W0401 V06S0203
|
|
arc: W1_H02W0601 S1_V02N0601
|
|
arc: W1_H02W0701 V06S0203
|
|
arc: A0 S1_V02N0701
|
|
arc: A1 S1_V02N0701
|
|
arc: A3 H02E0701
|
|
arc: A5 S1_V02N0301
|
|
arc: B0 V00T0000
|
|
arc: B2 V02N0101
|
|
arc: B5 V00B0100
|
|
arc: C0 H00L0100
|
|
arc: C1 H00L0100
|
|
arc: C2 H00L0100
|
|
arc: C5 V02N0001
|
|
arc: CE0 E1_H02W0101
|
|
arc: CE1 E1_H02W0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 Q0
|
|
arc: D2 Q2
|
|
arc: D3 H02E0201
|
|
arc: D5 V00B0000
|
|
arc: E1_H01E0001 Q0
|
|
arc: E1_H01E0101 Q2
|
|
arc: E1_H02E0101 Q1
|
|
arc: E1_H02E0201 Q2
|
|
arc: E1_H02E0301 F3
|
|
arc: E1_H02E0401 F4
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F5C_SLICE
|
|
arc: H00L0100 Q1
|
|
arc: LSR0 V00T0100
|
|
arc: M4 H02E0401
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR0
|
|
arc: N1_V01N0001 Q1
|
|
arc: N1_V01N0101 Q1
|
|
arc: V00T0000 Q2
|
|
word: SLICEA.K0.INIT 0001010101000000
|
|
word: SLICEA.K1.INIT 0000010100000101
|
|
word: SLICEB.K0.INIT 0000001100110000
|
|
word: SLICEB.K1.INIT 0000000001010101
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000100100000000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R24C44:PLC2
|
|
arc: E1_H02E0401 V01N0001
|
|
arc: H00L0000 N1_V02S0201
|
|
arc: H00L0100 V02S0101
|
|
arc: H00R0000 V02N0601
|
|
arc: H00R0100 N1_V02S0701
|
|
arc: N1_V02N0001 H01E0001
|
|
arc: N1_V02N0101 S1_V02N0101
|
|
arc: N1_V02N0201 W1_H02E0201
|
|
arc: N1_V02N0301 H01E0101
|
|
arc: N1_V02N0601 E1_H02W0601
|
|
arc: N1_V02N0701 H01E0101
|
|
arc: S1_V02S0101 N1_V02S0001
|
|
arc: S1_V02S0401 H06W0203
|
|
arc: S3_V06S0203 E3_H06W0203
|
|
arc: V00B0000 S1_V02N0001
|
|
arc: V00B0100 H02E0701
|
|
arc: V00T0000 V02S0401
|
|
arc: V00T0100 H02E0301
|
|
arc: W1_H02W0001 N1_V01S0000
|
|
arc: W1_H02W0401 V02S0401
|
|
arc: W1_H02W0601 N1_V01S0000
|
|
arc: A0 V01N0101
|
|
arc: A1 V01N0101
|
|
arc: A2 V01N0101
|
|
arc: A3 V01N0101
|
|
arc: A5 N1_V01S0100
|
|
arc: A7 N1_V01S0100
|
|
arc: B2 H01W0100
|
|
arc: B5 V02N0501
|
|
arc: B7 H02E0101
|
|
arc: C0 E1_H02W0401
|
|
arc: C2 E1_H02W0401
|
|
arc: C4 E1_H02W0601
|
|
arc: C5 E1_H02W0601
|
|
arc: C6 H02E0401
|
|
arc: C7 V00T0000
|
|
arc: CE1 H00R0000
|
|
arc: CE2 V02N0601
|
|
arc: CE3 V02N0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 S1_V02N0201
|
|
arc: D1 E1_H02W0201
|
|
arc: D2 S1_V02N0201
|
|
arc: D3 V02N0201
|
|
arc: D4 S1_V02N0401
|
|
arc: D5 H01W0000
|
|
arc: D6 W1_H02E0001
|
|
arc: D7 H02E0201
|
|
arc: E1_H01E0001 Q5
|
|
arc: E1_H01E0101 F4
|
|
arc: F0 F5A_SLICE
|
|
arc: F1 FXA_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F4 F5C_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 F6
|
|
arc: H01W0100 Q5
|
|
arc: LSR0 V00B0100
|
|
arc: LSR1 V00B0100
|
|
arc: M0 V00B0000
|
|
arc: M1 H02E0001
|
|
arc: M2 V00B0000
|
|
arc: M3 H00L0000
|
|
arc: M4 V00T0100
|
|
arc: M5 H00R0100
|
|
arc: M7 H00L0100
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR1
|
|
arc: N1_V02N0401 F6
|
|
arc: N1_V02N0501 F7
|
|
arc: S1_V02S0301 Q3
|
|
arc: S1_V02S0501 Q5
|
|
arc: S1_V02S0701 Q7
|
|
arc: V01S0000 F1
|
|
arc: V01S0100 Q3
|
|
arc: W1_H02W0101 Q3
|
|
arc: W1_H02W0501 Q7
|
|
word: SLICEA.K0.INIT 1010000000000000
|
|
word: SLICEA.K1.INIT 1010101000000000
|
|
word: SLICEB.K0.INIT 1010000010000000
|
|
word: SLICEB.K1.INIT 1010101000000000
|
|
word: SLICEC.K0.INIT 1111111111110000
|
|
word: SLICEC.K1.INIT 1100110011101100
|
|
word: SLICED.K1.INIT 1100100010110000
|
|
word: SLICED.K0.INIT 0000000000001111
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
|
|
.tile R24C45:PLC2
|
|
arc: H00R0000 V02S0601
|
|
arc: N1_V02N0301 H06E0003
|
|
arc: N1_V02N0401 E1_H02W0401
|
|
arc: N1_V02N0701 H02W0701
|
|
arc: S1_V02S0201 H01E0001
|
|
arc: S1_V02S0401 E1_H02W0401
|
|
arc: S1_V02S0701 H02W0701
|
|
arc: V00B0000 V02N0201
|
|
arc: V00B0100 V02N0301
|
|
arc: W1_H02W0101 H01E0101
|
|
arc: W1_H02W0501 S1_V02N0501
|
|
arc: A0 H02W0701
|
|
arc: A3 H02W0701
|
|
arc: B0 V00B0000
|
|
arc: B3 H00R0000
|
|
arc: C0 E1_H02W0401
|
|
arc: C2 S1_V02N0401
|
|
arc: C3 S1_V02N0401
|
|
arc: C6 V00T0000
|
|
arc: CE0 V02S0201
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V00B0100
|
|
arc: D3 V02N0201
|
|
arc: D6 V02N0401
|
|
arc: E1_H01E0001 Q0
|
|
arc: E1_H01E0101 F2
|
|
arc: E1_H02E0001 Q0
|
|
arc: E1_H02E0201 Q0
|
|
arc: F0 F0_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: LSR1 E1_H02W0501
|
|
arc: M2 V00B0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: N1_V02N0601 F6
|
|
arc: V00T0000 Q0
|
|
word: SLICEB.K0.INIT 0000111100001111
|
|
word: SLICEB.K1.INIT 0000101100001111
|
|
word: SLICED.K0.INIT 0000000000001111
|
|
word: SLICEA.K0.INIT 0100000000000000
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET SET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
|
|
.tile R24C46:PLC2
|
|
arc: E1_H02E0001 V02S0001
|
|
arc: E1_H02E0201 S1_V02N0201
|
|
arc: E1_H02E0601 S1_V02N0601
|
|
arc: H00L0100 N1_V02S0301
|
|
arc: H00R0100 S1_V02N0701
|
|
arc: N1_V01N0001 S3_V06N0003
|
|
arc: N1_V02N0201 H02W0201
|
|
arc: N1_V02N0401 H01E0001
|
|
arc: N1_V02N0701 H01E0101
|
|
arc: S1_V02S0501 V01N0101
|
|
arc: V00B0100 V02N0301
|
|
arc: V01S0100 S3_V06N0303
|
|
arc: W1_H02W0201 V01N0001
|
|
arc: W1_H02W0401 V01N0001
|
|
arc: W1_H02W0701 E1_H02W0701
|
|
arc: A0 E1_H02W0701
|
|
arc: A1 S1_V02N0501
|
|
arc: A3 E1_H02W0701
|
|
arc: A6 H00L0000
|
|
arc: A7 V02N0101
|
|
arc: B0 H02W0101
|
|
arc: B1 H00R0100
|
|
arc: B3 V02S0101
|
|
arc: B4 V02N0701
|
|
arc: B6 V00B0000
|
|
arc: B7 V01S0000
|
|
arc: C0 H02W0601
|
|
arc: C1 H00L0000
|
|
arc: C2 S1_V02N0401
|
|
arc: C3 N1_V01N0001
|
|
arc: C4 V00T0000
|
|
arc: C6 W1_H02E0401
|
|
arc: C7 V00T0000
|
|
arc: CE0 N1_V02S0201
|
|
arc: CE3 H00L0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02N0201
|
|
arc: D1 H00R0000
|
|
arc: D3 H02W0201
|
|
arc: D4 V00B0000
|
|
arc: D6 H02E0001
|
|
arc: D7 H02E0201
|
|
arc: E1_H01E0001 F1
|
|
arc: E1_H01E0101 F7
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00L0000 Q0
|
|
arc: H00R0000 Q6
|
|
arc: LSR1 E1_H02W0501
|
|
arc: M2 V00B0100
|
|
arc: M6 N1_V01N0101
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR3 LSR1
|
|
arc: N1_V01N0101 F2
|
|
arc: N1_V02N0601 F6
|
|
arc: S1_V02S0701 F7
|
|
arc: V00B0000 Q6
|
|
arc: V00T0000 Q0
|
|
arc: V01S0000 Q6
|
|
arc: W1_H02W0601 F4
|
|
word: SLICED.K1.INIT 1111001101010001
|
|
word: SLICEA.K0.INIT 0100000000000000
|
|
word: SLICEB.K1.INIT 0000101100001111
|
|
word: SLICEB.K0.INIT 0000111100001111
|
|
word: SLICED.K0.INIT 0100010000000100
|
|
word: SLICEC.K0.INIT 0000000011000000
|
|
word: SLICEA.K1.INIT 1000100010000000
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET SET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET SET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R24C47:PLC2
|
|
arc: E1_H02E0101 N1_V01S0100
|
|
arc: E1_H02E0201 V01N0001
|
|
arc: E1_H02E0401 S1_V02N0401
|
|
arc: E1_H02E0701 N1_V02S0701
|
|
arc: H00L0100 H02W0301
|
|
arc: H00R0000 V02N0401
|
|
arc: N1_V02N0101 H02W0101
|
|
arc: N1_V02N0201 H01E0001
|
|
arc: N1_V02N0401 S3_V06N0203
|
|
arc: N1_V02N0501 E1_H02W0501
|
|
arc: S1_V02S0401 H06W0203
|
|
arc: S1_V02S0701 H01E0101
|
|
arc: V00B0000 H02E0601
|
|
arc: V00B0100 N1_V02S0301
|
|
arc: W1_H02W0101 V06N0103
|
|
arc: W1_H02W0201 V06N0103
|
|
arc: W1_H02W0501 V01N0101
|
|
arc: W1_H02W0601 N1_V01S0000
|
|
arc: A0 H00L0100
|
|
arc: A3 F5
|
|
arc: A5 E1_H01W0000
|
|
arc: A6 V02S0301
|
|
arc: B0 H02W0101
|
|
arc: B3 V02S0301
|
|
arc: B4 S1_V02N0501
|
|
arc: B5 H02W0101
|
|
arc: B6 H02W0301
|
|
arc: C0 E1_H01W0000
|
|
arc: C2 H02W0601
|
|
arc: C3 H00R0100
|
|
arc: C5 V02N0001
|
|
arc: C6 Q6
|
|
arc: CE0 V02N0201
|
|
arc: CE2 V02S0601
|
|
arc: CE3 V02N0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 S1_V02N0001
|
|
arc: D2 H02W0201
|
|
arc: D3 F0
|
|
arc: D4 H02E0201
|
|
arc: D5 N1_V02S0601
|
|
arc: D6 H01W0000
|
|
arc: E1_H01E0001 F2
|
|
arc: E1_H01E0101 F6
|
|
arc: F0 F5A_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: H00R0100 Q7
|
|
arc: H01W0000 Q1
|
|
arc: M0 V00T0000
|
|
arc: M1 H02E0001
|
|
arc: M4 V00B0000
|
|
arc: M6 V00B0100
|
|
arc: M7 H00R0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V02N0601 Q4
|
|
arc: S3_V06S0203 F4
|
|
arc: V00T0000 F2
|
|
arc: V01S0000 F3
|
|
arc: V01S0100 F4
|
|
arc: W1_H02W0401 F4
|
|
arc: W3_H06W0203 F4
|
|
word: SLICEC.K0.INIT 0000000011001100
|
|
word: SLICEB.K1.INIT 1000001000000000
|
|
word: SLICED.K0.INIT 1000010000100001
|
|
word: SLICEC.K1.INIT 1101000000001101
|
|
word: SLICEA.K0.INIT 1010001001010001
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0000000000001111
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R24C48:PLC2
|
|
arc: E1_H02E0101 S1_V02N0101
|
|
arc: E1_H02E0201 V06S0103
|
|
arc: H00L0000 V02S0201
|
|
arc: H00L0100 H02W0101
|
|
arc: H00R0000 V02S0601
|
|
arc: H00R0100 H02E0701
|
|
arc: N1_V02N0101 S3_V06N0103
|
|
arc: N1_V02N0601 S1_V02N0301
|
|
arc: N1_V02N0701 H02W0701
|
|
arc: S1_V02S0601 H02W0601
|
|
arc: S3_V06S0003 N1_V02S0001
|
|
arc: V00T0000 V02S0401
|
|
arc: V00T0100 V02N0701
|
|
arc: W1_H02W0101 S1_V02N0101
|
|
arc: W1_H02W0201 N1_V01S0000
|
|
arc: W1_H02W0301 V02N0301
|
|
arc: W1_H02W0501 V02N0501
|
|
arc: W1_H02W0601 V02S0601
|
|
arc: A1 H00R0000
|
|
arc: A2 H02W0501
|
|
arc: A4 V00T0100
|
|
arc: A5 V02N0101
|
|
arc: B0 V02N0301
|
|
arc: B1 V02N0301
|
|
arc: B2 E1_H02W0101
|
|
arc: B4 H01E0101
|
|
arc: B5 H02E0101
|
|
arc: C0 N1_V01S0100
|
|
arc: C1 V02N0401
|
|
arc: C2 E1_H02W0401
|
|
arc: C3 E1_H02W0601
|
|
arc: C4 H01E0001
|
|
arc: CE1 S1_V02N0201
|
|
arc: CE2 H00L0000
|
|
arc: CE3 H00L0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H02E0201
|
|
arc: D1 V02S0001
|
|
arc: D2 E1_H02W0001
|
|
arc: D3 E1_H02W0001
|
|
arc: D4 V02S0401
|
|
arc: D5 H00R0100
|
|
arc: E1_H02E0701 F5
|
|
arc: F0 F5A_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: H01W0000 Q3
|
|
arc: M0 V00T0000
|
|
arc: M3 H00L0100
|
|
arc: M4 H02E0401
|
|
arc: M6 H02W0401
|
|
arc: M7 H02W0201
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q7
|
|
arc: N1_V01N0101 Q4
|
|
arc: N1_V02N0001 F2
|
|
arc: N1_V02N0201 F2
|
|
arc: N1_V02N0401 Q6
|
|
arc: S1_V02S0101 F3
|
|
arc: S1_V02S0701 F5
|
|
arc: S3_V06S0303 F5
|
|
arc: V01S0000 F0
|
|
arc: V01S0100 F4
|
|
arc: W1_H02W0701 F5
|
|
word: SLICEC.K1.INIT 0000000000010001
|
|
word: SLICEC.K0.INIT 1000100000001000
|
|
word: SLICEA.K0.INIT 1100000000110000
|
|
word: SLICEA.K1.INIT 1100001110000010
|
|
word: SLICEB.K0.INIT 0000010000000000
|
|
word: SLICEB.K1.INIT 0000000011110000
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R24C49:PLC2
|
|
arc: E1_H02E0001 V01N0001
|
|
arc: E1_H02E0101 S1_V02N0101
|
|
arc: E1_H02E0301 S1_V02N0301
|
|
arc: H00R0000 E1_H02W0601
|
|
arc: H00R0100 V02S0501
|
|
arc: N1_V02N0101 H02E0101
|
|
arc: N1_V02N0401 S1_V02N0101
|
|
arc: N1_V02N0501 S1_V02N0501
|
|
arc: N1_V02N0701 S3_V06N0203
|
|
arc: S1_V02S0601 E1_H02W0601
|
|
arc: V00B0000 V02N0001
|
|
arc: V00T0000 H02E0201
|
|
arc: V00T0100 S1_V02N0501
|
|
arc: V01S0000 S3_V06N0103
|
|
arc: V01S0100 S3_V06N0303
|
|
arc: W1_H02W0101 V06S0103
|
|
arc: W1_H02W0201 S3_V06N0103
|
|
arc: W1_H02W0401 V01N0001
|
|
arc: W1_H02W0501 S1_V02N0501
|
|
arc: W1_H02W0601 E1_H02W0601
|
|
arc: W1_H02W0701 E1_H02W0601
|
|
arc: A0 H02E0701
|
|
arc: A1 H02E0701
|
|
arc: A4 V00T0100
|
|
arc: A5 V00T0100
|
|
arc: B0 S1_V02N0101
|
|
arc: B1 S1_V02N0101
|
|
arc: B5 H00R0000
|
|
arc: B7 S1_V02N0501
|
|
arc: C1 E1_H02W0601
|
|
arc: C4 E1_H02W0601
|
|
arc: C5 V02S0001
|
|
arc: C6 V00T0100
|
|
arc: C7 V02S0001
|
|
arc: CE3 S1_V02N0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H00R0000
|
|
arc: D1 N1_V01S0000
|
|
arc: D3 N1_V01S0000
|
|
arc: D4 H00R0100
|
|
arc: D5 H00R0100
|
|
arc: E1_H02E0501 F5
|
|
arc: E1_H02E0701 Q7
|
|
arc: F0 F5A_SLICE
|
|
arc: F1 FXA_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F4 F5C_SLICE
|
|
arc: F5 FXC_SLICE
|
|
arc: F6 F5D_SLICE
|
|
arc: H00L0100 F1
|
|
arc: LSR1 H02W0301
|
|
arc: M0 V00B0000
|
|
arc: M1 E1_H02W0001
|
|
arc: M2 V00B0000
|
|
arc: M4 V00T0000
|
|
arc: M5 E1_H02W0001
|
|
arc: M6 V00T0000
|
|
arc: M7 H00L0100
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR3 LSR1
|
|
arc: S1_V02S0701 Q7
|
|
word: SLICEA.K0.INIT 1000100000000000
|
|
word: SLICEA.K1.INIT 1111111110000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 1111111100000000
|
|
word: SLICEC.K0.INIT 1111101010101010
|
|
word: SLICEC.K1.INIT 1111111011111010
|
|
word: SLICED.K0.INIT 1111000011110000
|
|
word: SLICED.K1.INIT 1111110011111100
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET SET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
|
|
.tile R24C50:PLC2
|
|
arc: E1_H02E0501 V02N0501
|
|
arc: H00R0100 H02E0501
|
|
arc: N1_V02N0601 H02W0601
|
|
arc: N1_V02N0701 W1_H02E0701
|
|
arc: S1_V02S0601 H02W0601
|
|
arc: V00B0100 V02S0101
|
|
arc: W1_H02W0101 V02N0101
|
|
arc: W1_H02W0301 V02N0301
|
|
arc: A0 W1_H02E0701
|
|
arc: A3 H02E0701
|
|
arc: A4 S1_V02N0101
|
|
arc: A7 H02W0701
|
|
arc: B0 E1_H02W0301
|
|
arc: B3 H02E0101
|
|
arc: B4 V01S0000
|
|
arc: B7 H02E0301
|
|
arc: C0 H02W0601
|
|
arc: C4 E1_H01E0101
|
|
arc: C7 V00T0000
|
|
arc: CE0 H00R0100
|
|
arc: CE3 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02N0001
|
|
arc: D3 S1_V02N0001
|
|
arc: D4 S1_V02N0401
|
|
arc: D7 V00B0000
|
|
arc: E1_H01E0101 F3
|
|
arc: F0 F0_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: LSR0 H02W0501
|
|
arc: M6 V00B0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR3 LSR0
|
|
arc: V00B0000 Q6
|
|
arc: V00T0000 Q0
|
|
arc: V01S0000 F7
|
|
arc: W1_H02W0001 Q0
|
|
arc: W1_H02W0401 Q6
|
|
arc: W1_H02W0601 Q6
|
|
arc: W3_H06W0203 F4
|
|
word: SLICEC.K0.INIT 0000000000000001
|
|
word: SLICED.K1.INIT 0001000100010000
|
|
word: SLICEB.K1.INIT 1100110010001000
|
|
word: SLICEA.K0.INIT 0100000000000000
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET SET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET SET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R24C51:PLC2
|
|
arc: N1_V02N0601 S1_V02N0601
|
|
arc: S1_V02S0001 W1_H02E0001
|
|
arc: S1_V02S0401 N1_V02S0401
|
|
arc: V00T0000 V02N0401
|
|
arc: W1_H02W0001 V02N0001
|
|
arc: W1_H02W0501 V02N0501
|
|
arc: W1_H02W0601 S1_V02N0601
|
|
arc: W1_H02W0701 V01N0101
|
|
arc: A0 H00L0100
|
|
arc: A1 H00L0100
|
|
arc: A2 E1_H01E0001
|
|
arc: A7 H02E0501
|
|
arc: B2 V01N0001
|
|
arc: C0 V02N0601
|
|
arc: C1 V02N0601
|
|
arc: C2 H00L0100
|
|
arc: CE0 H00R0100
|
|
arc: CE1 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 Q0
|
|
arc: D2 Q2
|
|
arc: D7 V02N0601
|
|
arc: E1_H01E0001 Q0
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00L0100 Q1
|
|
arc: H00R0100 F7
|
|
arc: LSR1 V00T0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR1
|
|
arc: N1_V01N0001 Q1
|
|
arc: N1_V01N0101 Q2
|
|
arc: N1_V02N0001 Q0
|
|
arc: N1_V02N0101 Q1
|
|
arc: N1_V02N0201 Q0
|
|
arc: N1_V02N0301 Q1
|
|
arc: V01S0100 Q0
|
|
word: SLICEA.K0.INIT 0101000010100000
|
|
word: SLICEA.K1.INIT 0101000001010000
|
|
word: SLICEB.K0.INIT 0100110010000000
|
|
word: SLICED.K1.INIT 1111111110101010
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R24C52:PLC2
|
|
arc: W1_H02W0301 V02S0301
|
|
|
|
.tile R24C7:PLC2
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
|
|
.tile R25C13:PLC2
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
|
|
.tile R25C14:PLC2
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: C0 V02N0401
|
|
arc: D0 H02W0201
|
|
arc: E3_H06E0003 F0
|
|
arc: F0 F0_SLICE
|
|
word: SLICEA.K0.INIT 0000111100000000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
|
|
.tile R25C15:PLC2
|
|
arc: W1_H02W0201 N3_V06S0103
|
|
|
|
.tile R25C16:PLC2
|
|
arc: S1_V02S0401 N3_V06S0203
|
|
|
|
.tile R25C17:PLC2
|
|
arc: S1_V02S0101 N3_V06S0103
|
|
arc: S1_V02S0501 H02W0501
|
|
|
|
.tile R25C18:PLC2
|
|
arc: W1_H02W0501 N3_V06S0303
|
|
|
|
.tile R25C19:PLC2
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
|
|
.tile R25C20:PLC2
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
|
|
.tile R25C23:PLC2
|
|
arc: S1_V02S0201 N3_V06S0103
|
|
|
|
.tile R25C24:PLC2
|
|
arc: S1_V02S0301 N3_V06S0003
|
|
|
|
.tile R25C25:PLC2
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
|
|
.tile R25C26:PLC2
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
arc: S1_V02S0701 N3_V06S0203
|
|
|
|
.tile R25C27:PLC2
|
|
arc: N1_V02N0201 S1_V02N0201
|
|
arc: S1_V02S0101 N3_V06S0103
|
|
arc: S1_V02S0501 N3_V06S0303
|
|
arc: S1_V02S0701 N3_V06S0203
|
|
|
|
.tile R25C2:PLC2
|
|
arc: E3_H06E0303 H01E0101
|
|
|
|
.tile R25C31:PLC2
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
arc: S1_V02S0701 E1_H02W0701
|
|
|
|
.tile R25C32:PLC2
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
arc: S1_V02S0701 H02W0701
|
|
|
|
.tile R25C33:PLC2
|
|
arc: E1_H02E0701 N3_V06S0203
|
|
arc: W1_H02W0701 N3_V06S0203
|
|
|
|
.tile R25C34:PLC2
|
|
arc: E1_H02E0001 N3_V06S0003
|
|
arc: E1_H02E0401 N3_V06S0203
|
|
arc: S1_V02S0101 N3_V06S0103
|
|
arc: S1_V02S0701 H02E0701
|
|
arc: V01S0000 S3_V06N0103
|
|
|
|
.tile R25C35:PLC2
|
|
arc: S1_V02S0001 H02E0001
|
|
arc: S1_V02S0101 S3_V06N0103
|
|
arc: S1_V02S0401 H02E0401
|
|
arc: S1_V02S0601 N3_V06S0303
|
|
arc: S1_V02S0701 W1_H02E0701
|
|
arc: V01S0000 N3_V06S0103
|
|
|
|
.tile R25C36:PLC2
|
|
arc: E1_H02E0701 N3_V06S0203
|
|
arc: V01S0000 N3_V06S0103
|
|
|
|
.tile R25C37:PLC2
|
|
arc: E1_H01E0101 W3_H06E0203
|
|
arc: E1_H02E0401 W3_H06E0203
|
|
arc: E1_H02E0601 V02S0601
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
arc: N1_V02N0101 S1_V02N0001
|
|
arc: S1_V02S0101 N3_V06S0103
|
|
arc: S1_V02S0201 W3_H06E0103
|
|
arc: S1_V02S0401 N3_V06S0203
|
|
arc: S1_V02S0501 N3_V06S0303
|
|
arc: S1_V02S0701 H02E0701
|
|
arc: S3_V06S0103 W3_H06E0103
|
|
arc: S3_V06S0303 N3_V06S0203
|
|
arc: V01S0100 S3_V06N0303
|
|
|
|
.tile R25C38:PLC2
|
|
arc: E1_H02E0001 V02S0001
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: E3_H06E0103 H01E0101
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
arc: H00R0000 H02E0601
|
|
arc: H00R0100 H02W0701
|
|
arc: N1_V02N0501 E1_H02W0501
|
|
arc: N3_V06N0103 S1_V02N0201
|
|
arc: S1_V02S0201 H02W0201
|
|
arc: S1_V02S0601 N3_V06S0303
|
|
arc: S1_V02S0701 W1_H02E0701
|
|
arc: A5 V02N0101
|
|
arc: B5 V02N0501
|
|
arc: C5 V00T0100
|
|
arc: CE1 H00R0100
|
|
arc: CE2 H02W0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D5 E1_H01W0100
|
|
arc: E1_H02E0601 Q4
|
|
arc: E1_H02E0701 F5
|
|
arc: F5 F5_SLICE
|
|
arc: M3 H00R0000
|
|
arc: M4 H02E0401
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: V00T0100 Q3
|
|
word: SLICEC.K1.INIT 1000001001000001
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R25C39:PLC2
|
|
arc: E1_H02E0001 N3_V06S0003
|
|
arc: E1_H02E0501 N3_V06S0303
|
|
arc: E1_H02E0601 V01N0001
|
|
arc: E3_H06E0003 N3_V06S0003
|
|
arc: H00L0000 H02W0201
|
|
arc: H00R0000 V02N0401
|
|
arc: H00R0100 V02S0501
|
|
arc: N1_V01N0001 N3_V06S0003
|
|
arc: N1_V02N0101 H02W0101
|
|
arc: N1_V02N0201 S1_V02N0201
|
|
arc: N1_V02N0401 S1_V02N0101
|
|
arc: N1_V02N0501 N3_V06S0303
|
|
arc: N1_V02N0601 S1_V02N0301
|
|
arc: S1_V02S0101 H02W0101
|
|
arc: S1_V02S0201 H02W0201
|
|
arc: S1_V02S0501 H02W0501
|
|
arc: S3_V06S0003 N3_V06S0003
|
|
arc: S3_V06S0103 N3_V06S0003
|
|
arc: S3_V06S0303 N3_V06S0303
|
|
arc: V00B0100 H02E0701
|
|
arc: V00T0000 V02N0601
|
|
arc: V01S0100 N3_V06S0303
|
|
arc: W1_H02W0101 V01N0101
|
|
arc: W1_H02W0201 N3_V06S0103
|
|
arc: W1_H02W0701 V02S0701
|
|
arc: A1 V02N0701
|
|
arc: A4 V02N0101
|
|
arc: B1 Q1
|
|
arc: B4 V02N0501
|
|
arc: C1 H00L0000
|
|
arc: C4 H02E0601
|
|
arc: CE0 H00R0100
|
|
arc: CE1 H00R0100
|
|
arc: CE2 S1_V02N0601
|
|
arc: CE3 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D1 V00T0100
|
|
arc: D4 V00B0000
|
|
arc: E1_H01E0001 F0
|
|
arc: E1_H01E0101 F4
|
|
arc: F0 F5A_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: H01W0100 Q7
|
|
arc: M0 V00B0100
|
|
arc: M1 H02E0001
|
|
arc: M3 E1_H02W0201
|
|
arc: M4 V00T0000
|
|
arc: M7 H00R0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: V00B0000 Q4
|
|
arc: V00T0100 Q3
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 1001000000001001
|
|
word: SLICEC.K0.INIT 1000001001000001
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
|
|
.tile R25C40:PLC2
|
|
arc: E1_H02E0201 V02N0201
|
|
arc: H00L0000 V02N0201
|
|
arc: N1_V02N0001 H02E0001
|
|
arc: N1_V02N0101 H02W0101
|
|
arc: N1_V02N0301 H02W0301
|
|
arc: N1_V02N0401 E1_H01W0000
|
|
arc: N1_V02N0501 S3_V06N0303
|
|
arc: N1_V02N0601 H01E0001
|
|
arc: S1_V02S0101 N3_V06S0103
|
|
arc: S1_V02S0201 N3_V06S0103
|
|
arc: S1_V02S0401 H06E0203
|
|
arc: S1_V02S0501 N3_V06S0303
|
|
arc: S3_V06S0103 N3_V06S0103
|
|
arc: V00B0100 V02N0301
|
|
arc: V00T0000 N1_V02S0401
|
|
arc: V01S0100 N3_V06S0303
|
|
arc: W1_H02W0101 N3_V06S0103
|
|
arc: W1_H02W0201 N3_V06S0103
|
|
arc: W1_H02W0501 N3_V06S0303
|
|
arc: A0 H00L0000
|
|
arc: A2 H02W0701
|
|
arc: A5 V02N0101
|
|
arc: A6 H02E0501
|
|
arc: B2 H02W0301
|
|
arc: B3 H02W0301
|
|
arc: B5 S1_V02N0501
|
|
arc: B6 V00T0000
|
|
arc: C0 N1_V01N0001
|
|
arc: C1 F4
|
|
arc: C2 V02N0601
|
|
arc: C3 E1_H01W0000
|
|
arc: C5 S1_V02N0001
|
|
arc: C6 V01N0101
|
|
arc: CE0 E1_H02W0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02S0001
|
|
arc: D1 V02N0001
|
|
arc: D2 H01E0101
|
|
arc: D5 E1_H01W0100
|
|
arc: D6 S1_V02N0601
|
|
arc: E1_H01E0001 F1
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F4 F5C_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: LSR0 V00B0100
|
|
arc: M2 H02E0601
|
|
arc: M4 V00B0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: N1_V01N0001 Q0
|
|
arc: N1_V01N0101 Q0
|
|
arc: N1_V02N0201 Q0
|
|
arc: V00B0000 F6
|
|
arc: V01S0000 F2
|
|
word: SLICEA.K0.INIT 0000010101010000
|
|
word: SLICEB.K0.INIT 1110000000000000
|
|
word: SLICEB.K1.INIT 1111110011111100
|
|
word: SLICED.K0.INIT 1000001001000001
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000100100000000
|
|
word: SLICEA.K1.INIT 0000000000001111
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
|
|
.tile R25C41:PLC2
|
|
arc: E1_H02E0001 S1_V02N0001
|
|
arc: E1_H02E0301 N1_V02S0301
|
|
arc: E1_H02E0701 V06N0203
|
|
arc: H00L0000 H02E0201
|
|
arc: H00L0100 N1_V02S0101
|
|
arc: H00R0100 S1_V02N0701
|
|
arc: N1_V02N0201 H06E0103
|
|
arc: N1_V02N0301 S1_V02N0201
|
|
arc: N1_V02N0501 E1_H02W0501
|
|
arc: N1_V02N0601 S3_V06N0303
|
|
arc: S1_V02S0001 W1_H02E0001
|
|
arc: S1_V02S0401 H01E0001
|
|
arc: S1_V02S0501 E1_H02W0501
|
|
arc: S1_V02S0601 N3_V06S0303
|
|
arc: S3_V06S0003 N3_V06S0303
|
|
arc: V00B0100 S1_V02N0101
|
|
arc: V00T0000 H02E0201
|
|
arc: W1_H02W0201 E1_H02W0201
|
|
arc: A1 H01E0001
|
|
arc: A3 V02N0501
|
|
arc: A4 V02S0101
|
|
arc: A6 H00L0000
|
|
arc: B1 Q1
|
|
arc: B3 V02N0101
|
|
arc: B4 V02S0501
|
|
arc: B6 H02W0301
|
|
arc: C0 V02N0401
|
|
arc: C1 V02N0401
|
|
arc: C3 H02W0601
|
|
arc: C4 V01N0101
|
|
arc: C6 S1_V02N0201
|
|
arc: CE0 H00R0000
|
|
arc: CE1 H00R0000
|
|
arc: CE3 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H02E0201
|
|
arc: D1 H02E0201
|
|
arc: D3 N1_V01S0000
|
|
arc: D4 V01N0001
|
|
arc: D6 S1_V02N0401
|
|
arc: E1_H01E0001 F2
|
|
arc: E1_H01E0101 F0
|
|
arc: F0 F5A_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: H00R0000 F6
|
|
arc: H01W0000 Q7
|
|
arc: H01W0100 Q7
|
|
arc: LSR0 V00T0000
|
|
arc: LSR1 V00T0000
|
|
arc: M0 V00B0100
|
|
arc: M1 H00L0100
|
|
arc: M2 V00B0000
|
|
arc: M3 H00R0100
|
|
arc: M7 H02W0201
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR3 LSR0
|
|
arc: N1_V01N0001 F0
|
|
arc: N1_V01N0101 Q3
|
|
arc: S1_V02S0301 Q1
|
|
arc: V00B0000 F4
|
|
arc: V01S0000 Q3
|
|
arc: W1_H02W0101 Q1
|
|
arc: W1_H02W0301 Q3
|
|
arc: W1_H02W0701 Q7
|
|
word: SLICEA.K0.INIT 1111111111110000
|
|
word: SLICEA.K1.INIT 1111111101000000
|
|
word: SLICED.K0.INIT 1110101010101010
|
|
word: SLICEC.K0.INIT 1000001001000001
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 1000010000100001
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R25C42:PLC2
|
|
arc: E1_H02E0001 V02N0001
|
|
arc: E1_H02E0101 V02N0101
|
|
arc: E1_H02E0201 V01N0001
|
|
arc: E1_H02E0401 V01N0001
|
|
arc: E1_H02E0501 V01N0101
|
|
arc: E1_H02E0601 V02S0601
|
|
arc: E1_H02E0701 V02N0701
|
|
arc: H00L0100 H02E0301
|
|
arc: H00R0000 S1_V02N0401
|
|
arc: H00R0100 E1_H02W0501
|
|
arc: N1_V02N0001 H01E0001
|
|
arc: N1_V02N0401 S1_V02N0101
|
|
arc: N1_V02N0501 N3_V06S0303
|
|
arc: N1_V02N0601 N3_V06S0303
|
|
arc: N1_V02N0701 H02E0701
|
|
arc: S1_V02S0001 H06E0003
|
|
arc: S1_V02S0101 H06W0103
|
|
arc: S1_V02S0301 N3_V06S0003
|
|
arc: S1_V02S0601 N3_V06S0303
|
|
arc: S3_V06S0103 N3_V06S0003
|
|
arc: S3_V06S0203 N3_V06S0103
|
|
arc: S3_V06S0303 N3_V06S0303
|
|
arc: V00B0000 V02N0201
|
|
arc: V01S0000 N3_V06S0103
|
|
arc: V01S0100 N3_V06S0303
|
|
arc: W1_H02W0101 H01E0101
|
|
arc: W1_H02W0201 E1_H02W0201
|
|
arc: W1_H02W0301 E1_H02W0301
|
|
arc: W1_H02W0601 N3_V06S0303
|
|
arc: A4 S1_V02N0101
|
|
arc: A5 S1_V02N0301
|
|
arc: A6 S1_V02N0101
|
|
arc: A7 S1_V02N0301
|
|
arc: B4 V02N0701
|
|
arc: B5 V02N0701
|
|
arc: B6 V02N0501
|
|
arc: B7 V02N0501
|
|
arc: C4 V02N0001
|
|
arc: C5 V02N0201
|
|
arc: C6 V02N0001
|
|
arc: C7 V02N0201
|
|
arc: CE3 V02N0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D4 V00B0000
|
|
arc: D5 V02S0601
|
|
arc: D6 V00B0000
|
|
arc: D7 V02S0601
|
|
arc: F0 F5A_SLICE
|
|
arc: F1 FXA_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F3 FXB_SLICE
|
|
arc: F4 F5C_SLICE
|
|
arc: F5 FXC_SLICE
|
|
arc: F6 F5D_SLICE
|
|
arc: M0 V00B0100
|
|
arc: M1 H00R0000
|
|
arc: M2 V00B0100
|
|
arc: M3 H00R0100
|
|
arc: M4 V00B0100
|
|
arc: M5 H00R0000
|
|
arc: M6 V00B0100
|
|
arc: M7 H00L0100
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 F3
|
|
arc: N1_V01N0101 Q7
|
|
arc: V00B0100 Q7
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 0000000010010000
|
|
word: SLICEC.K1.INIT 1001000000000000
|
|
word: SLICED.K0.INIT 0000000000001001
|
|
word: SLICED.K1.INIT 0000000010010000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R25C43:PLC2
|
|
arc: E1_H02E0401 V01N0001
|
|
arc: E1_H02E0501 V01N0101
|
|
arc: E1_H02E0601 V01N0001
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
arc: H00L0000 S1_V02N0001
|
|
arc: N1_V01N0101 N3_V06S0203
|
|
arc: N1_V02N0001 E1_H01W0000
|
|
arc: N1_V02N0101 V01N0101
|
|
arc: N1_V02N0301 V01N0101
|
|
arc: N1_V02N0501 S1_V02N0401
|
|
arc: N1_V02N0601 H02E0601
|
|
arc: N1_V02N0701 S3_V06N0203
|
|
arc: N3_V06N0103 V01N0101
|
|
arc: N3_V06N0303 V01N0101
|
|
arc: S1_V02S0201 E1_H02W0201
|
|
arc: S1_V02S0301 V01N0101
|
|
arc: S3_V06S0103 N3_V06S0003
|
|
arc: S3_V06S0203 W3_H06E0203
|
|
arc: S3_V06S0303 N3_V06S0303
|
|
arc: V00B0100 H02E0501
|
|
arc: V00T0000 H02E0001
|
|
arc: V00T0100 E1_H02W0301
|
|
arc: V01S0100 N3_V06S0303
|
|
arc: W1_H02W0201 V02N0201
|
|
arc: W1_H02W0501 N3_V06S0303
|
|
arc: A4 N1_V01N0101
|
|
arc: A5 V00T0000
|
|
arc: A6 H02E0701
|
|
arc: A7 V00T0100
|
|
arc: B4 E1_H02W0301
|
|
arc: B5 H02E0101
|
|
arc: B6 E1_H02W0301
|
|
arc: B7 H02E0101
|
|
arc: C4 H02E0401
|
|
arc: C5 V00T0100
|
|
arc: C6 H02E0601
|
|
arc: C7 V00T0000
|
|
arc: D4 H02E0001
|
|
arc: D5 H02E0201
|
|
arc: D6 H02E0201
|
|
arc: D7 H02E0201
|
|
arc: F0 F5A_SLICE
|
|
arc: F1 FXA_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F3 FXB_SLICE
|
|
arc: F4 F5C_SLICE
|
|
arc: F5 FXC_SLICE
|
|
arc: F6 F5D_SLICE
|
|
arc: M0 V00B0100
|
|
arc: M1 W1_H02E0001
|
|
arc: M2 V00B0100
|
|
arc: M3 H00L0000
|
|
arc: M4 V00B0100
|
|
arc: M5 W1_H02E0001
|
|
arc: M6 V00B0100
|
|
arc: V01S0000 F3
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 0010000100000000
|
|
word: SLICEC.K1.INIT 1000000000100000
|
|
word: SLICED.K0.INIT 0000001000000001
|
|
word: SLICED.K1.INIT 0000100000000010
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R25C44:PLC2
|
|
arc: E1_H01E0101 W3_H06E0203
|
|
arc: E1_H02E0301 S1_V02N0301
|
|
arc: E1_H02E0401 N1_V01S0000
|
|
arc: E1_H02E0501 N1_V01S0100
|
|
arc: E1_H02E0601 S1_V02N0601
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: H00R0100 V02N0701
|
|
arc: N1_V02N0001 S1_V02N0001
|
|
arc: N1_V02N0201 E1_H02W0201
|
|
arc: N1_V02N0401 S1_V02N0401
|
|
arc: N1_V02N0501 H02E0501
|
|
arc: S1_V02S0201 E1_H02W0201
|
|
arc: S1_V02S0301 N3_V06S0003
|
|
arc: S3_V06S0003 N3_V06S0003
|
|
arc: S3_V06S0103 N3_V06S0103
|
|
arc: V00B0000 S1_V02N0001
|
|
arc: V00B0100 H02E0501
|
|
arc: V00T0000 V02S0401
|
|
arc: W1_H02W0201 V06S0103
|
|
arc: W1_H02W0301 E1_H02W0301
|
|
arc: A0 V02S0701
|
|
arc: A1 V02S0701
|
|
arc: A3 H02W0701
|
|
arc: A6 H02E0501
|
|
arc: B0 E1_H01W0100
|
|
arc: B1 E1_H01W0100
|
|
arc: B3 H00R0100
|
|
arc: B6 V02N0701
|
|
arc: B7 V02N0501
|
|
arc: C0 H02E0401
|
|
arc: C1 H02E0601
|
|
arc: C3 V02S0401
|
|
arc: C6 V00T0000
|
|
arc: CE0 S1_V02N0201
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H02W0201
|
|
arc: D1 H02W0201
|
|
arc: D2 V00B0100
|
|
arc: D3 V00B0100
|
|
arc: D6 S1_V02N0401
|
|
arc: D7 V02N0601
|
|
arc: E1_H01E0001 Q1
|
|
arc: E1_H02E0101 Q1
|
|
arc: E1_H02E0201 F2
|
|
arc: F0 F5A_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 F7
|
|
arc: LSR1 E1_H02W0501
|
|
arc: M0 E1_H02W0601
|
|
arc: M1 H02W0001
|
|
arc: M2 V00B0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: N1_V01N0001 Q1
|
|
arc: N1_V01N0101 F0
|
|
arc: N1_V02N0301 Q1
|
|
arc: N1_V02N0601 F6
|
|
arc: W1_H02W0501 F7
|
|
word: SLICEB.K0.INIT 0000000011111111
|
|
word: SLICEB.K1.INIT 0000000010111111
|
|
word: SLICEA.K0.INIT 0111110111011101
|
|
word: SLICEA.K1.INIT 0001010001000100
|
|
word: SLICED.K0.INIT 1110101010101010
|
|
word: SLICED.K1.INIT 0011001111001100
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET SET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R25C45:PLC2
|
|
arc: E1_H02E0001 V02N0001
|
|
arc: E1_H02E0201 S1_V02N0201
|
|
arc: E1_H02E0501 E1_H01W0100
|
|
arc: H00R0100 V02N0701
|
|
arc: N1_V02N0001 N3_V06S0003
|
|
arc: N1_V02N0201 E1_H02W0201
|
|
arc: N1_V02N0301 S1_V02N0301
|
|
arc: N1_V02N0401 H01E0001
|
|
arc: N1_V02N0601 S1_V02N0301
|
|
arc: S1_V02S0101 H01E0101
|
|
arc: S1_V02S0301 H01E0101
|
|
arc: S3_V06S0003 N3_V06S0003
|
|
arc: S3_V06S0103 N3_V06S0003
|
|
arc: S3_V06S0303 N3_V06S0303
|
|
arc: V00B0000 H02W0401
|
|
arc: W1_H02W0001 S1_V02N0001
|
|
arc: W1_H02W0301 N3_V06S0003
|
|
arc: W1_H02W0701 V02S0701
|
|
arc: W3_H06W0103 E1_H02W0201
|
|
arc: A0 W1_H02E0501
|
|
arc: A1 E1_H02W0501
|
|
arc: A3 H02E0501
|
|
arc: A6 S1_V02N0101
|
|
arc: B0 V00T0000
|
|
arc: B3 H00L0000
|
|
arc: B6 V00B0000
|
|
arc: C0 W1_H02E0601
|
|
arc: C1 H02E0601
|
|
arc: C2 H02W0401
|
|
arc: C3 W1_H02E0401
|
|
arc: C6 V02N0001
|
|
arc: CE0 H00R0100
|
|
arc: CE1 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V01S0100
|
|
arc: D1 H02W0001
|
|
arc: D2 Q2
|
|
arc: D3 V02S0201
|
|
arc: D6 V02S0401
|
|
arc: E1_H01E0001 F3
|
|
arc: E1_H02E0401 F6
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F6 F5D_SLICE
|
|
arc: H00L0000 Q2
|
|
arc: H01W0100 Q0
|
|
arc: LSR1 H02E0301
|
|
arc: M6 H02E0401
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR1
|
|
arc: N1_V02N0101 F1
|
|
arc: V00T0000 Q0
|
|
arc: V01S0100 Q2
|
|
arc: W1_H02W0201 Q2
|
|
word: SLICED.K0.INIT 1110110011001100
|
|
word: SLICED.K1.INIT 1111111111111111
|
|
word: SLICEB.K1.INIT 1100101010000010
|
|
word: SLICEA.K1.INIT 1010000000000000
|
|
word: SLICEB.K0.INIT 0000000000001111
|
|
word: SLICEA.K0.INIT 0001010001000100
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R25C46:PLC2
|
|
arc: E1_H02E0101 N1_V01S0100
|
|
arc: E1_H02E0501 N1_V02S0501
|
|
arc: H00R0000 H02E0401
|
|
arc: N1_V01N0101 N3_V06S0203
|
|
arc: N1_V02N0101 W1_H02E0101
|
|
arc: N1_V02N0201 S1_V02N0201
|
|
arc: N1_V02N0301 S1_V02N0201
|
|
arc: N1_V02N0701 N3_V06S0203
|
|
arc: N3_V06N0203 S1_V02N0701
|
|
arc: S1_V02S0001 N3_V06S0003
|
|
arc: S1_V02S0401 N1_V02S0401
|
|
arc: S3_V06S0103 N3_V06S0003
|
|
arc: S3_V06S0303 N3_V06S0203
|
|
arc: V00B0000 N1_V02S0201
|
|
arc: V00T0100 H02W0101
|
|
arc: W1_H02W0001 E1_H02W0001
|
|
arc: W1_H02W0301 S1_V02N0301
|
|
arc: W1_H02W0401 V02N0401
|
|
arc: W1_H02W0501 E1_H01W0100
|
|
arc: W1_H02W0601 H01E0001
|
|
arc: A0 V01N0101
|
|
arc: A1 V01N0101
|
|
arc: A2 V02S0501
|
|
arc: A3 H02W0501
|
|
arc: A4 E1_H02W0701
|
|
arc: A5 V00T0100
|
|
arc: A7 Q7
|
|
arc: B0 V01N0001
|
|
arc: B4 H02W0301
|
|
arc: B5 E1_H02W0101
|
|
arc: B7 V02N0501
|
|
arc: C0 F6
|
|
arc: C1 F6
|
|
arc: C2 H00R0100
|
|
arc: C3 W1_H02E0601
|
|
arc: C4 S1_V02N0201
|
|
arc: C5 W1_H02E0601
|
|
arc: C6 V00B0100
|
|
arc: C7 V02N0201
|
|
arc: CE2 H00R0000
|
|
arc: CE3 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 S1_V02N0001
|
|
arc: D1 E1_H02W0201
|
|
arc: D2 V01S0100
|
|
arc: D3 E1_H02W0001
|
|
arc: D4 H02E0001
|
|
arc: D5 H02E0201
|
|
arc: D6 H01W0000
|
|
arc: D7 H01W0000
|
|
arc: E1_H01E0101 F3
|
|
arc: F0 F5A_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00R0100 Q7
|
|
arc: H01W0000 Q4
|
|
arc: H01W0100 F5
|
|
arc: LSR1 H02E0501
|
|
arc: M0 V00B0000
|
|
arc: M7 W1_H02E0201
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR1
|
|
arc: N1_V01N0001 F2
|
|
arc: S1_V02S0601 F6
|
|
arc: S1_V02S0701 F7
|
|
arc: V00B0100 Q7
|
|
arc: V01S0000 F0
|
|
arc: V01S0100 Q4
|
|
arc: W1_H02W0201 F2
|
|
word: SLICEB.K1.INIT 0000101000000000
|
|
word: SLICEC.K1.INIT 0000100000000000
|
|
word: SLICEC.K0.INIT 0100000000000000
|
|
word: SLICEB.K0.INIT 0000101000000000
|
|
word: SLICED.K1.INIT 0000110000001000
|
|
word: SLICED.K0.INIT 0000000011110000
|
|
word: SLICEA.K0.INIT 0101010100000100
|
|
word: SLICEA.K1.INIT 0101010100000101
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET SET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET SET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.B1MUX 1
|
|
|
|
.tile R25C47:PLC2
|
|
arc: E1_H02E0301 N1_V01S0100
|
|
arc: E1_H02E0601 N1_V01S0000
|
|
arc: E3_H06E0303 N1_V01S0100
|
|
arc: H00L0000 N1_V02S0201
|
|
arc: H00L0100 H02E0101
|
|
arc: H00R0000 H02W0401
|
|
arc: H00R0100 V02N0701
|
|
arc: N1_V02N0101 H02E0101
|
|
arc: N1_V02N0201 E1_H01W0000
|
|
arc: N1_V02N0301 E1_H02W0301
|
|
arc: N1_V02N0401 N3_V06S0203
|
|
arc: N1_V02N0501 H01E0101
|
|
arc: N1_V02N0601 E1_H01W0000
|
|
arc: N1_V02N0701 S1_V02N0701
|
|
arc: S1_V02S0101 S3_V06N0103
|
|
arc: S1_V02S0701 S3_V06N0203
|
|
arc: S3_V06S0203 N3_V06S0203
|
|
arc: V00B0000 S1_V02N0201
|
|
arc: V00B0100 E1_H02W0701
|
|
arc: V00T0000 V02N0601
|
|
arc: V00T0100 E1_H02W0301
|
|
arc: W1_H02W0101 S1_V02N0101
|
|
arc: W1_H02W0201 S1_V02N0201
|
|
arc: W1_H02W0301 N1_V01S0100
|
|
arc: A0 H02E0501
|
|
arc: A2 F5
|
|
arc: A6 F5
|
|
arc: B0 V00B0000
|
|
arc: B2 S1_V02N0101
|
|
arc: C0 V02S0401
|
|
arc: C2 S1_V02N0601
|
|
arc: C5 S1_V02N0001
|
|
arc: C6 V02N0201
|
|
arc: CE0 H00R0000
|
|
arc: CE1 H00R0000
|
|
arc: CE2 H00R0000
|
|
arc: CE3 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 E1_H02W0001
|
|
arc: D2 W1_H02E0201
|
|
arc: D5 S1_V02N0401
|
|
arc: D6 W1_H02E0201
|
|
arc: E1_H01E0001 Q1
|
|
arc: E1_H01E0101 F6
|
|
arc: E1_H02E0101 Q3
|
|
arc: E1_H02E0501 Q7
|
|
arc: E3_H06E0003 F0
|
|
arc: F0 F5A_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: H01W0100 F2
|
|
arc: M0 V00T0000
|
|
arc: M1 H00R0100
|
|
arc: M2 V00B0100
|
|
arc: M3 H00L0000
|
|
arc: M4 V00T0100
|
|
arc: M7 H00L0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q1
|
|
arc: N1_V01N0101 F2
|
|
arc: N1_V02N0001 Q2
|
|
arc: V01S0000 Q4
|
|
arc: W1_H02W0501 F5
|
|
word: SLICEB.K0.INIT 0000100000000000
|
|
word: SLICED.K0.INIT 1010000000000000
|
|
word: SLICEA.K0.INIT 1011000010111011
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 1111000000000000
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R25C48:PLC2
|
|
arc: E1_H02E0001 S1_V02N0001
|
|
arc: E1_H02E0601 N3_V06S0303
|
|
arc: E1_H02E0701 V02S0701
|
|
arc: H00L0100 V02N0101
|
|
arc: H00R0100 V02N0501
|
|
arc: N1_V02N0001 S1_V02N0001
|
|
arc: N1_V02N0101 N3_V06S0103
|
|
arc: N1_V02N0301 N3_V06S0003
|
|
arc: N1_V02N0401 H01E0001
|
|
arc: N1_V02N0501 H01E0101
|
|
arc: N1_V02N0601 S1_V02N0301
|
|
arc: S1_V02S0201 N1_V02S0201
|
|
arc: S1_V02S0301 N3_V06S0003
|
|
arc: S3_V06S0003 N3_V06S0003
|
|
arc: S3_V06S0203 N3_V06S0103
|
|
arc: V01S0100 N3_V06S0303
|
|
arc: W1_H02W0001 V01N0001
|
|
arc: W1_H02W0101 V01N0101
|
|
arc: W1_H02W0201 S1_V02N0201
|
|
arc: W1_H02W0701 V02S0701
|
|
arc: A0 S1_V02N0701
|
|
arc: A2 V00T0000
|
|
arc: A3 H00L0100
|
|
arc: A4 H02W0501
|
|
arc: A5 Q5
|
|
arc: A6 S1_V02N0101
|
|
arc: A7 H02E0501
|
|
arc: B0 F3
|
|
arc: B3 H02E0101
|
|
arc: B4 V02N0701
|
|
arc: B7 N1_V02S0501
|
|
arc: C0 N1_V01S0100
|
|
arc: C1 F4
|
|
arc: C3 V02N0401
|
|
arc: C4 H02W0401
|
|
arc: C5 V00T0000
|
|
arc: C6 S1_V02N0001
|
|
arc: C7 V02N0001
|
|
arc: CE1 H02W0101
|
|
arc: CE2 H02W0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H00R0000
|
|
arc: D2 F0
|
|
arc: D3 N1_V01S0000
|
|
arc: D4 H02W0201
|
|
arc: D5 F0
|
|
arc: D6 V02S0601
|
|
arc: D7 H00R0100
|
|
arc: E1_H01E0001 F0
|
|
arc: E1_H01E0101 Q2
|
|
arc: E1_H02E0201 F0
|
|
arc: E1_H02E0401 F6
|
|
arc: E1_H02E0501 Q5
|
|
arc: F0 F5A_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00R0000 F4
|
|
arc: H01W0000 F6
|
|
arc: LSR0 V00B0000
|
|
arc: M0 H02E0601
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR0
|
|
arc: N1_V02N0701 F7
|
|
arc: S1_V02S0401 F6
|
|
arc: S1_V02S0601 F6
|
|
arc: V00B0000 F6
|
|
arc: V00T0000 Q2
|
|
arc: V01S0000 F6
|
|
arc: W1_H02W0401 F6
|
|
word: SLICED.K0.INIT 1010000000000000
|
|
word: SLICEB.K0.INIT 0101010100000000
|
|
word: SLICEC.K1.INIT 0101101000000000
|
|
word: SLICED.K1.INIT 1001000000001001
|
|
word: SLICEB.K1.INIT 1001000000000000
|
|
word: SLICEA.K1.INIT 1111000011110000
|
|
word: SLICEA.K0.INIT 1111111000000000
|
|
word: SLICEC.K0.INIT 0001000000000000
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
|
|
.tile R25C49:PLC2
|
|
arc: E1_H02E0001 W3_H06E0003
|
|
arc: E1_H02E0101 N3_V06S0103
|
|
arc: E1_H02E0201 N3_V06S0103
|
|
arc: E1_H02E0301 N1_V01S0100
|
|
arc: E1_H02E0401 N1_V01S0000
|
|
arc: E1_H02E0501 V02N0501
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
arc: H00L0000 H02W0201
|
|
arc: H00R0000 V02N0401
|
|
arc: H00R0100 S1_V02N0701
|
|
arc: N1_V01N0001 S3_V06N0003
|
|
arc: N1_V02N0001 H01E0001
|
|
arc: N1_V02N0101 H01E0101
|
|
arc: N1_V02N0301 H01E0101
|
|
arc: N1_V02N0501 H02E0501
|
|
arc: N1_V02N0701 W3_H06E0203
|
|
arc: S1_V02S0001 N1_V01S0000
|
|
arc: S1_V02S0201 E1_H02W0201
|
|
arc: S1_V02S0301 W1_H02E0301
|
|
arc: S1_V02S0601 H01E0001
|
|
arc: S1_V02S0701 H02E0701
|
|
arc: S3_V06S0003 N3_V06S0003
|
|
arc: S3_V06S0103 N3_V06S0103
|
|
arc: S3_V06S0203 W3_H06E0203
|
|
arc: V00B0000 H02E0401
|
|
arc: V00B0100 H02W0501
|
|
arc: V00T0000 H02E0201
|
|
arc: V00T0100 V02N0501
|
|
arc: W1_H02W0001 E1_H02W0001
|
|
arc: W1_H02W0101 V01N0101
|
|
arc: W1_H02W0201 N3_V06S0103
|
|
arc: W1_H02W0301 W3_H06E0003
|
|
arc: W1_H02W0401 V01N0001
|
|
arc: W1_H02W0501 V02N0501
|
|
arc: W1_H02W0701 W3_H06E0203
|
|
arc: A1 V02N0501
|
|
arc: A4 H02E0501
|
|
arc: A6 H00L0000
|
|
arc: B0 V02N0101
|
|
arc: B1 V02N0101
|
|
arc: B4 H01E0101
|
|
arc: B6 V02N0701
|
|
arc: C0 V02S0601
|
|
arc: C1 N1_V02S0601
|
|
arc: C3 N1_V02S0601
|
|
arc: C4 Q4
|
|
arc: C6 V02N0201
|
|
arc: CE2 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V00T0100
|
|
arc: D1 E1_H02W0001
|
|
arc: D2 V00T0100
|
|
arc: D3 V00B0100
|
|
arc: D4 H02E0201
|
|
arc: D6 H00R0100
|
|
arc: E1_H01E0101 F6
|
|
arc: F0 F5A_SLICE
|
|
arc: F1 FXA_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: LSR1 V00B0000
|
|
arc: M0 H01E0001
|
|
arc: M1 H02E0001
|
|
arc: M2 V00T0000
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR2 LSR1
|
|
arc: N1_V02N0601 Q4
|
|
arc: S1_V02S0101 F1
|
|
arc: S1_V02S0401 F6
|
|
arc: V01S0000 F1
|
|
word: SLICEC.K0.INIT 0111100000000000
|
|
word: SLICED.K0.INIT 0100000000000000
|
|
word: SLICEA.K0.INIT 1111111111000000
|
|
word: SLICEA.K1.INIT 1111111011111010
|
|
word: SLICEB.K0.INIT 1111111100000000
|
|
word: SLICEB.K1.INIT 1111111111110000
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
|
|
.tile R25C50:PLC2
|
|
arc: E1_H01E0001 W3_H06E0003
|
|
arc: E1_H02E0101 S1_V02N0101
|
|
arc: H00L0100 H02E0301
|
|
arc: H00R0000 H02W0601
|
|
arc: N1_V02N0001 W1_H02E0001
|
|
arc: N1_V02N0101 H02E0101
|
|
arc: N1_V02N0201 S3_V06N0103
|
|
arc: N1_V02N0301 H01E0101
|
|
arc: N1_V02N0501 H02E0501
|
|
arc: S1_V02S0101 N3_V06S0103
|
|
arc: S1_V02S0201 H02E0201
|
|
arc: S1_V02S0501 H02E0501
|
|
arc: S1_V02S0701 H02W0701
|
|
arc: S3_V06S0203 N3_V06S0103
|
|
arc: S3_V06S0303 H06E0303
|
|
arc: V00B0000 H02W0401
|
|
arc: V00B0100 V02N0301
|
|
arc: V00T0000 E1_H02W0001
|
|
arc: V00T0100 V02N0701
|
|
arc: W1_H02W0201 S1_V02N0201
|
|
arc: W1_H02W0501 V02N0501
|
|
arc: A0 W1_H02E0701
|
|
arc: A1 W1_H02E0701
|
|
arc: A4 V00T0100
|
|
arc: A5 H02E0501
|
|
arc: A6 N1_V01N0101
|
|
arc: B0 S1_V02N0101
|
|
arc: B1 V02N0301
|
|
arc: B4 S1_V02N0501
|
|
arc: B5 H02E0101
|
|
arc: B6 S1_V02N0701
|
|
arc: C0 V02S0601
|
|
arc: C1 V02S0601
|
|
arc: C4 S1_V02N0001
|
|
arc: C5 V01N0101
|
|
arc: C6 W1_H02E0601
|
|
arc: CE2 H00R0000
|
|
arc: CE3 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D1 V02N0201
|
|
arc: D3 V00B0100
|
|
arc: D4 V02N0601
|
|
arc: D5 V01N0001
|
|
arc: D6 H01W0000
|
|
arc: E1_H01E0101 F4
|
|
arc: E1_H02E0501 F5
|
|
arc: F0 F5A_SLICE
|
|
arc: F1 FXA_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: H01W0000 Q6
|
|
arc: M0 V00B0000
|
|
arc: M1 W1_H02E0001
|
|
arc: M2 V00B0000
|
|
arc: M5 H02E0001
|
|
arc: M6 V00T0000
|
|
arc: M7 H00L0100
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0101 Q7
|
|
arc: N1_V02N0701 Q5
|
|
arc: S1_V02S0301 F1
|
|
arc: V01S0000 F6
|
|
word: SLICEA.K0.INIT 1000000010000000
|
|
word: SLICEA.K1.INIT 1110110011001100
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 1111111100000000
|
|
word: SLICED.K0.INIT 1001000000001001
|
|
word: SLICEC.K1.INIT 0000000001000000
|
|
word: SLICEC.K0.INIT 0000001000000000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R25C51:PLC2
|
|
arc: E1_H02E0701 N3_V06S0203
|
|
arc: E3_H06E0203 H01E0001
|
|
arc: H00L0000 V02S0001
|
|
arc: H00L0100 E1_H02W0101
|
|
arc: H00R0100 H02E0501
|
|
arc: N1_V01N0101 N3_V06S0203
|
|
arc: N1_V02N0001 S1_V02N0001
|
|
arc: N1_V02N0501 H01E0101
|
|
arc: N1_V02N0701 N1_V01S0100
|
|
arc: S1_V02S0001 N1_V02S0501
|
|
arc: S1_V02S0101 N1_V02S0101
|
|
arc: S1_V02S0201 N1_V02S0701
|
|
arc: S1_V02S0701 N1_V02S0601
|
|
arc: S3_V06S0203 N3_V06S0103
|
|
arc: V00B0000 V02N0201
|
|
arc: V00B0100 H02E0501
|
|
arc: V00T0100 V02N0701
|
|
arc: W1_H02W0001 V02N0001
|
|
arc: W1_H02W0201 N3_V06S0103
|
|
arc: W1_H02W0701 N3_V06S0203
|
|
arc: A1 N1_V02S0501
|
|
arc: A3 V02N0501
|
|
arc: A4 V00B0000
|
|
arc: B1 N1_V02S0101
|
|
arc: B3 H01W0100
|
|
arc: B4 V00B0100
|
|
arc: B6 H02E0101
|
|
arc: C1 N1_V02S0601
|
|
arc: C3 E1_H02W0401
|
|
arc: C4 N1_V02S0001
|
|
arc: C6 S1_V02N0001
|
|
arc: CE0 H00R0000
|
|
arc: CE1 H00R0000
|
|
arc: CE2 H00R0000
|
|
arc: CE3 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D1 S1_V02N0201
|
|
arc: D3 H02W0201
|
|
arc: D4 V02N0401
|
|
arc: D5 H00R0100
|
|
arc: D6 V02N0601
|
|
arc: E1_H01E0001 F6
|
|
arc: E1_H01E0101 F0
|
|
arc: E1_H02E0601 F6
|
|
arc: F0 F5A_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F4 F5C_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: H00R0000 F6
|
|
arc: H01W0100 Q7
|
|
arc: M0 V00T0000
|
|
arc: M1 E1_H02W0001
|
|
arc: M2 V00T0100
|
|
arc: M3 E1_H02W0201
|
|
arc: M4 E1_H01E0101
|
|
arc: M5 H00L0100
|
|
arc: M6 W1_H02E0401
|
|
arc: M7 H00L0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 F4
|
|
arc: N1_V02N0101 Q1
|
|
arc: N1_V02N0301 Q1
|
|
arc: N1_V02N0401 F6
|
|
arc: N1_V02N0601 F4
|
|
arc: S1_V02S0301 Q3
|
|
arc: S1_V02S0401 Q6
|
|
arc: S1_V02S0501 Q5
|
|
arc: S1_V02S0601 F6
|
|
arc: V00T0000 F2
|
|
arc: V01S0000 F4
|
|
arc: V01S0100 Q3
|
|
arc: W1_H02W0401 F4
|
|
arc: W1_H02W0601 F6
|
|
word: SLICED.K0.INIT 1100000000000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 1001000000001001
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 1110110000000000
|
|
word: SLICEC.K1.INIT 1111111100000000
|
|
word: SLICEC.K0.INIT 1100110011001000
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R25C52:PLC2
|
|
arc: H00R0000 H02E0601
|
|
arc: N1_V02N0201 H01E0001
|
|
arc: S1_V02S0001 N1_V02S0501
|
|
arc: S1_V02S0401 N3_V06S0203
|
|
arc: S1_V02S0701 H02E0701
|
|
arc: V00B0100 H02W0701
|
|
arc: W1_H02W0001 V02N0001
|
|
arc: W1_H02W0201 N1_V02S0201
|
|
arc: CE0 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: M0 V00B0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: V01S0000 Q0
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R25C53:PLC2
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: N1_V02N0601 S1_V02N0301
|
|
arc: S1_V02S0101 N3_V06S0103
|
|
arc: S1_V02S0301 E3_H06W0003
|
|
arc: S1_V02S0701 W1_H02E0701
|
|
arc: W1_H02W0001 E1_H02W0501
|
|
arc: W1_H02W0101 V02N0101
|
|
arc: W1_H02W0201 V02N0201
|
|
arc: W1_H02W0401 V02N0401
|
|
arc: W1_H02W0701 S1_V02N0701
|
|
|
|
.tile R25C54:PLC2
|
|
arc: S1_V02S0401 N3_V06S0203
|
|
arc: S1_V02S0501 N3_V06S0303
|
|
arc: S1_V02S0701 H06E0203
|
|
|
|
.tile R25C55:PLC2
|
|
arc: W1_H02W0501 W3_H06E0303
|
|
|
|
.tile R25C56:PLC2
|
|
arc: N3_V06N0103 H06E0103
|
|
|
|
.tile R25C59:PLC2
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
|
|
.tile R25C60:PLC2
|
|
arc: S1_V02S0101 N3_V06S0103
|
|
|
|
.tile R25C61:PLC2
|
|
arc: S1_V02S0101 N3_V06S0103
|
|
|
|
.tile R25C62:PLC2
|
|
arc: S1_V02S0401 N3_V06S0203
|
|
|
|
.tile R25C63:PLC2
|
|
arc: E1_H02E0701 N3_V06S0203
|
|
|
|
.tile R25C64:PLC2
|
|
arc: S1_V02S0701 H02E0701
|
|
|
|
.tile R25C65:PLC2
|
|
arc: S1_V02S0701 W1_H02E0701
|
|
arc: W3_H06W0303 E3_H06W0203
|
|
|
|
.tile R25C71:PLC2
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
|
|
.tile R25C77:PLC2
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
|
|
.tile R25C7:PLC2
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
|
|
.tile R25C83:PLC2
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
|
|
.tile R25C8:PLC2
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
|
|
.tile R26C10:PLC2
|
|
arc: W3_H06W0203 E3_H06W0203
|
|
|
|
.tile R26C11:PLC2
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
|
|
.tile R26C13:PLC2
|
|
arc: E1_H02E0401 S3_V06N0203
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
|
|
.tile R26C14:PLC2
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: N1_V02N0401 H02E0401
|
|
|
|
.tile R26C16:PLC2
|
|
arc: W3_H06W0203 E3_H06W0203
|
|
|
|
.tile R26C17:PLC2
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
|
|
.tile R26C19:PLC2
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
|
|
.tile R26C20:PLC2
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
|
|
.tile R26C22:PLC2
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
|
|
.tile R26C23:PLC2
|
|
arc: W3_H06W0303 E3_H06W0203
|
|
|
|
.tile R26C25:PLC2
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: S1_V02S0101 S3_V06N0103
|
|
arc: S1_V02S0701 E1_H02W0701
|
|
|
|
.tile R26C26:PLC2
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
|
|
.tile R26C27:PLC2
|
|
arc: W1_H02W0701 V02S0701
|
|
|
|
.tile R26C28:PLC2
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
|
|
.tile R26C29:PLC2
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
|
|
.tile R26C2:PLC2
|
|
arc: E3_H06E0303 H01E0101
|
|
|
|
.tile R26C31:PLC2
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
|
|
.tile R26C32:PLC2
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
arc: V01S0000 S3_V06N0103
|
|
|
|
.tile R26C34:PLC2
|
|
arc: E1_H02E0601 N1_V01S0000
|
|
arc: N3_V06N0203 E3_H06W0203
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
|
|
.tile R26C35:PLC2
|
|
arc: H00L0100 V02N0101
|
|
arc: H00R0000 V02N0401
|
|
arc: H00R0100 V02N0501
|
|
arc: S1_V02S0601 N1_V01S0000
|
|
arc: S1_V02S0701 H06E0203
|
|
arc: V00B0100 E1_H02W0701
|
|
arc: V00T0000 V02N0401
|
|
arc: V00T0100 S1_V02N0501
|
|
arc: A0 H02W0701
|
|
arc: A1 H02W0701
|
|
arc: A2 V02N0701
|
|
arc: A3 H02W0701
|
|
arc: A4 V02S0101
|
|
arc: A5 S1_V02N0301
|
|
arc: B0 V00T0000
|
|
arc: B1 V00T0000
|
|
arc: B2 H00R0000
|
|
arc: B3 H00R0000
|
|
arc: B4 V00B0100
|
|
arc: B5 E1_H02W0101
|
|
arc: C0 H00L0100
|
|
arc: C1 H00L0100
|
|
arc: C2 H00L0100
|
|
arc: C3 H00L0100
|
|
arc: C4 V00T0100
|
|
arc: C5 H02E0601
|
|
arc: CE0 H00R0100
|
|
arc: CE1 H00R0100
|
|
arc: CLK1 G_HPBX0000
|
|
arc: D0 V02N0201
|
|
arc: D1 V02N0201
|
|
arc: D2 V02N0001
|
|
arc: D3 V02N0001
|
|
arc: D4 S1_V02N0401
|
|
arc: D5 V02S0401
|
|
arc: E3_H06E0003 Q3
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: LSR1 E1_H02W0301
|
|
arc: MUXCLK0 CLK1
|
|
arc: MUXCLK1 CLK1
|
|
arc: N3_V06N0003 Q0
|
|
arc: N3_V06N0103 Q1
|
|
arc: W3_H06W0103 Q2
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
enum: SLICEA.MODE DPRAM
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.WREMUX WRE
|
|
enum: CLK1.CLKMUX CLK
|
|
enum: SLICEA.MODE DPRAM
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE DPRAM
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE DPRAM
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE RAMW
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK1.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK1.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK1.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK1.CLKMUX CLK
|
|
|
|
.tile R26C36:PLC2
|
|
arc: S1_V02S0601 N1_V01S0000
|
|
arc: S1_V02S0701 H02W0701
|
|
arc: W1_H02W0701 V02N0701
|
|
|
|
.tile R26C37:PLC2
|
|
arc: E1_H02E0101 W3_H06E0103
|
|
arc: E1_H02E0201 V02S0201
|
|
arc: E1_H02E0401 V02S0401
|
|
arc: E1_H02E0501 N1_V01S0100
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: W1_H02W0101 V02N0101
|
|
arc: W1_H02W0301 V02N0301
|
|
arc: W1_H02W0701 V02S0701
|
|
|
|
.tile R26C38:PLC2
|
|
arc: E1_H02E0001 V02N0001
|
|
arc: E1_H02E0201 S1_V02N0201
|
|
arc: H00R0100 H02E0501
|
|
arc: N1_V02N0101 H02W0101
|
|
arc: N1_V02N0501 H02W0501
|
|
arc: V00T0100 H02E0101
|
|
arc: CE0 E1_H02W0101
|
|
arc: CE3 E1_H02W0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H02E0101 Q1
|
|
arc: E1_H02E0401 Q6
|
|
arc: M1 H00R0100
|
|
arc: M6 V00T0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R26C39:PLC2
|
|
arc: E1_H02E0101 N1_V01S0100
|
|
arc: E1_H02E0301 N1_V01S0100
|
|
arc: E1_H02E0401 S1_V02N0401
|
|
arc: E1_H02E0701 S1_V02N0701
|
|
arc: E3_H06E0103 N1_V01S0100
|
|
arc: H00L0100 S1_V02N0101
|
|
arc: H00R0100 H02W0701
|
|
arc: N1_V02N0101 E1_H02W0101
|
|
arc: N1_V02N0401 W1_H02E0401
|
|
arc: N1_V02N0501 N1_V01S0100
|
|
arc: N1_V02N0601 E1_H02W0601
|
|
arc: N1_V02N0701 N1_V01S0100
|
|
arc: S1_V02S0201 N1_V02S0701
|
|
arc: S3_V06S0303 N1_V01S0100
|
|
arc: V00B0000 V02S0201
|
|
arc: V00T0000 W1_H02E0201
|
|
arc: V00T0100 E1_H02W0301
|
|
arc: W1_H02W0101 E1_H02W0101
|
|
arc: W1_H02W0501 S1_V02N0501
|
|
arc: A1 S1_V02N0701
|
|
arc: A3 V00B0000
|
|
arc: A5 Q5
|
|
arc: A7 Q7
|
|
arc: B1 Q1
|
|
arc: B2 S1_V02N0301
|
|
arc: B3 Q3
|
|
arc: B5 V02N0701
|
|
arc: B7 E1_H02W0101
|
|
arc: C1 H00L0100
|
|
arc: C2 H02W0401
|
|
arc: C3 S1_V02N0601
|
|
arc: C5 H02E0401
|
|
arc: C7 V02S0201
|
|
arc: CE0 H00L0000
|
|
arc: CE1 H00L0000
|
|
arc: CE2 H00L0000
|
|
arc: CE3 H00L0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D1 H00R0000
|
|
arc: D2 V02N0001
|
|
arc: D3 V01S0100
|
|
arc: D5 H02W0201
|
|
arc: D7 H01W0000
|
|
arc: E1_H01E0001 F3
|
|
arc: E1_H01E0101 F2
|
|
arc: E1_H02E0001 F0
|
|
arc: E1_H02E0201 F2
|
|
arc: E1_H02E0501 F7
|
|
arc: F0 F5A_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00L0000 F2
|
|
arc: H00R0000 Q6
|
|
arc: H01W0000 Q4
|
|
arc: M0 V00B0100
|
|
arc: M1 E1_H02W0001
|
|
arc: M2 V00T0000
|
|
arc: M3 H00R0100
|
|
arc: M4 E1_H02W0401
|
|
arc: M5 H02E0001
|
|
arc: M6 V00T0100
|
|
arc: M7 E1_H02W0201
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 F0
|
|
arc: N1_V01N0101 F2
|
|
arc: N1_V02N0201 F2
|
|
arc: S1_V02S0001 F2
|
|
arc: V00B0100 F5
|
|
arc: V01S0000 F2
|
|
arc: V01S0100 Q2
|
|
word: SLICEB.K0.INIT 1100000000000000
|
|
word: SLICEB.K1.INIT 1000001001000001
|
|
word: SLICED.K1.INIT 1000010000100001
|
|
word: SLICEC.K1.INIT 1001000000001001
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 1000001001000001
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R26C3:PLC2
|
|
arc: W1_H02W0701 V02N0701
|
|
|
|
.tile R26C40:PLC2
|
|
arc: E1_H02E0001 S1_V02N0001
|
|
arc: E1_H02E0201 V02N0201
|
|
arc: E1_H02E0301 N1_V01S0100
|
|
arc: E1_H02E0401 V02S0401
|
|
arc: E1_H02E0601 N1_V01S0000
|
|
arc: H00L0000 H02E0201
|
|
arc: H00L0100 W1_H02E0101
|
|
arc: H00R0000 V02N0401
|
|
arc: N1_V02N0001 H02E0001
|
|
arc: N1_V02N0101 W1_H02E0101
|
|
arc: N1_V02N0201 S3_V06N0103
|
|
arc: N1_V02N0301 H01E0101
|
|
arc: N1_V02N0501 S1_V02N0401
|
|
arc: N1_V02N0601 H01E0001
|
|
arc: S1_V02S0001 S3_V06N0003
|
|
arc: S1_V02S0401 S3_V06N0203
|
|
arc: V00T0000 V02N0601
|
|
arc: V00T0100 H02E0301
|
|
arc: W1_H02W0101 H01E0101
|
|
arc: W1_H02W0201 V02S0201
|
|
arc: W1_H02W0401 E1_H02W0101
|
|
arc: W1_H02W0701 N1_V01S0100
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
arc: W3_H06W0203 E3_H06W0203
|
|
arc: A4 H02E0701
|
|
arc: A5 V02S0101
|
|
arc: A6 V00T0100
|
|
arc: A7 H02E0701
|
|
arc: B4 H02E0101
|
|
arc: B5 H02E0101
|
|
arc: B6 S1_V02N0701
|
|
arc: B7 H02E0301
|
|
arc: C4 V02S0201
|
|
arc: C5 H02E0401
|
|
arc: C6 V02S0201
|
|
arc: C7 V02S0201
|
|
arc: CE3 H00L0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D4 H00R0100
|
|
arc: D5 H00R0100
|
|
arc: D6 H00R0100
|
|
arc: D7 H00R0100
|
|
arc: E1_H01E0001 F3
|
|
arc: F0 F5A_SLICE
|
|
arc: F1 FXA_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F3 FXB_SLICE
|
|
arc: F4 F5C_SLICE
|
|
arc: F5 FXC_SLICE
|
|
arc: F6 F5D_SLICE
|
|
arc: H00R0100 Q7
|
|
arc: M0 V00T0000
|
|
arc: M1 H00L0100
|
|
arc: M2 V00T0000
|
|
arc: M3 H00R0000
|
|
arc: M4 V00T0000
|
|
arc: M5 H00L0100
|
|
arc: M6 V00T0000
|
|
arc: M7 W1_H02E0201
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0101 Q7
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 0010000000000010
|
|
word: SLICEC.K1.INIT 1000000001000000
|
|
word: SLICED.K0.INIT 0001000000000001
|
|
word: SLICED.K1.INIT 0100000000000100
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R26C41:PLC2
|
|
arc: E1_H02E0001 V01N0001
|
|
arc: E1_H02E0201 V02N0201
|
|
arc: E1_H02E0601 S3_V06N0303
|
|
arc: E1_H02E0701 S1_V02N0701
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: H00L0000 S1_V02N0001
|
|
arc: H00L0100 N1_V02S0301
|
|
arc: H00R0000 V02S0401
|
|
arc: H00R0100 W1_H02E0501
|
|
arc: N1_V02N0101 W1_H02E0101
|
|
arc: N1_V02N0201 H02E0201
|
|
arc: N1_V02N0301 H02E0301
|
|
arc: N1_V02N0401 E1_H02W0401
|
|
arc: N1_V02N0601 E1_H01W0000
|
|
arc: S1_V02S0001 E3_H06W0003
|
|
arc: S1_V02S0101 W1_H02E0101
|
|
arc: S1_V02S0201 W1_H02E0201
|
|
arc: S1_V02S0301 H02E0301
|
|
arc: V00T0100 V02S0501
|
|
arc: V01S0000 S3_V06N0103
|
|
arc: W1_H02W0001 E1_H02W0501
|
|
arc: W1_H02W0101 S1_V02N0101
|
|
arc: W1_H02W0201 S1_V02N0201
|
|
arc: W1_H02W0301 N1_V02S0301
|
|
arc: W1_H02W0401 S1_V02N0401
|
|
arc: W1_H02W0601 V02S0601
|
|
arc: A0 F7
|
|
arc: A2 F7
|
|
arc: A7 V02N0301
|
|
arc: B2 V02S0301
|
|
arc: B7 N1_V01S0000
|
|
arc: C0 E1_H02W0401
|
|
arc: C1 E1_H02W0401
|
|
arc: C2 E1_H02W0401
|
|
arc: C3 E1_H02W0401
|
|
arc: C6 H02E0601
|
|
arc: C7 H01E0001
|
|
arc: CE1 E1_H02W0101
|
|
arc: CE2 E1_H02W0101
|
|
arc: CE3 E1_H02W0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 N1_V02S0001
|
|
arc: D1 N1_V02S0001
|
|
arc: D2 N1_V02S0201
|
|
arc: D3 N1_V02S0001
|
|
arc: D6 H01W0000
|
|
arc: D7 H00R0100
|
|
arc: E1_H02E0501 Q5
|
|
arc: E3_H06E0103 F1
|
|
arc: F0 F5A_SLICE
|
|
arc: F1 FXA_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 F7
|
|
arc: M0 H02E0601
|
|
arc: M1 H00R0000
|
|
arc: M2 H02E0601
|
|
arc: M3 H00L0100
|
|
arc: M4 V00T0100
|
|
arc: M5 H00L0000
|
|
arc: M7 E1_H02W0201
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q4
|
|
arc: N1_V01N0101 Q3
|
|
arc: N1_V02N0501 Q7
|
|
arc: V01S0100 F6
|
|
word: SLICEA.K0.INIT 1010000000000000
|
|
word: SLICEA.K1.INIT 1111000000000000
|
|
word: SLICEB.K0.INIT 1110000000000000
|
|
word: SLICEB.K1.INIT 1111000000000000
|
|
word: SLICED.K0.INIT 0000000000001111
|
|
word: SLICED.K1.INIT 1100100011000000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R26C42:PLC2
|
|
arc: E1_H02E0101 W1_H02E0001
|
|
arc: E1_H02E0501 N1_V01S0100
|
|
arc: H00L0000 V02S0001
|
|
arc: H00L0100 N1_V02S0101
|
|
arc: H00R0100 H02E0701
|
|
arc: N1_V02N0001 S1_V02N0501
|
|
arc: N1_V02N0101 N1_V01S0100
|
|
arc: N1_V02N0201 H06E0103
|
|
arc: N1_V02N0501 N1_V01S0100
|
|
arc: N1_V02N0701 N1_V01S0100
|
|
arc: S1_V02S0101 H06E0103
|
|
arc: S1_V02S0201 H06E0103
|
|
arc: S1_V02S0301 H02W0301
|
|
arc: S1_V02S0401 E1_H02W0401
|
|
arc: S1_V02S0701 N1_V01S0100
|
|
arc: S3_V06S0003 N1_V01S0000
|
|
arc: S3_V06S0103 H06E0103
|
|
arc: V00B0000 V02N0201
|
|
arc: V00T0100 N1_V02S0501
|
|
arc: W1_H02W0101 V02S0101
|
|
arc: A0 N1_V02S0501
|
|
arc: A3 H02E0501
|
|
arc: A4 H02W0701
|
|
arc: B0 V01N0001
|
|
arc: B1 N1_V02S0101
|
|
arc: B3 Q3
|
|
arc: C0 H00L0100
|
|
arc: C3 N1_V02S0601
|
|
arc: C4 V02N0001
|
|
arc: C6 V02N0201
|
|
arc: CE0 E1_H02W0101
|
|
arc: CE1 H00R0000
|
|
arc: CE2 H00R0000
|
|
arc: CE3 E1_H02W0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H02E0001
|
|
arc: D1 V00T0100
|
|
arc: D3 S1_V02N0201
|
|
arc: D4 H02E0201
|
|
arc: D6 E1_H01W0100
|
|
arc: E1_H01E0001 F6
|
|
arc: E1_H01E0101 F4
|
|
arc: E1_H02E0001 F0
|
|
arc: E1_H02E0301 Q1
|
|
arc: E1_H02E0401 F6
|
|
arc: E1_H02E0601 F4
|
|
arc: E1_H02E0701 Q7
|
|
arc: F0 F5A_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: H00R0000 F4
|
|
arc: H01W0000 F4
|
|
arc: M0 V00B0000
|
|
arc: M1 H00R0100
|
|
arc: M3 W1_H02E0201
|
|
arc: M4 W1_H02E0401
|
|
arc: M7 H00L0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q7
|
|
arc: N1_V01N0101 Q1
|
|
arc: N1_V02N0301 F3
|
|
arc: N1_V02N0401 Q4
|
|
arc: N1_V02N0601 F4
|
|
arc: S1_V02S0601 F4
|
|
arc: V01S0100 F4
|
|
word: SLICEA.K0.INIT 1100100000000000
|
|
word: SLICEA.K1.INIT 1111111111001100
|
|
word: SLICED.K0.INIT 0000000000001111
|
|
word: SLICEC.K0.INIT 1010000000000000
|
|
word: SLICEB.K1.INIT 1000010000100001
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R26C43:PLC2
|
|
arc: E1_H02E0101 V02N0101
|
|
arc: E1_H02E0201 W3_H06E0103
|
|
arc: E1_H02E0401 S3_V06N0203
|
|
arc: E1_H02E0501 S3_V06N0303
|
|
arc: E3_H06E0203 S3_V06N0203
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
arc: H00R0100 V02N0501
|
|
arc: N1_V01N0101 S3_V06N0203
|
|
arc: N1_V02N0001 H01E0001
|
|
arc: N1_V02N0101 H01E0101
|
|
arc: N1_V02N0201 W3_H06E0103
|
|
arc: N1_V02N0301 V01N0101
|
|
arc: N1_V02N0501 H01E0101
|
|
arc: N1_V02N0601 S3_V06N0303
|
|
arc: N1_V02N0701 S3_V06N0203
|
|
arc: S1_V02S0001 E1_H01W0000
|
|
arc: S1_V02S0201 N1_V02S0701
|
|
arc: S1_V02S0401 W3_H06E0203
|
|
arc: S1_V02S0501 S3_V06N0303
|
|
arc: S1_V02S0601 W1_H02E0601
|
|
arc: S1_V02S0701 S3_V06N0203
|
|
arc: V00B0000 V02N0201
|
|
arc: V00B0100 H02E0701
|
|
arc: V00T0100 S1_V02N0501
|
|
arc: V01S0100 S3_V06N0303
|
|
arc: W1_H02W0101 H01E0101
|
|
arc: W1_H02W0201 W3_H06E0103
|
|
arc: W1_H02W0301 N1_V01S0100
|
|
arc: W1_H02W0401 V06S0203
|
|
arc: W1_H02W0501 N1_V01S0100
|
|
arc: W1_H02W0701 E1_H02W0601
|
|
arc: A2 H02E0501
|
|
arc: A3 H02W0701
|
|
arc: A5 V00T0100
|
|
arc: B0 V02S0301
|
|
arc: B2 H02E0301
|
|
arc: B3 V02N0301
|
|
arc: B5 H02W0301
|
|
arc: C0 N1_V01N0001
|
|
arc: C2 N1_V02S0601
|
|
arc: C3 H00R0100
|
|
arc: C5 V02N0001
|
|
arc: CE0 E1_H02W0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02S0201
|
|
arc: D2 V00B0100
|
|
arc: D3 N1_V01S0000
|
|
arc: D5 V01N0001
|
|
arc: E1_H01E0001 F3
|
|
arc: E1_H01E0101 F3
|
|
arc: F0 F0_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F5C_SLICE
|
|
arc: H01W0100 F4
|
|
arc: LSR0 V00B0000
|
|
arc: M4 V00T0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: N1_V01N0001 Q0
|
|
arc: V00T0000 F2
|
|
word: SLICEB.K0.INIT 1000001001000001
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000100000000100
|
|
word: SLICEB.K1.INIT 1010101010000000
|
|
word: SLICEA.K0.INIT 0000001100110000
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R26C44:PLC2
|
|
arc: E1_H02E0601 V02N0601
|
|
arc: H00L0000 W1_H02E0001
|
|
arc: H00R0000 W1_H02E0601
|
|
arc: H00R0100 V02N0701
|
|
arc: N1_V02N0001 W1_H02E0001
|
|
arc: N1_V02N0101 H06E0103
|
|
arc: N1_V02N0201 H01E0001
|
|
arc: N1_V02N0401 H02E0401
|
|
arc: N1_V02N0501 S1_V02N0501
|
|
arc: N1_V02N0701 S1_V02N0601
|
|
arc: S1_V02S0101 H06W0103
|
|
arc: S1_V02S0301 H02W0301
|
|
arc: S1_V02S0401 H06W0203
|
|
arc: S1_V02S0501 H06W0303
|
|
arc: S3_V06S0103 N1_V02S0101
|
|
arc: V00B0000 H02E0401
|
|
arc: V00B0100 E1_H02W0501
|
|
arc: V00T0100 W1_H02E0101
|
|
arc: W1_H02W0101 V02N0101
|
|
arc: W1_H02W0301 N1_V02S0301
|
|
arc: W1_H02W0701 N1_V02S0701
|
|
arc: A1 N1_V02S0501
|
|
arc: A6 E1_H01W0000
|
|
arc: B1 V00B0000
|
|
arc: C0 H02E0401
|
|
arc: C1 W1_H02E0401
|
|
arc: C2 H00L0000
|
|
arc: C6 V00B0100
|
|
arc: CE1 H00R0100
|
|
arc: CE2 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02S0201
|
|
arc: D1 V02S0201
|
|
arc: D2 H01E0101
|
|
arc: D6 H02W0001
|
|
arc: E1_H01E0101 F0
|
|
arc: F0 F5A_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: H01W0000 Q2
|
|
arc: M0 V00T0000
|
|
arc: M2 V00T0100
|
|
arc: M4 H02W0401
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: N1_V02N0601 Q4
|
|
arc: V00T0000 F2
|
|
arc: W1_H02W0401 F6
|
|
word: SLICED.K0.INIT 0101000000000000
|
|
word: SLICEB.K0.INIT 0000000000001111
|
|
word: SLICEA.K0.INIT 1111111111110000
|
|
word: SLICEA.K1.INIT 1100111011001100
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R26C45:PLC2
|
|
arc: E1_H02E0501 N3_V06S0303
|
|
arc: E3_H06E0103 W1_H02E0201
|
|
arc: H00L0000 E1_H02W0201
|
|
arc: H00R0000 H02W0401
|
|
arc: H00R0100 N1_V02S0701
|
|
arc: N1_V02N0001 S1_V02N0001
|
|
arc: N1_V02N0401 H02W0401
|
|
arc: N1_V02N0501 W1_H02E0501
|
|
arc: N1_V02N0701 H01E0101
|
|
arc: S1_V02S0501 N1_V02S0401
|
|
arc: V00B0000 S1_V02N0001
|
|
arc: V00B0100 V02N0101
|
|
arc: V00T0100 N1_V02S0701
|
|
arc: V01S0000 N3_V06S0103
|
|
arc: W1_H02W0101 H01E0101
|
|
arc: W1_H02W0301 S3_V06N0003
|
|
arc: W1_H02W0401 E1_H02W0101
|
|
arc: W1_H02W0601 E1_H02W0301
|
|
arc: A1 H00R0000
|
|
arc: A2 V00B0000
|
|
arc: A7 H02W0701
|
|
arc: B1 V00B0000
|
|
arc: B2 E1_H02W0301
|
|
arc: B7 V01S0000
|
|
arc: C0 H02W0401
|
|
arc: C1 H00L0000
|
|
arc: C2 H00R0100
|
|
arc: C7 V00T0000
|
|
arc: CE0 W1_H02E0101
|
|
arc: CE1 W1_H02E0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D1 V00T0100
|
|
arc: D2 S1_V02N0201
|
|
arc: D7 H01W0000
|
|
arc: E1_H01E0101 F7
|
|
arc: E1_H02E0201 Q2
|
|
arc: E1_H02E0301 Q1
|
|
arc: F0 F5A_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 Q1
|
|
arc: LSR1 E1_H02W0501
|
|
arc: M0 V00B0100
|
|
arc: M1 V01S0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR1
|
|
arc: V00T0000 Q2
|
|
arc: V01S0100 F0
|
|
arc: W1_H02W0001 Q2
|
|
word: SLICEA.K0.INIT 0000111100001111
|
|
word: SLICEA.K1.INIT 0101010100010101
|
|
word: SLICEB.K0.INIT 0000100000000000
|
|
word: SLICED.K1.INIT 1000100010000000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET SET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET SET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R26C46:PLC2
|
|
arc: E1_H02E0001 N1_V01S0000
|
|
arc: E1_H02E0601 V06S0303
|
|
arc: H00L0100 V02N0101
|
|
arc: H00R0000 W1_H02E0601
|
|
arc: N1_V02N0201 S1_V02N0701
|
|
arc: N1_V02N0401 S3_V06N0203
|
|
arc: N1_V02N0501 H02E0501
|
|
arc: N1_V02N0601 H06E0303
|
|
arc: N1_V02N0701 S1_V02N0701
|
|
arc: N3_V06N0203 S3_V06N0103
|
|
arc: N3_V06N0303 S3_V06N0203
|
|
arc: S1_V02S0001 N1_V02S0501
|
|
arc: S1_V02S0101 H01E0101
|
|
arc: S1_V02S0401 S3_V06N0203
|
|
arc: S1_V02S0501 H02E0501
|
|
arc: S1_V02S0701 S3_V06N0203
|
|
arc: W1_H02W0401 S3_V06N0203
|
|
arc: W1_H02W0501 N1_V02S0501
|
|
arc: W1_H02W0701 S1_V02N0701
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
arc: A0 F7
|
|
arc: A1 N1_V02S0701
|
|
arc: A6 V02N0301
|
|
arc: B1 H00R0100
|
|
arc: B2 H00R0000
|
|
arc: B4 H02E0301
|
|
arc: B6 V02N0501
|
|
arc: C1 V02S0401
|
|
arc: C2 E1_H02W0401
|
|
arc: C3 V02N0601
|
|
arc: C5 F4
|
|
arc: C6 V02N0201
|
|
arc: C7 E1_H01E0101
|
|
arc: CE3 H00L0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 E1_H02W0201
|
|
arc: D1 E1_H02W0201
|
|
arc: D2 E1_H02W0001
|
|
arc: D3 V01S0100
|
|
arc: D4 H02E0201
|
|
arc: D5 V02S0601
|
|
arc: D6 S1_V02N0401
|
|
arc: D7 V02N0401
|
|
arc: E1_H01E0001 F7
|
|
arc: E1_H01E0101 F3
|
|
arc: E1_H02E0501 F5
|
|
arc: F0 F5A_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00R0100 F7
|
|
arc: LSR0 V00T0000
|
|
arc: M0 V00B0100
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR3 LSR0
|
|
arc: N1_V01N0001 F4
|
|
arc: N1_V01N0101 F3
|
|
arc: S1_V02S0201 F2
|
|
arc: S1_V02S0601 Q6
|
|
arc: V00B0100 F5
|
|
arc: V00T0000 F2
|
|
arc: V01S0000 F0
|
|
arc: V01S0100 Q6
|
|
word: SLICEC.K1.INIT 0000000000001111
|
|
word: SLICED.K1.INIT 0000000000001111
|
|
word: SLICEB.K0.INIT 0011000000000000
|
|
word: SLICED.K0.INIT 0010000000000000
|
|
word: SLICEC.K0.INIT 0000000011001100
|
|
word: SLICEB.K1.INIT 0000000011110000
|
|
word: SLICEA.K0.INIT 0101010100000000
|
|
word: SLICEA.K1.INIT 1011111100000000
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG0.REGSET SET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R26C47:PLC2
|
|
arc: E1_H02E0201 E3_H06W0103
|
|
arc: E1_H02E0301 S1_V02N0301
|
|
arc: E1_H02E0601 S1_V02N0601
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: E3_H06E0103 V06N0103
|
|
arc: H00R0100 N1_V02S0701
|
|
arc: N1_V02N0001 N1_V01S0000
|
|
arc: N1_V02N0201 H06W0103
|
|
arc: N1_V02N0401 S3_V06N0203
|
|
arc: N1_V02N0501 W1_H02E0501
|
|
arc: N1_V02N0601 V01N0001
|
|
arc: N1_V02N0701 S3_V06N0203
|
|
arc: S1_V02S0401 E1_H01W0000
|
|
arc: S1_V02S0501 W1_H02E0501
|
|
arc: V00T0100 H02W0101
|
|
arc: W1_H02W0101 V02S0101
|
|
arc: W1_H02W0201 V06N0103
|
|
arc: W1_H02W0301 V02N0301
|
|
arc: W1_H02W0501 E1_H01W0100
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
arc: W3_H06W0103 E1_H02W0101
|
|
arc: A2 E1_H02W0501
|
|
arc: A4 F5
|
|
arc: A5 H02E0501
|
|
arc: A6 F5
|
|
arc: B0 H02W0301
|
|
arc: B2 H02W0101
|
|
arc: C0 E1_H02W0601
|
|
arc: C2 E1_H02W0401
|
|
arc: C4 H02E0601
|
|
arc: C5 H01E0001
|
|
arc: C6 H02E0601
|
|
arc: D0 V00T0100
|
|
arc: D2 E1_H02W0001
|
|
arc: D4 H00R0100
|
|
arc: D6 H00R0100
|
|
arc: E1_H01E0101 F4
|
|
arc: F0 F5A_SLICE
|
|
arc: F1 FXA_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: M0 H02W0601
|
|
arc: M1 H02E0001
|
|
arc: M2 H02W0601
|
|
arc: V01S0000 F1
|
|
arc: W3_H06W0203 F4
|
|
arc: W3_H06W0303 F6
|
|
word: SLICEA.K0.INIT 1111111100110000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 1101110011011101
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 1010000010100000
|
|
word: SLICEC.K0.INIT 1010000000000000
|
|
word: SLICED.K0.INIT 0000101010101010
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.B0MUX 1
|
|
|
|
.tile R26C48:PLC2
|
|
arc: E1_H02E0701 N1_V02S0701
|
|
arc: E3_H06E0103 H01E0101
|
|
arc: H00R0000 V02S0601
|
|
arc: H00R0100 S1_V02N0501
|
|
arc: N1_V02N0001 S1_V02N0001
|
|
arc: N1_V02N0101 S1_V02N0101
|
|
arc: N1_V02N0201 N1_V01S0000
|
|
arc: N1_V02N0701 H02W0701
|
|
arc: S1_V02S0201 E1_H02W0201
|
|
arc: S1_V02S0401 N1_V02S0101
|
|
arc: S3_V06S0103 N1_V01S0100
|
|
arc: S3_V06S0303 N1_V01S0100
|
|
arc: V00B0000 S1_V02N0201
|
|
arc: V00B0100 E1_H02W0701
|
|
arc: W1_H02W0101 N1_V02S0101
|
|
arc: W1_H02W0201 E1_H01W0000
|
|
arc: W1_H02W0601 S1_V02N0601
|
|
arc: A1 H02W0701
|
|
arc: A6 N1_V01S0100
|
|
arc: A7 H00L0000
|
|
arc: B6 H02E0301
|
|
arc: B7 V02N0501
|
|
arc: C2 V02N0601
|
|
arc: C4 E1_H02W0601
|
|
arc: C6 V00T0000
|
|
arc: CE0 H00R0000
|
|
arc: CE1 V02S0201
|
|
arc: CE2 V02S0601
|
|
arc: CE3 V02S0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D1 H02W0201
|
|
arc: D2 V00B0100
|
|
arc: D4 V02N0401
|
|
arc: D6 H00L0100
|
|
arc: D7 E1_H02W0201
|
|
arc: E1_H01E0001 F4
|
|
arc: E1_H01E0101 F1
|
|
arc: E1_H02E0601 F4
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00L0000 F2
|
|
arc: H00L0100 Q1
|
|
arc: H01W0000 F4
|
|
arc: H01W0100 F7
|
|
arc: M0 V00B0000
|
|
arc: M1 H00R0100
|
|
arc: M3 H00R0100
|
|
arc: M5 E1_H02W0001
|
|
arc: M7 H02E0201
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 F4
|
|
arc: N1_V01N0101 F2
|
|
arc: N1_V02N0301 Q3
|
|
arc: N1_V02N0401 F6
|
|
arc: N1_V02N0501 Q5
|
|
arc: S1_V02S0601 F4
|
|
arc: S1_V02S0701 Q7
|
|
arc: S3_V06S0203 F4
|
|
arc: V00T0000 Q0
|
|
arc: V01S0000 F1
|
|
arc: V01S0100 F2
|
|
arc: W1_H02W0001 F2
|
|
arc: W1_H02W0301 F1
|
|
arc: W1_H02W0401 F4
|
|
word: SLICED.K1.INIT 1000100000000000
|
|
word: SLICEB.K0.INIT 0000000011110000
|
|
word: SLICED.K0.INIT 1000001001000001
|
|
word: SLICEC.K0.INIT 0000111100000000
|
|
word: SLICEA.K1.INIT 0000000010101010
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R26C49:PLC2
|
|
arc: E1_H01E0101 W3_H06E0203
|
|
arc: E1_H02E0201 V02S0201
|
|
arc: E1_H02E0301 S1_V02N0301
|
|
arc: E1_H02E0401 W3_H06E0203
|
|
arc: E1_H02E0501 S3_V06N0303
|
|
arc: E1_H02E0601 W1_H02E0601
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: H00L0100 V02S0101
|
|
arc: N1_V02N0101 S1_V02N0101
|
|
arc: N1_V02N0201 H01E0001
|
|
arc: N1_V02N0301 S1_V02N0301
|
|
arc: N1_V02N0501 S3_V06N0303
|
|
arc: N1_V02N0601 N1_V01S0000
|
|
arc: N1_V02N0701 H02W0701
|
|
arc: N3_V06N0203 W3_H06E0203
|
|
arc: S1_V02S0601 E1_H02W0601
|
|
arc: V00T0000 V02S0401
|
|
arc: V01S0100 S3_V06N0303
|
|
arc: W1_H02W0501 H01E0101
|
|
arc: W1_H02W0701 N1_V02S0701
|
|
arc: A0 H02E0701
|
|
arc: B0 S1_V02N0101
|
|
arc: B2 E1_H01W0100
|
|
arc: B6 V02N0501
|
|
arc: C0 E1_H02W0601
|
|
arc: C2 E1_H01W0000
|
|
arc: C3 F4
|
|
arc: C4 V02N0201
|
|
arc: CE0 H00L0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02N0001
|
|
arc: D3 F2
|
|
arc: D4 S1_V02N0401
|
|
arc: D6 V02S0601
|
|
arc: E1_H01E0001 Q0
|
|
arc: F0 F0_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: H01W0000 F3
|
|
arc: LSR1 V00T0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: N1_V01N0001 Q0
|
|
arc: N1_V01N0101 F6
|
|
arc: N1_V02N0401 F6
|
|
arc: V01S0000 F3
|
|
arc: W1_H02W0001 F2
|
|
arc: W1_H02W0101 F3
|
|
arc: W1_H02W0201 Q0
|
|
arc: W1_H02W0401 F4
|
|
arc: W1_H02W0601 F4
|
|
word: SLICEB.K1.INIT 0000000000001111
|
|
word: SLICED.K0.INIT 1111111111001100
|
|
word: SLICEA.K0.INIT 0100000000000000
|
|
word: SLICEB.K0.INIT 0000110000001100
|
|
word: SLICEC.K0.INIT 0000111100000000
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET SET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
|
|
.tile R26C4:PLC2
|
|
arc: W3_H06W0303 E3_H06W0203
|
|
|
|
.tile R26C50:PLC2
|
|
arc: E1_H02E0101 V02S0101
|
|
arc: E1_H02E0401 N1_V01S0000
|
|
arc: H00L0100 V02S0301
|
|
arc: H00R0000 S1_V02N0601
|
|
arc: N1_V02N0001 H01E0001
|
|
arc: N1_V02N0201 H06E0103
|
|
arc: N1_V02N0301 H02W0301
|
|
arc: N1_V02N0401 V01N0001
|
|
arc: N1_V02N0501 H01E0101
|
|
arc: N1_V02N0601 W1_H02E0601
|
|
arc: N1_V02N0701 S1_V02N0701
|
|
arc: N3_V06N0303 S1_V02N0601
|
|
arc: S1_V02S0601 H02W0601
|
|
arc: V00B0000 H02W0601
|
|
arc: V00T0000 V02N0401
|
|
arc: W1_H02W0001 E1_H01W0000
|
|
arc: W1_H02W0601 S1_V02N0601
|
|
arc: W1_H02W0701 S1_V02N0701
|
|
arc: A0 W1_H02E0701
|
|
arc: A3 V02S0701
|
|
arc: A4 V02N0101
|
|
arc: A5 V02N0101
|
|
arc: A6 H02E0501
|
|
arc: A7 H02E0501
|
|
arc: B0 V02N0101
|
|
arc: B1 E1_H02W0301
|
|
arc: B3 H02E0301
|
|
arc: B4 V02S0501
|
|
arc: B5 H02W0301
|
|
arc: B7 H02W0301
|
|
arc: C0 H02W0601
|
|
arc: C1 H02E0601
|
|
arc: C2 V02N0601
|
|
arc: C3 H00L0000
|
|
arc: C5 H02E0401
|
|
arc: CE0 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H02W0001
|
|
arc: D2 H00R0000
|
|
arc: D3 V00T0100
|
|
arc: D4 V00B0000
|
|
arc: D5 V00B0000
|
|
arc: E1_H01E0001 F1
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F5C_SLICE
|
|
arc: F5 FXC_SLICE
|
|
arc: F6 F5D_SLICE
|
|
arc: H00L0000 Q0
|
|
arc: H00R0100 F5
|
|
arc: H01W0000 Q0
|
|
arc: H01W0100 Q1
|
|
arc: LSR1 V00T0000
|
|
arc: M1 H00L0100
|
|
arc: M4 H02W0401
|
|
arc: M5 H02W0001
|
|
arc: M6 H02W0401
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: N1_V01N0001 Q1
|
|
arc: N1_V01N0101 Q0
|
|
arc: N1_V02N0101 F3
|
|
arc: S1_V02S0101 F1
|
|
arc: V00T0100 Q1
|
|
arc: V01S0000 F2
|
|
arc: W1_H02W0201 F2
|
|
arc: W3_H06W0103 F2
|
|
word: SLICEA.K0.INIT 0100000000000000
|
|
word: SLICEC.K0.INIT 1110111011001100
|
|
word: SLICEC.K1.INIT 1111111011111100
|
|
word: SLICED.K0.INIT 1010101010101010
|
|
word: SLICED.K1.INIT 1110111011101110
|
|
word: SLICEB.K1.INIT 1000100010000000
|
|
word: SLICEA.K1.INIT 0011000000110000
|
|
word: SLICEB.K0.INIT 1111000000000000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET SET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET SET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
|
|
.tile R26C51:PLC2
|
|
arc: E1_H02E0301 V02N0301
|
|
arc: E1_H02E0401 V02N0401
|
|
arc: E1_H02E0601 V02N0601
|
|
arc: H00L0000 W1_H02E0201
|
|
arc: H00R0000 V02S0601
|
|
arc: H01W0000 W3_H06E0103
|
|
arc: N1_V02N0001 H01E0001
|
|
arc: N1_V02N0501 S1_V02N0501
|
|
arc: N1_V02N0601 H01E0001
|
|
arc: S1_V02S0001 S3_V06N0003
|
|
arc: S1_V02S0101 H06E0103
|
|
arc: S1_V02S0201 H06E0103
|
|
arc: S1_V02S0401 H01E0001
|
|
arc: S1_V02S0501 N1_V02S0401
|
|
arc: V00T0000 S1_V02N0601
|
|
arc: V00T0100 V02S0701
|
|
arc: W1_H02W0001 V02N0001
|
|
arc: W1_H02W0301 V06S0003
|
|
arc: W1_H02W0401 N1_V01S0000
|
|
arc: W1_H02W0601 H01E0001
|
|
arc: A1 F5
|
|
arc: A2 V02N0701
|
|
arc: A4 V00T0000
|
|
arc: A5 V02N0101
|
|
arc: A6 N1_V01N0101
|
|
arc: A7 N1_V01S0100
|
|
arc: B1 V02S0101
|
|
arc: B2 V02S0101
|
|
arc: B3 H02E0101
|
|
arc: B4 V02S0501
|
|
arc: B5 E1_H02W0101
|
|
arc: B6 E1_H02W0101
|
|
arc: B7 V02N0501
|
|
arc: C1 S1_V02N0601
|
|
arc: C2 H00R0100
|
|
arc: C4 V02S0201
|
|
arc: C5 V01N0101
|
|
arc: C6 H02E0401
|
|
arc: C7 E1_H01E0101
|
|
arc: CE0 H00R0000
|
|
arc: CE2 V02S0601
|
|
arc: CE3 V02S0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D1 H02W0201
|
|
arc: D2 V02S0001
|
|
arc: D3 V00B0100
|
|
arc: D4 H02W0201
|
|
arc: D5 V02S0401
|
|
arc: D6 F2
|
|
arc: D7 S1_V02N0401
|
|
arc: E1_H01E0101 Q1
|
|
arc: F0 F5A_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00R0100 Q7
|
|
arc: M0 V00B0000
|
|
arc: M1 H00L0000
|
|
arc: M2 V00T0100
|
|
arc: M4 E1_H02W0401
|
|
arc: M7 E1_H02W0201
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0101 Q4
|
|
arc: N1_V02N0201 F0
|
|
arc: N1_V02N0401 F6
|
|
arc: N1_V02N0701 F7
|
|
arc: V00B0000 F4
|
|
arc: V00B0100 Q7
|
|
arc: V01S0000 Q1
|
|
word: SLICEC.K0.INIT 1000001011000011
|
|
word: SLICEC.K1.INIT 1000010000100001
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 1000100000001000
|
|
word: SLICED.K1.INIT 1000101011001111
|
|
word: SLICEB.K0.INIT 1010010110000100
|
|
word: SLICEB.K1.INIT 1100110000110011
|
|
word: SLICED.K0.INIT 1001000000000000
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R26C52:PLC2
|
|
arc: H00R0000 V02N0601
|
|
arc: N1_V02N0001 H06E0003
|
|
arc: V01S0000 S3_V06N0103
|
|
arc: W1_H02W0201 N1_V01S0000
|
|
arc: W1_H02W0301 V02N0301
|
|
arc: A0 V02N0701
|
|
arc: A1 V02N0501
|
|
arc: A2 V02N0701
|
|
arc: A3 V02N0501
|
|
arc: A4 V02N0301
|
|
arc: A5 H02W0701
|
|
arc: B0 V02N0101
|
|
arc: B1 V02N0101
|
|
arc: B2 V02N0101
|
|
arc: B3 V02N0101
|
|
arc: B4 V02S0701
|
|
arc: C0 H02E0601
|
|
arc: C1 H02E0401
|
|
arc: C2 H02E0401
|
|
arc: C3 H02E0601
|
|
arc: C4 H02W0601
|
|
arc: C5 V02S0001
|
|
arc: CE0 H00R0000
|
|
arc: CE1 H00R0000
|
|
arc: CLK1 G_HPBX0000
|
|
arc: D0 V02N0001
|
|
arc: D1 V02N0001
|
|
arc: D2 V02N0001
|
|
arc: D3 V02N0001
|
|
arc: D4 S1_V02N0401
|
|
arc: D5 V02S0401
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: LSR1 H02E0301
|
|
arc: MUXCLK0 CLK1
|
|
arc: MUXCLK1 CLK1
|
|
arc: N3_V06N0103 Q1
|
|
arc: W3_H06W0003 Q0
|
|
arc: W3_H06W0103 Q2
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
enum: SLICEA.MODE DPRAM
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.WREMUX WRE
|
|
enum: CLK1.CLKMUX CLK
|
|
enum: SLICEA.MODE DPRAM
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE DPRAM
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE DPRAM
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE RAMW
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK1.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK1.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK1.CLKMUX CLK
|
|
|
|
.tile R26C53:PLC2
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: N1_V02N0101 S3_V06N0103
|
|
arc: N1_V02N0201 S1_V02N0701
|
|
arc: N1_V02N0401 S1_V02N0101
|
|
arc: N3_V06N0103 S1_V02N0101
|
|
arc: V01S0100 S3_V06N0303
|
|
arc: W1_H02W0101 S1_V02N0101
|
|
arc: W1_H02W0201 V02N0201
|
|
arc: W1_H02W0401 S1_V02N0401
|
|
arc: W1_H02W0601 V02N0601
|
|
arc: W1_H02W0701 V06S0203
|
|
arc: W3_H06W0103 S3_V06N0103
|
|
arc: W3_H06W0303 E3_H06W0203
|
|
|
|
.tile R26C57:PLC2
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
|
|
.tile R26C59:PLC2
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: E3_H06E0103 V01N0101
|
|
arc: S1_V02S0301 N3_V06S0003
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
|
|
.tile R26C5:PLC2
|
|
arc: S3_V06S0303 E3_H06W0303
|
|
|
|
.tile R26C62:PLC2
|
|
arc: S1_V02S0701 E1_H02W0701
|
|
|
|
.tile R26C64:PLC2
|
|
arc: E1_H02E0601 N3_V06S0303
|
|
arc: W1_H02W0701 V02S0701
|
|
|
|
.tile R26C65:PLC2
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: S1_V02S0201 N3_V06S0103
|
|
arc: S1_V02S0601 H02E0601
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
|
|
.tile R26C71:PLC2
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
|
|
.tile R26C77:PLC2
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
|
|
.tile R26C7:PLC2
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
|
|
.tile R26C83:PLC2
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
|
|
.tile R26C87:PLC2
|
|
arc: E1_H02E0701 V02N0701
|
|
|
|
.tile R26C8:PLC2
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
|
|
.tile R27C10:PLC2
|
|
arc: H01W0100 E3_H06W0303
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
arc: W3_H06W0203 E3_H06W0203
|
|
arc: W3_H06W0303 E1_H01W0100
|
|
|
|
.tile R27C11:PLC2
|
|
arc: H01W0100 E3_H06W0303
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
arc: W3_H06W0303 E3_H06W0203
|
|
|
|
.tile R27C12:PLC2
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
arc: W3_H06W0203 E3_H06W0203
|
|
|
|
.tile R27C13:PLC2
|
|
arc: E1_H02E0201 S1_V02N0201
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
arc: N3_V06N0103 E3_H06W0103
|
|
arc: S3_V06S0303 E3_H06W0303
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
arc: W3_H06W0203 E3_H06W0203
|
|
|
|
.tile R27C14:PLC2
|
|
arc: S3_V06S0103 E3_H06W0103
|
|
|
|
.tile R27C15:PLC2
|
|
arc: E1_H02E0301 W1_H02E0201
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: S3_V06S0003 E3_H06W0003
|
|
arc: W3_H06W0303 E3_H06W0203
|
|
|
|
.tile R27C16:PLC2
|
|
arc: E1_H02E0001 E3_H06W0003
|
|
arc: E1_H02E0201 E3_H06W0103
|
|
arc: E1_H02E0401 N1_V02S0401
|
|
arc: W3_H06W0003 E1_H01W0000
|
|
arc: W3_H06W0103 E1_H01W0100
|
|
arc: W3_H06W0203 E3_H06W0203
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
|
|
.tile R27C17:PLC2
|
|
arc: H00R0000 H02W0401
|
|
arc: H01W0100 E3_H06W0303
|
|
arc: N3_V06N0203 E3_H06W0203
|
|
arc: V00B0000 H02E0401
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
arc: W3_H06W0303 E1_H01W0100
|
|
arc: A0 E1_H02W0701
|
|
arc: A1 E1_H02W0701
|
|
arc: A2 E1_H02W0501
|
|
arc: A3 E1_H02W0501
|
|
arc: A4 S1_V02N0301
|
|
arc: A5 N1_V02S0101
|
|
arc: B0 H02W0301
|
|
arc: B1 H02W0301
|
|
arc: B2 H02W0301
|
|
arc: B3 H02W0301
|
|
arc: B4 N1_V02S0501
|
|
arc: B5 W1_H02E0301
|
|
arc: C0 H02W0601
|
|
arc: C1 H02W0601
|
|
arc: C2 H02W0601
|
|
arc: C3 H02W0601
|
|
arc: C4 V02N0001
|
|
arc: C5 V01N0101
|
|
arc: CE0 H00R0000
|
|
arc: CE1 H00R0000
|
|
arc: CLK1 G_HPBX0000
|
|
arc: D0 H02E0201
|
|
arc: D1 H02E0001
|
|
arc: D2 H02E0201
|
|
arc: D3 H02E0201
|
|
arc: D4 V02N0401
|
|
arc: D5 V00B0000
|
|
arc: E3_H06E0103 Q1
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: H01W0000 Q2
|
|
arc: LSR1 E1_H02W0301
|
|
arc: MUXCLK0 CLK1
|
|
arc: MUXCLK1 CLK1
|
|
arc: V01S0000 Q3
|
|
arc: W3_H06W0003 Q0
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
enum: SLICEA.MODE DPRAM
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.WREMUX WRE
|
|
enum: CLK1.CLKMUX CLK
|
|
enum: SLICEA.MODE DPRAM
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE DPRAM
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE DPRAM
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE RAMW
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK1.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK1.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK1.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK1.CLKMUX CLK
|
|
|
|
.tile R27C18:PLC2
|
|
arc: H01W0100 E3_H06W0303
|
|
arc: W1_H02W0301 E1_H02W0301
|
|
arc: W1_H02W0401 E1_H02W0401
|
|
arc: W1_H02W0601 E1_H02W0601
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
arc: W3_H06W0303 E3_H06W0203
|
|
|
|
.tile R27C19:PLC2
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
arc: W1_H02W0301 E1_H02W0301
|
|
arc: W1_H02W0501 E1_H02W0401
|
|
arc: W1_H02W0701 E1_H02W0701
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
arc: W3_H06W0303 E3_H06W0203
|
|
|
|
.tile R27C20:PLC2
|
|
arc: W1_H02W0301 E3_H06W0003
|
|
arc: W1_H02W0401 E3_H06W0203
|
|
arc: W1_H02W0601 E3_H06W0303
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
|
|
.tile R27C21:PLC2
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: W1_H02W0301 E3_H06W0003
|
|
arc: W1_H02W0401 E3_H06W0203
|
|
arc: W1_H02W0701 E3_H06W0203
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
|
|
.tile R27C22:PLC2
|
|
arc: E1_H02E0001 E3_H06W0003
|
|
arc: E1_H02E0201 E3_H06W0103
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
arc: W3_H06W0203 E3_H06W0203
|
|
arc: W3_H06W0303 E1_H01W0100
|
|
|
|
.tile R27C23:PLC2
|
|
arc: E1_H02E0001 V02N0001
|
|
arc: E1_H02E0101 S1_V02N0101
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: H01W0100 E3_H06W0303
|
|
arc: S3_V06S0003 E3_H06W0003
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
arc: W3_H06W0303 E3_H06W0203
|
|
arc: A0 E1_H02W0701
|
|
arc: A1 E1_H02W0501
|
|
arc: A2 E1_H02W0501
|
|
arc: A3 E1_H02W0501
|
|
arc: A4 S1_V02N0101
|
|
arc: A5 S1_V02N0301
|
|
arc: B0 E1_H02W0101
|
|
arc: B1 E1_H02W0101
|
|
arc: B2 E1_H02W0101
|
|
arc: B3 E1_H02W0101
|
|
arc: B4 H02W0301
|
|
arc: B5 S1_V02N0701
|
|
arc: C0 H02W0401
|
|
arc: C1 H02W0401
|
|
arc: C2 H02W0401
|
|
arc: C3 H02W0401
|
|
arc: C4 V02N0001
|
|
arc: C5 N1_V02S0201
|
|
arc: CE0 H02W0101
|
|
arc: CE1 H02W0101
|
|
arc: CLK1 G_HPBX0000
|
|
arc: D0 H02E0001
|
|
arc: D1 H02E0201
|
|
arc: D2 H02E0201
|
|
arc: D3 H02E0001
|
|
arc: D4 V02N0601
|
|
arc: D5 V02N0401
|
|
arc: E3_H06E0003 Q0
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: LSR1 E1_H02W0301
|
|
arc: MUXCLK0 CLK1
|
|
arc: MUXCLK1 CLK1
|
|
arc: N3_V06N0103 Q2
|
|
arc: W3_H06W0003 Q3
|
|
arc: W3_H06W0103 Q1
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK1.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK1.CLKMUX CLK
|
|
enum: SLICEA.MODE DPRAM
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.WREMUX WRE
|
|
enum: CLK1.CLKMUX CLK
|
|
enum: SLICEA.MODE DPRAM
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE DPRAM
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE DPRAM
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE RAMW
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK1.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK1.CLKMUX CLK
|
|
|
|
.tile R27C24:PLC2
|
|
arc: W1_H02W0101 E1_H02W0101
|
|
arc: W1_H02W0301 N1_V02S0301
|
|
arc: W1_H02W0401 E1_H02W0401
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
arc: W3_H06W0203 E3_H06W0203
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
|
|
.tile R27C25:PLC2
|
|
arc: E1_H02E0201 S1_V02N0201
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: V00B0100 H02W0701
|
|
arc: V00T0000 W1_H02E0001
|
|
arc: V00T0100 W1_H02E0101
|
|
arc: W1_H02W0101 E1_H01W0100
|
|
arc: W1_H02W0301 E1_H02W0301
|
|
arc: W1_H02W0501 E1_H02W0401
|
|
arc: W1_H02W0701 E1_H02W0701
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
arc: A0 E1_H02W0701
|
|
arc: A1 E1_H02W0701
|
|
arc: A2 E1_H02W0701
|
|
arc: A3 E1_H02W0701
|
|
arc: A4 V00T0100
|
|
arc: A5 V02S0101
|
|
arc: B0 E1_H01W0100
|
|
arc: B1 E1_H01W0100
|
|
arc: B2 E1_H01W0100
|
|
arc: B3 E1_H01W0100
|
|
arc: B4 V02S0701
|
|
arc: B5 V02N0701
|
|
arc: C0 H02W0401
|
|
arc: C1 H02W0401
|
|
arc: C2 H02W0401
|
|
arc: C3 H02W0401
|
|
arc: C4 V00T0000
|
|
arc: C5 V00B0100
|
|
arc: CE0 H02W0101
|
|
arc: CE1 H02W0101
|
|
arc: CLK1 G_HPBX0000
|
|
arc: D0 E1_H02W0001
|
|
arc: D1 E1_H02W0201
|
|
arc: D2 E1_H02W0001
|
|
arc: D3 E1_H02W0001
|
|
arc: D4 V02N0601
|
|
arc: D5 V02N0401
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: LSR1 E1_H02W0301
|
|
arc: MUXCLK0 CLK1
|
|
arc: MUXCLK1 CLK1
|
|
arc: V01S0000 Q1
|
|
arc: V01S0100 Q3
|
|
arc: W3_H06W0003 Q0
|
|
arc: W3_H06W0103 Q2
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK1.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK1.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK1.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK1.CLKMUX CLK
|
|
enum: SLICEA.MODE DPRAM
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.WREMUX WRE
|
|
enum: CLK1.CLKMUX CLK
|
|
enum: SLICEA.MODE DPRAM
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE DPRAM
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE DPRAM
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE RAMW
|
|
|
|
.tile R27C26:PLC2
|
|
arc: E1_H01E0001 E3_H06W0003
|
|
arc: E1_H02E0101 E3_H06W0103
|
|
arc: E1_H02E0201 V01N0001
|
|
arc: E1_H02E0401 E3_H06W0203
|
|
arc: E1_H02E0501 E3_H06W0303
|
|
arc: E1_H02E0601 E3_H06W0303
|
|
arc: H01W0100 E3_H06W0303
|
|
arc: W1_H02W0101 E3_H06W0103
|
|
arc: W1_H02W0401 E3_H06W0203
|
|
arc: W1_H02W0701 N1_V02S0701
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
arc: W3_H06W0103 E1_H01W0100
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
arc: W3_H06W0303 E3_H06W0203
|
|
|
|
.tile R27C27:PLC2
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: H00R0100 H02E0501
|
|
arc: N1_V02N0201 E3_H06W0103
|
|
arc: V00B0000 H02E0601
|
|
arc: V00B0100 N1_V02S0101
|
|
arc: V00T0000 H02E0201
|
|
arc: V00T0100 N1_V02S0501
|
|
arc: W1_H02W0001 E1_H01W0000
|
|
arc: W1_H02W0201 E1_H01W0000
|
|
arc: W1_H02W0301 E3_H06W0003
|
|
arc: W1_H02W0401 E3_H06W0203
|
|
arc: W1_H02W0701 E3_H06W0203
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
arc: W3_H06W0203 E3_H06W0203
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
arc: A0 H01E0001
|
|
arc: A1 H01E0001
|
|
arc: A2 H01E0001
|
|
arc: A3 H01E0001
|
|
arc: A4 E1_H02W0501
|
|
arc: A5 V00T0100
|
|
arc: B0 V00B0000
|
|
arc: B1 V00B0000
|
|
arc: B2 H00R0100
|
|
arc: B3 H00R0100
|
|
arc: B4 N1_V02S0701
|
|
arc: B5 V00B0100
|
|
arc: C0 H02E0401
|
|
arc: C1 H02E0401
|
|
arc: C2 H02E0401
|
|
arc: C3 H02E0401
|
|
arc: C4 V00T0000
|
|
arc: C5 V02N0001
|
|
arc: CE0 H02E0101
|
|
arc: CE1 H02E0101
|
|
arc: CLK1 G_HPBX0000
|
|
arc: D0 H02W0001
|
|
arc: D1 H02W0001
|
|
arc: D2 H02W0001
|
|
arc: D3 H02W0001
|
|
arc: D4 V02N0601
|
|
arc: D5 W1_H02E0201
|
|
arc: E3_H06E0103 Q1
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: H01W0100 Q0
|
|
arc: LSR1 E1_H02W0301
|
|
arc: MUXCLK0 CLK1
|
|
arc: MUXCLK1 CLK1
|
|
arc: N3_V06N0003 Q3
|
|
arc: W3_H06W0103 Q2
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK1.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK1.CLKMUX CLK
|
|
enum: SLICEA.MODE DPRAM
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.WREMUX WRE
|
|
enum: CLK1.CLKMUX CLK
|
|
enum: SLICEA.MODE DPRAM
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE DPRAM
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE DPRAM
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE RAMW
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK1.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK1.CLKMUX CLK
|
|
|
|
.tile R27C28:PLC2
|
|
arc: H01W0000 E3_H06W0103
|
|
arc: N3_V06N0303 E3_H06W0303
|
|
arc: W1_H02W0001 E3_H06W0003
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
arc: W3_H06W0203 E3_H06W0203
|
|
|
|
.tile R27C29:PLC2
|
|
arc: E1_H02E0501 S1_V02N0501
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: W1_H02W0301 E1_H02W0301
|
|
arc: W1_H02W0501 S1_V02N0501
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
arc: W3_H06W0303 E1_H02W0601
|
|
|
|
.tile R27C2:PLC2
|
|
arc: S3_V06S0203 H06W0203
|
|
|
|
.tile R27C30:PLC2
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
arc: W3_H06W0203 E3_H06W0203
|
|
arc: W3_H06W0303 E1_H01W0100
|
|
|
|
.tile R27C31:PLC2
|
|
arc: E1_H01E0001 W3_H06E0003
|
|
arc: E1_H02E0001 S1_V02N0001
|
|
arc: E1_H02E0101 E3_H06W0103
|
|
arc: E1_H02E0301 E3_H06W0003
|
|
arc: E1_H02E0401 E1_H01W0000
|
|
arc: E1_H02E0601 E1_H01W0000
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: H00L0100 H02W0301
|
|
arc: H00R0000 H02W0401
|
|
arc: H00R0100 H02W0701
|
|
arc: V00B0000 H02W0401
|
|
arc: V00T0000 H02W0001
|
|
arc: V00T0100 S1_V02N0501
|
|
arc: W1_H02W0301 E1_H02W0301
|
|
arc: W1_H02W0601 E1_H02W0601
|
|
arc: W3_H06W0303 E1_H01W0100
|
|
arc: A0 E1_H02W0701
|
|
arc: A1 E1_H02W0701
|
|
arc: A2 E1_H02W0701
|
|
arc: A3 E1_H02W0701
|
|
arc: A4 W1_H02E0501
|
|
arc: A5 S1_V02N0301
|
|
arc: B0 V00B0000
|
|
arc: B1 H00R0100
|
|
arc: B2 H00R0000
|
|
arc: B3 H00R0000
|
|
arc: B4 N1_V02S0701
|
|
arc: C0 E1_H01W0000
|
|
arc: C1 E1_H01W0000
|
|
arc: C2 E1_H01W0000
|
|
arc: C3 E1_H01W0000
|
|
arc: C4 V00T0000
|
|
arc: C5 V00T0100
|
|
arc: CE0 H00L0100
|
|
arc: CE1 H00L0100
|
|
arc: CLK1 G_HPBX0000
|
|
arc: D0 E1_H02W0201
|
|
arc: D1 E1_H02W0001
|
|
arc: D2 E1_H02W0001
|
|
arc: D3 E1_H02W0001
|
|
arc: D4 V02N0401
|
|
arc: D5 H02W0201
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: H01W0100 Q1
|
|
arc: LSR1 E1_H02W0301
|
|
arc: MUXCLK0 CLK1
|
|
arc: MUXCLK1 CLK1
|
|
arc: N3_V06N0003 Q0
|
|
arc: W3_H06W0103 Q2
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK1.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK1.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK1.CLKMUX CLK
|
|
enum: SLICEA.MODE DPRAM
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.WREMUX WRE
|
|
enum: CLK1.CLKMUX CLK
|
|
enum: SLICEA.MODE DPRAM
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE DPRAM
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE DPRAM
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE RAMW
|
|
|
|
.tile R27C32:PLC2
|
|
arc: E1_H02E0601 E3_H06W0303
|
|
arc: H01W0000 E3_H06W0103
|
|
arc: V00B0100 V02N0301
|
|
arc: W1_H02W0001 V02N0001
|
|
arc: W1_H02W0201 N1_V01S0000
|
|
arc: W1_H02W0301 E3_H06W0003
|
|
arc: W1_H02W0401 E3_H06W0203
|
|
arc: W1_H02W0701 E3_H06W0203
|
|
arc: W3_H06W0003 E1_H01W0000
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
arc: W3_H06W0303 E3_H06W0203
|
|
arc: A0 H02W0701
|
|
arc: A1 H02W0701
|
|
arc: A2 H02W0701
|
|
arc: A3 H02W0701
|
|
arc: A4 S1_V02N0101
|
|
arc: A5 V02N0101
|
|
arc: B0 H02E0301
|
|
arc: B1 H02E0301
|
|
arc: B2 H02E0301
|
|
arc: B3 H02E0301
|
|
arc: B4 N1_V02S0701
|
|
arc: B5 V00B0100
|
|
arc: C0 H02E0401
|
|
arc: C1 H02E0401
|
|
arc: C2 H02E0601
|
|
arc: C3 H02E0601
|
|
arc: C4 V02N0001
|
|
arc: C5 H01E0001
|
|
arc: CE0 H02E0101
|
|
arc: CE1 H02E0101
|
|
arc: CLK1 G_HPBX0000
|
|
arc: D0 E1_H02W0001
|
|
arc: D1 E1_H02W0201
|
|
arc: D2 E1_H02W0001
|
|
arc: D3 E1_H02W0001
|
|
arc: D4 V02N0401
|
|
arc: D5 H02E0001
|
|
arc: E3_H06E0003 Q3
|
|
arc: E3_H06E0103 Q1
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: H01W0100 Q2
|
|
arc: LSR1 H02W0301
|
|
arc: MUXCLK0 CLK1
|
|
arc: MUXCLK1 CLK1
|
|
arc: V01S0000 Q0
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK1.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK1.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK1.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK1.CLKMUX CLK
|
|
enum: SLICEA.MODE DPRAM
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.WREMUX WRE
|
|
enum: CLK1.CLKMUX CLK
|
|
enum: SLICEA.MODE DPRAM
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE DPRAM
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE DPRAM
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE RAMW
|
|
|
|
.tile R27C33:PLC2
|
|
arc: E1_H02E0001 E1_H01W0000
|
|
arc: E1_H02E0201 E1_H01W0000
|
|
arc: E1_H02E0301 E3_H06W0003
|
|
arc: E1_H02E0701 E3_H06W0203
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: H01W0000 E3_H06W0103
|
|
arc: W1_H02W0001 E1_H01W0000
|
|
arc: W1_H02W0201 E1_H01W0000
|
|
arc: W1_H02W0301 E3_H06W0003
|
|
arc: W1_H02W0601 E1_H02W0301
|
|
arc: W1_H02W0701 E3_H06W0203
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
arc: W3_H06W0103 E1_H01W0100
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
|
|
.tile R27C34:PLC2
|
|
arc: E1_H02E0001 E3_H06W0003
|
|
arc: E1_H02E0201 E3_H06W0103
|
|
arc: E1_H02E0301 S1_V02N0301
|
|
arc: H00R0000 W1_H02E0601
|
|
arc: H01W0000 E3_H06W0103
|
|
arc: N3_V06N0203 E3_H06W0203
|
|
arc: V00B0100 N1_V02S0101
|
|
arc: W1_H02W0001 E3_H06W0003
|
|
arc: W1_H02W0201 E3_H06W0103
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
arc: W3_H06W0203 E1_H01W0000
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
arc: A0 H02E0701
|
|
arc: A1 H02E0701
|
|
arc: A2 H02E0701
|
|
arc: A3 H02E0701
|
|
arc: A4 V02N0101
|
|
arc: A5 S1_V02N0101
|
|
arc: B0 E1_H02W0301
|
|
arc: B1 E1_H02W0101
|
|
arc: B2 E1_H02W0101
|
|
arc: B3 E1_H02W0301
|
|
arc: B4 N1_V02S0701
|
|
arc: B5 V00B0100
|
|
arc: C0 E1_H02W0601
|
|
arc: C1 E1_H02W0601
|
|
arc: C2 E1_H02W0601
|
|
arc: C3 E1_H02W0601
|
|
arc: C4 H02W0601
|
|
arc: C5 S1_V02N0001
|
|
arc: CE0 H00R0000
|
|
arc: CE1 H00R0000
|
|
arc: CLK1 G_HPBX0000
|
|
arc: D0 H02E0201
|
|
arc: D1 H02E0001
|
|
arc: D2 H02E0201
|
|
arc: D3 H02E0001
|
|
arc: D4 V02N0401
|
|
arc: D5 V01N0001
|
|
arc: E3_H06E0003 Q3
|
|
arc: E3_H06E0103 Q1
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: H01W0100 Q2
|
|
arc: LSR1 H02E0301
|
|
arc: MUXCLK0 CLK1
|
|
arc: MUXCLK1 CLK1
|
|
arc: N3_V06N0003 Q0
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
enum: SLICEA.MODE DPRAM
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.WREMUX WRE
|
|
enum: CLK1.CLKMUX CLK
|
|
enum: SLICEA.MODE DPRAM
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE DPRAM
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE DPRAM
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE RAMW
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK1.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK1.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK1.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK1.CLKMUX CLK
|
|
|
|
.tile R27C35:PLC2
|
|
arc: E1_H02E0101 E1_H01W0100
|
|
arc: E1_H02E0501 V02N0501
|
|
arc: E1_H02E0701 V02S0701
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
arc: H00R0100 H02W0501
|
|
arc: H01W0000 E3_H06W0103
|
|
arc: N1_V02N0001 H02E0001
|
|
arc: N1_V02N0101 H06W0103
|
|
arc: N1_V02N0201 H02E0201
|
|
arc: N1_V02N0401 H06W0203
|
|
arc: N1_V02N0501 H06W0303
|
|
arc: N1_V02N0701 W1_H02E0701
|
|
arc: V00B0000 E1_H02W0401
|
|
arc: V00T0000 N1_V02S0601
|
|
arc: V00T0100 V02N0501
|
|
arc: W1_H02W0301 E3_H06W0003
|
|
arc: W1_H02W0601 V02N0601
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
arc: A0 W1_H02E0701
|
|
arc: A1 W1_H02E0701
|
|
arc: A2 V00B0000
|
|
arc: A3 W1_H02E0701
|
|
arc: A4 S1_V02N0301
|
|
arc: A5 V00T0000
|
|
arc: B0 H02W0101
|
|
arc: B1 H02W0301
|
|
arc: B2 H02W0101
|
|
arc: B3 H02W0301
|
|
arc: B4 N1_V02S0701
|
|
arc: B5 H02E0301
|
|
arc: C0 H02W0601
|
|
arc: C1 H02W0601
|
|
arc: C2 H02W0601
|
|
arc: C3 H02W0601
|
|
arc: C4 V00T0100
|
|
arc: C5 N1_V02S0001
|
|
arc: CE0 H00R0100
|
|
arc: CE1 H00R0100
|
|
arc: CLK1 G_HPBX0000
|
|
arc: D0 H02E0201
|
|
arc: D1 H02E0001
|
|
arc: D2 H02E0201
|
|
arc: D3 H02E0001
|
|
arc: D4 V02N0401
|
|
arc: D5 V02S0601
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: LSR1 E1_H02W0301
|
|
arc: MUXCLK0 CLK1
|
|
arc: MUXCLK1 CLK1
|
|
arc: N3_V06N0103 Q1
|
|
arc: S3_V06S0003 Q0
|
|
arc: W3_H06W0003 Q3
|
|
arc: W3_H06W0103 Q2
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
enum: SLICEA.MODE DPRAM
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.WREMUX WRE
|
|
enum: CLK1.CLKMUX CLK
|
|
enum: SLICEA.MODE DPRAM
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE DPRAM
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE DPRAM
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE RAMW
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK1.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK1.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK1.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK1.CLKMUX CLK
|
|
|
|
.tile R27C36:PLC2
|
|
arc: H00L0100 H02W0101
|
|
arc: H00R0000 H02W0401
|
|
arc: H00R0100 H02W0701
|
|
arc: H01W0100 E3_H06W0303
|
|
arc: N1_V02N0701 H06W0203
|
|
arc: V00B0000 H02W0401
|
|
arc: V00B0100 H02E0501
|
|
arc: V00T0000 H02W0201
|
|
arc: W1_H02W0101 E1_H02W0101
|
|
arc: W1_H02W0301 E1_H02W0201
|
|
arc: W1_H02W0501 E1_H02W0501
|
|
arc: W1_H02W0601 E1_H02W0301
|
|
arc: W3_H06W0203 E3_H06W0203
|
|
arc: A0 H00R0000
|
|
arc: A1 H00L0100
|
|
arc: A2 V00B0000
|
|
arc: A3 V00T0000
|
|
arc: A4 V02N0101
|
|
arc: A5 H02E0701
|
|
arc: B0 E1_H02W0101
|
|
arc: B1 E1_H02W0101
|
|
arc: B2 E1_H02W0101
|
|
arc: B3 E1_H02W0101
|
|
arc: B4 V02S0701
|
|
arc: B5 V02N0501
|
|
arc: C0 H00R0100
|
|
arc: C1 H00R0100
|
|
arc: C2 H00R0100
|
|
arc: C3 H00R0100
|
|
arc: C4 V00B0100
|
|
arc: C5 H02W0601
|
|
arc: CE0 H02E0101
|
|
arc: CE1 H02E0101
|
|
arc: CLK1 G_HPBX0000
|
|
arc: D0 E1_H02W0001
|
|
arc: D1 E1_H02W0001
|
|
arc: D2 E1_H02W0001
|
|
arc: D3 E1_H02W0001
|
|
arc: D4 V02N0401
|
|
arc: D5 V02S0601
|
|
arc: E3_H06E0103 Q1
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: LSR1 H02W0301
|
|
arc: MUXCLK0 CLK1
|
|
arc: MUXCLK1 CLK1
|
|
arc: N3_V06N0003 Q3
|
|
arc: W3_H06W0003 Q0
|
|
arc: W3_H06W0103 Q2
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
enum: SLICEA.MODE DPRAM
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.WREMUX WRE
|
|
enum: CLK1.CLKMUX CLK
|
|
enum: SLICEA.MODE DPRAM
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE DPRAM
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE DPRAM
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE RAMW
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK1.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK1.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK1.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK1.CLKMUX CLK
|
|
|
|
.tile R27C37:PLC2
|
|
arc: E1_H02E0001 S1_V02N0001
|
|
arc: E1_H02E0101 E3_H06W0103
|
|
arc: E1_H02E0401 E3_H06W0203
|
|
arc: E1_H02E0501 N1_V02S0501
|
|
arc: H00L0000 E1_H02W0201
|
|
arc: H00L0100 E1_H02W0101
|
|
arc: H00R0000 S1_V02N0401
|
|
arc: H00R0100 H02W0501
|
|
arc: N1_V02N0001 E3_H06W0003
|
|
arc: N1_V02N0101 W3_H06E0103
|
|
arc: N1_V02N0301 E1_H02W0301
|
|
arc: V00B0100 W1_H02E0501
|
|
arc: V00T0000 E1_H02W0201
|
|
arc: W1_H02W0101 E1_H02W0101
|
|
arc: W1_H02W0201 E1_H02W0201
|
|
arc: W1_H02W0301 E1_H02W0301
|
|
arc: W1_H02W0401 E1_H02W0101
|
|
arc: W1_H02W0601 S1_V02N0601
|
|
arc: W1_H02W0701 E3_H06W0203
|
|
arc: W3_H06W0003 E1_H01W0000
|
|
arc: W3_H06W0103 E1_H01W0100
|
|
arc: A0 H00L0000
|
|
arc: A1 H00L0000
|
|
arc: A2 H00L0100
|
|
arc: A3 V00T0000
|
|
arc: A4 V02N0101
|
|
arc: A5 N1_V02S0101
|
|
arc: B0 H02W0101
|
|
arc: B1 H02W0101
|
|
arc: B2 H02W0101
|
|
arc: B3 H02W0101
|
|
arc: B4 N1_V02S0701
|
|
arc: B5 H00R0000
|
|
arc: C0 E1_H02W0601
|
|
arc: C1 E1_H02W0401
|
|
arc: C2 E1_H02W0401
|
|
arc: C3 E1_H02W0601
|
|
arc: C4 V00B0100
|
|
arc: C5 H02W0601
|
|
arc: CE0 H00R0100
|
|
arc: CE1 H00R0100
|
|
arc: CLK1 G_HPBX0000
|
|
arc: D0 H02W0001
|
|
arc: D1 H02W0001
|
|
arc: D2 H02W0001
|
|
arc: D3 H02W0001
|
|
arc: D4 V02N0401
|
|
arc: D5 V01N0001
|
|
arc: E3_H06E0003 Q0
|
|
arc: E3_H06E0103 Q2
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: LSR1 E1_H02W0301
|
|
arc: MUXCLK0 CLK1
|
|
arc: MUXCLK1 CLK1
|
|
arc: N3_V06N0003 Q3
|
|
arc: N3_V06N0103 Q1
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
enum: SLICEA.MODE DPRAM
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.WREMUX WRE
|
|
enum: CLK1.CLKMUX CLK
|
|
enum: SLICEA.MODE DPRAM
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE DPRAM
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE DPRAM
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE RAMW
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK1.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK1.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK1.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK1.CLKMUX CLK
|
|
|
|
.tile R27C38:PLC2
|
|
arc: E1_H01E0001 E3_H06W0003
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: H00L0100 H02W0101
|
|
arc: H01W0000 E3_H06W0103
|
|
arc: H01W0100 E3_H06W0303
|
|
arc: N1_V02N0001 S1_V02N0501
|
|
arc: V00T0000 H02W0201
|
|
arc: V00T0100 E1_H02W0301
|
|
arc: W1_H02W0001 E1_H02W0001
|
|
arc: W1_H02W0101 E3_H06W0103
|
|
arc: W1_H02W0201 E3_H06W0103
|
|
arc: W1_H02W0301 E3_H06W0003
|
|
arc: W1_H02W0501 E3_H06W0303
|
|
arc: W1_H02W0601 N1_V02S0601
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
arc: A0 H00L0100
|
|
arc: A1 H00L0100
|
|
arc: A2 V00T0000
|
|
arc: A3 V00T0000
|
|
arc: A4 S1_V02N0101
|
|
arc: A5 H02E0501
|
|
arc: B0 H02E0101
|
|
arc: B1 H02E0101
|
|
arc: B2 H02E0101
|
|
arc: B3 H02E0101
|
|
arc: B4 N1_V02S0701
|
|
arc: B5 V02N0501
|
|
arc: C0 H02E0401
|
|
arc: C1 H02E0401
|
|
arc: C2 H02E0401
|
|
arc: C3 H02E0401
|
|
arc: C4 V02N0001
|
|
arc: C5 N1_V02S0201
|
|
arc: CE0 E1_H02W0101
|
|
arc: CE1 E1_H02W0101
|
|
arc: CE3 E1_H02W0101
|
|
arc: CLK1 G_HPBX0000
|
|
arc: D0 E1_H02W0001
|
|
arc: D1 E1_H02W0001
|
|
arc: D2 E1_H02W0001
|
|
arc: D3 E1_H02W0001
|
|
arc: D4 V02N0401
|
|
arc: D5 V02N0601
|
|
arc: E3_H06E0003 Q3
|
|
arc: E3_H06E0303 Q6
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: LSR1 H02W0301
|
|
arc: M6 V00T0100
|
|
arc: MUXCLK0 CLK1
|
|
arc: MUXCLK1 CLK1
|
|
arc: MUXCLK3 CLK1
|
|
arc: N1_V02N0201 Q2
|
|
arc: N3_V06N0103 Q1
|
|
arc: S3_V06S0303 Q6
|
|
arc: V01S0000 Q0
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK1.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK1.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK1.CLKMUX CLK
|
|
enum: SLICEA.MODE DPRAM
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.WREMUX WRE
|
|
enum: CLK1.CLKMUX CLK
|
|
enum: SLICEA.MODE DPRAM
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK1.CLKMUX CLK
|
|
enum: SLICEB.MODE DPRAM
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE DPRAM
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK1.CLKMUX CLK
|
|
enum: SLICEC.MODE RAMW
|
|
|
|
.tile R27C39:PLC2
|
|
arc: E1_H01E0101 E3_H06W0203
|
|
arc: E1_H02E0101 W1_H02E0001
|
|
arc: E1_H02E0201 E3_H06W0103
|
|
arc: E1_H02E0301 E3_H06W0003
|
|
arc: E1_H02E0401 N1_V01S0000
|
|
arc: E1_H02E0501 V02N0501
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
arc: H00L0000 V02S0001
|
|
arc: H00L0100 N1_V02S0101
|
|
arc: H00R0000 H02W0401
|
|
arc: H00R0100 S1_V02N0501
|
|
arc: N1_V02N0001 E3_H06W0003
|
|
arc: N1_V02N0301 E3_H06W0003
|
|
arc: N1_V02N0601 N1_V01S0000
|
|
arc: N1_V02N0701 S1_V02N0601
|
|
arc: S1_V02S0001 N1_V02S0501
|
|
arc: S1_V02S0701 E1_H02W0701
|
|
arc: S3_V06S0003 E3_H06W0003
|
|
arc: W1_H02W0101 E3_H06W0103
|
|
arc: W1_H02W0201 E3_H06W0103
|
|
arc: W1_H02W0301 E3_H06W0003
|
|
arc: W1_H02W0401 H01E0001
|
|
arc: W1_H02W0601 H01E0001
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
arc: W3_H06W0303 E1_H01W0100
|
|
arc: A0 V02N0501
|
|
arc: A1 H00L0100
|
|
arc: B0 V02N0101
|
|
arc: B1 Q1
|
|
arc: C0 N1_V01N0001
|
|
arc: C1 S1_V02N0601
|
|
arc: CE0 V02S0201
|
|
arc: CE1 V02S0201
|
|
arc: CE2 H00L0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 Q0
|
|
arc: D1 V00T0100
|
|
arc: E1_H02E0601 Q4
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: M0 H02W0601
|
|
arc: M1 H00R0100
|
|
arc: M2 E1_H02W0601
|
|
arc: M3 H00R0000
|
|
arc: M4 H02W0401
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: N1_V01N0001 Q2
|
|
arc: N1_V02N0101 F1
|
|
arc: N1_V02N0201 F0
|
|
arc: V00T0100 Q3
|
|
word: SLICEA.K0.INIT 1000010000100001
|
|
word: SLICEA.K1.INIT 1001000000001001
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R27C3:PLC2
|
|
arc: E3_H06E0303 W1_H02E0501
|
|
arc: N1_V02N0701 H02W0701
|
|
arc: S3_V06S0003 E3_H06W0003
|
|
arc: S3_V06S0103 H06W0103
|
|
arc: S3_V06S0203 H06W0203
|
|
arc: S3_V06S0303 E3_H06W0303
|
|
|
|
.tile R27C40:PLC2
|
|
arc: E1_H02E0301 V06N0003
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: H00L0000 H02E0201
|
|
arc: H00R0000 H02E0401
|
|
arc: H00R0100 E1_H02W0501
|
|
arc: N1_V02N0001 E1_H01W0000
|
|
arc: N1_V02N0201 V01N0001
|
|
arc: N1_V02N0401 E1_H01W0000
|
|
arc: N1_V02N0501 H02E0501
|
|
arc: N3_V06N0003 S1_V02N0001
|
|
arc: S1_V02S0001 N1_V02S0501
|
|
arc: S1_V02S0201 N1_V02S0201
|
|
arc: S1_V02S0301 N1_V02S0201
|
|
arc: S1_V02S0401 N1_V02S0401
|
|
arc: S1_V02S0501 E3_H06W0303
|
|
arc: S1_V02S0601 E3_H06W0303
|
|
arc: V00B0100 H02W0701
|
|
arc: V00T0000 H02E0201
|
|
arc: V00T0100 H02W0101
|
|
arc: W1_H02W0001 E3_H06W0003
|
|
arc: W1_H02W0101 E1_H02W0001
|
|
arc: W1_H02W0301 E3_H06W0003
|
|
arc: W1_H02W0401 V02S0401
|
|
arc: W1_H02W0601 V01N0001
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
arc: W3_H06W0303 E3_H06W0203
|
|
arc: A0 H00L0000
|
|
arc: A1 H00L0000
|
|
arc: A2 V00T0000
|
|
arc: A3 V00T0000
|
|
arc: A4 H02W0501
|
|
arc: A5 V00T0100
|
|
arc: B0 E1_H02W0101
|
|
arc: B1 E1_H02W0101
|
|
arc: B2 E1_H02W0101
|
|
arc: B3 E1_H02W0101
|
|
arc: B4 E1_H02W0301
|
|
arc: B5 S1_V02N0501
|
|
arc: C0 E1_H02W0401
|
|
arc: C1 E1_H02W0401
|
|
arc: C2 E1_H02W0401
|
|
arc: C3 E1_H02W0401
|
|
arc: C4 H02W0401
|
|
arc: C5 V02S0001
|
|
arc: CE0 H00R0100
|
|
arc: CE1 H00R0100
|
|
arc: CE2 H00R0000
|
|
arc: CLK1 G_HPBX0000
|
|
arc: D0 H01E0101
|
|
arc: D1 H01E0101
|
|
arc: D2 H01E0101
|
|
arc: D3 H01E0101
|
|
arc: D4 V02N0601
|
|
arc: D5 H02W0001
|
|
arc: E3_H06E0103 Q2
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: H01W0100 Q1
|
|
arc: LSR1 H02E0301
|
|
arc: M4 V00B0100
|
|
arc: MUXCLK0 CLK1
|
|
arc: MUXCLK1 CLK1
|
|
arc: MUXCLK2 CLK1
|
|
arc: N1_V02N0601 Q4
|
|
arc: V01S0000 Q0
|
|
arc: V01S0100 Q3
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
enum: SLICEA.MODE DPRAM
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.WREMUX WRE
|
|
enum: CLK1.CLKMUX CLK
|
|
enum: SLICEA.MODE DPRAM
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE DPRAM
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE DPRAM
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE RAMW
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK1.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK1.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK1.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK1.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK1.CLKMUX CLK
|
|
|
|
.tile R27C41:PLC2
|
|
arc: E1_H02E0001 N1_V02S0001
|
|
arc: E1_H02E0101 E3_H06W0103
|
|
arc: E1_H02E0201 S1_V02N0201
|
|
arc: E1_H02E0301 S1_V02N0301
|
|
arc: E1_H02E0401 W1_H02E0101
|
|
arc: E1_H02E0501 S3_V06N0303
|
|
arc: E1_H02E0601 N1_V01S0000
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: E3_H06E0203 N1_V01S0000
|
|
arc: H00L0000 E1_H02W0201
|
|
arc: H00L0100 H02E0301
|
|
arc: H00R0000 V02N0601
|
|
arc: H00R0100 S1_V02N0501
|
|
arc: N1_V02N0001 E1_H02W0001
|
|
arc: N1_V02N0101 N1_V01S0100
|
|
arc: N1_V02N0201 E3_H06W0103
|
|
arc: N1_V02N0401 H06W0203
|
|
arc: N1_V02N0701 S1_V02N0701
|
|
arc: N3_V06N0003 W3_H06E0003
|
|
arc: N3_V06N0103 E3_H06W0103
|
|
arc: S1_V02S0001 N3_V06S0003
|
|
arc: S1_V02S0101 V01N0101
|
|
arc: S1_V02S0401 H06W0203
|
|
arc: S1_V02S0601 V01N0001
|
|
arc: V00B0100 H02W0701
|
|
arc: V00T0000 N1_V02S0601
|
|
arc: W1_H02W0001 V02S0001
|
|
arc: W1_H02W0101 V06N0103
|
|
arc: W1_H02W0401 N1_V01S0000
|
|
arc: W1_H02W0501 S3_V06N0303
|
|
arc: W1_H02W0601 V02N0601
|
|
arc: W1_H02W0701 V02N0701
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
arc: W3_H06W0303 E3_H06W0203
|
|
arc: A3 E1_H02W0501
|
|
arc: A5 V02N0101
|
|
arc: B1 V02N0101
|
|
arc: B3 V02S0101
|
|
arc: B5 V00B0100
|
|
arc: C3 W1_H02E0601
|
|
arc: C5 H02W0601
|
|
arc: CE0 V02S0201
|
|
arc: CE1 V02S0201
|
|
arc: CE3 H00L0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D1 V01S0100
|
|
arc: D3 V00T0100
|
|
arc: D5 V00B0000
|
|
arc: E1_H02E0701 Q7
|
|
arc: F1 F1_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: H01W0000 F1
|
|
arc: M1 H00R0100
|
|
arc: M3 H00R0000
|
|
arc: M6 V00T0000
|
|
arc: M7 H00L0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 F5
|
|
arc: N1_V02N0301 F3
|
|
arc: V00B0000 Q6
|
|
arc: V00T0100 Q3
|
|
arc: V01S0100 Q1
|
|
word: SLICEC.K1.INIT 1000001001000001
|
|
word: SLICEA.K1.INIT 0011001111001100
|
|
word: SLICEB.K1.INIT 1000001001000001
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R27C42:PLC2
|
|
arc: E1_H02E0001 V02N0001
|
|
arc: E1_H02E0101 N1_V01S0100
|
|
arc: E1_H02E0601 N1_V02S0601
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: H00L0000 H02W0201
|
|
arc: H00L0100 V02S0301
|
|
arc: H00R0000 V02S0601
|
|
arc: N1_V02N0001 H06W0003
|
|
arc: N1_V02N0401 E1_H01W0000
|
|
arc: S3_V06S0003 H06W0003
|
|
arc: V00B0100 V02N0301
|
|
arc: W1_H02W0001 E1_H02W0501
|
|
arc: W1_H02W0101 E1_H02W0001
|
|
arc: W1_H02W0301 N1_V02S0301
|
|
arc: W1_H02W0401 E1_H02W0101
|
|
arc: W1_H02W0501 E1_H02W0501
|
|
arc: W1_H02W0601 E1_H02W0301
|
|
arc: W1_H02W0701 V02S0701
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
arc: W3_H06W0303 E1_H02W0501
|
|
arc: A0 H02W0701
|
|
arc: A3 H02E0701
|
|
arc: A5 V02S0101
|
|
arc: A6 N1_V01N0101
|
|
arc: B0 V02N0101
|
|
arc: B3 Q3
|
|
arc: B5 V02N0501
|
|
arc: B6 V02S0701
|
|
arc: C0 E1_H02W0601
|
|
arc: C3 V02N0601
|
|
arc: C5 E1_H02W0401
|
|
arc: C6 V02S0201
|
|
arc: CE0 H00R0000
|
|
arc: CE1 H00L0000
|
|
arc: CE2 H00L0000
|
|
arc: CE3 H00L0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 E1_H02W0201
|
|
arc: D3 V02N0201
|
|
arc: D5 E1_H01W0100
|
|
arc: D6 H00R0100
|
|
arc: E1_H01E0101 F0
|
|
arc: F0 F5A_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: H00R0100 Q7
|
|
arc: M0 V00B0100
|
|
arc: M1 H02E0001
|
|
arc: M2 V00B0000
|
|
arc: M3 H00L0100
|
|
arc: M4 H02W0401
|
|
arc: M7 H02E0201
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 F5
|
|
arc: N1_V01N0101 Q4
|
|
arc: N1_V02N0101 Q1
|
|
arc: N1_V02N0201 F2
|
|
arc: N1_V02N0301 Q1
|
|
arc: V00B0000 F6
|
|
word: SLICEA.K0.INIT 1110101010101010
|
|
word: SLICEA.K1.INIT 1111111111111111
|
|
word: SLICED.K0.INIT 1001000000001001
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 1000010000100001
|
|
word: SLICEC.K1.INIT 1000001001000001
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R27C43:PLC2
|
|
arc: E1_H02E0101 W1_H02E0101
|
|
arc: E1_H02E0601 W1_H02E0601
|
|
arc: E1_H02E0701 W1_H02E0601
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: E3_H06E0303 N1_V01S0100
|
|
arc: H00L0100 W1_H02E0301
|
|
arc: H00R0000 V02S0601
|
|
arc: H00R0100 V02S0501
|
|
arc: N1_V02N0101 H01E0101
|
|
arc: N1_V02N0401 S1_V02N0101
|
|
arc: N3_V06N0103 E3_H06W0103
|
|
arc: V00B0000 S1_V02N0201
|
|
arc: V00B0100 W1_H02E0501
|
|
arc: V00T0000 V02N0601
|
|
arc: W1_H02W0401 V02S0401
|
|
arc: W1_H02W0501 V02N0501
|
|
arc: W1_H02W0701 V02S0701
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
arc: W3_H06W0103 E1_H01W0100
|
|
arc: W3_H06W0203 E1_H01W0000
|
|
arc: A0 E1_H01E0001
|
|
arc: A1 V02N0701
|
|
arc: A2 V02N0701
|
|
arc: A5 Q5
|
|
arc: B0 E1_H02W0101
|
|
arc: B1 Q1
|
|
arc: B5 V02N0501
|
|
arc: C1 H02E0601
|
|
arc: C3 W1_H02E0601
|
|
arc: C5 V00T0100
|
|
arc: CE0 H00L0000
|
|
arc: CE1 H00L0000
|
|
arc: CE2 H00L0000
|
|
arc: CE3 H02E0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02S0201
|
|
arc: D1 V02S0001
|
|
arc: D2 V01S0100
|
|
arc: D3 V00B0100
|
|
arc: D5 H02E0001
|
|
arc: E1_H01E0001 F3
|
|
arc: E1_H01E0101 F0
|
|
arc: E1_H02E0001 F0
|
|
arc: E1_H02E0301 F3
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: H00L0000 F0
|
|
arc: H01W0000 Q6
|
|
arc: H01W0100 Q4
|
|
arc: M0 V00T0000
|
|
arc: M1 H00R0000
|
|
arc: M2 V00B0000
|
|
arc: M3 H00R0100
|
|
arc: M4 W1_H02E0401
|
|
arc: M5 H00L0100
|
|
arc: M6 V00B0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q2
|
|
arc: N1_V01N0101 Q6
|
|
arc: N1_V02N0001 F2
|
|
arc: N1_V02N0201 F0
|
|
arc: N1_V02N0301 F1
|
|
arc: N1_V02N0501 F5
|
|
arc: S3_V06S0003 F3
|
|
arc: V00T0100 Q3
|
|
arc: V01S0000 F3
|
|
arc: V01S0100 Q0
|
|
arc: W1_H02W0001 Q2
|
|
arc: W1_H02W0201 F0
|
|
word: SLICEB.K0.INIT 0101010110101010
|
|
word: SLICEA.K1.INIT 1000001001000001
|
|
word: SLICEC.K1.INIT 1001000000001001
|
|
word: SLICEA.K0.INIT 1000100000000000
|
|
word: SLICEB.K1.INIT 0000111100000000
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R27C44:PLC2
|
|
arc: E1_H02E0201 H01E0001
|
|
arc: E1_H02E0301 S1_V02N0301
|
|
arc: E1_H02E0401 V06S0203
|
|
arc: E1_H02E0601 W3_H06E0303
|
|
arc: E1_H02E0701 V06S0203
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
arc: H00L0000 H02E0001
|
|
arc: H00L0100 N1_V02S0301
|
|
arc: H00R0000 S1_V02N0401
|
|
arc: N1_V02N0001 E1_H01W0000
|
|
arc: N1_V02N0101 H01E0101
|
|
arc: N1_V02N0201 N3_V06S0103
|
|
arc: N1_V02N0301 H01E0101
|
|
arc: N1_V02N0401 E1_H01W0000
|
|
arc: N1_V02N0601 W3_H06E0303
|
|
arc: N1_V02N0701 H01E0101
|
|
arc: N3_V06N0203 W3_H06E0203
|
|
arc: N3_V06N0303 E3_H06W0303
|
|
arc: S1_V02S0301 N1_V02S0301
|
|
arc: S1_V02S0401 H01E0001
|
|
arc: S1_V02S0601 E1_H01W0000
|
|
arc: S1_V02S0701 H01E0101
|
|
arc: S3_V06S0003 W3_H06E0003
|
|
arc: V00T0100 H02W0101
|
|
arc: W1_H02W0201 E1_H01W0000
|
|
arc: W1_H02W0401 V01N0001
|
|
arc: W1_H02W0601 H01E0001
|
|
arc: W3_H06W0203 E1_H01W0000
|
|
arc: A1 H02W0501
|
|
arc: A2 H02W0701
|
|
arc: A3 V02S0501
|
|
arc: A5 V02S0301
|
|
arc: B1 H02E0101
|
|
arc: B2 V02N0101
|
|
arc: B3 V02S0101
|
|
arc: B5 H00R0000
|
|
arc: C1 S1_V02N0401
|
|
arc: C2 E1_H02W0601
|
|
arc: C3 E1_H02W0401
|
|
arc: C5 H02W0401
|
|
arc: CE0 H00L0000
|
|
arc: CE1 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H00R0000
|
|
arc: D1 E1_H02W0001
|
|
arc: D2 E1_H02W0201
|
|
arc: D3 H02W0001
|
|
arc: D5 V02S0401
|
|
arc: E1_H01E0001 F0
|
|
arc: E1_H02E0001 Q2
|
|
arc: E1_H02E0101 Q3
|
|
arc: E1_H02E0501 F5
|
|
arc: E3_H06E0003 F3
|
|
arc: E3_H06E0103 F2
|
|
arc: F0 F5A_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: H00R0100 F5
|
|
arc: H01W0000 F3
|
|
arc: H01W0100 F2
|
|
arc: M0 V00T0100
|
|
arc: M1 H00L0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: N3_V06N0003 Q3
|
|
arc: V01S0000 Q3
|
|
arc: V01S0100 Q2
|
|
arc: W1_H02W0001 F2
|
|
arc: W1_H02W0101 F3
|
|
arc: W1_H02W0301 Q1
|
|
arc: W1_H02W0501 F5
|
|
arc: W3_H06W0003 F3
|
|
arc: W3_H06W0103 F2
|
|
arc: W3_H06W0303 F5
|
|
word: SLICEA.K0.INIT 0000000011111111
|
|
word: SLICEA.K1.INIT 0000111100000111
|
|
word: SLICEC.K1.INIT 0000000100010001
|
|
word: SLICEB.K0.INIT 0010001010100010
|
|
word: SLICEB.K1.INIT 1011111100000000
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R27C45:PLC2
|
|
arc: E1_H02E0201 N1_V01S0000
|
|
arc: E1_H02E0401 S1_V02N0401
|
|
arc: E1_H02E0601 W1_H02E0301
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
arc: H00L0100 N1_V02S0101
|
|
arc: H00R0000 H02E0401
|
|
arc: H00R0100 H02E0701
|
|
arc: N1_V02N0001 H01E0001
|
|
arc: N1_V02N0201 S1_V02N0701
|
|
arc: S1_V02S0701 N3_V06S0203
|
|
arc: S3_V06S0303 N3_V06S0203
|
|
arc: V00B0000 W1_H02E0601
|
|
arc: V00B0100 N1_V02S0101
|
|
arc: V00T0000 V02N0401
|
|
arc: V00T0100 H02W0301
|
|
arc: W1_H02W0001 E1_H02W0501
|
|
arc: W1_H02W0401 E1_H02W0401
|
|
arc: W1_H02W0501 V02S0501
|
|
arc: W1_H02W0701 E1_H02W0701
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
arc: W3_H06W0203 E1_H01W0000
|
|
arc: A0 W1_H02E0701
|
|
arc: A1 W1_H02E0701
|
|
arc: A2 V00T0000
|
|
arc: A3 V02N0501
|
|
arc: A4 N1_V02S0101
|
|
arc: A5 V00T0000
|
|
arc: A6 S1_V02N0301
|
|
arc: A7 W1_H02E0701
|
|
arc: B0 N1_V02S0301
|
|
arc: B1 N1_V02S0301
|
|
arc: B2 N1_V02S0301
|
|
arc: B3 N1_V02S0101
|
|
arc: B4 V02N0701
|
|
arc: B5 V00B0100
|
|
arc: B6 V00T0000
|
|
arc: B7 V00T0000
|
|
arc: C0 V02N0401
|
|
arc: C1 V02N0401
|
|
arc: C2 W1_H02E0601
|
|
arc: C3 V02N0401
|
|
arc: C4 S1_V02N0001
|
|
arc: C5 S1_V02N0001
|
|
arc: C6 V00B0100
|
|
arc: C7 S1_V02N0001
|
|
arc: D0 S1_V02N0001
|
|
arc: D1 S1_V02N0001
|
|
arc: D2 S1_V02N0001
|
|
arc: D3 S1_V02N0001
|
|
arc: D4 V00B0000
|
|
arc: D5 V02N0601
|
|
arc: D6 V02N0601
|
|
arc: D7 H00L0100
|
|
arc: E1_H01E0001 F3
|
|
arc: E1_H02E0301 F3
|
|
arc: E3_H06E0003 F3
|
|
arc: F0 F5A_SLICE
|
|
arc: F1 FXA_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F3 FXB_SLICE
|
|
arc: F4 F5C_SLICE
|
|
arc: F5 FXC_SLICE
|
|
arc: F6 F5D_SLICE
|
|
arc: H01W0000 F3
|
|
arc: M0 V00T0100
|
|
arc: M1 H00R0100
|
|
arc: M2 V00T0100
|
|
arc: M3 E1_H02W0201
|
|
arc: M4 V00T0100
|
|
arc: M5 H00R0000
|
|
arc: M6 V00T0100
|
|
arc: N1_V02N0101 F3
|
|
arc: N1_V02N0301 F3
|
|
arc: N3_V06N0003 F3
|
|
arc: S1_V02S0301 F3
|
|
arc: S3_V06S0003 F3
|
|
arc: V01S0000 F3
|
|
arc: V01S0100 F3
|
|
arc: W1_H02W0101 F3
|
|
arc: W3_H06W0003 F3
|
|
word: SLICEA.K0.INIT 1000110000001100
|
|
word: SLICEA.K1.INIT 1100110001001100
|
|
word: SLICEB.K0.INIT 1000010000000100
|
|
word: SLICEB.K1.INIT 1100010001000100
|
|
word: SLICEC.K0.INIT 1010001000000000
|
|
word: SLICEC.K1.INIT 1100010010001000
|
|
word: SLICED.K0.INIT 1000000000000000
|
|
word: SLICED.K1.INIT 1100010000000000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R27C46:PLC2
|
|
arc: E1_H02E0001 W1_H02E0501
|
|
arc: E1_H02E0101 W1_H02E0001
|
|
arc: E1_H02E0201 H01E0001
|
|
arc: E1_H02E0401 W1_H02E0101
|
|
arc: E1_H02E0501 E3_H06W0303
|
|
arc: E1_H02E0601 W1_H02E0601
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: E3_H06E0303 W1_H02E0501
|
|
arc: H00L0000 H02E0201
|
|
arc: H00R0000 V02S0401
|
|
arc: H00R0100 V02N0501
|
|
arc: N1_V02N0001 E1_H01W0000
|
|
arc: N1_V02N0101 V01N0101
|
|
arc: N1_V02N0201 H01E0001
|
|
arc: N1_V02N0301 W1_H02E0301
|
|
arc: N1_V02N0401 E1_H01W0000
|
|
arc: N1_V02N0501 E1_H02W0501
|
|
arc: N1_V02N0701 H06E0203
|
|
arc: N3_V06N0203 W3_H06E0203
|
|
arc: S1_V02S0101 N1_V02S0001
|
|
arc: S1_V02S0201 W1_H02E0201
|
|
arc: S1_V02S0301 N3_V06S0003
|
|
arc: S1_V02S0401 H01E0001
|
|
arc: V00B0000 V02S0201
|
|
arc: V00B0100 V02N0301
|
|
arc: V00T0000 H02W0001
|
|
arc: V00T0100 N1_V02S0701
|
|
arc: W1_H02W0001 E1_H02W0501
|
|
arc: W1_H02W0201 N1_V01S0000
|
|
arc: W1_H02W0401 E1_H02W0401
|
|
arc: W1_H02W0601 E1_H02W0601
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
arc: A0 S1_V02N0701
|
|
arc: A3 F7
|
|
arc: A4 V02N0101
|
|
arc: A5 V00T0000
|
|
arc: A6 H00R0000
|
|
arc: A7 H00L0000
|
|
arc: B0 S1_V02N0301
|
|
arc: B1 S1_V02N0301
|
|
arc: B3 V02S0101
|
|
arc: B4 V02S0501
|
|
arc: B5 V02S0701
|
|
arc: B6 S1_V02N0501
|
|
arc: B7 V02N0701
|
|
arc: C0 S1_V02N0401
|
|
arc: C1 S1_V02N0401
|
|
arc: C3 F4
|
|
arc: C4 E1_H01E0101
|
|
arc: C5 S1_V02N0001
|
|
arc: C6 Q6
|
|
arc: C7 V00T0000
|
|
arc: CE3 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 E1_H02W0001
|
|
arc: D1 E1_H02W0001
|
|
arc: D3 V00T0100
|
|
arc: D4 V02S0601
|
|
arc: D5 E1_H01W0100
|
|
arc: D6 V02S0601
|
|
arc: D7 E1_H01W0100
|
|
arc: E1_H01E0001 F0
|
|
arc: E1_H01E0101 Q6
|
|
arc: E1_H02E0301 F3
|
|
arc: E3_H06E0003 F0
|
|
arc: F0 F5A_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 F0
|
|
arc: LSR0 V00B0000
|
|
arc: M0 H02W0601
|
|
arc: M6 V00B0100
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR3 LSR0
|
|
arc: N1_V02N0601 Q6
|
|
arc: S1_V02S0501 F5
|
|
arc: W1_H02W0301 F3
|
|
arc: W3_H06W0003 F0
|
|
arc: W3_H06W0303 F6
|
|
word: SLICEC.K1.INIT 0000000000100000
|
|
word: SLICED.K1.INIT 0100010001000000
|
|
word: SLICEC.K0.INIT 0001000100010000
|
|
word: SLICED.K0.INIT 0000010000000000
|
|
word: SLICEB.K1.INIT 0000000000000001
|
|
word: SLICEA.K0.INIT 0000000001110101
|
|
word: SLICEA.K1.INIT 0000000000110000
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET SET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
|
|
.tile R27C47:PLC2
|
|
arc: E1_H02E0001 H01E0001
|
|
arc: E1_H02E0301 V02N0301
|
|
arc: E1_H02E0401 V06S0203
|
|
arc: E1_H02E0601 V02N0601
|
|
arc: E1_H02E0701 S1_V02N0701
|
|
arc: E3_H06E0003 H01E0001
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
arc: H00R0000 W1_H02E0401
|
|
arc: N1_V02N0001 H06W0003
|
|
arc: N1_V02N0101 H02E0101
|
|
arc: N1_V02N0301 S1_V02N0201
|
|
arc: N1_V02N0401 H02E0401
|
|
arc: N1_V02N0601 H06E0303
|
|
arc: N1_V02N0701 S1_V02N0601
|
|
arc: S1_V02S0301 W1_H02E0301
|
|
arc: S1_V02S0501 H02W0501
|
|
arc: S1_V02S0601 H06E0303
|
|
arc: V00T0100 N1_V02S0701
|
|
arc: W1_H02W0201 E1_H02W0701
|
|
arc: W1_H02W0601 N1_V01S0000
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
arc: W3_H06W0303 E3_H06W0203
|
|
arc: A0 H02W0501
|
|
arc: A2 H02E0501
|
|
arc: A3 E1_H02W0701
|
|
arc: A4 F7
|
|
arc: A7 F5
|
|
arc: B0 V02N0101
|
|
arc: B1 Q1
|
|
arc: B3 H02E0301
|
|
arc: B5 S1_V02N0501
|
|
arc: B6 H02W0301
|
|
arc: C0 W1_H02E0601
|
|
arc: C3 V02N0601
|
|
arc: C4 E1_H02W0401
|
|
arc: C5 S1_V02N0001
|
|
arc: C6 H02E0601
|
|
arc: CE0 V02N0201
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H02E0201
|
|
arc: D1 V01S0100
|
|
arc: D2 V00T0100
|
|
arc: D3 V00T0100
|
|
arc: D4 E1_H01W0100
|
|
arc: D5 H02W0201
|
|
arc: D6 V02S0401
|
|
arc: D7 V02N0401
|
|
arc: E1_H01E0001 F1
|
|
arc: E3_H06E0203 F4
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 F1
|
|
arc: H01W0100 Q1
|
|
arc: LSR0 V00B0000
|
|
arc: M1 H00R0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: N1_V01N0001 F3
|
|
arc: N1_V02N0201 F2
|
|
arc: N3_V06N0103 F2
|
|
arc: V00B0000 F6
|
|
arc: V01S0100 Q0
|
|
arc: W1_H02W0001 Q0
|
|
arc: W1_H02W0401 F4
|
|
arc: W1_H02W0501 F7
|
|
arc: W1_H02W0701 F5
|
|
arc: W3_H06W0103 F2
|
|
word: SLICED.K0.INIT 1100000000000000
|
|
word: SLICEA.K0.INIT 0100000000000000
|
|
word: SLICEA.K1.INIT 0000000011001100
|
|
word: SLICEB.K1.INIT 0000001100000101
|
|
word: SLICEB.K0.INIT 1010101000000000
|
|
word: SLICEC.K1.INIT 0000000011110011
|
|
word: SLICED.K1.INIT 1010101000000000
|
|
word: SLICEC.K0.INIT 1010000000000000
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET SET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET SET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.B0MUX 1
|
|
|
|
.tile R27C48:PLC2
|
|
arc: E1_H02E0101 W1_H02E0001
|
|
arc: E1_H02E0601 V06S0303
|
|
arc: E1_H02E0701 V02N0701
|
|
arc: H00L0000 H02W0001
|
|
arc: H00R0000 N1_V02S0401
|
|
arc: H00R0100 H02W0501
|
|
arc: N1_V02N0001 H06E0003
|
|
arc: N1_V02N0101 H02W0101
|
|
arc: N1_V02N0201 H01E0001
|
|
arc: N1_V02N0301 H06E0003
|
|
arc: N1_V02N0401 S1_V02N0401
|
|
arc: N1_V02N0501 S1_V02N0401
|
|
arc: N1_V02N0601 E1_H02W0601
|
|
arc: N3_V06N0103 W3_H06E0103
|
|
arc: S1_V02S0001 H06E0003
|
|
arc: S1_V02S0501 V01N0101
|
|
arc: S1_V02S0601 E1_H02W0601
|
|
arc: S3_V06S0003 N3_V06S0303
|
|
arc: V00B0100 S1_V02N0301
|
|
arc: V00T0100 S1_V02N0701
|
|
arc: V01S0100 N3_V06S0303
|
|
arc: W1_H02W0001 V01N0001
|
|
arc: W1_H02W0201 V01N0001
|
|
arc: W1_H02W0301 N1_V01S0100
|
|
arc: W1_H02W0501 V06S0303
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
arc: A0 V02N0701
|
|
arc: A1 V02N0701
|
|
arc: A5 N1_V02S0301
|
|
arc: A7 F5
|
|
arc: B0 N1_V02S0301
|
|
arc: B1 Q1
|
|
arc: B4 N1_V01S0000
|
|
arc: B5 V02S0701
|
|
arc: B7 H02E0301
|
|
arc: C0 H00L0100
|
|
arc: C1 V02N0401
|
|
arc: C5 V02N0001
|
|
arc: C7 E1_H01E0101
|
|
arc: CE0 H00R0000
|
|
arc: CE1 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V00T0100
|
|
arc: D1 V00T0100
|
|
arc: D4 V02S0401
|
|
arc: D5 H00L0100
|
|
arc: D7 F0
|
|
arc: E1_H01E0101 Q3
|
|
arc: F0 F5A_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00L0100 Q1
|
|
arc: H01W0100 F4
|
|
arc: M0 V00T0000
|
|
arc: M1 H00R0100
|
|
arc: M2 V00B0100
|
|
arc: M3 H00L0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: N1_V02N0701 F7
|
|
arc: V00T0000 Q2
|
|
arc: W1_H02W0401 F4
|
|
arc: W1_H02W0601 F4
|
|
word: SLICEA.K0.INIT 0100010100000000
|
|
word: SLICEA.K1.INIT 1010001000000000
|
|
word: SLICEC.K1.INIT 1100001101000001
|
|
word: SLICED.K1.INIT 1000001000000000
|
|
word: SLICEC.K0.INIT 0000000000110011
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
|
|
.tile R27C49:PLC2
|
|
arc: E1_H02E0501 W1_H02E0401
|
|
arc: E1_H02E0601 V01N0001
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
arc: H00L0000 H02W0001
|
|
arc: N1_V02N0001 E1_H02W0001
|
|
arc: N1_V02N0201 E1_H01W0000
|
|
arc: N1_V02N0501 N1_V01S0100
|
|
arc: N1_V02N0701 E1_H01W0100
|
|
arc: S1_V02S0201 N1_V02S0701
|
|
arc: S1_V02S0301 N1_V02S0301
|
|
arc: S1_V02S0601 V01N0001
|
|
arc: S1_V02S0701 H02W0701
|
|
arc: V00B0000 V02N0001
|
|
arc: V00B0100 H02W0701
|
|
arc: V00T0000 E1_H02W0201
|
|
arc: V00T0100 H02W0301
|
|
arc: V01S0000 N3_V06S0103
|
|
arc: W1_H02W0001 N1_V02S0001
|
|
arc: W1_H02W0101 V02N0101
|
|
arc: W1_H02W0401 N1_V01S0000
|
|
arc: W1_H02W0501 W3_H06E0303
|
|
arc: W1_H02W0701 S1_V02N0701
|
|
arc: A0 H02W0501
|
|
arc: A1 H02W0501
|
|
arc: A2 V00T0000
|
|
arc: A3 V00T0000
|
|
arc: A4 W1_H02E0701
|
|
arc: A5 E1_H02W0701
|
|
arc: B0 H02W0101
|
|
arc: B1 H02W0101
|
|
arc: B2 H02W0101
|
|
arc: B3 H02W0101
|
|
arc: B4 V00B0100
|
|
arc: B5 E1_H02W0101
|
|
arc: C0 H00L0000
|
|
arc: C1 H00L0000
|
|
arc: C2 H00L0000
|
|
arc: C3 H00L0000
|
|
arc: C4 W1_H02E0601
|
|
arc: C5 V00T0100
|
|
arc: CE0 H02E0101
|
|
arc: CE1 H02E0101
|
|
arc: CLK1 G_HPBX0000
|
|
arc: D0 W1_H02E0001
|
|
arc: D1 W1_H02E0001
|
|
arc: D2 W1_H02E0001
|
|
arc: D3 W1_H02E0001
|
|
arc: D4 V01N0001
|
|
arc: D5 V00B0000
|
|
arc: E3_H06E0003 Q0
|
|
arc: E3_H06E0103 Q1
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: LSR1 E1_H02W0301
|
|
arc: MUXCLK0 CLK1
|
|
arc: MUXCLK1 CLK1
|
|
arc: W3_H06W0003 Q3
|
|
arc: W3_H06W0103 Q2
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK1.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK1.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK1.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK1.CLKMUX CLK
|
|
enum: SLICEA.MODE DPRAM
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.WREMUX WRE
|
|
enum: CLK1.CLKMUX CLK
|
|
enum: SLICEA.MODE DPRAM
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE DPRAM
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE DPRAM
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE RAMW
|
|
|
|
.tile R27C4:PLC2
|
|
arc: W1_H02W0701 E3_H06W0203
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
|
|
.tile R27C50:PLC2
|
|
arc: E1_H01E0001 W3_H06E0003
|
|
arc: E1_H02E0001 W3_H06E0003
|
|
arc: E1_H02E0101 W3_H06E0103
|
|
arc: E1_H02E0301 W3_H06E0003
|
|
arc: E1_H02E0601 W3_H06E0303
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
arc: H01W0100 W3_H06E0303
|
|
arc: N1_V02N0001 E1_H01W0000
|
|
arc: N1_V02N0101 S1_V02N0101
|
|
arc: N1_V02N0201 E1_H01W0000
|
|
arc: N1_V02N0501 W3_H06E0303
|
|
arc: N1_V02N0601 W3_H06E0303
|
|
arc: N1_V02N0701 W1_H02E0701
|
|
arc: S1_V02S0101 N3_V06S0103
|
|
arc: S1_V02S0301 N1_V02S0201
|
|
arc: S1_V02S0601 W3_H06E0303
|
|
arc: S3_V06S0203 N3_V06S0103
|
|
arc: V00B0000 H02E0601
|
|
arc: W1_H02W0001 W3_H06E0003
|
|
arc: W1_H02W0101 W3_H06E0103
|
|
arc: W1_H02W0301 S1_V02N0301
|
|
arc: W1_H02W0501 E1_H01W0100
|
|
arc: W1_H02W0601 E1_H01W0000
|
|
arc: W1_H02W0701 N1_V02S0701
|
|
arc: W3_H06W0003 E1_H01W0000
|
|
arc: W3_H06W0303 E3_H06W0203
|
|
arc: A0 H02E0501
|
|
arc: A5 V00B0000
|
|
arc: A6 E1_H01W0000
|
|
arc: B0 V02S0101
|
|
arc: B5 N1_V02S0701
|
|
arc: B6 N1_V01S0000
|
|
arc: C0 W1_H02E0601
|
|
arc: C5 V00T0000
|
|
arc: C6 V02N0001
|
|
arc: CE0 S1_V02N0201
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H02W0001
|
|
arc: D5 V02N0401
|
|
arc: D6 E1_H02W0201
|
|
arc: F0 F0_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: H01W0000 Q0
|
|
arc: LSR1 E1_H02W0301
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: N1_V01N0001 F5
|
|
arc: N1_V02N0401 F6
|
|
arc: S1_V02S0001 Q0
|
|
arc: V00T0000 Q0
|
|
word: SLICED.K0.INIT 0100000000000000
|
|
word: SLICEA.K0.INIT 0000100000000000
|
|
word: SLICEC.K1.INIT 0100010001000000
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET SET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R27C51:PLC2
|
|
arc: E1_H02E0101 E1_H01W0100
|
|
arc: E1_H02E0301 W3_H06E0003
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
arc: H00R0000 H02W0601
|
|
arc: N1_V02N0001 W3_H06E0003
|
|
arc: N1_V02N0101 N3_V06S0103
|
|
arc: N1_V02N0301 W3_H06E0003
|
|
arc: N1_V02N0401 H01E0001
|
|
arc: N1_V02N0501 N3_V06S0303
|
|
arc: N1_V02N0601 H01E0001
|
|
arc: N1_V02N0701 N3_V06S0203
|
|
arc: S1_V02S0001 W3_H06E0003
|
|
arc: S1_V02S0101 N3_V06S0103
|
|
arc: S1_V02S0501 N3_V06S0303
|
|
arc: S1_V02S0701 N3_V06S0203
|
|
arc: S3_V06S0003 W3_H06E0003
|
|
arc: S3_V06S0303 N3_V06S0303
|
|
arc: V00B0100 E1_H02W0501
|
|
arc: V01S0100 N3_V06S0303
|
|
arc: W1_H02W0001 W3_H06E0003
|
|
arc: W1_H02W0101 E1_H02W0101
|
|
arc: W1_H02W0301 W3_H06E0003
|
|
arc: W1_H02W0701 W3_H06E0203
|
|
arc: A2 V02N0701
|
|
arc: B1 V02S0101
|
|
arc: B2 N1_V02S0301
|
|
arc: C0 E1_H02W0401
|
|
arc: C1 E1_H02W0401
|
|
arc: C2 V02N0401
|
|
arc: CE0 H00R0000
|
|
arc: CE2 N1_V02S0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02S0201
|
|
arc: D1 V02S0001
|
|
arc: D2 N1_V01S0000
|
|
arc: E1_H01E0001 F0
|
|
arc: E1_H01E0101 F0
|
|
arc: E3_H06E0003 F0
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: H01W0000 Q0
|
|
arc: H01W0100 F0
|
|
arc: M4 V00B0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: N1_V01N0101 Q4
|
|
arc: N1_V02N0201 F2
|
|
arc: S3_V06S0103 F1
|
|
arc: V01S0000 Q0
|
|
arc: W1_H02W0201 F0
|
|
arc: W3_H06W0003 F0
|
|
word: SLICEB.K0.INIT 1111001101010001
|
|
word: SLICEA.K1.INIT 0000000000111111
|
|
word: SLICEA.K0.INIT 0000000011110000
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
|
|
.tile R27C52:PLC2
|
|
arc: E1_H02E0001 W3_H06E0003
|
|
arc: E1_H02E0101 W1_H02E0101
|
|
arc: E1_H02E0201 W3_H06E0103
|
|
arc: E1_H02E0301 E1_H01W0100
|
|
arc: E1_H02E0401 V02N0401
|
|
arc: E1_H02E0501 W3_H06E0303
|
|
arc: E1_H02E0601 W1_H02E0301
|
|
arc: E1_H02E0701 H01E0101
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
arc: H00L0000 W1_H02E0001
|
|
arc: H00L0100 W1_H02E0301
|
|
arc: H01W0100 W3_H06E0303
|
|
arc: N1_V02N0001 W3_H06E0003
|
|
arc: N1_V02N0101 W1_H02E0101
|
|
arc: N1_V02N0301 H02W0301
|
|
arc: N1_V02N0501 H01E0101
|
|
arc: N1_V02N0601 W3_H06E0303
|
|
arc: N1_V02N0701 H01E0101
|
|
arc: S1_V02S0601 W1_H02E0601
|
|
arc: S1_V02S0701 N3_V06S0203
|
|
arc: V00T0100 H02W0301
|
|
arc: W1_H02W0201 S1_V02N0201
|
|
arc: W1_H02W0301 V01N0101
|
|
arc: W1_H02W0601 W3_H06E0303
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
arc: W3_H06W0303 E1_H01W0100
|
|
arc: A0 H01E0001
|
|
arc: A1 H01E0001
|
|
arc: A2 H01E0001
|
|
arc: A3 H01E0001
|
|
arc: A4 V00T0100
|
|
arc: A5 V02N0301
|
|
arc: B0 W1_H02E0101
|
|
arc: B1 W1_H02E0101
|
|
arc: B2 W1_H02E0101
|
|
arc: B3 W1_H02E0101
|
|
arc: B4 N1_V02S0701
|
|
arc: B5 N1_V01S0000
|
|
arc: C0 H00L0000
|
|
arc: C1 H00L0000
|
|
arc: C2 H00L0100
|
|
arc: C3 H00L0000
|
|
arc: C4 H02W0601
|
|
arc: C5 E1_H02W0401
|
|
arc: CE0 H02E0101
|
|
arc: CE1 H02E0101
|
|
arc: CLK1 G_HPBX0000
|
|
arc: D0 H02W0001
|
|
arc: D1 H02W0001
|
|
arc: D2 H02W0001
|
|
arc: D3 H02W0001
|
|
arc: D4 V02N0401
|
|
arc: D5 V02N0601
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: LSR1 H02E0301
|
|
arc: MUXCLK0 CLK1
|
|
arc: MUXCLK1 CLK1
|
|
arc: N3_V06N0103 Q1
|
|
arc: S3_V06S0103 Q2
|
|
arc: V01S0100 Q3
|
|
arc: W3_H06W0003 Q0
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK1.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK1.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK1.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK1.CLKMUX CLK
|
|
enum: SLICEA.MODE DPRAM
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.WREMUX WRE
|
|
enum: CLK1.CLKMUX CLK
|
|
enum: SLICEA.MODE DPRAM
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE DPRAM
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE DPRAM
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE RAMW
|
|
|
|
.tile R27C53:PLC2
|
|
arc: E1_H02E0301 W1_H02E0301
|
|
arc: E1_H02E0501 N1_V01S0100
|
|
arc: E1_H02E0601 S1_V02N0601
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: H00L0100 N1_V02S0101
|
|
arc: H00R0100 H02E0501
|
|
arc: H01W0100 W3_H06E0303
|
|
arc: N1_V02N0201 S1_V02N0701
|
|
arc: N1_V02N0301 S3_V06N0003
|
|
arc: N1_V02N0601 W3_H06E0303
|
|
arc: N1_V02N0701 S3_V06N0203
|
|
arc: V00B0000 H02E0401
|
|
arc: V00B0100 N1_V02S0301
|
|
arc: V00T0000 S1_V02N0401
|
|
arc: V00T0100 H02E0301
|
|
arc: W1_H02W0001 W3_H06E0003
|
|
arc: W1_H02W0101 S1_V02N0101
|
|
arc: W1_H02W0301 S1_V02N0301
|
|
arc: W1_H02W0401 W3_H06E0203
|
|
arc: W1_H02W0501 E1_H02W0501
|
|
arc: W1_H02W0601 W3_H06E0303
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
arc: A0 H02E0701
|
|
arc: A1 H02E0701
|
|
arc: A2 H02E0701
|
|
arc: A3 H02E0701
|
|
arc: A4 S1_V02N0301
|
|
arc: A5 V00T0000
|
|
arc: B0 H02E0101
|
|
arc: B1 H02E0101
|
|
arc: B2 H02E0101
|
|
arc: B3 H02E0101
|
|
arc: B4 N1_V02S0701
|
|
arc: C0 H02E0601
|
|
arc: C1 H02E0601
|
|
arc: C2 H02E0601
|
|
arc: C3 H02E0601
|
|
arc: C4 V00T0100
|
|
arc: C5 V00B0100
|
|
arc: CE0 H00R0100
|
|
arc: CE1 H00R0100
|
|
arc: CLK1 G_HPBX0000
|
|
arc: D0 H02E0001
|
|
arc: D1 H02E0001
|
|
arc: D2 H02E0001
|
|
arc: D3 H02E0001
|
|
arc: D4 V00B0000
|
|
arc: D5 H00L0100
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: LSR1 W1_H02E0301
|
|
arc: MUXCLK0 CLK1
|
|
arc: MUXCLK1 CLK1
|
|
arc: N3_V06N0103 Q1
|
|
arc: W3_H06W0003 Q0
|
|
arc: W3_H06W0103 Q2
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
enum: SLICEA.MODE DPRAM
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.WREMUX WRE
|
|
enum: CLK1.CLKMUX CLK
|
|
enum: SLICEA.MODE DPRAM
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE DPRAM
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE DPRAM
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE RAMW
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK1.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK1.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK1.CLKMUX CLK
|
|
|
|
.tile R27C54:PLC2
|
|
arc: E3_H06E0103 W1_H02E0201
|
|
arc: H00R0100 W1_H02E0501
|
|
arc: V00B0000 W1_H02E0401
|
|
arc: V00T0100 W1_H02E0301
|
|
arc: W1_H02W0401 N1_V02S0401
|
|
arc: A0 W1_H02E0701
|
|
arc: A1 W1_H02E0701
|
|
arc: A2 W1_H02E0701
|
|
arc: A3 W1_H02E0701
|
|
arc: A4 V02N0301
|
|
arc: A5 H02E0501
|
|
arc: B0 E1_H02W0101
|
|
arc: B1 E1_H02W0101
|
|
arc: B2 E1_H02W0101
|
|
arc: B3 E1_H02W0101
|
|
arc: B4 N1_V02S0501
|
|
arc: B5 N1_V02S0701
|
|
arc: C0 W1_H02E0601
|
|
arc: C1 W1_H02E0601
|
|
arc: C2 W1_H02E0601
|
|
arc: C3 W1_H02E0601
|
|
arc: C4 V00T0100
|
|
arc: C5 H02E0601
|
|
arc: CE0 H00R0100
|
|
arc: CE1 H00R0100
|
|
arc: CLK1 G_HPBX0000
|
|
arc: D0 W1_H02E0001
|
|
arc: D1 W1_H02E0001
|
|
arc: D2 W1_H02E0001
|
|
arc: D3 W1_H02E0001
|
|
arc: D4 V00B0000
|
|
arc: D5 H02W0001
|
|
arc: E3_H06E0003 Q0
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: LSR1 H02E0301
|
|
arc: MUXCLK0 CLK1
|
|
arc: MUXCLK1 CLK1
|
|
arc: V01S0000 Q1
|
|
arc: V01S0100 Q2
|
|
arc: W3_H06W0003 Q3
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
enum: SLICEA.MODE DPRAM
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.WREMUX WRE
|
|
enum: CLK1.CLKMUX CLK
|
|
enum: SLICEA.MODE DPRAM
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE DPRAM
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE DPRAM
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE RAMW
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK1.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK1.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK1.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK1.CLKMUX CLK
|
|
|
|
.tile R27C55:PLC2
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
arc: W1_H02W0001 V02N0001
|
|
arc: W1_H02W0501 W3_H06E0303
|
|
|
|
.tile R27C56:PLC2
|
|
arc: E1_H02E0101 W3_H06E0103
|
|
arc: E1_H02E0201 W3_H06E0103
|
|
arc: E1_H02E0301 W3_H06E0003
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
arc: W1_H02W0101 W3_H06E0103
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
|
|
.tile R27C57:PLC2
|
|
arc: E1_H02E0001 W3_H06E0003
|
|
arc: E1_H02E0101 W3_H06E0103
|
|
arc: E1_H02E0301 W3_H06E0003
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
|
|
.tile R27C58:PLC2
|
|
arc: E1_H01E0001 W3_H06E0003
|
|
arc: E1_H02E0001 W3_H06E0003
|
|
arc: E1_H02E0101 W1_H02E0101
|
|
arc: E1_H02E0201 W3_H06E0103
|
|
arc: E1_H02E0301 W1_H02E0201
|
|
arc: E1_H02E0401 E3_H06W0203
|
|
arc: E1_H02E0501 W3_H06E0303
|
|
arc: E1_H02E0601 W1_H02E0301
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
|
|
.tile R27C59:PLC2
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: E3_H06E0203 H01E0001
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
arc: H00L0000 H02E0001
|
|
arc: H00L0100 W1_H02E0301
|
|
arc: H00R0100 H02E0501
|
|
arc: V00B0000 S1_V02N0201
|
|
arc: V00B0100 V02S0301
|
|
arc: V00T0000 W1_H02E0001
|
|
arc: V00T0100 W1_H02E0101
|
|
arc: A0 H00L0100
|
|
arc: A1 H00L0100
|
|
arc: A2 V00T0000
|
|
arc: A3 V00T0000
|
|
arc: A4 S1_V02N0301
|
|
arc: A5 V02N0101
|
|
arc: B0 H02E0301
|
|
arc: B1 H02E0301
|
|
arc: B2 H02E0101
|
|
arc: B3 H02E0101
|
|
arc: B4 H02W0101
|
|
arc: B5 V00B0100
|
|
arc: C0 H02E0601
|
|
arc: C1 H02E0601
|
|
arc: C2 H02E0601
|
|
arc: C3 H02E0601
|
|
arc: C4 H02E0401
|
|
arc: C5 S1_V02N0001
|
|
arc: CE0 H00L0000
|
|
arc: CE1 H00R0100
|
|
arc: CLK1 G_HPBX0000
|
|
arc: D0 H02E0201
|
|
arc: D1 H02E0201
|
|
arc: D2 H02E0201
|
|
arc: D3 H02E0201
|
|
arc: D4 V02N0401
|
|
arc: D5 V00B0000
|
|
arc: E3_H06E0003 Q3
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: LSR1 V00T0100
|
|
arc: MUXCLK0 CLK1
|
|
arc: MUXCLK1 CLK1
|
|
arc: N1_V01N0101 Q0
|
|
arc: S3_V06S0103 Q1
|
|
arc: W3_H06W0103 Q2
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
enum: SLICEA.MODE DPRAM
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.WREMUX WRE
|
|
enum: CLK1.CLKMUX CLK
|
|
enum: SLICEA.MODE DPRAM
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE DPRAM
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE DPRAM
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE RAMW
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK1.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK1.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK1.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK1.CLKMUX CLK
|
|
|
|
.tile R27C5:PLC2
|
|
arc: N3_V06N0103 E3_H06W0103
|
|
arc: N3_V06N0303 E3_H06W0303
|
|
arc: W3_H06W0203 E3_H06W0203
|
|
|
|
.tile R27C60:PLC2
|
|
arc: E1_H02E0101 W1_H02E0001
|
|
arc: E1_H02E0301 W1_H02E0301
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: W1_H02W0101 N1_V02S0101
|
|
|
|
.tile R27C61:PLC2
|
|
arc: E1_H02E0001 V02N0001
|
|
arc: E1_H02E0101 N1_V02S0101
|
|
arc: E1_H02E0601 W3_H06E0303
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
|
|
.tile R27C62:PLC2
|
|
arc: E1_H01E0001 W3_H06E0003
|
|
arc: E1_H01E0101 W3_H06E0203
|
|
arc: E1_H02E0001 W3_H06E0003
|
|
arc: E1_H02E0101 W3_H06E0103
|
|
arc: E1_H02E0201 W3_H06E0103
|
|
arc: E1_H02E0301 W3_H06E0003
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: H00L0000 H02W0201
|
|
arc: H00L0100 H02W0301
|
|
arc: V00B0100 H02W0701
|
|
arc: V00T0000 H02W0201
|
|
arc: A0 H00L0100
|
|
arc: A1 H00L0000
|
|
arc: A2 V00T0000
|
|
arc: A3 V00T0000
|
|
arc: A4 H02W0501
|
|
arc: A5 V02N0101
|
|
arc: B0 W1_H02E0301
|
|
arc: B1 H02W0101
|
|
arc: B2 H02W0101
|
|
arc: B3 W1_H02E0301
|
|
arc: B4 V02S0701
|
|
arc: B5 H02E0101
|
|
arc: C0 H02W0401
|
|
arc: C1 H02W0601
|
|
arc: C2 H02W0601
|
|
arc: C3 H02W0401
|
|
arc: C4 E1_H02W0401
|
|
arc: C5 S1_V02N0001
|
|
arc: CE0 W1_H02E0101
|
|
arc: CE1 W1_H02E0101
|
|
arc: CLK1 G_HPBX0000
|
|
arc: D0 E1_H02W0201
|
|
arc: D1 E1_H02W0201
|
|
arc: D2 E1_H02W0201
|
|
arc: D3 E1_H02W0201
|
|
arc: D4 H02E0001
|
|
arc: D5 N1_V02S0401
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: LSR1 V00B0100
|
|
arc: MUXCLK0 CLK1
|
|
arc: MUXCLK1 CLK1
|
|
arc: N3_V06N0103 Q2
|
|
arc: V01S0000 Q3
|
|
arc: V01S0100 Q0
|
|
arc: W3_H06W0103 Q1
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
enum: SLICEA.MODE DPRAM
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.WREMUX WRE
|
|
enum: CLK1.CLKMUX CLK
|
|
enum: SLICEA.MODE DPRAM
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE DPRAM
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE DPRAM
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE RAMW
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK1.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK1.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK1.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK1.CLKMUX CLK
|
|
|
|
.tile R27C63:PLC2
|
|
arc: E1_H01E0001 W3_H06E0003
|
|
arc: E1_H02E0001 E1_H01W0000
|
|
arc: E1_H02E0101 W3_H06E0103
|
|
arc: E1_H02E0201 E1_H01W0000
|
|
arc: E1_H02E0601 H01E0001
|
|
arc: E1_H02E0701 W3_H06E0203
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: E3_H06E0303 W1_H02E0601
|
|
arc: W1_H02W0101 H01E0101
|
|
arc: W1_H02W0201 W3_H06E0103
|
|
arc: W1_H02W0301 W3_H06E0003
|
|
arc: W1_H02W0401 H01E0001
|
|
arc: W1_H02W0501 E1_H02W0501
|
|
arc: W1_H02W0601 H01E0001
|
|
arc: W1_H02W0701 W3_H06E0203
|
|
|
|
.tile R27C64:PLC2
|
|
arc: E1_H01E0101 W3_H06E0203
|
|
arc: E1_H02E0001 W3_H06E0003
|
|
arc: E1_H02E0101 W1_H02E0101
|
|
arc: E1_H02E0301 W1_H02E0201
|
|
arc: E1_H02E0401 E1_H01W0000
|
|
arc: E1_H02E0501 S1_V02N0501
|
|
arc: E1_H02E0601 W1_H02E0301
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
arc: H00L0000 W1_H02E0001
|
|
arc: H00L0100 W1_H02E0301
|
|
arc: H00R0100 H02W0701
|
|
arc: H01W0000 W3_H06E0103
|
|
arc: V00B0100 H02E0701
|
|
arc: V00T0000 H02W0201
|
|
arc: W1_H02W0201 W3_H06E0103
|
|
arc: W1_H02W0401 E1_H01W0000
|
|
arc: W3_H06W0203 E1_H01W0000
|
|
arc: A0 H01E0001
|
|
arc: A1 H01E0001
|
|
arc: A2 H01E0001
|
|
arc: A3 H01E0001
|
|
arc: A4 H02W0501
|
|
arc: A5 S1_V02N0301
|
|
arc: B0 W1_H02E0101
|
|
arc: B1 W1_H02E0101
|
|
arc: B2 W1_H02E0101
|
|
arc: B3 W1_H02E0101
|
|
arc: B4 N1_V02S0701
|
|
arc: B5 S1_V02N0701
|
|
arc: C0 H00L0000
|
|
arc: C1 H00L0000
|
|
arc: C2 H00L0000
|
|
arc: C3 H00L0100
|
|
arc: C4 V00T0000
|
|
arc: C5 V02N0001
|
|
arc: CE0 H00R0100
|
|
arc: CE1 H00R0100
|
|
arc: CLK1 G_HPBX0000
|
|
arc: D0 H02E0001
|
|
arc: D1 H02E0201
|
|
arc: D2 H02E0001
|
|
arc: D3 H02E0201
|
|
arc: D4 V02N0401
|
|
arc: D5 H02W0001
|
|
arc: E3_H06E0003 Q3
|
|
arc: E3_H06E0103 Q1
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: LSR1 V00B0100
|
|
arc: MUXCLK0 CLK1
|
|
arc: MUXCLK1 CLK1
|
|
arc: V01S0000 Q0
|
|
arc: W3_H06W0103 Q2
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK1.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK1.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK1.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK1.CLKMUX CLK
|
|
enum: SLICEA.MODE DPRAM
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.WREMUX WRE
|
|
enum: CLK1.CLKMUX CLK
|
|
enum: SLICEA.MODE DPRAM
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE DPRAM
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE DPRAM
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE RAMW
|
|
|
|
.tile R27C65:PLC2
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
arc: H00L0000 H02E0001
|
|
arc: H00L0100 W1_H02E0101
|
|
arc: H01W0000 W3_H06E0103
|
|
arc: V00B0100 W1_H02E0701
|
|
arc: V00T0100 S1_V02N0501
|
|
arc: W1_H02W0001 S1_V02N0001
|
|
arc: W1_H02W0201 W3_H06E0103
|
|
arc: W1_H02W0501 S1_V02N0501
|
|
arc: W1_H02W0701 W3_H06E0203
|
|
arc: A0 H00L0100
|
|
arc: A1 H00L0100
|
|
arc: A2 H00L0100
|
|
arc: A3 H00L0100
|
|
arc: A4 V00T0100
|
|
arc: A5 H02E0501
|
|
arc: B0 H02E0301
|
|
arc: B1 H02E0101
|
|
arc: B2 H02E0301
|
|
arc: B3 H02E0301
|
|
arc: B4 N1_V02S0701
|
|
arc: B5 E1_H02W0101
|
|
arc: C0 H02E0601
|
|
arc: C1 H02E0601
|
|
arc: C2 H02E0601
|
|
arc: C3 W1_H02E0601
|
|
arc: C4 H02E0401
|
|
arc: C5 V02S0201
|
|
arc: CE0 H00L0000
|
|
arc: CE1 H00L0000
|
|
arc: CLK1 G_HPBX0000
|
|
arc: D0 H01E0101
|
|
arc: D1 H01E0101
|
|
arc: D2 H01E0101
|
|
arc: D3 H01E0101
|
|
arc: D4 V02N0401
|
|
arc: D5 V02S0601
|
|
arc: E3_H06E0003 Q0
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: LSR1 V00B0100
|
|
arc: MUXCLK0 CLK1
|
|
arc: MUXCLK1 CLK1
|
|
arc: N3_V06N0003 Q3
|
|
arc: V01S0000 Q2
|
|
arc: V01S0100 Q1
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
enum: SLICEA.MODE DPRAM
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.WREMUX WRE
|
|
enum: CLK1.CLKMUX CLK
|
|
enum: SLICEA.MODE DPRAM
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE DPRAM
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE DPRAM
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE RAMW
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK1.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK1.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK1.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK1.CLKMUX CLK
|
|
|
|
.tile R27C66:PLC2
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
|
|
.tile R27C67:PLC2
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
arc: W1_H02W0101 V02N0101
|
|
|
|
.tile R27C68:PLC2
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
|
|
.tile R27C69:PLC2
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: N3_V06N0103 H06E0103
|
|
|
|
.tile R27C6:PLC2
|
|
arc: N3_V06N0203 E3_H06W0203
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
|
|
.tile R27C70:PLC2
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
|
|
.tile R27C71:PLC2
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
|
|
.tile R27C72:PLC2
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
|
|
.tile R27C73:PLC2
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: N3_V06N0003 W3_H06E0003
|
|
|
|
.tile R27C74:PLC2
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
|
|
.tile R27C75:PLC2
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: N3_V06N0103 W3_H06E0103
|
|
|
|
.tile R27C76:PLC2
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
|
|
.tile R27C77:PLC2
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
|
|
.tile R27C78:PLC2
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
|
|
.tile R27C79:PLC2
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
|
|
.tile R27C7:PLC2
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
arc: W3_H06W0303 E3_H06W0203
|
|
|
|
.tile R27C80:PLC2
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
arc: N3_V06N0303 H06E0303
|
|
|
|
.tile R27C81:PLC2
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
|
|
.tile R27C82:PLC2
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
|
|
.tile R27C83:PLC2
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
|
|
.tile R27C84:PLC2
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
|
|
.tile R27C85:PLC2
|
|
arc: E1_H01E0001 W3_H06E0003
|
|
|
|
.tile R27C86:PLC2
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: E3_H06E0203 H01E0001
|
|
|
|
.tile R27C87:PLC2
|
|
arc: N1_V02N0701 W3_H06E0203
|
|
arc: S1_V02S0501 H06E0303
|
|
|
|
.tile R27C88:PLC2
|
|
arc: N3_V06N0003 W3_H06E0003
|
|
arc: S3_V06S0203 W3_H06E0203
|
|
arc: S3_V06S0303 W3_H06E0303
|
|
|
|
.tile R27C9:PLC2
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
arc: W3_H06W0303 E1_H01W0100
|
|
|
|
.tile R28C10:PLC2
|
|
arc: W3_H06W0203 E3_H06W0203
|
|
|
|
.tile R28C11:PLC2
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
|
|
.tile R28C13:PLC2
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
|
|
.tile R28C14:PLC2
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
|
|
.tile R28C16:PLC2
|
|
arc: E1_H02E0401 S3_V06N0203
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
|
|
.tile R28C17:PLC2
|
|
arc: N1_V01N0101 N3_V06S0203
|
|
arc: N1_V02N0001 S3_V06N0003
|
|
arc: N1_V02N0401 H02E0401
|
|
arc: W3_H06W0003 N1_V01S0000
|
|
|
|
.tile R28C19:PLC2
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
arc: W3_H06W0303 E3_H06W0203
|
|
|
|
.tile R28C20:PLC2
|
|
arc: S3_V06S0003 E3_H06W0003
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
|
|
.tile R28C22:PLC2
|
|
arc: E1_H02E0401 S3_V06N0203
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
|
|
.tile R28C23:PLC2
|
|
arc: N1_V02N0001 S3_V06N0003
|
|
arc: N1_V02N0401 H02E0401
|
|
arc: N1_V02N0601 E1_H02W0601
|
|
|
|
.tile R28C24:PLC2
|
|
arc: E1_H02E0701 S3_V06N0203
|
|
|
|
.tile R28C25:PLC2
|
|
arc: E1_H02E0001 W3_H06E0003
|
|
arc: E1_H02E0601 S3_V06N0303
|
|
arc: N1_V02N0401 S1_V02N0101
|
|
arc: N1_V02N0601 S3_V06N0303
|
|
arc: N1_V02N0701 H02E0701
|
|
arc: W1_H02W0601 S3_V06N0303
|
|
arc: W3_H06W0103 N1_V01S0100
|
|
arc: W3_H06W0203 N1_V01S0000
|
|
|
|
.tile R28C26:PLC2
|
|
arc: N1_V01N0001 S3_V06N0003
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
arc: W3_H06W0303 E3_H06W0203
|
|
|
|
.tile R28C27:PLC2
|
|
arc: N1_V02N0001 W1_H02E0001
|
|
arc: N1_V02N0601 W1_H02E0601
|
|
|
|
.tile R28C28:PLC2
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
|
|
.tile R28C2:PLC2
|
|
arc: S3_V06S0103 H06W0103
|
|
arc: S3_V06S0203 E3_H06W0203
|
|
|
|
.tile R28C30:PLC2
|
|
arc: E1_H02E0101 S3_V06N0103
|
|
|
|
.tile R28C31:PLC2
|
|
arc: E1_H02E0401 S3_V06N0203
|
|
arc: N1_V02N0401 S3_V06N0203
|
|
|
|
.tile R28C32:PLC2
|
|
arc: N1_V02N0001 S3_V06N0003
|
|
arc: N1_V02N0101 W1_H02E0101
|
|
arc: N1_V02N0301 H06W0003
|
|
arc: N1_V02N0401 H02E0401
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
arc: W3_H06W0203 N1_V01S0000
|
|
|
|
.tile R28C34:PLC2
|
|
arc: E1_H02E0301 S1_V02N0301
|
|
arc: E1_H02E0401 S3_V06N0203
|
|
arc: N1_V01N0001 S3_V06N0003
|
|
arc: N1_V02N0101 H02W0101
|
|
arc: N1_V02N0401 S3_V06N0203
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
|
|
.tile R28C35:PLC2
|
|
arc: E1_H02E0101 V06N0103
|
|
arc: E3_H06E0303 S3_V06N0303
|
|
arc: N1_V02N0301 H02E0301
|
|
arc: N1_V02N0401 H02E0401
|
|
arc: N1_V02N0501 S3_V06N0303
|
|
arc: N1_V02N0601 S3_V06N0303
|
|
arc: W1_H02W0101 V06N0103
|
|
arc: W3_H06W0003 S3_V06N0003
|
|
|
|
.tile R28C36:PLC2
|
|
arc: N1_V02N0101 H02E0101
|
|
arc: N1_V02N0401 W1_H02E0401
|
|
arc: N1_V02N0501 S3_V06N0303
|
|
|
|
.tile R28C37:PLC2
|
|
arc: E1_H02E0001 V02N0001
|
|
arc: E1_H02E0201 V06S0103
|
|
arc: E1_H02E0401 S3_V06N0203
|
|
arc: E1_H02E0501 N3_V06S0303
|
|
arc: N1_V01N0001 S3_V06N0003
|
|
arc: N1_V02N0101 H02W0101
|
|
arc: N1_V02N0401 S3_V06N0203
|
|
|
|
.tile R28C38:PLC2
|
|
arc: E1_H02E0201 S1_V02N0201
|
|
arc: N1_V02N0001 S3_V06N0003
|
|
arc: N1_V02N0201 H02W0201
|
|
arc: N1_V02N0401 H02E0401
|
|
arc: N1_V02N0501 H02E0501
|
|
arc: N1_V02N0601 S1_V02N0601
|
|
arc: W1_H02W0101 V02N0101
|
|
arc: W3_H06W0003 N1_V01S0000
|
|
|
|
.tile R28C39:PLC2
|
|
arc: E1_H02E0101 E3_H06W0103
|
|
arc: E1_H02E0501 E1_H01W0100
|
|
arc: E1_H02E0601 V06S0303
|
|
arc: E1_H02E0701 S3_V06N0203
|
|
arc: H00L0000 W1_H02E0001
|
|
arc: H00L0100 H02W0101
|
|
arc: H00R0000 V02N0401
|
|
arc: H00R0100 E1_H02W0701
|
|
arc: N1_V02N0101 E1_H02W0101
|
|
arc: N1_V02N0301 H06W0003
|
|
arc: N1_V02N0401 S3_V06N0203
|
|
arc: N1_V02N0501 S3_V06N0303
|
|
arc: N1_V02N0601 S3_V06N0303
|
|
arc: N1_V02N0701 S3_V06N0203
|
|
arc: N3_V06N0003 S3_V06N0303
|
|
arc: N3_V06N0303 S3_V06N0203
|
|
arc: S1_V02S0201 W1_H02E0201
|
|
arc: V00T0000 V02N0601
|
|
arc: V01S0100 S3_V06N0303
|
|
arc: W1_H02W0201 V06S0103
|
|
arc: A0 V02N0701
|
|
arc: A1 V02N0701
|
|
arc: A3 V00T0000
|
|
arc: A4 V00T0000
|
|
arc: B0 S1_V02N0101
|
|
arc: B1 S1_V02N0101
|
|
arc: B3 Q3
|
|
arc: B4 E1_H02W0101
|
|
arc: C0 H00L0100
|
|
arc: C1 H00L0100
|
|
arc: C3 E1_H01W0000
|
|
arc: C4 V00B0100
|
|
arc: CE1 H00R0100
|
|
arc: CE2 S1_V02N0601
|
|
arc: CE3 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 S1_V02N0201
|
|
arc: D1 S1_V02N0201
|
|
arc: D3 H02W0201
|
|
arc: D4 V01N0001
|
|
arc: E1_H01E0001 F4
|
|
arc: E1_H01E0101 Q7
|
|
arc: E1_H02E0301 F3
|
|
arc: E3_H06E0003 F0
|
|
arc: F0 F5A_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: M0 H02W0601
|
|
arc: M3 H00R0000
|
|
arc: M5 W1_H02E0001
|
|
arc: M7 H00L0000
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: V00B0100 Q5
|
|
word: SLICEB.K1.INIT 1001000000001001
|
|
word: SLICEC.K0.INIT 1000010000100001
|
|
word: SLICEA.K0.INIT 0111111110001111
|
|
word: SLICEA.K1.INIT 0000011100001000
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R28C40:PLC2
|
|
arc: E1_H02E0401 S3_V06N0203
|
|
arc: E1_H02E0501 E1_H01W0100
|
|
arc: E3_H06E0203 N1_V01S0000
|
|
arc: H00L0000 V02S0001
|
|
arc: H00R0000 S1_V02N0601
|
|
arc: N1_V01N0001 S3_V06N0003
|
|
arc: N1_V02N0001 S3_V06N0003
|
|
arc: N1_V02N0401 S1_V02N0101
|
|
arc: N1_V02N0601 S3_V06N0303
|
|
arc: N1_V02N0701 H02E0701
|
|
arc: S1_V02S0001 H06W0003
|
|
arc: S1_V02S0101 H02W0101
|
|
arc: S1_V02S0201 H06W0103
|
|
arc: S1_V02S0601 H02W0601
|
|
arc: V00T0000 V02S0401
|
|
arc: V00T0100 H02E0301
|
|
arc: V01S0000 S3_V06N0103
|
|
arc: W1_H02W0101 V01N0101
|
|
arc: W1_H02W0201 V06S0103
|
|
arc: W1_H02W0601 V01N0001
|
|
arc: W3_H06W0103 N1_V01S0100
|
|
arc: A1 H02E0701
|
|
arc: A2 H02E0701
|
|
arc: A3 H02E0501
|
|
arc: A4 N1_V01N0101
|
|
arc: A7 H02E0701
|
|
arc: B1 V02S0301
|
|
arc: B2 H02W0301
|
|
arc: B3 H02W0101
|
|
arc: B4 E1_H02W0301
|
|
arc: B5 E1_H02W0301
|
|
arc: B7 H02W0101
|
|
arc: C1 H00L0100
|
|
arc: C2 H02E0601
|
|
arc: C3 E1_H01W0000
|
|
arc: C4 E1_H02W0401
|
|
arc: C7 S1_V02N0201
|
|
arc: CE0 E1_H02W0101
|
|
arc: CE1 V02N0201
|
|
arc: CE2 E1_H02W0101
|
|
arc: CE3 E1_H02W0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D1 V01S0100
|
|
arc: D2 H01E0101
|
|
arc: D3 V02S0201
|
|
arc: D4 F2
|
|
arc: D5 E1_H02W0001
|
|
arc: D7 H00R0100
|
|
arc: E1_H01E0001 F6
|
|
arc: E1_H01E0101 F6
|
|
arc: E1_H02E0601 F4
|
|
arc: E3_H06E0003 F0
|
|
arc: F0 F5A_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F5C_SLICE
|
|
arc: F6 F5D_SLICE
|
|
arc: H00L0100 Q3
|
|
arc: H00R0100 Q5
|
|
arc: H01W0000 Q7
|
|
arc: H01W0100 Q1
|
|
arc: M0 H01E0001
|
|
arc: M1 H02W0001
|
|
arc: M2 V00T0000
|
|
arc: M3 H00L0000
|
|
arc: M4 E1_H01E0101
|
|
arc: M5 H00R0000
|
|
arc: M6 V00T0100
|
|
arc: M7 W1_H02E0201
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0101 F3
|
|
arc: V01S0100 Q2
|
|
word: SLICEC.K0.INIT 1010100000000000
|
|
word: SLICEC.K1.INIT 1111111111001100
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 1000001001000001
|
|
word: SLICEB.K0.INIT 1001000000001001
|
|
word: SLICEB.K1.INIT 1001000000001001
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 1000010000100001
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R28C41:PLC2
|
|
arc: E1_H02E0001 N3_V06S0003
|
|
arc: E1_H02E0201 S3_V06N0103
|
|
arc: E1_H02E0601 V06N0303
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
arc: H00L0100 N1_V02S0301
|
|
arc: H00R0000 V02N0401
|
|
arc: N1_V01N0001 N3_V06S0003
|
|
arc: N1_V01N0101 S3_V06N0203
|
|
arc: N1_V02N0001 V01N0001
|
|
arc: N1_V02N0101 S3_V06N0103
|
|
arc: N1_V02N0201 S1_V02N0201
|
|
arc: N1_V02N0401 H02E0401
|
|
arc: N1_V02N0601 V01N0001
|
|
arc: N1_V02N0701 S3_V06N0203
|
|
arc: N3_V06N0103 S3_V06N0103
|
|
arc: N3_V06N0203 S3_V06N0103
|
|
arc: N3_V06N0303 S3_V06N0203
|
|
arc: V00B0000 V02S0001
|
|
arc: V00B0100 V02S0101
|
|
arc: V00T0000 S1_V02N0401
|
|
arc: W1_H02W0001 V06S0003
|
|
arc: W1_H02W0101 S3_V06N0103
|
|
arc: W1_H02W0601 E1_H02W0601
|
|
arc: A3 S1_V02N0701
|
|
arc: B3 E1_H01W0100
|
|
arc: B7 W1_H02E0101
|
|
arc: C3 H02W0601
|
|
arc: C4 H01E0001
|
|
arc: C7 E1_H02W0601
|
|
arc: CE0 H00R0100
|
|
arc: CE2 H00R0100
|
|
arc: CE3 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D3 V02N0001
|
|
arc: D4 F2
|
|
arc: D7 V02S0401
|
|
arc: E1_H01E0101 F7
|
|
arc: F2 F5B_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00R0100 F7
|
|
arc: H01W0000 Q0
|
|
arc: H01W0100 F4
|
|
arc: M0 V00B0000
|
|
arc: M1 H00L0100
|
|
arc: M2 V00T0000
|
|
arc: M4 V00B0100
|
|
arc: M7 H00R0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: S1_V02S0501 Q7
|
|
arc: S1_V02S0601 Q4
|
|
arc: S1_V02S0701 F7
|
|
arc: S3_V06S0203 F7
|
|
arc: V01S0000 F4
|
|
arc: V01S0100 F7
|
|
arc: W1_H02W0301 Q1
|
|
arc: W1_H02W0701 F7
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000010000100
|
|
word: SLICEC.K0.INIT 0000000000001111
|
|
word: SLICED.K1.INIT 1100000000000000
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R28C42:PLC2
|
|
arc: E1_H02E0201 V06S0103
|
|
arc: E1_H02E0401 V06S0203
|
|
arc: E1_H02E0501 S3_V06N0303
|
|
arc: H00L0000 H02E0001
|
|
arc: H00R0000 H02W0401
|
|
arc: H00R0100 W1_H02E0501
|
|
arc: N1_V02N0001 H06W0003
|
|
arc: N1_V02N0101 H06W0103
|
|
arc: N1_V02N0201 H02E0201
|
|
arc: N1_V02N0501 S3_V06N0303
|
|
arc: N1_V02N0601 S3_V06N0303
|
|
arc: N3_V06N0303 S1_V02N0501
|
|
arc: S1_V02S0401 N1_V02S0401
|
|
arc: S1_V02S0501 N1_V02S0401
|
|
arc: S1_V02S0601 W1_H02E0601
|
|
arc: S1_V02S0701 E1_H01W0100
|
|
arc: V00B0000 E1_H02W0401
|
|
arc: V00B0100 V02N0101
|
|
arc: V00T0000 N1_V02S0401
|
|
arc: W1_H02W0001 E1_H01W0000
|
|
arc: W1_H02W0101 H01E0101
|
|
arc: W1_H02W0401 E1_H01W0000
|
|
arc: W1_H02W0601 S3_V06N0303
|
|
arc: W3_H06W0003 E1_H02W0301
|
|
arc: A2 V00T0000
|
|
arc: A4 E1_H01W0000
|
|
arc: A5 E1_H01W0000
|
|
arc: B0 V00T0000
|
|
arc: B2 E1_H02W0101
|
|
arc: B4 V02N0501
|
|
arc: B5 V02N0701
|
|
arc: C0 F4
|
|
arc: C1 N1_V02S0401
|
|
arc: C2 F4
|
|
arc: C3 N1_V02S0401
|
|
arc: C4 V01N0101
|
|
arc: C5 V01N0101
|
|
arc: CE1 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02N0001
|
|
arc: D1 V01S0100
|
|
arc: D2 V02N0201
|
|
arc: D3 V01S0100
|
|
arc: D4 V02N0401
|
|
arc: D5 V02N0601
|
|
arc: F0 F5A_SLICE
|
|
arc: F1 FXA_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F4 F5C_SLICE
|
|
arc: H01W0100 Q3
|
|
arc: LSR0 V00B0000
|
|
arc: M0 W1_H02E0601
|
|
arc: M1 H00R0100
|
|
arc: M2 W1_H02E0601
|
|
arc: M3 H00L0000
|
|
arc: M4 V00B0100
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXLSR1 LSR0
|
|
arc: N1_V02N0301 F1
|
|
arc: V01S0000 Q3
|
|
arc: V01S0100 F4
|
|
arc: W1_H02W0301 Q3
|
|
word: SLICEA.K0.INIT 1100000000000000
|
|
word: SLICEA.K1.INIT 1111000000000000
|
|
word: SLICEB.K0.INIT 1010000010000000
|
|
word: SLICEB.K1.INIT 1111000000000000
|
|
word: SLICEC.K0.INIT 0111110111110101
|
|
word: SLICEC.K1.INIT 0001010001010000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R28C43:PLC2
|
|
arc: E1_H02E0001 N1_V01S0000
|
|
arc: E1_H02E0101 S1_V02N0101
|
|
arc: E1_H02E0201 V06S0103
|
|
arc: E1_H02E0601 N1_V01S0000
|
|
arc: E3_H06E0203 N1_V01S0000
|
|
arc: H00R0100 V02N0701
|
|
arc: N1_V01N0001 S3_V06N0003
|
|
arc: N1_V02N0501 H02E0501
|
|
arc: N1_V02N0601 W1_H02E0601
|
|
arc: N1_V02N0701 H02W0701
|
|
arc: S1_V02S0001 H06E0003
|
|
arc: S1_V02S0201 H02E0201
|
|
arc: S1_V02S0301 S3_V06N0003
|
|
arc: S1_V02S0401 H02E0401
|
|
arc: V00B0000 H02W0401
|
|
arc: V00B0100 S1_V02N0101
|
|
arc: V00T0100 E1_H02W0301
|
|
arc: W1_H02W0601 N1_V01S0000
|
|
arc: W3_H06W0003 N1_V01S0000
|
|
arc: A4 V00T0100
|
|
arc: B4 N1_V01S0000
|
|
arc: C1 N1_V01N0001
|
|
arc: C4 V00B0100
|
|
arc: CE2 H00R0000
|
|
arc: CE3 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D1 H02E0201
|
|
arc: D4 E1_H02W0201
|
|
arc: E1_H01E0001 F1
|
|
arc: E1_H01E0101 Q6
|
|
arc: E3_H06E0103 F1
|
|
arc: F1 F1_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: H00R0000 F4
|
|
arc: H01W0000 Q5
|
|
arc: H01W0100 Q5
|
|
arc: LSR0 V00B0000
|
|
arc: LSR1 V00B0100
|
|
arc: M5 H00R0100
|
|
arc: M6 H02E0401
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR0
|
|
arc: N3_V06N0103 F1
|
|
arc: V01S0000 Q6
|
|
arc: W1_H02W0401 F4
|
|
arc: W3_H06W0103 F1
|
|
word: SLICEC.K0.INIT 1111100011110000
|
|
word: SLICEA.K1.INIT 0000000011110000
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
|
|
.tile R28C44:PLC2
|
|
arc: E1_H02E0001 V06S0003
|
|
arc: E1_H02E0301 V02N0301
|
|
arc: E1_H02E0401 V02N0401
|
|
arc: E1_H02E0601 E1_H01W0000
|
|
arc: E3_H06E0003 N1_V01S0000
|
|
arc: E3_H06E0203 N1_V01S0000
|
|
arc: E3_H06E0303 N1_V01S0100
|
|
arc: H00L0100 V02S0301
|
|
arc: H00R0000 V02S0601
|
|
arc: H00R0100 V02S0701
|
|
arc: N1_V02N0101 H06W0103
|
|
arc: N1_V02N0501 H06W0303
|
|
arc: N1_V02N0601 H02E0601
|
|
arc: S1_V02S0001 H01E0001
|
|
arc: S1_V02S0201 N3_V06S0103
|
|
arc: S1_V02S0301 N3_V06S0003
|
|
arc: S1_V02S0401 H06W0203
|
|
arc: S1_V02S0601 H06W0303
|
|
arc: V00B0000 V02N0001
|
|
arc: W1_H02W0101 H01E0101
|
|
arc: W1_H02W0301 V02N0301
|
|
arc: W1_H02W0401 V02N0401
|
|
arc: W1_H02W0701 S3_V06N0203
|
|
arc: A0 H01E0001
|
|
arc: A1 H01E0001
|
|
arc: A5 Q5
|
|
arc: B1 H02E0101
|
|
arc: B5 V02N0501
|
|
arc: C0 V02N0401
|
|
arc: C1 V02S0401
|
|
arc: C2 V02N0401
|
|
arc: C3 V02N0401
|
|
arc: C5 H02W0601
|
|
arc: CE1 H00R0100
|
|
arc: CE2 V02N0601
|
|
arc: CE3 V02N0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H02E0001
|
|
arc: D1 S1_V02N0201
|
|
arc: D3 S1_V02N0201
|
|
arc: D5 H01W0000
|
|
arc: E1_H02E0701 F5
|
|
arc: E3_H06E0103 F1
|
|
arc: F0 F5A_SLICE
|
|
arc: F1 FXA_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: H01W0000 Q7
|
|
arc: M0 V00B0000
|
|
arc: M1 H00R0000
|
|
arc: M2 V00B0000
|
|
arc: M3 H02E0201
|
|
arc: M5 H00L0100
|
|
arc: M7 H02E0201
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q3
|
|
word: SLICEA.K0.INIT 1111101011110000
|
|
word: SLICEA.K1.INIT 1111111111101100
|
|
word: SLICEB.K0.INIT 1111000011110000
|
|
word: SLICEB.K1.INIT 1111111111110000
|
|
word: SLICEC.K1.INIT 1000010000100001
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R28C45:PLC2
|
|
arc: E1_H02E0001 W3_H06E0003
|
|
arc: E1_H02E0601 W1_H02E0601
|
|
arc: E1_H02E0701 N1_V01S0100
|
|
arc: N1_V02N0001 W1_H02E0001
|
|
arc: N1_V02N0201 N1_V01S0000
|
|
arc: N1_V02N0401 E1_H02W0401
|
|
arc: N1_V02N0501 E1_H02W0501
|
|
arc: N1_V02N0601 E1_H02W0601
|
|
arc: N1_V02N0701 E1_H02W0701
|
|
arc: S1_V02S0001 E1_H02W0001
|
|
arc: S1_V02S0401 H06W0203
|
|
arc: S1_V02S0701 H02E0701
|
|
arc: V00B0000 V02N0201
|
|
arc: W1_H02W0201 N1_V01S0000
|
|
arc: W1_H02W0301 E1_H02W0201
|
|
arc: W1_H02W0601 V06S0303
|
|
arc: W3_H06W0003 V06S0003
|
|
arc: W3_H06W0103 E1_H02W0201
|
|
arc: A0 H00L0000
|
|
arc: A2 S1_V02N0701
|
|
arc: A3 E1_H01E0001
|
|
arc: A5 V00T0100
|
|
arc: B0 E1_H02W0301
|
|
arc: B1 E1_H02W0301
|
|
arc: B2 H00L0000
|
|
arc: B3 V02N0101
|
|
arc: B4 E1_H02W0301
|
|
arc: B5 V02N0501
|
|
arc: B6 E1_H02W0301
|
|
arc: C0 H02E0601
|
|
arc: C1 H00L0100
|
|
arc: C2 H00L0100
|
|
arc: C3 H00L0000
|
|
arc: C5 V01N0101
|
|
arc: C6 H02E0401
|
|
arc: CE0 H00R0000
|
|
arc: CE2 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V00T0100
|
|
arc: D1 V01S0100
|
|
arc: D2 V01S0100
|
|
arc: D3 V00T0100
|
|
arc: D4 H01W0000
|
|
arc: D5 H01W0000
|
|
arc: E1_H01E0001 Q4
|
|
arc: E1_H01E0101 F2
|
|
arc: E1_H02E0201 F2
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: H00L0000 Q0
|
|
arc: H00L0100 Q1
|
|
arc: H00R0000 F6
|
|
arc: H01W0000 Q4
|
|
arc: LSR1 V00B0000
|
|
arc: M2 V00B0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR2 LSR1
|
|
arc: V00B0100 F5
|
|
arc: V00T0100 Q1
|
|
arc: V01S0100 Q4
|
|
word: SLICEA.K0.INIT 0100100010001000
|
|
word: SLICEC.K0.INIT 0000000011001100
|
|
word: SLICEA.K1.INIT 0000110011000000
|
|
word: SLICED.K0.INIT 1111110011111100
|
|
word: SLICEC.K1.INIT 1110100001000100
|
|
word: SLICEB.K1.INIT 0001001000110000
|
|
word: SLICEB.K0.INIT 0111110111011101
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
|
|
.tile R28C46:PLC2
|
|
arc: E1_H02E0401 S1_V02N0401
|
|
arc: E1_H02E0501 H01E0101
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
arc: H00L0000 V02S0201
|
|
arc: H00R0000 V02S0401
|
|
arc: N1_V02N0101 S3_V06N0103
|
|
arc: N1_V02N0401 H06E0203
|
|
arc: N1_V02N0701 S3_V06N0203
|
|
arc: N3_V06N0003 S1_V02N0301
|
|
arc: N3_V06N0203 S1_V02N0401
|
|
arc: N3_V06N0303 S3_V06N0203
|
|
arc: S1_V02S0001 W1_H02E0001
|
|
arc: S1_V02S0101 N1_V02S0001
|
|
arc: V00B0000 V02S0201
|
|
arc: V00B0100 V02N0101
|
|
arc: V00T0000 S1_V02N0401
|
|
arc: V00T0100 W1_H02E0301
|
|
arc: V01S0000 S3_V06N0103
|
|
arc: A1 H00L0000
|
|
arc: A5 S1_V02N0301
|
|
arc: B0 W1_H02E0301
|
|
arc: B1 W1_H02E0301
|
|
arc: B4 N1_V02S0701
|
|
arc: B5 W1_H02E0301
|
|
arc: C0 V02N0601
|
|
arc: C1 E1_H02W0601
|
|
arc: C4 V00T0100
|
|
arc: C5 H02E0601
|
|
arc: C7 V00T0000
|
|
arc: D0 V02S0201
|
|
arc: D1 H02E0001
|
|
arc: D3 H02E0001
|
|
arc: D4 V00B0000
|
|
arc: D5 H02E0001
|
|
arc: D6 S1_V02N0401
|
|
arc: D7 H02E0001
|
|
arc: F0 F5A_SLICE
|
|
arc: F1 FXA_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F4 F5C_SLICE
|
|
arc: F5 FXC_SLICE
|
|
arc: F6 F5D_SLICE
|
|
arc: M0 V00B0100
|
|
arc: M1 H00R0000
|
|
arc: M2 V00B0100
|
|
arc: M4 V00B0100
|
|
arc: M5 H00R0000
|
|
arc: M6 V00B0100
|
|
arc: N1_V01N0101 F5
|
|
arc: N1_V02N0301 F1
|
|
arc: N1_V02N0501 F5
|
|
word: SLICEA.K0.INIT 1100000000000000
|
|
word: SLICEA.K1.INIT 1111111110000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 1111111100000000
|
|
word: SLICEC.K0.INIT 1111110011001100
|
|
word: SLICEC.K1.INIT 1111111111101010
|
|
word: SLICED.K0.INIT 1111111100000000
|
|
word: SLICED.K1.INIT 1111111111110000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
|
|
.tile R28C47:PLC2
|
|
arc: E1_H02E0201 V06N0103
|
|
arc: E1_H02E0601 V02S0601
|
|
arc: H00R0100 W1_H02E0701
|
|
arc: N1_V02N0101 E1_H02W0101
|
|
arc: N1_V02N0201 H06E0103
|
|
arc: N1_V02N0301 S3_V06N0003
|
|
arc: N1_V02N0401 E1_H01W0000
|
|
arc: N1_V02N0601 W3_H06E0303
|
|
arc: N3_V06N0003 S3_V06N0303
|
|
arc: N3_V06N0103 S3_V06N0003
|
|
arc: N3_V06N0303 S3_V06N0303
|
|
arc: S1_V02S0001 N1_V02S0501
|
|
arc: S1_V02S0601 V01N0001
|
|
arc: V00B0000 H02E0401
|
|
arc: V00B0100 V02N0301
|
|
arc: W1_H02W0001 V01N0001
|
|
arc: W1_H02W0201 V02N0201
|
|
arc: W1_H02W0301 V02N0301
|
|
arc: W1_H02W0401 V06N0203
|
|
arc: W1_H02W0501 W3_H06E0303
|
|
arc: W1_H02W0601 W3_H06E0303
|
|
arc: W1_H02W0701 V02N0701
|
|
arc: W3_H06W0103 E1_H01W0100
|
|
arc: W3_H06W0203 V06S0203
|
|
arc: W3_H06W0303 S3_V06N0303
|
|
arc: A1 S1_V02N0701
|
|
arc: A5 H02E0501
|
|
arc: B0 V00B0000
|
|
arc: B1 V01N0001
|
|
arc: B4 V02S0501
|
|
arc: B5 V02S0501
|
|
arc: C0 S1_V02N0601
|
|
arc: C1 S1_V02N0401
|
|
arc: C2 H02E0401
|
|
arc: C3 H02E0401
|
|
arc: C4 V02N0201
|
|
arc: C5 S1_V02N0201
|
|
arc: D0 V02N0201
|
|
arc: D1 W1_H02E0201
|
|
arc: D3 W1_H02E0201
|
|
arc: D4 S1_V02N0601
|
|
arc: D5 V01N0001
|
|
arc: D7 W1_H02E0201
|
|
arc: E1_H02E0101 F1
|
|
arc: E1_H02E0701 F5
|
|
arc: F0 F5A_SLICE
|
|
arc: F1 FXA_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F4 F5C_SLICE
|
|
arc: F5 FXC_SLICE
|
|
arc: F6 F5D_SLICE
|
|
arc: M0 V00B0100
|
|
arc: M1 H00R0100
|
|
arc: M2 V00B0100
|
|
arc: M4 V00B0100
|
|
arc: M5 H00R0100
|
|
arc: M6 V00B0100
|
|
word: SLICEC.K0.INIT 1100000000000000
|
|
word: SLICEC.K1.INIT 1100101010101010
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 1111111100000000
|
|
word: SLICEA.K0.INIT 1111110011001100
|
|
word: SLICEA.K1.INIT 1111111111101010
|
|
word: SLICEB.K0.INIT 1111000011110000
|
|
word: SLICEB.K1.INIT 1111111111110000
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
|
|
.tile R28C48:PLC2
|
|
arc: E1_H02E0001 V02S0001
|
|
arc: E1_H02E0601 V02N0601
|
|
arc: H00R0000 V02N0601
|
|
arc: N1_V02N0001 S1_V02N0501
|
|
arc: N1_V02N0101 S3_V06N0103
|
|
arc: N1_V02N0201 H02E0201
|
|
arc: N1_V02N0401 E1_H02W0401
|
|
arc: N1_V02N0501 N1_V01S0100
|
|
arc: N1_V02N0701 S3_V06N0203
|
|
arc: N3_V06N0303 S3_V06N0203
|
|
arc: S1_V02S0101 H02W0101
|
|
arc: S1_V02S0201 H02W0201
|
|
arc: V00B0100 H02E0701
|
|
arc: V00T0100 V02S0501
|
|
arc: W1_H02W0601 S1_V02N0601
|
|
arc: W3_H06W0203 V06S0203
|
|
arc: A0 H00R0000
|
|
arc: B0 E1_H02W0101
|
|
arc: B5 F3
|
|
arc: B7 F3
|
|
arc: C0 S1_V02N0601
|
|
arc: C1 E1_H01W0000
|
|
arc: C2 F4
|
|
arc: C3 V02S0601
|
|
arc: C4 V00T0000
|
|
arc: C5 H02E0601
|
|
arc: C7 N1_V02S0201
|
|
arc: CE0 H02E0101
|
|
arc: CE2 H02E0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02S0001
|
|
arc: D1 S1_V02N0001
|
|
arc: D2 V02N0001
|
|
arc: D3 E1_H02W0001
|
|
arc: D4 V00B0000
|
|
arc: D5 N1_V02S0601
|
|
arc: D7 V02N0401
|
|
arc: E1_H01E0101 F3
|
|
arc: E1_H02E0201 Q0
|
|
arc: E1_H02E0401 Q4
|
|
arc: E1_H02E0501 F5
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 F2
|
|
arc: H01W0100 F2
|
|
arc: LSR0 V00T0100
|
|
arc: M4 V00B0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR2 LSR0
|
|
arc: N1_V01N0001 F1
|
|
arc: N1_V01N0101 F7
|
|
arc: N1_V02N0601 F4
|
|
arc: S1_V02S0701 F5
|
|
arc: V00B0000 Q4
|
|
arc: V00T0000 Q0
|
|
arc: V01S0000 Q4
|
|
arc: V01S0100 Q0
|
|
word: SLICEC.K1.INIT 0000110000000000
|
|
word: SLICEA.K1.INIT 0000111100000000
|
|
word: SLICED.K1.INIT 1100000000000000
|
|
word: SLICEA.K0.INIT 0000100000000000
|
|
word: SLICEC.K0.INIT 0000111100000000
|
|
word: SLICEB.K1.INIT 0000000000001111
|
|
word: SLICEB.K0.INIT 0000000000001111
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET SET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET SET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
|
|
.tile R28C49:PLC2
|
|
arc: E1_H02E0201 S1_V02N0201
|
|
arc: E1_H02E0601 N1_V02S0601
|
|
arc: H00R0000 V02S0601
|
|
arc: H00R0100 S1_V02N0701
|
|
arc: N1_V01N0001 S3_V06N0003
|
|
arc: N1_V02N0001 S1_V02N0001
|
|
arc: N1_V02N0101 W3_H06E0103
|
|
arc: N1_V02N0301 S3_V06N0003
|
|
arc: N1_V02N0401 E1_H01W0000
|
|
arc: N3_V06N0103 S1_V02N0201
|
|
arc: S1_V02S0101 H01E0101
|
|
arc: S1_V02S0601 H02E0601
|
|
arc: S1_V02S0701 E1_H01W0100
|
|
arc: S3_V06S0203 N1_V01S0000
|
|
arc: V00B0100 S1_V02N0301
|
|
arc: V00T0000 S1_V02N0401
|
|
arc: W1_H02W0101 W3_H06E0103
|
|
arc: W1_H02W0201 W3_H06E0103
|
|
arc: A1 S1_V02N0501
|
|
arc: A4 V02N0301
|
|
arc: A6 F7
|
|
arc: A7 H00R0000
|
|
arc: B0 V00T0000
|
|
arc: B1 V00T0000
|
|
arc: B4 S1_V02N0501
|
|
arc: B6 H02W0101
|
|
arc: B7 V02S0701
|
|
arc: C0 N1_V02S0601
|
|
arc: C1 N1_V02S0601
|
|
arc: C4 H02E0601
|
|
arc: C6 H02E0401
|
|
arc: C7 V02N0001
|
|
arc: CE2 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02S0201
|
|
arc: D1 E1_H02W0201
|
|
arc: D3 E1_H02W0201
|
|
arc: D4 H02E0001
|
|
arc: D6 H02E0201
|
|
arc: D7 V00B0000
|
|
arc: E1_H02E0301 F1
|
|
arc: F0 F5A_SLICE
|
|
arc: F1 FXA_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 Q4
|
|
arc: LSR1 H02E0501
|
|
arc: M0 V00B0100
|
|
arc: M1 H02E0001
|
|
arc: M2 V00B0100
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR2 LSR1
|
|
arc: S1_V02S0401 Q4
|
|
arc: V00B0000 Q4
|
|
arc: V01S0000 F6
|
|
word: SLICEC.K0.INIT 0010000000000000
|
|
word: SLICED.K1.INIT 0001000100010000
|
|
word: SLICED.K0.INIT 0001000100010101
|
|
word: SLICEA.K0.INIT 1100000000000000
|
|
word: SLICEA.K1.INIT 1000000010111111
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000011111111
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET SET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
|
|
.tile R28C4:PLC2
|
|
arc: W3_H06W0303 E3_H06W0203
|
|
|
|
.tile R28C50:PLC2
|
|
arc: E1_H02E0401 V06S0203
|
|
arc: E1_H02E0501 W3_H06E0303
|
|
arc: E1_H02E0701 W3_H06E0203
|
|
arc: H00R0000 H02E0601
|
|
arc: H00R0100 S1_V02N0701
|
|
arc: H01W0100 W3_H06E0303
|
|
arc: N1_V02N0001 W3_H06E0003
|
|
arc: N1_V02N0601 W3_H06E0303
|
|
arc: N1_V02N0701 W3_H06E0203
|
|
arc: S1_V02S0101 H06W0103
|
|
arc: S1_V02S0201 S3_V06N0103
|
|
arc: S1_V02S0301 N3_V06S0003
|
|
arc: S1_V02S0401 H02W0401
|
|
arc: S1_V02S0501 V01N0101
|
|
arc: S1_V02S0701 N1_V02S0601
|
|
arc: S3_V06S0103 E1_H01W0100
|
|
arc: V00B0000 S1_V02N0201
|
|
arc: V00B0100 H02W0701
|
|
arc: V00T0000 E1_H02W0201
|
|
arc: V00T0100 H02E0301
|
|
arc: W1_H02W0001 W3_H06E0003
|
|
arc: W1_H02W0101 V02N0101
|
|
arc: W1_H02W0401 V06S0203
|
|
arc: A0 V02N0501
|
|
arc: A1 V02N0501
|
|
arc: A4 V02S0301
|
|
arc: B1 H00R0100
|
|
arc: B4 V02N0501
|
|
arc: C0 H00R0100
|
|
arc: C1 E1_H01W0000
|
|
arc: C3 E1_H01W0000
|
|
arc: C4 V02S0001
|
|
arc: CE3 H00L0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H00R0000
|
|
arc: D1 H00R0000
|
|
arc: D2 V00B0100
|
|
arc: D3 V00B0100
|
|
arc: D4 H01W0000
|
|
arc: F0 F5A_SLICE
|
|
arc: F1 FXA_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: H00L0100 F1
|
|
arc: H01W0000 Q6
|
|
arc: LSR1 V00T0000
|
|
arc: M0 V00B0000
|
|
arc: M1 H02W0001
|
|
arc: M2 V00B0000
|
|
arc: M6 V00T0100
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR3 LSR1
|
|
arc: N1_V02N0401 Q6
|
|
arc: S1_V02S0601 F4
|
|
arc: V01S0000 F1
|
|
word: SLICEA.K0.INIT 1111101010101010
|
|
word: SLICEA.K1.INIT 1110111110101111
|
|
word: SLICEB.K0.INIT 1111111100000000
|
|
word: SLICEB.K1.INIT 1111111100001111
|
|
word: SLICEC.K0.INIT 0000000000100000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET SET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
|
|
.tile R28C51:PLC2
|
|
arc: E1_H02E0001 N1_V01S0000
|
|
arc: E3_H06E0203 N1_V01S0000
|
|
arc: H00R0100 N1_V02S0501
|
|
arc: N1_V02N0401 H02E0401
|
|
arc: N1_V02N0501 S3_V06N0303
|
|
arc: N1_V02N0601 S3_V06N0303
|
|
arc: N1_V02N0701 N1_V01S0100
|
|
arc: N3_V06N0103 S3_V06N0103
|
|
arc: S1_V02S0001 N1_V02S0501
|
|
arc: S1_V02S0501 V01N0101
|
|
arc: S1_V02S0701 S3_V06N0203
|
|
arc: V00T0000 W1_H02E0201
|
|
arc: V00T0100 S1_V02N0701
|
|
arc: W1_H02W0001 V02S0001
|
|
arc: W1_H02W0401 V06S0203
|
|
arc: W1_H02W0701 S1_V02N0701
|
|
arc: A0 E1_H01E0001
|
|
arc: A1 E1_H01E0001
|
|
arc: A4 V00T0100
|
|
arc: A6 S1_V02N0101
|
|
arc: B0 S1_V02N0101
|
|
arc: B1 S1_V02N0101
|
|
arc: B4 S1_V02N0501
|
|
arc: B6 V02N0501
|
|
arc: C0 V02N0601
|
|
arc: C1 V02N0601
|
|
arc: C4 V02S0001
|
|
arc: C6 V00B0100
|
|
arc: CE0 H00R0000
|
|
arc: CE2 H00R0000
|
|
arc: CE3 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02N0001
|
|
arc: D1 V02N0201
|
|
arc: D4 N1_V02S0401
|
|
arc: D6 H00L0100
|
|
arc: E1_H01E0001 Q4
|
|
arc: F0 F5A_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: H00L0100 Q1
|
|
arc: H00R0000 F4
|
|
arc: H01W0000 F0
|
|
arc: H01W0100 Q4
|
|
arc: LSR0 V00T0000
|
|
arc: LSR1 V00T0100
|
|
arc: M0 V00B0000
|
|
arc: M1 H00R0100
|
|
arc: M4 E1_H02W0401
|
|
arc: M7 E1_H02W0201
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR0
|
|
arc: S1_V02S0101 Q1
|
|
arc: S1_V02S0301 Q1
|
|
arc: S1_V02S0401 Q4
|
|
arc: V00B0000 F6
|
|
arc: V00B0100 Q7
|
|
arc: V01S0000 Q7
|
|
arc: W1_H02W0201 F0
|
|
word: SLICEC.K0.INIT 1110101010101010
|
|
word: SLICED.K0.INIT 1101100010010000
|
|
word: SLICEA.K0.INIT 1000000000101010
|
|
word: SLICEA.K1.INIT 1110101010111111
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R28C52:PLC2
|
|
arc: E3_H06E0103 N1_V01S0100
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
arc: H00R0100 W1_H02E0501
|
|
arc: N1_V02N0301 H02W0301
|
|
arc: N1_V02N0401 S3_V06N0203
|
|
arc: N1_V02N0601 H02W0601
|
|
arc: V00B0000 V02N0201
|
|
arc: A1 W1_H02E0701
|
|
arc: B1 H00R0100
|
|
arc: C1 V02S0601
|
|
arc: D1 H02E0001
|
|
arc: F0 F5A_SLICE
|
|
arc: M0 V00B0000
|
|
arc: N1_V01N0101 F0
|
|
arc: W1_H02W0201 F0
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000001000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R28C53:PLC2
|
|
arc: E1_H02E0301 V02N0301
|
|
arc: N1_V02N0101 S3_V06N0103
|
|
arc: N1_V02N0401 S1_V02N0101
|
|
arc: N1_V02N0701 S3_V06N0203
|
|
arc: V01S0100 S3_V06N0303
|
|
arc: W1_H02W0201 N3_V06S0103
|
|
arc: W1_H02W0301 E3_H06W0003
|
|
arc: W1_H02W0401 S1_V02N0401
|
|
arc: W1_H02W0601 V06N0303
|
|
arc: W3_H06W0103 S3_V06N0103
|
|
|
|
.tile R28C54:PLC2
|
|
arc: E3_H06E0203 N1_V01S0000
|
|
arc: E3_H06E0303 N1_V01S0100
|
|
arc: N1_V02N0301 H02E0301
|
|
|
|
.tile R28C55:PLC2
|
|
arc: N1_V02N0001 S3_V06N0003
|
|
|
|
.tile R28C57:PLC2
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
|
|
.tile R28C58:PLC2
|
|
arc: E1_H02E0101 S3_V06N0103
|
|
arc: E1_H02E0401 S3_V06N0203
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
|
|
.tile R28C59:PLC2
|
|
arc: N1_V02N0101 H02E0101
|
|
arc: N1_V02N0401 H02E0401
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
|
|
.tile R28C5:PLC2
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
|
|
.tile R28C60:PLC2
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
|
|
.tile R28C61:PLC2
|
|
arc: N1_V02N0001 S3_V06N0003
|
|
|
|
.tile R28C62:PLC2
|
|
arc: E3_H06E0203 N1_V01S0000
|
|
arc: E3_H06E0303 N1_V01S0100
|
|
arc: N1_V02N0101 H06W0103
|
|
|
|
.tile R28C63:PLC2
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
|
|
.tile R28C64:PLC2
|
|
arc: E1_H02E0401 S3_V06N0203
|
|
arc: E3_H06E0003 N1_V01S0000
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
arc: N1_V02N0001 H02W0001
|
|
arc: N1_V02N0401 S3_V06N0203
|
|
|
|
.tile R28C65:PLC2
|
|
arc: E3_H06E0003 N1_V01S0000
|
|
arc: E3_H06E0303 N1_V01S0100
|
|
arc: N1_V02N0401 H02E0401
|
|
arc: W1_H02W0001 V06N0003
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
arc: W3_H06W0103 S3_V06N0103
|
|
|
|
.tile R28C66:PLC2
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
|
|
.tile R28C67:PLC2
|
|
arc: N1_V02N0101 N3_V06S0103
|
|
|
|
.tile R28C68:PLC2
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
|
|
.tile R28C69:PLC2
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
|
|
.tile R28C70:PLC2
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
|
|
.tile R28C71:PLC2
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
|
|
.tile R28C72:PLC2
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
|
|
.tile R28C74:PLC2
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
|
|
.tile R28C75:PLC2
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
|
|
.tile R28C76:PLC2
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
|
|
.tile R28C77:PLC2
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
|
|
.tile R28C78:PLC2
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
|
|
.tile R28C7:PLC2
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
arc: V01S0100 S3_V06N0303
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
arc: W3_H06W0203 E3_H06W0203
|
|
|
|
.tile R28C80:PLC2
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
|
|
.tile R28C81:PLC2
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
|
|
.tile R28C82:PLC2
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
|
|
.tile R28C83:PLC2
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
|
|
.tile R28C84:PLC2
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
|
|
.tile R28C86:PLC2
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
|
|
.tile R28C87:PLC2
|
|
arc: E1_H02E0501 W3_H06E0303
|
|
arc: S3_V06S0203 H06E0203
|
|
arc: S3_V06S0303 H06E0303
|
|
|
|
.tile R28C88:PLC2
|
|
arc: S3_V06S0003 W3_H06E0003
|
|
arc: S3_V06S0203 W3_H06E0203
|
|
arc: S3_V06S0303 W3_H06E0303
|
|
|
|
.tile R28C8:PLC2
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
|
|
.tile R29C13:PLC2
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
arc: N1_V02N0201 W3_H06E0103
|
|
|
|
.tile R29C17:PLC2
|
|
arc: N1_V02N0301 S1_V02N0201
|
|
|
|
.tile R29C19:PLC2
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
|
|
.tile R29C22:PLC2
|
|
arc: E1_H02E0301 S1_V02N0301
|
|
|
|
.tile R29C23:PLC2
|
|
arc: N1_V02N0101 S1_V02N0001
|
|
arc: N1_V02N0301 H02E0301
|
|
arc: N1_V02N0701 E1_H02W0701
|
|
|
|
.tile R29C25:PLC2
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: N1_V02N0201 S1_V02N0201
|
|
arc: W1_H02W0701 W3_H06E0203
|
|
|
|
.tile R29C29:PLC2
|
|
arc: N1_V02N0501 S1_V02N0401
|
|
|
|
.tile R29C31:PLC2
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: N1_V02N0001 S3_V06N0003
|
|
arc: N1_V02N0301 W3_H06E0003
|
|
arc: N1_V02N0501 H06W0303
|
|
|
|
.tile R29C32:PLC2
|
|
arc: N1_V02N0101 S1_V02N0101
|
|
|
|
.tile R29C34:PLC2
|
|
arc: N1_V02N0001 S1_V02N0001
|
|
arc: N1_V02N0101 S3_V06N0103
|
|
arc: N1_V02N0301 S1_V02N0301
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
|
|
.tile R29C35:PLC2
|
|
arc: N1_V02N0301 S1_V02N0201
|
|
|
|
.tile R29C36:PLC2
|
|
arc: E1_H02E0701 S1_V02N0701
|
|
|
|
.tile R29C37:PLC2
|
|
arc: E1_H01E0101 W3_H06E0203
|
|
arc: E1_H02E0401 W3_H06E0203
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
arc: N1_V02N0001 S1_V02N0501
|
|
arc: N1_V02N0401 S1_V02N0101
|
|
arc: N1_V02N0601 S3_V06N0303
|
|
|
|
.tile R29C38:PLC2
|
|
arc: E1_H02E0201 W1_H02E0701
|
|
arc: N1_V02N0101 S1_V02N0001
|
|
arc: N1_V02N0501 H01E0101
|
|
|
|
.tile R29C39:PLC2
|
|
arc: E1_H02E0301 N1_V01S0100
|
|
arc: E1_H02E0601 S1_V02N0601
|
|
arc: E3_H06E0203 W1_H02E0401
|
|
arc: H00L0000 N1_V02S0001
|
|
arc: H00L0100 S1_V02N0301
|
|
arc: H00R0100 S1_V02N0701
|
|
arc: N1_V02N0401 W1_H02E0401
|
|
arc: N1_V02N0501 E1_H02W0501
|
|
arc: N1_V02N0601 S1_V02N0601
|
|
arc: N1_V02N0701 V01N0101
|
|
arc: S1_V02S0101 H06W0103
|
|
arc: S1_V02S0201 N1_V02S0701
|
|
arc: V00B0000 V02S0201
|
|
arc: V00T0000 H02W0001
|
|
arc: V00T0100 E1_H02W0301
|
|
arc: A0 E1_H02W0701
|
|
arc: A2 H02W0501
|
|
arc: A4 S1_V02N0101
|
|
arc: B0 H01W0100
|
|
arc: B2 V02N0301
|
|
arc: B4 H02W0301
|
|
arc: B5 E1_H02W0101
|
|
arc: C0 N1_V01S0100
|
|
arc: C2 F4
|
|
arc: C3 H02W0601
|
|
arc: C4 Q4
|
|
arc: C5 S1_V02N0201
|
|
arc: CE1 H02W0101
|
|
arc: CE2 H00R0100
|
|
arc: CE3 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H00R0000
|
|
arc: D2 E1_H02W0001
|
|
arc: D4 F0
|
|
arc: D5 E1_H01W0100
|
|
arc: E1_H01E0101 Q5
|
|
arc: E1_H02E0501 Q7
|
|
arc: E3_H06E0103 F2
|
|
arc: F0 F5A_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: H00R0000 Q6
|
|
arc: H01W0100 Q5
|
|
arc: M0 V00T0000
|
|
arc: M2 V00B0100
|
|
arc: M3 H00L0100
|
|
arc: M4 V00B0000
|
|
arc: M5 H00L0000
|
|
arc: M6 V00T0100
|
|
arc: M7 H02E0201
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q3
|
|
arc: V00B0100 F5
|
|
arc: V01S0000 F2
|
|
arc: V01S0100 F2
|
|
word: SLICEA.K0.INIT 1000101001000101
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 1100000011110000
|
|
word: SLICEC.K0.INIT 1000010000000000
|
|
word: SLICEB.K1.INIT 1111000011110000
|
|
word: SLICEB.K0.INIT 1010101010101000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R29C3:PLC2
|
|
arc: W1_H02W0501 E1_H02W0501
|
|
|
|
.tile R29C40:PLC2
|
|
arc: E1_H02E0201 N1_V01S0000
|
|
arc: E1_H02E0401 V06N0203
|
|
arc: H00R0100 V02N0501
|
|
arc: N1_V02N0001 S1_V02N0501
|
|
arc: N1_V02N0201 V01N0001
|
|
arc: N1_V02N0501 S3_V06N0303
|
|
arc: N3_V06N0103 S1_V02N0201
|
|
arc: N3_V06N0303 S1_V02N0501
|
|
arc: S1_V02S0201 V01N0001
|
|
arc: S1_V02S0301 H02E0301
|
|
arc: S1_V02S0601 N1_V02S0301
|
|
arc: V00B0000 S1_V02N0001
|
|
arc: W1_H02W0101 V01N0101
|
|
arc: W1_H02W0501 N1_V02S0501
|
|
arc: W1_H02W0601 N1_V02S0601
|
|
arc: W3_H06W0303 E3_H06W0203
|
|
arc: A1 H00L0100
|
|
arc: A2 E1_H02W0701
|
|
arc: A3 H02E0501
|
|
arc: A6 V02S0101
|
|
arc: A7 Q7
|
|
arc: B0 V00T0000
|
|
arc: B1 V02N0301
|
|
arc: B2 V02N0101
|
|
arc: B3 H02E0301
|
|
arc: C1 V02N0401
|
|
arc: C2 V02S0601
|
|
arc: C3 H02E0601
|
|
arc: C7 V00T0100
|
|
arc: CE0 H00L0000
|
|
arc: CE3 H00L0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V00B0100
|
|
arc: D1 V01S0100
|
|
arc: D2 V02N0001
|
|
arc: D3 H01E0101
|
|
arc: D6 H00R0100
|
|
arc: D7 H01W0000
|
|
arc: E1_H01E0001 F6
|
|
arc: E1_H01E0101 Q1
|
|
arc: E1_H02E0601 F6
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00L0000 F2
|
|
arc: H00L0100 Q1
|
|
arc: H01W0000 Q0
|
|
arc: H01W0100 F0
|
|
arc: LSR1 V00B0000
|
|
arc: M0 H02W0601
|
|
arc: M1 E1_H02W0001
|
|
arc: M7 H02W0201
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR3 LSR1
|
|
arc: N1_V01N0001 F1
|
|
arc: N1_V01N0101 Q7
|
|
arc: S1_V02S0501 Q7
|
|
arc: V00B0100 Q7
|
|
arc: V00T0000 Q0
|
|
arc: V00T0100 Q1
|
|
arc: V01S0000 F7
|
|
arc: V01S0100 Q0
|
|
arc: W1_H02W0001 F0
|
|
arc: W1_H02W0301 F3
|
|
word: SLICED.K0.INIT 0101010110101010
|
|
word: SLICED.K1.INIT 0000010101010101
|
|
word: SLICEB.K1.INIT 1000010010100101
|
|
word: SLICEA.K0.INIT 0000000000110011
|
|
word: SLICEA.K1.INIT 1100101110000000
|
|
word: SLICEB.K0.INIT 1110110011001100
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R29C41:PLC2
|
|
arc: E1_H02E0101 V01N0101
|
|
arc: E1_H02E0201 E3_H06W0103
|
|
arc: E1_H02E0301 N1_V01S0100
|
|
arc: E1_H02E0401 N1_V01S0000
|
|
arc: E1_H02E0701 E3_H06W0203
|
|
arc: H00L0000 S1_V02N0201
|
|
arc: H00R0000 H02E0601
|
|
arc: H00R0100 V02S0701
|
|
arc: N1_V01N0001 S3_V06N0003
|
|
arc: N1_V02N0001 H01E0001
|
|
arc: N1_V02N0201 E1_H02W0201
|
|
arc: N1_V02N0301 S3_V06N0003
|
|
arc: N1_V02N0401 H02E0401
|
|
arc: N1_V02N0501 S1_V02N0401
|
|
arc: N1_V02N0701 S3_V06N0203
|
|
arc: N3_V06N0003 S3_V06N0303
|
|
arc: N3_V06N0103 S3_V06N0003
|
|
arc: S1_V02S0401 E1_H02W0401
|
|
arc: V00T0000 V02S0601
|
|
arc: W1_H02W0001 S1_V02N0001
|
|
arc: W1_H02W0101 H01E0101
|
|
arc: W1_H02W0201 E3_H06W0103
|
|
arc: W1_H02W0301 S1_V02N0301
|
|
arc: W1_H02W0501 V06N0303
|
|
arc: W1_H02W0601 N1_V02S0601
|
|
arc: W1_H02W0701 S1_V02N0701
|
|
arc: A4 H02W0501
|
|
arc: A5 H02W0501
|
|
arc: A6 H02W0501
|
|
arc: A7 H02W0501
|
|
arc: B4 V02N0501
|
|
arc: B5 V02N0501
|
|
arc: B6 V02N0501
|
|
arc: B7 V02N0501
|
|
arc: C4 W1_H02E0601
|
|
arc: C5 W1_H02E0601
|
|
arc: C6 W1_H02E0601
|
|
arc: C7 W1_H02E0601
|
|
arc: CE3 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D4 V02N0601
|
|
arc: D5 V02N0601
|
|
arc: D6 V02N0601
|
|
arc: D7 V02N0601
|
|
arc: E1_H01E0101 F3
|
|
arc: F0 F5A_SLICE
|
|
arc: F1 FXA_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F3 FXB_SLICE
|
|
arc: F4 F5C_SLICE
|
|
arc: F5 FXC_SLICE
|
|
arc: F6 F5D_SLICE
|
|
arc: M0 V00T0000
|
|
arc: M1 H00L0000
|
|
arc: M2 V00T0000
|
|
arc: M3 H00R0000
|
|
arc: M4 V00T0000
|
|
arc: M5 H00L0000
|
|
arc: M6 V00T0000
|
|
arc: M7 H02E0201
|
|
arc: MUXCLK3 CLK0
|
|
arc: S1_V02S0501 Q7
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 0000100000000010
|
|
word: SLICEC.K1.INIT 1000000000100000
|
|
word: SLICED.K0.INIT 0000010000000001
|
|
word: SLICED.K1.INIT 0100000000010000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R29C42:PLC2
|
|
arc: E1_H02E0001 V02N0001
|
|
arc: E1_H02E0101 V02N0101
|
|
arc: E1_H02E0601 S1_V02N0601
|
|
arc: H00L0100 H02W0101
|
|
arc: S1_V02S0201 E1_H01W0000
|
|
arc: W1_H02W0001 V06S0003
|
|
arc: W1_H02W0501 V02N0501
|
|
arc: W1_H02W0701 E1_H01W0100
|
|
arc: W3_H06W0103 E1_H01W0100
|
|
arc: A0 H00L0100
|
|
arc: A2 V02S0701
|
|
arc: A3 V00B0000
|
|
arc: A4 H02W0701
|
|
arc: A5 V02N0101
|
|
arc: A7 V02N0101
|
|
arc: B0 V00B0000
|
|
arc: B2 H02E0101
|
|
arc: B3 H00R0100
|
|
arc: B6 H02W0101
|
|
arc: B7 V02S0501
|
|
arc: C0 H00R0100
|
|
arc: C1 V02S0601
|
|
arc: C2 S1_V02N0401
|
|
arc: C3 H02W0601
|
|
arc: C4 Q4
|
|
arc: C7 H02E0401
|
|
arc: CE0 H00R0000
|
|
arc: CE2 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 Q0
|
|
arc: D1 F2
|
|
arc: D2 H01E0101
|
|
arc: D3 N1_V01S0000
|
|
arc: D4 H00R0100
|
|
arc: D5 H00R0100
|
|
arc: D6 V02S0401
|
|
arc: D7 H02W0001
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F5D_SLICE
|
|
arc: H00R0000 F6
|
|
arc: H00R0100 Q5
|
|
arc: LSR0 H02E0301
|
|
arc: M6 V00T0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR2 LSR0
|
|
arc: N1_V01N0101 Q0
|
|
arc: N1_V02N0001 F2
|
|
arc: N1_V02N0101 F3
|
|
arc: N1_V02N0201 F2
|
|
arc: N1_V02N0401 Q4
|
|
arc: N1_V02N0501 Q5
|
|
arc: N1_V02N0601 Q4
|
|
arc: N1_V02N0701 Q5
|
|
arc: V00B0000 Q4
|
|
arc: V00T0100 F1
|
|
word: SLICEB.K1.INIT 1101100110000000
|
|
word: SLICEB.K0.INIT 1010101010000000
|
|
word: SLICEA.K0.INIT 0001010101000000
|
|
word: SLICEC.K0.INIT 0000010101010000
|
|
word: SLICEC.K1.INIT 0000000001010101
|
|
word: SLICEA.K1.INIT 0000000000001111
|
|
word: SLICED.K0.INIT 1111111111001100
|
|
word: SLICED.K1.INIT 1010111010101010
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R29C43:PLC2
|
|
arc: E1_H02E0201 W1_H02E0201
|
|
arc: E1_H02E0401 V06N0203
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: H00R0000 H02W0401
|
|
arc: N1_V02N0101 S3_V06N0103
|
|
arc: N1_V02N0201 S1_V02N0701
|
|
arc: N1_V02N0701 W1_H02E0701
|
|
arc: V00B0000 V02S0201
|
|
arc: V00B0100 V02N0101
|
|
arc: V00T0000 V02S0401
|
|
arc: W1_H02W0001 N1_V01S0000
|
|
arc: W1_H02W0101 V02N0101
|
|
arc: W1_H02W0201 E1_H02W0701
|
|
arc: W1_H02W0601 N1_V01S0000
|
|
arc: W1_H02W0701 V06N0203
|
|
arc: A2 H02W0501
|
|
arc: A3 H02W0501
|
|
arc: A6 V02S0301
|
|
arc: B2 V01N0001
|
|
arc: C2 S1_V02N0601
|
|
arc: C3 V02N0401
|
|
arc: CE2 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H02W0001
|
|
arc: D1 H02W0001
|
|
arc: D2 V02S0001
|
|
arc: D3 S1_V02N0001
|
|
arc: D6 V00B0000
|
|
arc: E1_H01E0001 F1
|
|
arc: E1_H01E0101 F6
|
|
arc: E1_H02E0101 F1
|
|
arc: F0 F5A_SLICE
|
|
arc: F1 FXA_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: H01W0000 F1
|
|
arc: H01W0100 F6
|
|
arc: LSR1 V00B0100
|
|
arc: M0 H02E0601
|
|
arc: M1 H02E0001
|
|
arc: M2 H02E0601
|
|
arc: M4 V00T0000
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR2 LSR1
|
|
arc: N3_V06N0303 F6
|
|
arc: S1_V02S0601 F6
|
|
arc: V01S0000 F1
|
|
arc: V01S0100 Q4
|
|
arc: W1_H02W0401 Q4
|
|
word: SLICEA.K0.INIT 1111111100000000
|
|
word: SLICEA.K1.INIT 1111111100000000
|
|
word: SLICEB.K0.INIT 1010001010100000
|
|
word: SLICEB.K1.INIT 1010101000001010
|
|
word: SLICED.K0.INIT 0000000001010101
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
|
|
.tile R29C44:PLC2
|
|
arc: E1_H02E0001 V02S0001
|
|
arc: E1_H02E0201 V06S0103
|
|
arc: E1_H02E0301 S3_V06N0003
|
|
arc: E1_H02E0401 V02S0401
|
|
arc: E3_H06E0103 H01E0101
|
|
arc: E3_H06E0303 H01E0101
|
|
arc: H00R0000 N1_V02S0601
|
|
arc: H00R0100 S1_V02N0501
|
|
arc: N1_V02N0001 H01E0001
|
|
arc: N1_V02N0301 H01E0101
|
|
arc: N1_V02N0401 H02E0401
|
|
arc: N1_V02N0501 S1_V02N0401
|
|
arc: N1_V02N0601 E1_H01W0000
|
|
arc: N3_V06N0103 H06W0103
|
|
arc: S1_V02S0101 W1_H02E0101
|
|
arc: S1_V02S0201 V01N0001
|
|
arc: S1_V02S0601 E1_H02W0601
|
|
arc: V00B0100 S1_V02N0101
|
|
arc: V00T0100 H02E0101
|
|
arc: V01S0100 S3_V06N0303
|
|
arc: W1_H02W0001 E1_H02W0501
|
|
arc: W1_H02W0401 V01N0001
|
|
arc: W1_H02W0501 E1_H02W0501
|
|
arc: A0 E1_H02W0701
|
|
arc: A1 E1_H02W0701
|
|
arc: A4 V02N0101
|
|
arc: A5 H02W0501
|
|
arc: B1 V02N0301
|
|
arc: B4 H02W0301
|
|
arc: B5 H01E0101
|
|
arc: C0 N1_V02S0401
|
|
arc: C1 N1_V02S0401
|
|
arc: C4 V01N0101
|
|
arc: C5 H02E0401
|
|
arc: CE2 E1_H02W0101
|
|
arc: CE3 E1_H02W0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02S0001
|
|
arc: D1 V02S0001
|
|
arc: D3 V02N0001
|
|
arc: D4 V00B0000
|
|
arc: D5 N1_V02S0601
|
|
arc: E1_H01E0001 F1
|
|
arc: E1_H01E0101 Q7
|
|
arc: E1_H02E0601 F4
|
|
arc: F0 F5A_SLICE
|
|
arc: F1 FXA_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: M0 H01E0001
|
|
arc: M1 H00R0000
|
|
arc: M2 V00T0100
|
|
arc: M4 H02W0401
|
|
arc: M6 V00B0100
|
|
arc: M7 H00R0100
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: S1_V02S0701 F5
|
|
arc: V00B0000 Q4
|
|
arc: V01S0000 Q6
|
|
word: SLICEA.K0.INIT 1010000000000000
|
|
word: SLICEA.K1.INIT 1110110011001100
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 1111111100000000
|
|
word: SLICEC.K1.INIT 1111100011110000
|
|
word: SLICEC.K0.INIT 1000000001000000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R29C45:PLC2
|
|
arc: E1_H02E0101 W3_H06E0103
|
|
arc: E1_H02E0401 W3_H06E0203
|
|
arc: E1_H02E0601 V02N0601
|
|
arc: H00L0000 W1_H02E0201
|
|
arc: H00R0000 V02S0401
|
|
arc: N1_V02N0001 N3_V06S0003
|
|
arc: N1_V02N0301 N3_V06S0003
|
|
arc: N1_V02N0401 H01E0001
|
|
arc: N1_V02N0701 E3_H06W0203
|
|
arc: S1_V02S0501 E1_H02W0501
|
|
arc: S1_V02S0701 N1_V02S0701
|
|
arc: V00B0000 S1_V02N0001
|
|
arc: V00T0100 V02S0701
|
|
arc: W1_H02W0401 E1_H02W0401
|
|
arc: W1_H02W0501 E1_H02W0501
|
|
arc: W1_H02W0701 W3_H06E0203
|
|
arc: A1 V02N0501
|
|
arc: A3 V00B0000
|
|
arc: A5 N1_V02S0301
|
|
arc: A7 Q7
|
|
arc: B1 S1_V02N0301
|
|
arc: B2 N1_V02S0301
|
|
arc: B3 Q3
|
|
arc: B5 H02W0301
|
|
arc: C1 E1_H01W0000
|
|
arc: C2 V02N0401
|
|
arc: C3 H00L0100
|
|
arc: C5 E1_H02W0601
|
|
arc: CE0 H00R0100
|
|
arc: CE1 H00R0100
|
|
arc: CE3 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D1 H01E0101
|
|
arc: D2 V02S0001
|
|
arc: D3 S1_V02N0201
|
|
arc: D5 V02N0401
|
|
arc: D7 H00L0100
|
|
arc: E1_H01E0101 F2
|
|
arc: E1_H02E0001 F2
|
|
arc: E1_H02E0201 F0
|
|
arc: E1_H02E0301 Q3
|
|
arc: E1_H02E0501 F7
|
|
arc: F0 F5A_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00L0100 Q1
|
|
arc: H00R0100 F5
|
|
arc: H01W0000 F2
|
|
arc: LSR0 E1_H02W0301
|
|
arc: LSR1 H02W0301
|
|
arc: M0 V00T0100
|
|
arc: M1 H00L0000
|
|
arc: M3 H00R0000
|
|
arc: M7 H02E0201
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR3 LSR1
|
|
arc: N1_V01N0101 Q3
|
|
arc: N1_V02N0101 Q1
|
|
arc: N1_V02N0201 F2
|
|
arc: N1_V02N0501 Q7
|
|
arc: S1_V02S0001 F2
|
|
arc: S1_V02S0201 F2
|
|
arc: V01S0000 Q1
|
|
arc: V01S0100 Q1
|
|
arc: W1_H02W0301 F3
|
|
word: SLICEB.K0.INIT 1100000000000000
|
|
word: SLICEC.K1.INIT 1110110011001100
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 1000010000100001
|
|
word: SLICEB.K1.INIT 1111110001010100
|
|
word: SLICED.K1.INIT 0000000001010101
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
|
|
.tile R29C46:PLC2
|
|
arc: E1_H02E0101 W1_H02E0001
|
|
arc: E1_H02E0401 N1_V01S0000
|
|
arc: E1_H02E0601 W1_H02E0301
|
|
arc: H00L0000 H02E0001
|
|
arc: H00L0100 N1_V02S0101
|
|
arc: H00R0000 W1_H02E0601
|
|
arc: H00R0100 H02E0501
|
|
arc: N1_V02N0001 S1_V02N0501
|
|
arc: N1_V02N0101 H02E0101
|
|
arc: N1_V02N0301 E1_H01W0100
|
|
arc: N1_V02N0401 E1_H01W0000
|
|
arc: N1_V02N0501 S1_V02N0501
|
|
arc: N1_V02N0601 E1_H02W0601
|
|
arc: N1_V02N0701 H06W0203
|
|
arc: N3_V06N0003 S3_V06N0303
|
|
arc: N3_V06N0303 S3_V06N0303
|
|
arc: S1_V02S0001 E1_H01W0000
|
|
arc: S1_V02S0301 E1_H01W0100
|
|
arc: S1_V02S0501 H02W0501
|
|
arc: S1_V02S0601 N1_V02S0301
|
|
arc: V00B0100 V02N0101
|
|
arc: V00T0000 V02N0401
|
|
arc: W1_H02W0101 H01E0101
|
|
arc: W1_H02W0301 V02N0301
|
|
arc: W1_H02W0501 N1_V02S0501
|
|
arc: W1_H02W0601 V06N0303
|
|
arc: W1_H02W0701 E1_H02W0601
|
|
arc: W3_H06W0203 E3_H06W0203
|
|
arc: A0 F5
|
|
arc: A2 F5
|
|
arc: A4 E1_H02W0701
|
|
arc: A5 H02E0501
|
|
arc: A6 S1_V02N0301
|
|
arc: A7 V02S0101
|
|
arc: B2 H01W0100
|
|
arc: B4 V01S0000
|
|
arc: B5 H02E0301
|
|
arc: B6 V02N0501
|
|
arc: B7 E1_H02W0301
|
|
arc: C0 H00R0100
|
|
arc: C2 H00R0100
|
|
arc: C4 H02E0601
|
|
arc: C5 F4
|
|
arc: C6 V00T0100
|
|
arc: C7 V00T0000
|
|
arc: CE1 H00L0000
|
|
arc: CE2 H00L0000
|
|
arc: CE3 H00L0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V01S0100
|
|
arc: D1 V01S0100
|
|
arc: D2 H02E0201
|
|
arc: D3 V01S0100
|
|
arc: D4 V02N0601
|
|
arc: D5 H02W0201
|
|
arc: D6 V00B0000
|
|
arc: D7 E1_H02W0201
|
|
arc: E1_H01E0001 F6
|
|
arc: E1_H01E0101 F1
|
|
arc: F0 F5A_SLICE
|
|
arc: F1 FXA_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 Q6
|
|
arc: H01W0100 F7
|
|
arc: M0 V00B0100
|
|
arc: M1 H00R0000
|
|
arc: M2 V00B0100
|
|
arc: M3 H00L0100
|
|
arc: M4 H02E0401
|
|
arc: M5 H02W0001
|
|
arc: M6 W1_H02E0401
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: V00B0000 Q4
|
|
arc: V00T0100 Q3
|
|
arc: V01S0000 Q5
|
|
arc: V01S0100 F7
|
|
word: SLICEA.K0.INIT 1010111100000000
|
|
word: SLICEA.K1.INIT 1111111100000000
|
|
word: SLICEB.K0.INIT 1000110010001000
|
|
word: SLICEB.K1.INIT 1111111100000000
|
|
word: SLICED.K0.INIT 1000001001000001
|
|
word: SLICEC.K0.INIT 1001000000001001
|
|
word: SLICEC.K1.INIT 1101000000000000
|
|
word: SLICED.K1.INIT 0000000000001000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R29C47:PLC2
|
|
arc: E1_H02E0101 V01N0101
|
|
arc: E1_H02E0301 S3_V06N0003
|
|
arc: H00R0000 H02W0401
|
|
arc: N1_V02N0301 H01E0101
|
|
arc: N1_V02N0601 S3_V06N0303
|
|
arc: N1_V02N0701 S1_V02N0701
|
|
arc: N3_V06N0203 S3_V06N0103
|
|
arc: N3_V06N0303 S3_V06N0203
|
|
arc: S1_V02S0101 H06E0103
|
|
arc: S1_V02S0201 H06E0103
|
|
arc: V00B0100 N1_V02S0301
|
|
arc: V01S0100 S3_V06N0303
|
|
arc: W1_H02W0001 V02N0001
|
|
arc: W1_H02W0201 H01E0001
|
|
arc: W1_H02W0301 V02N0301
|
|
arc: W1_H02W0401 V06N0203
|
|
arc: W1_H02W0601 V02S0601
|
|
arc: W3_H06W0103 S3_V06N0103
|
|
arc: W3_H06W0203 S3_V06N0203
|
|
arc: A0 F7
|
|
arc: B0 H02E0101
|
|
arc: B3 E1_H02W0101
|
|
arc: B5 H02E0101
|
|
arc: B7 S1_V02N0701
|
|
arc: C0 H02W0601
|
|
arc: C2 H02E0401
|
|
arc: C3 N1_V02S0601
|
|
arc: C5 V00T0000
|
|
arc: C7 H02E0601
|
|
arc: CE0 S1_V02N0201
|
|
arc: CE3 S1_V02N0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V00B0100
|
|
arc: D2 V02S0001
|
|
arc: D3 H00R0000
|
|
arc: D5 H00R0100
|
|
arc: E1_H01E0001 F7
|
|
arc: E1_H02E0501 F7
|
|
arc: E1_H02E0701 F5
|
|
arc: E3_H06E0103 F2
|
|
arc: F0 F0_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00R0100 Q7
|
|
arc: H01W0000 Q7
|
|
arc: H01W0100 Q0
|
|
arc: LSR1 V00T0100
|
|
arc: M7 E1_H01W0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR3 LSR1
|
|
arc: N1_V01N0001 F2
|
|
arc: N1_V02N0001 Q0
|
|
arc: N1_V02N0201 F2
|
|
arc: N1_V02N0501 Q7
|
|
arc: N3_V06N0103 F2
|
|
arc: S1_V02S0701 F7
|
|
arc: V00T0000 Q0
|
|
arc: V00T0100 F3
|
|
arc: V01S0000 F7
|
|
arc: W1_H02W0501 F7
|
|
word: SLICEC.K1.INIT 1100110011000000
|
|
word: SLICEB.K0.INIT 1111000000000000
|
|
word: SLICED.K1.INIT 0000001100000011
|
|
word: SLICEB.K1.INIT 1100000000000000
|
|
word: SLICEA.K0.INIT 0000100000000000
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET SET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET SET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R29C48:PLC2
|
|
arc: E1_H02E0001 N1_V02S0001
|
|
arc: H00L0000 N1_V02S0001
|
|
arc: H00L0100 V02N0301
|
|
arc: H00R0000 V02N0401
|
|
arc: N1_V02N0001 E1_H01W0000
|
|
arc: N1_V02N0301 H02E0301
|
|
arc: N1_V02N0401 H06W0203
|
|
arc: N1_V02N0601 H01E0001
|
|
arc: N1_V02N0701 N3_V06S0203
|
|
arc: S1_V02S0001 N1_V02S0001
|
|
arc: S1_V02S0201 H01E0001
|
|
arc: S1_V02S0301 H02E0301
|
|
arc: V00B0000 S1_V02N0201
|
|
arc: V00T0100 V02S0701
|
|
arc: W1_H02W0201 N1_V01S0000
|
|
arc: W1_H02W0301 N1_V01S0100
|
|
arc: W1_H02W0401 V06S0203
|
|
arc: W1_H02W0601 V02N0601
|
|
arc: W1_H02W0701 V02N0701
|
|
arc: A0 H01E0001
|
|
arc: A1 H01E0001
|
|
arc: A5 H02E0701
|
|
arc: B1 V02S0101
|
|
arc: B5 H00R0000
|
|
arc: C0 V02N0601
|
|
arc: C1 V02N0601
|
|
arc: C5 H02W0601
|
|
arc: CE2 H02E0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02S0201
|
|
arc: D1 S1_V02N0001
|
|
arc: D3 S1_V02N0001
|
|
arc: D5 H02W0201
|
|
arc: E1_H01E0001 Q5
|
|
arc: E1_H01E0101 F4
|
|
arc: F0 F5A_SLICE
|
|
arc: F1 FXA_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F4 F5C_SLICE
|
|
arc: H01W0000 F1
|
|
arc: LSR1 V00T0100
|
|
arc: M0 V00B0000
|
|
arc: M1 H00L0000
|
|
arc: M2 V00B0000
|
|
arc: M4 H02W0401
|
|
arc: M5 H00L0100
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR2 LSR1
|
|
arc: V01S0000 Q5
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0001000100010101
|
|
word: SLICEA.K0.INIT 1010000000000000
|
|
word: SLICEA.K1.INIT 1111011110000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 1111111100000000
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET SET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
|
|
.tile R29C49:PLC2
|
|
arc: E1_H01E0001 W3_H06E0003
|
|
arc: E1_H02E0001 W3_H06E0003
|
|
arc: E1_H02E0501 V06N0303
|
|
arc: H00R0100 E1_H02W0501
|
|
arc: N1_V02N0001 H01E0001
|
|
arc: N1_V02N0301 E1_H01W0100
|
|
arc: N1_V02N0701 H01E0101
|
|
arc: V00B0100 V02N0101
|
|
arc: W1_H02W0101 V02S0101
|
|
arc: W1_H02W0401 N1_V01S0000
|
|
arc: A0 W1_H02E0501
|
|
arc: A6 V02S0101
|
|
arc: A7 S1_V02N0101
|
|
arc: B0 N1_V02S0301
|
|
arc: B6 V02S0701
|
|
arc: B7 S1_V02N0501
|
|
arc: C0 V02N0601
|
|
arc: C4 V00T0000
|
|
arc: C6 H02W0601
|
|
arc: C7 V00T0000
|
|
arc: CE0 S1_V02N0201
|
|
arc: CE2 S1_V02N0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H02E0001
|
|
arc: D4 V00B0000
|
|
arc: D6 H00R0100
|
|
arc: D7 V00B0000
|
|
arc: E1_H01E0101 F6
|
|
arc: F0 F0_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 F4
|
|
arc: LSR0 H02W0301
|
|
arc: M4 V00B0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR2 LSR0
|
|
arc: S1_V02S0501 F7
|
|
arc: V00B0000 Q4
|
|
arc: V00T0000 Q0
|
|
arc: W1_H02W0201 Q0
|
|
arc: W1_H02W0601 Q4
|
|
arc: W3_H06W0203 F4
|
|
word: SLICEC.K0.INIT 0000111100000000
|
|
word: SLICED.K0.INIT 0000100000000000
|
|
word: SLICEA.K0.INIT 0000100000000000
|
|
word: SLICED.K1.INIT 0000000000100000
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET SET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET SET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R29C50:PLC2
|
|
arc: E3_H06E0203 H01E0001
|
|
arc: H00L0000 H02E0001
|
|
arc: H00L0100 V02S0101
|
|
arc: H00R0000 V02S0401
|
|
arc: H00R0100 V02N0501
|
|
arc: H01W0100 W3_H06E0303
|
|
arc: N1_V02N0101 H06E0103
|
|
arc: N1_V02N0201 N1_V01S0000
|
|
arc: N1_V02N0301 S3_V06N0003
|
|
arc: N1_V02N0501 H02E0501
|
|
arc: S1_V02S0101 E1_H01W0100
|
|
arc: S1_V02S0601 H06W0303
|
|
arc: V00B0000 V02S0201
|
|
arc: V00B0100 N1_V02S0101
|
|
arc: W1_H02W0301 H01E0101
|
|
arc: W1_H02W0601 N1_V02S0601
|
|
arc: A1 S1_V02N0701
|
|
arc: B1 Q1
|
|
arc: C1 H00L0100
|
|
arc: CE0 H00R0100
|
|
arc: CE2 S1_V02N0601
|
|
arc: CE3 S1_V02N0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D1 V01S0100
|
|
arc: E1_H01E0101 Q7
|
|
arc: E1_H02E0401 Q6
|
|
arc: F1 F1_SLICE
|
|
arc: M0 V00B0100
|
|
arc: M1 E1_H02W0001
|
|
arc: M5 H00R0000
|
|
arc: M6 V00B0000
|
|
arc: M7 H00L0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0101 F1
|
|
arc: V01S0000 Q5
|
|
arc: V01S0100 Q0
|
|
word: SLICEA.K1.INIT 1001000000001001
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R29C51:PLC2
|
|
arc: N1_V02N0501 V01N0101
|
|
arc: N1_V02N0601 V01N0001
|
|
arc: N3_V06N0203 S1_V02N0401
|
|
arc: S1_V02S0501 N1_V02S0501
|
|
arc: V00B0100 V02N0301
|
|
arc: A0 V02S0501
|
|
arc: A3 N1_V02S0701
|
|
arc: A6 N1_V02S0101
|
|
arc: B0 V01N0001
|
|
arc: B3 V02S0301
|
|
arc: B4 N1_V01S0000
|
|
arc: B6 V02S0701
|
|
arc: B7 E1_H02W0101
|
|
arc: C0 S1_V02N0601
|
|
arc: C2 V02N0401
|
|
arc: C3 F4
|
|
arc: C6 H02E0401
|
|
arc: C7 V02N0001
|
|
arc: CE0 H00L0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02N0201
|
|
arc: D2 V02N0201
|
|
arc: D3 H01E0101
|
|
arc: D4 V02S0401
|
|
arc: D6 V02N0601
|
|
arc: D7 V02N0401
|
|
arc: E1_H01E0001 F7
|
|
arc: F0 F0_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00L0000 F2
|
|
arc: H01W0100 F4
|
|
arc: LSR0 V00B0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: N1_V01N0101 Q0
|
|
arc: N1_V02N0001 Q0
|
|
arc: N1_V02N0201 Q0
|
|
arc: S1_V02S0201 F2
|
|
arc: V01S0000 F3
|
|
arc: V01S0100 F6
|
|
arc: W1_H02W0501 F7
|
|
arc: W3_H06W0203 F7
|
|
word: SLICEA.K0.INIT 0110101000000000
|
|
word: SLICEB.K0.INIT 1111111111110000
|
|
word: SLICED.K1.INIT 0000000011000000
|
|
word: SLICEB.K1.INIT 1000101001000101
|
|
word: SLICEC.K0.INIT 0000000000110011
|
|
word: SLICED.K0.INIT 1010010100100001
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
|
|
.tile R29C52:PLC2
|
|
arc: N1_V02N0201 H01E0001
|
|
arc: S1_V02S0201 N1_V02S0701
|
|
arc: W1_H02W0001 S1_V02N0001
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
|
|
.tile R29C53:PLC2
|
|
arc: N1_V02N0101 S1_V02N0001
|
|
arc: N1_V02N0301 S1_V02N0201
|
|
arc: N1_V02N0401 S3_V06N0203
|
|
arc: N1_V02N0601 S1_V02N0301
|
|
arc: N1_V02N0701 H06E0203
|
|
arc: N3_V06N0103 S3_V06N0003
|
|
arc: N3_V06N0203 S3_V06N0103
|
|
arc: V01S0000 S3_V06N0103
|
|
arc: W1_H02W0101 N1_V01S0100
|
|
arc: W3_H06W0303 S3_V06N0303
|
|
|
|
.tile R29C58:PLC2
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
|
|
.tile R29C59:PLC2
|
|
arc: N1_V02N0001 S1_V02N0501
|
|
arc: N1_V02N0201 N3_V06S0103
|
|
arc: N1_V02N0301 S1_V02N0201
|
|
|
|
.tile R29C5:PLC2
|
|
arc: W1_H02W0501 V06S0303
|
|
|
|
.tile R29C62:PLC2
|
|
arc: N1_V02N0001 H06W0003
|
|
|
|
.tile R29C64:PLC2
|
|
arc: N1_V02N0301 S3_V06N0003
|
|
arc: N1_V02N0501 S1_V02N0501
|
|
arc: N1_V02N0701 H02W0701
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
|
|
.tile R29C65:PLC2
|
|
arc: N1_V02N0001 E3_H06W0003
|
|
arc: N1_V02N0501 S1_V02N0401
|
|
arc: W1_H02W0701 S3_V06N0203
|
|
arc: W3_H06W0003 S3_V06N0003
|
|
|
|
.tile R29C70:PLC2
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
|
|
.tile R29C71:PLC2
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
|
|
.tile R29C76:PLC2
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
|
|
.tile R29C77:PLC2
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
|
|
.tile R29C7:PLC2
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: E3_H06E0103 N1_V01S0100
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
|
|
.tile R29C82:PLC2
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
|
|
.tile R29C83:PLC2
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
|
|
.tile R29C87:PLC2
|
|
arc: E1_H02E0501 N1_V02S0501
|
|
|
|
.tile R29C88:PLC2
|
|
arc: W3_H06W0303 E1_H01W0100
|
|
|
|
.tile R2C34:PLC2
|
|
arc: N1_V02N0501 S3_V06N0303
|
|
|
|
.tile R2C35:PLC2
|
|
arc: N1_V02N0701 S3_V06N0203
|
|
|
|
.tile R2C77:PLC2
|
|
arc: N1_V02N0501 S3_V06N0303
|
|
|
|
.tile R2C83:PLC2
|
|
arc: N1_V02N0701 S3_V06N0203
|
|
|
|
.tile R30C13:PLC2
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
|
|
.tile R30C19:PLC2
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
|
|
.tile R30C25:PLC2
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
arc: N1_V02N0101 S3_V06N0103
|
|
|
|
.tile R30C31:PLC2
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
|
|
.tile R30C34:PLC2
|
|
arc: N1_V02N0301 S3_V06N0003
|
|
|
|
.tile R30C37:PLC2
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
arc: N3_V06N0303 S3_V06N0203
|
|
|
|
.tile R30C38:PLC2
|
|
arc: N1_V02N0201 S1_V02N0201
|
|
arc: N1_V02N0601 H06W0303
|
|
|
|
.tile R30C39:PLC2
|
|
arc: E1_H02E0001 V06S0003
|
|
arc: E1_H02E0101 V02N0101
|
|
arc: E1_H02E0201 V01N0001
|
|
arc: E1_H02E0401 S1_V02N0401
|
|
arc: E1_H02E0501 V02N0501
|
|
arc: E1_H02E0601 V02N0601
|
|
arc: N1_V02N0301 E1_H01W0100
|
|
arc: N1_V02N0601 E1_H01W0000
|
|
arc: S1_V02S0601 E1_H01W0000
|
|
arc: V00T0100 V02N0701
|
|
arc: A2 V00T0000
|
|
arc: B0 V00T0000
|
|
arc: B2 H01W0100
|
|
arc: B7 N1_V01S0000
|
|
arc: C0 H00L0100
|
|
arc: C1 H00L0100
|
|
arc: C2 N1_V01S0100
|
|
arc: CE0 H00R0100
|
|
arc: CE1 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 N1_V01S0000
|
|
arc: D1 N1_V01S0000
|
|
arc: D2 Q2
|
|
arc: D7 H02W0001
|
|
arc: E1_H01E0001 Q0
|
|
arc: E1_H01E0101 Q1
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00L0100 Q1
|
|
arc: H00R0100 F7
|
|
arc: H01W0100 Q1
|
|
arc: LSR0 V00T0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR0
|
|
arc: N1_V01N0101 Q0
|
|
arc: N1_V02N0101 Q1
|
|
arc: N1_V02N0201 Q2
|
|
arc: V00T0000 Q0
|
|
word: SLICEB.K0.INIT 0111000010000000
|
|
word: SLICEA.K0.INIT 0011110000000000
|
|
word: SLICEA.K1.INIT 0000111100000000
|
|
word: SLICED.K1.INIT 1111111111001100
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R30C40:PLC2
|
|
arc: H00L0100 S1_V02N0301
|
|
arc: H00R0000 V02N0401
|
|
arc: H00R0100 H02W0701
|
|
arc: N1_V02N0001 H02E0001
|
|
arc: N1_V02N0101 S1_V02N0101
|
|
arc: N1_V02N0301 H01E0101
|
|
arc: N1_V02N0401 H01E0001
|
|
arc: N1_V02N0601 S3_V06N0303
|
|
arc: N3_V06N0003 S3_V06N0303
|
|
arc: S1_V02S0101 H02E0101
|
|
arc: V00B0000 N1_V02S0201
|
|
arc: V00B0100 V02N0301
|
|
arc: V00T0000 V02N0601
|
|
arc: W1_H02W0001 V02N0001
|
|
arc: A1 H02E0501
|
|
arc: A5 V00B0000
|
|
arc: B1 V02N0101
|
|
arc: C1 S1_V02N0601
|
|
arc: C5 N1_V02S0001
|
|
arc: CE0 V02S0201
|
|
arc: CE1 H00R0100
|
|
arc: CE2 H00R0100
|
|
arc: CE3 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D1 N1_V01S0000
|
|
arc: D5 E1_H02W0001
|
|
arc: E1_H01E0001 Q7
|
|
arc: E1_H02E0401 Q6
|
|
arc: E1_H02E0501 F5
|
|
arc: E1_H02E0601 Q6
|
|
arc: F0 F5A_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: H01W0000 F5
|
|
arc: H01W0100 F0
|
|
arc: M0 V00B0100
|
|
arc: M1 H00L0100
|
|
arc: M2 V00T0000
|
|
arc: M5 H00R0000
|
|
arc: M6 H02E0401
|
|
arc: M7 H00L0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 F5
|
|
arc: N1_V01N0101 F5
|
|
arc: N1_V02N0201 Q2
|
|
arc: N1_V02N0501 Q5
|
|
arc: S1_V02S0501 F5
|
|
arc: S1_V02S0701 F5
|
|
arc: V01S0000 Q1
|
|
word: SLICEC.K1.INIT 1010000000000000
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000001001
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R30C41:PLC2
|
|
arc: E1_H02E0501 S1_V02N0501
|
|
arc: H00R0000 W1_H02E0601
|
|
arc: H00R0100 N1_V02S0501
|
|
arc: N1_V02N0201 S1_V02N0701
|
|
arc: N1_V02N0501 H02W0501
|
|
arc: N1_V02N0601 H02E0601
|
|
arc: N1_V02N0701 V01N0101
|
|
arc: N3_V06N0103 E3_H06W0103
|
|
arc: N3_V06N0203 S1_V02N0401
|
|
arc: N3_V06N0303 S1_V02N0601
|
|
arc: S1_V02S0101 H06W0103
|
|
arc: S1_V02S0201 N1_V02S0701
|
|
arc: V00B0000 W1_H02E0601
|
|
arc: W1_H02W0701 N1_V02S0701
|
|
arc: W3_H06W0303 S3_V06N0303
|
|
arc: A2 V02N0501
|
|
arc: A5 H02W0501
|
|
arc: A6 H02W0501
|
|
arc: B2 E1_H02W0301
|
|
arc: B5 H00R0000
|
|
arc: B6 V00B0000
|
|
arc: C2 E1_H02W0401
|
|
arc: C5 H01E0001
|
|
arc: C6 H02E0401
|
|
arc: D2 W1_H02E0201
|
|
arc: D5 H00R0100
|
|
arc: D6 N1_V02S0601
|
|
arc: E1_H01E0001 F2
|
|
arc: F2 F2_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: N1_V01N0101 F5
|
|
arc: N1_V02N0401 F6
|
|
word: SLICED.K0.INIT 1000010000100001
|
|
word: SLICEC.K1.INIT 1000010000100001
|
|
word: SLICEB.K0.INIT 1000101000000000
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
|
|
.tile R30C42:PLC2
|
|
arc: E1_H02E0501 W1_H02E0501
|
|
arc: N1_V02N0001 H01E0001
|
|
arc: N1_V02N0101 H02W0101
|
|
arc: N1_V02N0501 S1_V02N0501
|
|
arc: N3_V06N0303 S1_V02N0501
|
|
arc: W1_H02W0001 V06S0003
|
|
arc: W1_H02W0501 V02N0501
|
|
arc: A0 E1_H01E0001
|
|
arc: B1 Q1
|
|
arc: B3 H02W0101
|
|
arc: C0 H00L0000
|
|
arc: CE0 H00L0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02S0201
|
|
arc: D1 V02S0201
|
|
arc: D3 V02S0201
|
|
arc: E1_H01E0001 Q1
|
|
arc: E1_H02E0101 F3
|
|
arc: E1_H02E0201 Q0
|
|
arc: E1_H02E0301 Q1
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: H00L0000 Q0
|
|
arc: H00L0100 F3
|
|
arc: LSR1 W1_H02E0501
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
word: SLICEA.K0.INIT 0101101000000000
|
|
word: SLICEA.K1.INIT 0011001100000000
|
|
word: SLICEB.K1.INIT 1111111111001100
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R30C43:PLC2
|
|
arc: E1_H02E0001 W1_H02E0501
|
|
arc: E1_H02E0301 V06S0003
|
|
arc: E1_H02E0401 W3_H06E0203
|
|
arc: E1_H02E0701 S1_V02N0701
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: H00L0000 H02E0201
|
|
arc: N1_V02N0101 S1_V02N0101
|
|
arc: N3_V06N0103 S1_V02N0101
|
|
arc: S1_V02S0001 E1_H01W0000
|
|
arc: S1_V02S0701 V01N0101
|
|
arc: W1_H02W0101 S1_V02N0101
|
|
arc: W1_H02W0301 N1_V01S0100
|
|
arc: A0 V02N0501
|
|
arc: A2 V00T0000
|
|
arc: A3 V00T0000
|
|
arc: A5 N1_V01S0100
|
|
arc: B0 H02E0301
|
|
arc: B2 H02E0301
|
|
arc: B3 H02E0301
|
|
arc: B5 H02W0301
|
|
arc: B6 H02W0301
|
|
arc: C0 H00L0000
|
|
arc: C2 H00L0000
|
|
arc: C3 H00L0000
|
|
arc: C5 H01E0001
|
|
arc: CE0 H02E0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 N1_V01S0000
|
|
arc: D2 H02W0001
|
|
arc: D3 H02W0201
|
|
arc: D5 H02E0201
|
|
arc: D6 H02W0201
|
|
arc: E1_H01E0001 F2
|
|
arc: E1_H01E0101 F2
|
|
arc: F0 F0_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: LSR1 H02E0501
|
|
arc: M2 V00B0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: N1_V01N0001 F6
|
|
arc: N1_V02N0401 F6
|
|
arc: V00B0100 F5
|
|
arc: V00T0000 Q0
|
|
arc: V01S0100 Q0
|
|
arc: W1_H02W0401 F6
|
|
word: SLICED.K0.INIT 0000000000110011
|
|
word: SLICEA.K0.INIT 0110101000000000
|
|
word: SLICEC.K1.INIT 1110000010001100
|
|
word: SLICEB.K1.INIT 0000000001101010
|
|
word: SLICEB.K0.INIT 0110101011111111
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
|
|
.tile R30C44:PLC2
|
|
arc: E1_H02E0001 N1_V02S0001
|
|
arc: E1_H02E0201 V02N0201
|
|
arc: E1_H02E0401 E1_H01W0000
|
|
arc: E1_H02E0601 V02S0601
|
|
arc: H00L0000 N1_V02S0201
|
|
arc: H00L0100 N1_V02S0301
|
|
arc: H00R0100 V02S0701
|
|
arc: N1_V02N0001 H01E0001
|
|
arc: N1_V02N0101 H02W0101
|
|
arc: N1_V02N0201 H01E0001
|
|
arc: N1_V02N0301 H01E0101
|
|
arc: S1_V02S0001 H06W0003
|
|
arc: S1_V02S0101 N1_V01S0100
|
|
arc: S1_V02S0401 H06W0203
|
|
arc: V00B0100 H02W0501
|
|
arc: A0 H02W0701
|
|
arc: A5 V02S0101
|
|
arc: B0 E1_H01W0100
|
|
arc: B5 H02E0301
|
|
arc: C0 N1_V02S0601
|
|
arc: C3 V02N0401
|
|
arc: C5 N1_V02S0001
|
|
arc: CE0 V02S0201
|
|
arc: CE1 V02S0201
|
|
arc: CE3 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 N1_V01S0000
|
|
arc: D3 V00B0100
|
|
arc: D5 H02W0001
|
|
arc: F0 F5A_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: H01W0000 Q7
|
|
arc: LSR0 H02W0301
|
|
arc: LSR1 H02W0301
|
|
arc: M0 V00T0100
|
|
arc: M1 H00L0100
|
|
arc: M2 H02W0601
|
|
arc: M7 H00L0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR3 LSR0
|
|
arc: N1_V01N0001 F5
|
|
arc: N1_V01N0101 F0
|
|
arc: S1_V02S0701 Q7
|
|
arc: V00T0100 F3
|
|
arc: V01S0000 Q2
|
|
arc: V01S0100 Q7
|
|
arc: W1_H02W0001 Q2
|
|
arc: W1_H02W0201 Q2
|
|
arc: W1_H02W0301 Q1
|
|
arc: W3_H06W0103 Q2
|
|
word: SLICEC.K1.INIT 1110101010101010
|
|
word: SLICEB.K1.INIT 0000111100000000
|
|
word: SLICEA.K0.INIT 1001000000001001
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
|
|
.tile R30C45:PLC2
|
|
arc: E1_H02E0001 V06S0003
|
|
arc: E1_H02E0401 V02N0401
|
|
arc: E1_H02E0501 V02N0501
|
|
arc: H00L0000 V02S0001
|
|
arc: H00R0100 W1_H02E0701
|
|
arc: N1_V02N0401 E1_H02W0401
|
|
arc: N1_V02N0501 S1_V02N0501
|
|
arc: N1_V02N0601 S1_V02N0301
|
|
arc: N1_V02N0701 N1_V01S0100
|
|
arc: S1_V02S0001 E1_H01W0000
|
|
arc: S1_V02S0401 E1_H02W0401
|
|
arc: V00B0100 E1_H02W0501
|
|
arc: V00T0100 V02S0701
|
|
arc: W1_H02W0001 V06S0003
|
|
arc: W1_H02W0101 V02N0101
|
|
arc: W1_H02W0301 E1_H02W0201
|
|
arc: W1_H02W0601 E1_H02W0301
|
|
arc: W1_H02W0701 S1_V02N0701
|
|
arc: A0 S1_V02N0501
|
|
arc: A2 V00B0000
|
|
arc: A5 Q5
|
|
arc: A6 F5
|
|
arc: A7 V02N0101
|
|
arc: B2 S1_V02N0101
|
|
arc: B5 H00R0000
|
|
arc: B6 V02N0701
|
|
arc: B7 V02N0501
|
|
arc: C0 N1_V01N0001
|
|
arc: C2 V02N0601
|
|
arc: C5 V02N0001
|
|
arc: C6 V00T0000
|
|
arc: C7 H02E0401
|
|
arc: CE0 V02S0201
|
|
arc: CE1 V02S0201
|
|
arc: CE2 H00L0000
|
|
arc: CE3 H00L0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 N1_V01S0000
|
|
arc: D2 Q2
|
|
arc: D5 V01N0001
|
|
arc: D6 F2
|
|
arc: D7 H00L0100
|
|
arc: E1_H01E0001 Q4
|
|
arc: E1_H01E0101 F6
|
|
arc: F0 F0_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00L0100 Q1
|
|
arc: H00R0000 Q6
|
|
arc: H01W0000 Q5
|
|
arc: H01W0100 Q0
|
|
arc: M0 V00T0100
|
|
arc: M1 W1_H02E0001
|
|
arc: M2 H02E0601
|
|
arc: M4 W1_H02E0401
|
|
arc: M5 H00R0100
|
|
arc: M6 V00B0100
|
|
arc: M7 H02E0201
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q2
|
|
arc: V00B0000 Q6
|
|
arc: V00T0000 F0
|
|
arc: V01S0000 Q7
|
|
arc: V01S0100 F7
|
|
arc: W1_H02W0501 Q7
|
|
word: SLICEC.K1.INIT 1111001101010001
|
|
word: SLICEB.K0.INIT 1011000010111011
|
|
word: SLICED.K1.INIT 1100010000110001
|
|
word: SLICEA.K0.INIT 1111010100000000
|
|
word: SLICED.K0.INIT 1000000000000000
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R30C46:PLC2
|
|
arc: E1_H02E0001 W1_H02E0001
|
|
arc: E1_H02E0301 S1_V02N0301
|
|
arc: E1_H02E0701 S1_V02N0701
|
|
arc: H00L0000 N1_V02S0001
|
|
arc: H00L0100 S1_V02N0301
|
|
arc: H00R0000 V02S0601
|
|
arc: N1_V02N0101 H01E0101
|
|
arc: N1_V02N0301 S1_V02N0301
|
|
arc: N1_V02N0401 S1_V02N0101
|
|
arc: N1_V02N0501 S1_V02N0501
|
|
arc: N1_V02N0601 H01E0001
|
|
arc: N3_V06N0003 S1_V02N0301
|
|
arc: N3_V06N0303 S3_V06N0303
|
|
arc: S1_V02S0001 W1_H02E0001
|
|
arc: A1 H02E0501
|
|
arc: A2 H00L0100
|
|
arc: B1 Q1
|
|
arc: B2 V02S0301
|
|
arc: C1 V02N0401
|
|
arc: C2 V02N0601
|
|
arc: CE0 V02N0201
|
|
arc: CE1 V02N0201
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D1 V00T0100
|
|
arc: D2 V02S0001
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: H01W0000 Q3
|
|
arc: M1 H00L0000
|
|
arc: M3 H00R0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: V00T0100 Q3
|
|
arc: V01S0000 F1
|
|
arc: V01S0100 F2
|
|
word: SLICEB.K0.INIT 0000000001000000
|
|
word: SLICEA.K1.INIT 1001000010011001
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R30C47:PLC2
|
|
arc: E1_H02E0001 W1_H02E0001
|
|
arc: E1_H02E0101 V02S0101
|
|
arc: E1_H02E0401 N3_V06S0203
|
|
arc: E1_H02E0601 N1_V01S0000
|
|
arc: E3_H06E0203 N3_V06S0203
|
|
arc: H00L0000 S1_V02N0201
|
|
arc: N1_V02N0001 S1_V02N0501
|
|
arc: N1_V02N0201 N1_V01S0000
|
|
arc: N1_V02N0301 S1_V02N0201
|
|
arc: N1_V02N0401 N1_V01S0000
|
|
arc: N1_V02N0601 N1_V01S0000
|
|
arc: N1_V02N0701 S1_V02N0701
|
|
arc: N3_V06N0203 S1_V02N0401
|
|
arc: V00B0000 V02S0201
|
|
arc: V00B0100 V02N0101
|
|
arc: W1_H02W0201 E1_H02W0201
|
|
arc: W1_H02W0301 E3_H06W0003
|
|
arc: W1_H02W0401 N1_V01S0000
|
|
arc: W1_H02W0501 N1_V01S0100
|
|
arc: W3_H06W0003 E1_H01W0000
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
arc: W3_H06W0203 E1_H01W0000
|
|
arc: A0 V02S0701
|
|
arc: A1 V02S0701
|
|
arc: A5 S1_V02N0301
|
|
arc: B0 H02E0301
|
|
arc: B1 H02W0101
|
|
arc: B3 H02E0301
|
|
arc: B4 N1_V01S0000
|
|
arc: B5 N1_V01S0000
|
|
arc: B7 S1_V02N0701
|
|
arc: C1 H00L0000
|
|
arc: C4 S1_V02N0201
|
|
arc: C5 V02S0201
|
|
arc: C6 S1_V02N0201
|
|
arc: D0 H02E0001
|
|
arc: D1 V02N0001
|
|
arc: D2 E1_H02W0201
|
|
arc: D3 V02N0001
|
|
arc: D4 V00B0000
|
|
arc: D5 V02N0401
|
|
arc: D7 V02N0401
|
|
arc: E1_H02E0701 F5
|
|
arc: F0 F5A_SLICE
|
|
arc: F1 FXA_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F4 F5C_SLICE
|
|
arc: F5 FXC_SLICE
|
|
arc: F6 F5D_SLICE
|
|
arc: M0 V00B0100
|
|
arc: M1 W1_H02E0001
|
|
arc: M2 V00B0100
|
|
arc: M4 W1_H02E0401
|
|
arc: M5 W1_H02E0001
|
|
arc: M6 W1_H02E0401
|
|
arc: N1_V01N0101 F5
|
|
arc: V01S0000 F1
|
|
word: SLICEC.K0.INIT 1111110011110000
|
|
word: SLICEC.K1.INIT 1111111111101010
|
|
word: SLICED.K0.INIT 1111000011110000
|
|
word: SLICED.K1.INIT 1111111111001100
|
|
word: SLICEA.K0.INIT 1110111011001100
|
|
word: SLICEA.K1.INIT 1111111111111000
|
|
word: SLICEB.K0.INIT 1111111100000000
|
|
word: SLICEB.K1.INIT 1111111111001100
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
|
|
.tile R30C48:PLC2
|
|
arc: E1_H02E0201 W1_H02E0701
|
|
arc: E1_H02E0501 N3_V06S0303
|
|
arc: E1_H02E0601 N3_V06S0303
|
|
arc: H00L0100 H02E0101
|
|
arc: H00R0100 H02W0501
|
|
arc: N1_V02N0001 N1_V01S0000
|
|
arc: N1_V02N0401 H02E0401
|
|
arc: N1_V02N0501 S1_V02N0501
|
|
arc: N1_V02N0601 N3_V06S0303
|
|
arc: N1_V02N0701 W1_H02E0701
|
|
arc: N3_V06N0103 S1_V02N0101
|
|
arc: S1_V02S0001 N3_V06S0003
|
|
arc: S1_V02S0401 H02E0401
|
|
arc: V00B0000 V02S0201
|
|
arc: V00B0100 V02N0301
|
|
arc: V01S0100 N3_V06S0303
|
|
arc: W1_H02W0101 N1_V02S0101
|
|
arc: A1 H00L0100
|
|
arc: A4 V02N0101
|
|
arc: B0 H02E0101
|
|
arc: B1 V00B0000
|
|
arc: B4 N1_V01S0000
|
|
arc: C0 H02E0601
|
|
arc: C1 V02N0401
|
|
arc: C3 V02N0401
|
|
arc: C4 H02W0401
|
|
arc: CE2 S1_V02N0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V01S0100
|
|
arc: D1 V01S0100
|
|
arc: D4 S1_V02N0401
|
|
arc: F0 F5A_SLICE
|
|
arc: F1 FXA_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: H01W0000 F4
|
|
arc: M0 V00B0100
|
|
arc: M1 H02E0001
|
|
arc: M2 V00B0100
|
|
arc: M5 H00R0100
|
|
arc: MUXCLK2 CLK0
|
|
arc: N1_V02N0301 F1
|
|
arc: V01S0000 Q5
|
|
word: SLICEA.K0.INIT 1100000000000000
|
|
word: SLICEA.K1.INIT 1111100011110000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 1111000011110000
|
|
word: SLICEC.K0.INIT 0000000000100000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R30C49:PLC2
|
|
arc: E1_H02E0001 V01N0001
|
|
arc: E1_H02E0101 V01N0101
|
|
arc: E1_H02E0401 W1_H02E0401
|
|
arc: E1_H02E0501 W1_H02E0401
|
|
arc: E1_H02E0701 S1_V02N0701
|
|
arc: H00R0000 W1_H02E0401
|
|
arc: H00R0100 S1_V02N0701
|
|
arc: N1_V02N0001 W3_H06E0003
|
|
arc: N1_V02N0201 S1_V02N0201
|
|
arc: N1_V02N0301 E1_H01W0100
|
|
arc: N1_V02N0401 W1_H02E0401
|
|
arc: N1_V02N0501 H02E0501
|
|
arc: N1_V02N0601 H02E0601
|
|
arc: N1_V02N0701 W1_H02E0701
|
|
arc: N3_V06N0103 S1_V02N0101
|
|
arc: N3_V06N0203 S1_V02N0701
|
|
arc: N3_V06N0303 S3_V06N0303
|
|
arc: S1_V02S0701 N1_V02S0601
|
|
arc: V00B0000 V02N0001
|
|
arc: V00T0000 N1_V02S0601
|
|
arc: V01S0100 S3_V06N0303
|
|
arc: W1_H02W0201 S1_V02N0201
|
|
arc: W1_H02W0401 N1_V02S0401
|
|
arc: W1_H02W0501 V01N0101
|
|
arc: A1 H02E0501
|
|
arc: A4 V00T0000
|
|
arc: A5 V00T0000
|
|
arc: B0 V00T0000
|
|
arc: B1 V00T0000
|
|
arc: B5 S1_V02N0701
|
|
arc: B7 S1_V02N0701
|
|
arc: C0 H02E0601
|
|
arc: C1 V02N0401
|
|
arc: C3 V02N0401
|
|
arc: C4 W1_H02E0401
|
|
arc: C5 W1_H02E0401
|
|
arc: D0 H00R0000
|
|
arc: D1 H00R0000
|
|
arc: D4 H00R0100
|
|
arc: D5 V02N0401
|
|
arc: D6 H00R0100
|
|
arc: D7 V02N0401
|
|
arc: F0 F5A_SLICE
|
|
arc: F1 FXA_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F4 F5C_SLICE
|
|
arc: F5 FXC_SLICE
|
|
arc: F6 F5D_SLICE
|
|
arc: M0 V00B0000
|
|
arc: M1 E1_H02W0001
|
|
arc: M2 V00B0000
|
|
arc: M4 H02W0401
|
|
arc: M5 E1_H02W0001
|
|
arc: M6 V00B0000
|
|
arc: N1_V02N0101 F1
|
|
arc: V01S0000 F5
|
|
word: SLICEA.K0.INIT 1100000000000000
|
|
word: SLICEA.K1.INIT 1111100011110000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 1111000011110000
|
|
word: SLICEC.K0.INIT 1111111110100000
|
|
word: SLICEC.K1.INIT 1111111111101100
|
|
word: SLICED.K0.INIT 1111111100000000
|
|
word: SLICED.K1.INIT 1111111111001100
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
|
|
.tile R30C50:PLC2
|
|
arc: H00L0100 H02E0101
|
|
arc: H00R0000 N1_V02S0601
|
|
arc: N1_V02N0701 H06E0203
|
|
arc: S1_V02S0601 N1_V02S0301
|
|
arc: V00T0000 V02S0601
|
|
arc: V00T0100 N1_V02S0501
|
|
arc: W1_H02W0401 V02N0401
|
|
arc: A0 S1_V02N0701
|
|
arc: A3 H02W0701
|
|
arc: A4 H02W0701
|
|
arc: A5 H02W0501
|
|
arc: A6 V02N0101
|
|
arc: B0 V02S0101
|
|
arc: B1 E1_H01W0100
|
|
arc: B3 Q3
|
|
arc: B4 H02W0101
|
|
arc: B5 H00L0000
|
|
arc: B6 N1_V01S0000
|
|
arc: B7 N1_V02S0701
|
|
arc: C0 H02W0601
|
|
arc: C1 N1_V02S0601
|
|
arc: C3 N1_V01N0001
|
|
arc: C4 S1_V02N0201
|
|
arc: C5 F6
|
|
arc: C6 Q6
|
|
arc: C7 H02E0401
|
|
arc: CE0 H00R0100
|
|
arc: CE1 H00R0100
|
|
arc: CE2 H00R0100
|
|
arc: CE3 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H00R0000
|
|
arc: D1 V02N0201
|
|
arc: D3 W1_H02E0201
|
|
arc: D4 H01W0000
|
|
arc: D5 V00B0000
|
|
arc: D6 W1_H02E0201
|
|
arc: D7 H02W0001
|
|
arc: E1_H01E0001 F7
|
|
arc: E1_H01E0101 F7
|
|
arc: E1_H02E0201 F0
|
|
arc: E1_H02E0501 F7
|
|
arc: E1_H02E0601 Q4
|
|
arc: E1_H02E0701 Q5
|
|
arc: F0 F5A_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00L0000 F2
|
|
arc: H00R0100 F7
|
|
arc: H01W0000 Q4
|
|
arc: H01W0100 F0
|
|
arc: M0 V00B0100
|
|
arc: M1 H00L0100
|
|
arc: M2 V00T0100
|
|
arc: M3 E1_H02W0201
|
|
arc: M4 E1_H02W0401
|
|
arc: M5 H02E0001
|
|
arc: M6 V00T0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q1
|
|
arc: N1_V02N0201 F0
|
|
arc: N1_V02N0501 F7
|
|
arc: S1_V02S0501 F7
|
|
arc: V00B0000 F4
|
|
arc: V00B0100 F5
|
|
arc: V01S0000 F7
|
|
word: SLICED.K1.INIT 1100000000000000
|
|
word: SLICEA.K0.INIT 1111101100000000
|
|
word: SLICEA.K1.INIT 1111000011000000
|
|
word: SLICEC.K1.INIT 0001001100110011
|
|
word: SLICEC.K0.INIT 1010100011111100
|
|
word: SLICED.K0.INIT 1000010000100001
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 1001000000001001
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R30C51:PLC2
|
|
arc: E1_H02E0101 W1_H02E0001
|
|
arc: H00R0100 H02E0701
|
|
arc: N1_V02N0001 S1_V02N0001
|
|
arc: N1_V02N0201 H02E0201
|
|
arc: N1_V02N0301 H01E0101
|
|
arc: N1_V02N0401 S1_V02N0401
|
|
arc: N1_V02N0501 W1_H02E0501
|
|
arc: N1_V02N0601 H02E0601
|
|
arc: N1_V02N0701 W1_H02E0701
|
|
arc: S1_V02S0001 N1_V02S0001
|
|
arc: S1_V02S0201 H01E0001
|
|
arc: S1_V02S0601 H01E0001
|
|
arc: W1_H02W0001 V06S0003
|
|
arc: W1_H02W0101 N1_V02S0101
|
|
arc: W1_H02W0501 N1_V01S0100
|
|
arc: W1_H02W0701 N1_V02S0701
|
|
arc: A4 S1_V02N0101
|
|
arc: A6 V02N0101
|
|
arc: B1 Q1
|
|
arc: B4 V02S0501
|
|
arc: B6 N1_V01S0000
|
|
arc: C0 N1_V01N0001
|
|
arc: C1 N1_V01N0001
|
|
arc: C4 V02N0001
|
|
arc: C6 F4
|
|
arc: CE0 V02S0201
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H02E0201
|
|
arc: D1 H02E0201
|
|
arc: D4 V01N0001
|
|
arc: D6 H00R0100
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: H01W0100 F6
|
|
arc: LSR1 H02E0501
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: N1_V01N0001 Q0
|
|
arc: N1_V01N0101 Q0
|
|
arc: N1_V02N0101 Q1
|
|
arc: V01S0000 Q1
|
|
arc: W1_H02W0601 F6
|
|
word: SLICEA.K0.INIT 0000111100000000
|
|
word: SLICEA.K1.INIT 0011110000000000
|
|
word: SLICEC.K0.INIT 1000010000100001
|
|
word: SLICED.K0.INIT 1000000001000000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
|
|
.tile R30C52:PLC2
|
|
arc: W1_H02W0201 V02S0201
|
|
arc: W1_H02W0401 V02N0401
|
|
|
|
.tile R30C53:PLC2
|
|
arc: N1_V02N0101 W1_H02E0101
|
|
arc: N1_V02N0401 N1_V01S0000
|
|
arc: W3_H06W0003 N1_V01S0000
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
|
|
.tile R30C59:PLC2
|
|
arc: E3_H06E0103 V06S0103
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
|
|
.tile R30C65:PLC2
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
|
|
.tile R30C71:PLC2
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
arc: W3_H06W0303 E3_H06W0203
|
|
|
|
.tile R30C77:PLC2
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: W3_H06W0203 E3_H06W0203
|
|
|
|
.tile R30C7:PLC2
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
|
|
.tile R30C83:PLC2
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
|
|
.tile R31C13:PLC2
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
|
|
.tile R31C17:PLC2
|
|
arc: N1_V02N0201 S3_V06N0103
|
|
|
|
.tile R31C19:PLC2
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
|
|
.tile R31C22:PLC2
|
|
arc: N1_V02N0301 S3_V06N0003
|
|
|
|
.tile R31C23:PLC2
|
|
arc: N1_V02N0001 S3_V06N0003
|
|
|
|
.tile R31C25:PLC2
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
arc: N1_V02N0201 S3_V06N0103
|
|
|
|
.tile R31C29:PLC2
|
|
arc: N1_V02N0401 S3_V06N0203
|
|
|
|
.tile R31C2:PLC2
|
|
arc: W1_H02W0701 V06S0203
|
|
|
|
.tile R31C31:PLC2
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
|
|
.tile R31C32:PLC2
|
|
arc: N1_V02N0101 H06W0103
|
|
|
|
.tile R31C34:PLC2
|
|
arc: N1_V02N0001 E3_H06W0003
|
|
arc: N1_V02N0301 H06E0003
|
|
arc: N3_V06N0103 S3_V06N0003
|
|
|
|
.tile R31C35:PLC2
|
|
arc: N1_V02N0201 S3_V06N0103
|
|
arc: N3_V06N0103 S3_V06N0103
|
|
arc: W3_H06W0103 S3_V06N0103
|
|
|
|
.tile R31C36:PLC2
|
|
arc: N1_V02N0701 E1_H01W0100
|
|
|
|
.tile R31C37:PLC2
|
|
arc: E1_H01E0101 W3_H06E0203
|
|
arc: E1_H02E0601 N3_V06S0303
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
arc: H01W0100 W3_H06E0303
|
|
arc: N1_V02N0101 S3_V06N0103
|
|
arc: N1_V02N0501 W3_H06E0303
|
|
arc: N3_V06N0303 S3_V06N0203
|
|
arc: S1_V02S0401 W3_H06E0203
|
|
|
|
.tile R31C38:PLC2
|
|
arc: E1_H02E0101 E1_H01W0100
|
|
arc: E1_H02E0201 V06N0103
|
|
arc: E3_H06E0103 H01E0101
|
|
arc: N1_V02N0001 S3_V06N0003
|
|
|
|
.tile R31C39:PLC2
|
|
arc: E1_H02E0001 N3_V06S0003
|
|
arc: E1_H02E0201 V02N0201
|
|
arc: E1_H02E0301 N3_V06S0003
|
|
arc: E1_H02E0501 N3_V06S0303
|
|
arc: E1_H02E0601 N3_V06S0303
|
|
arc: E1_H02E0701 V06N0203
|
|
arc: H00L0000 N1_V02S0201
|
|
arc: H00R0000 W1_H02E0601
|
|
arc: N1_V02N0101 H02W0101
|
|
arc: N1_V02N0301 E1_H02W0301
|
|
arc: N1_V02N0501 N3_V06S0303
|
|
arc: N1_V02N0601 N3_V06S0303
|
|
arc: V00B0100 E1_H02W0701
|
|
arc: V00T0000 H02W0201
|
|
arc: V00T0100 E1_H02W0101
|
|
arc: V01S0000 N3_V06S0103
|
|
arc: A1 V02N0501
|
|
arc: A5 Q5
|
|
arc: A6 S1_V02N0101
|
|
arc: A7 N1_V02S0101
|
|
arc: B1 Q1
|
|
arc: B5 V02N0501
|
|
arc: B6 H02W0101
|
|
arc: C1 E1_H02W0601
|
|
arc: C5 V00T0100
|
|
arc: C6 V01N0101
|
|
arc: C7 S1_V02N0001
|
|
arc: CE0 H00R0100
|
|
arc: CE1 H00R0100
|
|
arc: CE2 V02S0601
|
|
arc: CE3 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D1 V01S0100
|
|
arc: D5 H01W0000
|
|
arc: D6 H00L0100
|
|
arc: D7 E1_H02W0001
|
|
arc: E1_H01E0001 Q2
|
|
arc: E1_H01E0101 Q7
|
|
arc: F0 F5A_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00L0100 Q3
|
|
arc: H00R0100 F7
|
|
arc: H01W0000 Q4
|
|
arc: H01W0100 F7
|
|
arc: M0 V00B0000
|
|
arc: M1 H00R0000
|
|
arc: M2 V00B0100
|
|
arc: M3 H02E0201
|
|
arc: M4 V00T0000
|
|
arc: M5 H00R0000
|
|
arc: M6 V00T0000
|
|
arc: M7 H00L0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 F5
|
|
arc: N1_V02N0201 F0
|
|
arc: N1_V02N0701 F7
|
|
arc: S1_V02S0501 F7
|
|
arc: V00B0000 F6
|
|
arc: V01S0100 Q6
|
|
word: SLICEC.K1.INIT 1000010000100001
|
|
word: SLICED.K1.INIT 1010000000000000
|
|
word: SLICED.K0.INIT 1000001001000001
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 1000001001000001
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R31C40:PLC2
|
|
arc: E1_H02E0001 N1_V01S0000
|
|
arc: E1_H02E0301 V06N0003
|
|
arc: E1_H02E0401 V02N0401
|
|
arc: E1_H02E0501 V02S0501
|
|
arc: E1_H02E0701 V02S0701
|
|
arc: H00L0000 V02N0201
|
|
arc: H00R0100 V02S0501
|
|
arc: N1_V02N0001 S1_V02N0001
|
|
arc: N1_V02N0101 H01E0101
|
|
arc: N1_V02N0201 S1_V02N0201
|
|
arc: N1_V02N0401 H02W0401
|
|
arc: N1_V02N0501 H06E0303
|
|
arc: N1_V02N0601 H06W0303
|
|
arc: N3_V06N0303 S3_V06N0203
|
|
arc: S1_V02S0401 H02W0401
|
|
arc: V00T0000 V02N0401
|
|
arc: V01S0000 N3_V06S0103
|
|
arc: W1_H02W0101 N3_V06S0103
|
|
arc: W1_H02W0201 S1_V02N0201
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
arc: A0 N1_V02S0501
|
|
arc: A1 N1_V02S0501
|
|
arc: A2 H02E0701
|
|
arc: A3 V00B0000
|
|
arc: A5 H02E0701
|
|
arc: A7 F5
|
|
arc: B1 N1_V02S0301
|
|
arc: B2 V02S0101
|
|
arc: B3 E1_H02W0101
|
|
arc: B5 E1_H02W0101
|
|
arc: B7 V01S0000
|
|
arc: C0 H02E0601
|
|
arc: C1 H02E0601
|
|
arc: C2 H00L0100
|
|
arc: C3 N1_V02S0601
|
|
arc: C5 V00B0100
|
|
arc: C7 H01E0001
|
|
arc: CE0 W1_H02E0101
|
|
arc: CE1 H00R0100
|
|
arc: CE2 W1_H02E0101
|
|
arc: CE3 W1_H02E0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H00R0000
|
|
arc: D1 H00R0000
|
|
arc: D2 V02N0001
|
|
arc: D3 V00T0100
|
|
arc: D5 H01W0000
|
|
arc: D7 F0
|
|
arc: E1_H01E0001 F7
|
|
arc: E1_H01E0101 F2
|
|
arc: F0 F5A_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00L0100 Q3
|
|
arc: H00R0000 Q4
|
|
arc: H01W0000 Q7
|
|
arc: M0 V00B0100
|
|
arc: M1 H02E0001
|
|
arc: M3 H02E0201
|
|
arc: M4 V00T0000
|
|
arc: M5 E1_H02W0001
|
|
arc: M6 H02W0401
|
|
arc: M7 H00L0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V02N0301 F3
|
|
arc: V00B0000 Q6
|
|
arc: V00B0100 Q5
|
|
arc: V00T0100 Q1
|
|
word: SLICEB.K0.INIT 1000001001000001
|
|
word: SLICEB.K1.INIT 1001000000001001
|
|
word: SLICEA.K0.INIT 1010000000001010
|
|
word: SLICEA.K1.INIT 1000000000001000
|
|
word: SLICEC.K1.INIT 1100010000110001
|
|
word: SLICED.K1.INIT 1000001000000000
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R31C41:PLC2
|
|
arc: E1_H02E0001 W1_H02E0501
|
|
arc: E1_H02E0201 S1_V02N0201
|
|
arc: E1_H02E0401 V06S0203
|
|
arc: E1_H02E0501 N1_V02S0501
|
|
arc: E3_H06E0103 W1_H02E0201
|
|
arc: H00L0100 H02E0301
|
|
arc: H00R0100 H02E0701
|
|
arc: N1_V02N0001 H01E0001
|
|
arc: N1_V02N0301 N3_V06S0003
|
|
arc: N1_V02N0401 S3_V06N0203
|
|
arc: N1_V02N0501 H01E0101
|
|
arc: N1_V02N0701 S1_V02N0601
|
|
arc: N3_V06N0303 S3_V06N0203
|
|
arc: V00B0000 E1_H02W0401
|
|
arc: V00T0000 V02N0401
|
|
arc: V00T0100 W1_H02E0301
|
|
arc: W1_H02W0001 S1_V02N0001
|
|
arc: W1_H02W0101 V06N0103
|
|
arc: W1_H02W0301 N3_V06S0003
|
|
arc: W1_H02W0401 S3_V06N0203
|
|
arc: W1_H02W0601 S1_V02N0601
|
|
arc: W1_H02W0701 V02N0701
|
|
arc: A2 W1_H02E0501
|
|
arc: A3 H02W0501
|
|
arc: A7 V02S0101
|
|
arc: B2 F3
|
|
arc: B3 V02N0101
|
|
arc: B7 S1_V02N0701
|
|
arc: C2 N1_V01N0001
|
|
arc: C3 H00L0000
|
|
arc: C7 V02N0201
|
|
arc: CE0 H00R0100
|
|
arc: CE1 V02S0201
|
|
arc: CE2 H00R0100
|
|
arc: CE3 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D2 V00B0100
|
|
arc: D3 H00R0000
|
|
arc: D7 N1_V02S0401
|
|
arc: E1_H01E0001 F2
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00L0000 Q0
|
|
arc: H00R0000 Q4
|
|
arc: M0 V00B0000
|
|
arc: M2 V00B0000
|
|
arc: M4 V00T0100
|
|
arc: M6 V00T0000
|
|
arc: M7 H00L0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q6
|
|
arc: N1_V01N0101 Q2
|
|
arc: N1_V02N0201 Q2
|
|
arc: V00B0100 F7
|
|
arc: V01S0000 Q7
|
|
word: SLICEB.K1.INIT 1000010000100001
|
|
word: SLICED.K1.INIT 1100001110000010
|
|
word: SLICEB.K0.INIT 1000010000000000
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R31C42:PLC2
|
|
arc: E1_H02E0401 V02N0401
|
|
arc: E1_H02E0501 W1_H02E0401
|
|
arc: E1_H02E0601 N3_V06S0303
|
|
arc: E1_H02E0701 N3_V06S0203
|
|
arc: H00L0000 V02N0001
|
|
arc: H00R0000 H02E0401
|
|
arc: H00R0100 W1_H02E0501
|
|
arc: N1_V02N0501 N3_V06S0303
|
|
arc: N1_V02N0601 H01E0001
|
|
arc: S1_V02S0701 E1_H01W0100
|
|
arc: V00B0000 V02N0001
|
|
arc: V00B0100 V02N0301
|
|
arc: V00T0000 H02E0001
|
|
arc: V01S0100 N3_V06S0303
|
|
arc: W1_H02W0001 V02N0001
|
|
arc: W1_H02W0101 V02N0101
|
|
arc: W1_H02W0501 V02N0501
|
|
arc: A1 F7
|
|
arc: A4 H02E0501
|
|
arc: A7 Q7
|
|
arc: B1 V00T0000
|
|
arc: B3 V02N0301
|
|
arc: B4 V02N0501
|
|
arc: B7 V02N0501
|
|
arc: C1 H00L0100
|
|
arc: C3 E1_H02W0401
|
|
arc: C4 Q4
|
|
arc: C7 V00B0100
|
|
arc: CE1 H00R0100
|
|
arc: CE2 H00R0000
|
|
arc: CE3 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D1 V02N0201
|
|
arc: D3 W1_H02E0001
|
|
arc: D4 V02N0401
|
|
arc: D7 W1_H02E0001
|
|
arc: E1_H01E0001 F0
|
|
arc: F0 F5A_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00L0100 Q3
|
|
arc: M0 V00T0100
|
|
arc: M3 H02E0201
|
|
arc: M4 V00B0000
|
|
arc: M7 H00L0000
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V02N0401 F4
|
|
arc: V00T0100 F3
|
|
word: SLICEC.K0.INIT 1000001001000001
|
|
word: SLICEB.K1.INIT 1111000000110000
|
|
word: SLICED.K1.INIT 1001000010011001
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000010000010
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R31C43:PLC2
|
|
arc: E1_H01E0001 W3_H06E0003
|
|
arc: E1_H02E0101 V02N0101
|
|
arc: E1_H02E0301 W3_H06E0003
|
|
arc: E1_H02E0501 W3_H06E0303
|
|
arc: E1_H02E0601 V02N0601
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
arc: H00L0000 E1_H02W0201
|
|
arc: H00L0100 H02W0101
|
|
arc: H00R0000 H02E0401
|
|
arc: H00R0100 V02S0701
|
|
arc: H01W0100 W3_H06E0303
|
|
arc: N1_V01N0101 N3_V06S0203
|
|
arc: N1_V02N0001 H01E0001
|
|
arc: N1_V02N0501 N1_V01S0100
|
|
arc: N1_V02N0601 H01E0001
|
|
arc: N1_V02N0701 W3_H06E0203
|
|
arc: N3_V06N0203 S3_V06N0203
|
|
arc: S1_V02S0201 E1_H02W0201
|
|
arc: S1_V02S0401 W3_H06E0203
|
|
arc: S1_V02S0601 N3_V06S0303
|
|
arc: S1_V02S0701 N1_V02S0601
|
|
arc: V00B0000 V02N0001
|
|
arc: V01S0000 N3_V06S0103
|
|
arc: W1_H02W0401 W3_H06E0203
|
|
arc: W3_H06W0303 N3_V06S0303
|
|
arc: A1 H00L0000
|
|
arc: A3 V02N0501
|
|
arc: A5 Q5
|
|
arc: B1 F3
|
|
arc: B3 Q3
|
|
arc: B5 H00R0000
|
|
arc: C1 N1_V01N0001
|
|
arc: C2 V02N0401
|
|
arc: C3 E1_H01W0000
|
|
arc: C5 H02E0601
|
|
arc: CE0 V02N0201
|
|
arc: CE1 V02N0201
|
|
arc: CE2 S1_V02N0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D1 F2
|
|
arc: D2 Q2
|
|
arc: D3 V02S0001
|
|
arc: D5 H01W0000
|
|
arc: E1_H01E0101 F0
|
|
arc: F0 F5A_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: H01W0000 Q3
|
|
arc: M0 V00B0100
|
|
arc: M1 H02W0001
|
|
arc: M2 V00B0000
|
|
arc: M3 H00R0100
|
|
arc: M5 H00L0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: N1_V01N0001 Q1
|
|
arc: V00B0100 F5
|
|
word: SLICEC.K1.INIT 1001000010011001
|
|
word: SLICEB.K1.INIT 1101110111010000
|
|
word: SLICEB.K0.INIT 1111000000001111
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 1000010000000000
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R31C44:PLC2
|
|
arc: E1_H02E0001 W1_H02E0501
|
|
arc: E1_H02E0201 N3_V06S0103
|
|
arc: E1_H02E0401 V02N0401
|
|
arc: H00L0100 V02S0101
|
|
arc: H00R0000 V02N0601
|
|
arc: H00R0100 N1_V02S0701
|
|
arc: N1_V02N0101 S3_V06N0103
|
|
arc: N1_V02N0201 W3_H06E0103
|
|
arc: N1_V02N0401 H02W0401
|
|
arc: N1_V02N0501 H02E0501
|
|
arc: S1_V02S0201 S3_V06N0103
|
|
arc: V00B0000 V02N0001
|
|
arc: V00B0100 W1_H02E0701
|
|
arc: V00T0100 H02E0101
|
|
arc: W1_H02W0001 H01E0001
|
|
arc: W1_H02W0101 N3_V06S0103
|
|
arc: W1_H02W0401 N1_V01S0000
|
|
arc: A2 F7
|
|
arc: A4 V02N0101
|
|
arc: A5 V02N0101
|
|
arc: A6 V02N0101
|
|
arc: A7 N1_V01S0100
|
|
arc: B2 V02N0301
|
|
arc: B4 V01S0000
|
|
arc: B5 V01S0000
|
|
arc: B6 V02S0701
|
|
arc: C2 V02S0401
|
|
arc: C4 V02N0201
|
|
arc: C5 V01N0101
|
|
arc: C6 Q6
|
|
arc: CE1 H00R0100
|
|
arc: CE3 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02S0001
|
|
arc: D1 V02S0001
|
|
arc: D2 H01E0101
|
|
arc: D3 V02S0001
|
|
arc: D4 V00B0000
|
|
arc: D5 V00B0000
|
|
arc: D6 V01N0001
|
|
arc: D7 H02W0001
|
|
arc: E1_H01E0001 F1
|
|
arc: E1_H01E0101 F6
|
|
arc: E3_H06E0203 F4
|
|
arc: F0 F5A_SLICE
|
|
arc: F1 FXA_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F4 F5C_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 Q3
|
|
arc: LSR0 V00T0100
|
|
arc: LSR1 H02W0301
|
|
arc: M0 H02E0601
|
|
arc: M1 H00R0000
|
|
arc: M2 H02E0601
|
|
arc: M3 H00L0100
|
|
arc: M4 E1_H01E0101
|
|
arc: M6 V00B0100
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR3 LSR1
|
|
arc: S1_V02S0101 F1
|
|
arc: S1_V02S0301 F1
|
|
arc: V01S0000 Q3
|
|
arc: V01S0100 Q6
|
|
word: SLICED.K1.INIT 0101010100000000
|
|
word: SLICED.K0.INIT 1010100011000100
|
|
word: SLICEC.K0.INIT 0111111110110011
|
|
word: SLICEC.K1.INIT 0001001100100000
|
|
word: SLICEA.K0.INIT 1111111100000000
|
|
word: SLICEA.K1.INIT 1111111100000000
|
|
word: SLICEB.K0.INIT 0101000001000000
|
|
word: SLICEB.K1.INIT 1111111100000000
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R31C45:PLC2
|
|
arc: E1_H02E0001 S1_V02N0001
|
|
arc: E1_H02E0301 N3_V06S0003
|
|
arc: E1_H02E0601 W1_H02E0301
|
|
arc: E3_H06E0003 H01E0001
|
|
arc: H00L0000 E1_H02W0201
|
|
arc: H00L0100 H02W0101
|
|
arc: N1_V01N0001 N3_V06S0003
|
|
arc: N1_V02N0001 V01N0001
|
|
arc: N1_V02N0101 N3_V06S0103
|
|
arc: N1_V02N0201 N1_V01S0000
|
|
arc: N1_V02N0301 N3_V06S0003
|
|
arc: N1_V02N0401 H01E0001
|
|
arc: N1_V02N0501 N3_V06S0303
|
|
arc: N1_V02N0601 E1_H02W0601
|
|
arc: N1_V02N0701 N1_V01S0100
|
|
arc: S1_V02S0201 N3_V06S0103
|
|
arc: S1_V02S0301 N3_V06S0003
|
|
arc: S1_V02S0501 N3_V06S0303
|
|
arc: V00B0100 H02W0501
|
|
arc: V00T0000 H02E0201
|
|
arc: V01S0100 N3_V06S0303
|
|
arc: W1_H02W0001 V02N0001
|
|
arc: W1_H02W0201 N3_V06S0103
|
|
arc: W1_H02W0301 E1_H02W0301
|
|
arc: W1_H02W0401 V01N0001
|
|
arc: A0 V01N0101
|
|
arc: A2 H02W0501
|
|
arc: A3 V02N0501
|
|
arc: A7 E1_H02W0501
|
|
arc: B0 V02N0101
|
|
arc: B2 H00R0100
|
|
arc: B3 H01W0100
|
|
arc: B6 N1_V02S0501
|
|
arc: B7 V02N0701
|
|
arc: C0 N1_V01N0001
|
|
arc: C2 E1_H01W0000
|
|
arc: C3 H02W0401
|
|
arc: C6 S1_V02N0001
|
|
arc: C7 V00T0100
|
|
arc: CE0 H00R0000
|
|
arc: CE1 H00R0000
|
|
arc: CE2 H00R0000
|
|
arc: CE3 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02S0001
|
|
arc: D2 V02N0201
|
|
arc: D3 F0
|
|
arc: D6 H02W0001
|
|
arc: D7 V00B0000
|
|
arc: E1_H01E0001 F6
|
|
arc: E1_H01E0101 F3
|
|
arc: E1_H02E0101 Q3
|
|
arc: E1_H02E0201 F2
|
|
arc: E1_H02E0401 F6
|
|
arc: E1_H02E0501 Q7
|
|
arc: E1_H02E0701 Q5
|
|
arc: F0 F5A_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00R0000 F6
|
|
arc: H00R0100 F7
|
|
arc: H01W0100 Q6
|
|
arc: M0 V00B0100
|
|
arc: M1 H00L0000
|
|
arc: M3 H00L0100
|
|
arc: M4 H02E0401
|
|
arc: M5 H02E0001
|
|
arc: M6 V00T0000
|
|
arc: M7 H02W0201
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: S1_V02S0401 F6
|
|
arc: S1_V02S0601 F6
|
|
arc: S1_V02S0701 Q5
|
|
arc: V00B0000 Q4
|
|
arc: V00T0100 Q1
|
|
word: SLICED.K0.INIT 1100000000000000
|
|
word: SLICEB.K1.INIT 1001000000000000
|
|
word: SLICEA.K0.INIT 1010010100100001
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 1100010000000000
|
|
word: SLICED.K1.INIT 1000001001000001
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R31C46:PLC2
|
|
arc: E1_H02E0001 S1_V02N0001
|
|
arc: E1_H02E0601 E1_H01W0000
|
|
arc: E1_H02E0701 E1_H01W0100
|
|
arc: H00L0000 E1_H02W0001
|
|
arc: N1_V02N0201 H01E0001
|
|
arc: N1_V02N0301 H02E0301
|
|
arc: N1_V02N0401 S1_V02N0101
|
|
arc: N1_V02N0501 N3_V06S0303
|
|
arc: N1_V02N0601 N3_V06S0303
|
|
arc: S1_V02S0201 H01E0001
|
|
arc: S1_V02S0601 H02E0601
|
|
arc: V00B0000 V02N0201
|
|
arc: V00B0100 H02E0701
|
|
arc: V00T0000 H02E0201
|
|
arc: V01S0000 N3_V06S0103
|
|
arc: W1_H02W0001 V02S0001
|
|
arc: W1_H02W0101 V01N0101
|
|
arc: W1_H02W0201 E1_H02W0701
|
|
arc: W1_H02W0401 N1_V01S0000
|
|
arc: W3_H06W0303 E3_H06W0203
|
|
arc: A0 H02W0501
|
|
arc: A1 V02N0501
|
|
arc: A2 V00T0000
|
|
arc: A4 V00T0100
|
|
arc: A6 V02N0101
|
|
arc: A7 H02E0501
|
|
arc: B0 H02E0101
|
|
arc: B1 H02E0101
|
|
arc: B2 H00R0100
|
|
arc: B6 N1_V02S0501
|
|
arc: B7 V02N0701
|
|
arc: C0 H00L0100
|
|
arc: C1 H00L0100
|
|
arc: C2 N1_V01S0100
|
|
arc: C3 N1_V01S0100
|
|
arc: C4 Q4
|
|
arc: C5 V00T0100
|
|
arc: C6 V02S0001
|
|
arc: C7 V02N0001
|
|
arc: CE0 H00R0000
|
|
arc: CE1 H00R0000
|
|
arc: CE2 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 S1_V02N0201
|
|
arc: D2 H01E0101
|
|
arc: D4 H00L0100
|
|
arc: D5 H00L0100
|
|
arc: D6 H02E0001
|
|
arc: D7 F0
|
|
arc: E1_H01E0101 F2
|
|
arc: E1_H02E0101 Q1
|
|
arc: E1_H02E0201 F2
|
|
arc: E1_H02E0301 Q3
|
|
arc: E1_H02E0401 Q4
|
|
arc: F0 F5A_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00L0100 Q1
|
|
arc: H00R0000 F6
|
|
arc: H00R0100 F7
|
|
arc: H01W0000 Q4
|
|
arc: LSR0 E1_H02W0301
|
|
arc: LSR1 H02W0301
|
|
arc: M0 V00B0100
|
|
arc: M1 H02W0001
|
|
arc: M2 V00B0000
|
|
arc: M3 H00L0000
|
|
arc: M4 E1_H02W0401
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR0
|
|
arc: V00T0100 Q3
|
|
arc: V01S0100 F4
|
|
arc: W1_H02W0501 F5
|
|
word: SLICED.K0.INIT 1110101010101010
|
|
word: SLICEC.K0.INIT 0000000001011111
|
|
word: SLICEA.K0.INIT 0000000010010000
|
|
word: SLICEA.K1.INIT 1001000010010000
|
|
word: SLICED.K1.INIT 1001000000000000
|
|
word: SLICEB.K1.INIT 1111000011110000
|
|
word: SLICEB.K0.INIT 1111000011100000
|
|
word: SLICEC.K1.INIT 0000000000001111
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
|
|
.tile R31C47:PLC2
|
|
arc: E1_H02E0401 V02N0401
|
|
arc: E1_H02E0501 V06N0303
|
|
arc: E1_H02E0601 V06N0303
|
|
arc: E1_H02E0701 N1_V02S0701
|
|
arc: N1_V02N0001 E1_H01W0000
|
|
arc: N1_V02N0101 H01E0101
|
|
arc: N1_V02N0201 N1_V01S0000
|
|
arc: N1_V02N0401 H06E0203
|
|
arc: N1_V02N0601 N1_V01S0000
|
|
arc: N1_V02N0701 S3_V06N0203
|
|
arc: N3_V06N0103 S3_V06N0003
|
|
arc: N3_V06N0203 S3_V06N0103
|
|
arc: V00B0000 W1_H02E0401
|
|
arc: W1_H02W0001 S1_V02N0001
|
|
arc: W1_H02W0201 W3_H06E0103
|
|
arc: W1_H02W0301 E1_H02W0201
|
|
arc: W1_H02W0501 V06N0303
|
|
arc: W1_H02W0601 V06N0303
|
|
arc: A1 H00L0100
|
|
arc: A2 V00T0000
|
|
arc: A4 V00T0000
|
|
arc: B0 H01W0100
|
|
arc: B1 V00T0000
|
|
arc: B4 H02E0301
|
|
arc: C1 H02E0601
|
|
arc: C2 H02E0601
|
|
arc: C4 H02E0401
|
|
arc: C6 V02N0201
|
|
arc: CE0 H00R0000
|
|
arc: CE1 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H01E0101
|
|
arc: D1 H01E0101
|
|
arc: D2 H01E0101
|
|
arc: D4 H01W0000
|
|
arc: D6 H02E0201
|
|
arc: E1_H01E0001 F4
|
|
arc: E1_H02E0001 Q0
|
|
arc: E1_H02E0201 Q2
|
|
arc: E1_H02E0301 Q1
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: H00L0100 Q1
|
|
arc: H00R0000 F6
|
|
arc: H01W0000 Q2
|
|
arc: H01W0100 Q0
|
|
arc: LSR1 V00B0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR1
|
|
arc: V00T0000 Q0
|
|
word: SLICEA.K0.INIT 0011001100000000
|
|
word: SLICEA.K1.INIT 0110101000000000
|
|
word: SLICEB.K0.INIT 0101101000000000
|
|
word: SLICED.K0.INIT 1111111111110000
|
|
word: SLICEC.K0.INIT 1010100011000100
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
|
|
.tile R31C48:PLC2
|
|
arc: E1_H02E0101 V06N0103
|
|
arc: E1_H02E0301 N3_V06S0003
|
|
arc: H00L0100 H02E0301
|
|
arc: H00R0000 S1_V02N0401
|
|
arc: N1_V02N0101 H02W0101
|
|
arc: N1_V02N0201 W1_H02E0201
|
|
arc: N1_V02N0301 H06E0003
|
|
arc: N1_V02N0401 E1_H02W0401
|
|
arc: S1_V02S0701 E1_H02W0701
|
|
arc: V00B0000 H02E0601
|
|
arc: V00B0100 N1_V02S0301
|
|
arc: W1_H02W0001 V02S0001
|
|
arc: W1_H02W0301 V02N0301
|
|
arc: W1_H02W0401 N3_V06S0203
|
|
arc: W1_H02W0701 V02N0701
|
|
arc: A0 W1_H02E0701
|
|
arc: A1 H00L0100
|
|
arc: A2 H02E0701
|
|
arc: A3 V02N0501
|
|
arc: A5 H02E0501
|
|
arc: A6 N1_V01N0101
|
|
arc: B0 W1_H02E0101
|
|
arc: B1 W1_H02E0101
|
|
arc: B3 V02N0101
|
|
arc: B5 F3
|
|
arc: B6 V02N0501
|
|
arc: C0 H00L0100
|
|
arc: C1 W1_H02E0601
|
|
arc: C2 V02S0401
|
|
arc: C3 N1_V01N0001
|
|
arc: C5 V02N0201
|
|
arc: C6 V00T0100
|
|
arc: CE0 H00L0000
|
|
arc: CE1 H00L0000
|
|
arc: CE2 H00L0000
|
|
arc: CE3 H00L0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H02E0201
|
|
arc: D1 H02E0001
|
|
arc: D2 N1_V02S0001
|
|
arc: D3 N1_V01S0000
|
|
arc: D5 H00R0100
|
|
arc: D6 V00B0000
|
|
arc: E1_H01E0001 F6
|
|
arc: E1_H01E0101 F2
|
|
arc: E1_H02E0001 Q2
|
|
arc: E1_H02E0201 F2
|
|
arc: E1_H02E0501 F5
|
|
arc: F0 F5A_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: H00L0000 F2
|
|
arc: H00R0100 Q7
|
|
arc: H01W0000 F0
|
|
arc: M0 H01E0001
|
|
arc: M1 W1_H02E0001
|
|
arc: M2 H02W0601
|
|
arc: M3 E1_H02W0201
|
|
arc: M4 V00B0100
|
|
arc: M6 H02W0401
|
|
arc: M7 H00R0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q6
|
|
arc: N1_V01N0101 Q3
|
|
arc: N1_V02N0001 F0
|
|
arc: S1_V02S0201 F2
|
|
arc: S1_V02S0401 Q6
|
|
arc: S1_V02S0601 Q4
|
|
arc: V00T0100 Q1
|
|
arc: V01S0000 F2
|
|
arc: V01S0100 F2
|
|
word: SLICEB.K0.INIT 1010000000000000
|
|
word: SLICEA.K0.INIT 0111101111110011
|
|
word: SLICEA.K1.INIT 0001001000100010
|
|
word: SLICEC.K1.INIT 1000000001000000
|
|
word: SLICEB.K1.INIT 1000101001000101
|
|
word: SLICED.K0.INIT 1000001001000001
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R31C49:PLC2
|
|
arc: E1_H02E0001 V01N0001
|
|
arc: E1_H02E0201 V01N0001
|
|
arc: E1_H02E0401 V01N0001
|
|
arc: E1_H02E0501 H01E0101
|
|
arc: E1_H02E0701 N1_V01S0100
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
arc: H00L0000 H02E0201
|
|
arc: H00R0000 W1_H02E0401
|
|
arc: N1_V01N0001 N3_V06S0003
|
|
arc: N1_V01N0101 N3_V06S0203
|
|
arc: N1_V02N0101 N3_V06S0103
|
|
arc: N1_V02N0201 N1_V01S0000
|
|
arc: N1_V02N0401 E1_H01W0000
|
|
arc: N1_V02N0501 V01N0101
|
|
arc: N1_V02N0601 N1_V01S0000
|
|
arc: N3_V06N0003 S3_V06N0303
|
|
arc: S1_V02S0001 N3_V06S0003
|
|
arc: S1_V02S0301 H02E0301
|
|
arc: V00B0100 H02E0501
|
|
arc: V00T0000 H02E0001
|
|
arc: V00T0100 N1_V02S0501
|
|
arc: W1_H02W0101 N3_V06S0103
|
|
arc: W1_H02W0201 V02N0201
|
|
arc: W1_H02W0401 V06S0203
|
|
arc: W1_H02W0601 W3_H06E0303
|
|
arc: A1 H02W0701
|
|
arc: A2 F5
|
|
arc: A5 V00T0000
|
|
arc: B0 H02E0301
|
|
arc: B1 V02N0301
|
|
arc: B2 S1_V02N0101
|
|
arc: B5 H02E0101
|
|
arc: C0 H00L0100
|
|
arc: C1 H00L0100
|
|
arc: C2 V02N0401
|
|
arc: C5 H01E0001
|
|
arc: C6 V01N0101
|
|
arc: CE1 H00L0000
|
|
arc: CE2 H00L0000
|
|
arc: CE3 H00L0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02N0001
|
|
arc: D1 V02N0001
|
|
arc: D2 V00T0100
|
|
arc: D3 V00T0100
|
|
arc: D5 F0
|
|
arc: D6 F2
|
|
arc: E1_H01E0001 F2
|
|
arc: E1_H01E0101 F2
|
|
arc: E1_H02E0601 F6
|
|
arc: F0 F5A_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: H00L0100 Q3
|
|
arc: M0 H02W0601
|
|
arc: M2 V00B0100
|
|
arc: M3 E1_H02W0201
|
|
arc: M5 H00R0000
|
|
arc: M6 E1_H02W0401
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V02N0001 F2
|
|
arc: S1_V02S0401 F6
|
|
arc: S1_V02S0601 Q6
|
|
arc: S1_V02S0701 Q5
|
|
arc: V01S0000 F2
|
|
word: SLICED.K0.INIT 1111111111110000
|
|
word: SLICEA.K0.INIT 1100001100000000
|
|
word: SLICEA.K1.INIT 1010010110000100
|
|
word: SLICEC.K1.INIT 1001000000000000
|
|
word: SLICEB.K1.INIT 1111111100000000
|
|
word: SLICEB.K0.INIT 1111111000000000
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R31C50:PLC2
|
|
arc: H00R0000 H02E0601
|
|
arc: N1_V02N0101 H06W0103
|
|
arc: N1_V02N0201 S1_V02N0201
|
|
arc: N1_V02N0401 H01E0001
|
|
arc: N1_V02N0601 N1_V01S0000
|
|
arc: N1_V02N0701 N3_V06S0203
|
|
arc: N3_V06N0103 S3_V06N0103
|
|
arc: S1_V02S0501 N3_V06S0303
|
|
arc: S1_V02S0701 N3_V06S0203
|
|
arc: W1_H02W0201 S3_V06N0103
|
|
arc: W1_H02W0401 W3_H06E0203
|
|
arc: W1_H02W0601 V01N0001
|
|
arc: W1_H02W0701 N3_V06S0203
|
|
arc: A0 H00L0000
|
|
arc: A1 H00L0000
|
|
arc: A2 V02N0501
|
|
arc: A3 V01N0101
|
|
arc: B0 V02N0301
|
|
arc: B1 V02N0101
|
|
arc: B2 H00L0000
|
|
arc: B3 V01N0001
|
|
arc: C0 V02N0401
|
|
arc: C1 V02N0601
|
|
arc: C2 H02E0401
|
|
arc: C3 H02E0401
|
|
arc: CE1 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H02E0001
|
|
arc: D1 H02E0201
|
|
arc: D2 H01E0101
|
|
arc: D3 V02N0001
|
|
arc: F0 F5A_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: H00L0000 Q2
|
|
arc: H01W0000 F0
|
|
arc: LSR1 H02E0501
|
|
arc: M0 V00T0100
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXLSR1 LSR1
|
|
arc: V00T0100 F3
|
|
word: SLICEB.K0.INIT 0110110000000000
|
|
word: SLICEB.K1.INIT 1110000010001010
|
|
word: SLICEA.K0.INIT 0110111110101111
|
|
word: SLICEA.K1.INIT 0000011000001010
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R31C51:PLC2
|
|
arc: H00R0100 V02N0501
|
|
arc: N1_V02N0101 E1_H02W0101
|
|
arc: N1_V02N0401 S1_V02N0401
|
|
arc: N1_V02N0601 N1_V01S0000
|
|
arc: V00B0100 W1_H02E0701
|
|
arc: W1_H02W0201 V02N0201
|
|
arc: W1_H02W0401 S1_V02N0401
|
|
arc: CE0 V02S0201
|
|
arc: CE3 V02S0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: M0 V00B0100
|
|
arc: M7 H00R0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q7
|
|
arc: N1_V02N0001 Q0
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R31C52:PLC2
|
|
arc: N1_V02N0001 H06E0003
|
|
arc: N1_V02N0401 H06E0203
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
|
|
.tile R31C53:PLC2
|
|
arc: N1_V02N0001 E3_H06W0003
|
|
arc: N1_V02N0201 S3_V06N0103
|
|
arc: N1_V02N0301 S3_V06N0003
|
|
arc: N3_V06N0303 S3_V06N0203
|
|
arc: W1_H02W0101 V06N0103
|
|
arc: W3_H06W0103 V06N0103
|
|
|
|
.tile R31C58:PLC2
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
|
|
.tile R31C59:PLC2
|
|
arc: N1_V02N0201 S3_V06N0103
|
|
arc: N1_V02N0501 S3_V06N0303
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
|
|
.tile R31C64:PLC2
|
|
arc: N1_V02N0501 S3_V06N0303
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
|
|
.tile R31C65:PLC2
|
|
arc: N1_V02N0401 S3_V06N0203
|
|
arc: N3_V06N0003 S3_V06N0303
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
|
|
.tile R31C70:PLC2
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
|
|
.tile R31C71:PLC2
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
|
|
.tile R31C76:PLC2
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
|
|
.tile R31C77:PLC2
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
|
|
.tile R31C7:PLC2
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
|
|
.tile R31C82:PLC2
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
|
|
.tile R31C83:PLC2
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
|
|
.tile R31C88:PLC2
|
|
arc: W3_H06W0303 E1_H01W0100
|
|
|
|
.tile R32C13:PLC2
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
arc: N3_V06N0203 S3_V06N0203
|
|
|
|
.tile R32C19:PLC2
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
|
|
.tile R32C25:PLC2
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: N3_V06N0103 S3_V06N0003
|
|
|
|
.tile R32C31:PLC2
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
|
|
.tile R32C32:PLC2
|
|
arc: N3_V06N0103 S3_V06N0103
|
|
|
|
.tile R32C37:PLC2
|
|
arc: E1_H02E0201 W3_H06E0103
|
|
arc: E1_H02E0401 V02S0401
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
|
|
.tile R32C38:PLC2
|
|
arc: N1_V02N0201 H02E0201
|
|
|
|
.tile R32C39:PLC2
|
|
arc: H00R0100 V02S0501
|
|
arc: N1_V02N0201 W1_H02E0201
|
|
arc: N1_V02N0401 N1_V01S0000
|
|
arc: N1_V02N0501 N3_V06S0303
|
|
arc: V00B0000 W1_H02E0401
|
|
arc: V00T0000 W1_H02E0201
|
|
arc: C2 S1_V02N0401
|
|
arc: CE1 H00R0100
|
|
arc: CE2 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D2 Q2
|
|
arc: E1_H01E0001 F2
|
|
arc: F2 F2_SLICE
|
|
arc: M2 V00B0000
|
|
arc: M4 V00T0000
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: N1_V01N0101 Q4
|
|
word: SLICEB.K0.INIT 0000111111110000
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R32C3:PLC2
|
|
arc: W1_H02W0501 V02N0501
|
|
|
|
.tile R32C40:PLC2
|
|
arc: E1_H02E0201 V02N0201
|
|
arc: E1_H02E0301 S1_V02N0301
|
|
arc: E1_H02E0601 S1_V02N0601
|
|
arc: H00R0000 V02S0401
|
|
arc: H00R0100 N1_V02S0501
|
|
arc: N1_V02N0101 S3_V06N0103
|
|
arc: N1_V02N0201 S1_V02N0201
|
|
arc: N1_V02N0301 E1_H01W0100
|
|
arc: N1_V02N0401 S3_V06N0203
|
|
arc: N1_V02N0601 H01E0001
|
|
arc: N3_V06N0003 S3_V06N0003
|
|
arc: N3_V06N0103 S3_V06N0103
|
|
arc: N3_V06N0203 S3_V06N0203
|
|
arc: V00B0000 S1_V02N0001
|
|
arc: V01S0000 S3_V06N0103
|
|
arc: CE1 H00R0100
|
|
arc: CE2 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0001 Q5
|
|
arc: M2 V00B0000
|
|
arc: M5 H00R0000
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: N1_V02N0001 Q2
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R32C41:PLC2
|
|
arc: E1_H02E0001 V06N0003
|
|
arc: E1_H02E0101 S1_V02N0101
|
|
arc: E1_H02E0401 E3_H06W0203
|
|
arc: E1_H02E0701 S1_V02N0701
|
|
arc: H00L0000 E1_H02W0001
|
|
arc: H01W0100 E3_H06W0303
|
|
arc: N1_V02N0101 H02W0101
|
|
arc: N1_V02N0201 H01E0001
|
|
arc: N1_V02N0401 S1_V02N0401
|
|
arc: N1_V02N0501 E3_H06W0303
|
|
arc: N1_V02N0601 E3_H06W0303
|
|
arc: N1_V02N0701 E3_H06W0203
|
|
arc: N3_V06N0103 S3_V06N0003
|
|
arc: N3_V06N0303 E3_H06W0303
|
|
arc: V00B0000 H02W0401
|
|
arc: V00B0100 E1_H02W0701
|
|
arc: V00T0000 H02W0201
|
|
arc: A1 V02N0701
|
|
arc: A3 V00T0000
|
|
arc: A4 S1_V02N0101
|
|
arc: B1 V00B0000
|
|
arc: B3 H02W0101
|
|
arc: B4 N1_V01S0000
|
|
arc: C1 E1_H01W0000
|
|
arc: C3 H00R0100
|
|
arc: CE3 H00L0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D1 E1_H02W0201
|
|
arc: D3 V00B0100
|
|
arc: E1_H01E0001 F4
|
|
arc: E3_H06E0003 F0
|
|
arc: F0 F5A_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: H00R0100 Q7
|
|
arc: M0 V00T0100
|
|
arc: M7 H02E0201
|
|
arc: MUXCLK3 CLK0
|
|
arc: V00T0100 F3
|
|
word: SLICEC.K0.INIT 0110011001100110
|
|
word: SLICEB.K1.INIT 1000010000100001
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 1000001001000001
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R32C42:PLC2
|
|
arc: E1_H02E0201 W1_H02E0201
|
|
arc: E1_H02E0301 N1_V01S0100
|
|
arc: E1_H02E0401 S1_V02N0401
|
|
arc: E1_H02E0501 N1_V01S0100
|
|
arc: E1_H02E0601 W1_H02E0601
|
|
arc: E1_H02E0701 V02S0701
|
|
arc: H00L0100 H02E0101
|
|
arc: N1_V02N0001 H02E0001
|
|
arc: N1_V02N0101 H02E0101
|
|
arc: N1_V02N0201 H01E0001
|
|
arc: N1_V02N0301 N1_V01S0100
|
|
arc: N1_V02N0401 S1_V02N0101
|
|
arc: N1_V02N0501 S1_V02N0401
|
|
arc: V00T0100 W1_H02E0301
|
|
arc: V01S0000 N3_V06S0103
|
|
arc: W1_H02W0101 N1_V01S0100
|
|
arc: W1_H02W0201 N3_V06S0103
|
|
arc: W1_H02W0401 S1_V02N0401
|
|
arc: A0 H00L0100
|
|
arc: A1 F5
|
|
arc: A2 V00T0000
|
|
arc: A5 Q5
|
|
arc: A7 Q7
|
|
arc: B0 V00B0000
|
|
arc: B1 H01W0100
|
|
arc: B2 H02E0101
|
|
arc: B5 V01S0000
|
|
arc: B7 V01S0000
|
|
arc: C0 N1_V01S0100
|
|
arc: C1 H00L0000
|
|
arc: C2 S1_V02N0401
|
|
arc: C5 E1_H01E0101
|
|
arc: CE0 E1_H02W0101
|
|
arc: CE1 E1_H02W0101
|
|
arc: CE2 E1_H02W0101
|
|
arc: CE3 E1_H02W0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 Q0
|
|
arc: D1 V00B0100
|
|
arc: D2 V01S0100
|
|
arc: D5 S1_V02N0401
|
|
arc: D7 E1_H02W0001
|
|
arc: E1_H01E0001 F1
|
|
arc: E1_H01E0101 Q7
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00L0000 F2
|
|
arc: H01W0000 Q2
|
|
arc: H01W0100 F0
|
|
arc: M0 V00T0100
|
|
arc: M2 W1_H02E0601
|
|
arc: M4 H02E0401
|
|
arc: M5 H02E0001
|
|
arc: M7 E1_H01W0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: V00B0000 Q4
|
|
arc: V00B0100 F7
|
|
arc: V00T0000 Q0
|
|
arc: V01S0100 Q5
|
|
word: SLICEA.K0.INIT 1100001101000001
|
|
word: SLICED.K1.INIT 1011101100000000
|
|
word: SLICEB.K0.INIT 1101110100001101
|
|
word: SLICEC.K1.INIT 1100111101000101
|
|
word: SLICEA.K1.INIT 1000000000000000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R32C43:PLC2
|
|
arc: E1_H02E0201 S3_V06N0103
|
|
arc: E1_H02E0401 V02S0401
|
|
arc: E3_H06E0103 S3_V06N0103
|
|
arc: E3_H06E0203 S3_V06N0203
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
arc: H00R0000 V02S0401
|
|
arc: H00R0100 W1_H02E0701
|
|
arc: H01W0000 W3_H06E0103
|
|
arc: N1_V02N0001 N1_V01S0000
|
|
arc: N1_V02N0101 S3_V06N0103
|
|
arc: N1_V02N0401 H02E0401
|
|
arc: N1_V02N0501 H02E0501
|
|
arc: N1_V02N0601 H01E0001
|
|
arc: N1_V02N0701 S3_V06N0203
|
|
arc: N3_V06N0203 S3_V06N0103
|
|
arc: N3_V06N0303 S3_V06N0203
|
|
arc: V00B0100 S1_V02N0101
|
|
arc: V00T0000 V02S0601
|
|
arc: V00T0100 V02N0501
|
|
arc: A0 S1_V02N0701
|
|
arc: A2 V02S0701
|
|
arc: A3 F7
|
|
arc: A4 N1_V01N0101
|
|
arc: A7 H02W0701
|
|
arc: B0 H02E0301
|
|
arc: B3 Q3
|
|
arc: B4 F3
|
|
arc: B7 H02E0301
|
|
arc: C0 H00L0100
|
|
arc: C2 E1_H02W0401
|
|
arc: C4 V00B0100
|
|
arc: C7 H02W0401
|
|
arc: CE0 H00L0000
|
|
arc: CE1 H00L0000
|
|
arc: CE2 H00L0000
|
|
arc: CE3 H00L0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V01S0100
|
|
arc: D2 V02N0001
|
|
arc: D3 V02S0201
|
|
arc: D4 F0
|
|
arc: D7 V00B0000
|
|
arc: E1_H01E0001 F4
|
|
arc: E1_H01E0101 F2
|
|
arc: E1_H02E0001 F2
|
|
arc: F0 F5A_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00L0000 F2
|
|
arc: H00L0100 Q1
|
|
arc: M0 E1_H02W0601
|
|
arc: M1 H00R0000
|
|
arc: M2 V00T0000
|
|
arc: M3 H00R0100
|
|
arc: M4 V00T0100
|
|
arc: M5 E1_H02W0001
|
|
arc: M7 H02W0201
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0101 Q7
|
|
arc: N1_V02N0201 F2
|
|
arc: V00B0000 Q4
|
|
arc: V01S0000 F2
|
|
arc: V01S0100 Q4
|
|
arc: W1_H02W0001 F2
|
|
arc: W1_H02W0201 Q2
|
|
arc: W1_H02W0701 Q5
|
|
word: SLICED.K1.INIT 1111101000110010
|
|
word: SLICEB.K1.INIT 1000100000100010
|
|
word: SLICEA.K0.INIT 1000010010100101
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 1000010000000000
|
|
word: SLICEB.K0.INIT 1010000000000000
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R32C44:PLC2
|
|
arc: E1_H02E0001 V02N0001
|
|
arc: E1_H02E0201 W1_H02E0701
|
|
arc: E1_H02E0601 W1_H02E0601
|
|
arc: E3_H06E0103 W1_H02E0201
|
|
arc: N1_V02N0301 H06E0003
|
|
arc: N1_V02N0401 E1_H02W0401
|
|
arc: N1_V02N0601 H01E0001
|
|
arc: V00B0100 V02S0101
|
|
arc: V00T0000 H02E0001
|
|
arc: W1_H02W0001 N1_V01S0000
|
|
arc: W1_H02W0101 H01E0101
|
|
arc: W1_H02W0201 V02S0201
|
|
arc: W1_H02W0401 N1_V01S0000
|
|
arc: W1_H02W0701 N1_V02S0701
|
|
arc: A0 H00L0000
|
|
arc: A5 V02S0101
|
|
arc: B0 V02S0301
|
|
arc: B2 H00L0000
|
|
arc: C0 H00L0100
|
|
arc: C1 H00L0100
|
|
arc: C2 H00L0100
|
|
arc: C3 N1_V01S0100
|
|
arc: CE0 H00R0100
|
|
arc: CE1 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 Q0
|
|
arc: D1 V00B0100
|
|
arc: D2 V00B0100
|
|
arc: D3 N1_V01S0000
|
|
arc: D5 H02E0201
|
|
arc: E1_H01E0001 F3
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: H00L0000 Q2
|
|
arc: H00L0100 Q1
|
|
arc: H00R0100 F5
|
|
arc: LSR1 V00T0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR1
|
|
arc: N1_V01N0001 Q2
|
|
arc: N1_V01N0101 Q2
|
|
arc: N1_V02N0001 Q0
|
|
arc: N1_V02N0101 Q1
|
|
arc: N1_V02N0201 Q2
|
|
word: SLICEB.K1.INIT 0000000000001111
|
|
word: SLICEA.K0.INIT 0100110010000000
|
|
word: SLICEA.K1.INIT 0000111100000000
|
|
word: SLICEB.K0.INIT 0011110000000000
|
|
word: SLICEC.K1.INIT 1111111110101010
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R32C45:PLC2
|
|
arc: E1_H02E0201 V02S0201
|
|
arc: E1_H02E0701 N1_V01S0100
|
|
arc: H00L0000 V02S0201
|
|
arc: H00R0000 V02S0401
|
|
arc: H00R0100 E1_H02W0701
|
|
arc: N1_V01N0001 S3_V06N0003
|
|
arc: N1_V02N0001 H01E0001
|
|
arc: N1_V02N0101 S1_V02N0101
|
|
arc: N1_V02N0301 S3_V06N0003
|
|
arc: N1_V02N0501 E1_H02W0501
|
|
arc: N1_V02N0701 N1_V01S0100
|
|
arc: N3_V06N0003 E3_H06W0003
|
|
arc: V00T0100 V02N0501
|
|
arc: W1_H02W0001 E1_H02W0001
|
|
arc: W1_H02W0401 N1_V02S0401
|
|
arc: W1_H02W0601 H01E0001
|
|
arc: A0 H00L0000
|
|
arc: A1 V02S0701
|
|
arc: A4 S1_V02N0101
|
|
arc: A7 N1_V01S0100
|
|
arc: B0 V00T0000
|
|
arc: B1 V02S0301
|
|
arc: B4 V02S0501
|
|
arc: B6 S1_V02N0501
|
|
arc: B7 V00B0000
|
|
arc: C0 N1_V01N0001
|
|
arc: C1 N1_V01N0001
|
|
arc: C4 Q4
|
|
arc: C6 F4
|
|
arc: C7 S1_V02N0201
|
|
arc: CE0 H00R0000
|
|
arc: CE1 H00R0000
|
|
arc: CE2 V02S0601
|
|
arc: CE3 V02S0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V00B0100
|
|
arc: D1 V01S0100
|
|
arc: D4 H01W0000
|
|
arc: D6 H00L0100
|
|
arc: D7 H01W0000
|
|
arc: E1_H01E0001 F1
|
|
arc: E1_H02E0501 F7
|
|
arc: E1_H02E0601 F6
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00L0100 Q1
|
|
arc: H01W0000 Q6
|
|
arc: M0 H02E0601
|
|
arc: M1 H00R0100
|
|
arc: M2 E1_H02W0601
|
|
arc: M3 H02E0201
|
|
arc: M4 W1_H02E0401
|
|
arc: M5 H02E0001
|
|
arc: M6 V00T0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0101 Q3
|
|
arc: N1_V02N0201 F0
|
|
arc: V00B0000 Q4
|
|
arc: V00B0100 Q5
|
|
arc: V00T0000 Q0
|
|
arc: V01S0100 Q2
|
|
word: SLICEA.K0.INIT 1000001001000001
|
|
word: SLICEC.K0.INIT 1100010011110101
|
|
word: SLICED.K0.INIT 1100000000110000
|
|
word: SLICED.K1.INIT 1111001101010001
|
|
word: SLICEA.K1.INIT 1101000000001101
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R32C46:PLC2
|
|
arc: E1_H02E0201 S3_V06N0103
|
|
arc: E1_H02E0301 S3_V06N0003
|
|
arc: E1_H02E0601 V02S0601
|
|
arc: H00R0000 H02W0401
|
|
arc: N1_V01N0101 S3_V06N0203
|
|
arc: N1_V02N0001 H01E0001
|
|
arc: N1_V02N0101 S3_V06N0103
|
|
arc: N1_V02N0301 S3_V06N0003
|
|
arc: N1_V02N0501 H02W0501
|
|
arc: N1_V02N0701 H02E0701
|
|
arc: N3_V06N0103 H06E0103
|
|
arc: N3_V06N0203 S3_V06N0103
|
|
arc: N3_V06N0303 S3_V06N0203
|
|
arc: W1_H02W0401 N1_V01S0000
|
|
arc: A1 H02E0501
|
|
arc: B1 Q1
|
|
arc: C1 N1_V01S0100
|
|
arc: CE0 V02S0201
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D1 H02E0201
|
|
arc: F0 F5A_SLICE
|
|
arc: M0 H02E0601
|
|
arc: M1 H00R0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: N1_V02N0201 F0
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000100000000010
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R32C47:PLC2
|
|
arc: E1_H01E0101 E3_H06W0203
|
|
arc: E1_H02E0501 S1_V02N0501
|
|
arc: E1_H02E0701 W1_H02E0701
|
|
arc: N1_V02N0201 H02E0201
|
|
arc: N1_V02N0301 H02E0301
|
|
arc: N1_V02N0401 E3_H06W0203
|
|
arc: N1_V02N0501 E1_H02W0501
|
|
arc: N1_V02N0701 E1_H02W0701
|
|
arc: N3_V06N0203 S1_V02N0701
|
|
arc: W1_H02W0001 E1_H02W0501
|
|
arc: W1_H02W0401 S1_V02N0401
|
|
arc: W1_H02W0501 S1_V02N0501
|
|
arc: W1_H02W0601 V06N0303
|
|
arc: W1_H02W0701 V02N0701
|
|
arc: W3_H06W0203 E3_H06W0203
|
|
arc: W3_H06W0303 E3_H06W0203
|
|
|
|
.tile R32C48:PLC2
|
|
arc: E1_H02E0101 N3_V06S0103
|
|
arc: E1_H02E0301 N1_V01S0100
|
|
arc: E1_H02E0601 V02S0601
|
|
arc: H00L0000 V02S0201
|
|
arc: H00R0000 V02S0401
|
|
arc: H00R0100 H02W0501
|
|
arc: N1_V02N0101 S1_V02N0101
|
|
arc: N1_V02N0301 W1_H02E0301
|
|
arc: N1_V02N0401 H02W0401
|
|
arc: N1_V02N0501 N3_V06S0303
|
|
arc: N1_V02N0601 N1_V01S0000
|
|
arc: N1_V02N0701 H01E0101
|
|
arc: V00B0100 H02E0701
|
|
arc: V00T0000 H02W0201
|
|
arc: A0 V02S0701
|
|
arc: A4 F5
|
|
arc: A5 Q5
|
|
arc: A6 H02E0501
|
|
arc: B0 S1_V02N0101
|
|
arc: B4 E1_H02W0101
|
|
arc: B5 S1_V02N0701
|
|
arc: B6 V02S0701
|
|
arc: C0 N1_V01N0001
|
|
arc: C4 F6
|
|
arc: C5 V00B0100
|
|
arc: C6 V00T0100
|
|
arc: CE0 V02S0201
|
|
arc: CE1 V02S0201
|
|
arc: CE2 H00L0000
|
|
arc: CE3 H00L0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H00R0000
|
|
arc: D4 E1_H01W0100
|
|
arc: D5 V00B0000
|
|
arc: D6 H01W0000
|
|
arc: E1_H01E0001 F4
|
|
arc: E1_H01E0101 Q4
|
|
arc: F0 F5A_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: H01W0000 Q1
|
|
arc: M0 H02W0601
|
|
arc: M1 H02W0001
|
|
arc: M2 W1_H02E0601
|
|
arc: M3 E1_H02W0201
|
|
arc: M4 V00T0000
|
|
arc: M5 H00R0100
|
|
arc: M6 E1_H02W0401
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q2
|
|
arc: N1_V02N0201 F0
|
|
arc: V00B0000 Q6
|
|
arc: V00T0100 Q3
|
|
word: SLICEC.K1.INIT 1000010000100001
|
|
word: SLICED.K0.INIT 1000001001000001
|
|
word: SLICEA.K0.INIT 1010010100100001
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 1000000010100000
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R32C49:PLC2
|
|
arc: E1_H02E0401 S3_V06N0203
|
|
arc: E1_H02E0501 W3_H06E0303
|
|
arc: E1_H02E0701 N1_V02S0701
|
|
arc: H00R0000 V02S0401
|
|
arc: N1_V01N0101 S3_V06N0203
|
|
arc: N1_V02N0001 E1_H01W0000
|
|
arc: N1_V02N0101 S1_V02N0101
|
|
arc: N1_V02N0201 W3_H06E0103
|
|
arc: N1_V02N0301 E1_H01W0100
|
|
arc: N1_V02N0401 H01E0001
|
|
arc: N1_V02N0701 S3_V06N0203
|
|
arc: N3_V06N0303 S3_V06N0203
|
|
arc: S1_V02S0401 W3_H06E0203
|
|
arc: V00T0000 V02S0601
|
|
arc: V00T0100 H02E0101
|
|
arc: W1_H02W0001 V02S0001
|
|
arc: W1_H02W0201 S1_V02N0201
|
|
arc: W1_H02W0401 S3_V06N0203
|
|
arc: W1_H02W0501 W3_H06E0303
|
|
arc: W1_H02W0701 S3_V06N0203
|
|
arc: A0 W1_H02E0501
|
|
arc: A1 W1_H02E0501
|
|
arc: A4 F5
|
|
arc: A5 V02S0301
|
|
arc: A6 E1_H01W0000
|
|
arc: B0 V02S0301
|
|
arc: B3 Q3
|
|
arc: B4 V02S0701
|
|
arc: B5 S1_V02N0701
|
|
arc: C0 E1_H01W0000
|
|
arc: C1 E1_H01W0000
|
|
arc: C2 H00L0000
|
|
arc: C3 H00L0000
|
|
arc: C4 V00T0100
|
|
arc: C5 H02E0601
|
|
arc: CE1 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H01E0101
|
|
arc: D1 H01E0101
|
|
arc: D2 N1_V01S0000
|
|
arc: D3 N1_V01S0000
|
|
arc: D4 F0
|
|
arc: D5 V02S0601
|
|
arc: D6 E1_H01W0100
|
|
arc: E1_H01E0001 Q3
|
|
arc: E1_H01E0101 Q3
|
|
arc: F0 F5A_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: H00L0000 Q2
|
|
arc: H01W0100 F6
|
|
arc: LSR0 H02E0301
|
|
arc: M0 V00T0000
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXLSR1 LSR0
|
|
arc: N1_V01N0001 Q2
|
|
arc: V01S0100 F4
|
|
arc: W1_H02W0601 F6
|
|
word: SLICEB.K0.INIT 0000111100000000
|
|
word: SLICEB.K1.INIT 0011110000000000
|
|
word: SLICEA.K0.INIT 0010000000010000
|
|
word: SLICEA.K1.INIT 1010000001010000
|
|
word: SLICEC.K1.INIT 1000001011000011
|
|
word: SLICED.K0.INIT 0000000001010101
|
|
word: SLICEC.K0.INIT 1000001000000000
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
|
|
.tile R32C50:PLC2
|
|
arc: H00R0000 N1_V02S0601
|
|
arc: N1_V02N0001 H01E0001
|
|
arc: N1_V02N0101 H01E0101
|
|
arc: N1_V02N0201 S1_V02N0201
|
|
arc: N1_V02N0301 H01E0101
|
|
arc: N1_V02N0501 H01E0101
|
|
arc: N1_V02N0701 V01N0101
|
|
arc: S1_V02S0501 N1_V02S0501
|
|
arc: V00B0000 H02E0401
|
|
arc: V00B0100 V02N0101
|
|
arc: W1_H02W0201 W3_H06E0103
|
|
arc: W1_H02W0401 S1_V02N0401
|
|
arc: A5 H02E0701
|
|
arc: B5 V02S0501
|
|
arc: C5 V02N0001
|
|
arc: CE0 H00R0100
|
|
arc: CE1 H00R0100
|
|
arc: CE3 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D5 V00B0000
|
|
arc: F5 F5_SLICE
|
|
arc: H00R0100 F5
|
|
arc: H01W0000 Q6
|
|
arc: H01W0100 Q3
|
|
arc: LSR0 V00B0000
|
|
arc: LSR1 V00B0000
|
|
arc: M1 H02W0001
|
|
arc: M3 H00R0000
|
|
arc: M6 V00B0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR3 LSR1
|
|
arc: N1_V01N0001 Q1
|
|
arc: N1_V01N0101 Q3
|
|
arc: N1_V02N0401 Q6
|
|
arc: N1_V02N0601 Q6
|
|
arc: W1_H02W0101 Q1
|
|
word: SLICEC.K1.INIT 1111111110000000
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R32C51:PLC2
|
|
arc: N1_V02N0101 S1_V02N0101
|
|
arc: N1_V02N0201 S1_V02N0201
|
|
arc: N1_V02N0401 W1_H02E0401
|
|
arc: N1_V02N0501 W1_H02E0501
|
|
arc: S1_V02S0201 E1_H02W0201
|
|
arc: W1_H02W0001 N1_V02S0001
|
|
arc: A3 E1_H02W0501
|
|
arc: C3 W1_H02E0401
|
|
arc: CE0 V02N0201
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D3 V01S0100
|
|
arc: F0 F0_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: LSR1 V00T0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: N1_V02N0001 Q0
|
|
arc: N3_V06N0003 Q0
|
|
arc: V00T0100 F3
|
|
arc: V01S0100 Q0
|
|
arc: W3_H06W0003 Q0
|
|
word: SLICEB.K1.INIT 1111101011110000
|
|
word: SLICEA.K0.INIT 1111111111111111
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
|
|
.tile R32C52:PLC2
|
|
arc: N3_V06N0103 S3_V06N0103
|
|
|
|
.tile R32C53:PLC2
|
|
arc: N3_V06N0103 E3_H06W0103
|
|
arc: N3_V06N0303 S3_V06N0303
|
|
arc: W1_H02W0201 E3_H06W0103
|
|
arc: W1_H02W0501 S1_V02N0501
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
|
|
.tile R32C59:PLC2
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
|
|
.tile R32C65:PLC2
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
|
|
.tile R32C71:PLC2
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
|
|
.tile R32C77:PLC2
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
|
|
.tile R32C7:PLC2
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
|
|
.tile R32C83:PLC2
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
|
|
.tile R33C10:PLC2
|
|
arc: H01W0100 E3_H06W0303
|
|
|
|
.tile R33C11:PLC2
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
|
|
.tile R33C13:PLC2
|
|
arc: S3_V06S0003 N3_V06S0303
|
|
|
|
.tile R33C14:PLC2
|
|
arc: S3_V06S0203 N3_V06S0103
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
|
|
.tile R33C15:PLC2
|
|
arc: S3_V06S0003 N3_V06S0003
|
|
|
|
.tile R33C16:PLC2
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
|
|
.tile R33C17:PLC2
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
|
|
.tile R33C20:PLC2
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
|
|
.tile R33C22:PLC2
|
|
arc: W3_H06W0303 E3_H06W0203
|
|
|
|
.tile R33C23:PLC2
|
|
arc: W3_H06W0003 N3_V06S0003
|
|
|
|
.tile R33C26:PLC2
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
|
|
.tile R33C28:PLC2
|
|
arc: W3_H06W0203 E3_H06W0203
|
|
|
|
.tile R33C2:PLC2
|
|
arc: S3_V06S0103 H06W0103
|
|
arc: S3_V06S0303 N3_V06S0203
|
|
|
|
.tile R33C32:PLC2
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
|
|
.tile R33C34:PLC2
|
|
arc: W3_H06W0203 E3_H06W0203
|
|
|
|
.tile R33C35:PLC2
|
|
arc: E3_H06E0003 N3_V06S0003
|
|
|
|
.tile R33C38:PLC2
|
|
arc: W3_H06W0303 N3_V06S0303
|
|
|
|
.tile R33C39:PLC2
|
|
arc: N1_V02N0001 N3_V06S0003
|
|
arc: N1_V02N0101 V01N0101
|
|
|
|
.tile R33C3:PLC2
|
|
arc: N1_V02N0501 E3_H06W0303
|
|
arc: S3_V06S0003 N3_V06S0303
|
|
arc: S3_V06S0103 N3_V06S0003
|
|
arc: S3_V06S0203 N3_V06S0103
|
|
arc: S3_V06S0303 N3_V06S0203
|
|
|
|
.tile R33C40:PLC2
|
|
arc: N1_V02N0001 N1_V01S0000
|
|
arc: N1_V02N0201 S1_V02N0201
|
|
arc: W3_H06W0203 E3_H06W0203
|
|
|
|
.tile R33C41:PLC2
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: N1_V02N0001 E1_H02W0001
|
|
arc: N1_V02N0201 S1_V02N0701
|
|
arc: N1_V02N0601 S1_V02N0601
|
|
arc: N1_V02N0701 S1_V02N0601
|
|
arc: N3_V06N0303 S1_V02N0501
|
|
|
|
.tile R33C43:PLC2
|
|
arc: N1_V02N0001 E1_H02W0001
|
|
arc: N1_V02N0501 E1_H02W0501
|
|
arc: N1_V02N0601 N1_V01S0000
|
|
arc: W1_H02W0001 N3_V06S0003
|
|
|
|
.tile R33C44:PLC2
|
|
arc: E3_H06E0003 N3_V06S0003
|
|
arc: N1_V02N0001 S1_V02N0501
|
|
|
|
.tile R33C45:PLC2
|
|
arc: E1_H02E0101 V02N0101
|
|
arc: E1_H02E0201 N1_V02S0201
|
|
arc: N1_V02N0001 N3_V06S0003
|
|
arc: N1_V02N0501 N3_V06S0303
|
|
arc: W1_H02W0001 N3_V06S0003
|
|
arc: W1_H02W0501 N3_V06S0303
|
|
|
|
.tile R33C46:PLC2
|
|
arc: N1_V02N0001 E1_H02W0001
|
|
arc: N1_V02N0101 H02E0101
|
|
arc: N1_V02N0201 H02E0201
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
|
|
.tile R33C47:PLC2
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: N1_V02N0001 S1_V02N0001
|
|
arc: N1_V02N0701 S1_V02N0601
|
|
|
|
.tile R33C48:PLC2
|
|
arc: N1_V02N0401 E1_H02W0401
|
|
arc: W1_H02W0001 N3_V06S0003
|
|
|
|
.tile R33C49:PLC2
|
|
arc: E1_H02E0201 V02N0201
|
|
arc: E1_H02E0401 V02S0401
|
|
arc: N1_V02N0101 N1_V01S0100
|
|
|
|
.tile R33C50:PLC2
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: H00L0000 S1_V02N0001
|
|
arc: H00R0000 H02E0401
|
|
arc: H00R0100 V02S0501
|
|
arc: N1_V02N0001 H02W0001
|
|
arc: N1_V02N0101 S1_V02N0101
|
|
arc: V00T0000 H02E0201
|
|
arc: W1_H02W0401 N3_V06S0203
|
|
arc: A1 H00L0100
|
|
arc: A3 V02N0701
|
|
arc: A4 V02N0301
|
|
arc: B1 V02N0101
|
|
arc: B3 Q3
|
|
arc: B4 N1_V02S0701
|
|
arc: C1 F4
|
|
arc: C3 H02W0601
|
|
arc: C4 V00B0100
|
|
arc: CE1 H00R0100
|
|
arc: CE2 H00R0100
|
|
arc: CE3 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D1 V02N0201
|
|
arc: D3 V01S0100
|
|
arc: D4 H01W0000
|
|
arc: F0 F5A_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: H00L0100 Q3
|
|
arc: H01W0000 Q2
|
|
arc: M0 V00T0100
|
|
arc: M2 V00T0000
|
|
arc: M3 H00L0000
|
|
arc: M5 H00R0000
|
|
arc: M7 H02W0201
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0101 F0
|
|
arc: N1_V02N0201 F0
|
|
arc: V00B0100 Q5
|
|
arc: V00T0100 F3
|
|
arc: V01S0100 Q7
|
|
word: SLICEB.K1.INIT 1011000000001011
|
|
word: SLICEC.K0.INIT 1000001001000001
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 1011000000000000
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R33C51:PLC2
|
|
arc: E3_H06E0103 N1_V01S0100
|
|
arc: N1_V02N0201 N3_V06S0103
|
|
arc: N1_V02N0401 W1_H02E0401
|
|
arc: W1_H02W0001 N3_V06S0003
|
|
arc: W1_H02W0201 V02S0201
|
|
arc: W1_H02W0601 N3_V06S0303
|
|
|
|
.tile R33C52:PLC2
|
|
arc: W3_H06W0103 N3_V06S0103
|
|
|
|
.tile R33C53:PLC2
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: N3_V06N0003 S1_V02N0301
|
|
arc: N3_V06N0203 S1_V02N0401
|
|
|
|
.tile R33C56:PLC2
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
|
|
.tile R33C57:PLC2
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
|
|
.tile R33C59:PLC2
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
|
|
.tile R33C5:PLC2
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
|
|
.tile R33C62:PLC2
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
|
|
.tile R33C63:PLC2
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
|
|
.tile R33C65:PLC2
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
|
|
.tile R33C68:PLC2
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
|
|
.tile R33C69:PLC2
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
|
|
.tile R33C71:PLC2
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
|
|
.tile R33C74:PLC2
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
|
|
.tile R33C75:PLC2
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
|
|
.tile R33C77:PLC2
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
|
|
.tile R33C7:PLC2
|
|
arc: W3_H06W0203 E1_H01W0000
|
|
|
|
.tile R33C80:PLC2
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
|
|
.tile R33C81:PLC2
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
|
|
.tile R33C83:PLC2
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
|
|
.tile R33C86:PLC2
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
|
|
.tile R33C87:PLC2
|
|
arc: S3_V06S0303 W3_H06E0303
|
|
|
|
.tile R33C88:PLC2
|
|
arc: S3_V06S0303 N3_V06S0203
|
|
arc: V01S0100 N3_V06S0303
|
|
|
|
.tile R33C8:PLC2
|
|
arc: H01W0000 E3_H06W0103
|
|
|
|
.tile R33C9:PLC2
|
|
arc: W3_H06W0303 E1_H01W0100
|
|
|
|
.tile R35C13:PLC2
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
|
|
.tile R35C19:PLC2
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
|
|
.tile R35C25:PLC2
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
|
|
.tile R35C31:PLC2
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: N3_V06N0003 S3_V06N0303
|
|
|
|
.tile R35C34:PLC2
|
|
arc: N3_V06N0103 S3_V06N0103
|
|
|
|
.tile R35C37:PLC2
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: N3_V06N0303 S3_V06N0303
|
|
|
|
.tile R35C40:PLC2
|
|
arc: N1_V02N0201 H06E0103
|
|
arc: N3_V06N0303 S3_V06N0303
|
|
|
|
.tile R35C41:PLC2
|
|
arc: E3_H06E0003 V06N0003
|
|
arc: N1_V02N0501 S1_V02N0401
|
|
arc: N1_V02N0601 N1_V01S0000
|
|
arc: N1_V02N0701 E1_H02W0701
|
|
arc: N3_V06N0003 S3_V06N0003
|
|
arc: N3_V06N0203 E3_H06W0203
|
|
arc: N3_V06N0303 E3_H06W0303
|
|
|
|
.tile R35C43:PLC2
|
|
arc: E1_H01E0101 W3_H06E0203
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
arc: N3_V06N0103 W3_H06E0103
|
|
arc: W1_H02W0701 V06N0203
|
|
|
|
.tile R35C44:PLC2
|
|
arc: N1_V02N0501 H01E0101
|
|
arc: N3_V06N0003 H06E0003
|
|
arc: N3_V06N0303 H06W0303
|
|
|
|
.tile R35C46:PLC2
|
|
arc: N3_V06N0303 H06E0303
|
|
|
|
.tile R35C47:PLC2
|
|
arc: N1_V02N0001 E3_H06W0003
|
|
arc: N1_V02N0601 S1_V02N0301
|
|
arc: N3_V06N0003 S3_V06N0303
|
|
arc: N3_V06N0103 E3_H06W0103
|
|
arc: N3_V06N0203 E3_H06W0203
|
|
arc: N3_V06N0303 S3_V06N0303
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
arc: W3_H06W0303 E3_H06W0203
|
|
|
|
.tile R35C50:PLC2
|
|
arc: N1_V02N0001 S3_V06N0003
|
|
arc: N1_V02N0101 H06W0103
|
|
arc: N3_V06N0003 S3_V06N0303
|
|
|
|
.tile R35C53:PLC2
|
|
arc: N1_V02N0301 E3_H06W0003
|
|
arc: N1_V02N0401 S3_V06N0203
|
|
arc: N3_V06N0003 S3_V06N0303
|
|
arc: N3_V06N0103 E3_H06W0103
|
|
arc: N3_V06N0203 S3_V06N0103
|
|
arc: N3_V06N0303 S3_V06N0303
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
|
|
.tile R35C59:PLC2
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
|
|
.tile R35C64:PLC2
|
|
arc: N3_V06N0003 S3_V06N0003
|
|
|
|
.tile R35C65:PLC2
|
|
arc: N3_V06N0003 S3_V06N0303
|
|
arc: N3_V06N0203 S3_V06N0203
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
|
|
.tile R35C71:PLC2
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
|
|
.tile R35C77:PLC2
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
|
|
.tile R35C7:PLC2
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
|
|
.tile R35C83:PLC2
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
|
|
.tile R36C13:PLC2
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
|
|
.tile R36C19:PLC2
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
|
|
.tile R36C25:PLC2
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
arc: N3_V06N0103 S1_V02N0101
|
|
|
|
.tile R36C31:PLC2
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
|
|
.tile R36C34:PLC2
|
|
arc: N3_V06N0003 S3_V06N0003
|
|
|
|
.tile R36C37:PLC2
|
|
arc: E1_H01E0101 W3_H06E0203
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
arc: N3_V06N0203 W3_H06E0203
|
|
|
|
.tile R36C38:PLC2
|
|
arc: N1_V02N0101 H01E0101
|
|
|
|
.tile R36C40:PLC2
|
|
arc: N1_V02N0501 H06E0303
|
|
arc: N1_V02N0601 H06E0303
|
|
arc: N3_V06N0303 H06E0303
|
|
|
|
.tile R36C41:PLC2
|
|
arc: N3_V06N0303 S1_V02N0501
|
|
|
|
.tile R36C43:PLC2
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
|
|
.tile R36C46:PLC2
|
|
arc: N3_V06N0303 H06E0303
|
|
|
|
.tile R36C49:PLC2
|
|
arc: E1_H01E0001 W3_H06E0003
|
|
arc: N3_V06N0303 W3_H06E0303
|
|
|
|
.tile R36C50:PLC2
|
|
arc: N1_V02N0401 H01E0001
|
|
|
|
.tile R36C7:PLC2
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
|
|
.tile R36C88:PLC2
|
|
arc: E1_H02E0701 N1_V02S0701
|
|
|
|
.tile R37C13:PLC2
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
|
|
.tile R37C17:PLC2
|
|
arc: N3_V06N0103 S3_V06N0103
|
|
|
|
.tile R37C19:PLC2
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
|
|
.tile R37C22:PLC2
|
|
arc: N3_V06N0003 S3_V06N0003
|
|
|
|
.tile R37C23:PLC2
|
|
arc: N3_V06N0003 S3_V06N0303
|
|
|
|
.tile R37C25:PLC2
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: N3_V06N0103 S3_V06N0103
|
|
|
|
.tile R37C29:PLC2
|
|
arc: N3_V06N0203 S3_V06N0203
|
|
|
|
.tile R37C31:PLC2
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
|
|
.tile R37C34:PLC2
|
|
arc: N3_V06N0003 S3_V06N0303
|
|
|
|
.tile R37C35:PLC2
|
|
arc: N3_V06N0103 S3_V06N0103
|
|
|
|
.tile R37C37:PLC2
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
arc: N3_V06N0103 S3_V06N0103
|
|
arc: N3_V06N0203 W3_H06E0203
|
|
|
|
.tile R37C38:PLC2
|
|
arc: N3_V06N0003 S3_V06N0303
|
|
|
|
.tile R37C40:PLC2
|
|
arc: N3_V06N0203 H06E0203
|
|
|
|
.tile R37C41:PLC2
|
|
arc: N1_V02N0401 S3_V06N0203
|
|
arc: N3_V06N0203 S3_V06N0103
|
|
|
|
.tile R37C43:PLC2
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
arc: N3_V06N0203 W3_H06E0203
|
|
|
|
.tile R37C44:PLC2
|
|
arc: N3_V06N0103 S3_V06N0103
|
|
|
|
.tile R37C47:PLC2
|
|
arc: N1_V02N0301 S3_V06N0003
|
|
arc: N3_V06N0003 S3_V06N0003
|
|
arc: N3_V06N0103 S3_V06N0103
|
|
arc: N3_V06N0203 S3_V06N0103
|
|
|
|
.tile R37C49:PLC2
|
|
arc: N3_V06N0303 W3_H06E0303
|
|
|
|
.tile R37C50:PLC2
|
|
arc: N3_V06N0103 S3_V06N0003
|
|
|
|
.tile R37C53:PLC2
|
|
arc: N3_V06N0003 S3_V06N0303
|
|
arc: N3_V06N0103 S3_V06N0003
|
|
arc: N3_V06N0203 E3_H06W0203
|
|
|
|
.tile R37C59:PLC2
|
|
arc: N3_V06N0103 S3_V06N0103
|
|
arc: N3_V06N0303 S3_V06N0203
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
|
|
.tile R37C64:PLC2
|
|
arc: N3_V06N0303 S3_V06N0303
|
|
|
|
.tile R37C65:PLC2
|
|
arc: N3_V06N0203 S3_V06N0103
|
|
arc: N3_V06N0303 S3_V06N0203
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
|
|
.tile R37C71:PLC2
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
|
|
.tile R37C77:PLC2
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
|
|
.tile R37C7:PLC2
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
|
|
.tile R37C83:PLC2
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
|
|
.tile R37C88:PLC2
|
|
arc: E1_H02E0101 V06S0103
|
|
|
|
.tile R38C13:PLC2
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: N3_V06N0203 S3_V06N0103
|
|
|
|
.tile R38C19:PLC2
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
|
|
.tile R38C25:PLC2
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: N1_V02N0101 S3_V06N0103
|
|
arc: N3_V06N0003 S3_V06N0303
|
|
|
|
.tile R38C31:PLC2
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
|
|
.tile R38C32:PLC2
|
|
arc: N3_V06N0103 S3_V06N0003
|
|
|
|
.tile R38C37:PLC2
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: E3_H06E0203 W3_H06E0103
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.tile R38C40:PLC2
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arc: N3_V06N0003 H06E0003
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arc: N3_V06N0103 S3_V06N0103
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arc: N3_V06N0203 H06E0203
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.tile R38C41:PLC2
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arc: N1_V02N0501 S3_V06N0303
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arc: N3_V06N0003 S3_V06N0003
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.tile R38C43:PLC2
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arc: N3_V06N0103 S3_V06N0003
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arc: N3_V06N0203 W3_H06E0203
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.tile R38C45:PLC2
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arc: N3_V06N0003 S1_V02N0301
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.tile R38C46:PLC2
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arc: N3_V06N0003 S3_V06N0003
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arc: N3_V06N0103 S3_V06N0003
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arc: N3_V06N0203 S3_V06N0103
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.tile R38C49:PLC2
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arc: N3_V06N0203 S3_V06N0103
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.tile R38C52:PLC2
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arc: N3_V06N0103 S3_V06N0003
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.tile R38C53:PLC2
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arc: N3_V06N0303 S3_V06N0203
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.tile R38C7:PLC2
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arc: E3_H06E0103 W3_H06E0003
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arc: E3_H06E0303 W3_H06E0303
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.tile R39C13:PLC2
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arc: S3_V06S0103 N3_V06S0003
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.tile R39C14:PLC2
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arc: S3_V06S0303 N3_V06S0203
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.tile R39C15:PLC2
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arc: S3_V06S0103 N3_V06S0003
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.tile R39C2:PLC2
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arc: S3_V06S0103 N3_V06S0103
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arc: S3_V06S0303 N3_V06S0303
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.tile R39C3:PLC2
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arc: S3_V06S0003 N3_V06S0003
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arc: S3_V06S0103 N3_V06S0103
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arc: S3_V06S0203 N3_V06S0203
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arc: S3_V06S0303 N3_V06S0303
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.tile R39C87:PLC2
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arc: S3_V06S0303 N3_V06S0303
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.tile R39C88:PLC2
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arc: S3_V06S0303 N3_V06S0303
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.tile R3C13:PLC2
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arc: N1_V02N0701 S3_V06N0203
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.tile R3C16:PLC2
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arc: N1_V02N0501 S3_V06N0303
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.tile R3C18:PLC2
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arc: N1_V02N0701 S3_V06N0203
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.tile R3C19:PLC2
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arc: N1_V02N0501 S3_V06N0303
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.tile R3C22:PLC2
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arc: N1_V02N0001 H06W0003
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arc: N1_V02N0701 S3_V06N0203
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.tile R3C23:PLC2
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arc: N1_V02N0501 S3_V06N0303
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.tile R3C25:PLC2
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arc: W3_H06W0003 S3_V06N0003
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.tile R3C27:PLC2
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arc: N1_V02N0701 S3_V06N0203
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.tile R3C31:PLC2
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arc: N1_V02N0501 S3_V06N0303
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.tile R3C41:PLC2
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arc: N1_V02N0701 S3_V06N0203
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.tile R3C45:PLC2
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arc: S3_V06S0103 N1_V02S0101
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.tile R3C46:PLC2
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arc: S3_V06S0003 N1_V02S0001
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.tile R3C48:PLC2
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arc: N1_V02N0501 S3_V06N0303
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arc: S3_V06S0103 N1_V02S0201
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.tile R3C49:PLC2
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arc: S3_V06S0003 N1_V02S0301
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.tile R3C51:PLC2
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arc: S3_V06S0003 N1_V02S0001
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.tile R3C52:PLC2
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arc: S3_V06S0103 N1_V02S0201
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.tile R3C53:PLC2
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arc: N1_V02N0501 S3_V06N0303
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.tile R3C56:PLC2
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arc: N1_V02N0701 S1_V02N0701
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.tile R3C58:PLC2
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arc: N1_V02N0701 S3_V06N0203
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.tile R3C5:PLC2
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arc: N1_V02N0501 S3_V06N0303
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.tile R3C65:PLC2
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arc: N1_V02N0701 S3_V06N0203
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.tile R3C67:PLC2
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arc: N1_V02N0701 S3_V06N0203
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.tile R3C68:PLC2
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arc: N1_V02N0501 S3_V06N0303
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.tile R3C69:PLC2
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arc: N1_V02N0701 S3_V06N0203
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.tile R3C6:PLC2
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arc: N1_V02N0501 S3_V06N0303
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.tile R3C73:PLC2
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arc: N1_V02N0701 S3_V06N0203
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.tile R3C75:PLC2
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arc: N1_V02N0501 S3_V06N0303
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.tile R3C80:PLC2
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arc: N1_V02N0501 S3_V06N0303
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.tile R3C83:PLC2
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arc: N1_V02N0701 S3_V06N0203
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.tile R3C8:PLC2
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arc: N1_V02N0701 S3_V06N0203
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.tile R40C13:PLC2
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arc: E3_H06E0303 W3_H06E0303
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.tile R40C15:PLC2
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arc: E3_H06E0003 W3_H06E0303
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.tile R40C16:PLC2
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arc: N3_V06N0103 S3_V06N0103
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.tile R40C17:PLC2
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arc: N3_V06N0303 S3_V06N0303
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.tile R40C19:PLC2
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arc: E3_H06E0303 W3_H06E0303
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.tile R40C20:PLC2
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arc: S3_V06S0203 N3_V06S0103
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.tile R40C21:PLC2
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arc: E3_H06E0103 W3_H06E0003
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.tile R40C22:PLC2
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arc: N3_V06N0203 S3_V06N0203
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.tile R40C23:PLC2
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arc: N3_V06N0303 S3_V06N0203
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.tile R40C24:PLC2
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arc: N3_V06N0103 H06E0103
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.tile R40C25:PLC2
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arc: E3_H06E0003 W3_H06E0303
|
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arc: N3_V06N0203 S3_V06N0203
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.tile R40C26:PLC2
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arc: N3_V06N0303 S3_V06N0203
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.tile R40C2:PLC2
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arc: S3_V06S0203 N3_V06S0103
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.tile R40C30:PLC2
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arc: N3_V06N0103 S3_V06N0003
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.tile R40C31:PLC2
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arc: E3_H06E0003 W3_H06E0003
|
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arc: N3_V06N0103 S3_V06N0003
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.tile R40C32:PLC2
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arc: N3_V06N0003 S3_V06N0303
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.tile R40C34:PLC2
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arc: N3_V06N0003 H06E0003
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arc: N3_V06N0103 S3_V06N0003
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.tile R40C35:PLC2
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arc: N3_V06N0003 S3_V06N0303
|
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arc: N3_V06N0203 S3_V06N0103
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.tile R40C36:PLC2
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arc: N3_V06N0303 S3_V06N0303
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.tile R40C37:PLC2
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arc: N3_V06N0003 S3_V06N0303
|
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arc: N3_V06N0103 S3_V06N0003
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.tile R40C38:PLC2
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arc: N3_V06N0303 S3_V06N0303
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.tile R40C39:PLC2
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arc: N3_V06N0203 S3_V06N0203
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.tile R40C3:PLC2
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arc: E3_H06E0203 W1_H02E0701
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.tile R40C40:PLC2
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arc: N3_V06N0003 S3_V06N0003
|
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arc: N3_V06N0103 S3_V06N0003
|
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arc: N3_V06N0303 S3_V06N0203
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.tile R40C41:PLC2
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arc: N3_V06N0103 S3_V06N0003
|
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arc: N3_V06N0203 S3_V06N0103
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.tile R40C42:PLC2
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arc: N3_V06N0203 S3_V06N0103
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.tile R40C43:PLC2
|
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arc: N3_V06N0003 S3_V06N0003
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.tile R40C44:PLC2
|
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arc: N3_V06N0103 S3_V06N0003
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.tile R40C45:PLC2
|
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arc: N1_V02N0301 S3_V06N0003
|
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arc: N3_V06N0103 S3_V06N0003
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.tile R40C46:PLC2
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arc: N3_V06N0103 S3_V06N0103
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.tile R40C47:PLC2
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arc: N3_V06N0203 S3_V06N0103
|
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arc: N3_V06N0303 S3_V06N0303
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.tile R40C48:PLC2
|
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arc: N3_V06N0103 S3_V06N0103
|
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arc: N3_V06N0203 S3_V06N0103
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.tile R40C49:PLC2
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arc: N3_V06N0103 S3_V06N0103
|
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arc: N3_V06N0303 S3_V06N0203
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.tile R40C50:PLC2
|
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arc: N3_V06N0103 S3_V06N0003
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.tile R40C51:PLC2
|
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arc: N3_V06N0103 S3_V06N0103
|
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arc: N3_V06N0203 S3_V06N0103
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.tile R40C52:PLC2
|
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arc: N3_V06N0103 S3_V06N0003
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.tile R40C53:PLC2
|
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arc: N3_V06N0003 S3_V06N0303
|
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arc: N3_V06N0203 S3_V06N0103
|
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arc: N3_V06N0303 E3_H06W0303
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.tile R40C55:PLC2
|
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arc: N3_V06N0003 S3_V06N0003
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.tile R40C58:PLC2
|
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arc: N3_V06N0003 S3_V06N0003
|
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arc: N3_V06N0103 S3_V06N0103
|
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.tile R40C59:PLC2
|
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arc: W3_H06W0303 E3_H06W0303
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.tile R40C61:PLC2
|
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arc: N3_V06N0003 S3_V06N0003
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.tile R40C64:PLC2
|
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arc: N3_V06N0203 S3_V06N0103
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.tile R40C65:PLC2
|
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arc: N3_V06N0003 S3_V06N0003
|
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arc: W3_H06W0303 E3_H06W0303
|
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.tile R40C71:PLC2
|
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arc: W3_H06W0303 E3_H06W0303
|
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.tile R40C77:PLC2
|
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arc: W3_H06W0303 E3_H06W0303
|
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.tile R40C7:PLC2
|
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arc: E3_H06E0303 W3_H06E0303
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.tile R40C83:PLC2
|
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arc: W3_H06W0303 E3_H06W0303
|
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.tile R40C87:PLC2
|
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arc: S3_V06S0103 N3_V06S0003
|
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arc: S3_V06S0303 N3_V06S0303
|
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.tile R40C88:PLC2
|
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arc: E1_H02E0501 N3_V06S0303
|
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arc: S3_V06S0103 N3_V06S0003
|
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.tile R40C9:PLC2
|
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arc: E3_H06E0303 W3_H06E0203
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.tile R41C13:PLC2
|
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arc: E3_H06E0003 W3_H06E0003
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.tile R41C19:PLC2
|
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arc: E3_H06E0103 W3_H06E0003
|
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.tile R41C25:PLC2
|
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arc: E3_H06E0203 W3_H06E0103
|
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.tile R41C31:PLC2
|
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arc: E3_H06E0203 W3_H06E0203
|
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arc: N3_V06N0303 S3_V06N0303
|
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.tile R41C34:PLC2
|
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arc: N3_V06N0103 S3_V06N0103
|
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.tile R41C37:PLC2
|
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arc: E3_H06E0303 W3_H06E0203
|
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arc: N3_V06N0303 H06W0303
|
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.tile R41C40:PLC2
|
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arc: N3_V06N0303 H06E0303
|
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arc: W3_H06W0303 E3_H06W0203
|
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.tile R41C41:PLC2
|
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arc: N3_V06N0003 S3_V06N0003
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.tile R41C46:PLC2
|
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arc: W3_H06W0203 E3_H06W0203
|
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.tile R41C47:PLC2
|
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arc: N3_V06N0303 S3_V06N0303
|
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.tile R41C50:PLC2
|
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arc: N3_V06N0003 S3_V06N0003
|
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arc: N3_V06N0303 S3_V06N0303
|
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.tile R41C52:PLC2
|
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arc: W3_H06W0203 E3_H06W0203
|
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.tile R41C53:PLC2
|
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arc: N3_V06N0103 S3_V06N0103
|
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arc: N3_V06N0203 S3_V06N0203
|
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arc: N3_V06N0303 S1_V02N0501
|
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.tile R41C58:PLC2
|
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arc: W3_H06W0203 E3_H06W0203
|
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.tile R41C64:PLC2
|
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arc: N3_V06N0003 S3_V06N0303
|
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arc: W3_H06W0203 E3_H06W0203
|
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.tile R41C65:PLC2
|
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arc: N3_V06N0203 E3_H06W0203
|
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arc: N3_V06N0303 E3_H06W0303
|
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.tile R41C70:PLC2
|
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arc: W3_H06W0203 E3_H06W0203
|
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.tile R41C71:PLC2
|
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arc: W3_H06W0203 E3_H06W0103
|
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arc: W3_H06W0303 E3_H06W0203
|
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.tile R41C76:PLC2
|
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arc: W3_H06W0203 E3_H06W0103
|
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.tile R41C77:PLC2
|
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arc: W3_H06W0103 E3_H06W0003
|
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arc: W3_H06W0203 E3_H06W0103
|
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.tile R41C7:PLC2
|
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arc: E3_H06E0003 W3_H06E0303
|
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.tile R41C82:PLC2
|
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arc: W3_H06W0103 E3_H06W0103
|
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.tile R41C83:PLC2
|
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arc: W3_H06W0003 E3_H06W0303
|
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arc: W3_H06W0103 E3_H06W0003
|
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.tile R41C88:PLC2
|
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arc: W3_H06W0103 E1_H01W0100
|
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.tile R42C13:PLC2
|
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arc: E3_H06E0303 W3_H06E0303
|
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.tile R42C19:PLC2
|
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arc: E3_H06E0003 W3_H06E0303
|
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.tile R42C25:PLC2
|
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arc: E3_H06E0003 W3_H06E0003
|
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.tile R42C31:PLC2
|
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arc: E3_H06E0003 W3_H06E0003
|
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.tile R42C34:PLC2
|
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arc: N3_V06N0003 H06E0003
|
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.tile R42C7:PLC2
|
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arc: E3_H06E0303 W3_H06E0303
|
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.tile R42C87:PLC2
|
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arc: E1_H02E0501 V06S0303
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.tile R43C13:PLC2
|
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arc: E3_H06E0003 W3_H06E0303
|
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.tile R43C17:PLC2
|
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arc: N3_V06N0103 S3_V06N0003
|
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.tile R43C19:PLC2
|
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arc: E3_H06E0003 W3_H06E0003
|
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.tile R43C22:PLC2
|
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arc: N3_V06N0003 S3_V06N0303
|
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.tile R43C23:PLC2
|
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arc: N3_V06N0303 S3_V06N0203
|
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.tile R43C25:PLC2
|
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arc: E3_H06E0003 W3_H06E0003
|
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arc: N3_V06N0103 S3_V06N0103
|
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.tile R43C29:PLC2
|
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arc: N3_V06N0203 S3_V06N0203
|
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.tile R43C31:PLC2
|
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arc: E3_H06E0103 W3_H06E0003
|
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.tile R43C34:PLC2
|
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arc: N3_V06N0303 S3_V06N0303
|
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.tile R43C35:PLC2
|
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arc: N3_V06N0103 S3_V06N0103
|
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.tile R43C37:PLC2
|
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arc: N3_V06N0103 W3_H06E0103
|
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.tile R43C38:PLC2
|
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arc: N3_V06N0303 S3_V06N0203
|
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.tile R43C41:PLC2
|
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arc: N3_V06N0103 E3_H06W0103
|
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arc: N3_V06N0203 S3_V06N0203
|
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.tile R43C44:PLC2
|
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arc: N3_V06N0103 H06W0103
|
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.tile R43C47:PLC2
|
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arc: N3_V06N0003 E3_H06W0003
|
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arc: N3_V06N0103 S3_V06N0103
|
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arc: W3_H06W0103 E3_H06W0003
|
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.tile R43C50:PLC2
|
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arc: N3_V06N0003 H06W0003
|
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.tile R43C53:PLC2
|
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arc: N1_V02N0501 E3_H06W0303
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arc: N3_V06N0003 S3_V06N0003
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arc: N3_V06N0303 S3_V06N0203
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arc: W3_H06W0003 E3_H06W0303
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.tile R43C59:PLC2
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arc: N3_V06N0103 S3_V06N0003
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arc: N3_V06N0203 S3_V06N0103
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arc: W3_H06W0303 E3_H06W0303
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.tile R43C64:PLC2
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arc: N3_V06N0303 S3_V06N0203
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.tile R43C65:PLC2
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arc: N3_V06N0103 S3_V06N0003
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arc: N3_V06N0203 S3_V06N0203
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arc: W3_H06W0303 E3_H06W0203
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.tile R43C71:PLC2
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arc: W3_H06W0203 E3_H06W0103
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.tile R43C77:PLC2
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arc: W3_H06W0103 E3_H06W0003
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.tile R43C7:PLC2
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arc: E3_H06E0303 W3_H06E0303
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.tile R43C83:PLC2
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arc: W3_H06W0003 E3_H06W0303
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.tile R44C13:PLC2
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arc: E3_H06E0103 W3_H06E0003
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arc: N3_V06N0103 S3_V06N0003
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.tile R44C19:PLC2
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arc: E3_H06E0103 W3_H06E0103
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.tile R44C25:PLC2
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arc: N3_V06N0103 W3_H06E0103
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arc: N3_V06N0303 S3_V06N0203
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.tile R44C32:PLC2
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arc: N3_V06N0003 S3_V06N0303
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.tile R44C40:PLC2
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arc: N3_V06N0103 S3_V06N0103
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.tile R44C41:PLC2
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arc: N3_V06N0003 S1_V02N0301
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arc: N3_V06N0303 S3_V06N0303
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.tile R44C43:PLC2
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arc: N3_V06N0003 S3_V06N0003
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.tile R44C46:PLC2
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arc: N3_V06N0003 S3_V06N0003
|
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arc: N3_V06N0103 S1_V02N0101
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.tile R44C49:PLC2
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arc: N3_V06N0103 S3_V06N0103
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.tile R44C52:PLC2
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arc: N3_V06N0003 S3_V06N0003
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.tile R44C53:PLC2
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arc: N3_V06N0203 E3_H06W0203
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.tile R44C59:PLC2
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arc: W3_H06W0203 E3_H06W0103
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.tile R44C65:PLC2
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arc: W3_H06W0103 E3_H06W0003
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.tile R44C71:PLC2
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arc: W3_H06W0003 E3_H06W0303
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.tile R44C77:PLC2
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arc: W3_H06W0303 E3_H06W0303
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.tile R44C7:PLC2
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arc: E3_H06E0003 W3_H06E0303
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.tile R44C83:PLC2
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arc: W3_H06W0303 E3_H06W0303
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.tile R45C13:PLC2
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arc: S3_V06S0103 N3_V06S0103
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.tile R45C14:PLC2
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arc: S3_V06S0303 N3_V06S0303
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.tile R45C15:PLC2
|
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arc: S3_V06S0203 N3_V06S0103
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.tile R45C2:PLC2
|
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arc: S3_V06S0203 N3_V06S0103
|
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arc: S3_V06S0303 N3_V06S0303
|
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.tile R45C3:PLC2
|
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arc: S3_V06S0003 N3_V06S0003
|
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arc: S3_V06S0103 N3_V06S0103
|
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arc: S3_V06S0203 N3_V06S0203
|
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arc: S3_V06S0303 N3_V06S0303
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.tile R45C88:PLC2
|
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arc: S3_V06S0303 N3_V06S0303
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.tile R47C13:PLC2
|
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arc: E3_H06E0303 W3_H06E0303
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.tile R47C19:PLC2
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arc: E3_H06E0003 W3_H06E0303
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.tile R47C25:PLC2
|
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arc: E3_H06E0103 W3_H06E0003
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.tile R47C31:PLC2
|
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arc: E3_H06E0103 W3_H06E0103
|
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arc: N3_V06N0303 S3_V06N0303
|
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.tile R47C34:PLC2
|
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arc: N3_V06N0103 H06E0103
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.tile R47C41:PLC2
|
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arc: N3_V06N0003 S3_V06N0003
|
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.tile R47C47:PLC2
|
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arc: N3_V06N0303 S3_V06N0203
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.tile R47C50:PLC2
|
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arc: N3_V06N0003 S3_V06N0303
|
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arc: N3_V06N0303 H06W0303
|
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.tile R47C53:PLC2
|
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arc: N3_V06N0103 S3_V06N0003
|
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arc: N3_V06N0203 S3_V06N0103
|
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arc: W3_H06W0303 E3_H06W0203
|
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.tile R47C59:PLC2
|
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arc: W3_H06W0203 E3_H06W0203
|
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.tile R47C64:PLC2
|
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arc: N3_V06N0303 S3_V06N0303
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.tile R47C65:PLC2
|
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arc: W3_H06W0203 E3_H06W0103
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.tile R47C71:PLC2
|
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arc: W3_H06W0103 E3_H06W0003
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.tile R47C77:PLC2
|
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arc: W3_H06W0003 E3_H06W0003
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.tile R47C7:PLC2
|
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arc: E3_H06E0303 W3_H06E0303
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.tile R47C83:PLC2
|
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arc: W3_H06W0003 E3_H06W0303
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.tile R49C13:PLC2
|
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arc: E3_H06E0103 W3_H06E0003
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.tile R49C17:PLC2
|
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arc: N3_V06N0003 S3_V06N0303
|
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.tile R49C19:PLC2
|
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arc: E3_H06E0103 W3_H06E0103
|
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.tile R49C22:PLC2
|
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arc: N3_V06N0303 S3_V06N0203
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.tile R49C23:PLC2
|
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arc: N3_V06N0203 S3_V06N0203
|
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.tile R49C25:PLC2
|
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arc: E3_H06E0203 W3_H06E0103
|
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arc: N3_V06N0103 S3_V06N0003
|
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.tile R49C29:PLC2
|
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arc: N3_V06N0203 S3_V06N0203
|
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.tile R49C31:PLC2
|
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arc: E3_H06E0303 W3_H06E0203
|
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.tile R49C34:PLC2
|
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arc: N3_V06N0303 H06E0303
|
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.tile R49C35:PLC2
|
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arc: N3_V06N0103 S3_V06N0103
|
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.tile R49C38:PLC2
|
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arc: N3_V06N0203 S3_V06N0203
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.tile R49C41:PLC2
|
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arc: N3_V06N0203 S3_V06N0103
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.tile R49C47:PLC2
|
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arc: N3_V06N0103 S3_V06N0103
|
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.tile R49C53:PLC2
|
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arc: N3_V06N0003 S3_V06N0303
|
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arc: N3_V06N0203 E3_H06W0203
|
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.tile R49C59:PLC2
|
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arc: N3_V06N0003 S3_V06N0003
|
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arc: N3_V06N0103 S3_V06N0103
|
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arc: W3_H06W0203 E3_H06W0103
|
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.tile R49C64:PLC2
|
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arc: N3_V06N0203 E3_H06W0203
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.tile R49C65:PLC2
|
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arc: N3_V06N0003 S3_V06N0303
|
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arc: N3_V06N0203 S3_V06N0103
|
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arc: W3_H06W0103 E3_H06W0103
|
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.tile R49C70:PLC2
|
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arc: W3_H06W0203 E3_H06W0103
|
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.tile R49C71:PLC2
|
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arc: W3_H06W0103 E3_H06W0003
|
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.tile R49C76:PLC2
|
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arc: W3_H06W0103 E3_H06W0103
|
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.tile R49C77:PLC2
|
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arc: W3_H06W0003 E3_H06W0303
|
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.tile R49C7:PLC2
|
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arc: E3_H06E0003 W3_H06E0303
|
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.tile R49C82:PLC2
|
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arc: W3_H06W0103 E3_H06W0103
|
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.tile R49C83:PLC2
|
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arc: W3_H06W0303 E3_H06W0303
|
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.tile R49C88:PLC2
|
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arc: W3_H06W0103 E1_H01W0100
|
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.tile R50C13:PLC2
|
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arc: E3_H06E0303 W3_H06E0303
|
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arc: N3_V06N0003 S3_V06N0303
|
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.tile R50C19:PLC2
|
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arc: E3_H06E0303 W3_H06E0303
|
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.tile R50C25:PLC2
|
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arc: E3_H06E0003 W3_H06E0303
|
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arc: N3_V06N0203 S3_V06N0103
|
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.tile R50C31:PLC2
|
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arc: E3_H06E0103 W3_H06E0003
|
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.tile R50C32:PLC2
|
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arc: N3_V06N0303 H06W0303
|
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.tile R50C35:PLC2
|
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arc: W3_H06W0303 E3_H06W0303
|
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.tile R50C37:PLC2
|
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arc: E3_H06E0203 W3_H06E0103
|
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.tile R50C40:PLC2
|
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arc: N3_V06N0103 S3_V06N0003
|
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.tile R50C41:PLC2
|
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arc: N3_V06N0303 S3_V06N0303
|
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arc: W3_H06W0303 E3_H06W0303
|
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.tile R50C43:PLC2
|
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arc: E3_H06E0303 W3_H06E0203
|
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arc: N3_V06N0003 S3_V06N0003
|
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.tile R50C46:PLC2
|
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arc: N3_V06N0003 S3_V06N0003
|
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.tile R50C47:PLC2
|
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arc: W3_H06W0303 E3_H06W0203
|
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.tile R50C49:PLC2
|
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arc: E3_H06E0003 W3_H06E0303
|
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arc: N3_V06N0103 S3_V06N0003
|
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.tile R50C52:PLC2
|
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arc: N3_V06N0003 H06E0003
|
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.tile R50C53:PLC2
|
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arc: W3_H06W0203 E3_H06W0203
|
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.tile R50C59:PLC2
|
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arc: W3_H06W0203 E3_H06W0203
|
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.tile R50C65:PLC2
|
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arc: W3_H06W0203 E3_H06W0103
|
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.tile R50C71:PLC2
|
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arc: W3_H06W0103 E3_H06W0103
|
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.tile R50C77:PLC2
|
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arc: W3_H06W0103 E3_H06W0003
|
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.tile R50C7:PLC2
|
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arc: E3_H06E0303 W3_H06E0303
|
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.tile R50C83:PLC2
|
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arc: W3_H06W0003 E3_H06W0303
|
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.tile R50C88:PLC2
|
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arc: E1_H02E0701 S1_V02N0701
|
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.tile R51C13:PLC2
|
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arc: S3_V06S0103 N3_V06S0103
|
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.tile R51C14:PLC2
|
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arc: S3_V06S0303 N3_V06S0303
|
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.tile R51C15:PLC2
|
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arc: S3_V06S0203 N3_V06S0203
|
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.tile R51C2:PLC2
|
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arc: S3_V06S0303 N3_V06S0203
|
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arc: W1_H02W0601 N3_V06S0303
|
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|
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.tile R51C3:PLC2
|
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arc: S3_V06S0003 N3_V06S0003
|
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arc: S3_V06S0103 N3_V06S0103
|
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arc: S3_V06S0203 N3_V06S0203
|
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arc: S3_V06S0303 N3_V06S0303
|
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.tile R51C88:PLC2
|
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arc: S3_V06S0303 N3_V06S0303
|
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.tile R52C13:PLC2
|
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arc: E3_H06E0303 W3_H06E0303
|
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.tile R52C16:PLC2
|
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arc: N3_V06N0103 S3_V06N0103
|
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.tile R52C17:PLC2
|
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arc: N3_V06N0203 S3_V06N0203
|
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|
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.tile R52C19:PLC2
|
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arc: E3_H06E0303 W3_H06E0303
|
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.tile R52C20:PLC2
|
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arc: S3_V06S0003 N3_V06S0303
|
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.tile R52C22:PLC2
|
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arc: N3_V06N0103 S3_V06N0103
|
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.tile R52C23:PLC2
|
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arc: N3_V06N0203 S3_V06N0103
|
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.tile R52C25:PLC2
|
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arc: E3_H06E0003 W3_H06E0303
|
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arc: N3_V06N0103 S3_V06N0103
|
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|
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.tile R52C26:PLC2
|
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arc: N3_V06N0103 S3_V06N0003
|
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.tile R52C2:PLC2
|
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arc: W1_H02W0701 N3_V06S0203
|
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.tile R52C30:PLC2
|
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arc: N3_V06N0003 S3_V06N0303
|
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|
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.tile R52C31:PLC2
|
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arc: E3_H06E0103 W3_H06E0003
|
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arc: N3_V06N0303 S3_V06N0303
|
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|
|
.tile R52C32:PLC2
|
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arc: N3_V06N0303 S3_V06N0203
|
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.tile R52C34:PLC2
|
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arc: N3_V06N0003 S3_V06N0003
|
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|
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.tile R52C35:PLC2
|
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arc: N3_V06N0003 S3_V06N0303
|
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arc: N3_V06N0303 S3_V06N0203
|
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|
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.tile R52C36:PLC2
|
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arc: N3_V06N0303 S3_V06N0203
|
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|
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.tile R52C37:PLC2
|
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arc: E3_H06E0103 W3_H06E0103
|
|
arc: N3_V06N0003 S3_V06N0303
|
|
arc: N3_V06N0303 S3_V06N0203
|
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|
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.tile R52C38:PLC2
|
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arc: N3_V06N0203 S3_V06N0203
|
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|
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.tile R52C39:PLC2
|
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arc: N3_V06N0203 S3_V06N0203
|
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|
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.tile R52C40:PLC2
|
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arc: N3_V06N0203 S3_V06N0203
|
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|
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.tile R52C41:PLC2
|
|
arc: N3_V06N0003 S3_V06N0303
|
|
arc: N3_V06N0103 S3_V06N0003
|
|
arc: N3_V06N0303 E3_H06W0303
|
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|
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.tile R52C42:PLC2
|
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arc: N3_V06N0003 S3_V06N0303
|
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|
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.tile R52C43:PLC2
|
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arc: E3_H06E0203 W3_H06E0103
|
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arc: N3_V06N0003 S3_V06N0303
|
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|
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.tile R52C44:PLC2
|
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arc: N3_V06N0303 H06W0303
|
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|
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.tile R52C45:PLC2
|
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arc: N3_V06N0003 S3_V06N0303
|
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|
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.tile R52C46:PLC2
|
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arc: N3_V06N0003 S3_V06N0003
|
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|
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.tile R52C47:PLC2
|
|
arc: N3_V06N0003 S3_V06N0003
|
|
arc: N3_V06N0303 E3_H06W0303
|
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arc: W3_H06W0303 E3_H06W0303
|
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|
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.tile R52C48:PLC2
|
|
arc: N3_V06N0103 S3_V06N0003
|
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|
|
.tile R52C49:PLC2
|
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arc: E3_H06E0203 W3_H06E0203
|
|
arc: N3_V06N0103 S3_V06N0003
|
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|
|
.tile R52C50:PLC2
|
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arc: N3_V06N0003 S3_V06N0003
|
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|
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.tile R52C51:PLC2
|
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arc: N3_V06N0103 S3_V06N0003
|
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|
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.tile R52C52:PLC2
|
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arc: N3_V06N0003 S3_V06N0303
|
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|
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.tile R52C53:PLC2
|
|
arc: N3_V06N0003 S3_V06N0003
|
|
arc: N3_V06N0203 E3_H06W0203
|
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arc: W3_H06W0303 E3_H06W0203
|
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|
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.tile R52C55:PLC2
|
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arc: E3_H06E0303 W3_H06E0203
|
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arc: N3_V06N0303 S3_V06N0203
|
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|
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.tile R52C58:PLC2
|
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arc: N3_V06N0103 S3_V06N0103
|
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arc: N3_V06N0303 H06E0303
|
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|
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.tile R52C59:PLC2
|
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arc: W3_H06W0203 E3_H06W0103
|
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|
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.tile R52C61:PLC2
|
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arc: N3_V06N0003 S3_V06N0003
|
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|
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.tile R52C64:PLC2
|
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arc: N3_V06N0003 S3_V06N0003
|
|
|
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.tile R52C65:PLC2
|
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arc: W3_H06W0103 E3_H06W0103
|
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|
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.tile R52C71:PLC2
|
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arc: W3_H06W0103 E3_H06W0103
|
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|
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.tile R52C77:PLC2
|
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arc: W3_H06W0103 E3_H06W0003
|
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|
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.tile R52C7:PLC2
|
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arc: E3_H06E0303 W3_H06E0303
|
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|
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.tile R52C83:PLC2
|
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arc: W3_H06W0003 E3_H06W0303
|
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|
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.tile R52C87:PLC2
|
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arc: S3_V06S0203 N3_V06S0203
|
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.tile R52C88:PLC2
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arc: N1_V02N0701 N3_V06S0203
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.tile R53C13:PLC2
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arc: E3_H06E0303 W3_H06E0303
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.tile R53C19:PLC2
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arc: E3_H06E0303 W3_H06E0303
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.tile R53C25:PLC2
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arc: E3_H06E0303 W3_H06E0303
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.tile R53C31:PLC2
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arc: E3_H06E0003 W3_H06E0303
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arc: N3_V06N0303 S3_V06N0203
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.tile R53C37:PLC2
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arc: E3_H06E0003 W3_H06E0003
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.tile R53C41:PLC2
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arc: N3_V06N0003 S3_V06N0303
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.tile R53C43:PLC2
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arc: E3_H06E0103 W3_H06E0003
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.tile R53C47:PLC2
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arc: N3_V06N0203 S3_V06N0203
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.tile R53C49:PLC2
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arc: E3_H06E0203 W3_H06E0103
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.tile R53C50:PLC2
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arc: N3_V06N0303 S3_V06N0203
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.tile R53C53:PLC2
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arc: N3_V06N0003 E3_H06W0003
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arc: N3_V06N0103 S3_V06N0103
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.tile R53C55:PLC2
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arc: E3_H06E0303 W3_H06E0203
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.tile R53C59:PLC2
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arc: W3_H06W0003 E3_H06W0303
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.tile R53C61:PLC2
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arc: E3_H06E0303 W3_H06E0303
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.tile R53C64:PLC2
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arc: N3_V06N0303 H06E0303
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.tile R53C65:PLC2
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arc: W3_H06W0303 E3_H06W0203
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.tile R53C71:PLC2
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arc: W3_H06W0203 E3_H06W0103
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.tile R53C77:PLC2
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arc: W3_H06W0103 E3_H06W0003
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.tile R53C7:PLC2
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arc: E3_H06E0303 W3_H06E0303
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.tile R53C83:PLC2
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arc: W3_H06W0003 E3_H06W0303
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.tile R55C13:PLC2
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arc: E3_H06E0103 W3_H06E0003
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.tile R55C17:PLC2
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arc: N3_V06N0303 S3_V06N0303
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.tile R55C19:PLC2
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arc: E3_H06E0203 W3_H06E0103
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.tile R55C22:PLC2
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arc: N3_V06N0203 H06E0203
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.tile R55C23:PLC2
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arc: N3_V06N0203 S3_V06N0203
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.tile R55C25:PLC2
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arc: N3_V06N0003 S3_V06N0003
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.tile R55C29:PLC2
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arc: N3_V06N0203 S3_V06N0203
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.tile R55C35:PLC2
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arc: N3_V06N0103 S3_V06N0103
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.tile R55C38:PLC2
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arc: N3_V06N0203 S3_V06N0103
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.tile R55C41:PLC2
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arc: N3_V06N0103 S3_V06N0103
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.tile R55C47:PLC2
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arc: N3_V06N0103 S3_V06N0003
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.tile R55C53:PLC2
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arc: N3_V06N0303 S3_V06N0303
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.tile R55C59:PLC2
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arc: N3_V06N0003 S3_V06N0303
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arc: N3_V06N0103 E3_H06W0103
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.tile R55C65:PLC2
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arc: N3_V06N0103 S3_V06N0103
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arc: N3_V06N0303 S3_V06N0203
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arc: W3_H06W0103 E3_H06W0003
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.tile R55C71:PLC2
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arc: W3_H06W0003 E3_H06W0303
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.tile R55C77:PLC2
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arc: W3_H06W0303 E3_H06W0303
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.tile R55C7:PLC2
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arc: E3_H06E0003 W3_H06E0303
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.tile R55C83:PLC2
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arc: W3_H06W0303 E3_H06W0303
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.tile R55C87:PLC2
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arc: E1_H02E0701 V06S0203
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.tile R56C13:PLC2
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arc: E3_H06E0003 W3_H06E0303
|
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arc: N3_V06N0303 W3_H06E0303
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.tile R56C19:PLC2
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arc: E3_H06E0003 W3_H06E0003
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.tile R56C25:PLC2
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arc: E3_H06E0003 W3_H06E0003
|
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arc: N3_V06N0103 S3_V06N0103
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.tile R56C31:PLC2
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arc: E3_H06E0003 W3_H06E0003
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.tile R56C37:PLC2
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arc: E3_H06E0003 W3_H06E0003
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.tile R56C40:PLC2
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arc: N3_V06N0003 H06E0003
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.tile R56C41:PLC2
|
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arc: N3_V06N0303 S3_V06N0303
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.tile R56C43:PLC2
|
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arc: E3_H06E0003 W3_H06E0003
|
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arc: N3_V06N0003 W3_H06E0003
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.tile R56C46:PLC2
|
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arc: N3_V06N0003 H06E0003
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.tile R56C49:PLC2
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arc: N3_V06N0003 W3_H06E0003
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.tile R56C7:PLC2
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arc: E3_H06E0303 W3_H06E0303
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.tile R57C13:PLC2
|
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arc: S3_V06S0103 N3_V06S0103
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.tile R57C14:PLC2
|
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arc: S3_V06S0303 N3_V06S0303
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.tile R57C15:PLC2
|
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arc: S3_V06S0203 N3_V06S0203
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.tile R57C2:PLC2
|
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arc: S3_V06S0303 N3_V06S0303
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.tile R57C3:PLC2
|
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arc: S3_V06S0003 N3_V06S0003
|
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arc: S3_V06S0203 N3_V06S0103
|
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arc: W1_H02W0601 N3_V06S0303
|
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arc: W1_H02W0701 N3_V06S0203
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.tile R57C88:PLC2
|
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arc: E1_H02E0601 N3_V06S0303
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.tile R59C13:PLC2
|
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arc: E3_H06E0003 W3_H06E0303
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.tile R59C19:PLC2
|
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arc: E3_H06E0103 W3_H06E0003
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.tile R59C25:PLC2
|
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arc: E3_H06E0203 W3_H06E0103
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.tile R59C31:PLC2
|
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arc: N3_V06N0203 W3_H06E0203
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.tile R59C41:PLC2
|
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arc: N3_V06N0303 E3_H06W0303
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.tile R59C47:PLC2
|
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arc: N3_V06N0203 E3_H06W0203
|
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arc: W3_H06W0303 E3_H06W0203
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.tile R59C50:PLC2
|
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arc: N3_V06N0203 H06W0203
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.tile R59C53:PLC2
|
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arc: N3_V06N0103 E3_H06W0103
|
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arc: W3_H06W0203 E3_H06W0103
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.tile R59C59:PLC2
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arc: W3_H06W0103 E3_H06W0103
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.tile R59C65:PLC2
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arc: W3_H06W0103 E3_H06W0103
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.tile R59C71:PLC2
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arc: W3_H06W0103 E3_H06W0003
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.tile R59C77:PLC2
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arc: W3_H06W0003 E3_H06W0303
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.tile R59C7:PLC2
|
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arc: E3_H06E0303 W3_H06E0303
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.tile R59C83:PLC2
|
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arc: W3_H06W0303 E3_H06W0303
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.tile R5C56:PLC2
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arc: N1_V02N0701 S1_V02N0701
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.tile R61C13:PLC2
|
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arc: E3_H06E0303 W3_H06E0303
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.tile R61C17:PLC2
|
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arc: N3_V06N0303 E3_H06W0303
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.tile R61C19:PLC2
|
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arc: E3_H06E0003 W3_H06E0303
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.tile R61C23:PLC2
|
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arc: N3_V06N0203 E3_H06W0203
|
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arc: W3_H06W0303 E3_H06W0203
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.tile R61C25:PLC2
|
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arc: N3_V06N0003 W3_H06E0003
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.tile R61C29:PLC2
|
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arc: N3_V06N0203 E3_H06W0203
|
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arc: W3_H06W0203 E3_H06W0203
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.tile R61C35:PLC2
|
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arc: N3_V06N0103 E3_H06W0103
|
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arc: W3_H06W0203 E3_H06W0103
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.tile R61C38:PLC2
|
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arc: N3_V06N0103 H06W0103
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.tile R61C41:PLC2
|
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arc: N3_V06N0103 E3_H06W0103
|
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arc: W3_H06W0103 E3_H06W0103
|
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.tile R61C47:PLC2
|
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arc: N3_V06N0003 E3_H06W0003
|
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arc: W3_H06W0103 E3_H06W0003
|
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.tile R61C53:PLC2
|
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arc: N3_V06N0303 E3_H06W0303
|
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arc: W3_H06W0003 E3_H06W0303
|
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.tile R61C59:PLC2
|
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arc: N3_V06N0303 E3_H06W0303
|
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arc: W3_H06W0303 E3_H06W0303
|
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.tile R61C65:PLC2
|
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arc: N3_V06N0103 S3_V06N0103
|
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arc: N3_V06N0203 E3_H06W0203
|
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arc: W3_H06W0303 E3_H06W0203
|
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.tile R61C71:PLC2
|
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arc: W3_H06W0203 E3_H06W0103
|
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.tile R61C77:PLC2
|
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arc: W3_H06W0103 E3_H06W0003
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.tile R61C7:PLC2
|
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arc: E3_H06E0303 W3_H06E0303
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.tile R61C83:PLC2
|
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arc: W3_H06W0003 E3_H06W0303
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.tile R62C13:PLC2
|
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arc: E3_H06E0103 W3_H06E0003
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.tile R62C19:PLC2
|
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arc: E3_H06E0103 W3_H06E0103
|
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.tile R62C25:PLC2
|
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arc: N3_V06N0103 W3_H06E0103
|
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.tile R62C41:PLC2
|
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arc: N3_V06N0303 E3_H06W0303
|
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.tile R62C47:PLC2
|
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arc: W3_H06W0303 E3_H06W0303
|
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.tile R62C53:PLC2
|
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arc: W3_H06W0303 E3_H06W0203
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.tile R62C59:PLC2
|
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arc: W3_H06W0203 E3_H06W0103
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.tile R62C65:PLC2
|
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arc: W3_H06W0103 E3_H06W0103
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.tile R62C71:PLC2
|
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arc: W3_H06W0103 E3_H06W0003
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.tile R62C77:PLC2
|
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arc: W3_H06W0003 E3_H06W0303
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.tile R62C7:PLC2
|
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arc: E3_H06E0003 W3_H06E0303
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.tile R62C83:PLC2
|
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arc: W3_H06W0303 E3_H06W0303
|
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.tile R63C13:PLC2
|
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arc: S3_V06S0203 N3_V06S0103
|
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.tile R63C14:PLC2
|
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arc: S3_V06S0303 N3_V06S0303
|
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.tile R63C15:PLC2
|
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arc: S3_V06S0303 N3_V06S0203
|
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.tile R63C2:PLC2
|
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arc: V01S0100 N3_V06S0303
|
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.tile R63C3:PLC2
|
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arc: W1_H02W0301 N3_V06S0003
|
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arc: W1_H02W0701 N3_V06S0203
|
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.tile R64C16:PLC2
|
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arc: N3_V06N0103 S3_V06N0103
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.tile R64C17:PLC2
|
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arc: N3_V06N0103 S3_V06N0003
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.tile R64C20:PLC2
|
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arc: S3_V06S0203 N3_V06S0103
|
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.tile R64C22:PLC2
|
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arc: N3_V06N0103 S3_V06N0103
|
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.tile R64C23:PLC2
|
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arc: N3_V06N0103 S3_V06N0003
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.tile R64C25:PLC2
|
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arc: N3_V06N0103 S3_V06N0103
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.tile R64C26:PLC2
|
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arc: N3_V06N0003 S3_V06N0003
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.tile R64C2:PLC2
|
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arc: W1_H02W0701 N1_V01S0100
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.tile R64C30:PLC2
|
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arc: N3_V06N0203 S3_V06N0203
|
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.tile R64C31:PLC2
|
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arc: N3_V06N0203 S3_V06N0103
|
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.tile R64C32:PLC2
|
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arc: N3_V06N0103 S3_V06N0103
|
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.tile R64C34:PLC2
|
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arc: N3_V06N0303 S3_V06N0203
|
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.tile R64C35:PLC2
|
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arc: N3_V06N0103 E3_H06W0103
|
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arc: N3_V06N0203 S3_V06N0103
|
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.tile R64C36:PLC2
|
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arc: N3_V06N0103 S3_V06N0103
|
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.tile R64C37:PLC2
|
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arc: N3_V06N0203 S3_V06N0203
|
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.tile R64C38:PLC2
|
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arc: N3_V06N0103 S3_V06N0103
|
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.tile R64C39:PLC2
|
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arc: N3_V06N0103 S3_V06N0103
|
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.tile R64C40:PLC2
|
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arc: N3_V06N0203 S3_V06N0203
|
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.tile R64C41:PLC2
|
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arc: N3_V06N0203 S3_V06N0103
|
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arc: W3_H06W0103 E3_H06W0103
|
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.tile R64C42:PLC2
|
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arc: N3_V06N0303 S3_V06N0203
|
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.tile R64C43:PLC2
|
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arc: N3_V06N0303 S3_V06N0203
|
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.tile R64C45:PLC2
|
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arc: N3_V06N0203 S3_V06N0203
|
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.tile R64C46:PLC2
|
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arc: N3_V06N0303 S3_V06N0203
|
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.tile R64C47:PLC2
|
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arc: W3_H06W0103 E3_H06W0103
|
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.tile R64C48:PLC2
|
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arc: N3_V06N0003 S3_V06N0303
|
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.tile R64C49:PLC2
|
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arc: N3_V06N0303 S3_V06N0203
|
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.tile R64C51:PLC2
|
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arc: N3_V06N0003 S3_V06N0303
|
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.tile R64C52:PLC2
|
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arc: N3_V06N0203 S3_V06N0203
|
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.tile R64C53:PLC2
|
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arc: W3_H06W0103 E3_H06W0103
|
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.tile R64C55:PLC2
|
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arc: N3_V06N0103 S3_V06N0103
|
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.tile R64C58:PLC2
|
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arc: N3_V06N0003 S3_V06N0303
|
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.tile R64C59:PLC2
|
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arc: W3_H06W0103 E3_H06W0103
|
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.tile R64C61:PLC2
|
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arc: N3_V06N0003 S3_V06N0303
|
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.tile R64C64:PLC2
|
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arc: N3_V06N0303 S3_V06N0303
|
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.tile R64C65:PLC2
|
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arc: W3_H06W0103 E3_H06W0103
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.tile R64C71:PLC2
|
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arc: W3_H06W0103 E3_H06W0003
|
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.tile R64C77:PLC2
|
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arc: W3_H06W0003 E3_H06W0303
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.tile R64C83:PLC2
|
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arc: W3_H06W0303 E3_H06W0303
|
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.tile R67C65:PLC2
|
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arc: N3_V06N0103 E3_H06W0103
|
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.tile R67C71:PLC2
|
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arc: W3_H06W0103 E3_H06W0103
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.tile R67C77:PLC2
|
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arc: W3_H06W0103 E3_H06W0003
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.tile R67C83:PLC2
|
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arc: W3_H06W0003 E3_H06W0303
|
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.tile R69C11:PLC2
|
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arc: S1_V02S0701 E1_H02W0701
|
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.tile R69C13:PLC2
|
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arc: W1_H02W0701 N3_V06S0203
|
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.tile R69C14:PLC2
|
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arc: V01S0100 N3_V06S0303
|
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.tile R69C15:PLC2
|
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arc: V01S0100 N3_V06S0303
|
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.tile R7C15:PLC2
|
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arc: S3_V06S0003 N3_V06S0003
|
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.tile R7C16:PLC2
|
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arc: S3_V06S0103 N3_V06S0003
|
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.tile R7C17:PLC2
|
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arc: S3_V06S0103 N3_V06S0103
|
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.tile R7C18:PLC2
|
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arc: S3_V06S0203 N3_V06S0103
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.tile R7C23:PLC2
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arc: S3_V06S0003 N3_V06S0003
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.tile R7C24:PLC2
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arc: S3_V06S0003 N3_V06S0003
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.tile R7C26:PLC2
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arc: S3_V06S0203 N3_V06S0103
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.tile R7C27:PLC2
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arc: S3_V06S0103 N3_V06S0003
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arc: S3_V06S0203 N3_V06S0103
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arc: S3_V06S0303 N3_V06S0203
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.tile R7C33:PLC2
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arc: S3_V06S0103 N3_V06S0003
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.tile R7C34:PLC2
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arc: S3_V06S0003 N3_V06S0003
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arc: S3_V06S0103 N3_V06S0103
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arc: S3_V06S0203 N3_V06S0203
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.tile R7C35:PLC2
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arc: S3_V06S0103 N3_V06S0103
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arc: S3_V06S0303 N3_V06S0303
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.tile R7C36:PLC2
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arc: S3_V06S0003 N3_V06S0303
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arc: S3_V06S0103 N3_V06S0103
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.tile R7C37:PLC2
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arc: S3_V06S0003 N3_V06S0003
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arc: S3_V06S0103 N3_V06S0103
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.tile R7C38:PLC2
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arc: S3_V06S0303 N3_V06S0203
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.tile R7C39:PLC2
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arc: S3_V06S0103 N3_V06S0003
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arc: S3_V06S0203 N3_V06S0103
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arc: S3_V06S0303 N3_V06S0203
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.tile R7C40:PLC2
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arc: S3_V06S0203 N3_V06S0103
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arc: S3_V06S0303 N3_V06S0203
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.tile R7C41:PLC2
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arc: S3_V06S0103 N3_V06S0003
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.tile R7C42:PLC2
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arc: S3_V06S0003 N3_V06S0003
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arc: S3_V06S0103 N3_V06S0103
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arc: S3_V06S0203 N3_V06S0203
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.tile R7C43:PLC2
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arc: S3_V06S0003 N3_V06S0003
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arc: S3_V06S0203 N3_V06S0103
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.tile R7C44:PLC2
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arc: S3_V06S0103 N3_V06S0003
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.tile R7C45:PLC2
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arc: S3_V06S0003 N3_V06S0003
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arc: S3_V06S0203 N3_V06S0103
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arc: S3_V06S0303 N3_V06S0203
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.tile R7C46:PLC2
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arc: N3_V06N0303 S3_V06N0303
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arc: S3_V06S0003 N3_V06S0003
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.tile R7C47:PLC2
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arc: S3_V06S0103 N3_V06S0103
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.tile R7C48:PLC2
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arc: S3_V06S0003 N3_V06S0003
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arc: S3_V06S0103 N3_V06S0103
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.tile R7C49:PLC2
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arc: S3_V06S0003 N3_V06S0003
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.tile R7C50:PLC2
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arc: S3_V06S0003 N3_V06S0003
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arc: S3_V06S0103 N3_V06S0103
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.tile R7C51:PLC2
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arc: S3_V06S0103 N3_V06S0003
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arc: S3_V06S0203 N3_V06S0203
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arc: V01S0000 N3_V06S0103
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.tile R7C52:PLC2
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arc: S3_V06S0103 N3_V06S0003
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.tile R7C53:PLC2
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arc: S3_V06S0003 N3_V06S0003
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.tile R7C54:PLC2
|
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arc: S3_V06S0003 N3_V06S0003
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arc: S3_V06S0203 N3_V06S0203
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.tile R7C56:PLC2
|
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arc: N1_V02N0701 S3_V06N0203
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.tile R7C60:PLC2
|
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arc: S3_V06S0303 N3_V06S0303
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.tile R7C61:PLC2
|
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arc: S3_V06S0103 N3_V06S0003
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.tile R7C62:PLC2
|
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arc: S3_V06S0203 N3_V06S0103
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.tile R7C63:PLC2
|
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arc: S3_V06S0003 N3_V06S0303
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.tile R8C34:PLC2
|
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arc: N3_V06N0303 S3_V06N0303
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.tile R8C35:PLC2
|
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arc: N3_V06N0203 S3_V06N0203
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.tile R8C51:PLC2
|
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arc: S3_V06S0003 N1_V01S0000
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.tile R8C77:PLC2
|
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arc: N3_V06N0303 S3_V06N0203
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.tile R8C83:PLC2
|
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arc: N3_V06N0203 S3_V06N0203
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.tile R9C13:PLC2
|
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arc: N3_V06N0203 S3_V06N0103
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.tile R9C16:PLC2
|
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arc: N3_V06N0303 S3_V06N0203
|
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.tile R9C18:PLC2
|
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arc: N3_V06N0203 S3_V06N0103
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.tile R9C19:PLC2
|
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arc: N3_V06N0303 S3_V06N0303
|
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.tile R9C22:PLC2
|
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arc: N3_V06N0203 S3_V06N0103
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.tile R9C23:PLC2
|
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arc: N3_V06N0303 S3_V06N0203
|
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.tile R9C25:PLC2
|
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arc: N3_V06N0003 S3_V06N0003
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.tile R9C27:PLC2
|
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arc: N3_V06N0203 S3_V06N0103
|
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.tile R9C31:PLC2
|
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arc: N3_V06N0303 S3_V06N0203
|
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.tile R9C41:PLC2
|
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arc: N3_V06N0203 S3_V06N0203
|
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.tile R9C45:PLC2
|
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arc: S3_V06S0103 N3_V06S0103
|
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.tile R9C46:PLC2
|
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arc: S3_V06S0003 N3_V06S0003
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.tile R9C48:PLC2
|
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arc: N3_V06N0303 S3_V06N0303
|
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arc: S3_V06S0203 N3_V06S0103
|
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.tile R9C49:PLC2
|
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arc: S3_V06S0103 N3_V06S0003
|
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.tile R9C51:PLC2
|
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arc: S3_V06S0103 N3_V06S0003
|
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.tile R9C52:PLC2
|
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arc: S3_V06S0203 N3_V06S0103
|
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.tile R9C53:PLC2
|
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arc: N3_V06N0303 S3_V06N0303
|
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.tile R9C58:PLC2
|
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arc: N3_V06N0203 S3_V06N0203
|
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.tile R9C5:PLC2
|
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arc: N3_V06N0303 S3_V06N0303
|
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.tile R9C65:PLC2
|
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arc: N3_V06N0203 S3_V06N0203
|
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.tile R9C67:PLC2
|
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arc: N3_V06N0203 S3_V06N0103
|
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.tile R9C68:PLC2
|
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arc: N3_V06N0303 S3_V06N0303
|
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.tile R9C69:PLC2
|
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arc: N3_V06N0203 S3_V06N0103
|
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.tile R9C6:PLC2
|
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arc: N3_V06N0303 S3_V06N0203
|
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.tile R9C73:PLC2
|
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arc: N3_V06N0203 S3_V06N0103
|
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.tile R9C75:PLC2
|
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arc: N3_V06N0303 S3_V06N0303
|
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.tile R9C80:PLC2
|
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arc: N3_V06N0303 S3_V06N0303
|
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.tile R9C83:PLC2
|
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arc: N3_V06N0203 S3_V06N0203
|
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.tile R9C8:PLC2
|
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arc: N3_V06N0203 S3_V06N0103
|
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.tile TAP_R20C51:TAP_DRIVE
|
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arc: L_HPBX0000 G_VPTX0000
|
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.tile TAP_R21C31:TAP_DRIVE
|
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arc: R_HPBX0000 G_VPTX0000
|
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.tile TAP_R21C51:TAP_DRIVE
|
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arc: L_HPBX0000 G_VPTX0000
|
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arc: R_HPBX0000 G_VPTX0000
|
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.tile TAP_R23C31:TAP_DRIVE
|
|
arc: R_HPBX0000 G_VPTX0000
|
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.tile TAP_R23C51:TAP_DRIVE
|
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arc: L_HPBX0000 G_VPTX0000
|
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arc: R_HPBX0000 G_VPTX0000
|
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.tile TAP_R24C31:TAP_DRIVE
|
|
arc: R_HPBX0000 G_VPTX0000
|
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|
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.tile TAP_R24C51:TAP_DRIVE
|
|
arc: L_HPBX0000 G_VPTX0000
|
|
arc: R_HPBX0000 G_VPTX0000
|
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.tile TAP_R25C31:TAP_DRIVE
|
|
arc: R_HPBX0000 G_VPTX0000
|
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|
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.tile TAP_R25C51:TAP_DRIVE
|
|
arc: L_HPBX0000 G_VPTX0000
|
|
arc: R_HPBX0000 G_VPTX0000
|
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|
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.tile TAP_R26C31:TAP_DRIVE
|
|
arc: R_HPBX0000 G_VPTX0000
|
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|
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.tile TAP_R26C51:TAP_DRIVE
|
|
arc: L_HPBX0000 G_VPTX0000
|
|
arc: R_HPBX0000 G_VPTX0000
|
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|
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.tile TAP_R27C13:TAP_DRIVE
|
|
arc: R_HPBX0000 G_VPTX0000
|
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|
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.tile TAP_R27C31:TAP_DRIVE
|
|
arc: L_HPBX0000 G_VPTX0000
|
|
arc: R_HPBX0000 G_VPTX0000
|
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|
|
.tile TAP_R27C51:TAP_DRIVE
|
|
arc: L_HPBX0000 G_VPTX0000
|
|
arc: R_HPBX0000 G_VPTX0000
|
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|
|
.tile TAP_R27C78:TAP_DRIVE
|
|
arc: L_HPBX0000 G_VPTX0000
|
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|
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.tile TAP_R28C31:TAP_DRIVE
|
|
arc: R_HPBX0000 G_VPTX0000
|
|
|
|
.tile TAP_R28C51:TAP_DRIVE
|
|
arc: L_HPBX0000 G_VPTX0000
|
|
arc: R_HPBX0000 G_VPTX0000
|
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|
|
.tile TAP_R29C31:TAP_DRIVE
|
|
arc: R_HPBX0000 G_VPTX0000
|
|
|
|
.tile TAP_R29C51:TAP_DRIVE
|
|
arc: L_HPBX0000 G_VPTX0000
|
|
arc: R_HPBX0000 G_VPTX0000
|
|
|
|
.tile TAP_R30C31:TAP_DRIVE
|
|
arc: R_HPBX0000 G_VPTX0000
|
|
|
|
.tile TAP_R30C51:TAP_DRIVE
|
|
arc: L_HPBX0000 G_VPTX0000
|
|
arc: R_HPBX0000 G_VPTX0000
|
|
|
|
.tile TAP_R31C31:TAP_DRIVE
|
|
arc: R_HPBX0000 G_VPTX0000
|
|
|
|
.tile TAP_R31C51:TAP_DRIVE
|
|
arc: L_HPBX0000 G_VPTX0000
|
|
arc: R_HPBX0000 G_VPTX0000
|
|
|
|
.tile TAP_R32C31:TAP_DRIVE
|
|
arc: R_HPBX0000 G_VPTX0000
|
|
|
|
.tile TAP_R32C51:TAP_DRIVE
|
|
arc: L_HPBX0000 G_VPTX0000
|
|
arc: R_HPBX0000 G_VPTX0000
|
|
|
|
.tile TAP_R33C51:TAP_DRIVE
|
|
arc: L_HPBX0000 G_VPTX0000
|
|
|