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FPGA-Neural/sim/parameter_sweep.vcd
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micheleandClaude Sonnet 5 1a6f0ba2ef fix: guard neuron_parallel against invalid N_INPUTS/PARALLEL combos 
Both Phase 2 findings (docs/FPGA-NeuralNetwork-Engine.md) shared one
root cause: GROUPS = N_INPUTS / PARALLEL is integer division. When
N_INPUTS is not an exact multiple of PARALLEL, the remainder inputs
were silently dropped from the accumulation (wrong result, no
error); when PARALLEL > N_INPUTS, GROUPS = 0 and the controller's
terminal condition was never met, hanging the neuron forever.

Added a single elaboration-time guard to rtl/neuron_parallel.v: a
`generate` block instantiates a deliberately undefined module when
N_INPUTS % PARALLEL != 0, forcing a hard failure in both simulation
and synthesis instead of a silent wrong answer or a deadlock. Valid
configurations are unaffected (the branch is never elaborated). The
validated datapath (mac8/mac_unit/accumulation/ReLU/saturation) is
untouched -- this is authorized as a scoped exception to the
"core is fixed, do not touch" project policy, for this guard only.

- sim/neuron_parallel_guard_negative_nonmultiple_tb.v and
  sim/neuron_parallel_guard_negative_degenerate_tb.v: negative tests
  that must fail to elaborate; verified both fail with the expected
  "Unknown module type" error.
- sim/parameter_sweep_tb.v: rewritten to valid-configs-only (the
  three configs that used to demonstrate truncation/hang no longer
  compile, by design); added PARALLEL=2 and PARALLEL=4 configs,
  the two best-performing values from
  docs/FPGA-Neural-Datapatch-Benchmark.md.
- Full regression re-run after the RTL change: all existing
  testbenches still pass unchanged.

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01WQV3vS9TXaGDJ5cRfnfidt
2026-09-02 14:41:49 +02:00

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$date
Wed Sep 2 14:40:18 2026
$end
$version
Icarus Verilog
$end
$timescale
1ps
$end
$scope module tb $end
$var wire 8 ! y_g [7:0] $end
$var wire 8 " y_f [7:0] $end
$var wire 8 # y_d [7:0] $end
$var wire 8 $ y_a [7:0] $end
$var wire 1 % done_g $end
$var wire 1 & done_f $end
$var wire 1 ' done_d $end
$var wire 1 ( done_a $end
$var wire 1 ) busy_g $end
$var wire 1 * busy_f $end
$var wire 1 + busy_d $end
$var wire 1 , busy_a $end
$var parameter 32 - A_ACC_WIDTH $end
$var parameter 32 . A_DATA_WIDTH $end
$var parameter 32 / A_N_INPUTS $end
$var parameter 32 0 A_PARALLEL $end
$var parameter 32 1 D_ACC_WIDTH $end
$var parameter 32 2 D_DATA_WIDTH $end
$var parameter 32 3 D_N_INPUTS $end
$var parameter 32 4 D_PARALLEL $end
$var parameter 32 5 F_ACC_WIDTH $end
$var parameter 32 6 F_DATA_WIDTH $end
$var parameter 32 7 F_N_INPUTS $end
$var parameter 32 8 F_PARALLEL $end
$var parameter 32 9 G_ACC_WIDTH $end
$var parameter 32 : G_DATA_WIDTH $end
$var parameter 32 ; G_N_INPUTS $end
$var parameter 32 < G_PARALLEL $end
$var reg 8 = bias_a [7:0] $end
$var reg 8 > bias_d [7:0] $end
$var reg 8 ? bias_f [7:0] $end
$var reg 8 @ bias_g [7:0] $end
$var reg 1 A clk $end
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$var reg 1 C start_a $end
$var reg 1 D start_d $end
$var reg 1 E start_f $end
$var reg 1 F start_g $end
$var reg 256 G w_bus_a [255:0] $end
$var reg 512 H w_bus_d [511:0] $end
$var reg 256 I w_bus_f [255:0] $end
$var reg 256 J w_bus_g [255:0] $end
$var reg 256 K x_bus_a [255:0] $end
$var reg 512 L x_bus_d [511:0] $end
$var reg 256 M x_bus_f [255:0] $end
$var reg 256 N x_bus_g [255:0] $end
$var integer 32 O count [31:0] $end
$var integer 32 P errors [31:0] $end
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$var wire 1 C start $end
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$var wire 256 S x_bus [255:0] $end
$var wire 64 T x_group [63:0] $end
$var wire 64 U w_group [63:0] $end
$var wire 32 V final_acc [31:0] $end
$var wire 32 W bias_ext [31:0] $end
$var wire 32 X acc_next [31:0] $end
$var parameter 32 Y ACC_WIDTH $end
$var parameter 32 Z DATA_WIDTH $end
$var parameter 32 [ GROUPS $end
$var parameter 32 \ GROUP_INDEX_WIDTH $end
$var parameter 32 ] N_INPUTS $end
$var parameter 32 ^ PARALLEL $end
$var reg 32 _ acc [31:0] $end
$var reg 1 , busy $end
$var reg 1 ( done $end
$var reg 2 ` group_index [1:0] $end
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$var wire 64 c w_bus [63:0] $end
$var wire 64 d x_bus [63:0] $end
$var wire 32 e acc_out [31:0] $end
$var parameter 32 f ACC_WIDTH $end
$var parameter 32 g DATA_WIDTH $end
$var parameter 32 h PARALLEL $end
$var parameter 32 i TREE_LEVELS $end
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$var wire 8 m x [7:0] $end
$var wire 32 n product_ext [31:0] $end
$var wire 16 o product [15:0] $end
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$var parameter 32 r DATA_WIDTH $end
$var parameter 64 s PROD_WIDTH $end
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$var parameter 32 | DATA_WIDTH $end
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$var wire 8 #" x [7:0] $end
$var wire 32 $" product_ext [31:0] $end
$var wire 16 %" product [15:0] $end
$var wire 32 &" acc_out [31:0] $end
$var parameter 32 '" ACC_WIDTH $end
$var parameter 32 (" DATA_WIDTH $end
$var parameter 64 )" PROD_WIDTH $end
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$var wire 32 +" acc_in [31:0] $end
$var wire 8 ," w [7:0] $end
$var wire 8 -" x [7:0] $end
$var wire 32 ." product_ext [31:0] $end
$var wire 16 /" product [15:0] $end
$var wire 32 0" acc_out [31:0] $end
$var parameter 32 1" ACC_WIDTH $end
$var parameter 32 2" DATA_WIDTH $end
$var parameter 64 3" PROD_WIDTH $end
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$var wire 32 8" product_ext [31:0] $end
$var wire 16 9" product [15:0] $end
$var wire 32 :" acc_out [31:0] $end
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$var parameter 32 <" DATA_WIDTH $end
$var parameter 64 =" PROD_WIDTH $end
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$var wire 8 @" w [7:0] $end
$var wire 8 A" x [7:0] $end
$var wire 32 B" product_ext [31:0] $end
$var wire 16 C" product [15:0] $end
$var wire 32 D" acc_out [31:0] $end
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$var parameter 32 F" DATA_WIDTH $end
$var parameter 64 G" PROD_WIDTH $end
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$scope begin GEN_MAC[6] $end
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$var wire 8 K" x [7:0] $end
$var wire 32 L" product_ext [31:0] $end
$var wire 16 M" product [15:0] $end
$var wire 32 N" acc_out [31:0] $end
$var parameter 32 O" ACC_WIDTH $end
$var parameter 32 P" DATA_WIDTH $end
$var parameter 64 Q" PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[7] $end
$var parameter 4 R" i $end
$scope module u_mac $end
$var wire 32 S" acc_in [31:0] $end
$var wire 8 T" w [7:0] $end
$var wire 8 U" x [7:0] $end
$var wire 32 V" product_ext [31:0] $end
$var wire 16 W" product [15:0] $end
$var wire 32 X" acc_out [31:0] $end
$var parameter 32 Y" ACC_WIDTH $end
$var parameter 32 Z" DATA_WIDTH $end
$var parameter 64 [" PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_TREE_INPUT[0] $end
$var parameter 2 \" i $end
$upscope $end
$scope begin GEN_TREE_INPUT[1] $end
$var parameter 2 ]" i $end
$upscope $end
$scope begin GEN_TREE_INPUT[2] $end
$var parameter 3 ^" i $end
$upscope $end
$scope begin GEN_TREE_INPUT[3] $end
$var parameter 3 _" i $end
$upscope $end
$scope begin GEN_TREE_INPUT[4] $end
$var parameter 4 `" i $end
$upscope $end
$scope begin GEN_TREE_INPUT[5] $end
$var parameter 4 a" i $end
$upscope $end
$scope begin GEN_TREE_INPUT[6] $end
$var parameter 4 b" i $end
$upscope $end
$scope begin GEN_TREE_INPUT[7] $end
$var parameter 4 c" i $end
$upscope $end
$scope begin GEN_TREE_LEVEL[0] $end
$var parameter 2 d" level $end
$scope begin GEN_TREE_NODE[0] $end
$var parameter 2 e" node $end
$upscope $end
$scope begin GEN_TREE_NODE[1] $end
$var parameter 2 f" node $end
$upscope $end
$scope begin GEN_TREE_NODE[2] $end
$var parameter 3 g" node $end
$upscope $end
$scope begin GEN_TREE_NODE[3] $end
$var parameter 3 h" node $end
$upscope $end
$upscope $end
$scope begin GEN_TREE_LEVEL[1] $end
$var parameter 2 i" level $end
$scope begin GEN_TREE_NODE[0] $end
$var parameter 2 j" node $end
$upscope $end
$scope begin GEN_TREE_NODE[1] $end
$var parameter 2 k" node $end
$upscope $end
$upscope $end
$scope begin GEN_TREE_LEVEL[2] $end
$var parameter 3 l" level $end
$scope begin GEN_TREE_NODE[0] $end
$var parameter 2 m" node $end
$upscope $end
$upscope $end
$upscope $end
$upscope $end
$scope module u_d $end
$var wire 8 n" bias [7:0] $end
$var wire 1 A clk $end
$var wire 1 B rst $end
$var wire 1 D start $end
$var wire 512 o" w_bus [511:0] $end
$var wire 512 p" x_bus [511:0] $end
$var wire 256 q" x_group [255:0] $end
$var wire 256 r" w_group [255:0] $end
$var wire 32 s" final_acc [31:0] $end
$var wire 32 t" bias_ext [31:0] $end
$var wire 32 u" acc_next [31:0] $end
$var parameter 32 v" ACC_WIDTH $end
$var parameter 32 w" DATA_WIDTH $end
$var parameter 32 x" GROUPS $end
$var parameter 32 y" GROUP_INDEX_WIDTH $end
$var parameter 32 z" N_INPUTS $end
$var parameter 32 {" PARALLEL $end
$var reg 32 |" acc [31:0] $end
$var reg 1 + busy $end
$var reg 1 ' done $end
$var reg 1 }" group_index $end
$var reg 8 ~" y [7:0] $end
$scope module u_mac8 $end
$var wire 32 !# acc_in [31:0] $end
$var wire 256 "# w_bus [255:0] $end
$var wire 256 ## x_bus [255:0] $end
$var wire 32 $# acc_out [31:0] $end
$var parameter 32 %# ACC_WIDTH $end
$var parameter 32 &# DATA_WIDTH $end
$var parameter 32 '# PARALLEL $end
$var parameter 32 (# TREE_LEVELS $end
$scope begin GEN_MAC[0] $end
$var parameter 2 )# i $end
$scope module u_mac $end
$var wire 32 *# acc_in [31:0] $end
$var wire 8 +# w [7:0] $end
$var wire 8 ,# x [7:0] $end
$var wire 32 -# product_ext [31:0] $end
$var wire 16 .# product [15:0] $end
$var wire 32 /# acc_out [31:0] $end
$var parameter 32 0# ACC_WIDTH $end
$var parameter 32 1# DATA_WIDTH $end
$var parameter 64 2# PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[1] $end
$var parameter 2 3# i $end
$scope module u_mac $end
$var wire 32 4# acc_in [31:0] $end
$var wire 8 5# w [7:0] $end
$var wire 8 6# x [7:0] $end
$var wire 32 7# product_ext [31:0] $end
$var wire 16 8# product [15:0] $end
$var wire 32 9# acc_out [31:0] $end
$var parameter 32 :# ACC_WIDTH $end
$var parameter 32 ;# DATA_WIDTH $end
$var parameter 64 <# PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[2] $end
$var parameter 3 =# i $end
$scope module u_mac $end
$var wire 32 ># acc_in [31:0] $end
$var wire 8 ?# w [7:0] $end
$var wire 8 @# x [7:0] $end
$var wire 32 A# product_ext [31:0] $end
$var wire 16 B# product [15:0] $end
$var wire 32 C# acc_out [31:0] $end
$var parameter 32 D# ACC_WIDTH $end
$var parameter 32 E# DATA_WIDTH $end
$var parameter 64 F# PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[3] $end
$var parameter 3 G# i $end
$scope module u_mac $end
$var wire 32 H# acc_in [31:0] $end
$var wire 8 I# w [7:0] $end
$var wire 8 J# x [7:0] $end
$var wire 32 K# product_ext [31:0] $end
$var wire 16 L# product [15:0] $end
$var wire 32 M# acc_out [31:0] $end
$var parameter 32 N# ACC_WIDTH $end
$var parameter 32 O# DATA_WIDTH $end
$var parameter 64 P# PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[4] $end
$var parameter 4 Q# i $end
$scope module u_mac $end
$var wire 32 R# acc_in [31:0] $end
$var wire 8 S# w [7:0] $end
$var wire 8 T# x [7:0] $end
$var wire 32 U# product_ext [31:0] $end
$var wire 16 V# product [15:0] $end
$var wire 32 W# acc_out [31:0] $end
$var parameter 32 X# ACC_WIDTH $end
$var parameter 32 Y# DATA_WIDTH $end
$var parameter 64 Z# PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[5] $end
$var parameter 4 [# i $end
$scope module u_mac $end
$var wire 32 \# acc_in [31:0] $end
$var wire 8 ]# w [7:0] $end
$var wire 8 ^# x [7:0] $end
$var wire 32 _# product_ext [31:0] $end
$var wire 16 `# product [15:0] $end
$var wire 32 a# acc_out [31:0] $end
$var parameter 32 b# ACC_WIDTH $end
$var parameter 32 c# DATA_WIDTH $end
$var parameter 64 d# PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[6] $end
$var parameter 4 e# i $end
$scope module u_mac $end
$var wire 32 f# acc_in [31:0] $end
$var wire 8 g# w [7:0] $end
$var wire 8 h# x [7:0] $end
$var wire 32 i# product_ext [31:0] $end
$var wire 16 j# product [15:0] $end
$var wire 32 k# acc_out [31:0] $end
$var parameter 32 l# ACC_WIDTH $end
$var parameter 32 m# DATA_WIDTH $end
$var parameter 64 n# PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[7] $end
$var parameter 4 o# i $end
$scope module u_mac $end
$var wire 32 p# acc_in [31:0] $end
$var wire 8 q# w [7:0] $end
$var wire 8 r# x [7:0] $end
$var wire 32 s# product_ext [31:0] $end
$var wire 16 t# product [15:0] $end
$var wire 32 u# acc_out [31:0] $end
$var parameter 32 v# ACC_WIDTH $end
$var parameter 32 w# DATA_WIDTH $end
$var parameter 64 x# PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[8] $end
$var parameter 5 y# i $end
$scope module u_mac $end
$var wire 32 z# acc_in [31:0] $end
$var wire 8 {# w [7:0] $end
$var wire 8 |# x [7:0] $end
$var wire 32 }# product_ext [31:0] $end
$var wire 16 ~# product [15:0] $end
$var wire 32 !$ acc_out [31:0] $end
$var parameter 32 "$ ACC_WIDTH $end
$var parameter 32 #$ DATA_WIDTH $end
$var parameter 64 $$ PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[9] $end
$var parameter 5 %$ i $end
$scope module u_mac $end
$var wire 32 &$ acc_in [31:0] $end
$var wire 8 '$ w [7:0] $end
$var wire 8 ($ x [7:0] $end
$var wire 32 )$ product_ext [31:0] $end
$var wire 16 *$ product [15:0] $end
$var wire 32 +$ acc_out [31:0] $end
$var parameter 32 ,$ ACC_WIDTH $end
$var parameter 32 -$ DATA_WIDTH $end
$var parameter 64 .$ PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[10] $end
$var parameter 5 /$ i $end
$scope module u_mac $end
$var wire 32 0$ acc_in [31:0] $end
$var wire 8 1$ w [7:0] $end
$var wire 8 2$ x [7:0] $end
$var wire 32 3$ product_ext [31:0] $end
$var wire 16 4$ product [15:0] $end
$var wire 32 5$ acc_out [31:0] $end
$var parameter 32 6$ ACC_WIDTH $end
$var parameter 32 7$ DATA_WIDTH $end
$var parameter 64 8$ PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[11] $end
$var parameter 5 9$ i $end
$scope module u_mac $end
$var wire 32 :$ acc_in [31:0] $end
$var wire 8 ;$ w [7:0] $end
$var wire 8 <$ x [7:0] $end
$var wire 32 =$ product_ext [31:0] $end
$var wire 16 >$ product [15:0] $end
$var wire 32 ?$ acc_out [31:0] $end
$var parameter 32 @$ ACC_WIDTH $end
$var parameter 32 A$ DATA_WIDTH $end
$var parameter 64 B$ PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[12] $end
$var parameter 5 C$ i $end
$scope module u_mac $end
$var wire 32 D$ acc_in [31:0] $end
$var wire 8 E$ w [7:0] $end
$var wire 8 F$ x [7:0] $end
$var wire 32 G$ product_ext [31:0] $end
$var wire 16 H$ product [15:0] $end
$var wire 32 I$ acc_out [31:0] $end
$var parameter 32 J$ ACC_WIDTH $end
$var parameter 32 K$ DATA_WIDTH $end
$var parameter 64 L$ PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[13] $end
$var parameter 5 M$ i $end
$scope module u_mac $end
$var wire 32 N$ acc_in [31:0] $end
$var wire 8 O$ w [7:0] $end
$var wire 8 P$ x [7:0] $end
$var wire 32 Q$ product_ext [31:0] $end
$var wire 16 R$ product [15:0] $end
$var wire 32 S$ acc_out [31:0] $end
$var parameter 32 T$ ACC_WIDTH $end
$var parameter 32 U$ DATA_WIDTH $end
$var parameter 64 V$ PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[14] $end
$var parameter 5 W$ i $end
$scope module u_mac $end
$var wire 32 X$ acc_in [31:0] $end
$var wire 8 Y$ w [7:0] $end
$var wire 8 Z$ x [7:0] $end
$var wire 32 [$ product_ext [31:0] $end
$var wire 16 \$ product [15:0] $end
$var wire 32 ]$ acc_out [31:0] $end
$var parameter 32 ^$ ACC_WIDTH $end
$var parameter 32 _$ DATA_WIDTH $end
$var parameter 64 `$ PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[15] $end
$var parameter 5 a$ i $end
$scope module u_mac $end
$var wire 32 b$ acc_in [31:0] $end
$var wire 8 c$ w [7:0] $end
$var wire 8 d$ x [7:0] $end
$var wire 32 e$ product_ext [31:0] $end
$var wire 16 f$ product [15:0] $end
$var wire 32 g$ acc_out [31:0] $end
$var parameter 32 h$ ACC_WIDTH $end
$var parameter 32 i$ DATA_WIDTH $end
$var parameter 64 j$ PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[16] $end
$var parameter 6 k$ i $end
$scope module u_mac $end
$var wire 32 l$ acc_in [31:0] $end
$var wire 8 m$ w [7:0] $end
$var wire 8 n$ x [7:0] $end
$var wire 32 o$ product_ext [31:0] $end
$var wire 16 p$ product [15:0] $end
$var wire 32 q$ acc_out [31:0] $end
$var parameter 32 r$ ACC_WIDTH $end
$var parameter 32 s$ DATA_WIDTH $end
$var parameter 64 t$ PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[17] $end
$var parameter 6 u$ i $end
$scope module u_mac $end
$var wire 32 v$ acc_in [31:0] $end
$var wire 8 w$ w [7:0] $end
$var wire 8 x$ x [7:0] $end
$var wire 32 y$ product_ext [31:0] $end
$var wire 16 z$ product [15:0] $end
$var wire 32 {$ acc_out [31:0] $end
$var parameter 32 |$ ACC_WIDTH $end
$var parameter 32 }$ DATA_WIDTH $end
$var parameter 64 ~$ PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[18] $end
$var parameter 6 !% i $end
$scope module u_mac $end
$var wire 32 "% acc_in [31:0] $end
$var wire 8 #% w [7:0] $end
$var wire 8 $% x [7:0] $end
$var wire 32 %% product_ext [31:0] $end
$var wire 16 &% product [15:0] $end
$var wire 32 '% acc_out [31:0] $end
$var parameter 32 (% ACC_WIDTH $end
$var parameter 32 )% DATA_WIDTH $end
$var parameter 64 *% PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[19] $end
$var parameter 6 +% i $end
$scope module u_mac $end
$var wire 32 ,% acc_in [31:0] $end
$var wire 8 -% w [7:0] $end
$var wire 8 .% x [7:0] $end
$var wire 32 /% product_ext [31:0] $end
$var wire 16 0% product [15:0] $end
$var wire 32 1% acc_out [31:0] $end
$var parameter 32 2% ACC_WIDTH $end
$var parameter 32 3% DATA_WIDTH $end
$var parameter 64 4% PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[20] $end
$var parameter 6 5% i $end
$scope module u_mac $end
$var wire 32 6% acc_in [31:0] $end
$var wire 8 7% w [7:0] $end
$var wire 8 8% x [7:0] $end
$var wire 32 9% product_ext [31:0] $end
$var wire 16 :% product [15:0] $end
$var wire 32 ;% acc_out [31:0] $end
$var parameter 32 <% ACC_WIDTH $end
$var parameter 32 =% DATA_WIDTH $end
$var parameter 64 >% PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[21] $end
$var parameter 6 ?% i $end
$scope module u_mac $end
$var wire 32 @% acc_in [31:0] $end
$var wire 8 A% w [7:0] $end
$var wire 8 B% x [7:0] $end
$var wire 32 C% product_ext [31:0] $end
$var wire 16 D% product [15:0] $end
$var wire 32 E% acc_out [31:0] $end
$var parameter 32 F% ACC_WIDTH $end
$var parameter 32 G% DATA_WIDTH $end
$var parameter 64 H% PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[22] $end
$var parameter 6 I% i $end
$scope module u_mac $end
$var wire 32 J% acc_in [31:0] $end
$var wire 8 K% w [7:0] $end
$var wire 8 L% x [7:0] $end
$var wire 32 M% product_ext [31:0] $end
$var wire 16 N% product [15:0] $end
$var wire 32 O% acc_out [31:0] $end
$var parameter 32 P% ACC_WIDTH $end
$var parameter 32 Q% DATA_WIDTH $end
$var parameter 64 R% PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[23] $end
$var parameter 6 S% i $end
$scope module u_mac $end
$var wire 32 T% acc_in [31:0] $end
$var wire 8 U% w [7:0] $end
$var wire 8 V% x [7:0] $end
$var wire 32 W% product_ext [31:0] $end
$var wire 16 X% product [15:0] $end
$var wire 32 Y% acc_out [31:0] $end
$var parameter 32 Z% ACC_WIDTH $end
$var parameter 32 [% DATA_WIDTH $end
$var parameter 64 \% PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[24] $end
$var parameter 6 ]% i $end
$scope module u_mac $end
$var wire 32 ^% acc_in [31:0] $end
$var wire 8 _% w [7:0] $end
$var wire 8 `% x [7:0] $end
$var wire 32 a% product_ext [31:0] $end
$var wire 16 b% product [15:0] $end
$var wire 32 c% acc_out [31:0] $end
$var parameter 32 d% ACC_WIDTH $end
$var parameter 32 e% DATA_WIDTH $end
$var parameter 64 f% PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[25] $end
$var parameter 6 g% i $end
$scope module u_mac $end
$var wire 32 h% acc_in [31:0] $end
$var wire 8 i% w [7:0] $end
$var wire 8 j% x [7:0] $end
$var wire 32 k% product_ext [31:0] $end
$var wire 16 l% product [15:0] $end
$var wire 32 m% acc_out [31:0] $end
$var parameter 32 n% ACC_WIDTH $end
$var parameter 32 o% DATA_WIDTH $end
$var parameter 64 p% PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[26] $end
$var parameter 6 q% i $end
$scope module u_mac $end
$var wire 32 r% acc_in [31:0] $end
$var wire 8 s% w [7:0] $end
$var wire 8 t% x [7:0] $end
$var wire 32 u% product_ext [31:0] $end
$var wire 16 v% product [15:0] $end
$var wire 32 w% acc_out [31:0] $end
$var parameter 32 x% ACC_WIDTH $end
$var parameter 32 y% DATA_WIDTH $end
$var parameter 64 z% PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[27] $end
$var parameter 6 {% i $end
$scope module u_mac $end
$var wire 32 |% acc_in [31:0] $end
$var wire 8 }% w [7:0] $end
$var wire 8 ~% x [7:0] $end
$var wire 32 !& product_ext [31:0] $end
$var wire 16 "& product [15:0] $end
$var wire 32 #& acc_out [31:0] $end
$var parameter 32 $& ACC_WIDTH $end
$var parameter 32 %& DATA_WIDTH $end
$var parameter 64 && PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[28] $end
$var parameter 6 '& i $end
$scope module u_mac $end
$var wire 32 (& acc_in [31:0] $end
$var wire 8 )& w [7:0] $end
$var wire 8 *& x [7:0] $end
$var wire 32 +& product_ext [31:0] $end
$var wire 16 ,& product [15:0] $end
$var wire 32 -& acc_out [31:0] $end
$var parameter 32 .& ACC_WIDTH $end
$var parameter 32 /& DATA_WIDTH $end
$var parameter 64 0& PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[29] $end
$var parameter 6 1& i $end
$scope module u_mac $end
$var wire 32 2& acc_in [31:0] $end
$var wire 8 3& w [7:0] $end
$var wire 8 4& x [7:0] $end
$var wire 32 5& product_ext [31:0] $end
$var wire 16 6& product [15:0] $end
$var wire 32 7& acc_out [31:0] $end
$var parameter 32 8& ACC_WIDTH $end
$var parameter 32 9& DATA_WIDTH $end
$var parameter 64 :& PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[30] $end
$var parameter 6 ;& i $end
$scope module u_mac $end
$var wire 32 <& acc_in [31:0] $end
$var wire 8 =& w [7:0] $end
$var wire 8 >& x [7:0] $end
$var wire 32 ?& product_ext [31:0] $end
$var wire 16 @& product [15:0] $end
$var wire 32 A& acc_out [31:0] $end
$var parameter 32 B& ACC_WIDTH $end
$var parameter 32 C& DATA_WIDTH $end
$var parameter 64 D& PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[31] $end
$var parameter 6 E& i $end
$scope module u_mac $end
$var wire 32 F& acc_in [31:0] $end
$var wire 8 G& w [7:0] $end
$var wire 8 H& x [7:0] $end
$var wire 32 I& product_ext [31:0] $end
$var wire 16 J& product [15:0] $end
$var wire 32 K& acc_out [31:0] $end
$var parameter 32 L& ACC_WIDTH $end
$var parameter 32 M& DATA_WIDTH $end
$var parameter 64 N& PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_TREE_INPUT[0] $end
$var parameter 2 O& i $end
$upscope $end
$scope begin GEN_TREE_INPUT[1] $end
$var parameter 2 P& i $end
$upscope $end
$scope begin GEN_TREE_INPUT[2] $end
$var parameter 3 Q& i $end
$upscope $end
$scope begin GEN_TREE_INPUT[3] $end
$var parameter 3 R& i $end
$upscope $end
$scope begin GEN_TREE_INPUT[4] $end
$var parameter 4 S& i $end
$upscope $end
$scope begin GEN_TREE_INPUT[5] $end
$var parameter 4 T& i $end
$upscope $end
$scope begin GEN_TREE_INPUT[6] $end
$var parameter 4 U& i $end
$upscope $end
$scope begin GEN_TREE_INPUT[7] $end
$var parameter 4 V& i $end
$upscope $end
$scope begin GEN_TREE_INPUT[8] $end
$var parameter 5 W& i $end
$upscope $end
$scope begin GEN_TREE_INPUT[9] $end
$var parameter 5 X& i $end
$upscope $end
$scope begin GEN_TREE_INPUT[10] $end
$var parameter 5 Y& i $end
$upscope $end
$scope begin GEN_TREE_INPUT[11] $end
$var parameter 5 Z& i $end
$upscope $end
$scope begin GEN_TREE_INPUT[12] $end
$var parameter 5 [& i $end
$upscope $end
$scope begin GEN_TREE_INPUT[13] $end
$var parameter 5 \& i $end
$upscope $end
$scope begin GEN_TREE_INPUT[14] $end
$var parameter 5 ]& i $end
$upscope $end
$scope begin GEN_TREE_INPUT[15] $end
$var parameter 5 ^& i $end
$upscope $end
$scope begin GEN_TREE_INPUT[16] $end
$var parameter 6 _& i $end
$upscope $end
$scope begin GEN_TREE_INPUT[17] $end
$var parameter 6 `& i $end
$upscope $end
$scope begin GEN_TREE_INPUT[18] $end
$var parameter 6 a& i $end
$upscope $end
$scope begin GEN_TREE_INPUT[19] $end
$var parameter 6 b& i $end
$upscope $end
$scope begin GEN_TREE_INPUT[20] $end
$var parameter 6 c& i $end
$upscope $end
$scope begin GEN_TREE_INPUT[21] $end
$var parameter 6 d& i $end
$upscope $end
$scope begin GEN_TREE_INPUT[22] $end
$var parameter 6 e& i $end
$upscope $end
$scope begin GEN_TREE_INPUT[23] $end
$var parameter 6 f& i $end
$upscope $end
$scope begin GEN_TREE_INPUT[24] $end
$var parameter 6 g& i $end
$upscope $end
$scope begin GEN_TREE_INPUT[25] $end
$var parameter 6 h& i $end
$upscope $end
$scope begin GEN_TREE_INPUT[26] $end
$var parameter 6 i& i $end
$upscope $end
$scope begin GEN_TREE_INPUT[27] $end
$var parameter 6 j& i $end
$upscope $end
$scope begin GEN_TREE_INPUT[28] $end
$var parameter 6 k& i $end
$upscope $end
$scope begin GEN_TREE_INPUT[29] $end
$var parameter 6 l& i $end
$upscope $end
$scope begin GEN_TREE_INPUT[30] $end
$var parameter 6 m& i $end
$upscope $end
$scope begin GEN_TREE_INPUT[31] $end
$var parameter 6 n& i $end
$upscope $end
$scope begin GEN_TREE_LEVEL[0] $end
$var parameter 2 o& level $end
$scope begin GEN_TREE_NODE[0] $end
$var parameter 2 p& node $end
$upscope $end
$scope begin GEN_TREE_NODE[1] $end
$var parameter 2 q& node $end
$upscope $end
$scope begin GEN_TREE_NODE[2] $end
$var parameter 3 r& node $end
$upscope $end
$scope begin GEN_TREE_NODE[3] $end
$var parameter 3 s& node $end
$upscope $end
$scope begin GEN_TREE_NODE[4] $end
$var parameter 4 t& node $end
$upscope $end
$scope begin GEN_TREE_NODE[5] $end
$var parameter 4 u& node $end
$upscope $end
$scope begin GEN_TREE_NODE[6] $end
$var parameter 4 v& node $end
$upscope $end
$scope begin GEN_TREE_NODE[7] $end
$var parameter 4 w& node $end
$upscope $end
$scope begin GEN_TREE_NODE[8] $end
$var parameter 5 x& node $end
$upscope $end
$scope begin GEN_TREE_NODE[9] $end
$var parameter 5 y& node $end
$upscope $end
$scope begin GEN_TREE_NODE[10] $end
$var parameter 5 z& node $end
$upscope $end
$scope begin GEN_TREE_NODE[11] $end
$var parameter 5 {& node $end
$upscope $end
$scope begin GEN_TREE_NODE[12] $end
$var parameter 5 |& node $end
$upscope $end
$scope begin GEN_TREE_NODE[13] $end
$var parameter 5 }& node $end
$upscope $end
$scope begin GEN_TREE_NODE[14] $end
$var parameter 5 ~& node $end
$upscope $end
$scope begin GEN_TREE_NODE[15] $end
$var parameter 5 !' node $end
$upscope $end
$upscope $end
$scope begin GEN_TREE_LEVEL[1] $end
$var parameter 2 "' level $end
$scope begin GEN_TREE_NODE[0] $end
$var parameter 2 #' node $end
$upscope $end
$scope begin GEN_TREE_NODE[1] $end
$var parameter 2 $' node $end
$upscope $end
$scope begin GEN_TREE_NODE[2] $end
$var parameter 3 %' node $end
$upscope $end
$scope begin GEN_TREE_NODE[3] $end
$var parameter 3 &' node $end
$upscope $end
$scope begin GEN_TREE_NODE[4] $end
$var parameter 4 '' node $end
$upscope $end
$scope begin GEN_TREE_NODE[5] $end
$var parameter 4 (' node $end
$upscope $end
$scope begin GEN_TREE_NODE[6] $end
$var parameter 4 )' node $end
$upscope $end
$scope begin GEN_TREE_NODE[7] $end
$var parameter 4 *' node $end
$upscope $end
$upscope $end
$scope begin GEN_TREE_LEVEL[2] $end
$var parameter 3 +' level $end
$scope begin GEN_TREE_NODE[0] $end
$var parameter 2 ,' node $end
$upscope $end
$scope begin GEN_TREE_NODE[1] $end
$var parameter 2 -' node $end
$upscope $end
$scope begin GEN_TREE_NODE[2] $end
$var parameter 3 .' node $end
$upscope $end
$scope begin GEN_TREE_NODE[3] $end
$var parameter 3 /' node $end
$upscope $end
$upscope $end
$scope begin GEN_TREE_LEVEL[3] $end
$var parameter 3 0' level $end
$scope begin GEN_TREE_NODE[0] $end
$var parameter 2 1' node $end
$upscope $end
$scope begin GEN_TREE_NODE[1] $end
$var parameter 2 2' node $end
$upscope $end
$upscope $end
$scope begin GEN_TREE_LEVEL[4] $end
$var parameter 4 3' level $end
$scope begin GEN_TREE_NODE[0] $end
$var parameter 2 4' node $end
$upscope $end
$upscope $end
$upscope $end
$upscope $end
$scope module u_f $end
$var wire 8 5' bias [7:0] $end
$var wire 1 A clk $end
$var wire 1 B rst $end
$var wire 1 E start $end
$var wire 256 6' w_bus [255:0] $end
$var wire 256 7' x_bus [255:0] $end
$var wire 16 8' x_group [15:0] $end
$var wire 16 9' w_group [15:0] $end
$var wire 32 :' final_acc [31:0] $end
$var wire 32 ;' bias_ext [31:0] $end
$var wire 32 <' acc_next [31:0] $end
$var parameter 32 =' ACC_WIDTH $end
$var parameter 32 >' DATA_WIDTH $end
$var parameter 32 ?' GROUPS $end
$var parameter 32 @' GROUP_INDEX_WIDTH $end
$var parameter 32 A' N_INPUTS $end
$var parameter 32 B' PARALLEL $end
$var reg 32 C' acc [31:0] $end
$var reg 1 * busy $end
$var reg 1 & done $end
$var reg 4 D' group_index [3:0] $end
$var reg 8 E' y [7:0] $end
$scope module u_mac8 $end
$var wire 32 F' acc_in [31:0] $end
$var wire 16 G' w_bus [15:0] $end
$var wire 16 H' x_bus [15:0] $end
$var wire 32 I' acc_out [31:0] $end
$var parameter 32 J' ACC_WIDTH $end
$var parameter 32 K' DATA_WIDTH $end
$var parameter 32 L' PARALLEL $end
$var parameter 32 M' TREE_LEVELS $end
$scope begin GEN_MAC[0] $end
$var parameter 2 N' i $end
$scope module u_mac $end
$var wire 32 O' acc_in [31:0] $end
$var wire 8 P' w [7:0] $end
$var wire 8 Q' x [7:0] $end
$var wire 32 R' product_ext [31:0] $end
$var wire 16 S' product [15:0] $end
$var wire 32 T' acc_out [31:0] $end
$var parameter 32 U' ACC_WIDTH $end
$var parameter 32 V' DATA_WIDTH $end
$var parameter 64 W' PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[1] $end
$var parameter 2 X' i $end
$scope module u_mac $end
$var wire 32 Y' acc_in [31:0] $end
$var wire 8 Z' w [7:0] $end
$var wire 8 [' x [7:0] $end
$var wire 32 \' product_ext [31:0] $end
$var wire 16 ]' product [15:0] $end
$var wire 32 ^' acc_out [31:0] $end
$var parameter 32 _' ACC_WIDTH $end
$var parameter 32 `' DATA_WIDTH $end
$var parameter 64 a' PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_TREE_INPUT[0] $end
$var parameter 2 b' i $end
$upscope $end
$scope begin GEN_TREE_INPUT[1] $end
$var parameter 2 c' i $end
$upscope $end
$scope begin GEN_TREE_LEVEL[0] $end
$var parameter 2 d' level $end
$scope begin GEN_TREE_NODE[0] $end
$var parameter 2 e' node $end
$upscope $end
$upscope $end
$upscope $end
$upscope $end
$scope module u_g $end
$var wire 8 f' bias [7:0] $end
$var wire 1 A clk $end
$var wire 1 B rst $end
$var wire 1 F start $end
$var wire 256 g' w_bus [255:0] $end
$var wire 256 h' x_bus [255:0] $end
$var wire 32 i' x_group [31:0] $end
$var wire 32 j' w_group [31:0] $end
$var wire 32 k' final_acc [31:0] $end
$var wire 32 l' bias_ext [31:0] $end
$var wire 32 m' acc_next [31:0] $end
$var parameter 32 n' ACC_WIDTH $end
$var parameter 32 o' DATA_WIDTH $end
$var parameter 32 p' GROUPS $end
$var parameter 32 q' GROUP_INDEX_WIDTH $end
$var parameter 32 r' N_INPUTS $end
$var parameter 32 s' PARALLEL $end
$var reg 32 t' acc [31:0] $end
$var reg 1 ) busy $end
$var reg 1 % done $end
$var reg 3 u' group_index [2:0] $end
$var reg 8 v' y [7:0] $end
$scope module u_mac8 $end
$var wire 32 w' acc_in [31:0] $end
$var wire 32 x' w_bus [31:0] $end
$var wire 32 y' x_bus [31:0] $end
$var wire 32 z' acc_out [31:0] $end
$var parameter 32 {' ACC_WIDTH $end
$var parameter 32 |' DATA_WIDTH $end
$var parameter 32 }' PARALLEL $end
$var parameter 32 ~' TREE_LEVELS $end
$scope begin GEN_MAC[0] $end
$var parameter 2 !( i $end
$scope module u_mac $end
$var wire 32 "( acc_in [31:0] $end
$var wire 8 #( w [7:0] $end
$var wire 8 $( x [7:0] $end
$var wire 32 %( product_ext [31:0] $end
$var wire 16 &( product [15:0] $end
$var wire 32 '( acc_out [31:0] $end
$var parameter 32 (( ACC_WIDTH $end
$var parameter 32 )( DATA_WIDTH $end
$var parameter 64 *( PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[1] $end
$var parameter 2 +( i $end
$scope module u_mac $end
$var wire 32 ,( acc_in [31:0] $end
$var wire 8 -( w [7:0] $end
$var wire 8 .( x [7:0] $end
$var wire 32 /( product_ext [31:0] $end
$var wire 16 0( product [15:0] $end
$var wire 32 1( acc_out [31:0] $end
$var parameter 32 2( ACC_WIDTH $end
$var parameter 32 3( DATA_WIDTH $end
$var parameter 64 4( PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[2] $end
$var parameter 3 5( i $end
$scope module u_mac $end
$var wire 32 6( acc_in [31:0] $end
$var wire 8 7( w [7:0] $end
$var wire 8 8( x [7:0] $end
$var wire 32 9( product_ext [31:0] $end
$var wire 16 :( product [15:0] $end
$var wire 32 ;( acc_out [31:0] $end
$var parameter 32 <( ACC_WIDTH $end
$var parameter 32 =( DATA_WIDTH $end
$var parameter 64 >( PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[3] $end
$var parameter 3 ?( i $end
$scope module u_mac $end
$var wire 32 @( acc_in [31:0] $end
$var wire 8 A( w [7:0] $end
$var wire 8 B( x [7:0] $end
$var wire 32 C( product_ext [31:0] $end
$var wire 16 D( product [15:0] $end
$var wire 32 E( acc_out [31:0] $end
$var parameter 32 F( ACC_WIDTH $end
$var parameter 32 G( DATA_WIDTH $end
$var parameter 64 H( PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_TREE_INPUT[0] $end
$var parameter 2 I( i $end
$upscope $end
$scope begin GEN_TREE_INPUT[1] $end
$var parameter 2 J( i $end
$upscope $end
$scope begin GEN_TREE_INPUT[2] $end
$var parameter 3 K( i $end
$upscope $end
$scope begin GEN_TREE_INPUT[3] $end
$var parameter 3 L( i $end
$upscope $end
$scope begin GEN_TREE_LEVEL[0] $end
$var parameter 2 M( level $end
$scope begin GEN_TREE_NODE[0] $end
$var parameter 2 N( node $end
$upscope $end
$scope begin GEN_TREE_NODE[1] $end
$var parameter 2 O( node $end
$upscope $end
$upscope $end
$scope begin GEN_TREE_LEVEL[1] $end
$var parameter 2 P( level $end
$scope begin GEN_TREE_NODE[0] $end
$var parameter 2 Q( node $end
$upscope $end
$upscope $end
$upscope $end
$upscope $end
$upscope $end
$enddefinitions $end
$comment Show the parameter values. $end
$dumpall
b0 Q(
b1 P(
b1 O(
b0 N(
b0 M(
b11 L(
b10 K(
b1 J(
b0 I(
b10000 H(
b1000 G(
b100000 F(
b11 ?(
b10000 >(
b1000 =(
b100000 <(
b10 5(
b10000 4(
b1000 3(
b100000 2(
b1 +(
b10000 *(
b1000 )(
b100000 ((
b0 !(
b10 ~'
b100 }'
b1000 |'
b100000 {'
b100 s'
b100000 r'
b11 q'
b1000 p'
b1000 o'
b100000 n'
b0 e'
b0 d'
b1 c'
b0 b'
b10000 a'
b1000 `'
b100000 _'
b1 X'
b10000 W'
b1000 V'
b100000 U'
b0 N'
b1 M'
b10 L'
b1000 K'
b100000 J'
b10 B'
b100000 A'
b100 @'
b10000 ?'
b1000 >'
b100000 ='
b0 4'
b100 3'
b1 2'
b0 1'
b11 0'
b11 /'
b10 .'
b1 -'
b0 ,'
b10 +'
b111 *'
b110 )'
b101 ('
b100 ''
b11 &'
b10 %'
b1 $'
b0 #'
b1 "'
b1111 !'
b1110 ~&
b1101 }&
b1100 |&
b1011 {&
b1010 z&
b1001 y&
b1000 x&
b111 w&
b110 v&
b101 u&
b100 t&
b11 s&
b10 r&
b1 q&
b0 p&
b0 o&
b11111 n&
b11110 m&
b11101 l&
b11100 k&
b11011 j&
b11010 i&
b11001 h&
b11000 g&
b10111 f&
b10110 e&
b10101 d&
b10100 c&
b10011 b&
b10010 a&
b10001 `&
b10000 _&
b1111 ^&
b1110 ]&
b1101 \&
b1100 [&
b1011 Z&
b1010 Y&
b1001 X&
b1000 W&
b111 V&
b110 U&
b101 T&
b100 S&
b11 R&
b10 Q&
b1 P&
b0 O&
b10000 N&
b1000 M&
b100000 L&
b11111 E&
b10000 D&
b1000 C&
b100000 B&
b11110 ;&
b10000 :&
b1000 9&
b100000 8&
b11101 1&
b10000 0&
b1000 /&
b100000 .&
b11100 '&
b10000 &&
b1000 %&
b100000 $&
b11011 {%
b10000 z%
b1000 y%
b100000 x%
b11010 q%
b10000 p%
b1000 o%
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b100000 -
$end
#0
$dumpvars
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$end
#5000
b0 V
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1A
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b100000001000000010000000100000001000000010000000100000001 U
b100000001000000010000000100000001000000010000000100000001 c
b100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001 G
b100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001 R
b100000001000000010000000100000001000000010000000100000001 T
b100000001000000010000000100000001000000010000000100000001 d
b100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001 K
b100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001 S
b100000 O
0B
1A
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0A
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b100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001 r"
b100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001 "#
b1000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001 H
b1000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001 o"
b100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001 q"
b100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001 ##
b1000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001 L
b1000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001 p"
b1000000 O
1A
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b100000001 G'
b100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001 I
b100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001 6'
b100000001 8'
b100000001 H'
b100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001 M
b100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001 7'
b100000 O
1A
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0A
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0A
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1*
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0A
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1A
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1A
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1A
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1A
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1A
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b1000000010000000100000001 j'
b1000000010000000100000001 x'
b100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001 J
b100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001 g'
b1000000010000000100000001 i'
b1000000010000000100000001 y'
b100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001 N
b100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001 h'
b100000 O
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