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FPGA-Neural/sim/neuron_parallel.vcd
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micheleandClaude Sonnet 5 1a6f0ba2ef fix: guard neuron_parallel against invalid N_INPUTS/PARALLEL combos 
Both Phase 2 findings (docs/FPGA-NeuralNetwork-Engine.md) shared one
root cause: GROUPS = N_INPUTS / PARALLEL is integer division. When
N_INPUTS is not an exact multiple of PARALLEL, the remainder inputs
were silently dropped from the accumulation (wrong result, no
error); when PARALLEL > N_INPUTS, GROUPS = 0 and the controller's
terminal condition was never met, hanging the neuron forever.

Added a single elaboration-time guard to rtl/neuron_parallel.v: a
`generate` block instantiates a deliberately undefined module when
N_INPUTS % PARALLEL != 0, forcing a hard failure in both simulation
and synthesis instead of a silent wrong answer or a deadlock. Valid
configurations are unaffected (the branch is never elaborated). The
validated datapath (mac8/mac_unit/accumulation/ReLU/saturation) is
untouched -- this is authorized as a scoped exception to the
"core is fixed, do not touch" project policy, for this guard only.

- sim/neuron_parallel_guard_negative_nonmultiple_tb.v and
  sim/neuron_parallel_guard_negative_degenerate_tb.v: negative tests
  that must fail to elaborate; verified both fail with the expected
  "Unknown module type" error.
- sim/parameter_sweep_tb.v: rewritten to valid-configs-only (the
  three configs that used to demonstrate truncation/hang no longer
  compile, by design); added PARALLEL=2 and PARALLEL=4 configs,
  the two best-performing values from
  docs/FPGA-Neural-Datapatch-Benchmark.md.
- Full regression re-run after the RTL change: all existing
  testbenches still pass unchanged.

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01WQV3vS9TXaGDJ5cRfnfidt
2026-09-02 14:41:49 +02:00

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$date
Wed Sep 2 14:41:17 2026
$end
$version
Icarus Verilog
$end
$timescale
1ps
$end
$scope module tb $end
$var wire 8 ! y [7:0] $end
$var wire 1 " done $end
$var wire 1 # busy $end
$var parameter 32 $ ACC_WIDTH $end
$var parameter 32 % DATA_WIDTH $end
$var parameter 32 & N_INPUTS $end
$var parameter 32 ' PARALLEL $end
$var reg 8 ( bias [7:0] $end
$var reg 1 ) clk $end
$var reg 1 * rst $end
$var reg 1 + start $end
$var reg 256 , w_bus [255:0] $end
$var reg 256 - x_bus [255:0] $end
$var integer 32 . errors [31:0] $end
$var integer 32 / i [31:0] $end
$scope module dut $end
$var wire 8 0 bias [7:0] $end
$var wire 1 ) clk $end
$var wire 1 * rst $end
$var wire 1 + start $end
$var wire 256 1 w_bus [255:0] $end
$var wire 256 2 x_bus [255:0] $end
$var wire 64 3 x_group [63:0] $end
$var wire 64 4 w_group [63:0] $end
$var wire 32 5 final_acc [31:0] $end
$var wire 32 6 bias_ext [31:0] $end
$var wire 32 7 acc_next [31:0] $end
$var parameter 32 8 ACC_WIDTH $end
$var parameter 32 9 DATA_WIDTH $end
$var parameter 32 : GROUPS $end
$var parameter 32 ; GROUP_INDEX_WIDTH $end
$var parameter 32 < N_INPUTS $end
$var parameter 32 = PARALLEL $end
$var reg 32 > acc [31:0] $end
$var reg 1 # busy $end
$var reg 1 " done $end
$var reg 2 ? group_index [1:0] $end
$var reg 8 @ y [7:0] $end
$scope module u_mac8 $end
$var wire 32 A acc_in [31:0] $end
$var wire 64 B w_bus [63:0] $end
$var wire 64 C x_bus [63:0] $end
$var wire 32 D acc_out [31:0] $end
$var parameter 32 E ACC_WIDTH $end
$var parameter 32 F DATA_WIDTH $end
$var parameter 32 G PARALLEL $end
$var parameter 32 H TREE_LEVELS $end
$scope begin GEN_MAC[0] $end
$var parameter 2 I i $end
$scope module u_mac $end
$var wire 32 J acc_in [31:0] $end
$var wire 8 K w [7:0] $end
$var wire 8 L x [7:0] $end
$var wire 32 M product_ext [31:0] $end
$var wire 16 N product [15:0] $end
$var wire 32 O acc_out [31:0] $end
$var parameter 32 P ACC_WIDTH $end
$var parameter 32 Q DATA_WIDTH $end
$var parameter 64 R PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[1] $end
$var parameter 2 S i $end
$scope module u_mac $end
$var wire 32 T acc_in [31:0] $end
$var wire 8 U w [7:0] $end
$var wire 8 V x [7:0] $end
$var wire 32 W product_ext [31:0] $end
$var wire 16 X product [15:0] $end
$var wire 32 Y acc_out [31:0] $end
$var parameter 32 Z ACC_WIDTH $end
$var parameter 32 [ DATA_WIDTH $end
$var parameter 64 \ PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[2] $end
$var parameter 3 ] i $end
$scope module u_mac $end
$var wire 32 ^ acc_in [31:0] $end
$var wire 8 _ w [7:0] $end
$var wire 8 ` x [7:0] $end
$var wire 32 a product_ext [31:0] $end
$var wire 16 b product [15:0] $end
$var wire 32 c acc_out [31:0] $end
$var parameter 32 d ACC_WIDTH $end
$var parameter 32 e DATA_WIDTH $end
$var parameter 64 f PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[3] $end
$var parameter 3 g i $end
$scope module u_mac $end
$var wire 32 h acc_in [31:0] $end
$var wire 8 i w [7:0] $end
$var wire 8 j x [7:0] $end
$var wire 32 k product_ext [31:0] $end
$var wire 16 l product [15:0] $end
$var wire 32 m acc_out [31:0] $end
$var parameter 32 n ACC_WIDTH $end
$var parameter 32 o DATA_WIDTH $end
$var parameter 64 p PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[4] $end
$var parameter 4 q i $end
$scope module u_mac $end
$var wire 32 r acc_in [31:0] $end
$var wire 8 s w [7:0] $end
$var wire 8 t x [7:0] $end
$var wire 32 u product_ext [31:0] $end
$var wire 16 v product [15:0] $end
$var wire 32 w acc_out [31:0] $end
$var parameter 32 x ACC_WIDTH $end
$var parameter 32 y DATA_WIDTH $end
$var parameter 64 z PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[5] $end
$var parameter 4 { i $end
$scope module u_mac $end
$var wire 32 | acc_in [31:0] $end
$var wire 8 } w [7:0] $end
$var wire 8 ~ x [7:0] $end
$var wire 32 !" product_ext [31:0] $end
$var wire 16 "" product [15:0] $end
$var wire 32 #" acc_out [31:0] $end
$var parameter 32 $" ACC_WIDTH $end
$var parameter 32 %" DATA_WIDTH $end
$var parameter 64 &" PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[6] $end
$var parameter 4 '" i $end
$scope module u_mac $end
$var wire 32 (" acc_in [31:0] $end
$var wire 8 )" w [7:0] $end
$var wire 8 *" x [7:0] $end
$var wire 32 +" product_ext [31:0] $end
$var wire 16 ," product [15:0] $end
$var wire 32 -" acc_out [31:0] $end
$var parameter 32 ." ACC_WIDTH $end
$var parameter 32 /" DATA_WIDTH $end
$var parameter 64 0" PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[7] $end
$var parameter 4 1" i $end
$scope module u_mac $end
$var wire 32 2" acc_in [31:0] $end
$var wire 8 3" w [7:0] $end
$var wire 8 4" x [7:0] $end
$var wire 32 5" product_ext [31:0] $end
$var wire 16 6" product [15:0] $end
$var wire 32 7" acc_out [31:0] $end
$var parameter 32 8" ACC_WIDTH $end
$var parameter 32 9" DATA_WIDTH $end
$var parameter 64 :" PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_TREE_INPUT[0] $end
$var parameter 2 ;" i $end
$upscope $end
$scope begin GEN_TREE_INPUT[1] $end
$var parameter 2 <" i $end
$upscope $end
$scope begin GEN_TREE_INPUT[2] $end
$var parameter 3 =" i $end
$upscope $end
$scope begin GEN_TREE_INPUT[3] $end
$var parameter 3 >" i $end
$upscope $end
$scope begin GEN_TREE_INPUT[4] $end
$var parameter 4 ?" i $end
$upscope $end
$scope begin GEN_TREE_INPUT[5] $end
$var parameter 4 @" i $end
$upscope $end
$scope begin GEN_TREE_INPUT[6] $end
$var parameter 4 A" i $end
$upscope $end
$scope begin GEN_TREE_INPUT[7] $end
$var parameter 4 B" i $end
$upscope $end
$scope begin GEN_TREE_LEVEL[0] $end
$var parameter 2 C" level $end
$scope begin GEN_TREE_NODE[0] $end
$var parameter 2 D" node $end
$upscope $end
$scope begin GEN_TREE_NODE[1] $end
$var parameter 2 E" node $end
$upscope $end
$scope begin GEN_TREE_NODE[2] $end
$var parameter 3 F" node $end
$upscope $end
$scope begin GEN_TREE_NODE[3] $end
$var parameter 3 G" node $end
$upscope $end
$upscope $end
$scope begin GEN_TREE_LEVEL[1] $end
$var parameter 2 H" level $end
$scope begin GEN_TREE_NODE[0] $end
$var parameter 2 I" node $end
$upscope $end
$scope begin GEN_TREE_NODE[1] $end
$var parameter 2 J" node $end
$upscope $end
$upscope $end
$scope begin GEN_TREE_LEVEL[2] $end
$var parameter 3 K" level $end
$scope begin GEN_TREE_NODE[0] $end
$var parameter 2 L" node $end
$upscope $end
$upscope $end
$upscope $end
$upscope $end
$scope task run_neuron $end
$upscope $end
$scope task test_1 $end
$upscope $end
$scope task test_2 $end
$upscope $end
$scope task test_3 $end
$upscope $end
$scope task test_4 $end
$upscope $end
$upscope $end
$enddefinitions $end
$comment Show the parameter values. $end
$dumpall
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b1000 =
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$end
#0
$dumpvars
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$end
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b100000010000000011 -
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b110010001100100011001000110010001100100011001000110010001100100 C
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b100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001 1
b1111111100000010111111110000001011111111000000101111111100000010 3
b1111111100000010111111110000001011111111000000101111111100000010 C
b1111111100000010111111110000001011111111000000101111111100000010111111110000001011111111000000101111111100000010111111110000001011111111000000101111111100000010111111110000001011111111000000101111111100000010111111110000001011111111000000101111111100000010 -
b1111111100000010111111110000001011111111000000101111111100000010111111110000001011111111000000101111111100000010111111110000001011111111000000101111111100000010111111110000001011111111000000101111111100000010111111110000001011111111000000101111111100000010 2
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