micheleandClaude Sonnet 5
97a21be240
Adds FPGA-exclusive access to the onboard W25Q128JV SPI NOR flash for weights/bias/network persistence, layered as spi_flash_master (raw SPI, USRMCLK-driven) -> flash_copy_engine (flash<->PSRAM streaming, erase- before-write, Page Program loop) -> flash_slot_manager (16-slot catalog with CRC32), exposed via 8 new SPI opcodes (0x40-0x47). Fixes two pre-existing bugs found during bring-up: a psram_controller.v request lost during power-up, and a one-cycle-pulse race in the PSRAM arbiter request handshake. Full simulation + real Yosys/nextpnr-ecp5 synthesis verification (0 errors, Fmax 66.68MHz) in WORKLOG.md and docs/FPGA-Neural-Flash-Subsystem-Verification.md. Also updates docs/pinout to reflect the 56-signal real .lpf (3 new flash pins) and documents the WRITE_RAM/READ_RAM host backpressure risk found while testing this subsystem. Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
51 lines
1.8 KiB
Verilog
51 lines
1.8 KiB
Verilog
`timescale 1ns/1ps
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// ================================================================
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// CRC32_BYTE - combinational one-byte CRC32 update (IEEE 802.3 /
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// zlib.crc32 algorithm: reflected polynomial 0xEDB88320, MSB-first
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// byte order, init 0xFFFFFFFF, final XOR 0xFFFFFFFF applied by the
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// CALLER when reading out the finished CRC, not baked in here so
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// this block is a pure, reusable byte-update step).
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//
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// This exact reflected-polynomial bit-serial-per-byte construction
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// is the standard, widely-documented way to compute the same CRC32
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// zlib/PNG/Ethernet use; it is NOT re-derived from the flash
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// subsystem's own design -- the independent oracle for this
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// project is tools/flash_catalog/oracle.py's `crc32()`, which calls
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// Python's stdlib `zlib.crc32` (a completely separate implementation
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// in a different language). The two are cross-checked bit-for-bit
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// by sim/crc32_tb.v -- see WORKLOG.md's F4 entry for the numbers.
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//
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// Usage: register `crc_out` into your own accumulator on the cycle
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// a new byte is valid, seeded at 32'hFFFFFFFF before the first byte
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// of a message; XOR the final accumulated value with 32'hFFFFFFFF
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// to get the conventional CRC32 result.
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// ================================================================
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module crc32_byte (
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input wire [31:0] crc_in,
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input wire [7:0] data,
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output wire [31:0] crc_out
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);
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function [31:0] next_crc;
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input [31:0] c_in;
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input [7:0] d;
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reg [31:0] c;
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integer k;
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begin
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c = c_in ^ {24'h0, d};
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for (k = 0; k < 8; k = k + 1) begin
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if (c[0])
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c = (c >> 1) ^ 32'hEDB88320;
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else
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c = c >> 1;
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end
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next_crc = c;
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end
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endfunction
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assign crc_out = next_crc(crc_in, data);
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endmodule
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