286 lines
6.7 KiB
Verilog
286 lines
6.7 KiB
Verilog
`timescale 1ns/1ps
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module tb;
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parameter DATA_WIDTH = 16;
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parameter FRAC_BITS = 8;
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parameter N_INPUTS = 64;
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parameter PARALLEL = 8;
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parameter ACC_WIDTH = 40;
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reg clk;
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reg rst;
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reg start;
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reg signed [DATA_WIDTH*N_INPUTS-1:0] x_bus;
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reg signed [DATA_WIDTH*N_INPUTS-1:0] w_bus;
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reg signed [DATA_WIDTH-1:0] bias;
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wire signed [DATA_WIDTH-1:0] y;
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wire busy;
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wire done;
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integer i;
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integer errors;
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neuron_parallel #(
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.DATA_WIDTH(DATA_WIDTH),
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.FRAC_BITS(FRAC_BITS),
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.N_INPUTS(N_INPUTS),
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.PARALLEL(PARALLEL),
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.ACC_WIDTH(ACC_WIDTH)
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) dut (
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.clk(clk),
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.rst(rst),
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.start(start),
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.x_bus(x_bus),
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.w_bus(w_bus),
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.bias(bias),
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.y(y),
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.busy(busy),
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.done(done)
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);
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// Clock: 10 ns
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initial begin
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clk = 0;
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forever #5 clk = ~clk;
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end
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// ------------------------------------------------------------
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// Helper: convert real value to Q8.8
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// ------------------------------------------------------------
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function signed [15:0] q8_8;
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input real value;
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begin
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q8_8 = $rtoi(value * 256.0);
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end
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endfunction
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// ------------------------------------------------------------
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// Start neuron and wait for completion
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// ------------------------------------------------------------
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task run_neuron;
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begin
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@(posedge clk);
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start = 1;
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@(posedge clk);
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start = 0;
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wait(done == 1);
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@(posedge clk);
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end
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endtask
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// ------------------------------------------------------------
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// TEST 1
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//
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// Diverse vector:
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//
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// x0 = 1.5 w0 = 2.0 -> 3.0
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// x1 = 2.0 w1 = -1.0 -> -2.0
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// x2 = 0.5 w2 = 0.25 -> 0.125
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//
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// bias = 0.609375
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//
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// total = 1.734375
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// Q8.8 = 444
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// ------------------------------------------------------------
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task test_1;
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begin
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$display("");
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$display("TEST 1: DIVERSE VECTOR");
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x_bus = 0;
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w_bus = 0;
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bias = q8_8(0.609375);
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x_bus[0*16 +: 16] = q8_8(1.5);
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w_bus[0*16 +: 16] = q8_8(2.0);
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x_bus[1*16 +: 16] = q8_8(2.0);
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w_bus[1*16 +: 16] = q8_8(-1.0);
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x_bus[2*16 +: 16] = q8_8(0.5);
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w_bus[2*16 +: 16] = q8_8(0.25);
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run_neuron;
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$display("RTL = %0d", y);
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$display("EXPECTED = 444");
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if (y !== 16'sd444) begin
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$display("FAIL - TEST 1");
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errors = errors + 1;
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end
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else begin
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$display("PASS - TEST 1");
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end
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end
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endtask
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// ------------------------------------------------------------
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// TEST 2
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//
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// All products negative.
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// ReLU must force output to zero.
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// ------------------------------------------------------------
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task test_2;
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begin
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$display("");
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$display("TEST 2: RELU");
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x_bus = 0;
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w_bus = 0;
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bias = 0;
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for (i = 0; i < N_INPUTS; i = i + 1) begin
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x_bus[i*16 +: 16] = q8_8(1.0);
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w_bus[i*16 +: 16] = q8_8(-1.0);
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end
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run_neuron;
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$display("RTL = %0d", y);
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$display("EXPECTED = 0");
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if (y !== 16'sd0) begin
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$display("FAIL - TEST 2");
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errors = errors + 1;
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end
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else begin
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$display("PASS - TEST 2");
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end
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end
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endtask
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// ------------------------------------------------------------
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// TEST 3
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//
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// Large positive result.
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// Must saturate to +32767.
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// ------------------------------------------------------------
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task test_3;
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begin
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$display("");
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$display("TEST 3: POSITIVE SATURATION");
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x_bus = 0;
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w_bus = 0;
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bias = 0;
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for (i = 0; i < N_INPUTS; i = i + 1) begin
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x_bus[i*16 +: 16] = q8_8(127.0);
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w_bus[i*16 +: 16] = q8_8(2.0);
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end
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run_neuron;
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$display("RTL = %0d", y);
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$display("EXPECTED = 32767");
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if (y !== 16'sd32767) begin
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$display("FAIL - TEST 3");
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errors = errors + 1;
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end
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else begin
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$display("PASS - TEST 3");
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end
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end
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endtask
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// ------------------------------------------------------------
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// TEST 4
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//
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// Mixed positive/negative products.
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//
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// 32 x (+1)
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// 32 x (-1)
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// sum = 0
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// bias = -1
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//
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// ReLU -> 0
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// ------------------------------------------------------------
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task test_4;
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begin
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$display("");
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$display("TEST 4: MIXED VALUES + NEGATIVE BIAS");
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x_bus = 0;
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w_bus = 0;
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bias = q8_8(-1.0);
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for (i = 0; i < N_INPUTS; i = i + 1) begin
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if ((i % 2) == 0) begin
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x_bus[i*16 +: 16] = q8_8(2.0);
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w_bus[i*16 +: 16] = q8_8(0.5);
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end
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else begin
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x_bus[i*16 +: 16] = q8_8(-1.0);
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w_bus[i*16 +: 16] = q8_8(1.0);
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end
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end
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run_neuron;
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$display("RTL = %0d", y);
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$display("EXPECTED = 0");
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if (y !== 16'sd0) begin
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$display("FAIL - TEST 4");
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errors = errors + 1;
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end
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else begin
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$display("PASS - TEST 4");
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end
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end
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endtask
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// ------------------------------------------------------------
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// MAIN
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// ------------------------------------------------------------
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initial begin
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$dumpfile("sim/neuron_parallel.vcd");
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$dumpvars(0, tb);
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rst = 1;
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start = 0;
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x_bus = 0;
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w_bus = 0;
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bias = 0;
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errors = 0;
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repeat (2) @(posedge clk);
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rst = 0;
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$display("");
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$display("==============================");
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$display("NEURON_PARALLEL TESTBENCH");
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$display("==============================");
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test_1;
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test_2;
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test_3;
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test_4;
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$display("");
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$display("==============================");
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if (errors == 0) begin
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$display("ALL TESTS PASSED");
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end
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else begin
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$display("FAILURES = %0d", errors);
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end
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$display("==============================");
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$display("");
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$finish;
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end
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endmodule |