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FPGA-Neural/sim/memory_interface.vcd
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micheleandClaude Sonnet 5 14c8d87194 test: certify runtime width early-termination (C.2), document BUG-003/004 
n_inputs_real/n_neurons_real early termination for valid values is
certified real: a "poison" region (data that would saturate the result
if read past the claimed limit) confirms no over-read, cycle counts
scale proportionally. n_inputs_real non-multiple-of-PARALLEL at runtime
matches the documented silent-truncation risk exactly.

n_inputs_real=0 / n_neurons_real=0 (BUG-003/004): confirmed incorrect
behavior in every repetition, but the exact triggering mechanism was
NOT fully isolated -- nearly-identical repeated tests produced
different symptoms (clean hang vs. silently processing the full build
width vs. a third cycle count matching neither). Reported in full,
including the inconsistency itself, rather than picking the cleanest
result. The two new permanent testbenches reflect this honestly: the
solid early-termination checks are hard assertions, the n_*_real=0
probe is deliberately observe-only given the non-deterministic result.

Full regression: 38/38 real tests pass.

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
2026-09-04 14:27:14 +02:00

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$date
Fri Sep 4 14:26:02 2026
$end
$version
Icarus Verilog
$end
$timescale
1ps
$end
$scope module memory_interface_tb $end
$var wire 1 ! ready $end
$var wire 16 " rdata [15:0] $end
$var wire 1 # mem_wr $end
$var wire 16 $ mem_wdata [15:0] $end
$var wire 1 % mem_req $end
$var wire 1 & mem_ready $end
$var wire 16 ' mem_rdata [15:0] $end
$var wire 23 ( mem_addr [22:0] $end
$var parameter 32 ) ADDR_WIDTH $end
$var parameter 32 * DATA_WIDTH $end
$var reg 23 + addr [22:0] $end
$var reg 1 , clk $end
$var reg 1 - req $end
$var reg 1 . rst $end
$var reg 16 / wdata [15:0] $end
$var reg 1 0 wr $end
$scope module dut $end
$var wire 23 1 addr [22:0] $end
$var wire 1 , clk $end
$var wire 1 2 lb_n $end
$var wire 1 - req $end
$var wire 1 . rst $end
$var wire 1 3 ub_n $end
$var wire 16 4 wdata [15:0] $end
$var wire 1 0 wr $end
$var wire 1 & mem_ready $end
$var wire 16 5 mem_rdata [15:0] $end
$var parameter 32 6 ADDR_WIDTH $end
$var parameter 32 7 DATA_WIDTH $end
$var parameter 2 8 STATE_IDLE $end
$var parameter 2 9 STATE_WAIT $end
$var reg 23 : mem_addr [22:0] $end
$var reg 1 ; mem_lb_n $end
$var reg 1 % mem_req $end
$var reg 1 < mem_ub_n $end
$var reg 16 = mem_wdata [15:0] $end
$var reg 1 # mem_wr $end
$var reg 16 > rdata [15:0] $end
$var reg 1 ! ready $end
$var reg 2 ? state [1:0] $end
$upscope $end
$scope module memory $end
$var wire 23 @ addr [22:0] $end
$var wire 1 , clk $end
$var wire 1 % req $end
$var wire 1 . rst $end
$var wire 16 A wdata [15:0] $end
$var wire 1 # wr $end
$var parameter 32 B ADDR_WIDTH $end
$var parameter 32 C DATA_WIDTH $end
$var parameter 32 D DEPTH $end
$var parameter 32 E READ_LATENCY $end
$var reg 1 F busy $end
$var reg 23 G pending_addr [22:0] $end
$var reg 16 H pending_wdata [15:0] $end
$var reg 1 I pending_wr $end
$var reg 16 J rdata [15:0] $end
$var reg 1 & ready $end
$var integer 32 K delay_count [31:0] $end
$var integer 32 L i [31:0] $end
$upscope $end
$scope task read_mem $end
$var reg 23 M address [22:0] $end
$var reg 16 N expected [15:0] $end
$var reg 16 O received [15:0] $end
$upscope $end
$scope task write_mem $end
$var reg 23 P address [22:0] $end
$var reg 16 Q data [15:0] $end
$upscope $end
$upscope $end
$enddefinitions $end
$comment Show the parameter values. $end
$dumpall
b10 E
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$end
#0
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