michele
1ddaa9adfd
Yosys + nextpnr-ecp5 synthesis of the extended spi_neuron_top.v (layer_sequencer + mux + arbiter Port C wired in), speed grade -8, N_INPUTS=32/N_NEURONS=1: PARALLEL=8 -> 40.57 MHz FAIL, PARALLEL=2 -> 42.54 MHz FAIL. Both worse than Phase 4 alone (~52.58/~55.85 MHz for the identical configs) -- the Phase 5 wiring cost real timing headroom. Critical path also shifted from Phase 4's saturation- comparator finding to neuron_memory's x_mem/w_mem LUT-RAM read-mux tree feeding the accumulator. Full analysis and candidate next steps (block RAM for x_mem/w_mem, pipelining, a seed sweep to separate placement noise from a structural bottleneck) recorded under Phase 7 in docs/FPGA-NeuralNetwork-Engine.md.
6060 lines
551 KiB
Plaintext
6060 lines
551 KiB
Plaintext
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/----------------------------------------------------------------------------\
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| yosys -- Yosys Open SYnthesis Suite |
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| Copyright (C) 2012 - 2026 Claire Xenia Wolf <claire@yosyshq.com> |
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| Distributed under an ISC-like license, type "license" to see terms |
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\----------------------------------------------------------------------------/
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Yosys 0.68+post (git sha1 c12172fbae8af5e20f6fb52e3d4e92d56ed587b6, Release, AppleClang clang++ 21.0.0.21000101)
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-- Executing script file `/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/synth/ecp5/spi_neuron_top_p8/synth.ys' --
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1. Executing Verilog-2005 frontend: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_slave.v
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Parsing SystemVerilog input from `/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_slave.v' to AST representation.
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Generating RTLIL representation for module `\spi_slave'.
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Successfully finished Verilog frontend.
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2. Executing Verilog-2005 frontend: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v
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Parsing SystemVerilog input from `/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v' to AST representation.
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Generating RTLIL representation for module `\spi_engine'.
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Successfully finished Verilog frontend.
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3. Executing Verilog-2005 frontend: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v
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Parsing SystemVerilog input from `/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v' to AST representation.
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Generating RTLIL representation for module `\layer_sequencer'.
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Successfully finished Verilog frontend.
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4. Executing Verilog-2005 frontend: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mem_arbiter.v
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Parsing SystemVerilog input from `/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mem_arbiter.v' to AST representation.
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Generating RTLIL representation for module `\mem_arbiter'.
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Successfully finished Verilog frontend.
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5. Executing Verilog-2005 frontend: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v
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Parsing SystemVerilog input from `/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v' to AST representation.
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Generating RTLIL representation for module `\neuron_memory'.
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Successfully finished Verilog frontend.
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6. Executing Verilog-2005 frontend: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/int8_memory_access.v
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Parsing SystemVerilog input from `/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/int8_memory_access.v' to AST representation.
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Generating RTLIL representation for module `\int8_memory_access'.
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Successfully finished Verilog frontend.
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7. Executing Verilog-2005 frontend: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/memory_interface.v
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Parsing SystemVerilog input from `/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/memory_interface.v' to AST representation.
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Generating RTLIL representation for module `\memory_interface'.
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Successfully finished Verilog frontend.
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8. Executing Verilog-2005 frontend: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/psram_controller.v
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Parsing SystemVerilog input from `/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/psram_controller.v' to AST representation.
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/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/psram_controller.v:93: Warning: Yosys has only limited support for tri-state logic at the moment.
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Generating RTLIL representation for module `\psram_controller'.
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Successfully finished Verilog frontend.
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9. Executing Verilog-2005 frontend: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v
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Parsing SystemVerilog input from `/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v' to AST representation.
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Generating RTLIL representation for module `\neuron_parallel'.
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Successfully finished Verilog frontend.
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10. Executing Verilog-2005 frontend: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v
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Parsing SystemVerilog input from `/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v' to AST representation.
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Generating RTLIL representation for module `\mac8'.
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Successfully finished Verilog frontend.
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11. Executing Verilog-2005 frontend: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v
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Parsing SystemVerilog input from `/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v' to AST representation.
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Generating RTLIL representation for module `\mac_unit'.
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Successfully finished Verilog frontend.
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12. Executing Verilog-2005 frontend: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_neuron_top.v
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Parsing SystemVerilog input from `/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_neuron_top.v' to AST representation.
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Generating RTLIL representation for module `\spi_neuron_top'.
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Successfully finished Verilog frontend.
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13. Executing HIERARCHY pass (managing design hierarchy).
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13.1. Analyzing design hierarchy..
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Top module: \spi_neuron_top
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Used module: \psram_controller
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Used module: \memory_interface
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Used module: \int8_memory_access
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Used module: \mem_arbiter
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Used module: \neuron_memory
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Used module: \neuron_parallel
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Used module: \mac8
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Used module: \mac_unit
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Used module: \layer_sequencer
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Used module: \spi_engine
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Used module: \spi_slave
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Parameter \DATA_WIDTH = 8
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Parameter \N_INPUTS = 32
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Parameter \PARALLEL = 8
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Parameter \ACC_WIDTH = 32
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13.2. Executing AST frontend in derive mode using pre-parsed AST for module `\neuron_parallel'.
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Parameter \DATA_WIDTH = 8
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Parameter \N_INPUTS = 32
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Parameter \PARALLEL = 8
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Parameter \ACC_WIDTH = 32
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Generating RTLIL representation for module `$paramod$18f95495176adabb8b1efa1a4c23d17992af7212\neuron_parallel'.
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Parameter \ADDR_WIDTH = 22
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13.3. Executing AST frontend in derive mode using pre-parsed AST for module `\int8_memory_access'.
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Parameter \ADDR_WIDTH = 22
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Generating RTLIL representation for module `$paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010110'.
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Parameter \DATA_WIDTH = 8
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Parameter \ACC_WIDTH = 32
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Parameter \PARALLEL = 8
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13.4. Executing AST frontend in derive mode using pre-parsed AST for module `\mac8'.
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Parameter \DATA_WIDTH = 8
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Parameter \ACC_WIDTH = 32
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Parameter \PARALLEL = 8
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Generating RTLIL representation for module `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8'.
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Parameter \DATA_WIDTH = 16
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Parameter \ACC_WIDTH = 40
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13.5. Executing AST frontend in derive mode using pre-parsed AST for module `\mac_unit'.
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Parameter \DATA_WIDTH = 16
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Parameter \ACC_WIDTH = 40
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Generating RTLIL representation for module `$paramod$913793164bb5cb5821e69ced9b7f953b27ebd911\mac_unit'.
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Parameter \DATA_WIDTH = 16
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Parameter \ACC_WIDTH = 40
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Found cached RTLIL representation for module `$paramod$913793164bb5cb5821e69ced9b7f953b27ebd911\mac_unit'.
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Parameter \DATA_WIDTH = 16
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Parameter \ACC_WIDTH = 40
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Found cached RTLIL representation for module `$paramod$913793164bb5cb5821e69ced9b7f953b27ebd911\mac_unit'.
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Parameter \DATA_WIDTH = 16
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Parameter \ACC_WIDTH = 40
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Found cached RTLIL representation for module `$paramod$913793164bb5cb5821e69ced9b7f953b27ebd911\mac_unit'.
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Parameter \DATA_WIDTH = 16
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Parameter \ACC_WIDTH = 40
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Found cached RTLIL representation for module `$paramod$913793164bb5cb5821e69ced9b7f953b27ebd911\mac_unit'.
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Parameter \DATA_WIDTH = 16
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Parameter \ACC_WIDTH = 40
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Found cached RTLIL representation for module `$paramod$913793164bb5cb5821e69ced9b7f953b27ebd911\mac_unit'.
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Parameter \DATA_WIDTH = 16
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Parameter \ACC_WIDTH = 40
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Found cached RTLIL representation for module `$paramod$913793164bb5cb5821e69ced9b7f953b27ebd911\mac_unit'.
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Parameter \DATA_WIDTH = 16
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Parameter \ACC_WIDTH = 40
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Found cached RTLIL representation for module `$paramod$913793164bb5cb5821e69ced9b7f953b27ebd911\mac_unit'.
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Reprocessing module mac8 because instantiated module mac_unit has become available.
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Generating RTLIL representation for module `\mac8'.
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Parameter \ADDR_WIDTH = 22
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Parameter \DATA_WIDTH = 16
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Parameter \CLK_FREQ_MHZ = 80
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13.6. Executing AST frontend in derive mode using pre-parsed AST for module `\psram_controller'.
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Parameter \ADDR_WIDTH = 22
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Parameter \DATA_WIDTH = 16
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Parameter \CLK_FREQ_MHZ = 80
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Generating RTLIL representation for module `$paramod$a7831d90e36f1741b8aab496b8012d26eb45bb8d\psram_controller'.
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Parameter \ADDR_WIDTH = 22
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Parameter \DATA_WIDTH = 16
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13.7. Executing AST frontend in derive mode using pre-parsed AST for module `\memory_interface'.
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Parameter \ADDR_WIDTH = 22
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Parameter \DATA_WIDTH = 16
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Generating RTLIL representation for module `$paramod$606976195f63b53ce91799ce1552927edc9dfdd0\memory_interface'.
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Parameter \ADDR_WIDTH = 22
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Found cached RTLIL representation for module `$paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010110'.
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Parameter \ADDR_WIDTH = 22
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13.8. Executing AST frontend in derive mode using pre-parsed AST for module `\mem_arbiter'.
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Parameter \ADDR_WIDTH = 22
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Generating RTLIL representation for module `$paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010110'.
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Parameter \ADDR_WIDTH = 22
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Parameter \DATA_WIDTH = 8
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Parameter \N_INPUTS = 32
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Parameter \N_NEURONS = 1
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Parameter \PARALLEL = 8
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Parameter \ACC_WIDTH = 32
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13.9. Executing AST frontend in derive mode using pre-parsed AST for module `\neuron_memory'.
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Parameter \ADDR_WIDTH = 22
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Parameter \DATA_WIDTH = 8
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Parameter \N_INPUTS = 32
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Parameter \N_NEURONS = 1
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Parameter \PARALLEL = 8
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Parameter \ACC_WIDTH = 32
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Generating RTLIL representation for module `$paramod$625bd452a5b2f1609c59261f6b45d2c3299924cf\neuron_memory'.
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Parameter \ADDR_WIDTH = 22
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Parameter \DATA_WIDTH = 8
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Parameter \N_WIDTH = 1
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Parameter \N_LAYERS = 4
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13.10. Executing AST frontend in derive mode using pre-parsed AST for module `\layer_sequencer'.
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Parameter \ADDR_WIDTH = 22
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Parameter \DATA_WIDTH = 8
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Parameter \N_WIDTH = 1
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Parameter \N_LAYERS = 4
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Generating RTLIL representation for module `$paramod$6ef4b294e25a3b4c04a5a9c8b8177ec3433db948\layer_sequencer'.
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Parameter \ADDR_WIDTH = 22
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Parameter \DATA_WIDTH = 8
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Parameter \N_INPUTS = 32
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Parameter \N_NEURONS = 1
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Parameter \PARALLEL = 8
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13.11. Executing AST frontend in derive mode using pre-parsed AST for module `\spi_engine'.
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Parameter \ADDR_WIDTH = 22
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Parameter \DATA_WIDTH = 8
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Parameter \N_INPUTS = 32
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Parameter \N_NEURONS = 1
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Parameter \PARALLEL = 8
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Generating RTLIL representation for module `$paramod$7daeb8f261fda395eabf31b36fd9e0630350662f\spi_engine'.
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13.12. Analyzing design hierarchy..
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Top module: \spi_neuron_top
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Used module: $paramod$a7831d90e36f1741b8aab496b8012d26eb45bb8d\psram_controller
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Used module: $paramod$606976195f63b53ce91799ce1552927edc9dfdd0\memory_interface
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Used module: $paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010110
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Used module: $paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010110
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Used module: $paramod$625bd452a5b2f1609c59261f6b45d2c3299924cf\neuron_memory
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Used module: \neuron_parallel
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Used module: $paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8
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Used module: \mac_unit
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Used module: \int8_memory_access
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Used module: $paramod$6ef4b294e25a3b4c04a5a9c8b8177ec3433db948\layer_sequencer
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Used module: $paramod$7daeb8f261fda395eabf31b36fd9e0630350662f\spi_engine
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Used module: \spi_slave
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Parameter \DATA_WIDTH = 8
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Parameter \ACC_WIDTH = 32
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13.13. Executing AST frontend in derive mode using pre-parsed AST for module `\mac_unit'.
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Parameter \DATA_WIDTH = 8
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Parameter \ACC_WIDTH = 32
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Generating RTLIL representation for module `$paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\mac_unit'.
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Parameter \DATA_WIDTH = 8
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Parameter \ACC_WIDTH = 32
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Found cached RTLIL representation for module `$paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\mac_unit'.
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Parameter \DATA_WIDTH = 8
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Parameter \ACC_WIDTH = 32
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Found cached RTLIL representation for module `$paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\mac_unit'.
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Parameter \DATA_WIDTH = 8
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Parameter \ACC_WIDTH = 32
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Found cached RTLIL representation for module `$paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\mac_unit'.
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Parameter \DATA_WIDTH = 8
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Parameter \ACC_WIDTH = 32
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Found cached RTLIL representation for module `$paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\mac_unit'.
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Parameter \DATA_WIDTH = 8
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Parameter \ACC_WIDTH = 32
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Found cached RTLIL representation for module `$paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\mac_unit'.
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Parameter \DATA_WIDTH = 8
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Parameter \ACC_WIDTH = 32
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Found cached RTLIL representation for module `$paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\mac_unit'.
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Parameter \DATA_WIDTH = 8
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Parameter \ACC_WIDTH = 32
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Found cached RTLIL representation for module `$paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\mac_unit'.
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Reprocessing module $paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8 because instantiated module $paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\mac_unit has become available.
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Generating RTLIL representation for module `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8'.
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Parameter \DATA_WIDTH = 8
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Parameter \N_INPUTS = 32
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Parameter \PARALLEL = 8
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Parameter \ACC_WIDTH = 32
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Found cached RTLIL representation for module `$paramod$18f95495176adabb8b1efa1a4c23d17992af7212\neuron_parallel'.
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Parameter \ADDR_WIDTH = 22
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Found cached RTLIL representation for module `$paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010110'.
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13.14. Analyzing design hierarchy..
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Top module: \spi_neuron_top
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Used module: $paramod$a7831d90e36f1741b8aab496b8012d26eb45bb8d\psram_controller
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Used module: $paramod$606976195f63b53ce91799ce1552927edc9dfdd0\memory_interface
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Used module: $paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010110
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Used module: $paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010110
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Used module: $paramod$625bd452a5b2f1609c59261f6b45d2c3299924cf\neuron_memory
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Used module: $paramod$18f95495176adabb8b1efa1a4c23d17992af7212\neuron_parallel
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Used module: \mac8
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Used module: \mac_unit
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Used module: $paramod$6ef4b294e25a3b4c04a5a9c8b8177ec3433db948\layer_sequencer
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Used module: $paramod$7daeb8f261fda395eabf31b36fd9e0630350662f\spi_engine
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Used module: \spi_slave
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Parameter \DATA_WIDTH = 16
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Parameter \ACC_WIDTH = 40
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Found cached RTLIL representation for module `$paramod$913793164bb5cb5821e69ced9b7f953b27ebd911\mac_unit'.
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Parameter \DATA_WIDTH = 16
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Parameter \ACC_WIDTH = 40
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Found cached RTLIL representation for module `$paramod$913793164bb5cb5821e69ced9b7f953b27ebd911\mac_unit'.
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Parameter \DATA_WIDTH = 16
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Parameter \ACC_WIDTH = 40
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Found cached RTLIL representation for module `$paramod$913793164bb5cb5821e69ced9b7f953b27ebd911\mac_unit'.
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Parameter \DATA_WIDTH = 16
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Parameter \ACC_WIDTH = 40
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Found cached RTLIL representation for module `$paramod$913793164bb5cb5821e69ced9b7f953b27ebd911\mac_unit'.
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Parameter \DATA_WIDTH = 16
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Parameter \ACC_WIDTH = 40
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Found cached RTLIL representation for module `$paramod$913793164bb5cb5821e69ced9b7f953b27ebd911\mac_unit'.
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Parameter \DATA_WIDTH = 16
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Parameter \ACC_WIDTH = 40
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Found cached RTLIL representation for module `$paramod$913793164bb5cb5821e69ced9b7f953b27ebd911\mac_unit'.
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Parameter \DATA_WIDTH = 16
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Parameter \ACC_WIDTH = 40
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Found cached RTLIL representation for module `$paramod$913793164bb5cb5821e69ced9b7f953b27ebd911\mac_unit'.
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Parameter \DATA_WIDTH = 16
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Parameter \ACC_WIDTH = 40
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Found cached RTLIL representation for module `$paramod$913793164bb5cb5821e69ced9b7f953b27ebd911\mac_unit'.
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Parameter \DATA_WIDTH = 8
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Parameter \ACC_WIDTH = 32
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Parameter \PARALLEL = 8
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Found cached RTLIL representation for module `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8'.
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13.15. Analyzing design hierarchy..
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Top module: \spi_neuron_top
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Used module: $paramod$a7831d90e36f1741b8aab496b8012d26eb45bb8d\psram_controller
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Used module: $paramod$606976195f63b53ce91799ce1552927edc9dfdd0\memory_interface
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Used module: $paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010110
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Used module: $paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010110
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Used module: $paramod$625bd452a5b2f1609c59261f6b45d2c3299924cf\neuron_memory
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Used module: $paramod$18f95495176adabb8b1efa1a4c23d17992af7212\neuron_parallel
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Used module: $paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8
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Used module: \mac_unit
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Used module: $paramod$6ef4b294e25a3b4c04a5a9c8b8177ec3433db948\layer_sequencer
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Used module: $paramod$7daeb8f261fda395eabf31b36fd9e0630350662f\spi_engine
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Used module: \spi_slave
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Parameter \DATA_WIDTH = 8
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Parameter \ACC_WIDTH = 32
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Found cached RTLIL representation for module `$paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\mac_unit'.
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Parameter \DATA_WIDTH = 8
|
|
Parameter \ACC_WIDTH = 32
|
|
Found cached RTLIL representation for module `$paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\mac_unit'.
|
|
Parameter \DATA_WIDTH = 8
|
|
Parameter \ACC_WIDTH = 32
|
|
Found cached RTLIL representation for module `$paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\mac_unit'.
|
|
Parameter \DATA_WIDTH = 8
|
|
Parameter \ACC_WIDTH = 32
|
|
Found cached RTLIL representation for module `$paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\mac_unit'.
|
|
Parameter \DATA_WIDTH = 8
|
|
Parameter \ACC_WIDTH = 32
|
|
Found cached RTLIL representation for module `$paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\mac_unit'.
|
|
Parameter \DATA_WIDTH = 8
|
|
Parameter \ACC_WIDTH = 32
|
|
Found cached RTLIL representation for module `$paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\mac_unit'.
|
|
Parameter \DATA_WIDTH = 8
|
|
Parameter \ACC_WIDTH = 32
|
|
Found cached RTLIL representation for module `$paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\mac_unit'.
|
|
Parameter \DATA_WIDTH = 8
|
|
Parameter \ACC_WIDTH = 32
|
|
Found cached RTLIL representation for module `$paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\mac_unit'.
|
|
|
|
13.16. Analyzing design hierarchy..
|
|
Top module: \spi_neuron_top
|
|
Used module: $paramod$a7831d90e36f1741b8aab496b8012d26eb45bb8d\psram_controller
|
|
Used module: $paramod$606976195f63b53ce91799ce1552927edc9dfdd0\memory_interface
|
|
Used module: $paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010110
|
|
Used module: $paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010110
|
|
Used module: $paramod$625bd452a5b2f1609c59261f6b45d2c3299924cf\neuron_memory
|
|
Used module: $paramod$18f95495176adabb8b1efa1a4c23d17992af7212\neuron_parallel
|
|
Used module: $paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8
|
|
Used module: $paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\mac_unit
|
|
Used module: $paramod$6ef4b294e25a3b4c04a5a9c8b8177ec3433db948\layer_sequencer
|
|
Used module: $paramod$7daeb8f261fda395eabf31b36fd9e0630350662f\spi_engine
|
|
Used module: \spi_slave
|
|
|
|
13.17. Analyzing design hierarchy..
|
|
Top module: \spi_neuron_top
|
|
Used module: $paramod$a7831d90e36f1741b8aab496b8012d26eb45bb8d\psram_controller
|
|
Used module: $paramod$606976195f63b53ce91799ce1552927edc9dfdd0\memory_interface
|
|
Used module: $paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010110
|
|
Used module: $paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010110
|
|
Used module: $paramod$625bd452a5b2f1609c59261f6b45d2c3299924cf\neuron_memory
|
|
Used module: $paramod$18f95495176adabb8b1efa1a4c23d17992af7212\neuron_parallel
|
|
Used module: $paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8
|
|
Used module: $paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\mac_unit
|
|
Used module: $paramod$6ef4b294e25a3b4c04a5a9c8b8177ec3433db948\layer_sequencer
|
|
Used module: $paramod$7daeb8f261fda395eabf31b36fd9e0630350662f\spi_engine
|
|
Used module: \spi_slave
|
|
Removing unused module `\mac8'.
|
|
Removing unused module `\mac_unit'.
|
|
Removing unused module `$paramod$913793164bb5cb5821e69ced9b7f953b27ebd911\mac_unit'.
|
|
Removing unused module `\neuron_parallel'.
|
|
Removing unused module `\psram_controller'.
|
|
Removing unused module `\memory_interface'.
|
|
Removing unused module `\int8_memory_access'.
|
|
Removing unused module `\neuron_memory'.
|
|
Removing unused module `\mem_arbiter'.
|
|
Removing unused module `\layer_sequencer'.
|
|
Removing unused module `\spi_engine'.
|
|
Removed 11 unused modules.
|
|
|
|
14. Executing PROC pass (convert processes to netlists).
|
|
|
|
14.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
|
|
Cleaned up 0 empty switches.
|
|
|
|
14.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
|
|
Marked 5 switch rules as full_case in process $proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:121$492 in module $paramod$6ef4b294e25a3b4c04a5a9c8b8177ec3433db948\layer_sequencer.
|
|
Marked 8 switch rules as full_case in process $proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:260$375 in module $paramod$625bd452a5b2f1609c59261f6b45d2c3299924cf\neuron_memory.
|
|
Removed 1 dead cases from process $proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mem_arbiter.v:90$369 in module $paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010110.
|
|
Marked 4 switch rules as full_case in process $proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mem_arbiter.v:90$369 in module $paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010110.
|
|
Marked 2 switch rules as full_case in process $proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/memory_interface.v:33$367 in module $paramod$606976195f63b53ce91799ce1552927edc9dfdd0\memory_interface.
|
|
Marked 6 switch rules as full_case in process $proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/psram_controller.v:99$360 in module $paramod$a7831d90e36f1741b8aab496b8012d26eb45bb8d\psram_controller.
|
|
Marked 12 switch rules as full_case in process $proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:269$524 in module $paramod$7daeb8f261fda395eabf31b36fd9e0630350662f\spi_engine.
|
|
Marked 4 switch rules as full_case in process $proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:220$519 in module $paramod$7daeb8f261fda395eabf31b36fd9e0630350662f\spi_engine.
|
|
Marked 3 switch rules as full_case in process $proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:199$517 in module $paramod$7daeb8f261fda395eabf31b36fd9e0630350662f\spi_engine.
|
|
Marked 4 switch rules as full_case in process $proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/int8_memory_access.v:55$267 in module $paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010110.
|
|
Marked 5 switch rules as full_case in process $proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95$260 in module $paramod$18f95495176adabb8b1efa1a4c23d17992af7212\neuron_parallel.
|
|
Marked 6 switch rules as full_case in process $proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_slave.v:119$12 in module spi_slave.
|
|
Marked 1 switch rules as full_case in process $proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_slave.v:93$2 in module spi_slave.
|
|
Marked 1 switch rules as full_case in process $proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_slave.v:71$1 in module spi_slave.
|
|
Removed a total of 1 dead cases.
|
|
|
|
14.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
|
|
Removed 36 redundant assignments.
|
|
Promoted 35 assignments to connections.
|
|
|
|
14.4. Executing PROC_INIT pass (extract init attributes).
|
|
|
|
14.5. Executing PROC_ARST pass (detect async resets in processes).
|
|
|
|
14.6. Executing PROC_ROM pass (convert switches to ROMs).
|
|
Converted 1 switch.
|
|
<suppressed ~95 debug messages>
|
|
|
|
14.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
|
|
Creating decoders for process `$paramod$6ef4b294e25a3b4c04a5a9c8b8177ec3433db948\layer_sequencer.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:121$492'.
|
|
1/24: $0\bias_addr_acc[23:0] [15:8]
|
|
2/24: $0\bias_addr_acc[23:0] [7:0]
|
|
3/24: $0\bias_addr_acc[23:0] [23:16]
|
|
4/24: $0\w_base_acc[23:0] [7:0]
|
|
5/24: $0\w_base_acc[23:0] [23:16]
|
|
6/24: $0\ram_req[0:0]
|
|
7/24: $0\nm_start[0:0]
|
|
8/24: $0\copy_idx[0:0]
|
|
9/24: $0\write_sel[0:0]
|
|
10/24: $0\cur_sel[0:0]
|
|
11/24: $0\w_base_acc[23:0] [15:8]
|
|
12/24: $0\seq_done[0:0]
|
|
13/24: $0\desc_byte_idx[2:0]
|
|
14/24: $0\desc_table_addr[21:0]
|
|
15/24: $0\num_layers_reg[7:0]
|
|
16/24: $0\layer_idx[7:0]
|
|
17/24: $0\nm_bias_addr[21:0]
|
|
18/24: $0\nm_w_base[21:0]
|
|
19/24: $0\nm_x_base[21:0]
|
|
20/24: $0\state[3:0]
|
|
21/24: $0\seq_busy[0:0]
|
|
22/24: $0\ram_wdata[7:0]
|
|
23/24: $0\ram_addr[21:0]
|
|
24/24: $0\ram_wr[0:0]
|
|
Creating decoders for process `$paramod$625bd452a5b2f1609c59261f6b45d2c3299924cf\neuron_memory.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:260$375'.
|
|
1/42: $3$memwr$\y_reg$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:426$373_EN[7:0]$421
|
|
2/42: $3$memwr$\y_reg$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:426$373_DATA[7:0]$420
|
|
3/42: $3$memwr$\y_reg$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:426$373_ADDR[0:0]$419
|
|
4/42: $3$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:367$372_EN[7:0]$414
|
|
5/42: $3$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:367$372_DATA[7:0]$413
|
|
6/42: $3$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:367$372_ADDR[5:0]$412
|
|
7/42: $3$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:334$371_EN[7:0]$407
|
|
8/42: $3$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:334$371_DATA[7:0]$406
|
|
9/42: $3$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:334$371_ADDR[5:0]$405
|
|
10/42: $2$memwr$\y_reg$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:426$373_EN[7:0]$404
|
|
11/42: $2$memwr$\y_reg$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:426$373_DATA[7:0]$403
|
|
12/42: $2$memwr$\y_reg$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:426$373_ADDR[0:0]$402
|
|
13/42: $2$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:367$372_EN[7:0]$401
|
|
14/42: $2$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:367$372_DATA[7:0]$400
|
|
15/42: $2$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:367$372_ADDR[5:0]$399
|
|
16/42: $2$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:334$371_EN[7:0]$398
|
|
17/42: $2$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:334$371_DATA[7:0]$397
|
|
18/42: $2$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:334$371_ADDR[5:0]$396
|
|
19/42: $0\done[0:0]
|
|
20/42: $1\rst_i[31:0]
|
|
21/42: $1$memwr$\y_reg$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:281$370_EN[7:0]$386
|
|
22/42: $0\neuron_start[0:0]
|
|
23/42: $0\access_req[0:0]
|
|
24/42: $1$memwr$\y_reg$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:426$373_EN[7:0]$395
|
|
25/42: $1$memwr$\y_reg$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:426$373_DATA[7:0]$394
|
|
26/42: $1$memwr$\y_reg$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:426$373_ADDR[0:0]$393
|
|
27/42: $1$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:367$372_EN[7:0]$392
|
|
28/42: $1$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:367$372_DATA[7:0]$391
|
|
29/42: $1$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:367$372_ADDR[5:0]$390
|
|
30/42: $1$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:334$371_EN[7:0]$389
|
|
31/42: $1$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:334$371_DATA[7:0]$388
|
|
32/42: $1$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:334$371_ADDR[5:0]$387
|
|
33/42: $0\access_wdata[7:0]
|
|
34/42: $0\access_addr[21:0]
|
|
35/42: $0\access_wr[0:0]
|
|
36/42: $0\bias_reg[7:0]
|
|
37/42: $0\bias_group_addr[21:0]
|
|
38/42: $0\w_group_base[21:0]
|
|
39/42: $0\neuron_index[0:0]
|
|
40/42: $0\index[5:0]
|
|
41/42: $0\busy[0:0]
|
|
42/42: $0\state[3:0]
|
|
Creating decoders for process `$paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010110.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mem_arbiter.v:90$369'.
|
|
1/11: $0\c_ready[0:0]
|
|
2/11: $0\b_ready[0:0]
|
|
3/11: $0\a_ready[0:0]
|
|
4/11: $0\m_req[0:0]
|
|
5/11: $0\owner[1:0]
|
|
6/11: $0\m_wdata[7:0]
|
|
7/11: $0\m_addr[21:0]
|
|
8/11: $0\m_wr[0:0]
|
|
9/11: $0\c_rdata[7:0]
|
|
10/11: $0\b_rdata[7:0]
|
|
11/11: $0\a_rdata[7:0]
|
|
Creating decoders for process `$paramod$606976195f63b53ce91799ce1552927edc9dfdd0\memory_interface.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/memory_interface.v:33$367'.
|
|
1/9: $0\mem_req[0:0]
|
|
2/9: $0\ready[0:0]
|
|
3/9: $0\mem_ub_n[0:0]
|
|
4/9: $0\mem_lb_n[0:0]
|
|
5/9: $0\rdata[15:0]
|
|
6/9: $0\mem_wdata[15:0]
|
|
7/9: $0\mem_addr[21:0]
|
|
8/9: $0\mem_wr[0:0]
|
|
9/9: $0\state[1:0]
|
|
Creating decoders for process `$paramod$a7831d90e36f1741b8aab496b8012d26eb45bb8d\psram_controller.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/psram_controller.v:99$360'.
|
|
1/18: $0\dq_oe[0:0]
|
|
2/18: $0\psram_zz_n[0:0]
|
|
3/18: $0\psram_ub_n[0:0]
|
|
4/18: $0\psram_lb_n[0:0]
|
|
5/18: $0\psram_we_n[0:0]
|
|
6/18: $0\psram_oe_n[0:0]
|
|
7/18: $0\psram_ce_n[0:0]
|
|
8/18: $0\mem_ready[0:0]
|
|
9/18: $0\dq_out[15:0]
|
|
10/18: $0\ub_reg[0:0]
|
|
11/18: $0\lb_reg[0:0]
|
|
12/18: $0\wr_reg[0:0]
|
|
13/18: $0\wdata_reg[15:0]
|
|
14/18: $0\address_reg[21:0]
|
|
15/18: $0\counter[13:0]
|
|
16/18: $0\psram_a[21:0]
|
|
17/18: $0\mem_rdata[15:0]
|
|
18/18: $0\state[2:0]
|
|
Creating decoders for process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:100$606'.
|
|
Creating decoders for process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:100$604'.
|
|
Creating decoders for process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:100$602'.
|
|
Creating decoders for process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:100$600'.
|
|
Creating decoders for process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:100$598'.
|
|
Creating decoders for process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:100$596'.
|
|
Creating decoders for process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:100$594'.
|
|
Creating decoders for process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:81$593'.
|
|
Creating decoders for process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:81$592'.
|
|
Creating decoders for process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:81$591'.
|
|
Creating decoders for process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:81$590'.
|
|
Creating decoders for process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:81$589'.
|
|
Creating decoders for process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:81$588'.
|
|
Creating decoders for process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:81$587'.
|
|
Creating decoders for process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:81$586'.
|
|
Creating decoders for process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:40$585'.
|
|
Creating decoders for process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:40$584'.
|
|
Creating decoders for process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:40$583'.
|
|
Creating decoders for process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:40$582'.
|
|
Creating decoders for process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:40$581'.
|
|
Creating decoders for process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:40$580'.
|
|
Creating decoders for process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:40$579'.
|
|
Creating decoders for process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:40$578'.
|
|
Creating decoders for process `$paramod$7daeb8f261fda395eabf31b36fd9e0630350662f\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:269$524'.
|
|
1/29: $0\len_acc[15:0] [15:8]
|
|
2/29: $0\len_acc[15:0] [7:0]
|
|
3/29: $0\nm_soft_rst[0:0]
|
|
4/29: $0\nm_start[0:0]
|
|
5/29: $0\ram_req[0:0]
|
|
6/29: $0\status_snapshot[7:0]
|
|
7/29: $0\net_mode[0:0]
|
|
8/29: $0\resp_len[3:0]
|
|
9/29: $0\resp_index[3:0]
|
|
10/29: $0\cur_read_byte[7:0]
|
|
11/29: $0\pending_wdata[7:0]
|
|
12/29: $0\pending_write[0:0]
|
|
13/29: $0\cur_addr[21:0]
|
|
14/29: $0\len_remaining[15:0]
|
|
15/29: $0\run_start[0:0]
|
|
16/29: $0\addr_acc[23:0]
|
|
17/29: $0\byte_pos[1:0]
|
|
18/29: $0\opcode[7:0]
|
|
19/29: $0\state[3:0]
|
|
20/29: $0\run_num_layers[7:0]
|
|
21/29: $0\buf_b_base[21:0]
|
|
22/29: $0\buf_a_base[21:0]
|
|
23/29: $0\table_base[21:0]
|
|
24/29: $0\bias_addr[21:0]
|
|
25/29: $0\w_base[21:0]
|
|
26/29: $0\x_base[21:0]
|
|
27/29: $0\ram_wdata[7:0]
|
|
28/29: $0\ram_addr[21:0]
|
|
29/29: $0\ram_wr[0:0]
|
|
Creating decoders for process `$paramod$7daeb8f261fda395eabf31b36fd9e0630350662f\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:220$519'.
|
|
1/4: $4\tx_byte_comb[7:0]
|
|
2/4: $3\tx_byte_comb[7:0]
|
|
3/4: $2\tx_byte_comb[7:0]
|
|
4/4: $1\tx_byte_comb[7:0]
|
|
Creating decoders for process `$paramod$7daeb8f261fda395eabf31b36fd9e0630350662f\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:199$517'.
|
|
1/1: $0\status_done_sticky[0:0]
|
|
Creating decoders for process `$paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010110.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/int8_memory_access.v:55$267'.
|
|
1/10: $0\mem_req[0:0]
|
|
2/10: $0\ready[0:0]
|
|
3/10: $0\addr_reg[21:0]
|
|
4/10: $0\mem_ub_n[0:0]
|
|
5/10: $0\mem_lb_n[0:0]
|
|
6/10: $0\rdata[7:0]
|
|
7/10: $0\mem_wdata[15:0]
|
|
8/10: $0\mem_addr[21:0]
|
|
9/10: $0\mem_wr[0:0]
|
|
10/10: $0\state[1:0]
|
|
Creating decoders for process `$paramod$18f95495176adabb8b1efa1a4c23d17992af7212\neuron_parallel.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95$260'.
|
|
1/5: $0\done[0:0]
|
|
2/5: $0\acc[31:0]
|
|
3/5: $0\group_index[1:0]
|
|
4/5: $0\busy[0:0]
|
|
5/5: $0\y[7:0]
|
|
Creating decoders for process `\spi_slave.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_slave.v:119$12'.
|
|
1/9: $0\cs_end[0:0]
|
|
2/9: $0\cs_start[0:0]
|
|
3/9: $0\tx_byte_req[0:0]
|
|
4/9: $0\rx_valid[0:0]
|
|
5/9: $0\tx_shift[7:0]
|
|
6/9: $0\rx_shift[7:0]
|
|
7/9: $0\bit_count[2:0]
|
|
8/9: $0\rx_byte[7:0]
|
|
9/9: $0\miso[0:0]
|
|
Creating decoders for process `\spi_slave.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_slave.v:93$2'.
|
|
1/2: $0\cs_n_prev[0:0]
|
|
2/2: $0\sclk_prev[0:0]
|
|
Creating decoders for process `\spi_slave.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_slave.v:71$1'.
|
|
1/3: $0\cs_n_sync[2:0]
|
|
2/3: $0\mosi_sync[2:0]
|
|
3/3: $0\sclk_sync[2:0]
|
|
|
|
14.8. Executing PROC_DLATCH pass (convert process syncs to latches).
|
|
No latch inferred for signal `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.\tree[24]' from process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:100$606'.
|
|
No latch inferred for signal `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.\tree[17]' from process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:100$604'.
|
|
No latch inferred for signal `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.\tree[16]' from process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:100$602'.
|
|
No latch inferred for signal `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.\tree[11]' from process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:100$600'.
|
|
No latch inferred for signal `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.\tree[10]' from process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:100$598'.
|
|
No latch inferred for signal `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.\tree[9]' from process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:100$596'.
|
|
No latch inferred for signal `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.\tree[8]' from process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:100$594'.
|
|
No latch inferred for signal `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.\tree[7]' from process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:81$593'.
|
|
No latch inferred for signal `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.\tree[6]' from process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:81$592'.
|
|
No latch inferred for signal `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.\tree[5]' from process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:81$591'.
|
|
No latch inferred for signal `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.\tree[4]' from process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:81$590'.
|
|
No latch inferred for signal `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.\tree[3]' from process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:81$589'.
|
|
No latch inferred for signal `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.\tree[2]' from process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:81$588'.
|
|
No latch inferred for signal `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.\tree[1]' from process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:81$587'.
|
|
No latch inferred for signal `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.\tree[0]' from process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:81$586'.
|
|
No latch inferred for signal `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.\products[7]' from process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:40$585'.
|
|
No latch inferred for signal `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.\products[6]' from process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:40$584'.
|
|
No latch inferred for signal `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.\products[5]' from process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:40$583'.
|
|
No latch inferred for signal `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.\products[4]' from process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:40$582'.
|
|
No latch inferred for signal `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.\products[3]' from process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:40$581'.
|
|
No latch inferred for signal `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.\products[2]' from process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:40$580'.
|
|
No latch inferred for signal `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.\products[1]' from process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:40$579'.
|
|
No latch inferred for signal `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.\products[0]' from process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:40$578'.
|
|
No latch inferred for signal `$paramod$7daeb8f261fda395eabf31b36fd9e0630350662f\spi_engine.\tx_byte_comb' from process `$paramod$7daeb8f261fda395eabf31b36fd9e0630350662f\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:220$519'.
|
|
|
|
14.9. Executing PROC_DFF pass (convert process syncs to FFs).
|
|
Creating register for signal `$paramod$6ef4b294e25a3b4c04a5a9c8b8177ec3433db948\layer_sequencer.\ram_req' using process `$paramod$6ef4b294e25a3b4c04a5a9c8b8177ec3433db948\layer_sequencer.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:121$492'.
|
|
created $dff cell `$procdff$2984' with positive edge clock.
|
|
Creating register for signal `$paramod$6ef4b294e25a3b4c04a5a9c8b8177ec3433db948\layer_sequencer.\ram_wr' using process `$paramod$6ef4b294e25a3b4c04a5a9c8b8177ec3433db948\layer_sequencer.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:121$492'.
|
|
created $dff cell `$procdff$2985' with positive edge clock.
|
|
Creating register for signal `$paramod$6ef4b294e25a3b4c04a5a9c8b8177ec3433db948\layer_sequencer.\ram_addr' using process `$paramod$6ef4b294e25a3b4c04a5a9c8b8177ec3433db948\layer_sequencer.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:121$492'.
|
|
created $dff cell `$procdff$2986' with positive edge clock.
|
|
Creating register for signal `$paramod$6ef4b294e25a3b4c04a5a9c8b8177ec3433db948\layer_sequencer.\ram_wdata' using process `$paramod$6ef4b294e25a3b4c04a5a9c8b8177ec3433db948\layer_sequencer.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:121$492'.
|
|
created $dff cell `$procdff$2987' with positive edge clock.
|
|
Creating register for signal `$paramod$6ef4b294e25a3b4c04a5a9c8b8177ec3433db948\layer_sequencer.\nm_start' using process `$paramod$6ef4b294e25a3b4c04a5a9c8b8177ec3433db948\layer_sequencer.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:121$492'.
|
|
created $dff cell `$procdff$2988' with positive edge clock.
|
|
Creating register for signal `$paramod$6ef4b294e25a3b4c04a5a9c8b8177ec3433db948\layer_sequencer.\seq_busy' using process `$paramod$6ef4b294e25a3b4c04a5a9c8b8177ec3433db948\layer_sequencer.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:121$492'.
|
|
created $dff cell `$procdff$2989' with positive edge clock.
|
|
Creating register for signal `$paramod$6ef4b294e25a3b4c04a5a9c8b8177ec3433db948\layer_sequencer.\seq_done' using process `$paramod$6ef4b294e25a3b4c04a5a9c8b8177ec3433db948\layer_sequencer.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:121$492'.
|
|
created $dff cell `$procdff$2990' with positive edge clock.
|
|
Creating register for signal `$paramod$6ef4b294e25a3b4c04a5a9c8b8177ec3433db948\layer_sequencer.\state' using process `$paramod$6ef4b294e25a3b4c04a5a9c8b8177ec3433db948\layer_sequencer.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:121$492'.
|
|
created $dff cell `$procdff$2991' with positive edge clock.
|
|
Creating register for signal `$paramod$6ef4b294e25a3b4c04a5a9c8b8177ec3433db948\layer_sequencer.\nm_x_base' using process `$paramod$6ef4b294e25a3b4c04a5a9c8b8177ec3433db948\layer_sequencer.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:121$492'.
|
|
created $dff cell `$procdff$2992' with positive edge clock.
|
|
Creating register for signal `$paramod$6ef4b294e25a3b4c04a5a9c8b8177ec3433db948\layer_sequencer.\nm_w_base' using process `$paramod$6ef4b294e25a3b4c04a5a9c8b8177ec3433db948\layer_sequencer.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:121$492'.
|
|
created $dff cell `$procdff$2993' with positive edge clock.
|
|
Creating register for signal `$paramod$6ef4b294e25a3b4c04a5a9c8b8177ec3433db948\layer_sequencer.\nm_bias_addr' using process `$paramod$6ef4b294e25a3b4c04a5a9c8b8177ec3433db948\layer_sequencer.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:121$492'.
|
|
created $dff cell `$procdff$2994' with positive edge clock.
|
|
Creating register for signal `$paramod$6ef4b294e25a3b4c04a5a9c8b8177ec3433db948\layer_sequencer.\layer_idx' using process `$paramod$6ef4b294e25a3b4c04a5a9c8b8177ec3433db948\layer_sequencer.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:121$492'.
|
|
created $dff cell `$procdff$2995' with positive edge clock.
|
|
Creating register for signal `$paramod$6ef4b294e25a3b4c04a5a9c8b8177ec3433db948\layer_sequencer.\num_layers_reg' using process `$paramod$6ef4b294e25a3b4c04a5a9c8b8177ec3433db948\layer_sequencer.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:121$492'.
|
|
created $dff cell `$procdff$2996' with positive edge clock.
|
|
Creating register for signal `$paramod$6ef4b294e25a3b4c04a5a9c8b8177ec3433db948\layer_sequencer.\desc_table_addr' using process `$paramod$6ef4b294e25a3b4c04a5a9c8b8177ec3433db948\layer_sequencer.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:121$492'.
|
|
created $dff cell `$procdff$2997' with positive edge clock.
|
|
Creating register for signal `$paramod$6ef4b294e25a3b4c04a5a9c8b8177ec3433db948\layer_sequencer.\desc_byte_idx' using process `$paramod$6ef4b294e25a3b4c04a5a9c8b8177ec3433db948\layer_sequencer.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:121$492'.
|
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created $dff cell `$procdff$2998' with positive edge clock.
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Creating register for signal `$paramod$6ef4b294e25a3b4c04a5a9c8b8177ec3433db948\layer_sequencer.\w_base_acc' using process `$paramod$6ef4b294e25a3b4c04a5a9c8b8177ec3433db948\layer_sequencer.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:121$492'.
|
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created $dff cell `$procdff$2999' with positive edge clock.
|
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Creating register for signal `$paramod$6ef4b294e25a3b4c04a5a9c8b8177ec3433db948\layer_sequencer.\bias_addr_acc' using process `$paramod$6ef4b294e25a3b4c04a5a9c8b8177ec3433db948\layer_sequencer.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:121$492'.
|
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created $dff cell `$procdff$3000' with positive edge clock.
|
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Creating register for signal `$paramod$6ef4b294e25a3b4c04a5a9c8b8177ec3433db948\layer_sequencer.\cur_sel' using process `$paramod$6ef4b294e25a3b4c04a5a9c8b8177ec3433db948\layer_sequencer.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:121$492'.
|
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created $dff cell `$procdff$3001' with positive edge clock.
|
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Creating register for signal `$paramod$6ef4b294e25a3b4c04a5a9c8b8177ec3433db948\layer_sequencer.\write_sel' using process `$paramod$6ef4b294e25a3b4c04a5a9c8b8177ec3433db948\layer_sequencer.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:121$492'.
|
|
created $dff cell `$procdff$3002' with positive edge clock.
|
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Creating register for signal `$paramod$6ef4b294e25a3b4c04a5a9c8b8177ec3433db948\layer_sequencer.\copy_idx' using process `$paramod$6ef4b294e25a3b4c04a5a9c8b8177ec3433db948\layer_sequencer.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:121$492'.
|
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created $dff cell `$procdff$3003' with positive edge clock.
|
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Creating register for signal `$paramod$625bd452a5b2f1609c59261f6b45d2c3299924cf\neuron_memory.\state' using process `$paramod$625bd452a5b2f1609c59261f6b45d2c3299924cf\neuron_memory.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:260$375'.
|
|
created $dff cell `$procdff$3004' with positive edge clock.
|
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Creating register for signal `$paramod$625bd452a5b2f1609c59261f6b45d2c3299924cf\neuron_memory.\busy' using process `$paramod$625bd452a5b2f1609c59261f6b45d2c3299924cf\neuron_memory.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:260$375'.
|
|
created $dff cell `$procdff$3005' with positive edge clock.
|
|
Creating register for signal `$paramod$625bd452a5b2f1609c59261f6b45d2c3299924cf\neuron_memory.\done' using process `$paramod$625bd452a5b2f1609c59261f6b45d2c3299924cf\neuron_memory.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:260$375'.
|
|
created $dff cell `$procdff$3006' with positive edge clock.
|
|
Creating register for signal `$paramod$625bd452a5b2f1609c59261f6b45d2c3299924cf\neuron_memory.\index' using process `$paramod$625bd452a5b2f1609c59261f6b45d2c3299924cf\neuron_memory.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:260$375'.
|
|
created $dff cell `$procdff$3007' with positive edge clock.
|
|
Creating register for signal `$paramod$625bd452a5b2f1609c59261f6b45d2c3299924cf\neuron_memory.\neuron_index' using process `$paramod$625bd452a5b2f1609c59261f6b45d2c3299924cf\neuron_memory.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:260$375'.
|
|
created $dff cell `$procdff$3008' with positive edge clock.
|
|
Creating register for signal `$paramod$625bd452a5b2f1609c59261f6b45d2c3299924cf\neuron_memory.\w_group_base' using process `$paramod$625bd452a5b2f1609c59261f6b45d2c3299924cf\neuron_memory.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:260$375'.
|
|
created $dff cell `$procdff$3009' with positive edge clock.
|
|
Creating register for signal `$paramod$625bd452a5b2f1609c59261f6b45d2c3299924cf\neuron_memory.\bias_group_addr' using process `$paramod$625bd452a5b2f1609c59261f6b45d2c3299924cf\neuron_memory.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:260$375'.
|
|
created $dff cell `$procdff$3010' with positive edge clock.
|
|
Creating register for signal `$paramod$625bd452a5b2f1609c59261f6b45d2c3299924cf\neuron_memory.\bias_reg' using process `$paramod$625bd452a5b2f1609c59261f6b45d2c3299924cf\neuron_memory.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:260$375'.
|
|
created $dff cell `$procdff$3011' with positive edge clock.
|
|
Creating register for signal `$paramod$625bd452a5b2f1609c59261f6b45d2c3299924cf\neuron_memory.\access_req' using process `$paramod$625bd452a5b2f1609c59261f6b45d2c3299924cf\neuron_memory.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:260$375'.
|
|
created $dff cell `$procdff$3012' with positive edge clock.
|
|
Creating register for signal `$paramod$625bd452a5b2f1609c59261f6b45d2c3299924cf\neuron_memory.\access_wr' using process `$paramod$625bd452a5b2f1609c59261f6b45d2c3299924cf\neuron_memory.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:260$375'.
|
|
created $dff cell `$procdff$3013' with positive edge clock.
|
|
Creating register for signal `$paramod$625bd452a5b2f1609c59261f6b45d2c3299924cf\neuron_memory.\access_addr' using process `$paramod$625bd452a5b2f1609c59261f6b45d2c3299924cf\neuron_memory.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:260$375'.
|
|
created $dff cell `$procdff$3014' with positive edge clock.
|
|
Creating register for signal `$paramod$625bd452a5b2f1609c59261f6b45d2c3299924cf\neuron_memory.\access_wdata' using process `$paramod$625bd452a5b2f1609c59261f6b45d2c3299924cf\neuron_memory.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:260$375'.
|
|
created $dff cell `$procdff$3015' with positive edge clock.
|
|
Creating register for signal `$paramod$625bd452a5b2f1609c59261f6b45d2c3299924cf\neuron_memory.\neuron_start' using process `$paramod$625bd452a5b2f1609c59261f6b45d2c3299924cf\neuron_memory.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:260$375'.
|
|
created $dff cell `$procdff$3016' with positive edge clock.
|
|
Creating register for signal `$paramod$625bd452a5b2f1609c59261f6b45d2c3299924cf\neuron_memory.\rst_i' using process `$paramod$625bd452a5b2f1609c59261f6b45d2c3299924cf\neuron_memory.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:260$375'.
|
|
created $dff cell `$procdff$3017' with positive edge clock.
|
|
Creating register for signal `$paramod$625bd452a5b2f1609c59261f6b45d2c3299924cf\neuron_memory.$memwr$\y_reg$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:281$370_EN' using process `$paramod$625bd452a5b2f1609c59261f6b45d2c3299924cf\neuron_memory.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:260$375'.
|
|
created $dff cell `$procdff$3018' with positive edge clock.
|
|
Creating register for signal `$paramod$625bd452a5b2f1609c59261f6b45d2c3299924cf\neuron_memory.$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:334$371_ADDR' using process `$paramod$625bd452a5b2f1609c59261f6b45d2c3299924cf\neuron_memory.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:260$375'.
|
|
created $dff cell `$procdff$3019' with positive edge clock.
|
|
Creating register for signal `$paramod$625bd452a5b2f1609c59261f6b45d2c3299924cf\neuron_memory.$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:334$371_DATA' using process `$paramod$625bd452a5b2f1609c59261f6b45d2c3299924cf\neuron_memory.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:260$375'.
|
|
created $dff cell `$procdff$3020' with positive edge clock.
|
|
Creating register for signal `$paramod$625bd452a5b2f1609c59261f6b45d2c3299924cf\neuron_memory.$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:334$371_EN' using process `$paramod$625bd452a5b2f1609c59261f6b45d2c3299924cf\neuron_memory.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:260$375'.
|
|
created $dff cell `$procdff$3021' with positive edge clock.
|
|
Creating register for signal `$paramod$625bd452a5b2f1609c59261f6b45d2c3299924cf\neuron_memory.$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:367$372_ADDR' using process `$paramod$625bd452a5b2f1609c59261f6b45d2c3299924cf\neuron_memory.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:260$375'.
|
|
created $dff cell `$procdff$3022' with positive edge clock.
|
|
Creating register for signal `$paramod$625bd452a5b2f1609c59261f6b45d2c3299924cf\neuron_memory.$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:367$372_DATA' using process `$paramod$625bd452a5b2f1609c59261f6b45d2c3299924cf\neuron_memory.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:260$375'.
|
|
created $dff cell `$procdff$3023' with positive edge clock.
|
|
Creating register for signal `$paramod$625bd452a5b2f1609c59261f6b45d2c3299924cf\neuron_memory.$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:367$372_EN' using process `$paramod$625bd452a5b2f1609c59261f6b45d2c3299924cf\neuron_memory.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:260$375'.
|
|
created $dff cell `$procdff$3024' with positive edge clock.
|
|
Creating register for signal `$paramod$625bd452a5b2f1609c59261f6b45d2c3299924cf\neuron_memory.$memwr$\y_reg$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:426$373_ADDR' using process `$paramod$625bd452a5b2f1609c59261f6b45d2c3299924cf\neuron_memory.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:260$375'.
|
|
created $dff cell `$procdff$3025' with positive edge clock.
|
|
Creating register for signal `$paramod$625bd452a5b2f1609c59261f6b45d2c3299924cf\neuron_memory.$memwr$\y_reg$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:426$373_DATA' using process `$paramod$625bd452a5b2f1609c59261f6b45d2c3299924cf\neuron_memory.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:260$375'.
|
|
created $dff cell `$procdff$3026' with positive edge clock.
|
|
Creating register for signal `$paramod$625bd452a5b2f1609c59261f6b45d2c3299924cf\neuron_memory.$memwr$\y_reg$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:426$373_EN' using process `$paramod$625bd452a5b2f1609c59261f6b45d2c3299924cf\neuron_memory.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:260$375'.
|
|
created $dff cell `$procdff$3027' with positive edge clock.
|
|
Creating register for signal `$paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010110.\a_rdata' using process `$paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010110.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mem_arbiter.v:90$369'.
|
|
created $dff cell `$procdff$3028' with positive edge clock.
|
|
Creating register for signal `$paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010110.\a_ready' using process `$paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010110.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mem_arbiter.v:90$369'.
|
|
created $dff cell `$procdff$3029' with positive edge clock.
|
|
Creating register for signal `$paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010110.\b_rdata' using process `$paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010110.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mem_arbiter.v:90$369'.
|
|
created $dff cell `$procdff$3030' with positive edge clock.
|
|
Creating register for signal `$paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010110.\b_ready' using process `$paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010110.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mem_arbiter.v:90$369'.
|
|
created $dff cell `$procdff$3031' with positive edge clock.
|
|
Creating register for signal `$paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010110.\c_rdata' using process `$paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010110.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mem_arbiter.v:90$369'.
|
|
created $dff cell `$procdff$3032' with positive edge clock.
|
|
Creating register for signal `$paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010110.\c_ready' using process `$paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010110.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mem_arbiter.v:90$369'.
|
|
created $dff cell `$procdff$3033' with positive edge clock.
|
|
Creating register for signal `$paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010110.\m_req' using process `$paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010110.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mem_arbiter.v:90$369'.
|
|
created $dff cell `$procdff$3034' with positive edge clock.
|
|
Creating register for signal `$paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010110.\m_wr' using process `$paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010110.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mem_arbiter.v:90$369'.
|
|
created $dff cell `$procdff$3035' with positive edge clock.
|
|
Creating register for signal `$paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010110.\m_addr' using process `$paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010110.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mem_arbiter.v:90$369'.
|
|
created $dff cell `$procdff$3036' with positive edge clock.
|
|
Creating register for signal `$paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010110.\m_wdata' using process `$paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010110.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mem_arbiter.v:90$369'.
|
|
created $dff cell `$procdff$3037' with positive edge clock.
|
|
Creating register for signal `$paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010110.\owner' using process `$paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010110.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mem_arbiter.v:90$369'.
|
|
created $dff cell `$procdff$3038' with positive edge clock.
|
|
Creating register for signal `$paramod$606976195f63b53ce91799ce1552927edc9dfdd0\memory_interface.\state' using process `$paramod$606976195f63b53ce91799ce1552927edc9dfdd0\memory_interface.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/memory_interface.v:33$367'.
|
|
created $dff cell `$procdff$3039' with positive edge clock.
|
|
Creating register for signal `$paramod$606976195f63b53ce91799ce1552927edc9dfdd0\memory_interface.\mem_req' using process `$paramod$606976195f63b53ce91799ce1552927edc9dfdd0\memory_interface.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/memory_interface.v:33$367'.
|
|
created $dff cell `$procdff$3040' with positive edge clock.
|
|
Creating register for signal `$paramod$606976195f63b53ce91799ce1552927edc9dfdd0\memory_interface.\mem_wr' using process `$paramod$606976195f63b53ce91799ce1552927edc9dfdd0\memory_interface.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/memory_interface.v:33$367'.
|
|
created $dff cell `$procdff$3041' with positive edge clock.
|
|
Creating register for signal `$paramod$606976195f63b53ce91799ce1552927edc9dfdd0\memory_interface.\mem_addr' using process `$paramod$606976195f63b53ce91799ce1552927edc9dfdd0\memory_interface.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/memory_interface.v:33$367'.
|
|
created $dff cell `$procdff$3042' with positive edge clock.
|
|
Creating register for signal `$paramod$606976195f63b53ce91799ce1552927edc9dfdd0\memory_interface.\mem_wdata' using process `$paramod$606976195f63b53ce91799ce1552927edc9dfdd0\memory_interface.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/memory_interface.v:33$367'.
|
|
created $dff cell `$procdff$3043' with positive edge clock.
|
|
Creating register for signal `$paramod$606976195f63b53ce91799ce1552927edc9dfdd0\memory_interface.\rdata' using process `$paramod$606976195f63b53ce91799ce1552927edc9dfdd0\memory_interface.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/memory_interface.v:33$367'.
|
|
created $dff cell `$procdff$3044' with positive edge clock.
|
|
Creating register for signal `$paramod$606976195f63b53ce91799ce1552927edc9dfdd0\memory_interface.\ready' using process `$paramod$606976195f63b53ce91799ce1552927edc9dfdd0\memory_interface.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/memory_interface.v:33$367'.
|
|
created $dff cell `$procdff$3045' with positive edge clock.
|
|
Creating register for signal `$paramod$606976195f63b53ce91799ce1552927edc9dfdd0\memory_interface.\mem_lb_n' using process `$paramod$606976195f63b53ce91799ce1552927edc9dfdd0\memory_interface.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/memory_interface.v:33$367'.
|
|
created $dff cell `$procdff$3046' with positive edge clock.
|
|
Creating register for signal `$paramod$606976195f63b53ce91799ce1552927edc9dfdd0\memory_interface.\mem_ub_n' using process `$paramod$606976195f63b53ce91799ce1552927edc9dfdd0\memory_interface.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/memory_interface.v:33$367'.
|
|
created $dff cell `$procdff$3047' with positive edge clock.
|
|
Creating register for signal `$paramod$a7831d90e36f1741b8aab496b8012d26eb45bb8d\psram_controller.\state' using process `$paramod$a7831d90e36f1741b8aab496b8012d26eb45bb8d\psram_controller.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/psram_controller.v:99$360'.
|
|
created $dff cell `$procdff$3048' with positive edge clock.
|
|
Creating register for signal `$paramod$a7831d90e36f1741b8aab496b8012d26eb45bb8d\psram_controller.\mem_rdata' using process `$paramod$a7831d90e36f1741b8aab496b8012d26eb45bb8d\psram_controller.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/psram_controller.v:99$360'.
|
|
created $dff cell `$procdff$3049' with positive edge clock.
|
|
Creating register for signal `$paramod$a7831d90e36f1741b8aab496b8012d26eb45bb8d\psram_controller.\mem_ready' using process `$paramod$a7831d90e36f1741b8aab496b8012d26eb45bb8d\psram_controller.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/psram_controller.v:99$360'.
|
|
created $dff cell `$procdff$3050' with positive edge clock.
|
|
Creating register for signal `$paramod$a7831d90e36f1741b8aab496b8012d26eb45bb8d\psram_controller.\psram_a' using process `$paramod$a7831d90e36f1741b8aab496b8012d26eb45bb8d\psram_controller.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/psram_controller.v:99$360'.
|
|
created $dff cell `$procdff$3051' with positive edge clock.
|
|
Creating register for signal `$paramod$a7831d90e36f1741b8aab496b8012d26eb45bb8d\psram_controller.\psram_ce_n' using process `$paramod$a7831d90e36f1741b8aab496b8012d26eb45bb8d\psram_controller.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/psram_controller.v:99$360'.
|
|
created $dff cell `$procdff$3052' with positive edge clock.
|
|
Creating register for signal `$paramod$a7831d90e36f1741b8aab496b8012d26eb45bb8d\psram_controller.\psram_oe_n' using process `$paramod$a7831d90e36f1741b8aab496b8012d26eb45bb8d\psram_controller.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/psram_controller.v:99$360'.
|
|
created $dff cell `$procdff$3053' with positive edge clock.
|
|
Creating register for signal `$paramod$a7831d90e36f1741b8aab496b8012d26eb45bb8d\psram_controller.\psram_we_n' using process `$paramod$a7831d90e36f1741b8aab496b8012d26eb45bb8d\psram_controller.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/psram_controller.v:99$360'.
|
|
created $dff cell `$procdff$3054' with positive edge clock.
|
|
Creating register for signal `$paramod$a7831d90e36f1741b8aab496b8012d26eb45bb8d\psram_controller.\psram_lb_n' using process `$paramod$a7831d90e36f1741b8aab496b8012d26eb45bb8d\psram_controller.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/psram_controller.v:99$360'.
|
|
created $dff cell `$procdff$3055' with positive edge clock.
|
|
Creating register for signal `$paramod$a7831d90e36f1741b8aab496b8012d26eb45bb8d\psram_controller.\psram_ub_n' using process `$paramod$a7831d90e36f1741b8aab496b8012d26eb45bb8d\psram_controller.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/psram_controller.v:99$360'.
|
|
created $dff cell `$procdff$3056' with positive edge clock.
|
|
Creating register for signal `$paramod$a7831d90e36f1741b8aab496b8012d26eb45bb8d\psram_controller.\psram_zz_n' using process `$paramod$a7831d90e36f1741b8aab496b8012d26eb45bb8d\psram_controller.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/psram_controller.v:99$360'.
|
|
created $dff cell `$procdff$3057' with positive edge clock.
|
|
Creating register for signal `$paramod$a7831d90e36f1741b8aab496b8012d26eb45bb8d\psram_controller.\counter' using process `$paramod$a7831d90e36f1741b8aab496b8012d26eb45bb8d\psram_controller.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/psram_controller.v:99$360'.
|
|
created $dff cell `$procdff$3058' with positive edge clock.
|
|
Creating register for signal `$paramod$a7831d90e36f1741b8aab496b8012d26eb45bb8d\psram_controller.\address_reg' using process `$paramod$a7831d90e36f1741b8aab496b8012d26eb45bb8d\psram_controller.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/psram_controller.v:99$360'.
|
|
created $dff cell `$procdff$3059' with positive edge clock.
|
|
Creating register for signal `$paramod$a7831d90e36f1741b8aab496b8012d26eb45bb8d\psram_controller.\wdata_reg' using process `$paramod$a7831d90e36f1741b8aab496b8012d26eb45bb8d\psram_controller.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/psram_controller.v:99$360'.
|
|
created $dff cell `$procdff$3060' with positive edge clock.
|
|
Creating register for signal `$paramod$a7831d90e36f1741b8aab496b8012d26eb45bb8d\psram_controller.\wr_reg' using process `$paramod$a7831d90e36f1741b8aab496b8012d26eb45bb8d\psram_controller.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/psram_controller.v:99$360'.
|
|
created $dff cell `$procdff$3061' with positive edge clock.
|
|
Creating register for signal `$paramod$a7831d90e36f1741b8aab496b8012d26eb45bb8d\psram_controller.\lb_reg' using process `$paramod$a7831d90e36f1741b8aab496b8012d26eb45bb8d\psram_controller.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/psram_controller.v:99$360'.
|
|
created $dff cell `$procdff$3062' with positive edge clock.
|
|
Creating register for signal `$paramod$a7831d90e36f1741b8aab496b8012d26eb45bb8d\psram_controller.\ub_reg' using process `$paramod$a7831d90e36f1741b8aab496b8012d26eb45bb8d\psram_controller.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/psram_controller.v:99$360'.
|
|
created $dff cell `$procdff$3063' with positive edge clock.
|
|
Creating register for signal `$paramod$a7831d90e36f1741b8aab496b8012d26eb45bb8d\psram_controller.\dq_out' using process `$paramod$a7831d90e36f1741b8aab496b8012d26eb45bb8d\psram_controller.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/psram_controller.v:99$360'.
|
|
created $dff cell `$procdff$3064' with positive edge clock.
|
|
Creating register for signal `$paramod$a7831d90e36f1741b8aab496b8012d26eb45bb8d\psram_controller.\dq_oe' using process `$paramod$a7831d90e36f1741b8aab496b8012d26eb45bb8d\psram_controller.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/psram_controller.v:99$360'.
|
|
created $dff cell `$procdff$3065' with positive edge clock.
|
|
Creating register for signal `$paramod$7daeb8f261fda395eabf31b36fd9e0630350662f\spi_engine.\ram_req' using process `$paramod$7daeb8f261fda395eabf31b36fd9e0630350662f\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:269$524'.
|
|
created $dff cell `$procdff$3066' with positive edge clock.
|
|
Creating register for signal `$paramod$7daeb8f261fda395eabf31b36fd9e0630350662f\spi_engine.\ram_wr' using process `$paramod$7daeb8f261fda395eabf31b36fd9e0630350662f\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:269$524'.
|
|
created $dff cell `$procdff$3067' with positive edge clock.
|
|
Creating register for signal `$paramod$7daeb8f261fda395eabf31b36fd9e0630350662f\spi_engine.\ram_addr' using process `$paramod$7daeb8f261fda395eabf31b36fd9e0630350662f\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:269$524'.
|
|
created $dff cell `$procdff$3068' with positive edge clock.
|
|
Creating register for signal `$paramod$7daeb8f261fda395eabf31b36fd9e0630350662f\spi_engine.\ram_wdata' using process `$paramod$7daeb8f261fda395eabf31b36fd9e0630350662f\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:269$524'.
|
|
created $dff cell `$procdff$3069' with positive edge clock.
|
|
Creating register for signal `$paramod$7daeb8f261fda395eabf31b36fd9e0630350662f\spi_engine.\x_base' using process `$paramod$7daeb8f261fda395eabf31b36fd9e0630350662f\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:269$524'.
|
|
created $dff cell `$procdff$3070' with positive edge clock.
|
|
Creating register for signal `$paramod$7daeb8f261fda395eabf31b36fd9e0630350662f\spi_engine.\w_base' using process `$paramod$7daeb8f261fda395eabf31b36fd9e0630350662f\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:269$524'.
|
|
created $dff cell `$procdff$3071' with positive edge clock.
|
|
Creating register for signal `$paramod$7daeb8f261fda395eabf31b36fd9e0630350662f\spi_engine.\bias_addr' using process `$paramod$7daeb8f261fda395eabf31b36fd9e0630350662f\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:269$524'.
|
|
created $dff cell `$procdff$3072' with positive edge clock.
|
|
Creating register for signal `$paramod$7daeb8f261fda395eabf31b36fd9e0630350662f\spi_engine.\nm_start' using process `$paramod$7daeb8f261fda395eabf31b36fd9e0630350662f\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:269$524'.
|
|
created $dff cell `$procdff$3073' with positive edge clock.
|
|
Creating register for signal `$paramod$7daeb8f261fda395eabf31b36fd9e0630350662f\spi_engine.\nm_soft_rst' using process `$paramod$7daeb8f261fda395eabf31b36fd9e0630350662f\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:269$524'.
|
|
created $dff cell `$procdff$3074' with positive edge clock.
|
|
Creating register for signal `$paramod$7daeb8f261fda395eabf31b36fd9e0630350662f\spi_engine.\table_base' using process `$paramod$7daeb8f261fda395eabf31b36fd9e0630350662f\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:269$524'.
|
|
created $dff cell `$procdff$3075' with positive edge clock.
|
|
Creating register for signal `$paramod$7daeb8f261fda395eabf31b36fd9e0630350662f\spi_engine.\buf_a_base' using process `$paramod$7daeb8f261fda395eabf31b36fd9e0630350662f\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:269$524'.
|
|
created $dff cell `$procdff$3076' with positive edge clock.
|
|
Creating register for signal `$paramod$7daeb8f261fda395eabf31b36fd9e0630350662f\spi_engine.\buf_b_base' using process `$paramod$7daeb8f261fda395eabf31b36fd9e0630350662f\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:269$524'.
|
|
created $dff cell `$procdff$3077' with positive edge clock.
|
|
Creating register for signal `$paramod$7daeb8f261fda395eabf31b36fd9e0630350662f\spi_engine.\run_start' using process `$paramod$7daeb8f261fda395eabf31b36fd9e0630350662f\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:269$524'.
|
|
created $dff cell `$procdff$3078' with positive edge clock.
|
|
Creating register for signal `$paramod$7daeb8f261fda395eabf31b36fd9e0630350662f\spi_engine.\run_num_layers' using process `$paramod$7daeb8f261fda395eabf31b36fd9e0630350662f\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:269$524'.
|
|
created $dff cell `$procdff$3079' with positive edge clock.
|
|
Creating register for signal `$paramod$7daeb8f261fda395eabf31b36fd9e0630350662f\spi_engine.\state' using process `$paramod$7daeb8f261fda395eabf31b36fd9e0630350662f\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:269$524'.
|
|
created $dff cell `$procdff$3080' with positive edge clock.
|
|
Creating register for signal `$paramod$7daeb8f261fda395eabf31b36fd9e0630350662f\spi_engine.\opcode' using process `$paramod$7daeb8f261fda395eabf31b36fd9e0630350662f\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:269$524'.
|
|
created $dff cell `$procdff$3081' with positive edge clock.
|
|
Creating register for signal `$paramod$7daeb8f261fda395eabf31b36fd9e0630350662f\spi_engine.\byte_pos' using process `$paramod$7daeb8f261fda395eabf31b36fd9e0630350662f\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:269$524'.
|
|
created $dff cell `$procdff$3082' with positive edge clock.
|
|
Creating register for signal `$paramod$7daeb8f261fda395eabf31b36fd9e0630350662f\spi_engine.\addr_acc' using process `$paramod$7daeb8f261fda395eabf31b36fd9e0630350662f\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:269$524'.
|
|
created $dff cell `$procdff$3083' with positive edge clock.
|
|
Creating register for signal `$paramod$7daeb8f261fda395eabf31b36fd9e0630350662f\spi_engine.\len_acc' using process `$paramod$7daeb8f261fda395eabf31b36fd9e0630350662f\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:269$524'.
|
|
created $dff cell `$procdff$3084' with positive edge clock.
|
|
Creating register for signal `$paramod$7daeb8f261fda395eabf31b36fd9e0630350662f\spi_engine.\len_remaining' using process `$paramod$7daeb8f261fda395eabf31b36fd9e0630350662f\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:269$524'.
|
|
created $dff cell `$procdff$3085' with positive edge clock.
|
|
Creating register for signal `$paramod$7daeb8f261fda395eabf31b36fd9e0630350662f\spi_engine.\cur_addr' using process `$paramod$7daeb8f261fda395eabf31b36fd9e0630350662f\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:269$524'.
|
|
created $dff cell `$procdff$3086' with positive edge clock.
|
|
Creating register for signal `$paramod$7daeb8f261fda395eabf31b36fd9e0630350662f\spi_engine.\pending_write' using process `$paramod$7daeb8f261fda395eabf31b36fd9e0630350662f\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:269$524'.
|
|
created $dff cell `$procdff$3087' with positive edge clock.
|
|
Creating register for signal `$paramod$7daeb8f261fda395eabf31b36fd9e0630350662f\spi_engine.\pending_wdata' using process `$paramod$7daeb8f261fda395eabf31b36fd9e0630350662f\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:269$524'.
|
|
created $dff cell `$procdff$3088' with positive edge clock.
|
|
Creating register for signal `$paramod$7daeb8f261fda395eabf31b36fd9e0630350662f\spi_engine.\cur_read_byte' using process `$paramod$7daeb8f261fda395eabf31b36fd9e0630350662f\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:269$524'.
|
|
created $dff cell `$procdff$3089' with positive edge clock.
|
|
Creating register for signal `$paramod$7daeb8f261fda395eabf31b36fd9e0630350662f\spi_engine.\resp_index' using process `$paramod$7daeb8f261fda395eabf31b36fd9e0630350662f\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:269$524'.
|
|
created $dff cell `$procdff$3090' with positive edge clock.
|
|
Creating register for signal `$paramod$7daeb8f261fda395eabf31b36fd9e0630350662f\spi_engine.\resp_len' using process `$paramod$7daeb8f261fda395eabf31b36fd9e0630350662f\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:269$524'.
|
|
created $dff cell `$procdff$3091' with positive edge clock.
|
|
Creating register for signal `$paramod$7daeb8f261fda395eabf31b36fd9e0630350662f\spi_engine.\net_mode' using process `$paramod$7daeb8f261fda395eabf31b36fd9e0630350662f\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:269$524'.
|
|
created $dff cell `$procdff$3092' with positive edge clock.
|
|
Creating register for signal `$paramod$7daeb8f261fda395eabf31b36fd9e0630350662f\spi_engine.\status_snapshot' using process `$paramod$7daeb8f261fda395eabf31b36fd9e0630350662f\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:269$524'.
|
|
created $dff cell `$procdff$3093' with positive edge clock.
|
|
Creating register for signal `$paramod$7daeb8f261fda395eabf31b36fd9e0630350662f\spi_engine.\status_done_sticky' using process `$paramod$7daeb8f261fda395eabf31b36fd9e0630350662f\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:199$517'.
|
|
created $dff cell `$procdff$3094' with positive edge clock.
|
|
Creating register for signal `$paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010110.\state' using process `$paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010110.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/int8_memory_access.v:55$267'.
|
|
created $dff cell `$procdff$3095' with positive edge clock.
|
|
Creating register for signal `$paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010110.\mem_req' using process `$paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010110.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/int8_memory_access.v:55$267'.
|
|
created $dff cell `$procdff$3096' with positive edge clock.
|
|
Creating register for signal `$paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010110.\mem_wr' using process `$paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010110.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/int8_memory_access.v:55$267'.
|
|
created $dff cell `$procdff$3097' with positive edge clock.
|
|
Creating register for signal `$paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010110.\mem_addr' using process `$paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010110.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/int8_memory_access.v:55$267'.
|
|
created $dff cell `$procdff$3098' with positive edge clock.
|
|
Creating register for signal `$paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010110.\mem_wdata' using process `$paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010110.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/int8_memory_access.v:55$267'.
|
|
created $dff cell `$procdff$3099' with positive edge clock.
|
|
Creating register for signal `$paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010110.\rdata' using process `$paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010110.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/int8_memory_access.v:55$267'.
|
|
created $dff cell `$procdff$3100' with positive edge clock.
|
|
Creating register for signal `$paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010110.\ready' using process `$paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010110.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/int8_memory_access.v:55$267'.
|
|
created $dff cell `$procdff$3101' with positive edge clock.
|
|
Creating register for signal `$paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010110.\mem_lb_n' using process `$paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010110.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/int8_memory_access.v:55$267'.
|
|
created $dff cell `$procdff$3102' with positive edge clock.
|
|
Creating register for signal `$paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010110.\mem_ub_n' using process `$paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010110.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/int8_memory_access.v:55$267'.
|
|
created $dff cell `$procdff$3103' with positive edge clock.
|
|
Creating register for signal `$paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010110.\addr_reg' using process `$paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010110.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/int8_memory_access.v:55$267'.
|
|
created $dff cell `$procdff$3104' with positive edge clock.
|
|
Creating register for signal `$paramod$18f95495176adabb8b1efa1a4c23d17992af7212\neuron_parallel.\y' using process `$paramod$18f95495176adabb8b1efa1a4c23d17992af7212\neuron_parallel.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95$260'.
|
|
created $dff cell `$procdff$3105' with positive edge clock.
|
|
Creating register for signal `$paramod$18f95495176adabb8b1efa1a4c23d17992af7212\neuron_parallel.\busy' using process `$paramod$18f95495176adabb8b1efa1a4c23d17992af7212\neuron_parallel.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95$260'.
|
|
created $dff cell `$procdff$3106' with positive edge clock.
|
|
Creating register for signal `$paramod$18f95495176adabb8b1efa1a4c23d17992af7212\neuron_parallel.\done' using process `$paramod$18f95495176adabb8b1efa1a4c23d17992af7212\neuron_parallel.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95$260'.
|
|
created $dff cell `$procdff$3107' with positive edge clock.
|
|
Creating register for signal `$paramod$18f95495176adabb8b1efa1a4c23d17992af7212\neuron_parallel.\group_index' using process `$paramod$18f95495176adabb8b1efa1a4c23d17992af7212\neuron_parallel.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95$260'.
|
|
created $dff cell `$procdff$3108' with positive edge clock.
|
|
Creating register for signal `$paramod$18f95495176adabb8b1efa1a4c23d17992af7212\neuron_parallel.\acc' using process `$paramod$18f95495176adabb8b1efa1a4c23d17992af7212\neuron_parallel.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95$260'.
|
|
created $dff cell `$procdff$3109' with positive edge clock.
|
|
Creating register for signal `\spi_slave.\miso' using process `\spi_slave.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_slave.v:119$12'.
|
|
created $dff cell `$procdff$3110' with positive edge clock.
|
|
Creating register for signal `\spi_slave.\rx_byte' using process `\spi_slave.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_slave.v:119$12'.
|
|
created $dff cell `$procdff$3111' with positive edge clock.
|
|
Creating register for signal `\spi_slave.\rx_valid' using process `\spi_slave.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_slave.v:119$12'.
|
|
created $dff cell `$procdff$3112' with positive edge clock.
|
|
Creating register for signal `\spi_slave.\tx_byte_req' using process `\spi_slave.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_slave.v:119$12'.
|
|
created $dff cell `$procdff$3113' with positive edge clock.
|
|
Creating register for signal `\spi_slave.\cs_start' using process `\spi_slave.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_slave.v:119$12'.
|
|
created $dff cell `$procdff$3114' with positive edge clock.
|
|
Creating register for signal `\spi_slave.\cs_end' using process `\spi_slave.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_slave.v:119$12'.
|
|
created $dff cell `$procdff$3115' with positive edge clock.
|
|
Creating register for signal `\spi_slave.\bit_count' using process `\spi_slave.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_slave.v:119$12'.
|
|
created $dff cell `$procdff$3116' with positive edge clock.
|
|
Creating register for signal `\spi_slave.\rx_shift' using process `\spi_slave.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_slave.v:119$12'.
|
|
created $dff cell `$procdff$3117' with positive edge clock.
|
|
Creating register for signal `\spi_slave.\tx_shift' using process `\spi_slave.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_slave.v:119$12'.
|
|
created $dff cell `$procdff$3118' with positive edge clock.
|
|
Creating register for signal `\spi_slave.\sclk_prev' using process `\spi_slave.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_slave.v:93$2'.
|
|
created $dff cell `$procdff$3119' with positive edge clock.
|
|
Creating register for signal `\spi_slave.\cs_n_prev' using process `\spi_slave.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_slave.v:93$2'.
|
|
created $dff cell `$procdff$3120' with positive edge clock.
|
|
Creating register for signal `\spi_slave.\sclk_sync' using process `\spi_slave.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_slave.v:71$1'.
|
|
created $dff cell `$procdff$3121' with positive edge clock.
|
|
Creating register for signal `\spi_slave.\mosi_sync' using process `\spi_slave.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_slave.v:71$1'.
|
|
created $dff cell `$procdff$3122' with positive edge clock.
|
|
Creating register for signal `\spi_slave.\cs_n_sync' using process `\spi_slave.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_slave.v:71$1'.
|
|
created $dff cell `$procdff$3123' with positive edge clock.
|
|
|
|
14.10. Executing PROC_MEMWR pass (convert process memory writes to cells).
|
|
|
|
14.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
|
|
Found and cleaned up 10 empty switches in `$paramod$6ef4b294e25a3b4c04a5a9c8b8177ec3433db948\layer_sequencer.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:121$492'.
|
|
Removing empty process `$paramod$6ef4b294e25a3b4c04a5a9c8b8177ec3433db948\layer_sequencer.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:121$492'.
|
|
Found and cleaned up 10 empty switches in `$paramod$625bd452a5b2f1609c59261f6b45d2c3299924cf\neuron_memory.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:260$375'.
|
|
Removing empty process `$paramod$625bd452a5b2f1609c59261f6b45d2c3299924cf\neuron_memory.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:260$375'.
|
|
Found and cleaned up 8 empty switches in `$paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010110.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mem_arbiter.v:90$369'.
|
|
Removing empty process `$paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010110.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mem_arbiter.v:90$369'.
|
|
Found and cleaned up 5 empty switches in `$paramod$606976195f63b53ce91799ce1552927edc9dfdd0\memory_interface.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/memory_interface.v:33$367'.
|
|
Removing empty process `$paramod$606976195f63b53ce91799ce1552927edc9dfdd0\memory_interface.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/memory_interface.v:33$367'.
|
|
Found and cleaned up 7 empty switches in `$paramod$a7831d90e36f1741b8aab496b8012d26eb45bb8d\psram_controller.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/psram_controller.v:99$360'.
|
|
Removing empty process `$paramod$a7831d90e36f1741b8aab496b8012d26eb45bb8d\psram_controller.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/psram_controller.v:99$360'.
|
|
Removing empty process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:100$606'.
|
|
Removing empty process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:100$604'.
|
|
Removing empty process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:100$602'.
|
|
Removing empty process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:100$600'.
|
|
Removing empty process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:100$598'.
|
|
Removing empty process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:100$596'.
|
|
Removing empty process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:100$594'.
|
|
Removing empty process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:81$593'.
|
|
Removing empty process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:81$592'.
|
|
Removing empty process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:81$591'.
|
|
Removing empty process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:81$590'.
|
|
Removing empty process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:81$589'.
|
|
Removing empty process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:81$588'.
|
|
Removing empty process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:81$587'.
|
|
Removing empty process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:81$586'.
|
|
Removing empty process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:40$585'.
|
|
Removing empty process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:40$584'.
|
|
Removing empty process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:40$583'.
|
|
Removing empty process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:40$582'.
|
|
Removing empty process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:40$581'.
|
|
Removing empty process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:40$580'.
|
|
Removing empty process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:40$579'.
|
|
Removing empty process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:40$578'.
|
|
Found and cleaned up 26 empty switches in `$paramod$7daeb8f261fda395eabf31b36fd9e0630350662f\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:269$524'.
|
|
Removing empty process `$paramod$7daeb8f261fda395eabf31b36fd9e0630350662f\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:269$524'.
|
|
Found and cleaned up 4 empty switches in `$paramod$7daeb8f261fda395eabf31b36fd9e0630350662f\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:220$519'.
|
|
Removing empty process `$paramod$7daeb8f261fda395eabf31b36fd9e0630350662f\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:220$519'.
|
|
Found and cleaned up 4 empty switches in `$paramod$7daeb8f261fda395eabf31b36fd9e0630350662f\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:199$517'.
|
|
Removing empty process `$paramod$7daeb8f261fda395eabf31b36fd9e0630350662f\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:199$517'.
|
|
Found and cleaned up 6 empty switches in `$paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010110.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/int8_memory_access.v:55$267'.
|
|
Removing empty process `$paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010110.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/int8_memory_access.v:55$267'.
|
|
Found and cleaned up 6 empty switches in `$paramod$18f95495176adabb8b1efa1a4c23d17992af7212\neuron_parallel.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95$260'.
|
|
Removing empty process `$paramod$18f95495176adabb8b1efa1a4c23d17992af7212\neuron_parallel.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:95$260'.
|
|
Found and cleaned up 8 empty switches in `\spi_slave.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_slave.v:119$12'.
|
|
Removing empty process `spi_slave.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_slave.v:119$12'.
|
|
Found and cleaned up 1 empty switch in `\spi_slave.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_slave.v:93$2'.
|
|
Removing empty process `spi_slave.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_slave.v:93$2'.
|
|
Found and cleaned up 1 empty switch in `\spi_slave.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_slave.v:71$1'.
|
|
Removing empty process `spi_slave.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_slave.v:71$1'.
|
|
Cleaned up 96 empty switches.
|
|
|
|
14.12. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module spi_neuron_top.
|
|
Optimizing module $paramod$6ef4b294e25a3b4c04a5a9c8b8177ec3433db948\layer_sequencer.
|
|
<suppressed ~19 debug messages>
|
|
Optimizing module $paramod$625bd452a5b2f1609c59261f6b45d2c3299924cf\neuron_memory.
|
|
<suppressed ~20 debug messages>
|
|
Optimizing module $paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010110.
|
|
<suppressed ~5 debug messages>
|
|
Optimizing module $paramod$606976195f63b53ce91799ce1552927edc9dfdd0\memory_interface.
|
|
<suppressed ~8 debug messages>
|
|
Optimizing module $paramod$a7831d90e36f1741b8aab496b8012d26eb45bb8d\psram_controller.
|
|
<suppressed ~4 debug messages>
|
|
Optimizing module $paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.
|
|
Optimizing module $paramod$7daeb8f261fda395eabf31b36fd9e0630350662f\spi_engine.
|
|
<suppressed ~18 debug messages>
|
|
Optimizing module $paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\mac_unit.
|
|
Optimizing module $paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010110.
|
|
<suppressed ~15 debug messages>
|
|
Optimizing module $paramod$18f95495176adabb8b1efa1a4c23d17992af7212\neuron_parallel.
|
|
Optimizing module spi_slave.
|
|
<suppressed ~8 debug messages>
|
|
|
|
15. Executing FLATTEN pass (flatten design).
|
|
Deleting now unused module $paramod$6ef4b294e25a3b4c04a5a9c8b8177ec3433db948\layer_sequencer.
|
|
Deleting now unused module $paramod$625bd452a5b2f1609c59261f6b45d2c3299924cf\neuron_memory.
|
|
Deleting now unused module $paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010110.
|
|
Deleting now unused module $paramod$606976195f63b53ce91799ce1552927edc9dfdd0\memory_interface.
|
|
Deleting now unused module $paramod$a7831d90e36f1741b8aab496b8012d26eb45bb8d\psram_controller.
|
|
Deleting now unused module $paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.
|
|
Deleting now unused module $paramod$7daeb8f261fda395eabf31b36fd9e0630350662f\spi_engine.
|
|
Deleting now unused module $paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\mac_unit.
|
|
Deleting now unused module $paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010110.
|
|
Deleting now unused module $paramod$18f95495176adabb8b1efa1a4c23d17992af7212\neuron_parallel.
|
|
Deleting now unused module spi_slave.
|
|
<suppressed ~19 debug messages>
|
|
|
|
16. Executing OPT pass (performing simple optimizations).
|
|
|
|
16.1. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module spi_neuron_top.
|
|
<suppressed ~24 debug messages>
|
|
|
|
16.2. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\spi_neuron_top'.
|
|
Computing hashes of 1361 cells of `\spi_neuron_top'.
|
|
Finding duplicate cells in `\spi_neuron_top'.
|
|
Computing hashes of 1125 cells of `\spi_neuron_top'.
|
|
Finding duplicate cells in `\spi_neuron_top'.
|
|
Computing hashes of 1124 cells of `\spi_neuron_top'.
|
|
Finding duplicate cells in `\spi_neuron_top'.
|
|
<suppressed ~711 debug messages>
|
|
Removed a total of 237 cells.
|
|
|
|
16.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \spi_neuron_top..
|
|
Creating internal representation of mux trees.
|
|
Evaluating internal representation of mux trees.
|
|
Replacing known input bits on port A of cell $flatten\u_neuron_memory.$procmux$1314: \u_neuron_memory.neuron_index -> 1'0
|
|
Replacing known input bits on port A of cell $flatten\u_neuron_memory.\u_neuron.$procmux$2807: \u_neuron_memory.u_neuron.busy -> 1'0
|
|
Replacing known input bits on port A of cell $flatten\u_neuron_memory.\u_neuron.$procmux$2805: \u_neuron_memory.u_neuron.busy -> 1'1
|
|
Replacing known input bits on port A of cell $flatten\u_layer_sequencer.$procmux$712: \u_layer_sequencer.copy_idx -> 1'0
|
|
Analyzing evaluation results.
|
|
dead port 2/2 on $mux $flatten\u_neuron_memory.$procmux$958.
|
|
dead port 1/2 on $mux $flatten\u_neuron_memory.$procmux$961.
|
|
dead port 2/2 on $mux $flatten\u_neuron_memory.$procmux$967.
|
|
dead port 1/2 on $mux $flatten\u_neuron_memory.$procmux$970.
|
|
dead port 2/2 on $mux $flatten\u_neuron_memory.$procmux$976.
|
|
dead port 1/2 on $mux $flatten\u_neuron_memory.$procmux$979.
|
|
dead port 2/2 on $mux $flatten\u_neuron_memory.$procmux$988.
|
|
dead port 1/2 on $mux $flatten\u_neuron_memory.$procmux$991.
|
|
dead port 2/2 on $mux $flatten\u_neuron_memory.$procmux$1000.
|
|
dead port 1/2 on $mux $flatten\u_neuron_memory.$procmux$1003.
|
|
dead port 2/2 on $mux $flatten\u_neuron_memory.$procmux$1012.
|
|
dead port 1/2 on $mux $flatten\u_neuron_memory.$procmux$1015.
|
|
dead port 2/2 on $mux $flatten\u_neuron_memory.$procmux$1025.
|
|
dead port 1/2 on $mux $flatten\u_neuron_memory.$procmux$1028.
|
|
dead port 2/2 on $mux $flatten\u_neuron_memory.$procmux$1038.
|
|
dead port 1/2 on $mux $flatten\u_neuron_memory.$procmux$1041.
|
|
dead port 2/2 on $mux $flatten\u_neuron_memory.$procmux$1051.
|
|
dead port 1/2 on $mux $flatten\u_neuron_memory.$procmux$1054.
|
|
dead port 1/2 on $mux $flatten\u_neuron_memory.$procmux$1060.
|
|
dead port 1/2 on $mux $flatten\u_neuron_memory.$procmux$1066.
|
|
dead port 1/2 on $mux $flatten\u_neuron_memory.$procmux$1072.
|
|
dead port 1/2 on $mux $flatten\u_neuron_memory.$procmux$1081.
|
|
dead port 1/2 on $mux $flatten\u_neuron_memory.$procmux$1090.
|
|
dead port 1/2 on $mux $flatten\u_neuron_memory.$procmux$1099.
|
|
dead port 1/2 on $mux $flatten\u_neuron_memory.$procmux$1109.
|
|
dead port 1/2 on $mux $flatten\u_neuron_memory.$procmux$1119.
|
|
dead port 1/2 on $mux $flatten\u_neuron_memory.$procmux$1129.
|
|
dead port 2/2 on $mux $flatten\u_spi_engine.$procmux$2632.
|
|
dead port 2/2 on $mux $flatten\u_spi_engine.$procmux$2634.
|
|
dead port 2/2 on $mux $flatten\u_spi_engine.$procmux$2642.
|
|
dead port 2/2 on $mux $flatten\u_spi_engine.$procmux$2644.
|
|
dead port 2/2 on $mux $flatten\u_spi_engine.$procmux$2652.
|
|
Removed 32 multiplexer ports.
|
|
<suppressed ~926 debug messages>
|
|
|
|
16.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \spi_neuron_top.
|
|
New ctrl vector for $pmux cell $flatten\u_psram_ctrl.$procmux$1757: { $auto$opt_reduce.cc:137:opt_pmux$3148 $flatten\u_psram_ctrl.$procmux$1633_CMP }
|
|
Consolidated identical input bits for $mux cell $flatten\u_neuron_memory.$procmux$956:
|
|
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_neuron_memory.$procmux$956_Y
|
|
New ports: A=1'0, B=1'1, Y=$flatten\u_neuron_memory.$procmux$956_Y [0]
|
|
New connections: $flatten\u_neuron_memory.$procmux$956_Y [7:1] = { $flatten\u_neuron_memory.$procmux$956_Y [0] $flatten\u_neuron_memory.$procmux$956_Y [0] $flatten\u_neuron_memory.$procmux$956_Y [0] $flatten\u_neuron_memory.$procmux$956_Y [0] $flatten\u_neuron_memory.$procmux$956_Y [0] $flatten\u_neuron_memory.$procmux$956_Y [0] $flatten\u_neuron_memory.$procmux$956_Y [0] }
|
|
Consolidated identical input bits for $mux cell $flatten\u_neuron_memory.$procmux$986:
|
|
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_neuron_memory.$procmux$986_Y
|
|
New ports: A=1'0, B=1'1, Y=$flatten\u_neuron_memory.$procmux$986_Y [0]
|
|
New connections: $flatten\u_neuron_memory.$procmux$986_Y [7:1] = { $flatten\u_neuron_memory.$procmux$986_Y [0] $flatten\u_neuron_memory.$procmux$986_Y [0] $flatten\u_neuron_memory.$procmux$986_Y [0] $flatten\u_neuron_memory.$procmux$986_Y [0] $flatten\u_neuron_memory.$procmux$986_Y [0] $flatten\u_neuron_memory.$procmux$986_Y [0] $flatten\u_neuron_memory.$procmux$986_Y [0] }
|
|
Consolidated identical input bits for $mux cell $flatten\u_neuron_memory.$procmux$1023:
|
|
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_neuron_memory.$procmux$1023_Y
|
|
New ports: A=1'0, B=1'1, Y=$flatten\u_neuron_memory.$procmux$1023_Y [0]
|
|
New connections: $flatten\u_neuron_memory.$procmux$1023_Y [7:1] = { $flatten\u_neuron_memory.$procmux$1023_Y [0] $flatten\u_neuron_memory.$procmux$1023_Y [0] $flatten\u_neuron_memory.$procmux$1023_Y [0] $flatten\u_neuron_memory.$procmux$1023_Y [0] $flatten\u_neuron_memory.$procmux$1023_Y [0] $flatten\u_neuron_memory.$procmux$1023_Y [0] $flatten\u_neuron_memory.$procmux$1023_Y [0] }
|
|
Consolidated identical input bits for $mux cell $flatten\u_neuron_memory.$procmux$1147:
|
|
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_neuron_memory.$procmux$1147_Y
|
|
New ports: A=1'0, B=1'1, Y=$flatten\u_neuron_memory.$procmux$1147_Y [0]
|
|
New connections: $flatten\u_neuron_memory.$procmux$1147_Y [7:1] = { $flatten\u_neuron_memory.$procmux$1147_Y [0] $flatten\u_neuron_memory.$procmux$1147_Y [0] $flatten\u_neuron_memory.$procmux$1147_Y [0] $flatten\u_neuron_memory.$procmux$1147_Y [0] $flatten\u_neuron_memory.$procmux$1147_Y [0] $flatten\u_neuron_memory.$procmux$1147_Y [0] $flatten\u_neuron_memory.$procmux$1147_Y [0] }
|
|
New ctrl vector for $pmux cell $flatten\u_neuron_memory.$procmux$1362: { $flatten\u_neuron_memory.$procmux$959_CMP $auto$opt_reduce.cc:137:opt_pmux$3150 $flatten\u_neuron_memory.$procmux$1179_CMP }
|
|
New ctrl vector for $pmux cell $flatten\u_layer_sequencer.$procmux$695: $auto$opt_reduce.cc:137:opt_pmux$3152
|
|
New ctrl vector for $pmux cell $flatten\u_spi_engine.$procmux$1997: $auto$opt_reduce.cc:137:opt_pmux$3154
|
|
New ctrl vector for $pmux cell $flatten\u_spi_engine.$procmux$2074: { $flatten\u_spi_engine.$procmux$2075_CMP $auto$opt_reduce.cc:137:opt_pmux$3156 }
|
|
New ctrl vector for $pmux cell $flatten\u_spi_engine.$procmux$2098: $auto$opt_reduce.cc:137:opt_pmux$3158
|
|
New ctrl vector for $pmux cell $flatten\u_spi_engine.$procmux$2361: { $auto$opt_reduce.cc:137:opt_pmux$3160 $flatten\u_spi_engine.$procmux$2365_CMP $flatten\u_spi_engine.$procmux$2366_CMP $flatten\u_spi_engine.$procmux$2239_CTRL }
|
|
New ctrl vector for $pmux cell $flatten\u_psram_ctrl.$procmux$1745: { $auto$opt_reduce.cc:137:opt_pmux$3162 $flatten\u_psram_ctrl.$procmux$1633_CMP }
|
|
New ctrl vector for $pmux cell $flatten\u_spi_engine.$procmux$2603: $auto$opt_reduce.cc:137:opt_pmux$3164
|
|
Optimizing cells in module \spi_neuron_top.
|
|
Consolidated identical input bits for $mux cell $flatten\u_neuron_memory.$procmux$1057:
|
|
Old ports: A=8'00000000, B=$flatten\u_neuron_memory.$3$memwr$\y_reg$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:426$373_EN[7:0]$421, Y=$flatten\u_neuron_memory.$procmux$1057_Y
|
|
New ports: A=1'0, B=$flatten\u_neuron_memory.$procmux$956_Y [0], Y=$flatten\u_neuron_memory.$procmux$1057_Y [0]
|
|
New connections: $flatten\u_neuron_memory.$procmux$1057_Y [7:1] = { $flatten\u_neuron_memory.$procmux$1057_Y [0] $flatten\u_neuron_memory.$procmux$1057_Y [0] $flatten\u_neuron_memory.$procmux$1057_Y [0] $flatten\u_neuron_memory.$procmux$1057_Y [0] $flatten\u_neuron_memory.$procmux$1057_Y [0] $flatten\u_neuron_memory.$procmux$1057_Y [0] $flatten\u_neuron_memory.$procmux$1057_Y [0] }
|
|
Consolidated identical input bits for $mux cell $flatten\u_neuron_memory.$procmux$1078:
|
|
Old ports: A=8'00000000, B=$flatten\u_neuron_memory.$3$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:367$372_EN[7:0]$414, Y=$flatten\u_neuron_memory.$procmux$1078_Y
|
|
New ports: A=1'0, B=$flatten\u_neuron_memory.$procmux$986_Y [0], Y=$flatten\u_neuron_memory.$procmux$1078_Y [0]
|
|
New connections: $flatten\u_neuron_memory.$procmux$1078_Y [7:1] = { $flatten\u_neuron_memory.$procmux$1078_Y [0] $flatten\u_neuron_memory.$procmux$1078_Y [0] $flatten\u_neuron_memory.$procmux$1078_Y [0] $flatten\u_neuron_memory.$procmux$1078_Y [0] $flatten\u_neuron_memory.$procmux$1078_Y [0] $flatten\u_neuron_memory.$procmux$1078_Y [0] $flatten\u_neuron_memory.$procmux$1078_Y [0] }
|
|
Consolidated identical input bits for $mux cell $flatten\u_neuron_memory.$procmux$1106:
|
|
Old ports: A=8'00000000, B=$flatten\u_neuron_memory.$3$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:334$371_EN[7:0]$407, Y=$flatten\u_neuron_memory.$procmux$1106_Y
|
|
New ports: A=1'0, B=$flatten\u_neuron_memory.$procmux$1023_Y [0], Y=$flatten\u_neuron_memory.$procmux$1106_Y [0]
|
|
New connections: $flatten\u_neuron_memory.$procmux$1106_Y [7:1] = { $flatten\u_neuron_memory.$procmux$1106_Y [0] $flatten\u_neuron_memory.$procmux$1106_Y [0] $flatten\u_neuron_memory.$procmux$1106_Y [0] $flatten\u_neuron_memory.$procmux$1106_Y [0] $flatten\u_neuron_memory.$procmux$1106_Y [0] $flatten\u_neuron_memory.$procmux$1106_Y [0] $flatten\u_neuron_memory.$procmux$1106_Y [0] }
|
|
Optimizing cells in module \spi_neuron_top.
|
|
Consolidated identical input bits for $mux cell $flatten\u_neuron_memory.$procmux$1184:
|
|
Old ports: A=$flatten\u_neuron_memory.$2$memwr$\y_reg$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:426$373_EN[7:0]$404, B=8'00000000, Y=$flatten\u_neuron_memory.$procmux$1184_Y
|
|
New ports: A=$flatten\u_neuron_memory.$procmux$1057_Y [0], B=1'0, Y=$flatten\u_neuron_memory.$procmux$1184_Y [0]
|
|
New connections: $flatten\u_neuron_memory.$procmux$1184_Y [7:1] = { $flatten\u_neuron_memory.$procmux$1184_Y [0] $flatten\u_neuron_memory.$procmux$1184_Y [0] $flatten\u_neuron_memory.$procmux$1184_Y [0] $flatten\u_neuron_memory.$procmux$1184_Y [0] $flatten\u_neuron_memory.$procmux$1184_Y [0] $flatten\u_neuron_memory.$procmux$1184_Y [0] $flatten\u_neuron_memory.$procmux$1184_Y [0] }
|
|
Consolidated identical input bits for $mux cell $flatten\u_neuron_memory.$procmux$1193:
|
|
Old ports: A=$flatten\u_neuron_memory.$2$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:367$372_EN[7:0]$401, B=8'00000000, Y=$flatten\u_neuron_memory.$procmux$1193_Y
|
|
New ports: A=$flatten\u_neuron_memory.$procmux$1078_Y [0], B=1'0, Y=$flatten\u_neuron_memory.$procmux$1193_Y [0]
|
|
New connections: $flatten\u_neuron_memory.$procmux$1193_Y [7:1] = { $flatten\u_neuron_memory.$procmux$1193_Y [0] $flatten\u_neuron_memory.$procmux$1193_Y [0] $flatten\u_neuron_memory.$procmux$1193_Y [0] $flatten\u_neuron_memory.$procmux$1193_Y [0] $flatten\u_neuron_memory.$procmux$1193_Y [0] $flatten\u_neuron_memory.$procmux$1193_Y [0] $flatten\u_neuron_memory.$procmux$1193_Y [0] }
|
|
Consolidated identical input bits for $mux cell $flatten\u_neuron_memory.$procmux$1202:
|
|
Old ports: A=$flatten\u_neuron_memory.$2$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:334$371_EN[7:0]$398, B=8'00000000, Y=$flatten\u_neuron_memory.$procmux$1202_Y
|
|
New ports: A=$flatten\u_neuron_memory.$procmux$1106_Y [0], B=1'0, Y=$flatten\u_neuron_memory.$procmux$1202_Y [0]
|
|
New connections: $flatten\u_neuron_memory.$procmux$1202_Y [7:1] = { $flatten\u_neuron_memory.$procmux$1202_Y [0] $flatten\u_neuron_memory.$procmux$1202_Y [0] $flatten\u_neuron_memory.$procmux$1202_Y [0] $flatten\u_neuron_memory.$procmux$1202_Y [0] $flatten\u_neuron_memory.$procmux$1202_Y [0] $flatten\u_neuron_memory.$procmux$1202_Y [0] $flatten\u_neuron_memory.$procmux$1202_Y [0] }
|
|
Optimizing cells in module \spi_neuron_top.
|
|
Performed a total of 19 changes.
|
|
|
|
16.5. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\spi_neuron_top'.
|
|
Computing hashes of 1101 cells of `\spi_neuron_top'.
|
|
Finding duplicate cells in `\spi_neuron_top'.
|
|
Computing hashes of 1080 cells of `\spi_neuron_top'.
|
|
Finding duplicate cells in `\spi_neuron_top'.
|
|
Computing hashes of 1079 cells of `\spi_neuron_top'.
|
|
Finding duplicate cells in `\spi_neuron_top'.
|
|
<suppressed ~66 debug messages>
|
|
Removed a total of 22 cells.
|
|
|
|
16.6. Executing OPT_DFF pass (perform DFF optimizations).
|
|
Adding SRST signal on $flatten\u_int8_access.$procdff$3104 ($dff) from module spi_neuron_top (D = $flatten\u_int8_access.$procmux$2690_Y, Q = \u_int8_access.addr_reg, rval = 22'0000000000000000000000).
|
|
Adding EN signal on $auto$ff.cc:337:slice$3165 ($sdff) from module spi_neuron_top (D = \u_int8_access.addr, Q = \u_int8_access.addr_reg).
|
|
Adding SRST signal on $flatten\u_spi_slave.$procdff$3123 ($dff) from module spi_neuron_top (D = { \u_spi_slave.cs_n_sync [1:0] \u_spi_slave.cs_n }, Q = \u_spi_slave.cs_n_sync, rval = 3'111).
|
|
Adding SRST signal on $flatten\u_spi_slave.$procdff$3122 ($dff) from module spi_neuron_top (D = { \u_spi_slave.mosi_sync [1:0] \u_spi_slave.mosi }, Q = \u_spi_slave.mosi_sync, rval = 3'000).
|
|
Adding SRST signal on $flatten\u_spi_slave.$procdff$3121 ($dff) from module spi_neuron_top (D = { \u_spi_slave.sclk_sync [1:0] \u_spi_slave.sclk }, Q = \u_spi_slave.sclk_sync, rval = 3'000).
|
|
Adding SRST signal on $flatten\u_spi_slave.$procdff$3120 ($dff) from module spi_neuron_top (D = \u_spi_slave.cs_n_sync [2], Q = \u_spi_slave.cs_n_prev, rval = 1'1).
|
|
Adding SRST signal on $flatten\u_spi_slave.$procdff$3119 ($dff) from module spi_neuron_top (D = \u_spi_slave.sclk_sync [2], Q = \u_spi_slave.sclk_prev, rval = 1'0).
|
|
Adding SRST signal on $flatten\u_spi_slave.$procdff$3118 ($dff) from module spi_neuron_top (D = $flatten\u_spi_slave.$procmux$2897_Y, Q = \u_spi_slave.tx_shift, rval = 8'00000000).
|
|
Adding EN signal on $auto$ff.cc:337:slice$3174 ($sdff) from module spi_neuron_top (D = $flatten\u_spi_slave.$procmux$2897_Y, Q = \u_spi_slave.tx_shift).
|
|
Adding SRST signal on $flatten\u_spi_slave.$procdff$3117 ($dff) from module spi_neuron_top (D = $flatten\u_spi_slave.$procmux$2911_Y, Q = \u_spi_slave.rx_shift, rval = 8'00000000).
|
|
Adding EN signal on $auto$ff.cc:337:slice$3186 ($sdff) from module spi_neuron_top (D = { \u_spi_slave.rx_shift [6:0] \u_spi_slave.mosi_sync [2] }, Q = \u_spi_slave.rx_shift).
|
|
Adding SRST signal on $flatten\u_spi_slave.$procdff$3116 ($dff) from module spi_neuron_top (D = $flatten\u_spi_slave.$procmux$2925_Y, Q = \u_spi_slave.bit_count, rval = 3'000).
|
|
Adding EN signal on $auto$ff.cc:337:slice$3196 ($sdff) from module spi_neuron_top (D = $flatten\u_spi_slave.$procmux$2918_Y, Q = \u_spi_slave.bit_count).
|
|
Adding SRST signal on $flatten\u_spi_slave.$procdff$3115 ($dff) from module spi_neuron_top (D = $flatten\u_spi_slave.$procmux$2833_Y, Q = \u_spi_slave.cs_end, rval = 1'0).
|
|
Adding SRST signal on $flatten\u_spi_slave.$procdff$3114 ($dff) from module spi_neuron_top (D = $flatten\u_spi_slave.$procmux$2842_Y, Q = \u_spi_slave.cs_start, rval = 1'0).
|
|
Adding SRST signal on $flatten\u_spi_slave.$procdff$3113 ($dff) from module spi_neuron_top (D = $flatten\u_spi_slave.$procmux$2861_Y, Q = \u_spi_slave.tx_byte_req, rval = 1'0).
|
|
Adding SRST signal on $flatten\u_spi_slave.$procdff$3112 ($dff) from module spi_neuron_top (D = $flatten\u_spi_slave.$procmux$2868_Y, Q = \u_spi_slave.rx_valid, rval = 1'0).
|
|
Adding SRST signal on $flatten\u_spi_slave.$procdff$3111 ($dff) from module spi_neuron_top (D = $flatten\u_spi_slave.$procmux$2945_Y, Q = \u_spi_slave.rx_byte, rval = 8'00000000).
|
|
Adding EN signal on $auto$ff.cc:337:slice$3216 ($sdff) from module spi_neuron_top (D = { \u_spi_slave.rx_shift [6:0] \u_spi_slave.mosi_sync [2] }, Q = \u_spi_slave.rx_byte).
|
|
Adding SRST signal on $flatten\u_spi_slave.$procdff$3110 ($dff) from module spi_neuron_top (D = $flatten\u_spi_slave.$procmux$2964_Y, Q = \u_spi_slave.miso, rval = 1'0).
|
|
Adding EN signal on $auto$ff.cc:337:slice$3226 ($sdff) from module spi_neuron_top (D = $flatten\u_spi_slave.$procmux$2964_Y, Q = \u_spi_slave.miso).
|
|
Adding SRST signal on $flatten\u_int8_access.$procdff$3101 ($dff) from module spi_neuron_top (D = $flatten\u_int8_access.$procmux$2679_Y, Q = \u_int8_access.ready, rval = 1'0).
|
|
Adding SRST signal on $flatten\u_spi_engine.$procdff$3094 ($dff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$2661_Y, Q = \u_spi_engine.status_done_sticky, rval = 1'0).
|
|
Adding EN signal on $auto$ff.cc:337:slice$3243 ($sdff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$2661_Y, Q = \u_spi_engine.status_done_sticky).
|
|
Adding SRST signal on $flatten\u_spi_engine.$procdff$3093 ($dff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$2029_Y, Q = \u_spi_engine.status_snapshot, rval = 8'00000000).
|
|
Adding EN signal on $auto$ff.cc:337:slice$3249 ($sdff) from module spi_neuron_top (D = { 6'000000 \u_spi_engine.status_done_sticky $flatten\u_spi_engine.$or$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:177$511_Y }, Q = \u_spi_engine.status_snapshot).
|
|
Adding SRST signal on $flatten\u_spi_engine.$procdff$3092 ($dff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$2055_Y, Q = \u_spi_engine.net_mode, rval = 1'0).
|
|
Adding SRST signal on $flatten\u_spi_engine.$procdff$3091 ($dff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$2083_Y, Q = \u_spi_engine.resp_len, rval = 4'0000).
|
|
Adding EN signal on $auto$ff.cc:337:slice$3256 ($sdff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$2074_Y, Q = \u_spi_engine.resp_len).
|
|
Adding SRST signal on $flatten\u_spi_engine.$procdff$3090 ($dff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$2106_Y, Q = \u_spi_engine.resp_index, rval = 4'0000).
|
|
Adding EN signal on $auto$ff.cc:337:slice$3264 ($sdff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$2095_Y, Q = \u_spi_engine.resp_index).
|
|
Adding SRST signal on $flatten\u_spi_engine.$procdff$3089 ($dff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$2121_Y, Q = \u_spi_engine.cur_read_byte, rval = 8'00000000).
|
|
Adding EN signal on $auto$ff.cc:337:slice$3280 ($sdff) from module spi_neuron_top (D = \u_spi_engine.ram_rdata, Q = \u_spi_engine.cur_read_byte).
|
|
Adding SRST signal on $flatten\u_spi_engine.$procdff$3088 ($dff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$2140_Y, Q = \u_spi_engine.pending_wdata, rval = 8'00000000).
|
|
Adding EN signal on $auto$ff.cc:337:slice$3286 ($sdff) from module spi_neuron_top (D = \u_spi_engine.rx_byte, Q = \u_spi_engine.pending_wdata).
|
|
Adding EN signal on $flatten\u_spi_engine.$procdff$3087 ($dff) from module spi_neuron_top (D = 1'0, Q = \u_spi_engine.pending_write).
|
|
Adding SRST signal on $flatten\u_spi_engine.$procdff$3086 ($dff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$2169_Y, Q = \u_spi_engine.cur_addr, rval = 22'0000000000000000000000).
|
|
Adding EN signal on $auto$ff.cc:337:slice$3293 ($sdff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$2154_Y, Q = \u_spi_engine.cur_addr).
|
|
Adding SRST signal on $flatten\u_spi_engine.$procdff$3085 ($dff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$2192_Y, Q = \u_spi_engine.len_remaining, rval = 16'0000000000000000).
|
|
Adding EN signal on $auto$ff.cc:337:slice$3311 ($sdff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$2180_Y, Q = \u_spi_engine.len_remaining).
|
|
Adding SRST signal on $flatten\u_spi_engine.$procdff$3084 ($dff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$1924_Y, Q = \u_spi_engine.len_acc [7:0], rval = 8'00000000).
|
|
Adding SRST signal on $flatten\u_spi_engine.$procdff$3084 ($dff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$1892_Y, Q = \u_spi_engine.len_acc [15:8], rval = 8'00000000).
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Adding EN signal on $auto$ff.cc:337:slice$3328 ($sdff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$1880_Y, Q = \u_spi_engine.len_acc [15:8]).
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Adding EN signal on $auto$ff.cc:337:slice$3327 ($sdff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$1909_Y, Q = \u_spi_engine.len_acc [7:0]).
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Adding SRST signal on $flatten\u_spi_engine.$procdff$3083 ($dff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$2244_Y, Q = \u_spi_engine.addr_acc, rval = 24'000000000000000000000000).
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Adding EN signal on $auto$ff.cc:337:slice$3357 ($sdff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$2225_Y, Q = \u_spi_engine.addr_acc).
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Adding SRST signal on $flatten\u_spi_engine.$procdff$3082 ($dff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$2276_Y, Q = \u_spi_engine.byte_pos, rval = 2'00).
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Adding EN signal on $auto$ff.cc:337:slice$3373 ($sdff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$2264_Y, Q = \u_spi_engine.byte_pos).
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Adding SRST signal on $flatten\u_spi_engine.$procdff$3081 ($dff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$2299_Y, Q = \u_spi_engine.opcode, rval = 8'00000000).
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Adding EN signal on $auto$ff.cc:337:slice$3387 ($sdff) from module spi_neuron_top (D = \u_spi_engine.rx_byte, Q = \u_spi_engine.opcode).
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Adding SRST signal on $flatten\u_spi_engine.$procdff$3080 ($dff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$2305_Y, Q = \u_spi_engine.state, rval = 4'0000).
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Adding EN signal on $auto$ff.cc:337:slice$3393 ($sdff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$2305_Y, Q = \u_spi_engine.state).
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Adding SRST signal on $flatten\u_spi_engine.$procdff$3079 ($dff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$2387_Y, Q = \u_spi_engine.run_num_layers, rval = 8'00000000).
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Adding EN signal on $auto$ff.cc:337:slice$3427 ($sdff) from module spi_neuron_top (D = \u_spi_engine.rx_byte, Q = \u_spi_engine.run_num_layers).
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Adding SRST signal on $flatten\u_spi_engine.$procdff$3078 ($dff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$2200_Y, Q = \u_spi_engine.run_start, rval = 1'0).
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Adding SRST signal on $flatten\u_spi_engine.$procdff$3077 ($dff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$2416_Y, Q = \u_spi_engine.buf_b_base, rval = 22'0000000000000000000000).
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Adding EN signal on $auto$ff.cc:337:slice$3442 ($sdff) from module spi_neuron_top (D = { \u_spi_engine.addr_acc [13:0] \u_spi_engine.rx_byte }, Q = \u_spi_engine.buf_b_base).
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Adding SRST signal on $flatten\u_spi_engine.$procdff$3076 ($dff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$2446_Y, Q = \u_spi_engine.buf_a_base, rval = 22'0000000000000000000000).
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Adding EN signal on $auto$ff.cc:337:slice$3448 ($sdff) from module spi_neuron_top (D = { \u_spi_engine.addr_acc [13:0] \u_spi_engine.rx_byte }, Q = \u_spi_engine.buf_a_base).
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Adding SRST signal on $flatten\u_spi_engine.$procdff$3075 ($dff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$2477_Y, Q = \u_spi_engine.table_base, rval = 22'0000000000000000000000).
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Adding EN signal on $auto$ff.cc:337:slice$3454 ($sdff) from module spi_neuron_top (D = { \u_spi_engine.addr_acc [13:0] \u_spi_engine.rx_byte }, Q = \u_spi_engine.table_base).
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Adding SRST signal on $flatten\u_spi_engine.$procdff$3074 ($dff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$1946_Y, Q = \u_spi_engine.nm_soft_rst, rval = 1'0).
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Adding SRST signal on $flatten\u_spi_engine.$procdff$3073 ($dff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$1977_Y, Q = \u_spi_engine.nm_start, rval = 1'0).
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Adding SRST signal on $flatten\u_spi_engine.$procdff$3072 ($dff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$2509_Y, Q = \u_spi_engine.bias_addr, rval = 22'0000000000000000000000).
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Adding EN signal on $auto$ff.cc:337:slice$3476 ($sdff) from module spi_neuron_top (D = { \u_spi_engine.addr_acc [13:0] \u_spi_engine.rx_byte }, Q = \u_spi_engine.bias_addr).
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Adding SRST signal on $flatten\u_spi_engine.$procdff$3071 ($dff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$2542_Y, Q = \u_spi_engine.w_base, rval = 22'0000000000000000000000).
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Adding EN signal on $auto$ff.cc:337:slice$3482 ($sdff) from module spi_neuron_top (D = { \u_spi_engine.addr_acc [13:0] \u_spi_engine.rx_byte }, Q = \u_spi_engine.w_base).
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Adding SRST signal on $flatten\u_spi_engine.$procdff$3070 ($dff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$2576_Y, Q = \u_spi_engine.x_base, rval = 22'0000000000000000000000).
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Adding EN signal on $auto$ff.cc:337:slice$3488 ($sdff) from module spi_neuron_top (D = { \u_spi_engine.addr_acc [13:0] \u_spi_engine.rx_byte }, Q = \u_spi_engine.x_base).
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Adding SRST signal on $flatten\u_spi_engine.$procdff$3069 ($dff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$2592_Y, Q = \u_spi_engine.ram_wdata, rval = 8'00000000).
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Adding EN signal on $auto$ff.cc:337:slice$3494 ($sdff) from module spi_neuron_top (D = \u_spi_engine.pending_wdata, Q = \u_spi_engine.ram_wdata).
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Adding SRST signal on $flatten\u_spi_engine.$procdff$3068 ($dff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$2607_Y, Q = \u_spi_engine.ram_addr, rval = 22'0000000000000000000000).
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Adding EN signal on $auto$ff.cc:337:slice$3500 ($sdff) from module spi_neuron_top (D = \u_spi_engine.cur_addr, Q = \u_spi_engine.ram_addr).
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Adding SRST signal on $flatten\u_spi_engine.$procdff$3067 ($dff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$2622_Y, Q = \u_spi_engine.ram_wr, rval = 1'0).
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Adding EN signal on $auto$ff.cc:337:slice$3506 ($sdff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$2618_Y, Q = \u_spi_engine.ram_wr).
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Adding SRST signal on $flatten\u_spi_engine.$procdff$3066 ($dff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$1997_Y, Q = \u_spi_engine.ram_req, rval = 1'0).
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Adding SRST signal on $flatten\u_int8_access.$procdff$3100 ($dff) from module spi_neuron_top (D = $flatten\u_int8_access.$procmux$2725_Y, Q = \u_int8_access.rdata, rval = 8'00000000).
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Adding EN signal on $auto$ff.cc:337:slice$3517 ($sdff) from module spi_neuron_top (D = $flatten\u_int8_access.$procmux$2721_Y, Q = \u_int8_access.rdata).
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Adding SRST signal on $flatten\u_int8_access.$procdff$3099 ($dff) from module spi_neuron_top (D = $flatten\u_int8_access.$procmux$2737_Y, Q = \u_int8_access.mem_wdata, rval = 16'0000000000000000).
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Adding EN signal on $auto$ff.cc:337:slice$3521 ($sdff) from module spi_neuron_top (D = $flatten\u_int8_access.$procmux$2733_Y, Q = \u_int8_access.mem_wdata).
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Adding SRST signal on $flatten\u_int8_access.$procdff$3098 ($dff) from module spi_neuron_top (D = $flatten\u_int8_access.$procmux$2746_Y, Q = \u_int8_access.mem_addr, rval = 22'0000000000000000000000).
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Adding EN signal on $auto$ff.cc:337:slice$3525 ($sdff) from module spi_neuron_top (D = $flatten\u_int8_access.$shr$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/int8_memory_access.v:106$268_Y, Q = \u_int8_access.mem_addr).
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Adding SRST signal on $flatten\u_int8_access.$procdff$3097 ($dff) from module spi_neuron_top (D = $flatten\u_int8_access.$procmux$2755_Y, Q = \u_int8_access.mem_wr, rval = 1'0).
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Adding EN signal on $auto$ff.cc:337:slice$3529 ($sdff) from module spi_neuron_top (D = \u_int8_access.wr, Q = \u_int8_access.mem_wr).
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Adding SRST signal on $flatten\u_int8_access.$procdff$3096 ($dff) from module spi_neuron_top (D = $flatten\u_int8_access.$procmux$2671_Y, Q = \u_int8_access.mem_req, rval = 1'0).
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Adding SRST signal on $flatten\u_int8_access.$procdff$3095 ($dff) from module spi_neuron_top (D = $flatten\u_int8_access.$procmux$2763_Y, Q = \u_int8_access.state, rval = 2'00).
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Adding EN signal on $auto$ff.cc:337:slice$3538 ($sdff) from module spi_neuron_top (D = $flatten\u_int8_access.$procmux$2763_Y, Q = \u_int8_access.state).
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Adding SRST signal on $flatten\u_int8_access.$procdff$3102 ($dff) from module spi_neuron_top (D = $flatten\u_int8_access.$procmux$2708_Y, Q = \u_int8_access.mem_lb_n, rval = 1'1).
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Adding EN signal on $auto$ff.cc:337:slice$3546 ($sdff) from module spi_neuron_top (D = $flatten\u_int8_access.$procmux$2708_Y, Q = \u_int8_access.mem_lb_n).
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Adding SRST signal on $flatten\u_memory_if.$procdff$3047 ($dff) from module spi_neuron_top (D = $flatten\u_memory_if.$procmux$1562_Y, Q = \u_memory_if.mem_ub_n, rval = 1'1).
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Adding EN signal on $auto$ff.cc:337:slice$3554 ($sdff) from module spi_neuron_top (D = \u_memory_if.ub_n, Q = \u_memory_if.mem_ub_n).
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Adding SRST signal on $flatten\u_memory_if.$procdff$3046 ($dff) from module spi_neuron_top (D = $flatten\u_memory_if.$procmux$1571_Y, Q = \u_memory_if.mem_lb_n, rval = 1'1).
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Adding EN signal on $auto$ff.cc:337:slice$3558 ($sdff) from module spi_neuron_top (D = \u_memory_if.lb_n, Q = \u_memory_if.mem_lb_n).
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Adding SRST signal on $flatten\u_memory_if.$procdff$3045 ($dff) from module spi_neuron_top (D = $flatten\u_memory_if.$procmux$1551_Y, Q = \u_memory_if.ready, rval = 1'0).
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Adding SRST signal on $flatten\u_memory_if.$procdff$3044 ($dff) from module spi_neuron_top (D = $flatten\u_memory_if.$procmux$1581_Y, Q = \u_memory_if.rdata, rval = 16'0000000000000000).
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Adding EN signal on $auto$ff.cc:337:slice$3567 ($sdff) from module spi_neuron_top (D = \u_memory_if.mem_rdata, Q = \u_memory_if.rdata).
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Adding SRST signal on $flatten\u_memory_if.$procdff$3043 ($dff) from module spi_neuron_top (D = $flatten\u_memory_if.$procmux$1590_Y, Q = \u_memory_if.mem_wdata, rval = 16'0000000000000000).
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Adding EN signal on $auto$ff.cc:337:slice$3573 ($sdff) from module spi_neuron_top (D = \u_memory_if.wdata, Q = \u_memory_if.mem_wdata).
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Adding SRST signal on $flatten\u_memory_if.$procdff$3042 ($dff) from module spi_neuron_top (D = $flatten\u_memory_if.$procmux$1599_Y, Q = \u_memory_if.mem_addr, rval = 22'0000000000000000000000).
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Adding EN signal on $auto$ff.cc:337:slice$3577 ($sdff) from module spi_neuron_top (D = \u_memory_if.addr, Q = \u_memory_if.mem_addr).
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Adding SRST signal on $flatten\u_memory_if.$procdff$3041 ($dff) from module spi_neuron_top (D = $flatten\u_memory_if.$procmux$1608_Y, Q = \u_memory_if.mem_wr, rval = 1'0).
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Adding EN signal on $auto$ff.cc:337:slice$3581 ($sdff) from module spi_neuron_top (D = \u_memory_if.wr, Q = \u_memory_if.mem_wr).
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Adding SRST signal on $flatten\u_memory_if.$procdff$3040 ($dff) from module spi_neuron_top (D = $flatten\u_memory_if.$procmux$1543_Y, Q = \u_memory_if.mem_req, rval = 1'0).
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Adding SRST signal on $flatten\u_memory_if.$procdff$3039 ($dff) from module spi_neuron_top (D = $flatten\u_memory_if.$procmux$1616_Y, Q = \u_memory_if.state, rval = 2'00).
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Adding EN signal on $auto$ff.cc:337:slice$3590 ($sdff) from module spi_neuron_top (D = $flatten\u_memory_if.$procmux$1616_Y, Q = \u_memory_if.state).
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Adding SRST signal on $flatten\u_layer_sequencer.$procdff$3003 ($dff) from module spi_neuron_top (D = $flatten\u_layer_sequencer.$procmux$716_Y, Q = \u_layer_sequencer.copy_idx, rval = 1'0).
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Adding EN signal on $auto$ff.cc:337:slice$3598 ($sdff) from module spi_neuron_top (D = $flatten\u_layer_sequencer.$procmux$716_Y, Q = \u_layer_sequencer.copy_idx).
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Adding SRST signal on $flatten\u_layer_sequencer.$procdff$3002 ($dff) from module spi_neuron_top (D = $flatten\u_layer_sequencer.$procmux$733_Y, Q = \u_layer_sequencer.write_sel, rval = 1'0).
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Adding EN signal on $auto$ff.cc:337:slice$3608 ($sdff) from module spi_neuron_top (D = $flatten\u_layer_sequencer.$procmux$733_Y, Q = \u_layer_sequencer.write_sel).
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Adding SRST signal on $flatten\u_layer_sequencer.$procdff$3001 ($dff) from module spi_neuron_top (D = $flatten\u_layer_sequencer.$procmux$750_Y, Q = \u_layer_sequencer.cur_sel, rval = 1'0).
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Adding EN signal on $auto$ff.cc:337:slice$3622 ($sdff) from module spi_neuron_top (D = \u_layer_sequencer.write_sel, Q = \u_layer_sequencer.cur_sel).
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Adding SRST signal on $flatten\u_layer_sequencer.$procdff$3000 ($dff) from module spi_neuron_top (D = $flatten\u_layer_sequencer.$procmux$652_Y, Q = \u_layer_sequencer.bias_addr_acc [23:16], rval = 8'00000000).
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Adding SRST signal on $flatten\u_layer_sequencer.$procdff$3000 ($dff) from module spi_neuron_top (D = $flatten\u_layer_sequencer.$procmux$636_Y, Q = \u_layer_sequencer.bias_addr_acc [7:0], rval = 8'00000000).
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Adding SRST signal on $flatten\u_layer_sequencer.$procdff$3000 ($dff) from module spi_neuron_top (D = $flatten\u_layer_sequencer.$procmux$622_Y, Q = \u_layer_sequencer.bias_addr_acc [15:8], rval = 8'00000000).
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Adding EN signal on $auto$ff.cc:337:slice$3632 ($sdff) from module spi_neuron_top (D = \u_layer_sequencer.ram_rdata, Q = \u_layer_sequencer.bias_addr_acc [15:8]).
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Adding EN signal on $auto$ff.cc:337:slice$3631 ($sdff) from module spi_neuron_top (D = \u_layer_sequencer.ram_rdata, Q = \u_layer_sequencer.bias_addr_acc [7:0]).
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Adding EN signal on $auto$ff.cc:337:slice$3630 ($sdff) from module spi_neuron_top (D = \u_layer_sequencer.ram_rdata, Q = \u_layer_sequencer.bias_addr_acc [23:16]).
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Adding SRST signal on $flatten\u_layer_sequencer.$procdff$2999 ($dff) from module spi_neuron_top (D = $flatten\u_layer_sequencer.$procmux$768_Y, Q = \u_layer_sequencer.w_base_acc [15:8], rval = 8'00000000).
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Adding SRST signal on $flatten\u_layer_sequencer.$procdff$2999 ($dff) from module spi_neuron_top (D = $flatten\u_layer_sequencer.$procmux$688_Y, Q = \u_layer_sequencer.w_base_acc [23:16], rval = 8'00000000).
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Adding SRST signal on $flatten\u_layer_sequencer.$procdff$2999 ($dff) from module spi_neuron_top (D = $flatten\u_layer_sequencer.$procmux$669_Y, Q = \u_layer_sequencer.w_base_acc [7:0], rval = 8'00000000).
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Adding EN signal on $auto$ff.cc:337:slice$3644 ($sdff) from module spi_neuron_top (D = \u_layer_sequencer.ram_rdata, Q = \u_layer_sequencer.w_base_acc [7:0]).
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Adding EN signal on $auto$ff.cc:337:slice$3643 ($sdff) from module spi_neuron_top (D = \u_layer_sequencer.ram_rdata, Q = \u_layer_sequencer.w_base_acc [23:16]).
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Adding EN signal on $auto$ff.cc:337:slice$3642 ($sdff) from module spi_neuron_top (D = \u_layer_sequencer.ram_rdata, Q = \u_layer_sequencer.w_base_acc [15:8]).
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Adding SRST signal on $flatten\u_layer_sequencer.$procdff$2998 ($dff) from module spi_neuron_top (D = $flatten\u_layer_sequencer.$procmux$796_Y, Q = \u_layer_sequencer.desc_byte_idx, rval = 3'000).
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Adding EN signal on $auto$ff.cc:337:slice$3654 ($sdff) from module spi_neuron_top (D = $flatten\u_layer_sequencer.$procmux$796_Y, Q = \u_layer_sequencer.desc_byte_idx).
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Adding SRST signal on $flatten\u_layer_sequencer.$procdff$2997 ($dff) from module spi_neuron_top (D = $flatten\u_layer_sequencer.$procmux$819_Y, Q = \u_layer_sequencer.desc_table_addr, rval = 22'0000000000000000000000).
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Adding EN signal on $auto$ff.cc:337:slice$3670 ($sdff) from module spi_neuron_top (D = $flatten\u_layer_sequencer.$procmux$819_Y, Q = \u_layer_sequencer.desc_table_addr).
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Adding SRST signal on $flatten\u_layer_sequencer.$procdff$2996 ($dff) from module spi_neuron_top (D = $flatten\u_layer_sequencer.$procmux$836_Y, Q = \u_layer_sequencer.num_layers_reg, rval = 8'00000000).
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Adding EN signal on $auto$ff.cc:337:slice$3684 ($sdff) from module spi_neuron_top (D = \u_layer_sequencer.run_num_layers, Q = \u_layer_sequencer.num_layers_reg).
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Adding SRST signal on $flatten\u_layer_sequencer.$procdff$2995 ($dff) from module spi_neuron_top (D = $flatten\u_layer_sequencer.$procmux$850_Y, Q = \u_layer_sequencer.layer_idx, rval = 8'00000000).
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Adding EN signal on $auto$ff.cc:337:slice$3688 ($sdff) from module spi_neuron_top (D = $flatten\u_layer_sequencer.$procmux$850_Y, Q = \u_layer_sequencer.layer_idx).
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Adding SRST signal on $flatten\u_layer_sequencer.$procdff$2994 ($dff) from module spi_neuron_top (D = $flatten\u_layer_sequencer.$procmux$862_Y, Q = \u_layer_sequencer.nm_bias_addr, rval = 22'0000000000000000000000).
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Adding EN signal on $auto$ff.cc:337:slice$3702 ($sdff) from module spi_neuron_top (D = \u_layer_sequencer.bias_addr_acc [21:0], Q = \u_layer_sequencer.nm_bias_addr).
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Adding SRST signal on $flatten\u_layer_sequencer.$procdff$2993 ($dff) from module spi_neuron_top (D = $flatten\u_layer_sequencer.$procmux$871_Y, Q = \u_layer_sequencer.nm_w_base, rval = 22'0000000000000000000000).
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Adding EN signal on $auto$ff.cc:337:slice$3704 ($sdff) from module spi_neuron_top (D = \u_layer_sequencer.w_base_acc [21:0], Q = \u_layer_sequencer.nm_w_base).
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Adding SRST signal on $flatten\u_layer_sequencer.$procdff$2992 ($dff) from module spi_neuron_top (D = $flatten\u_layer_sequencer.$procmux$880_Y, Q = \u_layer_sequencer.nm_x_base, rval = 22'0000000000000000000000).
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Adding EN signal on $auto$ff.cc:337:slice$3706 ($sdff) from module spi_neuron_top (D = $flatten\u_layer_sequencer.$ternary$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:229$498_Y, Q = \u_layer_sequencer.nm_x_base).
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Adding SRST signal on $flatten\u_layer_sequencer.$procdff$2991 ($dff) from module spi_neuron_top (D = $flatten\u_layer_sequencer.$procmux$894_Y, Q = \u_layer_sequencer.state, rval = 4'0000).
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Adding EN signal on $auto$ff.cc:337:slice$3708 ($sdff) from module spi_neuron_top (D = $flatten\u_layer_sequencer.$procmux$894_Y, Q = \u_layer_sequencer.state).
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Adding SRST signal on $flatten\u_layer_sequencer.$procdff$2990 ($dff) from module spi_neuron_top (D = $flatten\u_layer_sequencer.$procmux$776_Y, Q = \u_layer_sequencer.seq_done, rval = 1'0).
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Adding SRST signal on $flatten\u_layer_sequencer.$procdff$2989 ($dff) from module spi_neuron_top (D = $flatten\u_layer_sequencer.$procmux$923_Y, Q = \u_layer_sequencer.seq_busy, rval = 1'0).
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Adding EN signal on $auto$ff.cc:337:slice$3727 ($sdff) from module spi_neuron_top (D = $flatten\u_layer_sequencer.$procmux$923_Y, Q = \u_layer_sequencer.seq_busy).
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Adding SRST signal on $flatten\u_layer_sequencer.$procdff$2988 ($dff) from module spi_neuron_top (D = $flatten\u_layer_sequencer.$procmux$705_Y, Q = \u_layer_sequencer.nm_start, rval = 1'0).
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Adding SRST signal on $flatten\u_layer_sequencer.$procdff$2987 ($dff) from module spi_neuron_top (D = $flatten\u_layer_sequencer.$procmux$933_Y, Q = \u_layer_sequencer.ram_wdata, rval = 8'00000000).
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Adding EN signal on $auto$ff.cc:337:slice$3742 ($sdff) from module spi_neuron_top (D = $flatten\u_layer_sequencer.$shiftx$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:261$503_Y, Q = \u_layer_sequencer.ram_wdata).
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Adding SRST signal on $flatten\u_layer_sequencer.$procdff$2986 ($dff) from module spi_neuron_top (D = $flatten\u_layer_sequencer.$procmux$940_Y, Q = \u_layer_sequencer.ram_addr, rval = 22'0000000000000000000000).
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Adding EN signal on $auto$ff.cc:337:slice$3744 ($sdff) from module spi_neuron_top (D = $flatten\u_layer_sequencer.$procmux$940_Y, Q = \u_layer_sequencer.ram_addr).
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Adding SRST signal on $flatten\u_layer_sequencer.$procdff$2985 ($dff) from module spi_neuron_top (D = $flatten\u_layer_sequencer.$procmux$948_Y, Q = \u_layer_sequencer.ram_wr, rval = 1'0).
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Adding EN signal on $auto$ff.cc:337:slice$3748 ($sdff) from module spi_neuron_top (D = $flatten\u_layer_sequencer.$procmux$948_Y, Q = \u_layer_sequencer.ram_wr).
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Adding SRST signal on $flatten\u_layer_sequencer.$procdff$2984 ($dff) from module spi_neuron_top (D = $flatten\u_layer_sequencer.$procmux$695_Y, Q = \u_layer_sequencer.ram_req, rval = 1'0).
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Adding SRST signal on $flatten\u_neuron_memory.\u_neuron.$procdff$3105 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.\u_neuron.$procmux$2827_Y, Q = \u_neuron_memory.u_neuron.y, rval = 8'00000000).
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Adding EN signal on $auto$ff.cc:337:slice$3753 ($sdff) from module spi_neuron_top (D = $flatten\u_neuron_memory.\u_neuron.$procmux$2820_Y, Q = \u_neuron_memory.u_neuron.y).
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Adding SRST signal on $flatten\u_neuron_memory.\u_neuron.$procdff$3106 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.\u_neuron.$procmux$2810_Y, Q = \u_neuron_memory.u_neuron.busy, rval = 1'0).
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Adding SRST signal on $flatten\u_neuron_memory.\u_neuron.$procdff$3107 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.\u_neuron.$procmux$2772_Y, Q = \u_neuron_memory.u_neuron.done, rval = 1'0).
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Adding SRST signal on $flatten\u_neuron_memory.\u_neuron.$procdff$3108 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.\u_neuron.$procmux$2796_Y, Q = \u_neuron_memory.u_neuron.group_index, rval = 2'00).
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Adding EN signal on $auto$ff.cc:337:slice$3765 ($sdff) from module spi_neuron_top (D = $flatten\u_neuron_memory.\u_neuron.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:141$266_Y, Q = \u_neuron_memory.u_neuron.group_index).
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Adding SRST signal on $flatten\u_neuron_memory.\u_neuron.$procdff$3109 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.\u_neuron.$procmux$2785_Y, Q = \u_neuron_memory.u_neuron.acc, rval = 0).
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Adding EN signal on $auto$ff.cc:337:slice$3773 ($sdff) from module spi_neuron_top (D = $flatten\u_neuron_memory.\u_neuron.$procmux$2783_Y, Q = \u_neuron_memory.u_neuron.acc).
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Adding SRST signal on $flatten\u_psram_ctrl.$procdff$3065 ($dff) from module spi_neuron_top (D = $flatten\u_psram_ctrl.$procmux$1626_Y, Q = \u_psram_ctrl.dq_oe, rval = 1'0).
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Adding SRST signal on $flatten\u_psram_ctrl.$procdff$3064 ($dff) from module spi_neuron_top (D = $flatten\u_psram_ctrl.$procmux$1739_Y, Q = \u_psram_ctrl.dq_out, rval = 16'0000000000000000).
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Adding EN signal on $auto$ff.cc:337:slice$3778 ($sdff) from module spi_neuron_top (D = \u_psram_ctrl.mem_wdata, Q = \u_psram_ctrl.dq_out).
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Adding SRST signal on $flatten\u_psram_ctrl.$procdff$3063 ($dff) from module spi_neuron_top (D = $flatten\u_psram_ctrl.$procmux$1745_Y, Q = \u_psram_ctrl.ub_reg, rval = 1'1).
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Adding EN signal on $auto$ff.cc:337:slice$3782 ($sdff) from module spi_neuron_top (D = $flatten\u_psram_ctrl.$procmux$1745_Y, Q = \u_psram_ctrl.ub_reg).
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Adding SRST signal on $flatten\u_psram_ctrl.$procdff$3062 ($dff) from module spi_neuron_top (D = $flatten\u_psram_ctrl.$procmux$1757_Y, Q = \u_psram_ctrl.lb_reg, rval = 1'1).
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Adding EN signal on $auto$ff.cc:337:slice$3790 ($sdff) from module spi_neuron_top (D = $flatten\u_psram_ctrl.$procmux$1757_Y, Q = \u_psram_ctrl.lb_reg).
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Adding SRST signal on $flatten\u_psram_ctrl.$procdff$3061 ($dff) from module spi_neuron_top (D = $flatten\u_psram_ctrl.$procmux$1774_Y, Q = \u_psram_ctrl.wr_reg, rval = 1'0).
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Adding EN signal on $auto$ff.cc:337:slice$3798 ($sdff) from module spi_neuron_top (D = \u_psram_ctrl.mem_wr, Q = \u_psram_ctrl.wr_reg).
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Adding SRST signal on $flatten\u_psram_ctrl.$procdff$3060 ($dff) from module spi_neuron_top (D = $flatten\u_psram_ctrl.$procmux$1785_Y, Q = \u_psram_ctrl.wdata_reg, rval = 16'0000000000000000).
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Adding EN signal on $auto$ff.cc:337:slice$3802 ($sdff) from module spi_neuron_top (D = \u_psram_ctrl.mem_wdata, Q = \u_psram_ctrl.wdata_reg).
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Adding SRST signal on $flatten\u_psram_ctrl.$procdff$3059 ($dff) from module spi_neuron_top (D = $flatten\u_psram_ctrl.$procmux$1796_Y, Q = \u_psram_ctrl.address_reg, rval = 22'0000000000000000000000).
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Adding EN signal on $auto$ff.cc:337:slice$3806 ($sdff) from module spi_neuron_top (D = \u_psram_ctrl.mem_addr, Q = \u_psram_ctrl.address_reg).
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Adding SRST signal on $flatten\u_psram_ctrl.$procdff$3058 ($dff) from module spi_neuron_top (D = $flatten\u_psram_ctrl.$procmux$1802_Y, Q = \u_psram_ctrl.counter, rval = 14'00000000000000).
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Adding EN signal on $auto$ff.cc:337:slice$3810 ($sdff) from module spi_neuron_top (D = $flatten\u_psram_ctrl.$procmux$1802_Y, Q = \u_psram_ctrl.counter).
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Adding SRST signal on $flatten\u_neuron_memory.\u_mem.$procdff$3095 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.\u_mem.$procmux$2763_Y, Q = \u_neuron_memory.u_mem.state, rval = 2'00).
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Adding EN signal on $auto$ff.cc:337:slice$3818 ($sdff) from module spi_neuron_top (D = $flatten\u_neuron_memory.\u_mem.$procmux$2763_Y, Q = \u_neuron_memory.u_mem.state).
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Adding SRST signal on $flatten\u_neuron_memory.\u_mem.$procdff$3096 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.\u_mem.$procmux$2671_Y, Q = \u_neuron_memory.u_mem.mem_req, rval = 1'0).
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Adding SRST signal on $flatten\u_neuron_memory.\u_mem.$procdff$3097 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.\u_mem.$procmux$2755_Y, Q = \u_neuron_memory.u_mem.mem_wr, rval = 1'0).
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Adding EN signal on $auto$ff.cc:337:slice$3831 ($sdff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.wr, Q = \u_neuron_memory.u_mem.mem_wr).
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Adding SRST signal on $flatten\u_neuron_memory.\u_mem.$procdff$3098 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.\u_mem.$procmux$2746_Y, Q = \u_neuron_memory.u_mem.mem_addr, rval = 22'0000000000000000000000).
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Adding EN signal on $auto$ff.cc:337:slice$3835 ($sdff) from module spi_neuron_top (D = $flatten\u_neuron_memory.\u_mem.$shr$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/int8_memory_access.v:106$268_Y, Q = \u_neuron_memory.u_mem.mem_addr).
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Adding SRST signal on $flatten\u_neuron_memory.\u_mem.$procdff$3099 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.\u_mem.$procmux$2737_Y, Q = \u_neuron_memory.u_mem.mem_wdata, rval = 16'0000000000000000).
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Adding EN signal on $auto$ff.cc:337:slice$3839 ($sdff) from module spi_neuron_top (D = $flatten\u_neuron_memory.\u_mem.$procmux$2733_Y, Q = \u_neuron_memory.u_mem.mem_wdata).
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Adding SRST signal on $flatten\u_neuron_memory.\u_mem.$procdff$3100 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.\u_mem.$procmux$2725_Y, Q = \u_neuron_memory.u_mem.rdata, rval = 8'00000000).
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Adding EN signal on $auto$ff.cc:337:slice$3843 ($sdff) from module spi_neuron_top (D = $flatten\u_neuron_memory.\u_mem.$procmux$2721_Y, Q = \u_neuron_memory.u_mem.rdata).
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Adding SRST signal on $flatten\u_neuron_memory.\u_mem.$procdff$3101 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.\u_mem.$procmux$2679_Y, Q = \u_neuron_memory.u_mem.ready, rval = 1'0).
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Adding SRST signal on $flatten\u_neuron_memory.\u_mem.$procdff$3102 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.\u_mem.$procmux$2708_Y, Q = \u_neuron_memory.u_mem.mem_lb_n, rval = 1'1).
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Adding EN signal on $auto$ff.cc:337:slice$3852 ($sdff) from module spi_neuron_top (D = $flatten\u_neuron_memory.\u_mem.$procmux$2708_Y, Q = \u_neuron_memory.u_mem.mem_lb_n).
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Adding SRST signal on $flatten\u_neuron_memory.\u_mem.$procdff$3103 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.\u_mem.$procmux$2696_Y, Q = \u_neuron_memory.u_mem.mem_ub_n, rval = 1'1).
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Adding EN signal on $auto$ff.cc:337:slice$3860 ($sdff) from module spi_neuron_top (D = $flatten\u_neuron_memory.\u_mem.$procmux$2696_Y, Q = \u_neuron_memory.u_mem.mem_ub_n).
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Adding EN signal on $flatten\u_neuron_memory.$procdff$3017 ($dff) from module spi_neuron_top (D = 1, Q = \u_neuron_memory.rst_i).
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Adding SRST signal on $flatten\u_neuron_memory.$procdff$3016 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$procmux$1151_Y, Q = \u_neuron_memory.neuron_start, rval = 1'0).
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Adding EN signal on $flatten\u_neuron_memory.$procdff$3015 ($dff) from module spi_neuron_top (D = 8'00000000, Q = \u_neuron_memory.access_wdata).
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Adding SRST signal on $flatten\u_neuron_memory.$procdff$3014 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$procmux$1220_Y, Q = \u_neuron_memory.access_addr, rval = 22'0000000000000000000000).
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Adding EN signal on $auto$ff.cc:337:slice$3871 ($sdff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$procmux$1220_Y, Q = \u_neuron_memory.access_addr).
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Adding SRST signal on $flatten\u_neuron_memory.$procdff$3013 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$procmux$1249_Y, Q = \u_neuron_memory.access_wr, rval = 1'0).
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Adding EN signal on $auto$ff.cc:337:slice$3887 ($sdff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$procmux$1249_Y, Q = \u_neuron_memory.access_wr).
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Adding SRST signal on $flatten\u_neuron_memory.$procdff$3012 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$procmux$1163_Y, Q = \u_neuron_memory.access_req, rval = 1'0).
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Adding SRST signal on $flatten\u_neuron_memory.$procdff$3011 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$procmux$1276_Y, Q = \u_neuron_memory.bias_reg, rval = 8'00000000).
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Adding EN signal on $auto$ff.cc:337:slice$3900 ($sdff) from module spi_neuron_top (D = \u_neuron_memory.access_rdata, Q = \u_neuron_memory.bias_reg).
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Adding SRST signal on $flatten\u_neuron_memory.$procdff$3010 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$procmux$1288_Y, Q = \u_neuron_memory.bias_group_addr, rval = 22'0000000000000000000000).
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Adding EN signal on $auto$ff.cc:337:slice$3904 ($sdff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$procmux$1288_Y, Q = \u_neuron_memory.bias_group_addr).
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Adding SRST signal on $flatten\u_neuron_memory.$procdff$3009 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$procmux$1303_Y, Q = \u_neuron_memory.w_group_base, rval = 22'0000000000000000000000).
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Adding EN signal on $auto$ff.cc:337:slice$3916 ($sdff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$procmux$1303_Y, Q = \u_neuron_memory.w_group_base).
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Adding SRST signal on $flatten\u_neuron_memory.$procdff$3008 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$procmux$1318_Y, Q = \u_neuron_memory.neuron_index, rval = 1'0).
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Adding EN signal on $auto$ff.cc:337:slice$3928 ($sdff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$procmux$1318_Y, Q = \u_neuron_memory.neuron_index).
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Adding SRST signal on $flatten\u_neuron_memory.$procdff$3007 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$procmux$1333_Y, Q = \u_neuron_memory.index, rval = 6'000000).
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Adding EN signal on $auto$ff.cc:337:slice$3938 ($sdff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$procmux$1333_Y, Q = \u_neuron_memory.index).
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Adding SRST signal on $flatten\u_neuron_memory.$procdff$3006 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$procmux$1134_Y, Q = \u_neuron_memory.done, rval = 1'0).
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Adding SRST signal on $flatten\u_neuron_memory.$procdff$3005 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$procmux$1362_Y, Q = \u_neuron_memory.busy, rval = 1'0).
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Adding EN signal on $auto$ff.cc:337:slice$3963 ($sdff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$procmux$1362_Y, Q = \u_neuron_memory.busy).
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Adding SRST signal on $flatten\u_neuron_memory.$procdff$3004 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$procmux$1381_Y, Q = \u_neuron_memory.state, rval = 4'0000).
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Adding EN signal on $auto$ff.cc:337:slice$3973 ($sdff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$procmux$1381_Y, Q = \u_neuron_memory.state).
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Adding SRST signal on $flatten\u_psram_ctrl.$procdff$3056 ($dff) from module spi_neuron_top (D = $flatten\u_psram_ctrl.$procmux$1647_Y, Q = \u_psram_ctrl.psram_ub_n, rval = 1'1).
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Adding SRST signal on $flatten\u_psram_ctrl.$procdff$3055 ($dff) from module spi_neuron_top (D = $flatten\u_psram_ctrl.$procmux$1661_Y, Q = \u_psram_ctrl.psram_lb_n, rval = 1'1).
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Adding SRST signal on $flatten\u_psram_ctrl.$procdff$3054 ($dff) from module spi_neuron_top (D = $flatten\u_psram_ctrl.$procmux$1678_Y, Q = \u_psram_ctrl.psram_we_n, rval = 1'1).
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Adding SRST signal on $flatten\u_psram_ctrl.$procdff$3053 ($dff) from module spi_neuron_top (D = $flatten\u_psram_ctrl.$procmux$1695_Y, Q = \u_psram_ctrl.psram_oe_n, rval = 1'1).
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Adding SRST signal on $flatten\u_psram_ctrl.$procdff$3052 ($dff) from module spi_neuron_top (D = $flatten\u_psram_ctrl.$procmux$1708_Y, Q = \u_psram_ctrl.psram_ce_n, rval = 1'1).
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Adding SRST signal on $flatten\u_psram_ctrl.$procdff$3051 ($dff) from module spi_neuron_top (D = $flatten\u_psram_ctrl.$procmux$1828_Y, Q = \u_psram_ctrl.psram_a, rval = 22'0000000000000000000000).
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Adding EN signal on $auto$ff.cc:337:slice$3996 ($sdff) from module spi_neuron_top (D = \u_psram_ctrl.mem_addr, Q = \u_psram_ctrl.psram_a).
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Adding SRST signal on $flatten\u_psram_ctrl.$procdff$3050 ($dff) from module spi_neuron_top (D = $flatten\u_psram_ctrl.$procmux$1721_Y, Q = \u_psram_ctrl.mem_ready, rval = 1'0).
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Adding SRST signal on $flatten\u_psram_ctrl.$procdff$3049 ($dff) from module spi_neuron_top (D = $flatten\u_psram_ctrl.$procmux$1839_Y, Q = \u_psram_ctrl.mem_rdata, rval = 16'0000000000000000).
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Adding EN signal on $auto$ff.cc:337:slice$4001 ($sdff) from module spi_neuron_top (D = $flatten\u_psram_ctrl.$ternary$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/psram_controller.v:93$359_Y, Q = \u_psram_ctrl.mem_rdata).
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Adding SRST signal on $flatten\u_psram_ctrl.$procdff$3048 ($dff) from module spi_neuron_top (D = $flatten\u_psram_ctrl.$procmux$1845_Y, Q = \u_psram_ctrl.state, rval = 3'000).
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Adding EN signal on $auto$ff.cc:337:slice$4005 ($sdff) from module spi_neuron_top (D = $flatten\u_psram_ctrl.$procmux$1845_Y, Q = \u_psram_ctrl.state).
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Adding SRST signal on $flatten\u_int8_access.$procdff$3103 ($dff) from module spi_neuron_top (D = $flatten\u_int8_access.$procmux$2696_Y, Q = \u_int8_access.mem_ub_n, rval = 1'1).
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Adding EN signal on $auto$ff.cc:337:slice$4017 ($sdff) from module spi_neuron_top (D = $flatten\u_int8_access.$procmux$2696_Y, Q = \u_int8_access.mem_ub_n).
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Adding SRST signal on $flatten\u_neuron_memory.\u_mem.$procdff$3104 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.\u_mem.$procmux$2690_Y, Q = \u_neuron_memory.u_mem.addr_reg, rval = 22'0000000000000000000000).
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Adding EN signal on $auto$ff.cc:337:slice$4025 ($sdff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.addr, Q = \u_neuron_memory.u_mem.addr_reg).
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Adding SRST signal on $flatten\u_arbiter.$procdff$3038 ($dff) from module spi_neuron_top (D = $flatten\u_arbiter.$procmux$1449_Y, Q = \u_arbiter.owner, rval = 2'00).
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Adding EN signal on $auto$ff.cc:337:slice$4029 ($sdff) from module spi_neuron_top (D = $flatten\u_arbiter.$procmux$1449_Y, Q = \u_arbiter.owner).
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Adding SRST signal on $flatten\u_arbiter.$procdff$3037 ($dff) from module spi_neuron_top (D = $flatten\u_arbiter.$procmux$1480_Y, Q = \u_arbiter.m_wdata, rval = 8'00000000).
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Adding EN signal on $auto$ff.cc:337:slice$4037 ($sdff) from module spi_neuron_top (D = $flatten\u_arbiter.$procmux$1478_Y, Q = \u_arbiter.m_wdata).
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Adding SRST signal on $flatten\u_arbiter.$procdff$3036 ($dff) from module spi_neuron_top (D = $flatten\u_arbiter.$procmux$1496_Y, Q = \u_arbiter.m_addr, rval = 22'0000000000000000000000).
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Adding EN signal on $auto$ff.cc:337:slice$4043 ($sdff) from module spi_neuron_top (D = $flatten\u_arbiter.$procmux$1494_Y, Q = \u_arbiter.m_addr).
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Adding SRST signal on $flatten\u_arbiter.$procdff$3035 ($dff) from module spi_neuron_top (D = $flatten\u_arbiter.$procmux$1512_Y, Q = \u_arbiter.m_wr, rval = 1'0).
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Adding EN signal on $auto$ff.cc:337:slice$4049 ($sdff) from module spi_neuron_top (D = $flatten\u_arbiter.$procmux$1510_Y, Q = \u_arbiter.m_wr).
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Adding SRST signal on $flatten\u_arbiter.$procdff$3034 ($dff) from module spi_neuron_top (D = $flatten\u_arbiter.$procmux$1440_Y, Q = \u_arbiter.m_req, rval = 1'0).
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Adding SRST signal on $flatten\u_arbiter.$procdff$3033 ($dff) from module spi_neuron_top (D = $flatten\u_arbiter.$procmux$1407_Y, Q = \u_arbiter.c_ready, rval = 1'0).
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Adding SRST signal on $flatten\u_arbiter.$procdff$3032 ($dff) from module spi_neuron_top (D = $flatten\u_arbiter.$procmux$1519_Y, Q = \u_arbiter.c_rdata, rval = 8'00000000).
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Adding EN signal on $auto$ff.cc:337:slice$4065 ($sdff) from module spi_neuron_top (D = \u_arbiter.m_rdata, Q = \u_arbiter.c_rdata).
|
|
Adding SRST signal on $flatten\u_arbiter.$procdff$3031 ($dff) from module spi_neuron_top (D = $flatten\u_arbiter.$procmux$1415_Y, Q = \u_arbiter.b_ready, rval = 1'0).
|
|
Adding SRST signal on $flatten\u_arbiter.$procdff$3030 ($dff) from module spi_neuron_top (D = $flatten\u_arbiter.$procmux$1527_Y, Q = \u_arbiter.b_rdata, rval = 8'00000000).
|
|
Adding EN signal on $auto$ff.cc:337:slice$4074 ($sdff) from module spi_neuron_top (D = \u_arbiter.m_rdata, Q = \u_arbiter.b_rdata).
|
|
Adding SRST signal on $flatten\u_arbiter.$procdff$3029 ($dff) from module spi_neuron_top (D = $flatten\u_arbiter.$procmux$1424_Y, Q = \u_arbiter.a_ready, rval = 1'0).
|
|
Adding SRST signal on $flatten\u_arbiter.$procdff$3028 ($dff) from module spi_neuron_top (D = $flatten\u_arbiter.$procmux$1536_Y, Q = \u_arbiter.a_rdata, rval = 8'00000000).
|
|
Adding EN signal on $auto$ff.cc:337:slice$4083 ($sdff) from module spi_neuron_top (D = \u_arbiter.m_rdata, Q = \u_arbiter.a_rdata).
|
|
Setting constant 0-bit at position 0 on $auto$ff.cc:337:slice$3870 ($dffe) from module spi_neuron_top.
|
|
Setting constant 0-bit at position 1 on $auto$ff.cc:337:slice$3870 ($dffe) from module spi_neuron_top.
|
|
Setting constant 0-bit at position 2 on $auto$ff.cc:337:slice$3870 ($dffe) from module spi_neuron_top.
|
|
Setting constant 0-bit at position 3 on $auto$ff.cc:337:slice$3870 ($dffe) from module spi_neuron_top.
|
|
Setting constant 0-bit at position 4 on $auto$ff.cc:337:slice$3870 ($dffe) from module spi_neuron_top.
|
|
Setting constant 0-bit at position 5 on $auto$ff.cc:337:slice$3870 ($dffe) from module spi_neuron_top.
|
|
Setting constant 0-bit at position 6 on $auto$ff.cc:337:slice$3870 ($dffe) from module spi_neuron_top.
|
|
Setting constant 0-bit at position 7 on $auto$ff.cc:337:slice$3870 ($dffe) from module spi_neuron_top.
|
|
Setting constant 1-bit at position 0 on $auto$ff.cc:337:slice$3868 ($dffe) from module spi_neuron_top.
|
|
Setting constant 0-bit at position 1 on $auto$ff.cc:337:slice$3868 ($dffe) from module spi_neuron_top.
|
|
Setting constant 0-bit at position 2 on $auto$ff.cc:337:slice$3868 ($dffe) from module spi_neuron_top.
|
|
Setting constant 0-bit at position 3 on $auto$ff.cc:337:slice$3868 ($dffe) from module spi_neuron_top.
|
|
Setting constant 0-bit at position 4 on $auto$ff.cc:337:slice$3868 ($dffe) from module spi_neuron_top.
|
|
Setting constant 0-bit at position 5 on $auto$ff.cc:337:slice$3868 ($dffe) from module spi_neuron_top.
|
|
Setting constant 0-bit at position 6 on $auto$ff.cc:337:slice$3868 ($dffe) from module spi_neuron_top.
|
|
Setting constant 0-bit at position 7 on $auto$ff.cc:337:slice$3868 ($dffe) from module spi_neuron_top.
|
|
Setting constant 0-bit at position 8 on $auto$ff.cc:337:slice$3868 ($dffe) from module spi_neuron_top.
|
|
Setting constant 0-bit at position 9 on $auto$ff.cc:337:slice$3868 ($dffe) from module spi_neuron_top.
|
|
Setting constant 0-bit at position 10 on $auto$ff.cc:337:slice$3868 ($dffe) from module spi_neuron_top.
|
|
Setting constant 0-bit at position 11 on $auto$ff.cc:337:slice$3868 ($dffe) from module spi_neuron_top.
|
|
Setting constant 0-bit at position 12 on $auto$ff.cc:337:slice$3868 ($dffe) from module spi_neuron_top.
|
|
Setting constant 0-bit at position 13 on $auto$ff.cc:337:slice$3868 ($dffe) from module spi_neuron_top.
|
|
Setting constant 0-bit at position 14 on $auto$ff.cc:337:slice$3868 ($dffe) from module spi_neuron_top.
|
|
Setting constant 0-bit at position 15 on $auto$ff.cc:337:slice$3868 ($dffe) from module spi_neuron_top.
|
|
Setting constant 0-bit at position 16 on $auto$ff.cc:337:slice$3868 ($dffe) from module spi_neuron_top.
|
|
Setting constant 0-bit at position 17 on $auto$ff.cc:337:slice$3868 ($dffe) from module spi_neuron_top.
|
|
Setting constant 0-bit at position 18 on $auto$ff.cc:337:slice$3868 ($dffe) from module spi_neuron_top.
|
|
Setting constant 0-bit at position 19 on $auto$ff.cc:337:slice$3868 ($dffe) from module spi_neuron_top.
|
|
Setting constant 0-bit at position 20 on $auto$ff.cc:337:slice$3868 ($dffe) from module spi_neuron_top.
|
|
Setting constant 0-bit at position 21 on $auto$ff.cc:337:slice$3868 ($dffe) from module spi_neuron_top.
|
|
Setting constant 0-bit at position 22 on $auto$ff.cc:337:slice$3868 ($dffe) from module spi_neuron_top.
|
|
Setting constant 0-bit at position 23 on $auto$ff.cc:337:slice$3868 ($dffe) from module spi_neuron_top.
|
|
Setting constant 0-bit at position 24 on $auto$ff.cc:337:slice$3868 ($dffe) from module spi_neuron_top.
|
|
Setting constant 0-bit at position 25 on $auto$ff.cc:337:slice$3868 ($dffe) from module spi_neuron_top.
|
|
Setting constant 0-bit at position 26 on $auto$ff.cc:337:slice$3868 ($dffe) from module spi_neuron_top.
|
|
Setting constant 0-bit at position 27 on $auto$ff.cc:337:slice$3868 ($dffe) from module spi_neuron_top.
|
|
Setting constant 0-bit at position 28 on $auto$ff.cc:337:slice$3868 ($dffe) from module spi_neuron_top.
|
|
Setting constant 0-bit at position 29 on $auto$ff.cc:337:slice$3868 ($dffe) from module spi_neuron_top.
|
|
Setting constant 0-bit at position 30 on $auto$ff.cc:337:slice$3868 ($dffe) from module spi_neuron_top.
|
|
Setting constant 0-bit at position 31 on $auto$ff.cc:337:slice$3868 ($dffe) from module spi_neuron_top.
|
|
Setting constant 1-bit at position 0 on $flatten\u_psram_ctrl.$procdff$3057 ($dff) from module spi_neuron_top.
|
|
Setting constant 0-bit at position 0 on $auto$ff.cc:337:slice$3292 ($dffe) from module spi_neuron_top.
|
|
Setting constant 0-bit at position 2 on $auto$ff.cc:337:slice$3250 ($sdffe) from module spi_neuron_top.
|
|
Setting constant 0-bit at position 3 on $auto$ff.cc:337:slice$3250 ($sdffe) from module spi_neuron_top.
|
|
Setting constant 0-bit at position 4 on $auto$ff.cc:337:slice$3250 ($sdffe) from module spi_neuron_top.
|
|
Setting constant 0-bit at position 5 on $auto$ff.cc:337:slice$3250 ($sdffe) from module spi_neuron_top.
|
|
Setting constant 0-bit at position 6 on $auto$ff.cc:337:slice$3250 ($sdffe) from module spi_neuron_top.
|
|
Setting constant 0-bit at position 7 on $auto$ff.cc:337:slice$3250 ($sdffe) from module spi_neuron_top.
|
|
|
|
16.7. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \spi_neuron_top..
|
|
Removed 419 unused cells and 1634 unused wires.
|
|
<suppressed ~465 debug messages>
|
|
|
|
16.8. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module spi_neuron_top.
|
|
<suppressed ~36 debug messages>
|
|
|
|
16.9. Rerunning OPT passes. (Maybe there is more to do..)
|
|
|
|
16.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \spi_neuron_top..
|
|
Creating internal representation of mux trees.
|
|
Evaluating internal representation of mux trees.
|
|
Analyzing evaluation results.
|
|
Removed 0 multiplexer ports.
|
|
<suppressed ~454 debug messages>
|
|
|
|
16.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \spi_neuron_top.
|
|
New ctrl vector for $pmux cell $flatten\u_arbiter.$procmux$1449: { $auto$opt_reduce.cc:137:opt_pmux$4089 $flatten\u_arbiter.$procmux$1443_CMP }
|
|
New ctrl vector for $pmux cell $flatten\u_psram_ctrl.$procmux$1802: { $flatten\u_psram_ctrl.$procmux$1722_CMP $auto$opt_reduce.cc:137:opt_pmux$4091 $flatten\u_psram_ctrl.$procmux$1633_CMP $flatten\u_psram_ctrl.$procmux$1752_CMP }
|
|
New ctrl vector for $pmux cell $flatten\u_neuron_memory.$procmux$1163: { $flatten\u_neuron_memory.$procmux$1058_CMP $auto$opt_reduce.cc:137:opt_pmux$4093 $flatten\u_neuron_memory.$procmux$1179_CMP }
|
|
New ctrl vector for $pmux cell $flatten\u_neuron_memory.$procmux$1249: { $flatten\u_neuron_memory.$procmux$1058_CMP $auto$opt_reduce.cc:137:opt_pmux$4095 $flatten\u_neuron_memory.$procmux$1179_CMP }
|
|
New ctrl vector for $pmux cell $flatten\u_spi_engine.$procmux$1909: { $auto$opt_reduce.cc:137:opt_pmux$4097 $flatten\u_spi_engine.$procmux$1890_CMP }
|
|
Optimizing cells in module \spi_neuron_top.
|
|
Performed a total of 5 changes.
|
|
|
|
16.12. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\spi_neuron_top'.
|
|
Computing hashes of 993 cells of `\spi_neuron_top'.
|
|
Finding duplicate cells in `\spi_neuron_top'.
|
|
Computing hashes of 868 cells of `\spi_neuron_top'.
|
|
Finding duplicate cells in `\spi_neuron_top'.
|
|
Computing hashes of 859 cells of `\spi_neuron_top'.
|
|
Finding duplicate cells in `\spi_neuron_top'.
|
|
<suppressed ~402 debug messages>
|
|
Removed a total of 134 cells.
|
|
|
|
16.13. Executing OPT_DFF pass (perform DFF optimizations).
|
|
Adding EN signal on $auto$ff.cc:337:slice$4030 ($sdffe) from module spi_neuron_top (D = $flatten\u_arbiter.$procmux$1449_Y, Q = \u_arbiter.owner).
|
|
Adding EN signal on $auto$ff.cc:337:slice$3344 ($sdffe) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$1909_Y, Q = \u_spi_engine.len_acc [7:0]).
|
|
Adding EN signal on $auto$ff.cc:337:slice$3888 ($sdffe) from module spi_neuron_top (D = $flatten\u_neuron_memory.$procmux$1249_Y, Q = \u_neuron_memory.access_wr).
|
|
Setting constant 0-bit at position 21 on $auto$ff.cc:337:slice$3526 ($sdffe) from module spi_neuron_top.
|
|
|
|
16.14. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \spi_neuron_top..
|
|
Removed 0 unused cells and 134 unused wires.
|
|
<suppressed ~1 debug messages>
|
|
|
|
16.15. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module spi_neuron_top.
|
|
|
|
16.16. Rerunning OPT passes. (Maybe there is more to do..)
|
|
|
|
16.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \spi_neuron_top..
|
|
Creating internal representation of mux trees.
|
|
Evaluating internal representation of mux trees.
|
|
Analyzing evaluation results.
|
|
Removed 0 multiplexer ports.
|
|
<suppressed ~443 debug messages>
|
|
|
|
16.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \spi_neuron_top.
|
|
New input vector for $reduce_and cell $auto$opt_dff.cc:337:make_patterns_logic$4114: { $auto$opt_dff.cc:319:make_patterns_logic$3873 $auto$opt_dff.cc:319:make_patterns_logic$3875 $auto$opt_dff.cc:319:make_patterns_logic$3881 $auto$opt_dff.cc:319:make_patterns_logic$3883 $auto$opt_dff.cc:319:make_patterns_logic$4109 $auto$opt_dff.cc:319:make_patterns_logic$4111 }
|
|
New input vector for $reduce_and cell $auto$opt_dff.cc:337:make_patterns_logic$4102: { $auto$opt_dff.cc:319:make_patterns_logic$4031 $auto$opt_dff.cc:319:make_patterns_logic$4033 $auto$opt_dff.cc:319:make_patterns_logic$4099 }
|
|
New input vector for $reduce_and cell $auto$opt_dff.cc:337:make_patterns_logic$4107: { $auto$rtlil.cc:3267:Not$3252 $auto$opt_dff.cc:319:make_patterns_logic$3297 $auto$opt_dff.cc:319:make_patterns_logic$3303 $auto$opt_dff.cc:319:make_patterns_logic$3305 $auto$opt_dff.cc:319:make_patterns_logic$3347 $auto$opt_dff.cc:319:make_patterns_logic$4104 }
|
|
Optimizing cells in module \spi_neuron_top.
|
|
Performed a total of 3 changes.
|
|
|
|
16.19. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\spi_neuron_top'.
|
|
Computing hashes of 866 cells of `\spi_neuron_top'.
|
|
Finding duplicate cells in `\spi_neuron_top'.
|
|
Removed a total of 0 cells.
|
|
|
|
16.20. Executing OPT_DFF pass (perform DFF optimizations).
|
|
Setting constant 0-bit at position 21 on $auto$ff.cc:337:slice$3578 ($sdffe) from module spi_neuron_top.
|
|
|
|
16.21. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \spi_neuron_top..
|
|
Removed 3 unused cells and 3 unused wires.
|
|
<suppressed ~4 debug messages>
|
|
|
|
16.22. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module spi_neuron_top.
|
|
|
|
16.23. Rerunning OPT passes. (Maybe there is more to do..)
|
|
|
|
16.24. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \spi_neuron_top..
|
|
Creating internal representation of mux trees.
|
|
Evaluating internal representation of mux trees.
|
|
Analyzing evaluation results.
|
|
Removed 0 multiplexer ports.
|
|
<suppressed ~443 debug messages>
|
|
|
|
16.25. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \spi_neuron_top.
|
|
Performed a total of 0 changes.
|
|
|
|
16.26. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\spi_neuron_top'.
|
|
Computing hashes of 863 cells of `\spi_neuron_top'.
|
|
Finding duplicate cells in `\spi_neuron_top'.
|
|
Removed a total of 0 cells.
|
|
|
|
16.27. Executing OPT_DFF pass (perform DFF optimizations).
|
|
Setting constant 0-bit at position 21 on $auto$ff.cc:337:slice$3997 ($sdffe) from module spi_neuron_top.
|
|
|
|
16.28. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \spi_neuron_top..
|
|
|
|
16.29. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module spi_neuron_top.
|
|
|
|
16.30. Rerunning OPT passes. (Maybe there is more to do..)
|
|
|
|
16.31. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \spi_neuron_top..
|
|
Creating internal representation of mux trees.
|
|
Evaluating internal representation of mux trees.
|
|
Analyzing evaluation results.
|
|
Removed 0 multiplexer ports.
|
|
<suppressed ~443 debug messages>
|
|
|
|
16.32. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \spi_neuron_top.
|
|
Performed a total of 0 changes.
|
|
|
|
16.33. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\spi_neuron_top'.
|
|
Computing hashes of 863 cells of `\spi_neuron_top'.
|
|
Finding duplicate cells in `\spi_neuron_top'.
|
|
Removed a total of 0 cells.
|
|
|
|
16.34. Executing OPT_DFF pass (perform DFF optimizations).
|
|
|
|
16.35. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \spi_neuron_top..
|
|
|
|
16.36. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module spi_neuron_top.
|
|
|
|
16.37. Finished fast OPT passes. (There is nothing left to do.)
|
|
|
|
17. Executing MEMORY pass.
|
|
|
|
17.1. Executing OPT_MEM pass (optimize memories).
|
|
spi_neuron_top.$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$609: removing const-0 lane 6
|
|
spi_neuron_top.$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$609: removing const-0 lane 7
|
|
Performed a total of 1 transformations.
|
|
|
|
17.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations).
|
|
Performed a total of 0 transformations.
|
|
|
|
17.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths).
|
|
Analyzing spi_neuron_top.u_neuron_memory.y_reg write port 0.
|
|
Analyzing spi_neuron_top.u_neuron_memory.y_reg write port 1.
|
|
Analyzing spi_neuron_top.u_neuron_memory.x_mem write port 0.
|
|
Analyzing spi_neuron_top.u_neuron_memory.w_mem write port 0.
|
|
|
|
17.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs).
|
|
|
|
17.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd).
|
|
Checking read port `\u_neuron_memory.y_reg'[0] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_neuron_memory.x_mem'[0] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_neuron_memory.x_mem'[1] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_neuron_memory.x_mem'[2] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_neuron_memory.x_mem'[3] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_neuron_memory.x_mem'[4] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_neuron_memory.x_mem'[5] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_neuron_memory.x_mem'[6] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_neuron_memory.x_mem'[7] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_neuron_memory.x_mem'[8] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_neuron_memory.x_mem'[9] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_neuron_memory.x_mem'[10] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_neuron_memory.x_mem'[11] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_neuron_memory.x_mem'[12] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_neuron_memory.x_mem'[13] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_neuron_memory.x_mem'[14] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_neuron_memory.x_mem'[15] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_neuron_memory.x_mem'[16] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_neuron_memory.x_mem'[17] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_neuron_memory.x_mem'[18] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_neuron_memory.x_mem'[19] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_neuron_memory.x_mem'[20] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_neuron_memory.x_mem'[21] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_neuron_memory.x_mem'[22] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_neuron_memory.x_mem'[23] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_neuron_memory.x_mem'[24] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_neuron_memory.x_mem'[25] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_neuron_memory.x_mem'[26] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_neuron_memory.x_mem'[27] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_neuron_memory.x_mem'[28] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_neuron_memory.x_mem'[29] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_neuron_memory.x_mem'[30] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_neuron_memory.x_mem'[31] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_neuron_memory.w_mem'[0] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_neuron_memory.w_mem'[1] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_neuron_memory.w_mem'[2] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_neuron_memory.w_mem'[3] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_neuron_memory.w_mem'[4] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_neuron_memory.w_mem'[5] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_neuron_memory.w_mem'[6] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_neuron_memory.w_mem'[7] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_neuron_memory.w_mem'[8] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_neuron_memory.w_mem'[9] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_neuron_memory.w_mem'[10] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_neuron_memory.w_mem'[11] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_neuron_memory.w_mem'[12] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_neuron_memory.w_mem'[13] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_neuron_memory.w_mem'[14] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_neuron_memory.w_mem'[15] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_neuron_memory.w_mem'[16] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_neuron_memory.w_mem'[17] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_neuron_memory.w_mem'[18] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_neuron_memory.w_mem'[19] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_neuron_memory.w_mem'[20] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_neuron_memory.w_mem'[21] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_neuron_memory.w_mem'[22] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_neuron_memory.w_mem'[23] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_neuron_memory.w_mem'[24] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_neuron_memory.w_mem'[25] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_neuron_memory.w_mem'[26] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_neuron_memory.w_mem'[27] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_neuron_memory.w_mem'[28] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_neuron_memory.w_mem'[29] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_neuron_memory.w_mem'[30] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_neuron_memory.w_mem'[31] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$609'[0] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port address `\u_neuron_memory.y_reg'[0] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_neuron_memory.x_mem'[0] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_neuron_memory.x_mem'[1] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_neuron_memory.x_mem'[2] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_neuron_memory.x_mem'[3] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_neuron_memory.x_mem'[4] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_neuron_memory.x_mem'[5] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_neuron_memory.x_mem'[6] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_neuron_memory.x_mem'[7] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_neuron_memory.x_mem'[8] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_neuron_memory.x_mem'[9] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_neuron_memory.x_mem'[10] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_neuron_memory.x_mem'[11] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_neuron_memory.x_mem'[12] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_neuron_memory.x_mem'[13] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_neuron_memory.x_mem'[14] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_neuron_memory.x_mem'[15] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_neuron_memory.x_mem'[16] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_neuron_memory.x_mem'[17] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_neuron_memory.x_mem'[18] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_neuron_memory.x_mem'[19] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_neuron_memory.x_mem'[20] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_neuron_memory.x_mem'[21] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_neuron_memory.x_mem'[22] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_neuron_memory.x_mem'[23] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_neuron_memory.x_mem'[24] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_neuron_memory.x_mem'[25] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_neuron_memory.x_mem'[26] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_neuron_memory.x_mem'[27] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_neuron_memory.x_mem'[28] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_neuron_memory.x_mem'[29] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_neuron_memory.x_mem'[30] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_neuron_memory.x_mem'[31] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_neuron_memory.w_mem'[0] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_neuron_memory.w_mem'[1] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_neuron_memory.w_mem'[2] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_neuron_memory.w_mem'[3] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_neuron_memory.w_mem'[4] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_neuron_memory.w_mem'[5] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_neuron_memory.w_mem'[6] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_neuron_memory.w_mem'[7] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_neuron_memory.w_mem'[8] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_neuron_memory.w_mem'[9] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_neuron_memory.w_mem'[10] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_neuron_memory.w_mem'[11] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_neuron_memory.w_mem'[12] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_neuron_memory.w_mem'[13] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_neuron_memory.w_mem'[14] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_neuron_memory.w_mem'[15] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_neuron_memory.w_mem'[16] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_neuron_memory.w_mem'[17] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_neuron_memory.w_mem'[18] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_neuron_memory.w_mem'[19] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_neuron_memory.w_mem'[20] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_neuron_memory.w_mem'[21] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_neuron_memory.w_mem'[22] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_neuron_memory.w_mem'[23] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_neuron_memory.w_mem'[24] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_neuron_memory.w_mem'[25] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_neuron_memory.w_mem'[26] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_neuron_memory.w_mem'[27] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_neuron_memory.w_mem'[28] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_neuron_memory.w_mem'[29] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_neuron_memory.w_mem'[30] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_neuron_memory.w_mem'[31] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$609'[0] in module `\spi_neuron_top': merged address FF to cell.
|
|
|
|
17.6. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \spi_neuron_top..
|
|
|
|
17.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells).
|
|
Consolidating write ports of memory spi_neuron_top.u_neuron_memory.y_reg by address:
|
|
Consolidating read ports of memory spi_neuron_top.u_neuron_memory.x_mem by address:
|
|
Merging ports 0, 7 (address 12).
|
|
Merging ports 0, 9 (address 12).
|
|
Merging ports 0, 16 (address 12).
|
|
Merging ports 0, 20 (address 12).
|
|
Merging ports 0, 28 (address 8).
|
|
Merging ports 0, 31 (address 8).
|
|
Merging ports 2, 4 (address 18).
|
|
Merging ports 2, 8 (address 18).
|
|
Merging ports 2, 11 (address 16).
|
|
Merging ports 2, 21 (address 16).
|
|
Merging ports 2, 22 (address 16).
|
|
Merging ports 2, 23 (address 16).
|
|
Merging ports 2, 24 (address 16).
|
|
Merging ports 2, 25 (address 16).
|
|
Merging ports 2, 26 (address 16).
|
|
Merging ports 2, 27 (address 16).
|
|
Merging ports 2, 29 (address 16).
|
|
Merging ports 2, 30 (address 16).
|
|
Merging ports 3, 5 (address 22).
|
|
Merging ports 3, 6 (address 22).
|
|
Merging ports 10, 12 (address 0).
|
|
Merging ports 10, 13 (address 0).
|
|
Merging ports 10, 14 (address 0).
|
|
Merging ports 10, 15 (address 0).
|
|
Merging ports 10, 17 (address 0).
|
|
Merging ports 10, 18 (address 0).
|
|
Merging ports 10, 19 (address 0).
|
|
Consolidating read ports of memory spi_neuron_top.u_neuron_memory.x_mem by address:
|
|
Merging ports 0, 1 (address 8).
|
|
Merging ports 0, 2 (address 8).
|
|
Merging ports 0, 3 (address 0).
|
|
Merging ports 0, 4 (address 0).
|
|
Consolidating read ports of memory spi_neuron_top.u_neuron_memory.w_mem by address:
|
|
Merging ports 0, 29 (address 8).
|
|
Merging ports 0, 31 (address 8).
|
|
Merging ports 1, 8 (address 12).
|
|
Merging ports 1, 10 (address 12).
|
|
Merging ports 1, 18 (address 12).
|
|
Merging ports 2, 4 (address 18).
|
|
Merging ports 2, 7 (address 18).
|
|
Merging ports 2, 9 (address 16).
|
|
Merging ports 2, 19 (address 16).
|
|
Merging ports 2, 21 (address 16).
|
|
Merging ports 2, 22 (address 16).
|
|
Merging ports 2, 23 (address 16).
|
|
Merging ports 2, 24 (address 16).
|
|
Merging ports 2, 25 (address 16).
|
|
Merging ports 2, 26 (address 16).
|
|
Merging ports 2, 27 (address 16).
|
|
Merging ports 2, 28 (address 16).
|
|
Merging ports 2, 30 (address 16).
|
|
Merging ports 11, 12 (address 0).
|
|
Merging ports 11, 13 (address 0).
|
|
Merging ports 11, 14 (address 0).
|
|
Merging ports 11, 15 (address 0).
|
|
Merging ports 11, 16 (address 0).
|
|
Merging ports 11, 17 (address 0).
|
|
Merging ports 11, 20 (address 0).
|
|
Consolidating read ports of memory spi_neuron_top.u_neuron_memory.w_mem by address:
|
|
Merging ports 0, 1 (address 8).
|
|
Merging ports 0, 2 (address 8).
|
|
Merging ports 0, 3 (address 0).
|
|
Merging ports 0, 4 (address 0).
|
|
Merging ports 0, 5 (address 0).
|
|
Merging ports 0, 6 (address 0).
|
|
Consolidating write ports of memory spi_neuron_top.u_neuron_memory.y_reg using sat-based resource sharing:
|
|
Checking group clocked with posedge \clk, width 8: ports 0, 1.
|
|
Common input cone for all EN signals: 6 cells.
|
|
Size of unconstrained SAT problem: 53 variables, 124 clauses
|
|
Merging port 1 into port 0.
|
|
|
|
17.8. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide).
|
|
Performed a total of 0 transformations.
|
|
|
|
17.9. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \spi_neuron_top..
|
|
Removed 0 unused cells and 62 unused wires.
|
|
<suppressed ~1 debug messages>
|
|
|
|
17.10. Executing MEMORY_COLLECT pass (generating $mem cells).
|
|
|
|
17.11. Executing MEMORY_MAP pass (converting memories to logic and flip-flops).
|
|
Mapping memory \u_neuron_memory.y_reg in module \spi_neuron_top:
|
|
created 1 $dff cells and 0 static cells of width 8.
|
|
read interface: 0 $dff and 0 $mux cells.
|
|
write interface: 1 write mux blocks.
|
|
Mapping memory $flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$609 in module \spi_neuron_top:
|
|
created 8 $dff cells and 0 static cells of width 6.
|
|
Extracted data FF from read port 0 of spi_neuron_top.$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$609: $$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$609$rdreg[0]
|
|
read interface: 1 $dff and 7 $mux cells.
|
|
write interface: 0 write mux blocks.
|
|
Mapping memory \u_neuron_memory.x_mem in module \spi_neuron_top:
|
|
created 32 $dff cells and 0 static cells of width 8.
|
|
read interface: 0 $dff and 0 $mux cells.
|
|
write interface: 32 write mux blocks.
|
|
Mapping memory \u_neuron_memory.w_mem in module \spi_neuron_top:
|
|
created 32 $dff cells and 0 static cells of width 8.
|
|
read interface: 0 $dff and 0 $mux cells.
|
|
write interface: 32 write mux blocks.
|
|
|
|
18. Executing OPT pass (performing simple optimizations).
|
|
|
|
18.1. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module spi_neuron_top.
|
|
<suppressed ~193 debug messages>
|
|
|
|
18.2. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\spi_neuron_top'.
|
|
Computing hashes of 1190 cells of `\spi_neuron_top'.
|
|
Finding duplicate cells in `\spi_neuron_top'.
|
|
Removed a total of 0 cells.
|
|
|
|
18.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \spi_neuron_top..
|
|
Creating internal representation of mux trees.
|
|
Evaluating internal representation of mux trees.
|
|
Replacing known input bits on port B of cell $auto$memory_share.cc:454:consolidate_wr_using_sat$4323: $flatten\u_neuron_memory.$0$memwr$\y_reg$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:426$373_EN[7:0]$385 [0] -> 1'1
|
|
Analyzing evaluation results.
|
|
Removed 0 multiplexer ports.
|
|
<suppressed ~777 debug messages>
|
|
|
|
18.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \spi_neuron_top.
|
|
Performed a total of 0 changes.
|
|
|
|
18.5. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\spi_neuron_top'.
|
|
Computing hashes of 1190 cells of `\spi_neuron_top'.
|
|
Finding duplicate cells in `\spi_neuron_top'.
|
|
Removed a total of 0 cells.
|
|
|
|
18.6. Executing OPT_DFF pass (perform DFF optimizations).
|
|
|
|
18.7. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \spi_neuron_top..
|
|
Removed 0 unused cells and 212 unused wires.
|
|
<suppressed ~1 debug messages>
|
|
|
|
18.8. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module spi_neuron_top.
|
|
|
|
18.9. Rerunning OPT passes. (Maybe there is more to do..)
|
|
|
|
18.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \spi_neuron_top..
|
|
Creating internal representation of mux trees.
|
|
Evaluating internal representation of mux trees.
|
|
Analyzing evaluation results.
|
|
Removed 0 multiplexer ports.
|
|
<suppressed ~777 debug messages>
|
|
|
|
18.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \spi_neuron_top.
|
|
Performed a total of 0 changes.
|
|
|
|
18.12. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\spi_neuron_top'.
|
|
Computing hashes of 1190 cells of `\spi_neuron_top'.
|
|
Finding duplicate cells in `\spi_neuron_top'.
|
|
Removed a total of 0 cells.
|
|
|
|
18.13. Executing OPT_DFF pass (perform DFF optimizations).
|
|
Adding EN signal on $memory\u_neuron_memory.y_reg[0]$4324 ($dff) from module spi_neuron_top (D = $auto$rtlil.cc:3402:Mux$4321, Q = \u_neuron_memory.y_reg[0]).
|
|
Adding SRST signal on $auto$ff.cc:337:slice$5411 ($dffe) from module spi_neuron_top (D = $flatten\u_neuron_memory.$0$memwr$\y_reg$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:426$373_DATA[7:0]$384, Q = \u_neuron_memory.y_reg[0], rval = 8'00000000).
|
|
Adding EN signal on $memory\u_neuron_memory.x_mem[0]$4477 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:334$371_DATA[7:0]$378, Q = \u_neuron_memory.x_mem[0]).
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|
Adding EN signal on $memory\u_neuron_memory.x_mem[1]$4479 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:334$371_DATA[7:0]$378, Q = \u_neuron_memory.x_mem[1]).
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|
Adding EN signal on $memory\u_neuron_memory.x_mem[2]$4481 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:334$371_DATA[7:0]$378, Q = \u_neuron_memory.x_mem[2]).
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|
Adding EN signal on $memory\u_neuron_memory.x_mem[3]$4483 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:334$371_DATA[7:0]$378, Q = \u_neuron_memory.x_mem[3]).
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|
Adding EN signal on $memory\u_neuron_memory.x_mem[4]$4485 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:334$371_DATA[7:0]$378, Q = \u_neuron_memory.x_mem[4]).
|
|
Adding EN signal on $memory\u_neuron_memory.x_mem[5]$4487 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:334$371_DATA[7:0]$378, Q = \u_neuron_memory.x_mem[5]).
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|
Adding EN signal on $memory\u_neuron_memory.x_mem[6]$4489 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:334$371_DATA[7:0]$378, Q = \u_neuron_memory.x_mem[6]).
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|
Adding EN signal on $memory\u_neuron_memory.x_mem[7]$4491 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:334$371_DATA[7:0]$378, Q = \u_neuron_memory.x_mem[7]).
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|
Adding EN signal on $memory\u_neuron_memory.x_mem[8]$4493 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:334$371_DATA[7:0]$378, Q = \u_neuron_memory.x_mem[8]).
|
|
Adding EN signal on $memory\u_neuron_memory.x_mem[9]$4495 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:334$371_DATA[7:0]$378, Q = \u_neuron_memory.x_mem[9]).
|
|
Adding EN signal on $memory\u_neuron_memory.x_mem[10]$4497 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:334$371_DATA[7:0]$378, Q = \u_neuron_memory.x_mem[10]).
|
|
Adding EN signal on $memory\u_neuron_memory.x_mem[11]$4499 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:334$371_DATA[7:0]$378, Q = \u_neuron_memory.x_mem[11]).
|
|
Adding EN signal on $memory\u_neuron_memory.x_mem[12]$4501 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:334$371_DATA[7:0]$378, Q = \u_neuron_memory.x_mem[12]).
|
|
Adding EN signal on $memory\u_neuron_memory.x_mem[13]$4503 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:334$371_DATA[7:0]$378, Q = \u_neuron_memory.x_mem[13]).
|
|
Adding EN signal on $memory\u_neuron_memory.x_mem[14]$4505 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:334$371_DATA[7:0]$378, Q = \u_neuron_memory.x_mem[14]).
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|
Adding EN signal on $memory\u_neuron_memory.x_mem[15]$4507 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:334$371_DATA[7:0]$378, Q = \u_neuron_memory.x_mem[15]).
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|
Adding EN signal on $memory\u_neuron_memory.x_mem[16]$4509 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:334$371_DATA[7:0]$378, Q = \u_neuron_memory.x_mem[16]).
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|
Adding EN signal on $memory\u_neuron_memory.x_mem[17]$4511 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:334$371_DATA[7:0]$378, Q = \u_neuron_memory.x_mem[17]).
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|
Adding EN signal on $memory\u_neuron_memory.x_mem[18]$4513 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:334$371_DATA[7:0]$378, Q = \u_neuron_memory.x_mem[18]).
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Adding EN signal on $memory\u_neuron_memory.x_mem[19]$4515 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:334$371_DATA[7:0]$378, Q = \u_neuron_memory.x_mem[19]).
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Adding EN signal on $memory\u_neuron_memory.x_mem[20]$4517 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:334$371_DATA[7:0]$378, Q = \u_neuron_memory.x_mem[20]).
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|
Adding EN signal on $memory\u_neuron_memory.x_mem[21]$4519 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:334$371_DATA[7:0]$378, Q = \u_neuron_memory.x_mem[21]).
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Adding EN signal on $memory\u_neuron_memory.x_mem[22]$4521 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:334$371_DATA[7:0]$378, Q = \u_neuron_memory.x_mem[22]).
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Adding EN signal on $memory\u_neuron_memory.x_mem[23]$4523 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:334$371_DATA[7:0]$378, Q = \u_neuron_memory.x_mem[23]).
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|
Adding EN signal on $memory\u_neuron_memory.x_mem[24]$4525 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:334$371_DATA[7:0]$378, Q = \u_neuron_memory.x_mem[24]).
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Adding EN signal on $memory\u_neuron_memory.x_mem[25]$4527 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:334$371_DATA[7:0]$378, Q = \u_neuron_memory.x_mem[25]).
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|
Adding EN signal on $memory\u_neuron_memory.x_mem[26]$4529 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:334$371_DATA[7:0]$378, Q = \u_neuron_memory.x_mem[26]).
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|
Adding EN signal on $memory\u_neuron_memory.x_mem[27]$4531 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:334$371_DATA[7:0]$378, Q = \u_neuron_memory.x_mem[27]).
|
|
Adding EN signal on $memory\u_neuron_memory.x_mem[28]$4533 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:334$371_DATA[7:0]$378, Q = \u_neuron_memory.x_mem[28]).
|
|
Adding EN signal on $memory\u_neuron_memory.x_mem[29]$4535 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:334$371_DATA[7:0]$378, Q = \u_neuron_memory.x_mem[29]).
|
|
Adding EN signal on $memory\u_neuron_memory.x_mem[30]$4537 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:334$371_DATA[7:0]$378, Q = \u_neuron_memory.x_mem[30]).
|
|
Adding EN signal on $memory\u_neuron_memory.x_mem[31]$4539 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:334$371_DATA[7:0]$378, Q = \u_neuron_memory.x_mem[31]).
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|
Adding EN signal on $memory\u_neuron_memory.w_mem[0]$4949 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:367$372_DATA[7:0]$381, Q = \u_neuron_memory.w_mem[0]).
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|
Adding EN signal on $memory\u_neuron_memory.w_mem[1]$4951 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:367$372_DATA[7:0]$381, Q = \u_neuron_memory.w_mem[1]).
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|
Adding EN signal on $memory\u_neuron_memory.w_mem[2]$4953 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:367$372_DATA[7:0]$381, Q = \u_neuron_memory.w_mem[2]).
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|
Adding EN signal on $memory\u_neuron_memory.w_mem[3]$4955 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:367$372_DATA[7:0]$381, Q = \u_neuron_memory.w_mem[3]).
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|
Adding EN signal on $memory\u_neuron_memory.w_mem[4]$4957 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:367$372_DATA[7:0]$381, Q = \u_neuron_memory.w_mem[4]).
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|
Adding EN signal on $memory\u_neuron_memory.w_mem[5]$4959 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:367$372_DATA[7:0]$381, Q = \u_neuron_memory.w_mem[5]).
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Adding EN signal on $memory\u_neuron_memory.w_mem[6]$4961 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:367$372_DATA[7:0]$381, Q = \u_neuron_memory.w_mem[6]).
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Adding EN signal on $memory\u_neuron_memory.w_mem[7]$4963 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:367$372_DATA[7:0]$381, Q = \u_neuron_memory.w_mem[7]).
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Adding EN signal on $memory\u_neuron_memory.w_mem[8]$4965 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:367$372_DATA[7:0]$381, Q = \u_neuron_memory.w_mem[8]).
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Adding EN signal on $memory\u_neuron_memory.w_mem[9]$4967 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:367$372_DATA[7:0]$381, Q = \u_neuron_memory.w_mem[9]).
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Adding EN signal on $memory\u_neuron_memory.w_mem[10]$4969 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:367$372_DATA[7:0]$381, Q = \u_neuron_memory.w_mem[10]).
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Adding EN signal on $memory\u_neuron_memory.w_mem[11]$4971 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:367$372_DATA[7:0]$381, Q = \u_neuron_memory.w_mem[11]).
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Adding EN signal on $memory\u_neuron_memory.w_mem[12]$4973 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:367$372_DATA[7:0]$381, Q = \u_neuron_memory.w_mem[12]).
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Adding EN signal on $memory\u_neuron_memory.w_mem[13]$4975 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:367$372_DATA[7:0]$381, Q = \u_neuron_memory.w_mem[13]).
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Adding EN signal on $memory\u_neuron_memory.w_mem[14]$4977 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:367$372_DATA[7:0]$381, Q = \u_neuron_memory.w_mem[14]).
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Adding EN signal on $memory\u_neuron_memory.w_mem[15]$4979 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:367$372_DATA[7:0]$381, Q = \u_neuron_memory.w_mem[15]).
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Adding EN signal on $memory\u_neuron_memory.w_mem[16]$4981 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:367$372_DATA[7:0]$381, Q = \u_neuron_memory.w_mem[16]).
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Adding EN signal on $memory\u_neuron_memory.w_mem[17]$4983 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:367$372_DATA[7:0]$381, Q = \u_neuron_memory.w_mem[17]).
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Adding EN signal on $memory\u_neuron_memory.w_mem[18]$4985 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:367$372_DATA[7:0]$381, Q = \u_neuron_memory.w_mem[18]).
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Adding EN signal on $memory\u_neuron_memory.w_mem[19]$4987 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:367$372_DATA[7:0]$381, Q = \u_neuron_memory.w_mem[19]).
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Adding EN signal on $memory\u_neuron_memory.w_mem[20]$4989 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:367$372_DATA[7:0]$381, Q = \u_neuron_memory.w_mem[20]).
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Adding EN signal on $memory\u_neuron_memory.w_mem[21]$4991 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:367$372_DATA[7:0]$381, Q = \u_neuron_memory.w_mem[21]).
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Adding EN signal on $memory\u_neuron_memory.w_mem[22]$4993 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:367$372_DATA[7:0]$381, Q = \u_neuron_memory.w_mem[22]).
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Adding EN signal on $memory\u_neuron_memory.w_mem[23]$4995 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:367$372_DATA[7:0]$381, Q = \u_neuron_memory.w_mem[23]).
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Adding EN signal on $memory\u_neuron_memory.w_mem[24]$4997 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:367$372_DATA[7:0]$381, Q = \u_neuron_memory.w_mem[24]).
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Adding EN signal on $memory\u_neuron_memory.w_mem[25]$4999 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:367$372_DATA[7:0]$381, Q = \u_neuron_memory.w_mem[25]).
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Adding EN signal on $memory\u_neuron_memory.w_mem[26]$5001 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:367$372_DATA[7:0]$381, Q = \u_neuron_memory.w_mem[26]).
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Adding EN signal on $memory\u_neuron_memory.w_mem[27]$5003 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:367$372_DATA[7:0]$381, Q = \u_neuron_memory.w_mem[27]).
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Adding EN signal on $memory\u_neuron_memory.w_mem[28]$5005 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:367$372_DATA[7:0]$381, Q = \u_neuron_memory.w_mem[28]).
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Adding EN signal on $memory\u_neuron_memory.w_mem[29]$5007 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:367$372_DATA[7:0]$381, Q = \u_neuron_memory.w_mem[29]).
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Adding EN signal on $memory\u_neuron_memory.w_mem[30]$5009 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:367$372_DATA[7:0]$381, Q = \u_neuron_memory.w_mem[30]).
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Adding EN signal on $memory\u_neuron_memory.w_mem[31]$5011 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:367$372_DATA[7:0]$381, Q = \u_neuron_memory.w_mem[31]).
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18.14. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \spi_neuron_top..
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|
Removed 66 unused cells and 66 unused wires.
|
|
<suppressed ~67 debug messages>
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18.15. Executing OPT_EXPR pass (perform const folding).
|
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Optimizing module spi_neuron_top.
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18.16. Rerunning OPT passes. (Maybe there is more to do..)
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18.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \spi_neuron_top..
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Creating internal representation of mux trees.
|
|
Evaluating internal representation of mux trees.
|
|
Analyzing evaluation results.
|
|
Removed 0 multiplexer ports.
|
|
<suppressed ~455 debug messages>
|
|
|
|
18.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \spi_neuron_top.
|
|
Performed a total of 0 changes.
|
|
|
|
18.19. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\spi_neuron_top'.
|
|
Computing hashes of 1124 cells of `\spi_neuron_top'.
|
|
Finding duplicate cells in `\spi_neuron_top'.
|
|
Removed a total of 0 cells.
|
|
|
|
18.20. Executing OPT_DFF pass (perform DFF optimizations).
|
|
|
|
18.21. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \spi_neuron_top..
|
|
|
|
18.22. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module spi_neuron_top.
|
|
|
|
18.23. Finished fast OPT passes. (There is nothing left to do.)
|
|
|
|
19. Executing TECHMAP pass (map to technology primitives).
|
|
|
|
19.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/techmap.v
|
|
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/techmap.v' to AST representation.
|
|
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
|
|
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
|
|
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
|
|
Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
|
|
Generating RTLIL representation for module `\_90_simplemap_various'.
|
|
Generating RTLIL representation for module `\_90_simplemap_registers'.
|
|
Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
|
|
Generating RTLIL representation for module `\_90_shift_shiftx'.
|
|
Generating RTLIL representation for module `\_90_fa'.
|
|
Generating RTLIL representation for module `\_90_lcu_brent_kung'.
|
|
Generating RTLIL representation for module `\_90_alu'.
|
|
Generating RTLIL representation for module `\_90_macc'.
|
|
Generating RTLIL representation for module `\_90_alumacc'.
|
|
Generating RTLIL representation for module `$__div_mod_u'.
|
|
Generating RTLIL representation for module `$__div_mod_trunc'.
|
|
Generating RTLIL representation for module `\_90_div'.
|
|
Generating RTLIL representation for module `\_90_mod'.
|
|
Generating RTLIL representation for module `$__div_mod_floor'.
|
|
Generating RTLIL representation for module `\_90_divfloor'.
|
|
Generating RTLIL representation for module `\_90_modfloor'.
|
|
Generating RTLIL representation for module `\_90_pow'.
|
|
Generating RTLIL representation for module `\_90_demux'.
|
|
Generating RTLIL representation for module `\_90_lut'.
|
|
Generating RTLIL representation for module `$connect'.
|
|
Generating RTLIL representation for module `$input_port'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
19.2. Continuing TECHMAP pass.
|
|
Using extmapper simplemap for cells of type $dffe.
|
|
Using extmapper simplemap for cells of type $sdffce.
|
|
Using extmapper simplemap for cells of type $and.
|
|
Using extmapper simplemap for cells of type $not.
|
|
Using extmapper simplemap for cells of type $mux.
|
|
Using extmapper simplemap for cells of type $sdffe.
|
|
Using extmapper simplemap for cells of type $reduce_and.
|
|
Using extmapper simplemap for cells of type $ne.
|
|
Using extmapper simplemap for cells of type $reduce_or.
|
|
Using extmapper simplemap for cells of type $sdff.
|
|
Using extmapper simplemap for cells of type $reduce_bool.
|
|
Using extmapper simplemap for cells of type $or.
|
|
Using extmapper simplemap for cells of type $logic_not.
|
|
Running "alumacc" on wrapper $extern:wrap:$add:Y_WIDTH=3:B_WIDTH=3:A_WIDTH=3:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47.
|
|
Using template $extern:wrap:$add:Y_WIDTH=3:B_WIDTH=3:A_WIDTH=3:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$add:Y_WIDTH=3:B_WIDTH=3:A_WIDTH=3:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47.
|
|
Using extmapper simplemap for cells of type $eq.
|
|
Using extmapper simplemap for cells of type $pmux.
|
|
Running "alumacc" on wrapper $extern:wrap:$add:Y_WIDTH=4:B_WIDTH=4:A_WIDTH=4:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47.
|
|
Using template $extern:wrap:$add:Y_WIDTH=4:B_WIDTH=4:A_WIDTH=4:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$add:Y_WIDTH=4:B_WIDTH=4:A_WIDTH=4:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47.
|
|
Running "alumacc" on wrapper $extern:wrap:$sub:Y_WIDTH=4:B_WIDTH=4:A_WIDTH=4:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47.
|
|
Using template $extern:wrap:$sub:Y_WIDTH=4:B_WIDTH=4:A_WIDTH=4:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$sub:Y_WIDTH=4:B_WIDTH=4:A_WIDTH=4:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47.
|
|
Running "alumacc" on wrapper $extern:wrap:$sub:Y_WIDTH=16:B_WIDTH=16:A_WIDTH=16:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47.
|
|
Using template $extern:wrap:$sub:Y_WIDTH=16:B_WIDTH=16:A_WIDTH=16:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$sub:Y_WIDTH=16:B_WIDTH=16:A_WIDTH=16:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47.
|
|
Running "alumacc" on wrapper $extern:wrap:$add:Y_WIDTH=22:B_WIDTH=1:A_WIDTH=22:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47.
|
|
Using template $extern:wrap:$add:Y_WIDTH=22:B_WIDTH=1:A_WIDTH=22:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$add:Y_WIDTH=22:B_WIDTH=1:A_WIDTH=22:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47.
|
|
Running "alumacc" on wrapper $extern:wrap:$add:Y_WIDTH=2:B_WIDTH=2:A_WIDTH=2:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47.
|
|
Using template $extern:wrap:$add:Y_WIDTH=2:B_WIDTH=2:A_WIDTH=2:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$add:Y_WIDTH=2:B_WIDTH=2:A_WIDTH=2:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47.
|
|
Using template $paramod$constmap:72feeb675a13be11da2f7fd881bfaac01d417b2e$paramod$f799933c7a2c73f0171e55c59a9c12bb6f45de64\_90_shift_shiftx for cells of type $shiftx.
|
|
Running "alumacc" on wrapper $extern:wrap:$lt:Y_WIDTH=1:B_WIDTH=32:A_WIDTH=4:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47.
|
|
Using template $extern:wrap:$lt:Y_WIDTH=1:B_WIDTH=32:A_WIDTH=4:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$lt:Y_WIDTH=1:B_WIDTH=32:A_WIDTH=4:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47.
|
|
Using extmapper simplemap for cells of type $logic_and.
|
|
Running "alumacc" on wrapper $extern:wrap:$add:Y_WIDTH=1:B_WIDTH=1:A_WIDTH=1:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47.
|
|
Using template $extern:wrap:$add:Y_WIDTH=1:B_WIDTH=1:A_WIDTH=1:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$add:Y_WIDTH=1:B_WIDTH=1:A_WIDTH=1:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47.
|
|
Running "alumacc" on wrapper $extern:wrap:$add:Y_WIDTH=22:B_WIDTH=22:A_WIDTH=22:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47.
|
|
Using template $extern:wrap:$add:Y_WIDTH=22:B_WIDTH=22:A_WIDTH=22:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$add:Y_WIDTH=22:B_WIDTH=22:A_WIDTH=22:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47.
|
|
Running "alumacc" on wrapper $extern:wrap:$add:Y_WIDTH=8:B_WIDTH=8:A_WIDTH=8:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47.
|
|
Using template $extern:wrap:$add:Y_WIDTH=8:B_WIDTH=8:A_WIDTH=8:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$add:Y_WIDTH=8:B_WIDTH=8:A_WIDTH=8:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47.
|
|
Running "alumacc" on wrapper $extern:wrap:$sub:Y_WIDTH=8:B_WIDTH=8:A_WIDTH=8:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47.
|
|
Using template $extern:wrap:$sub:Y_WIDTH=8:B_WIDTH=8:A_WIDTH=8:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$sub:Y_WIDTH=8:B_WIDTH=8:A_WIDTH=8:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47.
|
|
Using template $paramod$constmap:f1372740d55e3571b0e146ea54d721065f423f86$paramod$796607324003502d2965a80ed5fa389e4a388b81\_90_shift_shiftx for cells of type $shiftx.
|
|
Running "alumacc" on wrapper $extern:wrap:$add:Y_WIDTH=22:B_WIDTH=3:A_WIDTH=22:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47.
|
|
Using template $extern:wrap:$add:Y_WIDTH=22:B_WIDTH=3:A_WIDTH=22:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$add:Y_WIDTH=22:B_WIDTH=3:A_WIDTH=22:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47.
|
|
Using template $paramod$constmap:5c4c0ffeacdabe44d1a36a0cc4292e941b624a45$paramod$54aca743943b6266e5e4a14108590593a4f4405e\_90_shift_shiftx for cells of type $shiftx.
|
|
Running "alumacc" on wrapper $extern:wrap:$add:Y_WIDTH=32:B_WIDTH=32:A_WIDTH=32:B_SIGNED=1:A_SIGNED=1:394426c56d1a028ba8fdd5469b163e04011def47.
|
|
Using template $extern:wrap:$add:Y_WIDTH=32:B_WIDTH=32:A_WIDTH=32:B_SIGNED=1:A_SIGNED=1:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$add:Y_WIDTH=32:B_WIDTH=32:A_WIDTH=32:B_SIGNED=1:A_SIGNED=1:394426c56d1a028ba8fdd5469b163e04011def47.
|
|
Running "alumacc" on wrapper $extern:wrap:$le:Y_WIDTH=1:B_WIDTH=32:A_WIDTH=32:B_SIGNED=1:A_SIGNED=1:394426c56d1a028ba8fdd5469b163e04011def47.
|
|
Using template $extern:wrap:$le:Y_WIDTH=1:B_WIDTH=32:A_WIDTH=32:B_SIGNED=1:A_SIGNED=1:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$le:Y_WIDTH=1:B_WIDTH=32:A_WIDTH=32:B_SIGNED=1:A_SIGNED=1:394426c56d1a028ba8fdd5469b163e04011def47.
|
|
Running "alumacc" on wrapper $extern:wrap:$gt:Y_WIDTH=1:B_WIDTH=32:A_WIDTH=32:B_SIGNED=1:A_SIGNED=1:394426c56d1a028ba8fdd5469b163e04011def47.
|
|
Using template $extern:wrap:$gt:Y_WIDTH=1:B_WIDTH=32:A_WIDTH=32:B_SIGNED=1:A_SIGNED=1:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$gt:Y_WIDTH=1:B_WIDTH=32:A_WIDTH=32:B_SIGNED=1:A_SIGNED=1:394426c56d1a028ba8fdd5469b163e04011def47.
|
|
Running "alumacc" on wrapper $extern:wrap:$add:Y_WIDTH=2:B_WIDTH=1:A_WIDTH=2:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47.
|
|
Using template $extern:wrap:$add:Y_WIDTH=2:B_WIDTH=1:A_WIDTH=2:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$add:Y_WIDTH=2:B_WIDTH=1:A_WIDTH=2:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47.
|
|
Running "alumacc" on wrapper $extern:wrap:$mul:Y_WIDTH=16:B_WIDTH=8:A_WIDTH=8:B_SIGNED=1:A_SIGNED=1:394426c56d1a028ba8fdd5469b163e04011def47.
|
|
Using template $extern:wrap:$mul:Y_WIDTH=16:B_WIDTH=8:A_WIDTH=8:B_SIGNED=1:A_SIGNED=1:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$mul:Y_WIDTH=16:B_WIDTH=8:A_WIDTH=8:B_SIGNED=1:A_SIGNED=1:394426c56d1a028ba8fdd5469b163e04011def47.
|
|
Running "alumacc" on wrapper $extern:wrap:$add:Y_WIDTH=32:B_WIDTH=32:A_WIDTH=22:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47.
|
|
Using template $extern:wrap:$add:Y_WIDTH=32:B_WIDTH=32:A_WIDTH=22:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$add:Y_WIDTH=32:B_WIDTH=32:A_WIDTH=22:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47.
|
|
Running "alumacc" on wrapper $extern:wrap:$add:Y_WIDTH=22:B_WIDTH=6:A_WIDTH=22:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47.
|
|
Using template $extern:wrap:$add:Y_WIDTH=22:B_WIDTH=6:A_WIDTH=22:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$add:Y_WIDTH=22:B_WIDTH=6:A_WIDTH=22:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47.
|
|
Running "alumacc" on wrapper $extern:wrap:$add:Y_WIDTH=6:B_WIDTH=1:A_WIDTH=6:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47.
|
|
Using template $extern:wrap:$add:Y_WIDTH=6:B_WIDTH=1:A_WIDTH=6:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$add:Y_WIDTH=6:B_WIDTH=1:A_WIDTH=6:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47.
|
|
Using extmapper simplemap for cells of type $dff.
|
|
Running "alumacc" on wrapper $extern:wrap:$add:Y_WIDTH=14:B_WIDTH=1:A_WIDTH=14:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47.
|
|
Using template $extern:wrap:$add:Y_WIDTH=14:B_WIDTH=1:A_WIDTH=14:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$add:Y_WIDTH=14:B_WIDTH=1:A_WIDTH=14:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47.
|
|
Using template $paramod$713617589782cfade849bb573b5c36106c4b708f\_90_alu for cells of type $alu.
|
|
Using template $paramod$32efbfac1c4dc57230cf86180788fdfd12e3b511\_90_alu for cells of type $alu.
|
|
Using template $paramod$6cf9020614225d7c3916d5c4139d794ea8448572\_90_alu for cells of type $alu.
|
|
Using template $paramod$080e6a70eb8bfa1ccf22d9718e795074645029a4\_90_alu for cells of type $alu.
|
|
Using template $paramod$fc972a7a46956c1788f3cb5257b53c8f1df2d0cc\_90_alu for cells of type $alu.
|
|
Using template $paramod$7a00885c4503e0d6395d87bcf5ed878899b94083\_90_alu for cells of type $alu.
|
|
Using extmapper maccmap for cells of type $macc_v2.
|
|
add \u_neuron_memory.u_neuron.u_mac8.x_bus [7:0] * \u_neuron_memory.u_neuron.u_mac8.w_bus [7:0] (8x8 bits, signed)
|
|
add \u_neuron_memory.u_neuron.u_mac8.x_bus [15:8] * \u_neuron_memory.u_neuron.u_mac8.w_bus [15:8] (8x8 bits, signed)
|
|
add \u_neuron_memory.u_neuron.u_mac8.x_bus [23:16] * \u_neuron_memory.u_neuron.u_mac8.w_bus [23:16] (8x8 bits, signed)
|
|
add \u_neuron_memory.u_neuron.u_mac8.x_bus [31:24] * \u_neuron_memory.u_neuron.u_mac8.w_bus [31:24] (8x8 bits, signed)
|
|
add \u_neuron_memory.u_neuron.u_mac8.x_bus [39:32] * \u_neuron_memory.u_neuron.u_mac8.w_bus [39:32] (8x8 bits, signed)
|
|
add \u_neuron_memory.u_neuron.u_mac8.x_bus [47:40] * \u_neuron_memory.u_neuron.u_mac8.w_bus [47:40] (8x8 bits, signed)
|
|
add \u_neuron_memory.u_neuron.u_mac8.x_bus [55:48] * \u_neuron_memory.u_neuron.u_mac8.w_bus [55:48] (8x8 bits, signed)
|
|
add \u_neuron_memory.u_neuron.u_mac8.x_bus [63:56] * \u_neuron_memory.u_neuron.u_mac8.w_bus [63:56] (8x8 bits, signed)
|
|
Using template $paramod$2653f68ddb8eab7b1907b4a20767b72a824a7a36\_90_alu for cells of type $alu.
|
|
Using template $paramod$175e67c02b86e96b1288b9dc100122520d7240d8\_90_alu for cells of type $alu.
|
|
Using extmapper simplemap for cells of type $xor.
|
|
Using template $paramod$5795de66b4fd8cc5bd187dddeed92f207a6f390d\_90_alu for cells of type $alu.
|
|
Using template $paramod$78e969f2586efcf3a5b0b0440bcca0db83d5cca2\_90_alu for cells of type $alu.
|
|
Using template $paramod$a1bc51c02ce12ac21eb18988e83292af48ed7d72\_90_alu for cells of type $alu.
|
|
Using template $paramod$e161c1674351796cd6dd381e70ff05458bfe7755\_90_alu for cells of type $alu.
|
|
Using template $paramod$a7817265ef3ab2ee43da53bbd8a90f6450d412d9\_90_alu for cells of type $alu.
|
|
Using template $paramod$7e708ae28ab761f11d0fb59d3ffc72f6a4baf5d9\_90_alu for cells of type $alu.
|
|
Using template $paramod$6df0329addda9228fcc2546de2aaf14ad26c98e1\_90_alu for cells of type $alu.
|
|
Using template $paramod$740b056ede97228d3eae64ea2fdc81f0a33e0fe7\_90_alu for cells of type $alu.
|
|
Using template $paramod\_90_fa\WIDTH=32'00000000000000000000000000010000 for cells of type $fa.
|
|
Using extmapper simplemap for cells of type $pos.
|
|
Using template $paramod\_90_fa\WIDTH=32'00000000000000000000000000000011 for cells of type $fa.
|
|
Using template $paramod\_90_lcu_brent_kung\WIDTH=32'00000000000000000000000000000011 for cells of type $lcu.
|
|
Using template $paramod\_90_fa\WIDTH=32'00000000000000000000000000000100 for cells of type $fa.
|
|
Using template $paramod\_90_lcu_brent_kung\WIDTH=32'00000000000000000000000000000100 for cells of type $lcu.
|
|
Using template $paramod\_90_lcu_brent_kung\WIDTH=32'00000000000000000000000000010000 for cells of type $lcu.
|
|
Using template $paramod\_90_fa\WIDTH=32'00000000000000000000000000010110 for cells of type $fa.
|
|
Using template $paramod\_90_lcu_brent_kung\WIDTH=32'00000000000000000000000000010110 for cells of type $lcu.
|
|
Using template $paramod\_90_fa\WIDTH=32'00000000000000000000000000000010 for cells of type $fa.
|
|
Using template $paramod\_90_lcu_brent_kung\WIDTH=32'00000000000000000000000000000010 for cells of type $lcu.
|
|
Using template $paramod\_90_fa\WIDTH=32'00000000000000000000000000100000 for cells of type $fa.
|
|
Using template $paramod\_90_lcu_brent_kung\WIDTH=32'00000000000000000000000000100000 for cells of type $lcu.
|
|
Using template $paramod\_90_fa\WIDTH=32'00000000000000000000000000000001 for cells of type $fa.
|
|
Using template $paramod\_90_lcu_brent_kung\WIDTH=32'00000000000000000000000000000001 for cells of type $lcu.
|
|
Using template $paramod\_90_fa\WIDTH=32'00000000000000000000000000001000 for cells of type $fa.
|
|
Using template $paramod\_90_lcu_brent_kung\WIDTH=32'00000000000000000000000000001000 for cells of type $lcu.
|
|
Using template $paramod\_90_fa\WIDTH=32'00000000000000000000000000000110 for cells of type $fa.
|
|
Using template $paramod\_90_lcu_brent_kung\WIDTH=32'00000000000000000000000000000110 for cells of type $lcu.
|
|
Using template $paramod\_90_fa\WIDTH=32'00000000000000000000000000001110 for cells of type $fa.
|
|
Using template $paramod\_90_lcu_brent_kung\WIDTH=32'00000000000000000000000000001110 for cells of type $lcu.
|
|
No more expansions possible.
|
|
<suppressed ~8506 debug messages>
|
|
|
|
20. Executing OPT pass (performing simple optimizations).
|
|
|
|
20.1. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module spi_neuron_top.
|
|
<suppressed ~10446 debug messages>
|
|
|
|
20.2. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\spi_neuron_top'.
|
|
Computing hashes of 15443 cells of `\spi_neuron_top'.
|
|
Finding duplicate cells in `\spi_neuron_top'.
|
|
Computing hashes of 14379 cells of `\spi_neuron_top'.
|
|
Finding duplicate cells in `\spi_neuron_top'.
|
|
Computing hashes of 13893 cells of `\spi_neuron_top'.
|
|
Finding duplicate cells in `\spi_neuron_top'.
|
|
Computing hashes of 13680 cells of `\spi_neuron_top'.
|
|
Finding duplicate cells in `\spi_neuron_top'.
|
|
Computing hashes of 13589 cells of `\spi_neuron_top'.
|
|
Finding duplicate cells in `\spi_neuron_top'.
|
|
Computing hashes of 13511 cells of `\spi_neuron_top'.
|
|
Finding duplicate cells in `\spi_neuron_top'.
|
|
Computing hashes of 13453 cells of `\spi_neuron_top'.
|
|
Finding duplicate cells in `\spi_neuron_top'.
|
|
Computing hashes of 13421 cells of `\spi_neuron_top'.
|
|
Finding duplicate cells in `\spi_neuron_top'.
|
|
Computing hashes of 13420 cells of `\spi_neuron_top'.
|
|
Finding duplicate cells in `\spi_neuron_top'.
|
|
Computing hashes of 13419 cells of `\spi_neuron_top'.
|
|
Finding duplicate cells in `\spi_neuron_top'.
|
|
<suppressed ~6072 debug messages>
|
|
Removed a total of 2024 cells.
|
|
|
|
20.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \spi_neuron_top..
|
|
Creating internal representation of mux trees.
|
|
No muxes found in this module.
|
|
Removed 0 multiplexer ports.
|
|
|
|
20.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \spi_neuron_top.
|
|
Performed a total of 0 changes.
|
|
|
|
20.5. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\spi_neuron_top'.
|
|
Computing hashes of 13419 cells of `\spi_neuron_top'.
|
|
Finding duplicate cells in `\spi_neuron_top'.
|
|
Removed a total of 0 cells.
|
|
|
|
20.6. Executing OPT_DFF pass (perform DFF optimizations).
|
|
Adding SRST signal on $auto$ff.cc:337:slice$6609 ($_SDFF_PP0_) from module spi_neuron_top (D = $auto$simplemap.cc:189:logic_reduce$14468, Q = \u_psram_ctrl.mem_ready, rval = 1'0).
|
|
Adding SRST signal on $auto$ff.cc:337:slice$6912 ($_SDFF_PP0_) from module spi_neuron_top (D = $auto$simplemap.cc:189:logic_reduce$14627, Q = \u_psram_ctrl.dq_oe, rval = 1'0).
|
|
Adding SRST signal on $auto$ff.cc:337:slice$6787 ($_SDFF_PP0_) from module spi_neuron_top (D = $auto$simplemap.cc:189:logic_reduce$13600, Q = \u_neuron_memory.access_req, rval = 1'0).
|
|
Adding SRST signal on $auto$ff.cc:337:slice$6616 ($_SDFF_PP1_) from module spi_neuron_top (D = $auto$simplemap.cc:189:logic_reduce$14602, Q = \u_psram_ctrl.psram_ub_n, rval = 1'1).
|
|
Adding SRST signal on $auto$ff.cc:337:slice$6615 ($_SDFF_PP1_) from module spi_neuron_top (D = $auto$simplemap.cc:189:logic_reduce$14572, Q = \u_psram_ctrl.psram_lb_n, rval = 1'1).
|
|
Adding SRST signal on $auto$ff.cc:337:slice$6614 ($_SDFF_PP1_) from module spi_neuron_top (D = $auto$simplemap.cc:189:logic_reduce$14542, Q = \u_psram_ctrl.psram_we_n, rval = 1'1).
|
|
Adding SRST signal on $auto$ff.cc:337:slice$6613 ($_SDFF_PP1_) from module spi_neuron_top (D = $auto$simplemap.cc:189:logic_reduce$14519, Q = \u_psram_ctrl.psram_oe_n, rval = 1'1).
|
|
Adding SRST signal on $auto$ff.cc:337:slice$6612 ($_SDFF_PP1_) from module spi_neuron_top (D = $auto$simplemap.cc:189:logic_reduce$14503, Q = \u_psram_ctrl.psram_ce_n, rval = 1'1).
|
|
Adding SRST signal on $auto$ff.cc:337:slice$14558 ($_DFF_P_) from module spi_neuron_top (D = $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$609$rdmux[0][1][0]$b$4461 [5], Q = $flatten\u_spi_engine.$auto$proc_rom.cc:154:do_switch$608 [5], rval = 1'0).
|
|
Adding SRST signal on $auto$ff.cc:337:slice$14556 ($_DFF_P_) from module spi_neuron_top (D = $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$609$rdmux[0][0][0]$b$4458 [3], Q = $flatten\u_spi_engine.$auto$proc_rom.cc:154:do_switch$608 [3], rval = 1'0).
|
|
Adding SRST signal on $auto$ff.cc:337:slice$14557 ($_DFF_P_) from module spi_neuron_top (D = $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$609$rdmux[0][1][0]$a$4460 [4], Q = $flatten\u_spi_engine.$auto$proc_rom.cc:154:do_switch$608 [4], rval = 1'0).
|
|
|
|
20.7. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \spi_neuron_top..
|
|
Removed 1727 unused cells and 4959 unused wires.
|
|
<suppressed ~1728 debug messages>
|
|
|
|
20.8. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module spi_neuron_top.
|
|
<suppressed ~13 debug messages>
|
|
|
|
20.9. Rerunning OPT passes. (Maybe there is more to do..)
|
|
|
|
20.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \spi_neuron_top..
|
|
Creating internal representation of mux trees.
|
|
No muxes found in this module.
|
|
Removed 0 multiplexer ports.
|
|
|
|
20.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \spi_neuron_top.
|
|
Performed a total of 0 changes.
|
|
|
|
20.12. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\spi_neuron_top'.
|
|
Computing hashes of 11698 cells of `\spi_neuron_top'.
|
|
Finding duplicate cells in `\spi_neuron_top'.
|
|
Computing hashes of 11666 cells of `\spi_neuron_top'.
|
|
Finding duplicate cells in `\spi_neuron_top'.
|
|
Computing hashes of 11663 cells of `\spi_neuron_top'.
|
|
Finding duplicate cells in `\spi_neuron_top'.
|
|
<suppressed ~105 debug messages>
|
|
Removed a total of 35 cells.
|
|
|
|
20.13. Executing OPT_DFF pass (perform DFF optimizations).
|
|
|
|
20.14. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \spi_neuron_top..
|
|
Removed 0 unused cells and 48 unused wires.
|
|
<suppressed ~1 debug messages>
|
|
|
|
20.15. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module spi_neuron_top.
|
|
|
|
20.16. Rerunning OPT passes. (Maybe there is more to do..)
|
|
|
|
20.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \spi_neuron_top..
|
|
Creating internal representation of mux trees.
|
|
No muxes found in this module.
|
|
Removed 0 multiplexer ports.
|
|
|
|
20.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \spi_neuron_top.
|
|
Performed a total of 0 changes.
|
|
|
|
20.19. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\spi_neuron_top'.
|
|
Computing hashes of 11663 cells of `\spi_neuron_top'.
|
|
Finding duplicate cells in `\spi_neuron_top'.
|
|
Removed a total of 0 cells.
|
|
|
|
20.20. Executing OPT_DFF pass (perform DFF optimizations).
|
|
Adding SRST signal on $auto$ff.cc:337:slice$14553 ($_DFF_P_) from module spi_neuron_top (D = $auto$rtlil.cc:3402:Mux$4253 [0], Q = $flatten\u_spi_engine.$auto$proc_rom.cc:154:do_switch$608 [0], rval = 1'0).
|
|
|
|
20.21. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \spi_neuron_top..
|
|
Removed 1 unused cells and 1 unused wires.
|
|
<suppressed ~2 debug messages>
|
|
|
|
20.22. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module spi_neuron_top.
|
|
|
|
20.23. Rerunning OPT passes. (Maybe there is more to do..)
|
|
|
|
20.24. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \spi_neuron_top..
|
|
Creating internal representation of mux trees.
|
|
No muxes found in this module.
|
|
Removed 0 multiplexer ports.
|
|
|
|
20.25. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \spi_neuron_top.
|
|
Performed a total of 0 changes.
|
|
|
|
20.26. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\spi_neuron_top'.
|
|
Computing hashes of 11662 cells of `\spi_neuron_top'.
|
|
Finding duplicate cells in `\spi_neuron_top'.
|
|
Removed a total of 0 cells.
|
|
|
|
20.27. Executing OPT_DFF pass (perform DFF optimizations).
|
|
|
|
20.28. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \spi_neuron_top..
|
|
|
|
20.29. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module spi_neuron_top.
|
|
|
|
20.30. Finished fast OPT passes. (There is nothing left to do.)
|
|
|
|
21. Executing ABC pass (technology mapping using ABC).
|
|
|
|
21.1. Extracting gate netlist of module `\spi_neuron_top' to `<abc-temp-dir>/input.blif'..
|
|
Replacing 1012 occurrences of constant undef bits with constant zero bits
|
|
|
|
21.1.1. Executed ABC.
|
|
Extracted 10210 gates and 11406 wires to a netlist network with 1192 inputs and 625 outputs.
|
|
Running ABC script: <abc-temp-dir>/abc.script
|
|
ABC: ======== ABC command line "source <abc-temp-dir>/abc.script"
|
|
ABC: + read_blif <abc-temp-dir>/input.blif
|
|
ABC: + read_library <abc-temp-dir>/stdcells.genlib
|
|
ABC: + strash
|
|
ABC: + &get -n
|
|
ABC: + &fraig -x
|
|
ABC: + &put
|
|
ABC: + scorr
|
|
ABC: Warning: The network is combinational (run "fraig" or "fraig_sweep").
|
|
ABC: + dc2
|
|
ABC: + dretime
|
|
ABC: + strash
|
|
ABC: + &get -n
|
|
ABC: + &dch -f
|
|
ABC: + &nf
|
|
ABC: + &put
|
|
ABC: + write_blif <abc-temp-dir>/output.blif
|
|
|
|
21.1.2. Re-integrating ABC results.
|
|
ABC RESULTS: AND cells: 3746
|
|
ABC RESULTS: MUX cells: 371
|
|
ABC RESULTS: NOT cells: 524
|
|
ABC RESULTS: OR cells: 1776
|
|
ABC RESULTS: XOR cells: 1728
|
|
ABC RESULTS: ZERO cells: 10
|
|
ABC RESULTS: internal signals: 9589
|
|
ABC RESULTS: input signals: 1192
|
|
ABC RESULTS: output signals: 625
|
|
Removing temp directory.
|
|
Removing global temp directory.
|
|
Removed 0 unused cells and 4949 unused wires.
|
|
|
|
22. Executing SYNTH_LATTICE pass.
|
|
|
|
22.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v
|
|
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v' to AST representation.
|
|
Generating RTLIL representation for module `\LUT4'.
|
|
Generating RTLIL representation for module `\$__ABC9_LUT5'.
|
|
Generating RTLIL representation for module `\$__ABC9_LUT6'.
|
|
Generating RTLIL representation for module `\$__ABC9_LUT7'.
|
|
Generating RTLIL representation for module `\L6MUX21'.
|
|
Generating RTLIL representation for module `\TRELLIS_RAM16X2'.
|
|
Generating RTLIL representation for module `\PFUMX'.
|
|
Generating RTLIL representation for module `\TRELLIS_DPR16X4'.
|
|
Generating RTLIL representation for module `\DPR16X4C'.
|
|
Generating RTLIL representation for module `\LUT2'.
|
|
Generating RTLIL representation for module `\TRELLIS_FF'.
|
|
Generating RTLIL representation for module `\TRELLIS_IO'.
|
|
Generating RTLIL representation for module `\INV'.
|
|
Generating RTLIL representation for module `\TRELLIS_COMB'.
|
|
Generating RTLIL representation for module `\VLO'.
|
|
Generating RTLIL representation for module `\VHI'.
|
|
Generating RTLIL representation for module `\FD1P3AX'.
|
|
Generating RTLIL representation for module `\FD1P3AY'.
|
|
Generating RTLIL representation for module `\FD1P3BX'.
|
|
Generating RTLIL representation for module `\FD1P3DX'.
|
|
Generating RTLIL representation for module `\FD1P3IX'.
|
|
Generating RTLIL representation for module `\FD1P3JX'.
|
|
Generating RTLIL representation for module `\FD1S3AX'.
|
|
Generating RTLIL representation for module `\FD1S3AY'.
|
|
Generating RTLIL representation for module `\FD1S3BX'.
|
|
Generating RTLIL representation for module `\FD1S3DX'.
|
|
Generating RTLIL representation for module `\FD1S3IX'.
|
|
Generating RTLIL representation for module `\FD1S3JX'.
|
|
Generating RTLIL representation for module `\IFS1P3BX'.
|
|
Generating RTLIL representation for module `\IFS1P3DX'.
|
|
Generating RTLIL representation for module `\IFS1P3IX'.
|
|
Generating RTLIL representation for module `\IFS1P3JX'.
|
|
Generating RTLIL representation for module `\OFS1P3BX'.
|
|
Generating RTLIL representation for module `\OFS1P3DX'.
|
|
Generating RTLIL representation for module `\OFS1P3IX'.
|
|
Generating RTLIL representation for module `\OFS1P3JX'.
|
|
Generating RTLIL representation for module `\IB'.
|
|
Generating RTLIL representation for module `\IBPU'.
|
|
Generating RTLIL representation for module `\IBPD'.
|
|
Generating RTLIL representation for module `\OB'.
|
|
Generating RTLIL representation for module `\OBZ'.
|
|
Generating RTLIL representation for module `\OBZPU'.
|
|
Generating RTLIL representation for module `\OBZPD'.
|
|
Generating RTLIL representation for module `\OBCO'.
|
|
Generating RTLIL representation for module `\BB'.
|
|
Generating RTLIL representation for module `\BBPU'.
|
|
Generating RTLIL representation for module `\BBPD'.
|
|
Generating RTLIL representation for module `\ILVDS'.
|
|
Generating RTLIL representation for module `\OLVDS'.
|
|
Generating RTLIL representation for module `\CCU2C'.
|
|
Generating RTLIL representation for module `\DP16KD'.
|
|
Replacing existing blackbox module `\FD1P3AX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:2.1-2.261.
|
|
Generating RTLIL representation for module `\FD1P3AX'.
|
|
Replacing existing blackbox module `\FD1P3AY' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:3.1-3.261.
|
|
Generating RTLIL representation for module `\FD1P3AY'.
|
|
Replacing existing blackbox module `\FD1P3BX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:4.1-4.261.
|
|
Generating RTLIL representation for module `\FD1P3BX'.
|
|
Replacing existing blackbox module `\FD1P3DX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:5.1-5.261.
|
|
Generating RTLIL representation for module `\FD1P3DX'.
|
|
Replacing existing blackbox module `\FD1P3IX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:6.1-6.261.
|
|
Generating RTLIL representation for module `\FD1P3IX'.
|
|
Replacing existing blackbox module `\FD1P3JX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:7.1-7.261.
|
|
Generating RTLIL representation for module `\FD1P3JX'.
|
|
Replacing existing blackbox module `\FD1S3AX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:8.1-8.261.
|
|
Generating RTLIL representation for module `\FD1S3AX'.
|
|
Replacing existing blackbox module `\FD1S3AY' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:9.1-9.261.
|
|
Generating RTLIL representation for module `\FD1S3AY'.
|
|
Replacing existing blackbox module `\FD1S3BX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:10.1-10.261.
|
|
Generating RTLIL representation for module `\FD1S3BX'.
|
|
Replacing existing blackbox module `\FD1S3DX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:11.1-11.261.
|
|
Generating RTLIL representation for module `\FD1S3DX'.
|
|
Replacing existing blackbox module `\FD1S3IX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:12.1-12.261.
|
|
Generating RTLIL representation for module `\FD1S3IX'.
|
|
Replacing existing blackbox module `\FD1S3JX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:13.1-13.261.
|
|
Generating RTLIL representation for module `\FD1S3JX'.
|
|
Replacing existing blackbox module `\IFS1P3BX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:26.1-26.301.
|
|
Generating RTLIL representation for module `\IFS1P3BX'.
|
|
Replacing existing blackbox module `\IFS1P3DX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:27.1-27.301.
|
|
Generating RTLIL representation for module `\IFS1P3DX'.
|
|
Replacing existing blackbox module `\IFS1P3IX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:28.1-28.301.
|
|
Generating RTLIL representation for module `\IFS1P3IX'.
|
|
Replacing existing blackbox module `\IFS1P3JX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:29.1-29.301.
|
|
Generating RTLIL representation for module `\IFS1P3JX'.
|
|
Replacing existing blackbox module `\OFS1P3BX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:31.1-31.302.
|
|
Generating RTLIL representation for module `\OFS1P3BX'.
|
|
Replacing existing blackbox module `\OFS1P3DX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:32.1-32.302.
|
|
Generating RTLIL representation for module `\OFS1P3DX'.
|
|
Replacing existing blackbox module `\OFS1P3IX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:33.1-33.302.
|
|
Generating RTLIL representation for module `\OFS1P3IX'.
|
|
Replacing existing blackbox module `\OFS1P3JX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:34.1-34.302.
|
|
Generating RTLIL representation for module `\OFS1P3JX'.
|
|
Replacing existing blackbox module `\IB' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:2.1-2.157.
|
|
Generating RTLIL representation for module `\IB'.
|
|
Replacing existing blackbox module `\IBPU' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:3.1-3.157.
|
|
Generating RTLIL representation for module `\IBPU'.
|
|
Replacing existing blackbox module `\IBPD' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:4.1-4.157.
|
|
Generating RTLIL representation for module `\IBPD'.
|
|
Replacing existing blackbox module `\OB' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:5.1-5.157.
|
|
Generating RTLIL representation for module `\OB'.
|
|
Replacing existing blackbox module `\OBZ' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:6.1-6.164.
|
|
Generating RTLIL representation for module `\OBZ'.
|
|
Replacing existing blackbox module `\OBZPU' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:7.1-7.164.
|
|
Generating RTLIL representation for module `\OBZPU'.
|
|
Replacing existing blackbox module `\OBZPD' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:8.1-8.164.
|
|
Generating RTLIL representation for module `\OBZPD'.
|
|
Replacing existing blackbox module `\OBCO' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:9.1-9.90.
|
|
Generating RTLIL representation for module `\OBCO'.
|
|
Replacing existing blackbox module `\BB' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:10.1-10.179.
|
|
Generating RTLIL representation for module `\BB'.
|
|
Replacing existing blackbox module `\BBPU' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:11.1-11.179.
|
|
Generating RTLIL representation for module `\BBPU'.
|
|
Replacing existing blackbox module `\BBPD' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:12.1-12.179.
|
|
Generating RTLIL representation for module `\BBPD'.
|
|
Replacing existing blackbox module `\ILVDS' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:13.1-13.139.
|
|
Generating RTLIL representation for module `\ILVDS'.
|
|
Replacing existing blackbox module `\OLVDS' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:14.1-14.146.
|
|
Generating RTLIL representation for module `\OLVDS'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
22.2. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v
|
|
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v' to AST representation.
|
|
Generating RTLIL representation for module `\GSR'.
|
|
Generating RTLIL representation for module `\PUR'.
|
|
Generating RTLIL representation for module `\SGSR'.
|
|
Generating RTLIL representation for module `\PDPW16KD'.
|
|
Generating RTLIL representation for module `\MULT18X18D'.
|
|
Generating RTLIL representation for module `\ALU54B'.
|
|
Generating RTLIL representation for module `\CLKDIVF'.
|
|
Generating RTLIL representation for module `\PCSCLKDIV'.
|
|
Generating RTLIL representation for module `\DCSC'.
|
|
Generating RTLIL representation for module `\DCCA'.
|
|
Generating RTLIL representation for module `\ECLKSYNCB'.
|
|
Generating RTLIL representation for module `\ECLKBRIDGECS'.
|
|
Generating RTLIL representation for module `\DELAYF'.
|
|
Generating RTLIL representation for module `\DELAYG'.
|
|
Generating RTLIL representation for module `\USRMCLK'.
|
|
Generating RTLIL representation for module `\DQSBUFM'.
|
|
Generating RTLIL representation for module `\DDRDLLA'.
|
|
Generating RTLIL representation for module `\DLLDELD'.
|
|
Generating RTLIL representation for module `\IDDRX1F'.
|
|
Generating RTLIL representation for module `\IDDRX2F'.
|
|
Generating RTLIL representation for module `\IDDR71B'.
|
|
Generating RTLIL representation for module `\IDDRX2DQA'.
|
|
Generating RTLIL representation for module `\ODDRX1F'.
|
|
Generating RTLIL representation for module `\ODDRX2F'.
|
|
Generating RTLIL representation for module `\ODDR71B'.
|
|
Generating RTLIL representation for module `\OSHX2A'.
|
|
Generating RTLIL representation for module `\TSHX2DQA'.
|
|
Generating RTLIL representation for module `\TSHX2DQSA'.
|
|
Generating RTLIL representation for module `\ODDRX2DQA'.
|
|
Generating RTLIL representation for module `\ODDRX2DQSB'.
|
|
Generating RTLIL representation for module `\EHXPLLL'.
|
|
Generating RTLIL representation for module `\DTR'.
|
|
Generating RTLIL representation for module `\OSCG'.
|
|
Generating RTLIL representation for module `\EXTREFB'.
|
|
Generating RTLIL representation for module `\JTAGG'.
|
|
Generating RTLIL representation for module `\DCUA'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
22.3. Executing HIERARCHY pass (managing design hierarchy).
|
|
|
|
22.3.1. Analyzing design hierarchy..
|
|
Top module: \spi_neuron_top
|
|
|
|
22.3.2. Analyzing design hierarchy..
|
|
Top module: \spi_neuron_top
|
|
Removed 0 unused modules.
|
|
|
|
22.4. Executing PROC pass (convert processes to netlists).
|
|
|
|
22.4.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
|
|
Cleaned up 0 empty switches.
|
|
|
|
22.4.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
|
|
Removed a total of 0 dead cases.
|
|
|
|
22.4.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
|
|
Removed 0 redundant assignments.
|
|
Promoted 0 assignments to connections.
|
|
|
|
22.4.4. Executing PROC_INIT pass (extract init attributes).
|
|
|
|
22.4.5. Executing PROC_ARST pass (detect async resets in processes).
|
|
|
|
22.4.6. Executing PROC_ROM pass (convert switches to ROMs).
|
|
Converted 0 switches.
|
|
|
|
22.4.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
|
|
|
|
22.4.8. Executing PROC_DLATCH pass (convert process syncs to latches).
|
|
|
|
22.4.9. Executing PROC_DFF pass (convert process syncs to FFs).
|
|
|
|
22.4.10. Executing PROC_MEMWR pass (convert process memory writes to cells).
|
|
|
|
22.4.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
|
|
Cleaned up 0 empty switches.
|
|
|
|
22.4.12. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module spi_neuron_top.
|
|
<suppressed ~56 debug messages>
|
|
|
|
22.5. Executing CHECK pass (checking for obvious problems).
|
|
Checking module spi_neuron_top...
|
|
Found and reported 0 problems.
|
|
|
|
22.6. Executing FLATTEN pass (flatten design).
|
|
|
|
22.7. Executing TRIBUF pass.
|
|
|
|
22.8. Executing DEMINOUT pass (demote inout ports to input or output).
|
|
Demoting inout port spi_neuron_top.psram_dq to output.
|
|
|
|
22.9. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module spi_neuron_top.
|
|
|
|
22.10. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \spi_neuron_top..
|
|
|
|
22.11. Executing CHECK pass (checking for obvious problems).
|
|
Checking module spi_neuron_top...
|
|
Found and reported 0 problems.
|
|
|
|
22.12. Executing OPT pass (performing simple optimizations).
|
|
|
|
22.12.1. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module spi_neuron_top.
|
|
|
|
22.12.2. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\spi_neuron_top'.
|
|
Computing hashes of 9597 cells of `\spi_neuron_top'.
|
|
Finding duplicate cells in `\spi_neuron_top'.
|
|
Computing hashes of 9590 cells of `\spi_neuron_top'.
|
|
Finding duplicate cells in `\spi_neuron_top'.
|
|
<suppressed ~21 debug messages>
|
|
Removed a total of 7 cells.
|
|
|
|
22.12.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \spi_neuron_top..
|
|
Creating internal representation of mux trees.
|
|
No muxes found in this module.
|
|
Removed 0 multiplexer ports.
|
|
|
|
22.12.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \spi_neuron_top.
|
|
Performed a total of 0 changes.
|
|
|
|
22.12.5. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\spi_neuron_top'.
|
|
Computing hashes of 9590 cells of `\spi_neuron_top'.
|
|
Finding duplicate cells in `\spi_neuron_top'.
|
|
Removed a total of 0 cells.
|
|
|
|
22.12.6. Executing OPT_DFF pass (perform DFF optimizations).
|
|
Setting constant 0-bit at position 0 on $auto$ff.cc:337:slice$6678 ($_SDFFE_PP0P_) from module spi_neuron_top.
|
|
Setting constant 0-bit at position 0 on $auto$ff.cc:337:slice$6725 ($_SDFFE_PP0P_) from module spi_neuron_top.
|
|
Setting constant 0-bit at position 0 on $auto$ff.cc:337:slice$6383 ($_SDFFE_PP0P_) from module spi_neuron_top.
|
|
Setting constant 0-bit at position 0 on $auto$ff.cc:337:slice$6869 ($_SDFFE_PP0P_) from module spi_neuron_top.
|
|
Setting constant 0-bit at position 0 on $auto$ff.cc:337:slice$6971 ($_SDFFE_PP0P_) from module spi_neuron_top.
|
|
Setting constant 0-bit at position 0 on $auto$ff.cc:337:slice$7997 ($_SDFFE_PP0P_) from module spi_neuron_top.
|
|
Setting constant 0-bit at position 0 on $auto$ff.cc:337:slice$7038 ($_SDFFE_PP0P_) from module spi_neuron_top.
|
|
Setting constant 0-bit at position 0 on $auto$ff.cc:337:slice$7298 ($_SDFFE_PP0P_) from module spi_neuron_top.
|
|
Setting constant 0-bit at position 0 on $auto$ff.cc:337:slice$7316 ($_SDFFE_PP0P_) from module spi_neuron_top.
|
|
Setting constant 0-bit at position 0 on $auto$ff.cc:337:slice$7387 ($_SDFFE_PP0P_) from module spi_neuron_top.
|
|
|
|
22.12.7. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \spi_neuron_top..
|
|
Removed 4 unused cells and 11 unused wires.
|
|
<suppressed ~5 debug messages>
|
|
|
|
22.12.8. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module spi_neuron_top.
|
|
<suppressed ~242 debug messages>
|
|
|
|
22.12.9. Rerunning OPT passes. (Maybe there is more to do..)
|
|
|
|
22.12.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \spi_neuron_top..
|
|
Creating internal representation of mux trees.
|
|
No muxes found in this module.
|
|
Removed 0 multiplexer ports.
|
|
|
|
22.12.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \spi_neuron_top.
|
|
Performed a total of 0 changes.
|
|
|
|
22.12.12. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\spi_neuron_top'.
|
|
Computing hashes of 9334 cells of `\spi_neuron_top'.
|
|
Finding duplicate cells in `\spi_neuron_top'.
|
|
Computing hashes of 9330 cells of `\spi_neuron_top'.
|
|
Finding duplicate cells in `\spi_neuron_top'.
|
|
<suppressed ~12 debug messages>
|
|
Removed a total of 4 cells.
|
|
|
|
22.12.13. Executing OPT_DFF pass (perform DFF optimizations).
|
|
Setting constant 0-bit at position 0 on $auto$ff.cc:337:slice$6067 ($_SDFFCE_PN0P_) from module spi_neuron_top.
|
|
Setting constant 0-bit at position 0 on $auto$ff.cc:337:slice$6847 ($_SDFFE_PP0P_) from module spi_neuron_top.
|
|
|
|
22.12.14. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \spi_neuron_top..
|
|
Removed 130 unused cells and 369 unused wires.
|
|
<suppressed ~131 debug messages>
|
|
|
|
22.12.15. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module spi_neuron_top.
|
|
<suppressed ~3 debug messages>
|
|
|
|
22.12.16. Rerunning OPT passes. (Maybe there is more to do..)
|
|
|
|
22.12.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \spi_neuron_top..
|
|
Creating internal representation of mux trees.
|
|
No muxes found in this module.
|
|
Removed 0 multiplexer ports.
|
|
|
|
22.12.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \spi_neuron_top.
|
|
Performed a total of 0 changes.
|
|
|
|
22.12.19. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\spi_neuron_top'.
|
|
Computing hashes of 9195 cells of `\spi_neuron_top'.
|
|
Finding duplicate cells in `\spi_neuron_top'.
|
|
Removed a total of 0 cells.
|
|
|
|
22.12.20. Executing OPT_DFF pass (perform DFF optimizations).
|
|
Setting constant 0-bit at position 0 on $auto$ff.cc:337:slice$7005 ($_SDFFE_PP0P_) from module spi_neuron_top.
|
|
|
|
22.12.21. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \spi_neuron_top..
|
|
Removed 0 unused cells and 3 unused wires.
|
|
<suppressed ~1 debug messages>
|
|
|
|
22.12.22. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module spi_neuron_top.
|
|
<suppressed ~2 debug messages>
|
|
|
|
22.12.23. Rerunning OPT passes. (Maybe there is more to do..)
|
|
|
|
22.12.24. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \spi_neuron_top..
|
|
Creating internal representation of mux trees.
|
|
No muxes found in this module.
|
|
Removed 0 multiplexer ports.
|
|
|
|
22.12.25. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \spi_neuron_top.
|
|
Performed a total of 0 changes.
|
|
|
|
22.12.26. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\spi_neuron_top'.
|
|
Computing hashes of 9192 cells of `\spi_neuron_top'.
|
|
Finding duplicate cells in `\spi_neuron_top'.
|
|
Removed a total of 0 cells.
|
|
|
|
22.12.27. Executing OPT_DFF pass (perform DFF optimizations).
|
|
|
|
22.12.28. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \spi_neuron_top..
|
|
Removed 0 unused cells and 2 unused wires.
|
|
<suppressed ~1 debug messages>
|
|
|
|
22.12.29. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module spi_neuron_top.
|
|
|
|
22.12.30. Rerunning OPT passes. (Maybe there is more to do..)
|
|
|
|
22.12.31. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \spi_neuron_top..
|
|
Creating internal representation of mux trees.
|
|
No muxes found in this module.
|
|
Removed 0 multiplexer ports.
|
|
|
|
22.12.32. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \spi_neuron_top.
|
|
Performed a total of 0 changes.
|
|
|
|
22.12.33. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\spi_neuron_top'.
|
|
Computing hashes of 9192 cells of `\spi_neuron_top'.
|
|
Finding duplicate cells in `\spi_neuron_top'.
|
|
Removed a total of 0 cells.
|
|
|
|
22.12.34. Executing OPT_DFF pass (perform DFF optimizations).
|
|
|
|
22.12.35. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \spi_neuron_top..
|
|
|
|
22.12.36. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module spi_neuron_top.
|
|
|
|
22.12.37. Finished fast OPT passes. (There is nothing left to do.)
|
|
|
|
22.13. Executing FSM pass (extract and optimize FSM).
|
|
|
|
22.13.1. Executing FSM_DETECT pass (finding FSMs in design).
|
|
|
|
22.13.2. Executing FSM_EXTRACT pass (extracting FSM from design).
|
|
|
|
22.13.3. Executing FSM_OPT pass (simple optimizations of FSMs).
|
|
|
|
22.13.4. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \spi_neuron_top..
|
|
|
|
22.13.5. Executing FSM_OPT pass (simple optimizations of FSMs).
|
|
|
|
22.13.6. Executing FSM_RECODE pass (re-assigning FSM state encoding).
|
|
|
|
22.13.7. Executing FSM_INFO pass (dumping all available information on FSM cells).
|
|
|
|
22.13.8. Executing FSM_MAP pass (mapping FSMs to basic logic).
|
|
|
|
22.14. Executing OPT pass (performing simple optimizations).
|
|
|
|
22.14.1. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module spi_neuron_top.
|
|
|
|
22.14.2. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\spi_neuron_top'.
|
|
Computing hashes of 9192 cells of `\spi_neuron_top'.
|
|
Finding duplicate cells in `\spi_neuron_top'.
|
|
Removed a total of 0 cells.
|
|
|
|
22.14.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \spi_neuron_top..
|
|
Creating internal representation of mux trees.
|
|
No muxes found in this module.
|
|
Removed 0 multiplexer ports.
|
|
|
|
22.14.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \spi_neuron_top.
|
|
Performed a total of 0 changes.
|
|
|
|
22.14.5. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\spi_neuron_top'.
|
|
Computing hashes of 9192 cells of `\spi_neuron_top'.
|
|
Finding duplicate cells in `\spi_neuron_top'.
|
|
Removed a total of 0 cells.
|
|
|
|
22.14.6. Executing OPT_DFF pass (perform DFF optimizations).
|
|
|
|
22.14.7. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \spi_neuron_top..
|
|
|
|
22.14.8. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module spi_neuron_top.
|
|
|
|
22.14.9. Finished fast OPT passes. (There is nothing left to do.)
|
|
|
|
22.15. Executing WREDUCE pass (reducing word size of cells).
|
|
Removed top 1 bits (of 8) from wire spi_neuron_top.u_neuron_memory.y_reg[0].
|
|
Removed top 1 bits (of 22) from wire spi_neuron_top.psram_mem_addr.
|
|
Removed top 1 bits (of 22) from wire spi_neuron_top.i8_mem_addr.
|
|
Removed top 1 bits (of 8) from wire spi_neuron_top.seq_ram_wdata.
|
|
Removed top 1 bits (of 8) from wire spi_neuron_top.y_bus.
|
|
|
|
22.16. Executing PEEPOPT pass (run peephole optimizers).
|
|
|
|
22.17. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \spi_neuron_top..
|
|
Removed 0 unused cells and 5 unused wires.
|
|
<suppressed ~1 debug messages>
|
|
|
|
22.18. Executing SHARE pass (SAT-based resource sharing).
|
|
|
|
22.19. Executing TECHMAP pass (map to technology primitives).
|
|
|
|
22.19.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/cmp2lut.v
|
|
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/cmp2lut.v' to AST representation.
|
|
Generating RTLIL representation for module `\_90_lut_cmp_'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
22.19.2. Continuing TECHMAP pass.
|
|
No more expansions possible.
|
|
<suppressed ~6 debug messages>
|
|
|
|
22.20. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module spi_neuron_top.
|
|
|
|
22.21. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \spi_neuron_top..
|
|
|
|
22.22. Executing TECHMAP pass (map to technology primitives).
|
|
|
|
22.22.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/mul2dsp.v
|
|
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/mul2dsp.v' to AST representation.
|
|
Generating RTLIL representation for module `\_80_mul'.
|
|
Generating RTLIL representation for module `\_90_soft_mul'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
22.22.2. Continuing TECHMAP pass.
|
|
No more expansions possible.
|
|
<suppressed ~4 debug messages>
|
|
|
|
22.23. Executing TECHMAP pass (map to technology primitives).
|
|
|
|
22.23.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/dsp_map_18x18.v
|
|
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/dsp_map_18x18.v' to AST representation.
|
|
Generating RTLIL representation for module `$__MUL18X18'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
22.23.2. Continuing TECHMAP pass.
|
|
No more expansions possible.
|
|
<suppressed ~3 debug messages>
|
|
|
|
22.24. Executing ALUMACC pass (create $alu and $macc cells).
|
|
Extracting $alu and $macc cells in module spi_neuron_top:
|
|
created 0 $alu and 0 $macc cells.
|
|
|
|
22.25. Executing OPT pass (performing simple optimizations).
|
|
|
|
22.25.1. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module spi_neuron_top.
|
|
|
|
22.25.2. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\spi_neuron_top'.
|
|
Computing hashes of 9192 cells of `\spi_neuron_top'.
|
|
Finding duplicate cells in `\spi_neuron_top'.
|
|
Removed a total of 0 cells.
|
|
|
|
22.25.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \spi_neuron_top..
|
|
Creating internal representation of mux trees.
|
|
No muxes found in this module.
|
|
Removed 0 multiplexer ports.
|
|
|
|
22.25.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \spi_neuron_top.
|
|
Performed a total of 0 changes.
|
|
|
|
22.25.5. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\spi_neuron_top'.
|
|
Computing hashes of 9192 cells of `\spi_neuron_top'.
|
|
Finding duplicate cells in `\spi_neuron_top'.
|
|
Removed a total of 0 cells.
|
|
|
|
22.25.6. Executing OPT_DFF pass (perform DFF optimizations).
|
|
|
|
22.25.7. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \spi_neuron_top..
|
|
|
|
22.25.8. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module spi_neuron_top.
|
|
|
|
22.25.9. Finished fast OPT passes. (There is nothing left to do.)
|
|
|
|
22.26. Executing MEMORY pass.
|
|
|
|
22.26.1. Executing OPT_MEM pass (optimize memories).
|
|
Performed a total of 0 transformations.
|
|
|
|
22.26.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations).
|
|
Performed a total of 0 transformations.
|
|
|
|
22.26.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths).
|
|
|
|
22.26.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs).
|
|
|
|
22.26.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd).
|
|
|
|
22.26.6. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \spi_neuron_top..
|
|
|
|
22.26.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells).
|
|
|
|
22.26.8. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide).
|
|
Performed a total of 0 transformations.
|
|
|
|
22.26.9. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \spi_neuron_top..
|
|
|
|
22.26.10. Executing MEMORY_COLLECT pass (generating $mem cells).
|
|
|
|
22.27. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \spi_neuron_top..
|
|
|
|
22.28. Executing MEMORY_LIBMAP pass (mapping memories to cells).
|
|
|
|
22.29. Executing TECHMAP pass (map to technology primitives).
|
|
|
|
22.29.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/lutrams_map_trellis.v
|
|
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/lutrams_map_trellis.v' to AST representation.
|
|
Generating RTLIL representation for module `$__TRELLIS_DPR16X4_'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
22.29.2. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/brams_map_16kd.v
|
|
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/brams_map_16kd.v' to AST representation.
|
|
Generating RTLIL representation for module `$__DP16KD_'.
|
|
Generating RTLIL representation for module `$__PDPW16KD_'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
22.29.3. Continuing TECHMAP pass.
|
|
No more expansions possible.
|
|
<suppressed ~5 debug messages>
|
|
|
|
22.30. Executing OPT pass (performing simple optimizations).
|
|
|
|
22.30.1. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module spi_neuron_top.
|
|
<suppressed ~169 debug messages>
|
|
|
|
22.30.2. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\spi_neuron_top'.
|
|
Computing hashes of 9192 cells of `\spi_neuron_top'.
|
|
Finding duplicate cells in `\spi_neuron_top'.
|
|
Removed a total of 0 cells.
|
|
|
|
22.30.3. Executing OPT_DFF pass (perform DFF optimizations).
|
|
|
|
22.30.4. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \spi_neuron_top..
|
|
|
|
22.30.5. Finished fast OPT passes.
|
|
|
|
22.31. Executing MEMORY_MAP pass (converting memories to logic and flip-flops).
|
|
|
|
22.32. Executing OPT pass (performing simple optimizations).
|
|
|
|
22.32.1. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module spi_neuron_top.
|
|
|
|
22.32.2. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\spi_neuron_top'.
|
|
Computing hashes of 9192 cells of `\spi_neuron_top'.
|
|
Finding duplicate cells in `\spi_neuron_top'.
|
|
Removed a total of 0 cells.
|
|
|
|
22.32.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \spi_neuron_top..
|
|
Creating internal representation of mux trees.
|
|
No muxes found in this module.
|
|
Removed 0 multiplexer ports.
|
|
|
|
22.32.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \spi_neuron_top.
|
|
Performed a total of 0 changes.
|
|
|
|
22.32.5. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\spi_neuron_top'.
|
|
Computing hashes of 9192 cells of `\spi_neuron_top'.
|
|
Finding duplicate cells in `\spi_neuron_top'.
|
|
Removed a total of 0 cells.
|
|
|
|
22.32.6. Executing OPT_DFF pass (perform DFF optimizations).
|
|
|
|
22.32.7. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \spi_neuron_top..
|
|
|
|
22.32.8. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module spi_neuron_top.
|
|
|
|
22.32.9. Finished fast OPT passes. (There is nothing left to do.)
|
|
|
|
22.33. Executing TECHMAP pass (map to technology primitives).
|
|
|
|
22.33.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/techmap.v
|
|
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/techmap.v' to AST representation.
|
|
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
|
|
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
|
|
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
|
|
Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
|
|
Generating RTLIL representation for module `\_90_simplemap_various'.
|
|
Generating RTLIL representation for module `\_90_simplemap_registers'.
|
|
Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
|
|
Generating RTLIL representation for module `\_90_shift_shiftx'.
|
|
Generating RTLIL representation for module `\_90_fa'.
|
|
Generating RTLIL representation for module `\_90_lcu_brent_kung'.
|
|
Generating RTLIL representation for module `\_90_alu'.
|
|
Generating RTLIL representation for module `\_90_macc'.
|
|
Generating RTLIL representation for module `\_90_alumacc'.
|
|
Generating RTLIL representation for module `$__div_mod_u'.
|
|
Generating RTLIL representation for module `$__div_mod_trunc'.
|
|
Generating RTLIL representation for module `\_90_div'.
|
|
Generating RTLIL representation for module `\_90_mod'.
|
|
Generating RTLIL representation for module `$__div_mod_floor'.
|
|
Generating RTLIL representation for module `\_90_divfloor'.
|
|
Generating RTLIL representation for module `\_90_modfloor'.
|
|
Generating RTLIL representation for module `\_90_pow'.
|
|
Generating RTLIL representation for module `\_90_demux'.
|
|
Generating RTLIL representation for module `\_90_lut'.
|
|
Generating RTLIL representation for module `$connect'.
|
|
Generating RTLIL representation for module `$input_port'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
22.33.2. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v
|
|
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v' to AST representation.
|
|
Generating RTLIL representation for module `\_80_ccu2c_alu'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
22.33.3. Continuing TECHMAP pass.
|
|
No more expansions possible.
|
|
<suppressed ~77 debug messages>
|
|
|
|
22.34. Executing OPT pass (performing simple optimizations).
|
|
|
|
22.34.1. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module spi_neuron_top.
|
|
|
|
22.34.2. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\spi_neuron_top'.
|
|
Computing hashes of 9192 cells of `\spi_neuron_top'.
|
|
Finding duplicate cells in `\spi_neuron_top'.
|
|
Removed a total of 0 cells.
|
|
|
|
22.34.3. Executing OPT_DFF pass (perform DFF optimizations).
|
|
|
|
22.34.4. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \spi_neuron_top..
|
|
|
|
22.34.5. Finished fast OPT passes.
|
|
|
|
22.35. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \spi_neuron_top..
|
|
|
|
22.36. Executing DFFLEGALIZE pass (convert FFs to types supported by the target).
|
|
|
|
22.37. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\spi_neuron_top'.
|
|
Computing hashes of 9208 cells of `\spi_neuron_top'.
|
|
Finding duplicate cells in `\spi_neuron_top'.
|
|
Computing hashes of 9202 cells of `\spi_neuron_top'.
|
|
Finding duplicate cells in `\spi_neuron_top'.
|
|
Computing hashes of 9196 cells of `\spi_neuron_top'.
|
|
Finding duplicate cells in `\spi_neuron_top'.
|
|
<suppressed ~36 debug messages>
|
|
Removed a total of 12 cells.
|
|
|
|
22.38. Executing TECHMAP pass (map to technology primitives).
|
|
|
|
22.38.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v
|
|
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v' to AST representation.
|
|
Generating RTLIL representation for module `$_DFF_N_'.
|
|
Generating RTLIL representation for module `$_DFF_P_'.
|
|
Generating RTLIL representation for module `$_DFFE_NN_'.
|
|
Generating RTLIL representation for module `$_DFFE_PN_'.
|
|
Generating RTLIL representation for module `$_DFFE_NP_'.
|
|
Generating RTLIL representation for module `$_DFFE_PP_'.
|
|
Generating RTLIL representation for module `$_DFF_NP0_'.
|
|
Generating RTLIL representation for module `$_DFF_NP1_'.
|
|
Generating RTLIL representation for module `$_DFF_PP0_'.
|
|
Generating RTLIL representation for module `$_DFF_PP1_'.
|
|
Generating RTLIL representation for module `$_SDFF_NP0_'.
|
|
Generating RTLIL representation for module `$_SDFF_NP1_'.
|
|
Generating RTLIL representation for module `$_SDFF_PP0_'.
|
|
Generating RTLIL representation for module `$_SDFF_PP1_'.
|
|
Generating RTLIL representation for module `$_DFFE_NP0P_'.
|
|
Generating RTLIL representation for module `$_DFFE_NP1P_'.
|
|
Generating RTLIL representation for module `$_DFFE_PP0P_'.
|
|
Generating RTLIL representation for module `$_DFFE_PP1P_'.
|
|
Generating RTLIL representation for module `$_DFFE_NP0N_'.
|
|
Generating RTLIL representation for module `$_DFFE_NP1N_'.
|
|
Generating RTLIL representation for module `$_DFFE_PP0N_'.
|
|
Generating RTLIL representation for module `$_DFFE_PP1N_'.
|
|
Generating RTLIL representation for module `$_SDFFE_NP0P_'.
|
|
Generating RTLIL representation for module `$_SDFFE_NP1P_'.
|
|
Generating RTLIL representation for module `$_SDFFE_PP0P_'.
|
|
Generating RTLIL representation for module `$_SDFFE_PP1P_'.
|
|
Generating RTLIL representation for module `$_SDFFE_NP0N_'.
|
|
Generating RTLIL representation for module `$_SDFFE_NP1N_'.
|
|
Generating RTLIL representation for module `$_SDFFE_PP0N_'.
|
|
Generating RTLIL representation for module `$_SDFFE_PP1N_'.
|
|
Generating RTLIL representation for module `$_ALDFF_NP_'.
|
|
Generating RTLIL representation for module `$_ALDFF_PP_'.
|
|
Generating RTLIL representation for module `$_ALDFFE_NPN_'.
|
|
Generating RTLIL representation for module `$_ALDFFE_NPP_'.
|
|
Generating RTLIL representation for module `$_ALDFFE_PPN_'.
|
|
Generating RTLIL representation for module `$_ALDFFE_PPP_'.
|
|
Generating RTLIL representation for module `\FD1P3AX'.
|
|
Generating RTLIL representation for module `\FD1P3AY'.
|
|
Generating RTLIL representation for module `\FD1P3BX'.
|
|
Generating RTLIL representation for module `\FD1P3DX'.
|
|
Generating RTLIL representation for module `\FD1P3IX'.
|
|
Generating RTLIL representation for module `\FD1P3JX'.
|
|
Generating RTLIL representation for module `\FD1S3AX'.
|
|
Generating RTLIL representation for module `\FD1S3AY'.
|
|
Generating RTLIL representation for module `\FD1S3BX'.
|
|
Generating RTLIL representation for module `\FD1S3DX'.
|
|
Generating RTLIL representation for module `\FD1S3IX'.
|
|
Generating RTLIL representation for module `\FD1S3JX'.
|
|
Generating RTLIL representation for module `\IFS1P3BX'.
|
|
Generating RTLIL representation for module `\IFS1P3DX'.
|
|
Generating RTLIL representation for module `\IFS1P3IX'.
|
|
Generating RTLIL representation for module `\IFS1P3JX'.
|
|
Generating RTLIL representation for module `\OFS1P3BX'.
|
|
Generating RTLIL representation for module `\OFS1P3DX'.
|
|
Generating RTLIL representation for module `\OFS1P3IX'.
|
|
Generating RTLIL representation for module `\OFS1P3JX'.
|
|
Generating RTLIL representation for module `\IB'.
|
|
Generating RTLIL representation for module `\IBPU'.
|
|
Generating RTLIL representation for module `\IBPD'.
|
|
Generating RTLIL representation for module `\OB'.
|
|
Generating RTLIL representation for module `\OBZ'.
|
|
Generating RTLIL representation for module `\OBZPU'.
|
|
Generating RTLIL representation for module `\OBZPD'.
|
|
Generating RTLIL representation for module `\OBCO'.
|
|
Generating RTLIL representation for module `\BB'.
|
|
Generating RTLIL representation for module `\BBPU'.
|
|
Generating RTLIL representation for module `\BBPD'.
|
|
Generating RTLIL representation for module `\ILVDS'.
|
|
Generating RTLIL representation for module `\OLVDS'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
22.38.2. Continuing TECHMAP pass.
|
|
Using template $_SDFF_PP0_ for cells of type $_SDFF_PP0_.
|
|
Using template $_SDFF_PP1_ for cells of type $_SDFF_PP1_.
|
|
Using template $_SDFFE_PP0P_ for cells of type $_SDFFE_PP0P_.
|
|
Using template $_SDFFE_PP1P_ for cells of type $_SDFFE_PP1P_.
|
|
Using template $paramod$_DFFE_PP_\_TECHMAP_WIREINIT_Q_=1'x for cells of type $_DFFE_PP_.
|
|
No more expansions possible.
|
|
<suppressed ~1502 debug messages>
|
|
|
|
22.39. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module spi_neuron_top.
|
|
<suppressed ~1 debug messages>
|
|
|
|
22.40. Executing SIMPLEMAP pass (map simple cells to gate primitives).
|
|
|
|
22.41. Executing LATTICE_GSR pass (implement FF init values).
|
|
Handling GSR in spi_neuron_top.
|
|
|
|
22.42. Executing ATTRMVCP pass (move or copy attributes).
|
|
|
|
22.43. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \spi_neuron_top..
|
|
Removed 0 unused cells and 7974 unused wires.
|
|
<suppressed ~1 debug messages>
|
|
|
|
22.44. Executing CHECK pass (checking for obvious problems).
|
|
Checking module spi_neuron_top...
|
|
Found and reported 0 problems.
|
|
|
|
22.45. Executing TECHMAP pass (map to technology primitives).
|
|
|
|
22.45.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/latches_map.v
|
|
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/latches_map.v' to AST representation.
|
|
Generating RTLIL representation for module `$_DLATCH_N_'.
|
|
Generating RTLIL representation for module `$_DLATCH_P_'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
22.45.2. Continuing TECHMAP pass.
|
|
No more expansions possible.
|
|
<suppressed ~4 debug messages>
|
|
|
|
22.46. Executing ABC9 pass.
|
|
|
|
22.46.1. Executing ABC9_OPS pass (helper functions for ABC9).
|
|
|
|
22.46.2. Executing ABC9_OPS pass (helper functions for ABC9).
|
|
|
|
22.46.3. Executing SCC pass (detecting logic loops).
|
|
Found 0 SCCs in module spi_neuron_top.
|
|
Found 0 SCCs.
|
|
|
|
22.46.4. Executing ABC9_OPS pass (helper functions for ABC9).
|
|
|
|
22.46.5. Executing TECHMAP pass (map to technology primitives).
|
|
|
|
22.46.5.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/techmap.v
|
|
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/techmap.v' to AST representation.
|
|
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
|
|
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
|
|
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
|
|
Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
|
|
Generating RTLIL representation for module `\_90_simplemap_various'.
|
|
Generating RTLIL representation for module `\_90_simplemap_registers'.
|
|
Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
|
|
Generating RTLIL representation for module `\_90_shift_shiftx'.
|
|
Generating RTLIL representation for module `\_90_fa'.
|
|
Generating RTLIL representation for module `\_90_lcu_brent_kung'.
|
|
Generating RTLIL representation for module `\_90_alu'.
|
|
Generating RTLIL representation for module `\_90_macc'.
|
|
Generating RTLIL representation for module `\_90_alumacc'.
|
|
Generating RTLIL representation for module `$__div_mod_u'.
|
|
Generating RTLIL representation for module `$__div_mod_trunc'.
|
|
Generating RTLIL representation for module `\_90_div'.
|
|
Generating RTLIL representation for module `\_90_mod'.
|
|
Generating RTLIL representation for module `$__div_mod_floor'.
|
|
Generating RTLIL representation for module `\_90_divfloor'.
|
|
Generating RTLIL representation for module `\_90_modfloor'.
|
|
Generating RTLIL representation for module `\_90_pow'.
|
|
Generating RTLIL representation for module `\_90_demux'.
|
|
Generating RTLIL representation for module `\_90_lut'.
|
|
Generating RTLIL representation for module `$connect'.
|
|
Generating RTLIL representation for module `$input_port'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
22.46.5.2. Continuing TECHMAP pass.
|
|
No more expansions possible.
|
|
<suppressed ~165 debug messages>
|
|
|
|
22.46.6. Executing OPT pass (performing simple optimizations).
|
|
|
|
22.46.6.1. Executing OPT_EXPR pass (perform const folding).
|
|
|
|
22.46.6.2. Executing OPT_MERGE pass (detect identical cells).
|
|
Removed a total of 0 cells.
|
|
|
|
22.46.6.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Removed 0 multiplexer ports.
|
|
|
|
22.46.6.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Performed a total of 0 changes.
|
|
|
|
22.46.6.5. Executing OPT_MERGE pass (detect identical cells).
|
|
Removed a total of 0 cells.
|
|
|
|
22.46.6.6. Executing OPT_DFF pass (perform DFF optimizations).
|
|
|
|
22.46.6.7. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
|
|
22.46.6.8. Executing OPT_EXPR pass (perform const folding).
|
|
|
|
22.46.6.9. Finished fast OPT passes. (There is nothing left to do.)
|
|
|
|
22.46.7. Executing TECHMAP pass (map to technology primitives).
|
|
|
|
22.46.7.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/abc9_map.v
|
|
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/abc9_map.v' to AST representation.
|
|
Successfully finished Verilog frontend.
|
|
|
|
22.46.7.2. Continuing TECHMAP pass.
|
|
No more expansions possible.
|
|
<suppressed ~2 debug messages>
|
|
|
|
22.46.8. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/abc9_model.v
|
|
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/abc9_model.v' to AST representation.
|
|
Generating RTLIL representation for module `$__ABC9_DELAY'.
|
|
Generating RTLIL representation for module `$__ABC9_SCC_BREAKER'.
|
|
Generating RTLIL representation for module `$__DFF_N__$abc9_flop'.
|
|
Generating RTLIL representation for module `$__DFF_P__$abc9_flop'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
22.46.9. Executing ABC9_OPS pass (helper functions for ABC9).
|
|
|
|
22.46.10. Executing ABC9_OPS pass (helper functions for ABC9).
|
|
|
|
22.46.11. Executing ABC9_OPS pass (helper functions for ABC9).
|
|
<suppressed ~2 debug messages>
|
|
|
|
22.46.12. Executing AIGMAP pass (map logic to AIG).
|
|
Module spi_neuron_top: replaced 3704 cells with 21043 new cells, skipped 5491 cells.
|
|
replaced 4 cell types:
|
|
371 $_MUX_
|
|
1 $_ORNOT_
|
|
1627 $_OR_
|
|
1705 $_XOR_
|
|
not replaced 4 cell types:
|
|
3579 $_AND_
|
|
473 $_NOT_
|
|
19 $scopeinfo
|
|
1420 TRELLIS_FF
|
|
|
|
22.46.12.1. Executing ABC9_OPS pass (helper functions for ABC9).
|
|
|
|
22.46.12.2. Executing ABC9_OPS pass (helper functions for ABC9).
|
|
|
|
22.46.12.3. Executing XAIGER backend.
|
|
<suppressed ~5 debug messages>
|
|
Extracted 11435 AND gates and 26963 wires from module `spi_neuron_top' to a netlist network with 1425 inputs and 908 outputs.
|
|
|
|
22.46.12.4. Executing ABC9_EXE pass (technology mapping using ABC9).
|
|
|
|
22.46.12.5. Executing ABC9.
|
|
Running ABC command: "<yosys-exe-dir>/yosys-abc" -s -f <abc-temp-dir>/abc.script 2>&1
|
|
ABC: ======== ABC command line "source <abc-temp-dir>/abc.script"
|
|
ABC: + read_lut <abc-temp-dir>/input.lut
|
|
ABC: + read_box <abc-temp-dir>/input.box
|
|
ABC: + &read <abc-temp-dir>/input.xaig
|
|
ABC: + &ps
|
|
ABC: <abc-temp-dir>/input : i/o = 1425/ 908 and = 9965 lev = 97 (7.44) mem = 0.15 MB box = 0 bb = 0
|
|
ABC: + &scorr
|
|
ABC: Warning: The network is combinational.
|
|
ABC: + &sweep
|
|
ABC: + &dc2
|
|
ABC: + &dch -f -r
|
|
ABC: + &ps
|
|
ABC: <abc-temp-dir>/input : i/o = 1425/ 908 and = 11526 lev = 97 (7.46) mem = 0.17 MB ch = 931 box = 0 bb = 0
|
|
ABC: cst = 0 cls = 891 lit = 931 unused = 11129 proof = 0
|
|
ABC: + &if -W 300 -v
|
|
ABC: K = 7. Memory (bytes): Truth = 0. Cut = 76. Obj = 156. Set = 780. CutMin = no
|
|
ABC: Node = 11526. Ch = 891. Total mem = 2.27 MB. Peak cut mem = 0.31 MB.
|
|
ABC: P: Del = 12289.00. Ar = 16299.0. Edge = 18242. Cut = 168161. T = 0.02 sec
|
|
ABC: P: Del = 12216.00. Ar = 16226.0. Edge = 18056. Cut = 167431. T = 0.02 sec
|
|
ABC: P: Del = 12216.00. Ar = 11819.0. Edge = 18447. Cut = 388545. T = 0.04 sec
|
|
ABC: F: Del = 12216.00. Ar = 7390.0. Edge = 13796. Cut = 272811. T = 0.03 sec
|
|
ABC: A: Del = 12216.00. Ar = 6526.0. Edge = 12653. Cut = 260477. T = 0.03 sec
|
|
ABC: A: Del = 12216.00. Ar = 6432.0. Edge = 12517. Cut = 257946. T = 0.03 sec
|
|
ABC: Total time = 0.17 sec
|
|
ABC: + &write -n <abc-temp-dir>/output.aig
|
|
ABC: + &mfs
|
|
ABC: Timing manager is given but there is no GIA of boxes.
|
|
ABC: Error: Abc_FrameUpdateGia(): Transformation has failed.
|
|
ABC: + &ps -l
|
|
ABC: <abc-temp-dir>/input : i/o = 1425/ 908 and = 19099 lev = 97 (7.44) mem = 0.26 MB box = 0 bb = 0
|
|
ABC: Mapping (K=7) : lut = 3151 edge = 12517 lev = 26 (3.53) mem = 0.15 MB
|
|
ABC: LUT = 3151 : 2=701 22.2 % 3=587 18.6 % 4=816 25.9 % 5=454 14.4 % 6=331 10.5 % 7=262 8.3 % Ave = 3.97
|
|
ABC: + &write -n <abc-temp-dir>/output.aig
|
|
ABC: + &verify
|
|
ABC: Networks are equivalent. Time = 0.49 sec
|
|
ABC: + time
|
|
ABC: elapse: 1.25 seconds, total: 1.25 seconds
|
|
|
|
22.46.12.6. Executing AIGER frontend.
|
|
<suppressed ~8 debug messages>
|
|
Removed 32017 unused cells and 34035 unused wires.
|
|
|
|
22.46.12.7. Executing ABC_OPS_REINTEGRATE pass (reintegrate ABC mapped design into module).
|
|
ABC RESULTS: $lut cells: 3155
|
|
ABC RESULTS: input signals: 114
|
|
ABC RESULTS: output signals: 627
|
|
<suppressed ~4666 debug messages>
|
|
Removing temp directory.
|
|
|
|
22.46.13. Executing TECHMAP pass (map to technology primitives).
|
|
|
|
22.46.13.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/abc9_unmap.v
|
|
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/abc9_unmap.v' to AST representation.
|
|
Generating RTLIL representation for module `$__DFF_x__$abc9_flop'.
|
|
Generating RTLIL representation for module `$__ABC9_SCC_BREAKER'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
22.46.13.2. Continuing TECHMAP pass.
|
|
No more expansions possible.
|
|
<suppressed ~5 debug messages>
|
|
Removed 262 unused cells and 30890 unused wires.
|
|
|
|
22.47. Executing TECHMAP pass (map to technology primitives).
|
|
|
|
22.47.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v
|
|
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v' to AST representation.
|
|
Generating RTLIL representation for module `$_DFF_N_'.
|
|
Generating RTLIL representation for module `$_DFF_P_'.
|
|
Generating RTLIL representation for module `$_DFFE_NN_'.
|
|
Generating RTLIL representation for module `$_DFFE_PN_'.
|
|
Generating RTLIL representation for module `$_DFFE_NP_'.
|
|
Generating RTLIL representation for module `$_DFFE_PP_'.
|
|
Generating RTLIL representation for module `$_DFF_NP0_'.
|
|
Generating RTLIL representation for module `$_DFF_NP1_'.
|
|
Generating RTLIL representation for module `$_DFF_PP0_'.
|
|
Generating RTLIL representation for module `$_DFF_PP1_'.
|
|
Generating RTLIL representation for module `$_SDFF_NP0_'.
|
|
Generating RTLIL representation for module `$_SDFF_NP1_'.
|
|
Generating RTLIL representation for module `$_SDFF_PP0_'.
|
|
Generating RTLIL representation for module `$_SDFF_PP1_'.
|
|
Generating RTLIL representation for module `$_DFFE_NP0P_'.
|
|
Generating RTLIL representation for module `$_DFFE_NP1P_'.
|
|
Generating RTLIL representation for module `$_DFFE_PP0P_'.
|
|
Generating RTLIL representation for module `$_DFFE_PP1P_'.
|
|
Generating RTLIL representation for module `$_DFFE_NP0N_'.
|
|
Generating RTLIL representation for module `$_DFFE_NP1N_'.
|
|
Generating RTLIL representation for module `$_DFFE_PP0N_'.
|
|
Generating RTLIL representation for module `$_DFFE_PP1N_'.
|
|
Generating RTLIL representation for module `$_SDFFE_NP0P_'.
|
|
Generating RTLIL representation for module `$_SDFFE_NP1P_'.
|
|
Generating RTLIL representation for module `$_SDFFE_PP0P_'.
|
|
Generating RTLIL representation for module `$_SDFFE_PP1P_'.
|
|
Generating RTLIL representation for module `$_SDFFE_NP0N_'.
|
|
Generating RTLIL representation for module `$_SDFFE_NP1N_'.
|
|
Generating RTLIL representation for module `$_SDFFE_PP0N_'.
|
|
Generating RTLIL representation for module `$_SDFFE_PP1N_'.
|
|
Generating RTLIL representation for module `$_ALDFF_NP_'.
|
|
Generating RTLIL representation for module `$_ALDFF_PP_'.
|
|
Generating RTLIL representation for module `$_ALDFFE_NPN_'.
|
|
Generating RTLIL representation for module `$_ALDFFE_NPP_'.
|
|
Generating RTLIL representation for module `$_ALDFFE_PPN_'.
|
|
Generating RTLIL representation for module `$_ALDFFE_PPP_'.
|
|
Generating RTLIL representation for module `\FD1P3AX'.
|
|
Generating RTLIL representation for module `\FD1P3AY'.
|
|
Generating RTLIL representation for module `\FD1P3BX'.
|
|
Generating RTLIL representation for module `\FD1P3DX'.
|
|
Generating RTLIL representation for module `\FD1P3IX'.
|
|
Generating RTLIL representation for module `\FD1P3JX'.
|
|
Generating RTLIL representation for module `\FD1S3AX'.
|
|
Generating RTLIL representation for module `\FD1S3AY'.
|
|
Generating RTLIL representation for module `\FD1S3BX'.
|
|
Generating RTLIL representation for module `\FD1S3DX'.
|
|
Generating RTLIL representation for module `\FD1S3IX'.
|
|
Generating RTLIL representation for module `\FD1S3JX'.
|
|
Generating RTLIL representation for module `\IFS1P3BX'.
|
|
Generating RTLIL representation for module `\IFS1P3DX'.
|
|
Generating RTLIL representation for module `\IFS1P3IX'.
|
|
Generating RTLIL representation for module `\IFS1P3JX'.
|
|
Generating RTLIL representation for module `\OFS1P3BX'.
|
|
Generating RTLIL representation for module `\OFS1P3DX'.
|
|
Generating RTLIL representation for module `\OFS1P3IX'.
|
|
Generating RTLIL representation for module `\OFS1P3JX'.
|
|
Generating RTLIL representation for module `\IB'.
|
|
Generating RTLIL representation for module `\IBPU'.
|
|
Generating RTLIL representation for module `\IBPD'.
|
|
Generating RTLIL representation for module `\OB'.
|
|
Generating RTLIL representation for module `\OBZ'.
|
|
Generating RTLIL representation for module `\OBZPU'.
|
|
Generating RTLIL representation for module `\OBZPD'.
|
|
Generating RTLIL representation for module `\OBCO'.
|
|
Generating RTLIL representation for module `\BB'.
|
|
Generating RTLIL representation for module `\BBPU'.
|
|
Generating RTLIL representation for module `\BBPD'.
|
|
Generating RTLIL representation for module `\ILVDS'.
|
|
Generating RTLIL representation for module `\OLVDS'.
|
|
Generating RTLIL representation for module `$lut'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
22.47.2. Continuing TECHMAP pass.
|
|
Using template $paramod$d2706028118fd005e7450620f296d5b71156007d$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0001 for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01010011 for cells of type $lut.
|
|
Using template $paramod$fc6feb7ca0813ec6f9a6e104d2344b22630ad56a$lut for cells of type $lut.
|
|
Using template $paramod$6c32c5350840a7c9517f0d4121fba5c7248e9cd9$lut for cells of type $lut.
|
|
Using template $paramod$bcfa3a9d7fc9307b720401d437d1b7293fda0772$lut for cells of type $lut.
|
|
Using template $paramod$49daaa3151d04372ee2c0f64493bdd6fa0958f0d$lut for cells of type $lut.
|
|
Using template $paramod$ed8c03ad511f650cbc130404bfb483f77070eec3$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1000 for cells of type $lut.
|
|
Using template $paramod$5ced6aec9f7868698df267e83240fd84df81d1e9$lut for cells of type $lut.
|
|
Using template $paramod$30812a483b9068dc921626e3a4f302d54b70676a$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0110 for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10100110 for cells of type $lut.
|
|
Using template $paramod$d50acc7fb62b47e6057453527e351002ea7460d7$lut for cells of type $lut.
|
|
Using template $paramod$c39cf51e421cb703511090a7fcc264780c37d0f3$lut for cells of type $lut.
|
|
Using template $paramod$94fa19656a0f86c1a48ba0da5cc2525fc4c84311$lut for cells of type $lut.
|
|
Using template $paramod$e6169e7dd4da29ac27323558f96ff7abb20790dd$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01101001 for cells of type $lut.
|
|
Using template $paramod$634b76010884c93aa39ceb05c7c3755e34e7e4e9$lut for cells of type $lut.
|
|
Using template $paramod$a34b2af4b04eac866cfd8192d6d26f2a78ec48b5$lut for cells of type $lut.
|
|
Using template $paramod$dd47dcf493eab40808a04b86d3afaf501a4a7a5b$lut for cells of type $lut.
|
|
Using template $paramod$61c387311e0b7b1481f282cf3d339bc22e86cf60$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10011100 for cells of type $lut.
|
|
Using template $paramod$62fd01bf9487be2a6ce42bf75d5c83edbd636ad3$lut for cells of type $lut.
|
|
Using template $paramod$5829f5d2a4c5757263ee6385c6142d3c7cf9e5be$lut for cells of type $lut.
|
|
Using template $paramod$f466b24608bff90d4920f9d0bd1ba6912e707115$lut for cells of type $lut.
|
|
Using template $paramod$2fc5769f61bcdc4b8a34d6b27dd36e546baa75ac$lut for cells of type $lut.
|
|
Using template $paramod$d336aab779d23a0b6de03fca1716d09c9b8a1f77$lut for cells of type $lut.
|
|
Using template $paramod$f70269f202d4dce0365aebaed07094a4216142a8$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11100001 for cells of type $lut.
|
|
Using template $paramod$4664abeb1b30e94d123f8b3c5c3cb28bd0658846$lut for cells of type $lut.
|
|
Using template $paramod$62423d24853354285e811f5295e201dfab27e9a1$lut for cells of type $lut.
|
|
Using template $paramod$38e59850b72f4322e1ef8d4e95edd4b9b3092d0c$lut for cells of type $lut.
|
|
Using template $paramod$e65d8673490e651077bba169b274edbc4886cec5$lut for cells of type $lut.
|
|
Using template $paramod$e05138a447a72bd68c2d3b14da95b662aadd2926$lut for cells of type $lut.
|
|
Using template $paramod$dceb3ccb2fb46fcc5daf0692f4186bd664cd964f$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10010110 for cells of type $lut.
|
|
Using template $paramod$98a1d85b794f76bcbee32a84820fea5f6ddf6ea9$lut for cells of type $lut.
|
|
Using template $paramod$23af449acac76a041e3a207dd114e9e9ca83cf39$lut for cells of type $lut.
|
|
Using template $paramod$4c5136c2ed71d359e368c93f97ebbe23d0db589d$lut for cells of type $lut.
|
|
Using template $paramod$0c42aa2d810e617c3a061a5c3b298929baf96983$lut for cells of type $lut.
|
|
Using template $paramod$29f8e8d81860939642ad82bb36af3cbb544c3dea$lut for cells of type $lut.
|
|
Using template $paramod$2ea69c779d6c1b79ac5a87b0d1523c67d5628dba$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00001101 for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10011010 for cells of type $lut.
|
|
Using template $paramod$7d4170c04f817382b86ae1ec8336149c8b9c0e17$lut for cells of type $lut.
|
|
Using template $paramod$74896d5916b54059928d3e3a06a0d62a2b582a8d$lut for cells of type $lut.
|
|
Using template $paramod$5e879dc6c377dff2247b47adfb160fb82db5338f$lut for cells of type $lut.
|
|
Using template $paramod$98d40e23bb57d56e14345fb0942003de3e361f25$lut for cells of type $lut.
|
|
Using template $paramod$39d49f5eca1046549ce8acf11954c5b95fad7033$lut for cells of type $lut.
|
|
Using template $paramod$c80a15445dea4d9ea03bce7bc3cda507b32f6a28$lut for cells of type $lut.
|
|
Using template $paramod$3c7d59373c2f5f76844cdd2260010db21dd91810$lut for cells of type $lut.
|
|
Using template $paramod$f6bc77281b5396abb889842ec38cef5624b7d7a1$lut for cells of type $lut.
|
|
Using template $paramod$cc2aed4fef24762c7fd3f13ef75c76fd9c6a6f7f$lut for cells of type $lut.
|
|
Using template $paramod$3fbf9e179448527cc5870685155541058c0f9f7a$lut for cells of type $lut.
|
|
Using template $paramod$0d6ad13cc9bc63f1c46ce742dd55221ea1ac81cc$lut for cells of type $lut.
|
|
Using template $paramod$fd904e9e35cfd343a9df248824bd3f1408724879$lut for cells of type $lut.
|
|
Using template $paramod$537fdb28773a04d74588a1a929f87f803030b7f1$lut for cells of type $lut.
|
|
Using template $paramod$20dfb315e479042f47bf4256d9fefd2a8ab30a30$lut for cells of type $lut.
|
|
Using template $paramod$4282def8dbd6df3d1248ad282c629bee684502c2$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1001 for cells of type $lut.
|
|
Using template $paramod$21a9cf1c7cffed4ea7970972274e8bcced7c7005$lut for cells of type $lut.
|
|
Using template $paramod$32f5638f44492ee6293e9b257f28b9d2e15725ec$lut for cells of type $lut.
|
|
Using template $paramod$a50d8417db0f3a51891af8670e611f7f89ddeef4$lut for cells of type $lut.
|
|
Using template $paramod$9ce74923d452e8ee5688d8c41f43809d13df6a83$lut for cells of type $lut.
|
|
Using template $paramod$3f6fe0730f7978b946a57d55a78e206b053e637b$lut for cells of type $lut.
|
|
Using template $paramod$e9150f5ced6676f65b462943f111eaa0be71b7a4$lut for cells of type $lut.
|
|
Using template $paramod$e57dc1cede992b8185c4997780171c27cc6c58cb$lut for cells of type $lut.
|
|
Using template $paramod$734a8728c6fe40bda88b802e90e6e88fa1136b6e$lut for cells of type $lut.
|
|
Using template $paramod$2083f68b8cb0fc15c613b9fb9cf2127f5d8ee68d$lut for cells of type $lut.
|
|
Using template $paramod$307a28c095e824c1a92aac913d3773bcacda6f1e$lut for cells of type $lut.
|
|
Using template $paramod$89f931611b66d827751f4a175a88569d5ab95376$lut for cells of type $lut.
|
|
Using template $paramod$91427c780b4f46cd7bfe44375b61f1cddc9adf19$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000110 for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01000000 for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00010000 for cells of type $lut.
|
|
Using template $paramod$14c020ea613cb578a2526fa309c43212857e809f$lut for cells of type $lut.
|
|
Using template $paramod$8c86d63c8929a00d981a0f29330a873977c1ec84$lut for cells of type $lut.
|
|
Using template $paramod$d1e338e2a0496e2460cbc937540aee0394f830ee$lut for cells of type $lut.
|
|
Using template $paramod$f5c97e291c8b48d9f1b4239d871ab7639e5a24ac$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00010111 for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01001101 for cells of type $lut.
|
|
Using template $paramod$610895a8fdbf27a4d2da55f6513bb969354802ea$lut for cells of type $lut.
|
|
Using template $paramod$19f4c7cebef5466abeaff1137aadb472bf2ce597$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01110001 for cells of type $lut.
|
|
Using template $paramod$168828235b92dfb79376e0213763e466227d8c82$lut for cells of type $lut.
|
|
Using template $paramod$6d0f2c7158bc972797c0d51462b98fa376a63bdc$lut for cells of type $lut.
|
|
Using template $paramod$9ac03d5a97ea51a4907c40833f602372ed14f1ee$lut for cells of type $lut.
|
|
Using template $paramod$1c9e4b349de713b7b8551490e2e4810f31ed0e29$lut for cells of type $lut.
|
|
Using template $paramod$467d00627adf84eeb2da23a0dc015a4e83007bd5$lut for cells of type $lut.
|
|
Using template $paramod$2b2a4049dfa1b42607c2e74d1b62a88c2a5ce534$lut for cells of type $lut.
|
|
Using template $paramod$37d10916fe4d994cb00a883cdc2729a94b70e1bd$lut for cells of type $lut.
|
|
Using template $paramod$224de90f36f271e77aaab29f196b066b5070f8db$lut for cells of type $lut.
|
|
Using template $paramod$34381cfcbc83cddaa163bf4909fba3e7f04244d9$lut for cells of type $lut.
|
|
Using template $paramod$23953811f9a1e831a4c3afa54c7c0c00652edb7e$lut for cells of type $lut.
|
|
Using template $paramod$181f30a7f6b9865a9b16f988bd19adae2574284e$lut for cells of type $lut.
|
|
Using template $paramod$88fe8b4789b978c5cc4358a8f963d7786a28863c$lut for cells of type $lut.
|
|
Using template $paramod$c9d836ff5626f46164609b124ef8e155dba81adc$lut for cells of type $lut.
|
|
Using template $paramod$5cbf84ab48392a78ecda07bfdaaf5624bca8a179$lut for cells of type $lut.
|
|
Using template $paramod$08780779b300cf39ace10e3f96daa6e6285b7fe8$lut for cells of type $lut.
|
|
Using template $paramod$91ab9183084edb3d5e9dde9687e5a09e3808af20$lut for cells of type $lut.
|
|
Using template $paramod$059cc8cde48a0e9aa753eec71c2bc136c4667f47$lut for cells of type $lut.
|
|
Using template $paramod$56f9c7dcfe728ce42b1c29683c97d6f3f310bd67$lut for cells of type $lut.
|
|
Using template $paramod$218f2ad4b58608d5874c86dc4c3964787428f910$lut for cells of type $lut.
|
|
Using template $paramod$4bc1376624d72ad09a85f49bcb18bc9f85cffb7e$lut for cells of type $lut.
|
|
Using template $paramod$f38eb55540991c10fc1fea51759f9af8ad1893ec$lut for cells of type $lut.
|
|
Using template $paramod$c904c31930f461f85cc8ad05b26e4f78cadb815e$lut for cells of type $lut.
|
|
Using template $paramod$bbd9acbda2023ebb825d6ba5889520ded40a6d8c$lut for cells of type $lut.
|
|
Using template $paramod$f298c75fdc43c1cd093638bbb70b8a65486cd01b$lut for cells of type $lut.
|
|
Using template $paramod$4a5d26ac9e2ac9a0e0f4439f9789fcfd50e9a7b3$lut for cells of type $lut.
|
|
Using template $paramod$a656e4fc1ee33b02b80b6d81bc36586fd85648c5$lut for cells of type $lut.
|
|
Using template $paramod$4add378ab6d468705482af50ee8a161e31c5bb97$lut for cells of type $lut.
|
|
Using template $paramod$6e50534e93e6d70b225edf3b490981d5ba7c298d$lut for cells of type $lut.
|
|
Using template $paramod$31ea6763a3e1b0d18ee70244c483d9c522517ac3$lut for cells of type $lut.
|
|
Using template $paramod$11a49243691dd6fdc3df957107812275e2bd2aa8$lut for cells of type $lut.
|
|
Using template $paramod$b0a1a60564bf9a70cd83ff82c322d8476b608c8d$lut for cells of type $lut.
|
|
Using template $paramod$d755920e9eb3a95857b2c051dfc7ca1774f1081b$lut for cells of type $lut.
|
|
Using template $paramod$276b4b800477467287aa335ab75ec7a48300029d$lut for cells of type $lut.
|
|
Using template $paramod$c0afecef24c4f0c99b55d9dd5ecdde6e7eede546$lut for cells of type $lut.
|
|
Using template $paramod$ecfb634e52280d856fe3ba0734eb4fbc7aad0a8a$lut for cells of type $lut.
|
|
Using template $paramod$bd02f96aaa692aaa273a3bd0cf938457b0b516f9$lut for cells of type $lut.
|
|
Using template $paramod$12c369b9066f1ff5c587f79013effb1d8f94b0e8$lut for cells of type $lut.
|
|
Using template $paramod$558772b076c2cdf81c0c2c63608b82790d3b7ee4$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0100 for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00001110 for cells of type $lut.
|
|
Using template $paramod$f1029f646005abda698426a043a7c8fe4e2bd078$lut for cells of type $lut.
|
|
Using template $paramod$2cd56f4a8a5a71c5d234fe1a410d00e03c68d5ba$lut for cells of type $lut.
|
|
Using template $paramod$dc15832db2e16ff856d61daee6c300709999d75c$lut for cells of type $lut.
|
|
Using template $paramod$510a2ebe12b7cfb51a6dbcbfff839db48f3617c8$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0010 for cells of type $lut.
|
|
Using template $paramod$10a6d42c84663fca6c1622800fdec61acbd34667$lut for cells of type $lut.
|
|
Using template $paramod$48858a0cdda2de6934604a272e0a7e64a67fda48$lut for cells of type $lut.
|
|
Using template $paramod$5ba33a01ed090be98a3db1a7eaa124e470e0155f$lut for cells of type $lut.
|
|
Using template $paramod$a5dd40e72dc72c220b09ca0007541916024d0ac8$lut for cells of type $lut.
|
|
Using template $paramod$42164d6a2ae3f57d835829c4039fd2103e656214$lut for cells of type $lut.
|
|
Using template $paramod$970b149f7ff8e7a3dc62cb73b285391fdd5c44dc$lut for cells of type $lut.
|
|
Using template $paramod$1801fa6c6ee8a0d4f4253920223e889199182cc3$lut for cells of type $lut.
|
|
Using template $paramod$a2f3b410c79185949604f844704ae861e73889af$lut for cells of type $lut.
|
|
Using template $paramod$96812b2e7514cd5246a9433e71abec6e62271ab6$lut for cells of type $lut.
|
|
Using template $paramod$7d0749328a13c5a3a965480ac7736dbf8934708f$lut for cells of type $lut.
|
|
Using template $paramod$06f9f3aa8c5f5d33f2e885397b552711eb01bdd8$lut for cells of type $lut.
|
|
Using template $paramod$106af4d385b94e84bbd39f23c7196268b186b7a1$lut for cells of type $lut.
|
|
Using template $paramod$61af77eed7f358aa49c13132fc0b60ac3ba6c211$lut for cells of type $lut.
|
|
Using template $paramod$eb325f7ab9bff48ec9f667250aca37c095c8ecbb$lut for cells of type $lut.
|
|
Using template $paramod$991f2d26b50f4e3cea06d96a2cbaa0fcbc57cb70$lut for cells of type $lut.
|
|
Using template $paramod$b2077130d89736f5191d0d24f7f6ffd3bddb0a2d$lut for cells of type $lut.
|
|
Using template $paramod$31463559093d204ec219d751ebf37e3917952892$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00101011 for cells of type $lut.
|
|
Using template $paramod$80156a53c7dcf801cf3b4f1eea5d36060b5c55da$lut for cells of type $lut.
|
|
Using template $paramod$d6d1743bcffea08a1eea806b0b643d4ebe596df6$lut for cells of type $lut.
|
|
Using template $paramod$986bdc1b77bef3d2ca7cd5ade465cc0edaa7fc63$lut for cells of type $lut.
|
|
Using template $paramod$68d53a054b21edc0f9e3cf5af6f48cf12bc09c73$lut for cells of type $lut.
|
|
Using template $paramod$38081bc0e5b4a95f09789ff5ea3a8af81be33298$lut for cells of type $lut.
|
|
Using template $paramod$71488e4328fc30b316694302bd47d46fd0d52aa2$lut for cells of type $lut.
|
|
Using template $paramod$b7240117ff30e58db286ec740978de37850add78$lut for cells of type $lut.
|
|
Using template $paramod$9b2e1e19823fd9b8a87043b4d72345031957e93a$lut for cells of type $lut.
|
|
Using template $paramod$76ea0c1764468bda9b95c1f2b5bd831ab96d5fdd$lut for cells of type $lut.
|
|
Using template $paramod$de6180548792469f9c7e44dc56570744442e3a32$lut for cells of type $lut.
|
|
Using template $paramod$3ae3d53afe545bb2a8adcc2874a38320b5cf963b$lut for cells of type $lut.
|
|
Using template $paramod$67dd3ecca7baf2d962d41528a49ac740ec345653$lut for cells of type $lut.
|
|
Using template $paramod$f0653663d80ccfa3d2009570397535f0ef10cf47$lut for cells of type $lut.
|
|
Using template $paramod$e6bbd40c9f0b30f47733ab0440f95108ae3662c1$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11010100 for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01100000 for cells of type $lut.
|
|
Using template $paramod$7ef1ef525d09737bac8c1cb910238929cb4b2cf6$lut for cells of type $lut.
|
|
Using template $paramod$3f69e664f882c72c50f4cdc3ccd182259489e568$lut for cells of type $lut.
|
|
Using template $paramod$fd24ba8adbaf0b75005db1aa455afcfc2d436527$lut for cells of type $lut.
|
|
Using template $paramod$12df206ad8f700b41ff9e3425e770a2f97b4fc82$lut for cells of type $lut.
|
|
Using template $paramod$6e86fa9c7ec410d1b2b53d0395fb15a3abbdd8c5$lut for cells of type $lut.
|
|
Using template $paramod$34e58a2dab59796d38609a7fea01c3cd248cb5b8$lut for cells of type $lut.
|
|
Using template $paramod$78560d1e7fdb05910596a5c2828247a1ae48c179$lut for cells of type $lut.
|
|
Using template $paramod$9e7947d656aaef7c37cea4197ed323f24eae80a6$lut for cells of type $lut.
|
|
Using template $paramod$c0341fe0d8fa7322e3a621daa5fa8dd24c97627d$lut for cells of type $lut.
|
|
Using template $paramod$dd966daad423828f5a50694548850343f02adf76$lut for cells of type $lut.
|
|
Using template $paramod$67ffaf7f3fd04e034ef527a00d127f5bb4ef05ca$lut for cells of type $lut.
|
|
Using template $paramod$7b8155ba6ae4c7899ed5695ad3869f745590beb7$lut for cells of type $lut.
|
|
Using template $paramod$8dfe5d519a40d500cedc92f1cbab320a2987cd71$lut for cells of type $lut.
|
|
Using template $paramod$7e45e6d16392b4da8e70d5ab6545c9f7dced0ad0$lut for cells of type $lut.
|
|
Using template $paramod$ce60df3bbf1c70e825d52106f65b80e124ce440e$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01001000 for cells of type $lut.
|
|
Using template $paramod$f785706a0fd8c7911af7ba9ad71622479468a942$lut for cells of type $lut.
|
|
Using template $paramod$f5087c93ce5a3125685165f3416a0110e2b3d539$lut for cells of type $lut.
|
|
Using template $paramod$a7defd4f918862a5b442f9ecbddab049665c36c4$lut for cells of type $lut.
|
|
Using template $paramod$bd7578d8ce3e2437ea907b1d5f654d907114be68$lut for cells of type $lut.
|
|
Using template $paramod$f91974ed76679978bb5ed737ed2baef1784b50ab$lut for cells of type $lut.
|
|
Using template $paramod$f862d87c91b249b16d83d2fee7b9e7497f99519a$lut for cells of type $lut.
|
|
Using template $paramod$88754c52ccda9c40230e2061491e26cc9fad291e$lut for cells of type $lut.
|
|
Using template $paramod$5e40e99250530c5e8dad149036cc18ba8f448e52$lut for cells of type $lut.
|
|
Using template $paramod$71a58fb948c6ddfcbfd5eebfde56855deeed51d9$lut for cells of type $lut.
|
|
Using template $paramod$658b9ed803f0d3d335616d3858b53e0a2522f1e8$lut for cells of type $lut.
|
|
Using template $paramod$13c8ba777686657d21451bc82e62943f1a8ed648$lut for cells of type $lut.
|
|
Using template $paramod$5964dec528c7ded1ee9f528024feacf1107270a1$lut for cells of type $lut.
|
|
Using template $paramod$69f20e0703606f2ffd2ee27cd26f815bd5eeb6e9$lut for cells of type $lut.
|
|
Using template $paramod$bf0d22492b141397adcabc2e359ee0f860225fa5$lut for cells of type $lut.
|
|
Using template $paramod$9ea8ffee254f62629dd5d9acf87f7fade9d974bd$lut for cells of type $lut.
|
|
Using template $paramod$7162854acbcbb36033157818610f5e2f930c8783$lut for cells of type $lut.
|
|
Using template $paramod$35100bef3ae72d423ca869e61aecce0324b5beff$lut for cells of type $lut.
|
|
Using template $paramod$65a91ad2b16e43f528ed91aeb664601dd86616c5$lut for cells of type $lut.
|
|
Using template $paramod$c707bcf35ed8d2e65288948ef818d949e7bfb2c0$lut for cells of type $lut.
|
|
Using template $paramod$729aa850e969bb9bb1c205734876853e142656d4$lut for cells of type $lut.
|
|
Using template $paramod$a2b6873a8a225d2f4785edab35223a2339c153c3$lut for cells of type $lut.
|
|
Using template $paramod$c2d2e49550b9f972f03b0b50b3c90b8accd21335$lut for cells of type $lut.
|
|
Using template $paramod$d0804066a17bad877090a487367af7f49ee4b4c8$lut for cells of type $lut.
|
|
Using template $paramod$6c2ff5db04c3e2dc130157a6346f7f4c773861a1$lut for cells of type $lut.
|
|
Using template $paramod$51cce956e3787a5343180a9fb6ef91d9f3ad5dd8$lut for cells of type $lut.
|
|
Using template $paramod$ef3bcc46fb187f71f388f292fa3d05b3effd06c0$lut for cells of type $lut.
|
|
Using template $paramod$fde5000c4ec2ff76bd9e13a402f841293fc2d9d7$lut for cells of type $lut.
|
|
Using template $paramod$95d610b7cde71a8117e187cb1afc395c65ffdb27$lut for cells of type $lut.
|
|
Using template $paramod$9f6e5a164bd392e913b309507410922801688c11$lut for cells of type $lut.
|
|
Using template $paramod$986ae3d0e2afdda11b8a85123b334c6f534e9b2b$lut for cells of type $lut.
|
|
Using template $paramod$e64a3feba2a33df87f0169fedf41891f4633a20b$lut for cells of type $lut.
|
|
Using template $paramod$990755b3af3216e4f5ba0b4ff9a87f0511cfb89b$lut for cells of type $lut.
|
|
Using template $paramod$e3704d25f724ec87227eb692c918af16c5637558$lut for cells of type $lut.
|
|
Using template $paramod$2bdfdda73873e8931790d872b72220895e67fee5$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00010100 for cells of type $lut.
|
|
Using template $paramod$9795421a62d5ac7adf39d2775934b2a77e87deb6$lut for cells of type $lut.
|
|
Using template $paramod$c080b651596ecc27ba0aff2dec713213740aee0f$lut for cells of type $lut.
|
|
Using template $paramod$d89b437f6e04585fb6ec63e66c2a620393b6245e$lut for cells of type $lut.
|
|
Using template $paramod$9d2d51c431b0b64cba43ecafc110603fdeff7831$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11000001 for cells of type $lut.
|
|
Using template $paramod$98cc7036b8e5db607eb2c104230613da86a7114b$lut for cells of type $lut.
|
|
Using template $paramod$2d41e84d8a20fdfcf9ef269ad61c0ae8747d3e8f$lut for cells of type $lut.
|
|
Using template $paramod$1b697e6d706f5f9af60a3855be38f5135af1111d$lut for cells of type $lut.
|
|
Using template $paramod$a9ef7f32d11123563808a6ef9cbe34bf881c90c2$lut for cells of type $lut.
|
|
Using template $paramod$7e32661cfa094ec3351500918eefeef0e4156692$lut for cells of type $lut.
|
|
Using template $paramod$a9719b9eec88f4c364fa9530fab204f94e79380a$lut for cells of type $lut.
|
|
Using template $paramod$f477f498f8199b1cd775777541cfa76d5529fe64$lut for cells of type $lut.
|
|
Using template $paramod$6d3451bdf0bbc52b8ab7921edbbd8d0fcf63e8ba$lut for cells of type $lut.
|
|
Using template $paramod$ae222275c293ebce3eeaee76ec391462c9a85e56$lut for cells of type $lut.
|
|
Using template $paramod$7c7ec6ca7d7d79ede65fdc4f59bb6b5865f20f80$lut for cells of type $lut.
|
|
Using template $paramod$72021975b2025378db0ecc67ed68c27ae5824d67$lut for cells of type $lut.
|
|
Using template $paramod$50d6ecd3c261de977a09fdae75a3e7bd24bbe65f$lut for cells of type $lut.
|
|
Using template $paramod$88e7d7e2025d8ea17ed81362ddfc960bdb390881$lut for cells of type $lut.
|
|
Using template $paramod$05896c1110f557c6a9f9e7ecbe71099ef8aa8d6b$lut for cells of type $lut.
|
|
Using template $paramod$c932cb819d5ae2efe49a66858ab2e320baefeeb4$lut for cells of type $lut.
|
|
Using template $paramod$09f1a2f5281f2db3c2f592061d2159604391fa67$lut for cells of type $lut.
|
|
Using template $paramod$52836aa97b17d07ec23fe2b7525de119f0aab2b4$lut for cells of type $lut.
|
|
Using template $paramod$e85d8e7185253c652e9e38b663f5f40bdcc79bd0$lut for cells of type $lut.
|
|
Using template $paramod$4ff41c6a01734ba087995851f963274840e2b928$lut for cells of type $lut.
|
|
Using template $paramod$ed79033f25ce36bfc4928b5dd7f28842737c4f97$lut for cells of type $lut.
|
|
Using template $paramod$67da7c45d2a9d07010666a265edfa679d5d5f7b0$lut for cells of type $lut.
|
|
Using template $paramod$ce3b4c7f6a76b7e3a68690f0e39ef28ef77e99a0$lut for cells of type $lut.
|
|
Using template $paramod$c4eb6db429bce3963c85f3027edc1ea0505f7512$lut for cells of type $lut.
|
|
Using template $paramod$40e26ecbe3ccc46fcfbcf176ae95d0141635150a$lut for cells of type $lut.
|
|
Using template $paramod$0c627a428e1a5ec9cf47b308abf76ec18fb1758b$lut for cells of type $lut.
|
|
Using template $paramod$704cad882e2bedddf5c55ef18de55c67afe1e0ec$lut for cells of type $lut.
|
|
Using template $paramod$e640fa1287a20a8ad85af9d174ef348eed680d68$lut for cells of type $lut.
|
|
Using template $paramod$857512ea84a5fe5464efcd374b77666399ea78e1$lut for cells of type $lut.
|
|
Using template $paramod$1c348c177c87b6a45a399a194d4c05081b366460$lut for cells of type $lut.
|
|
Using template $paramod$f48bfbefa45c13216169eb3f6bfd33f86a743af6$lut for cells of type $lut.
|
|
Using template $paramod$911665c0d48e7d36f3cdfbbf1121690833f15cfb$lut for cells of type $lut.
|
|
Using template $paramod$c0f39e33befde703f5cd31f97cdafa23bd0f54c3$lut for cells of type $lut.
|
|
Using template $paramod$63dd0d1acaf3837c9483737d833f033d504ceead$lut for cells of type $lut.
|
|
Using template $paramod$c60ee7d4c9d9f26c6dd689357f8e76435885b168$lut for cells of type $lut.
|
|
Using template $paramod$e9a33f8910cac64e236ca6ab60d8f2a37b45ed64$lut for cells of type $lut.
|
|
Using template $paramod$848f0450b4c1911d92229377286eff1dd3d46a0a$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11101010 for cells of type $lut.
|
|
Using template $paramod$14d72975b70f98d25fb9ceff6c84ef8c4e940925$lut for cells of type $lut.
|
|
Using template $paramod$529a467dcdd0201cc0f853bca78501a68d459f13$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10001110 for cells of type $lut.
|
|
Using template $paramod$33afd9492b8e16b2019a7cc48f294a5bf7083e9a$lut for cells of type $lut.
|
|
Using template $paramod$336990e3794d0da41851dd3a164f81100939c30e$lut for cells of type $lut.
|
|
Using template $paramod$9537002533f156972fdfd92bb63b5fa9a9c88e64$lut for cells of type $lut.
|
|
Using template $paramod$270453e5afa31e3bd5e7357176b339514d55ca29$lut for cells of type $lut.
|
|
Using template $paramod$90e787925f20aa88bba625360708336bcbe8b476$lut for cells of type $lut.
|
|
Using template $paramod$9ca114ca71c717fad88e3af80cce24bc82061f7f$lut for cells of type $lut.
|
|
Using template $paramod$480632dc6f7c037df6062cf8bf88300b5262c395$lut for cells of type $lut.
|
|
Using template $paramod$44f5d5cf465bd602770cf7630cf2759e8971307d$lut for cells of type $lut.
|
|
Using template $paramod$8fbefeb634a4a275ce7207ab33dd7f7b52a837d6$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11010010 for cells of type $lut.
|
|
Using template $paramod$c5a8f97851b065b523217fb3187583e41a9bb41f$lut for cells of type $lut.
|
|
Using template $paramod$64cf72dcb4f2fa35b9d0c92f75f3c38ce6ea6fe4$lut for cells of type $lut.
|
|
Using template $paramod$dfc7446ad807e0a330d81dfb6b5ac0362b93cb0a$lut for cells of type $lut.
|
|
Using template $paramod$83e0060b184bd4d2e7b19dc66bfb878dbe678d6f$lut for cells of type $lut.
|
|
Using template $paramod$29658bc1d63574cbf1a532974926e1a5cad395a7$lut for cells of type $lut.
|
|
Using template $paramod$5ce454d1ce61a5f87fed6528e38ca41bdc265667$lut for cells of type $lut.
|
|
Using template $paramod$f58ca59c78d31abeeb2aedeb3ffb27449deffc49$lut for cells of type $lut.
|
|
Using template $paramod$a570d282c3142361076ff3339e402fb592265276$lut for cells of type $lut.
|
|
Using template $paramod$97e64a771338591114331b7605d6dbc3d3d78173$lut for cells of type $lut.
|
|
Using template $paramod$49921e578244afb337210ecb36b5a30be98417f6$lut for cells of type $lut.
|
|
Using template $paramod$58ff13f76f0f650fbed7e392b4debebea6a3fec7$lut for cells of type $lut.
|
|
Using template $paramod$2038e6709cb6ef4662f818e37e0fa90af8ded944$lut for cells of type $lut.
|
|
Using template $paramod$041aa1dcdd60d3c4ff6eb6326c9e544a0334c607$lut for cells of type $lut.
|
|
Using template $paramod$d2910732a79cbdc9d58486a8fa471c924bde24c4$lut for cells of type $lut.
|
|
Using template $paramod$100bcf011625811830c777f75a88a79323b9c6d1$lut for cells of type $lut.
|
|
Using template $paramod$057793edb45db8e7d3f9bfa0748b00ea2917d48b$lut for cells of type $lut.
|
|
Using template $paramod$9ca330ed12b40a064e7e977a60b03ac0299b910d$lut for cells of type $lut.
|
|
Using template $paramod$38ec4e8c9c23b1b17d100e8edc36f66555e44571$lut for cells of type $lut.
|
|
Using template $paramod$61b481f3fd7d0fd09fb1be7f5772ef270eebaa00$lut for cells of type $lut.
|
|
Using template $paramod$1dde36dc1acae67dc9ecd0c41bc23aaf9a5bb20b$lut for cells of type $lut.
|
|
Using template $paramod$6131e956661bb3bee05839db853d8feddb4dff47$lut for cells of type $lut.
|
|
Using template $paramod$5317ac627c175bc8f6fd2e30b19fec7af65eca0c$lut for cells of type $lut.
|
|
Using template $paramod$d2020c7ed1eb8cb08d59e03df00b681379f84f1e$lut for cells of type $lut.
|
|
Using template $paramod$34e4b6bc2e281cce1faf330983c5aa9b4c31b2c9$lut for cells of type $lut.
|
|
Using template $paramod$3496d0bce7bd3b7c87dfd7f2f75e8966e3d81528$lut for cells of type $lut.
|
|
Using template $paramod$22e896f24e3ab1973155760b25574ff826d9cbaa$lut for cells of type $lut.
|
|
Using template $paramod$b86a3846d6a747c30be2ee86f8659babbb6fd592$lut for cells of type $lut.
|
|
Using template $paramod$a24f8def735116860cc6ce2397b991f84a6f0841$lut for cells of type $lut.
|
|
Using template $paramod$30ac566440f0a3c450bcc32ad83ac583c462df11$lut for cells of type $lut.
|
|
Using template $paramod$a41d0e3b97911dca5b893a7d849ab04257ab9d97$lut for cells of type $lut.
|
|
Using template $paramod$a2d793e5d61b71f9b2beeccb844832f4dfeca3cc$lut for cells of type $lut.
|
|
Using template $paramod$66b2a5d2814bdbecd9abf5f86783353a4b58b5c2$lut for cells of type $lut.
|
|
Using template $paramod$5c9d981f79c4f2253671e2dbd39b499f63da5a32$lut for cells of type $lut.
|
|
Using template $paramod$4e787b59391890d26d8e39019a7e30cb821d452f$lut for cells of type $lut.
|
|
Using template $paramod$7e8b87916f806a9726d388c12ae064d6764ff2e6$lut for cells of type $lut.
|
|
Using template $paramod$835f81980fbede0ee8fb9c2b7ec25bba846dbf72$lut for cells of type $lut.
|
|
Using template $paramod$2e242b3870fd1c78b14e7f95ffa17bf0b3a3339c$lut for cells of type $lut.
|
|
Using template $paramod$c49834e615a08368472dfe9f2a6974c544906164$lut for cells of type $lut.
|
|
Using template $paramod$bdc3235c95f053384781b11f7e9f56cce251d777$lut for cells of type $lut.
|
|
Using template $paramod$f9911107f44d9500073730a8958583cf253e5802$lut for cells of type $lut.
|
|
Using template $paramod$15fde79be682b525c5842bf29c7e57f4328035ed$lut for cells of type $lut.
|
|
Using template $paramod$20890b177f1fac49e4c65502f15732c1fe8576d1$lut for cells of type $lut.
|
|
Using template $paramod$6b4c85ba8e079ecc7254f25ce86a7c83250f9836$lut for cells of type $lut.
|
|
Using template $paramod$bd4f8b91b313bf85c49d15c3abe87d1b27ee5444$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000111 for cells of type $lut.
|
|
Using template $paramod$201fe8b51a90a892f1a8d97334cf7aea3336eb5c$lut for cells of type $lut.
|
|
Using template $paramod$4e309f6669eadcfa589d4ae302672e3a030a20a5$lut for cells of type $lut.
|
|
Using template $paramod$604283e00458ca7d6874de7d702927666647dca9$lut for cells of type $lut.
|
|
Using template $paramod$88f339bc3623f3d1e079bdf8f29a450aece995e5$lut for cells of type $lut.
|
|
Using template $paramod$e587b001427d7322a7eccf8ae55ea7a6672c0fd9$lut for cells of type $lut.
|
|
Using template $paramod$1fbfc43e8d9414c743fa9b6b561b663af0f6bdcb$lut for cells of type $lut.
|
|
Using template $paramod$bc48f6d0cbe4088cf52fbe28aaaf0c5e03ea106b$lut for cells of type $lut.
|
|
Using template $paramod$e96de5e9fcce737e52eacf39c70c8f533dc27d63$lut for cells of type $lut.
|
|
Using template $paramod$13a06acca29b7c0bfdcea83e1c76ad7a358f2808$lut for cells of type $lut.
|
|
Using template $paramod$600ac91328c9902b54401401f45387945a57ce34$lut for cells of type $lut.
|
|
Using template $paramod$c8c52431b72b811d16b0555d4d274aca43bb2f09$lut for cells of type $lut.
|
|
Using template $paramod$1e6a59703fbf253b2291f4515d4b76f4cd47615e$lut for cells of type $lut.
|
|
Using template $paramod$ded06e93a694a7efa6c97a5cda26728df6569c98$lut for cells of type $lut.
|
|
Using template $paramod$6f625205336ac6ce7b8747324becdbce1049bc9c$lut for cells of type $lut.
|
|
Using template $paramod$92c3899764cd8074859d6a5a5b733cffe8a391b3$lut for cells of type $lut.
|
|
Using template $paramod$7347a2b57cdc7fd8078666268259a3c819e4f73c$lut for cells of type $lut.
|
|
Using template $paramod$fc00bb0f8c2cd4e80b21e34e6d02820030069f6a$lut for cells of type $lut.
|
|
Using template $paramod$d3f23fbaa1eb69cda229e65d906ec09d7bc67ba4$lut for cells of type $lut.
|
|
Using template $paramod$6e238df02989b317f10820a22773676e71120644$lut for cells of type $lut.
|
|
Using template $paramod$a50be0e6fa3a01511bb234559cb74fb8bd3e2061$lut for cells of type $lut.
|
|
Using template $paramod$f595837b1045925c7b898ea4f81fdb5bf632050e$lut for cells of type $lut.
|
|
Using template $paramod$f6993c1e2a10502e9f414b90ebe970e588917e6a$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00110110 for cells of type $lut.
|
|
Using template $paramod$0456a98798c34601885c32b21888b0cebf125876$lut for cells of type $lut.
|
|
Using template $paramod$3b05ce69402b9fa4320d7ba0b5dbbdce3f2d9804$lut for cells of type $lut.
|
|
Using template $paramod$fbd676b1046f1e90c4f68f8c79b281bde3ffa3a7$lut for cells of type $lut.
|
|
Using template $paramod$7eec9e728d9946d8c7237fe2ae539af0995ca637$lut for cells of type $lut.
|
|
Using template $paramod$53d9c8d53d7e6617004aa7eb64f8a9b8c129cbd4$lut for cells of type $lut.
|
|
Using template $paramod$d49d072cb935c1379d85ecbe3c5c346feb01d42b$lut for cells of type $lut.
|
|
Using template $paramod$b0e0db6dd78b20af88e5fdeaab8456f9b145a6a1$lut for cells of type $lut.
|
|
Using template $paramod$d27dc07c587de415cc34157f091316fd2db38291$lut for cells of type $lut.
|
|
Using template $paramod$a72a6e1ea3bbe5ee469e28178c7723fac5313f63$lut for cells of type $lut.
|
|
Using template $paramod$28e5b7ec316e4642842a9f9c1aeedba32c9fb33d$lut for cells of type $lut.
|
|
Using template $paramod$9eee4c52b8afba0d2c1454313768227d1b82e973$lut for cells of type $lut.
|
|
Using template $paramod$c5ee66eb2a490feb211407baec4a64d121f5aead$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11100100 for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000100 for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10000000 for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01000111 for cells of type $lut.
|
|
Using template $paramod$c1a19a87ccbbb03d43a72335db63f692ddf82cc1$lut for cells of type $lut.
|
|
Using template $paramod$000fa2164e1f538c16460571efee2b6209a086cc$lut for cells of type $lut.
|
|
Using template $paramod$cb92beff9eab733e7181d891fbc8c3950b9abc0a$lut for cells of type $lut.
|
|
Using template $paramod$de52a65f985bb8c1904b1b12752998fc37477714$lut for cells of type $lut.
|
|
Using template $paramod$243fb93e736df5581df7bafa378886f2bdf5bea9$lut for cells of type $lut.
|
|
Using template $paramod$848d2b023321e0badae356e7259e2c767c32a546$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00011011 for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00110101 for cells of type $lut.
|
|
Using template $paramod$71cf1e2581652e1c182b486b69228e5e0d80c23f$lut for cells of type $lut.
|
|
Using template $paramod$173accdd72264e7f28d902e007b63d44962d9678$lut for cells of type $lut.
|
|
Using template $paramod$293f13203b5ac015351d4de0dc2b1f647549f79a$lut for cells of type $lut.
|
|
Using template $paramod$1a64f21ea15b05b7fc930804a66f6689ebbd6394$lut for cells of type $lut.
|
|
Using template $paramod$80bc945f6d438f16387422ec284dc12b4bb4e68f$lut for cells of type $lut.
|
|
Using template $paramod$17f1b90a5c6d7e6613368c5e7d3f44dd634e59e2$lut for cells of type $lut.
|
|
Using template $paramod$df196ed0a1da5c4a58c5e08a1dac304fd3fccaab$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10010000 for cells of type $lut.
|
|
Using template $paramod$485c535cc2fb194dc6f114ba5c93554133564a61$lut for cells of type $lut.
|
|
Using template $paramod$6310694b3b02ffd8eb009d2db3583824c83bc731$lut for cells of type $lut.
|
|
Using template $paramod$ac9e30a76d6b9a46858490d570fa34ecc90414a5$lut for cells of type $lut.
|
|
Using template $paramod$3f0549729b9cf7d6fa6533d688d092bceca9764e$lut for cells of type $lut.
|
|
Using template $paramod$7d97ef8f03249325b519a8117e6765621372a297$lut for cells of type $lut.
|
|
Using template $paramod$22f597b759cdcfc80a35b46254c280c07d56a800$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10110100 for cells of type $lut.
|
|
Using template $paramod$7f0c33ebaba0ede46854143fc6bff56677faafba$lut for cells of type $lut.
|
|
Using template $paramod$0ada316cb4ce314e0242c6d96366a28dea61bbf1$lut for cells of type $lut.
|
|
Using template $paramod$f24d3b3a9a4424b2d12bd4628102c0845eddcbd9$lut for cells of type $lut.
|
|
Using template $paramod$40d52af5a074acbab6a75900455acddeca351844$lut for cells of type $lut.
|
|
Using template $paramod$c627e7fc36fd5f8fca16a74816d11be60e4b9470$lut for cells of type $lut.
|
|
Using template $paramod$b0fa3af98127aacbcb63c3a67cbfa059f6b66881$lut for cells of type $lut.
|
|
Using template $paramod$56932805221de1c6aa0bfe0962b716d72ab710ba$lut for cells of type $lut.
|
|
Using template $paramod$36e94cc1f26df3f9f7724be583f98e9223a4be57$lut for cells of type $lut.
|
|
Using template $paramod$ceda806a15614365c0296faf7ce6406e08af5f22$lut for cells of type $lut.
|
|
Using template $paramod$5ad8ad132dbd8b536e9db6def5eac5358db9caa3$lut for cells of type $lut.
|
|
Using template $paramod$ee43b3a9f27d73f1837ba0af6d9397cadabee8dd$lut for cells of type $lut.
|
|
Using template $paramod$7497a0c5bbd931e9debc133c2a3a4a9272b73a9b$lut for cells of type $lut.
|
|
Using template $paramod$e850b6d88de7519ea447582d9e402ec288ee870e$lut for cells of type $lut.
|
|
Using template $paramod$f3d77c4ba7d266704c2bcdc683b159e5e6610379$lut for cells of type $lut.
|
|
Using template $paramod$a1eb03dbedf56d71b03c2dffc2b92d38cdd89511$lut for cells of type $lut.
|
|
Using template $paramod$395780e50ac47eaba97fa7575c8d360d810322b4$lut for cells of type $lut.
|
|
Using template $paramod$ec260c6f6d38c799e6a0b34193844b3e4cfebd66$lut for cells of type $lut.
|
|
Using template $paramod$6204cb1477b6817575f39c70db34cb0bbff2c9bd$lut for cells of type $lut.
|
|
Using template $paramod$22b9f23591471a38957755ec230a1fb88d88d23b$lut for cells of type $lut.
|
|
Using template $paramod$a52ca690c30036fa7bcad6e5fa639c8b532f2a88$lut for cells of type $lut.
|
|
Using template $paramod$4abb7036e2a0a17603311f3ef2f4d9c681b11e7d$lut for cells of type $lut.
|
|
Using template $paramod$2646d268a64483bb76ff7a850d562d0837419a50$lut for cells of type $lut.
|
|
Using template $paramod$1f15c9a7b5add67417aa9115028050f625d3799d$lut for cells of type $lut.
|
|
Using template $paramod$6411303a6fcba89b59b7cc79cd2216c58a9917a4$lut for cells of type $lut.
|
|
Using template $paramod$e794f5340beae90a14afe300f946770f342b251a$lut for cells of type $lut.
|
|
Using template $paramod$a20d493743c6e762e93052351143ea302aa9a813$lut for cells of type $lut.
|
|
Using template $paramod$c6819da458dc401863a50ee8679e88f019e9000f$lut for cells of type $lut.
|
|
Using template $paramod$01d7e4c46752a9a63aa8c33d8e76e4c25170a6d1$lut for cells of type $lut.
|
|
Using template $paramod$74cd9640fed65427dbc2d98e5888a4cc9bd39f2c$lut for cells of type $lut.
|
|
Using template $paramod$03ef3163104187fab835c6b78d2d229daefca340$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00010010 for cells of type $lut.
|
|
Using template $paramod$52c44a5a4cd712275a4404fc28d7decd55483f31$lut for cells of type $lut.
|
|
Using template $paramod$6c20cd67f54616fdaaf67c3fd197a01f986074b6$lut for cells of type $lut.
|
|
Using template $paramod$d9e5e58ccbe2e7989f8d611ae016c0db99460a7a$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000010 for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1011 for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10101100 for cells of type $lut.
|
|
Using template $paramod$f9813472aa48e533b3838c6f2316dc2e78c66111$lut for cells of type $lut.
|
|
Using template $paramod$f7e977e4ab769956ecac4448595a773db86c44e8$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000001 for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00100000 for cells of type $lut.
|
|
Using template $paramod$101238f3d8d49ab12a9b49a2f01cd503b26e9c61$lut for cells of type $lut.
|
|
Using template $paramod$47a8214374025465e226fa66bee690ff33268a25$lut for cells of type $lut.
|
|
Using template $paramod$873c285bdccf0ac2b60d2304ea5cd14bf211d2a6$lut for cells of type $lut.
|
|
Using template $paramod$1cec58bfb33a7a51c359586aade8e947536c006e$lut for cells of type $lut.
|
|
Using template $paramod$9ce3cb48532e1935dedb6055756fefa71d90eef1$lut for cells of type $lut.
|
|
Using template $paramod$8765b80daad624736bde4934de2726615dda59cd$lut for cells of type $lut.
|
|
Using template $paramod$a99d914c790fb66ebd455749096b4bfb66d050d6$lut for cells of type $lut.
|
|
Using template $paramod$5e917dc4681c7b1e9a844916c6fcd38dea4152e3$lut for cells of type $lut.
|
|
Using template $paramod$51adb1afea57a9560b9534400e9af12cb2df0ba0$lut for cells of type $lut.
|
|
Using template $paramod$59dbfef3d2e0c7721ec21b9ce3ac17369e5a83a5$lut for cells of type $lut.
|
|
Using template $paramod$185d7c9bbdaa7018711d738ae4c61146fdade8ea$lut for cells of type $lut.
|
|
Using template $paramod$95c901695728852369d4b4be4dd0494f93a46cdf$lut for cells of type $lut.
|
|
Using template $paramod$9c6cdad02887f17f1d6f9265e5204359239a1a76$lut for cells of type $lut.
|
|
Using template $paramod$746e079691931a7a75eca548b520591dac2af82b$lut for cells of type $lut.
|
|
Using template $paramod$f3d61162ae96bf57c7a3ced00299ee3aa3ae2194$lut for cells of type $lut.
|
|
Using template $paramod$d04448acbf27092b2b78e72c90465e35168b30fd$lut for cells of type $lut.
|
|
Using template $paramod$60c57a531d15ac3dc4cc2d9845c81479cc8e53ec$lut for cells of type $lut.
|
|
Using template $paramod$b2873a6e0a1e666ef9a611756dd09af9c7a9752e$lut for cells of type $lut.
|
|
Using template $paramod$f5ebeca4cb38ca5246fdacefc3045c9c6b6d1641$lut for cells of type $lut.
|
|
Using template $paramod$4d7f17f71543a1e7fc1835bd79c4827a43f2e844$lut for cells of type $lut.
|
|
Using template $paramod$6cecf0051ac1d444068ae490b01109f8dbad3e3d$lut for cells of type $lut.
|
|
Using template $paramod$acca49b0b50d641cf85a727a03a2d5af4ae645fb$lut for cells of type $lut.
|
|
Using template $paramod$1e9d31fd9d29ec2b288c09d6ff4a2646e026682e$lut for cells of type $lut.
|
|
Using template $paramod$8f924d773a493f12f2d803c732778cdbe05d7173$lut for cells of type $lut.
|
|
Using template $paramod$02136aba093bf21ac0b01bdd0a2dcee1605cab28$lut for cells of type $lut.
|
|
Using template $paramod$43410ecf1cab767369c2a992c645894497981a55$lut for cells of type $lut.
|
|
Using template $paramod$ff16cf61c8d9f62541df761a3819e526d3bc83d2$lut for cells of type $lut.
|
|
Using template $paramod$d348c4ae9ddf77d22c9086454d16f8865662064f$lut for cells of type $lut.
|
|
Using template $paramod$c732c0feaa14d2679271e2d6da10be4d0aa25ed1$lut for cells of type $lut.
|
|
Using template $paramod$010572d7fc837e03f7dcfdac814510a0205f3a9c$lut for cells of type $lut.
|
|
Using template $paramod$896bec26da2a574516185ae45efa51fd98898ae1$lut for cells of type $lut.
|
|
Using template $paramod$4e2f660810cb085c95b5a682c0c8c7573ef75972$lut for cells of type $lut.
|
|
Using template $paramod$8512f4fb47fa9596f76cdbe5b407a5b54df368e7$lut for cells of type $lut.
|
|
Using template $paramod$a9d4626c045bbf11bce3a54cbe613d1ea1f12f80$lut for cells of type $lut.
|
|
Using template $paramod$0350ba3eb6fe68c92ce7b7a0ce391935d90e6a05$lut for cells of type $lut.
|
|
Using template $paramod$ca26c13a6c83a8abf5dd9e6b65ae37cc7e4209cd$lut for cells of type $lut.
|
|
Using template $paramod$f9d3baa294ddcbea473b5410008a92f4fe04b229$lut for cells of type $lut.
|
|
Using template $paramod$b263a528ddd608459d06aa05473d0ad783da878f$lut for cells of type $lut.
|
|
Using template $paramod$859d1e39c227fdb329f552960c701fb05ccfe4b6$lut for cells of type $lut.
|
|
Using template $paramod$8b3e98ea860f76acc00c303e2a8fde875a61c372$lut for cells of type $lut.
|
|
Using template $paramod$2a3341fb2d863a7a4392b5326ddb73c574aae404$lut for cells of type $lut.
|
|
Using template $paramod$540150ec7894dab433d2fb2f72131a5c67c987da$lut for cells of type $lut.
|
|
Using template $paramod$7eef6712db4faa1ab59b37004a6a2395bcc0e357$lut for cells of type $lut.
|
|
Using template $paramod$9660cb063f346fce9f38d616b37e2dab91535d2a$lut for cells of type $lut.
|
|
Using template $paramod$6d6df639895186cae215bde396881d0f3584cf81$lut for cells of type $lut.
|
|
Using template $paramod$65f1888682e6012bb5ad86166f33253b1a6d85b2$lut for cells of type $lut.
|
|
Using template $paramod$470fce5f01c8c2603a8ad5f90ad92c995d6847d6$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00110001 for cells of type $lut.
|
|
Using template $paramod$ccc5a92969fed653528a4e87965452463b0337da$lut for cells of type $lut.
|
|
Using template $paramod$ea4f2cc1b9644b1d417caa08b05cdaea00631aa7$lut for cells of type $lut.
|
|
Using template $paramod$c4123b0e6cf7af91f4d46999579192ff16bdaf2b$lut for cells of type $lut.
|
|
Using template $paramod$5c24efb1ef00c2fbe6898cb18002d4748c418328$lut for cells of type $lut.
|
|
Using template $paramod$3412f2978b7fc15d45f55b18956ffd2b3d05915d$lut for cells of type $lut.
|
|
Using template $paramod$a2b9ebb2b109ae4cce174f260ed0a1a0d0d6abb6$lut for cells of type $lut.
|
|
Using template $paramod$76f2ba42935dc8374c671f36078ef793be1dfc1a$lut for cells of type $lut.
|
|
Using template $paramod$68c9736ac5ca4780d5dcd7208fcc3e84d6fa7bed$lut for cells of type $lut.
|
|
Using template $paramod$8bb7bc4d06ad02cdf8cfed0d3d7d02832237ac4d$lut for cells of type $lut.
|
|
Using template $paramod$1be44086d9a255f8ff8e329ae0dc47216e839387$lut for cells of type $lut.
|
|
Using template $paramod$e36afbc69ef9cf4ecfa3262f9ac282e808c9c8ab$lut for cells of type $lut.
|
|
Using template $paramod$bea08a495d16293f8cc454a45845d26cde0762b6$lut for cells of type $lut.
|
|
Using template $paramod$c7989bc006ecd90852d715116bbb0c2ae5d62f06$lut for cells of type $lut.
|
|
Using template $paramod$8062a4edc83a551cef3aeeeb608a0c1426e28495$lut for cells of type $lut.
|
|
Using template $paramod$d42eecd53258520c422f639f35e962eea893a808$lut for cells of type $lut.
|
|
Using template $paramod$e2a336de569b193d1209067f148a6361513119ec$lut for cells of type $lut.
|
|
Using template $paramod$d23b18db936da6dbffb38d427fd1b308f079a4bf$lut for cells of type $lut.
|
|
Using template $paramod$db611a56de5084e153f5aedddc33ed1a6353da16$lut for cells of type $lut.
|
|
Using template $paramod$80d2c9166243792ad5622183c1c0b2eff6da2b3a$lut for cells of type $lut.
|
|
Using template $paramod$bff81b8b131e270afc60d76d4f58c0b23c97781a$lut for cells of type $lut.
|
|
Using template $paramod$2d08253b9c2a86b2cf86f315a619bb98932f37d2$lut for cells of type $lut.
|
|
Using template $paramod$fd84e06dd1ea35bc37072c5326697d95fbf6c0a7$lut for cells of type $lut.
|
|
Using template $paramod$63114da772fb28945ba24699e32f1e30ca7142f4$lut for cells of type $lut.
|
|
Using template $paramod$68a7a5187a4572d093f6f1e7256743d0a6407aa0$lut for cells of type $lut.
|
|
Using template $paramod$272652f6c6fbe9a75eff76e45cc7e2788835518b$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01110000 for cells of type $lut.
|
|
Using template $paramod$571404c0889eaf57f492cb5e37f8acb5df5852f9$lut for cells of type $lut.
|
|
Using template $paramod$11ec7271d8e6e5aeaace08c13e4c601f10e31038$lut for cells of type $lut.
|
|
Using template $paramod$7e1598d4ad491765d69c7a5c02ece8d7ef10c4d6$lut for cells of type $lut.
|
|
Using template $paramod$9bdc414229f06e785dc8fd97a243faa9336e164a$lut for cells of type $lut.
|
|
Using template $paramod$85b779ce5ab505dbf25e5e046fb43ca2b76b878b$lut for cells of type $lut.
|
|
Using template $paramod$c217e185eb8e6463ca272982ba8c5940fa90d81f$lut for cells of type $lut.
|
|
Using template $paramod$364c9ffbffac467d60dfec81bba4e18476c15602$lut for cells of type $lut.
|
|
Using template $paramod$30305e55a780880b9c824fe3509a4d981acb0f2b$lut for cells of type $lut.
|
|
Using template $paramod$52953750219effadf43093a566baf492fdd6b6c8$lut for cells of type $lut.
|
|
Using template $paramod$fe9a0158d0352193457c4f5b6282ac86d35fb3ee$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1110 for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11110111 for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11111110 for cells of type $lut.
|
|
Using template $paramod$d2db554138a52e6a16d1d732f855e0dfcc227939$lut for cells of type $lut.
|
|
Using template $paramod$fe2f9d17c2190294c981110de3971e10413f1fa6$lut for cells of type $lut.
|
|
Using template $paramod$7db4ad838e04469eaf8239e6b8045b04ce53937e$lut for cells of type $lut.
|
|
Using template $paramod$89e81ec938a5121bf0326afabb244602c5fb5e5e$lut for cells of type $lut.
|
|
Using template $paramod$7eb64b226657f4674ae0077d65976ccd9e7d4a51$lut for cells of type $lut.
|
|
Using template $paramod$738bbefc5da4c42e1062c1164481b705b5ca70a4$lut for cells of type $lut.
|
|
Using template $paramod$113844ddc8f6bcaae9d7d3c32b96ad83b783cb3e$lut for cells of type $lut.
|
|
Using template $paramod$c3e686da84159dd9b9c2ce7d4254235d7b6a16a7$lut for cells of type $lut.
|
|
Using template $paramod$0d8830964af4581fb091e25c07e1e5b90cee5f65$lut for cells of type $lut.
|
|
Using template $paramod$30ce3396a4f454a728b6261a41eaea793c92facd$lut for cells of type $lut.
|
|
Using template $paramod$ebc96d54c58bc295ed1c25971281979887a5ca05$lut for cells of type $lut.
|
|
Using template $paramod$d3949f71f49fbc586e9767c35be678f9222e5866$lut for cells of type $lut.
|
|
Using template $paramod$b156afa1915cc9f694d766c1454f8d3acad84883$lut for cells of type $lut.
|
|
Using template $paramod$dfb26c267cf741f733de1d8d54a7bf2596a93170$lut for cells of type $lut.
|
|
Using template $paramod$845c3c6ab923788679c7336f8060a138570a6f19$lut for cells of type $lut.
|
|
Using template $paramod$7ee02e32164dc82929bceecafae1bd85be8233ff$lut for cells of type $lut.
|
|
Using template $paramod$a67894ba2179e4ea74c29c013f0fc45af06dc1e5$lut for cells of type $lut.
|
|
Using template $paramod$483c970887190dc2321d49de42f65400207671c6$lut for cells of type $lut.
|
|
Using template $paramod$93ab9f081b0d5068b97ddd9b5dd6f8bc79663054$lut for cells of type $lut.
|
|
Using template $paramod$99eccfb38397e0f29bdb9de63eef04becf9f930a$lut for cells of type $lut.
|
|
Using template $paramod$a9571d03d8f092ab38ead3ca6303824be2c981f0$lut for cells of type $lut.
|
|
Using template $paramod$b27834385f52eaf4ed276ecbffb1b05d9c8a8b56$lut for cells of type $lut.
|
|
Using template $paramod$03a95d09d3ad23cff2cfd1e0252a3e3487142c41$lut for cells of type $lut.
|
|
Using template $paramod$c24a31304ce76c390dd484cfecee63738dd16acb$lut for cells of type $lut.
|
|
Using template $paramod$28ba90bb95963b63750b27cda749dbcd75757c3a$lut for cells of type $lut.
|
|
Using template $paramod$b3108a615469edc015754b6128d36e85c6e77cee$lut for cells of type $lut.
|
|
Using template $paramod$c9973847877ada7432713b54689bccc179bb3e79$lut for cells of type $lut.
|
|
Using template $paramod$a1a215291984385cd3400e5e055b0eec2ca38001$lut for cells of type $lut.
|
|
Using template $paramod$fb902bd06e69c18a6a27efd70c9886e1e7cb9b97$lut for cells of type $lut.
|
|
Using template $paramod$3b1afe6a7eda8fed889eae5a33173ccabf5b0aed$lut for cells of type $lut.
|
|
Using template $paramod$000ee3fdb1c02ebf0798cba1c78d898468e8661a$lut for cells of type $lut.
|
|
Using template $paramod$e9a6d92d0c7a91c9d9229a21c0b3e9a45635a79f$lut for cells of type $lut.
|
|
Using template $paramod$d8277bff239ad4b001ab03bca15d0a06663cda74$lut for cells of type $lut.
|
|
Using template $paramod$84ff9e3927ff2b237769aea87b33f256e4fc4feb$lut for cells of type $lut.
|
|
Using template $paramod$a3f0bb3fb5f1d56a06abe36dbd69b9d4c0ed6ad2$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11001000 for cells of type $lut.
|
|
Using template $paramod$d4f02cd09c5bd436c88ff2b2b271e9f8d4922b87$lut for cells of type $lut.
|
|
Using template $paramod$85fc7056898cbfe5cacacbe85d1cb13bd0b142bb$lut for cells of type $lut.
|
|
Using template $paramod$60f06af8637d35dcc2cab38b30e03dc2a88dbed7$lut for cells of type $lut.
|
|
Using template $paramod$38730422ff71627a20e6ac4c3f92e003724b9b88$lut for cells of type $lut.
|
|
Using template $paramod$710f75c3cc9bb1efd57e771d648110b904620cd3$lut for cells of type $lut.
|
|
Using template $paramod$fba030b6f83d058f4eabda3719de30e5e245df39$lut for cells of type $lut.
|
|
Using template $paramod$0f40065aa9b91e6d6fbb247c195f7b54abd3ecbb$lut for cells of type $lut.
|
|
Using template $paramod$a1b5c26a437d3cef171102d9b30f1646e5637d6c$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01010100 for cells of type $lut.
|
|
Using template $paramod$526e4703e3f9e5bf75da836fd3d4410dd76747a6$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11100000 for cells of type $lut.
|
|
Using template $paramod$58373a83b9a757186f5b938df0243166a71f0f0b$lut for cells of type $lut.
|
|
Using template $paramod$3d7168c8134c4765b84a7b86d5ef7e1e65bbf4a0$lut for cells of type $lut.
|
|
Using template $paramod$4cab3b31c601551ff65536bf4f533afa0b2094ee$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0111 for cells of type $lut.
|
|
Using template $paramod$1d709f1a03cb244f217c5a3d6c07924962c62ee4$lut for cells of type $lut.
|
|
Using template $paramod$fbfcbb65da9e491cb813a7d5cf89ca57a5099313$lut for cells of type $lut.
|
|
Using template $paramod$ac46f3bb46684dec331808dd9736c79f10a14f1a$lut for cells of type $lut.
|
|
Using template $paramod$1ec3fb8fd1fa98216cb96b4422de32c4ba5f6c9c$lut for cells of type $lut.
|
|
Using template $paramod$b2fd65cbfcccc481c9911162378839bd18af9a6c$lut for cells of type $lut.
|
|
Using template $paramod$d6f1219c0b8bf5e437227c8ff7392e64138100e7$lut for cells of type $lut.
|
|
Using template $paramod$88398de0036537463bc107bbf48dae52c453aae6$lut for cells of type $lut.
|
|
Using template $paramod$7c1f6afe503c0a9d86df3082e3bb8088dcf2d22b$lut for cells of type $lut.
|
|
Using template $paramod$c28a8b7ce0535d090c4cfb52e9c74affd52b110c$lut for cells of type $lut.
|
|
Using template $paramod$af89c709dbeadaebe9ab6d763949db89d3a5f81e$lut for cells of type $lut.
|
|
Using template $paramod$e8c09ab5aebca984fe90f009499cd9044f568f72$lut for cells of type $lut.
|
|
Using template $paramod$41326ad8644342a66dfb051d050f2b6fbf15015b$lut for cells of type $lut.
|
|
Using template $paramod$d63afe3a727d8bcac365413579cb24c0425e57da$lut for cells of type $lut.
|
|
Using template $paramod$b37a9a890b9890104435dcad740278bbb9bf2e30$lut for cells of type $lut.
|
|
Using template $paramod$150e4e91a6bc7251e04d8c45150d8506b0307139$lut for cells of type $lut.
|
|
Using template $paramod$a2047b3921650a538c82f8da1d6858a781b7c6e4$lut for cells of type $lut.
|
|
Using template $paramod$92d62964a217ae06de1b0e56ed1359336b55661f$lut for cells of type $lut.
|
|
Using template $paramod$753614714d23adf0cec714b63fdd42ccd69bbccd$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11001001 for cells of type $lut.
|
|
Using template $paramod$f3bb6ee3d59cb27b988e381606864bfd1d6bbd0d$lut for cells of type $lut.
|
|
Using template $paramod$d344cee926aed6a6701c9803aabde2d8aec3b0ef$lut for cells of type $lut.
|
|
Using template $paramod$cd05caaf261e4148f336c0ecc488c806e4433d99$lut for cells of type $lut.
|
|
Using template $paramod$f9df0bb8fc3cbb332d575e165ec04d3cfd4c90ca$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00010011 for cells of type $lut.
|
|
Using template $paramod$b7f39e1b5141a1b40969d98648878de7f99babfd$lut for cells of type $lut.
|
|
Using template $paramod$b11ef98d2ba248a72628d590fcde650faaa379f0$lut for cells of type $lut.
|
|
Using template $paramod$d55921ffc1c2a2cf0a27456811acd104d7a1887e$lut for cells of type $lut.
|
|
Using template $paramod$6c2c657b34cc512a16ac66c27497802bea50d222$lut for cells of type $lut.
|
|
Using template $paramod$6ab1af087b7cdbbe9fe0b2c8de0775ec05f2311f$lut for cells of type $lut.
|
|
Using template $paramod$b2b7a0f49688ec95df23179fc8f24d920f097d82$lut for cells of type $lut.
|
|
Using template $paramod$f2574d59274c3f1b35b541b0c67721aa790aa92f$lut for cells of type $lut.
|
|
Using template $paramod$a21efd7bd673fb80d1f7a999afb39b46d87849ed$lut for cells of type $lut.
|
|
Using template $paramod$a54587c856df3b7b67eae787417791e92ae5ae17$lut for cells of type $lut.
|
|
Using template $paramod$f3ab407a24c7fec73163b2677ab4a3c1dd360a8c$lut for cells of type $lut.
|
|
Using template $paramod$16fe2adc888057a9199146e9533f971b44a5231e$lut for cells of type $lut.
|
|
Using template $paramod$a1ac9f163527e773f2ad9beb35041f707a03d11a$lut for cells of type $lut.
|
|
Using template $paramod$b63ad9fd189ffa249d8fcf9c31bb572267009f3b$lut for cells of type $lut.
|
|
Using template $paramod$791b18bc56712c03692f66ec78c2ea4988ece475$lut for cells of type $lut.
|
|
Using template $paramod$d538551e8aa0422d7bd4c02cb37fe64f384e854b$lut for cells of type $lut.
|
|
Using template $paramod$0fb3437f3229691986674bbb93ca3e579291b720$lut for cells of type $lut.
|
|
Using template $paramod$3c3fed19c6fd1d349196eeef2e653fb0a32b5a50$lut for cells of type $lut.
|
|
Using template $paramod$5cf7953073b8db50f8fe81ad8deaa37e9ce65177$lut for cells of type $lut.
|
|
Using template $paramod$713acdfe6e7bb7c589604c251212f10c8ae34573$lut for cells of type $lut.
|
|
Using template $paramod$bf3c695b03cbb3727b63eb2bf69127329bf3a602$lut for cells of type $lut.
|
|
Using template $paramod$b9d8b7e91a2c68da033af948ea0bd8bdebbaf6b2$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11101100 for cells of type $lut.
|
|
Using template $paramod$61dbfffe165b884726f0b461e612b712b9b17b15$lut for cells of type $lut.
|
|
Using template $paramod$bf5054159991ce73aee8525b5ca6c5bf0bd74060$lut for cells of type $lut.
|
|
Using template $paramod$2a7a3cc91168274c34f004e2f49f0e8fb3473d79$lut for cells of type $lut.
|
|
Using template $paramod$22017edeb6d5e7ff29f15854dbf3b1f8e012dc4f$lut for cells of type $lut.
|
|
Using template $paramod$0ab70a8e6fbac37beb02008bda6f09f1d4db5088$lut for cells of type $lut.
|
|
Using template $paramod$eac45d17e250a7b9bea607047125ee81ec7f9634$lut for cells of type $lut.
|
|
Using template $paramod$0229b43b4d2b5d1206ac6cdf717e29127c865aeb$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01010110 for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11110001 for cells of type $lut.
|
|
Using template $paramod$5bfc54fb11dd37c2f7f6ac035f9ec46d74ac376f$lut for cells of type $lut.
|
|
Using template $paramod$2085c6b34d6c7fda5fabed17ac8f99e247d3a2cc$lut for cells of type $lut.
|
|
Using template $paramod$8101d9e9626186b085c3c63c84551dd3f6cf12c5$lut for cells of type $lut.
|
|
Using template $paramod$b6ebb0ea1200440e9f4d8451077c5efc796eb6bd$lut for cells of type $lut.
|
|
Using template $paramod$00e46ce433fed542da219a129ee7510f1880f472$lut for cells of type $lut.
|
|
Using template $paramod$7f439247de36c5d1e2dd48a8425a7ee7f902f183$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10110001 for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10000001 for cells of type $lut.
|
|
Using template $paramod$f070ba22083bf2a5dcf49edd1540eb987ca7729b$lut for cells of type $lut.
|
|
Using template $paramod$373e8e19877577962327116b0577ecfa959fa63e$lut for cells of type $lut.
|
|
Using template $paramod$f7adceb0c7872cbff53cd1760f1eb0b7c1107e0a$lut for cells of type $lut.
|
|
Using template $paramod$3b2443149f4e4da852ea6d30c3416b9726834917$lut for cells of type $lut.
|
|
Using template $paramod$c27dbc684adf6181c2c8e3cbe2804f28b5995c64$lut for cells of type $lut.
|
|
Using template $paramod$619b7c9a4d44585e10b42f7fb79b16304cca97c5$lut for cells of type $lut.
|
|
Using template $paramod$f3b603d1450c2c61ce732232fcb5fe1f2884aa83$lut for cells of type $lut.
|
|
Using template $paramod$f4b55478d434c2b186128aa20fe00bb7dbbdb660$lut for cells of type $lut.
|
|
Using template $paramod$39a5e38988734123ed33b342aec426bc56ea2d29$lut for cells of type $lut.
|
|
Using template $paramod$de90861e1fe17e402b75c49a386d7c5e85bb576f$lut for cells of type $lut.
|
|
Using template $paramod$a499a951fe2501b993cd3c1a7f4ea3cb664c3d4f$lut for cells of type $lut.
|
|
Using template $paramod$70e799d07c8873fab077dadf9b2388e2a7e218d8$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01001110 for cells of type $lut.
|
|
Using template $paramod$830698fa31c955ecb029cff9d157f6ad35fe94d9$lut for cells of type $lut.
|
|
Using template $paramod$7c62394fc9dcd57450f98f8754db0e3c7b377a8c$lut for cells of type $lut.
|
|
Using template $paramod$a04927f74543a2f2c75ad2073eedeadc9b3f7a78$lut for cells of type $lut.
|
|
Using template $paramod$c38f30bb72f3450f14df44bc5ed7093123ea9e2e$lut for cells of type $lut.
|
|
Using template $paramod$305f632a7558024bed26eab5baa1370d6d77c6d9$lut for cells of type $lut.
|
|
Using template $paramod$a3434cb8db1de59125a973ead7893dd6d9885b8c$lut for cells of type $lut.
|
|
Using template $paramod$31e1e3d6815de2bada6bfa7ac5bd6a81e7596a6b$lut for cells of type $lut.
|
|
Using template $paramod$97e9de72dcb0a3d718feb749ce656a0a32901518$lut for cells of type $lut.
|
|
Using template $paramod$f46e5089da66d6b70be2c32f2623d558f2226b37$lut for cells of type $lut.
|
|
Using template $paramod$459e5b39a252738a6497359b8c0da114191996a2$lut for cells of type $lut.
|
|
Using template $paramod$630206d61c6865b0a7772f9cad78ff171809be06$lut for cells of type $lut.
|
|
Using template $paramod$5b13d2ee598c87cdbe912286a35c6fd102e2087c$lut for cells of type $lut.
|
|
Using template $paramod$5e9374f44a27c3f8a1c38af244ec43ceb4fb8d4f$lut for cells of type $lut.
|
|
Using template $paramod$648d5b3c4c08a2b5e6752f60f9134dd7da5b02b9$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10001100 for cells of type $lut.
|
|
Using template $paramod$b9a74c8fb0d628811d75e37973e9ed5b54514ee0$lut for cells of type $lut.
|
|
Using template $paramod$32dee08328e8b29c9284c987432b771d306144c4$lut for cells of type $lut.
|
|
Using template $paramod$acf49cb7bd2805dee4b4ebb218aa5924b1be7704$lut for cells of type $lut.
|
|
Using template $paramod$e515f2e0976c0588506a69d91ee57d85a230c2f4$lut for cells of type $lut.
|
|
Using template $paramod$e49f6e3576ef1a6d2f58c54414dbb786af8cc869$lut for cells of type $lut.
|
|
Using template $paramod$51599577e92cd2756c2272cd36d7c29221c56d2f$lut for cells of type $lut.
|
|
Using template $paramod$40fc7aee2f2d49833ca09e258a134482d29300ad$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00101110 for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1101 for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11101111 for cells of type $lut.
|
|
Using template $paramod$6e98fea82e288eb70fa7833e8442d9b57c9d67e7$lut for cells of type $lut.
|
|
Using template $paramod$eb764785a67ae0903625e17df40813438d0457e8$lut for cells of type $lut.
|
|
Using template $paramod$66e741791413519a466d4f44240bc83d3a191818$lut for cells of type $lut.
|
|
Using template $paramod$e7acaad2d79ca9d6583d9edc46f9553c36f919ec$lut for cells of type $lut.
|
|
Using template $paramod$168aeef333136ff4f1f2ce3a62c8b6d1ffc7dc28$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10001011 for cells of type $lut.
|
|
Using template $paramod$84a9bb4ea112cac05b4a6b108a4c6ec2091f4ef3$lut for cells of type $lut.
|
|
Using template $paramod$eba7de026ff587370e320127e266317dae097a89$lut for cells of type $lut.
|
|
Using template $paramod$05fcf858dd0b908940cb641538dd7b70ee398afc$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11110010 for cells of type $lut.
|
|
Using template $paramod$6e1e2bf7f29cfe416c0ceb4dc5c676edd2a3b996$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11100010 for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10111111 for cells of type $lut.
|
|
Using template $paramod$0fa351d24d2713ce0a93e46f5deedd65d95d22b8$lut for cells of type $lut.
|
|
Using template $paramod$c11ee6bbb8d9fd9cf391261624c378fb45e86b84$lut for cells of type $lut.
|
|
Using template $paramod$478e33feeac3aa53ff57d491aada044b8aedceae$lut for cells of type $lut.
|
|
Using template $paramod$9d12c15405e25608417ce779d7fe1b86619365f9$lut for cells of type $lut.
|
|
Using template $paramod$3830fbfbec2ed4d6e3e957e17e4fca97b7adef1f$lut for cells of type $lut.
|
|
Using template $paramod$af763bca85949884aefa417266a961f9c91132de$lut for cells of type $lut.
|
|
Using template $paramod$fedc9dd49dc77948bb3b96048b3e9c4cb551096b$lut for cells of type $lut.
|
|
Using template $paramod$70ebb6cf5bc7d63c5c1a98ccefefa2af79e8f2a9$lut for cells of type $lut.
|
|
Using template $paramod$ee51b4667e8174b96303ce4018c086769bccd57c$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11111000 for cells of type $lut.
|
|
Using template $paramod$f21dc1be6328a927e095a2d7e735e0517631a79c$lut for cells of type $lut.
|
|
Using template $paramod$e4cede61517c69f4283b34833b70389aba0ba4b3$lut for cells of type $lut.
|
|
Using template $paramod$5ab8703b1aa62946296547e85dc0a19366704a74$lut for cells of type $lut.
|
|
Using template $paramod$fe94d8c9e91265ab708c60526b99157e8dad92bb$lut for cells of type $lut.
|
|
Using template $paramod$5aaf683a266233ca3958e90f61b904317f948e44$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11111011 for cells of type $lut.
|
|
Using template $paramod$4804ba902596a9a62ec5704b6cbf7afdc5ab29d6$lut for cells of type $lut.
|
|
Using template $paramod$87d995c9509899eb095b19b358f1d0ee4e974b2d$lut for cells of type $lut.
|
|
Using template $paramod$49b4d47dab45283a5bca35b8996da0a3c24bef1f$lut for cells of type $lut.
|
|
Using template $paramod$18b4576fcf375b39d4742d25337302ba17d3da17$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10111010 for cells of type $lut.
|
|
Using template $paramod$e57bcb018bfe8170bc04f13a73befe2def28cdf3$lut for cells of type $lut.
|
|
Using template $paramod$6d6beead1425af15cf78b27fd9b11b41b5d4bce8$lut for cells of type $lut.
|
|
Using template $paramod$722bfd9af0ae56ca9d1d12a221cb5ede16461f26$lut for cells of type $lut.
|
|
Using template $paramod$58bd588a49a6a3b9d057d75f907cb4932e1635f6$lut for cells of type $lut.
|
|
Using template $paramod$75a594fb1222912a8f084ecc3173a1411802aae0$lut for cells of type $lut.
|
|
Using template $paramod$fb5ee0bdef1c4e74aaf1fd8efae98b46a2f5e564$lut for cells of type $lut.
|
|
Using template $paramod$ef26adabe6060e01077b576cfe34e95e55a26aef$lut for cells of type $lut.
|
|
Using template $paramod$ab97d1bb00842ebb07c43c56b359e5465698afc2$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00001000 for cells of type $lut.
|
|
Using template $paramod$286d6b18e782cb14d345c8422500571fedf77570$lut for cells of type $lut.
|
|
Using template $paramod$3c64762f56d2dfc9226156923515f492b69b41a9$lut for cells of type $lut.
|
|
Using template $paramod$2f7deae5fb594b0c70bb82efd4d3682a7baaa352$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01100101 for cells of type $lut.
|
|
Using template $paramod$ea9f0804ffa1047d479d3e00429394419ff5856b$lut for cells of type $lut.
|
|
Using template $paramod$91fbcda5fe28095fdd779b73c95f4fc59d3c2bad$lut for cells of type $lut.
|
|
Using template $paramod$583294f05aaec818beb341e1ee966bc090a0a81c$lut for cells of type $lut.
|
|
Using template $paramod$72d515dae45e66ccd840269be98d8db82f37ab68$lut for cells of type $lut.
|
|
Using template $paramod$0d3ac82cf5b8a192d5ff4c23e3143360366ae882$lut for cells of type $lut.
|
|
Using template $paramod$d6a246575d0ba3dcbbccd768ad41b602f82ff057$lut for cells of type $lut.
|
|
Using template $paramod$18c471b8eff722fbc814801a8f3676079792e1ca$lut for cells of type $lut.
|
|
Using template $paramod$b4f15f202f50520dbc381cd0880ac94f830f05a8$lut for cells of type $lut.
|
|
Using template $paramod$5537196b57727378a8360bd7e25641fdc66dc28f$lut for cells of type $lut.
|
|
Using template $paramod$9efa31767d28d0289baa2563b9d4aa22c88e279f$lut for cells of type $lut.
|
|
Using template $paramod$dc15a2d86f211cdad96681d52b19d96d6735341a$lut for cells of type $lut.
|
|
Using template $paramod$c697e96f6c39333c61f6708189ec09dee5302bcc$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10111000 for cells of type $lut.
|
|
Using template $paramod$59848369e5f408d15e0c8c710ff689c98ce02999$lut for cells of type $lut.
|
|
Using template $paramod$1b4dea70ff04f88e4f935829ae81088bf4d3cdf3$lut for cells of type $lut.
|
|
Using template $paramod$47b2f5a9f58cb4be072657772748a1ab82d6819a$lut for cells of type $lut.
|
|
Using template $paramod$04c5b12d4740de5f8f090d1075bb2b548203e578$lut for cells of type $lut.
|
|
Using template $paramod$7e9df0afb32b76fe5fce0691b8752aca650057fa$lut for cells of type $lut.
|
|
Using template $paramod$085ac6daadd555b0f8cf8f603c7849f876be6cbc$lut for cells of type $lut.
|
|
Using template $paramod$ab8bb87959c5d7cfa27886cee1355b38e054a61a$lut for cells of type $lut.
|
|
Using template $paramod$e46703b423a661cd7d311c41833ea655969702cc$lut for cells of type $lut.
|
|
Using template $paramod$7947309ecdec9d9f5ac1e28d14e3a69ddbc57c40$lut for cells of type $lut.
|
|
Using template $paramod$9d1915f40715c7f715525567f7dfd63744c26c4a$lut for cells of type $lut.
|
|
Using template $paramod$6eb0120b614812da6c803ffd69aa81ac7857536d$lut for cells of type $lut.
|
|
Using template $paramod$ffc2ea81a65101fbef8a332deddf112494d27163$lut for cells of type $lut.
|
|
Using template $paramod$359fe4e746656bf9c72aecaff84fc7bdea9f55a5$lut for cells of type $lut.
|
|
Using template $paramod$75d5c453cca75cc7a7ca320c4fb7be0932b6aaa7$lut for cells of type $lut.
|
|
Using template $paramod$e90230c8dcea473069bf03fcce8b92040e4d209a$lut for cells of type $lut.
|
|
Using template $paramod$e51a8a571bee774247b38f52d6e85fd62ae52cea$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11011111 for cells of type $lut.
|
|
Using template $paramod$e8ba44e4a3ee29c32776f6151b0293be3e5fa416$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11010000 for cells of type $lut.
|
|
Using template $paramod$c5f3c57a6d466a2f42208bafb8985b96ce884440$lut for cells of type $lut.
|
|
Using template $paramod$edb78bf6097bd1610bf429917d83de43c0242af1$lut for cells of type $lut.
|
|
Using template $paramod$35059585e93e18989247e13034fd6a1ce4de9957$lut for cells of type $lut.
|
|
Using template $paramod$8494168726d27c2200605afcf1fb7470bf987857$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10001101 for cells of type $lut.
|
|
Using template $paramod$51f598eae0fd0a1d915d8f865e5f8ba665bae846$lut for cells of type $lut.
|
|
Using template $paramod$9cca2538994dcb20116ef116817856ba31a28354$lut for cells of type $lut.
|
|
Using template $paramod$097592bb16245531f0716c5ddb18d7090f9c7d9d$lut for cells of type $lut.
|
|
Using template $paramod$089fa05abdd3029ee96469cc22b23817eae53deb$lut for cells of type $lut.
|
|
Using template $paramod$708ff7e971fdbc9b041ef4977b41c8d828262923$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10001111 for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00101000 for cells of type $lut.
|
|
Using template $paramod$b16305c55e8688bbbd58bd36edbb9b6878120874$lut for cells of type $lut.
|
|
Using template $paramod$8c218f07f4fcb7aa89542ff3d7405186c308b9d1$lut for cells of type $lut.
|
|
Using template $paramod$f13784ede300b12a5285177c86c7721a54cf9e12$lut for cells of type $lut.
|
|
Using template $paramod$1d3e3dda7513a26513dc7c9f8a4ac0e6b682116c$lut for cells of type $lut.
|
|
Using template $paramod$640f0b255c4baeb1d5ed3ee07d5b4acf52609838$lut for cells of type $lut.
|
|
Using template $paramod$6b7c9c56fc2a32a479d463d5f3b0d3f4673b67f1$lut for cells of type $lut.
|
|
Using template $paramod$a5627e8ad36aa9b4fe2f6188097d151d45fefa8a$lut for cells of type $lut.
|
|
Using template $paramod$77b566652a2449bae604a937e67f0c9bd49bb4a7$lut for cells of type $lut.
|
|
Using template $paramod$6a34cd5b50e324824168b4186d0b04ba5e83b039$lut for cells of type $lut.
|
|
Using template $paramod$332530260df33f1e6567b344a898a29636fd4f0f$lut for cells of type $lut.
|
|
Using template $paramod$bb93cf0be1aea527e946a2842c881e26e918e93d$lut for cells of type $lut.
|
|
Using template $paramod$011998c9bc40e79d3b9378981668ce5683b7cfe4$lut for cells of type $lut.
|
|
Using template $paramod$8f7210088a40da1859d27e900c288fd298d68bed$lut for cells of type $lut.
|
|
Using template $paramod$debd9b669717840687fe3e52f7822c4b59921848$lut for cells of type $lut.
|
|
Using template $paramod$df208ff6c4621519a3b9ca6dd51a2309b7a22b96$lut for cells of type $lut.
|
|
Using template $paramod$4fd9f5b356316244f606b310fd2032795fb2b746$lut for cells of type $lut.
|
|
Using template $paramod$e44e5aa8c219aafd07bd79428a3dd225141eed54$lut for cells of type $lut.
|
|
Using template $paramod$be48d952fcad8a16b8d84daa4c48a3065f343e5e$lut for cells of type $lut.
|
|
Using template $paramod$55b06b5252c83d56004e2ea1ddaba2d789600bd1$lut for cells of type $lut.
|
|
Using template $paramod$eaefffc34a63d2d03fc8295bf3934082e33226c1$lut for cells of type $lut.
|
|
Using template $paramod$474bedaec9543fe0c362d2e4221204654298befe$lut for cells of type $lut.
|
|
Using template $paramod$f8f63b209b7230e81958663ff24fef1613156af7$lut for cells of type $lut.
|
|
Using template $paramod$589a3f982da79fa8946e49d2903c90d62ebf1752$lut for cells of type $lut.
|
|
Using template $paramod$0f19b1c588a47c675d00132b243b5e3308ffab5d$lut for cells of type $lut.
|
|
Using template $paramod$59e7850c29ed7dc1b5206cab42fa28a25e995cb5$lut for cells of type $lut.
|
|
Using template $paramod$85bfededee465bae5756ca624f885b4fd728f95c$lut for cells of type $lut.
|
|
Using template $paramod$38621c4d710b101de242bc8b9808c74c5e2b0fe5$lut for cells of type $lut.
|
|
Using template $paramod$0e61177c7beb2862bb3be1cd3cb0fcafd8edbf78$lut for cells of type $lut.
|
|
Using template $paramod$3fcffbc2ddcfbfad442bbfe9c66883d5514b6202$lut for cells of type $lut.
|
|
Using template $paramod$1d371fb9f6e4d1b0a5db1e4212eac65c4a243863$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10110000 for cells of type $lut.
|
|
Using template $paramod$7e8d331d1e06632d29fbdf6c3afc2de1856d3c67$lut for cells of type $lut.
|
|
Using template $paramod$946e4ba6cc6d5f643745e6b56089375901ce6d2c$lut for cells of type $lut.
|
|
Using template $paramod$7d35f3eb4056e6484203c99fe42cfcf1dfaba704$lut for cells of type $lut.
|
|
Using template $paramod$cdc5bba2585477f1744fd1f869bebc8beb23d707$lut for cells of type $lut.
|
|
Using template $paramod$da6220928701f9237d20caf438fe2b420e056575$lut for cells of type $lut.
|
|
Using template $paramod$6bfad119473132ff9415951cabd1d04190f1cdf6$lut for cells of type $lut.
|
|
Using template $paramod$bb2a931410ef42e12d3c0aec8ebd14c444415b42$lut for cells of type $lut.
|
|
Using template $paramod$5321e04f7ce32c091123c3570ab562efb1c81402$lut for cells of type $lut.
|
|
Using template $paramod$3a813c81898bbc8cecfd0cfc6aa14244c47ec5d4$lut for cells of type $lut.
|
|
Using template $paramod$6375ab94b303a3f3c8d7ca6946328cb3c0b443a7$lut for cells of type $lut.
|
|
Using template $paramod$2bf892cb2b52095d41d96cd0cddc511c2796a989$lut for cells of type $lut.
|
|
Using template $paramod$20f3f4b8e32f8a8b038b0056872dc94926194798$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00100011 for cells of type $lut.
|
|
Using template $paramod$47e24444b54a027b721781e1e632209e3df7d3de$lut for cells of type $lut.
|
|
Using template $paramod$238768b4e458888d568a599df3b40405977cf862$lut for cells of type $lut.
|
|
Using template $paramod$c68712dc4df814ac77e45c594b73bf1695cb9c5d$lut for cells of type $lut.
|
|
Using template $paramod$89e657d3deb4e004585d03c823ba6873736f7939$lut for cells of type $lut.
|
|
Using template $paramod$5cd6342b8b1615f2ee34e81b2e8af9c6ecb251a6$lut for cells of type $lut.
|
|
Using template $paramod$eba190482ad1ad908b8a152127298be31103daa8$lut for cells of type $lut.
|
|
Using template $paramod$a5788e8bd3559e65ba7c6a1d93529c6fb76569b9$lut for cells of type $lut.
|
|
Using template $paramod$5f840889b533dd3bcc51c37336d5c17765edeed3$lut for cells of type $lut.
|
|
Using template $paramod$801b4648f8a54abad7f2f86a1643f447cc0694f9$lut for cells of type $lut.
|
|
Using template $paramod$7843dc81c49c8b1162a4cb2fb3425453d572562c$lut for cells of type $lut.
|
|
Using template $paramod$407128e42df200d2e465baccb4b002b527d4e9f1$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10000100 for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00011111 for cells of type $lut.
|
|
Using template $paramod$90dc599eed99da511e64ad217d69e7ff2c1e56cc$lut for cells of type $lut.
|
|
Using template $paramod$b6aedd1d2a589b5ea7940b1674d8585d6e25c6d6$lut for cells of type $lut.
|
|
Using template $paramod$e7333de18ee6329af4f3b4f3f895c96b201b11f4$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01000101 for cells of type $lut.
|
|
Using template $paramod$43920eead97cfe6c48d10f084962e7b11714ac27$lut for cells of type $lut.
|
|
Using template $paramod$ef3f2547cf84a471ee84948e0f16dbdee8ed5b5d$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01101010 for cells of type $lut.
|
|
Using template $paramod$b55a3b7e8f658a2e148f7d2a78c30bafdc7c70d8$lut for cells of type $lut.
|
|
Using template $paramod$94ac66a11090dca84889e55fcf03297912a5b7ec$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10000010 for cells of type $lut.
|
|
Using template $paramod$498daa9936ffa1c0b12d774cacc95a35d14b818e$lut for cells of type $lut.
|
|
Using template $paramod$a670b08a47dd8a34f954c50cd06e9996d77e8467$lut for cells of type $lut.
|
|
Using template $paramod$7ccb46ee9b56c39e0a7d82a185b08cb026e04fbc$lut for cells of type $lut.
|
|
Using template $paramod$251994398653c4cf8de320f1e306e535d5d2d624$lut for cells of type $lut.
|
|
Using template $paramod$25b3ab2bd32f59f9e478199e68d7e3e24c3c689e$lut for cells of type $lut.
|
|
Using template $paramod$d29001d2b1912b522c117aa4c098ecc3ec91e3f3$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000001\LUT=2'01 for cells of type $lut.
|
|
No more expansions possible.
|
|
<suppressed ~13913 debug messages>
|
|
|
|
22.48. Executing OPT_LUT_INS pass (discard unused LUT inputs).
|
|
Optimizing LUTs in spi_neuron_top.
|
|
Optimizing lut $abc$87474$lut$aiger$o157.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
|
|
Optimizing lut $abc$87474$lut$aiger$o160.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
|
|
Optimizing lut $abc$87474$lut$aiger$o161.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
|
|
Optimizing lut $abc$87474$lut$aiger$o162.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
|
|
Optimizing lut $abc$87474$lut$aiger87473$19812.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$87621.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$87624.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$87625.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$87626.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$87627.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$87628.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$87629.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$87630.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$87631.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$87632.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$87633.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$87634.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$87635.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$87636.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$87637.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$87638.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$87641.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$19495.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$19495.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$19495.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$19495.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$19477.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$19477.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$19477.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$19477.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$19477.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
|
|
Optimizing lut $abc$87474$lut$aiger87473$19462.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$19446.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$19425.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$19402.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$19402.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$19388.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$19290.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$19290.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$19290.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$19290.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$19290.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$19269.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$19256.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
|
|
Optimizing lut $abc$87474$lut$aiger87473$19256.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$19256.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$19256.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$19256.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
|
|
Optimizing lut $abc$87474$lut$aiger87473$19256.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$19242.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
|
|
Optimizing lut $abc$87474$lut$aiger87473$19242.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
|
|
Optimizing lut $abc$87474$lut$aiger87473$19242.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
|
|
Optimizing lut $abc$87474$lut$aiger87473$19242.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
|
|
Optimizing lut $abc$87474$lut$aiger87473$19230.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$19173.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$19159.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$19159.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$19159.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$18999.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$19094.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$19068.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$19042.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$19042.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$19042.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$19018.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$18924.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$18924.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$18860.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$18860.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$18822.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$18799.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$18725.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$18725.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$18725.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$18783.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$18783.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$18783.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$18562.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$18562.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$18562.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$18562.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$18589.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$18589.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$18589.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$18589.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$18589.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$18668.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
|
|
Optimizing lut $abc$87474$lut$aiger87473$18668.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$18668.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
|
|
Optimizing lut $abc$87474$lut$aiger87473$18668.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$18638.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$18628.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$18628.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
|
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Optimizing lut $abc$87474$lut$aiger87473$18628.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
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Optimizing lut $abc$87474$lut$aiger87473$18628.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
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Optimizing lut $abc$87474$lut$aiger87473$17727.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
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Optimizing lut $abc$87474$lut$aiger87473$17727.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
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Optimizing lut $abc$87474$lut$aiger87473$17727.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
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Optimizing lut $abc$87474$lut$aiger87473$17727.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
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Optimizing lut $abc$87474$lut$aiger87473$17727.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
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Optimizing lut $abc$87474$lut$aiger87473$17727.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
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Optimizing lut $abc$87474$lut$aiger87473$17716.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
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Optimizing lut $abc$87474$lut$aiger87473$17716.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
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Optimizing lut $abc$87474$lut$aiger87473$17716.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
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Optimizing lut $abc$87474$lut$aiger87473$17716.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
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Optimizing lut $abc$87474$lut$aiger87473$17704.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
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Optimizing lut $abc$87474$lut$aiger87473$17704.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
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Optimizing lut $abc$87474$lut$aiger87473$17704.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
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Optimizing lut $abc$87474$lut$aiger87473$17704.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
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Optimizing lut $abc$87474$lut$aiger87473$17704.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
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Optimizing lut $abc$87474$lut$aiger87473$17704.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
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Optimizing lut $abc$87474$lut$aiger87473$17502.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
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Optimizing lut $abc$87474$lut$aiger87473$18438.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
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Optimizing lut $abc$87474$lut$aiger87473$18438.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
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Optimizing lut $abc$87474$lut$aiger87473$18438.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
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Optimizing lut $abc$87474$lut$aiger87473$18363.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
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Optimizing lut $abc$87474$lut$aiger87473$18363.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
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Optimizing lut $abc$87474$lut$aiger87473$18363.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
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Optimizing lut $abc$87474$lut$aiger87473$18363.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
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|
Optimizing lut $abc$87474$lut$aiger87473$18363.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
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Optimizing lut $abc$87474$lut$aiger87473$18576.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
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|
Optimizing lut $abc$87474$lut$aiger87473$18576.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
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Optimizing lut $abc$87474$lut$aiger87473$18576.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
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|
Optimizing lut $abc$87474$lut$aiger87473$18576.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
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|
Optimizing lut $abc$87474$lut$aiger87473$18576.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
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|
Optimizing lut $abc$87474$lut$aiger87473$18576.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
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|
Optimizing lut $abc$87474$lut$aiger87473$18250.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
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Optimizing lut $abc$87474$lut$aiger87473$18250.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
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|
Optimizing lut $abc$87474$lut$aiger87473$18250.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
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|
Optimizing lut $abc$87474$lut$aiger87473$18132.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
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Optimizing lut $abc$87474$lut$aiger87473$18132.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
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|
Optimizing lut $abc$87474$lut$aiger87473$18271.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
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Optimizing lut $abc$87474$lut$aiger87473$18271.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
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Optimizing lut $abc$87474$lut$aiger87473$18271.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
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Optimizing lut $abc$87474$lut$aiger87473$18271.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
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Optimizing lut $abc$87474$lut$aiger87473$18271.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
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|
Optimizing lut $abc$87474$lut$aiger87473$18271.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
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Optimizing lut $abc$87474$lut$aiger87473$18541.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
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|
Optimizing lut $abc$87474$lut$aiger87473$18541.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
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|
Optimizing lut $abc$87474$lut$aiger87473$18541.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
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|
Optimizing lut $abc$87474$lut$aiger87473$18541.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
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|
Optimizing lut $abc$87474$lut$aiger87473$18541.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
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|
Optimizing lut $abc$87474$lut$aiger87473$18541.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
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|
Optimizing lut $abc$87474$lut$aiger87473$18522.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
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Optimizing lut $abc$87474$lut$aiger87473$18522.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
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|
Optimizing lut $abc$87474$lut$aiger87473$18056.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
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Optimizing lut $abc$87474$lut$aiger87473$18032.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
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Optimizing lut $abc$87474$lut$aiger87473$18032.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
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Optimizing lut $abc$87474$lut$aiger87473$18032.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
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Optimizing lut $abc$87474$lut$aiger87473$18032.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
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Optimizing lut $abc$87474$lut$aiger87473$18032.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
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Optimizing lut $abc$87474$lut$aiger87473$18032.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
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Optimizing lut $abc$87474$lut$aiger87473$17878.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
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Optimizing lut $abc$87474$lut$aiger87473$18446.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
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Optimizing lut $abc$87474$lut$aiger87473$18446.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
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Optimizing lut $abc$87474$lut$aiger87473$18446.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
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|
Optimizing lut $abc$87474$lut$aiger87473$18446.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
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|
Optimizing lut $abc$87474$lut$aiger87473$18446.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
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|
Optimizing lut $abc$87474$lut$aiger87473$18446.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
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|
Optimizing lut $abc$87474$lut$aiger87473$18376.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
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|
Optimizing lut $abc$87474$lut$aiger87473$18376.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
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|
Optimizing lut $abc$87474$lut$aiger87473$18376.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
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|
Optimizing lut $abc$87474$lut$aiger87473$17986.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
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|
Optimizing lut $abc$87474$lut$aiger87473$17986.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
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|
Optimizing lut $abc$87474$lut$aiger87473$17986.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
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|
Optimizing lut $abc$87474$lut$aiger87473$17986.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
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|
Optimizing lut $abc$87474$lut$aiger87473$17986.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
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|
Optimizing lut $abc$87474$lut$aiger87473$17986.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
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|
Optimizing lut $abc$87474$lut$aiger87473$17098.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
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|
Optimizing lut $abc$87474$lut$aiger87473$18371.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
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|
Optimizing lut $abc$87474$lut$aiger87473$18371.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
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|
Optimizing lut $abc$87474$lut$aiger87473$18371.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
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|
Optimizing lut $abc$87474$lut$aiger87473$18371.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
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|
Optimizing lut $abc$87474$lut$aiger87473$18371.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
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|
Optimizing lut $abc$87474$lut$aiger87473$18371.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
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|
Optimizing lut $abc$87474$lut$aiger87473$17860.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
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|
Optimizing lut $abc$87474$lut$aiger87473$17860.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
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|
Optimizing lut $abc$87474$lut$aiger87473$17860.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
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|
Optimizing lut $abc$87474$lut$aiger87473$17860.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
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|
Optimizing lut $abc$87474$lut$aiger87473$18357.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
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|
Optimizing lut $abc$87474$lut$aiger87473$18357.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
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|
Optimizing lut $abc$87474$lut$aiger87473$18357.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
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|
Optimizing lut $abc$87474$lut$aiger87473$18357.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
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|
Optimizing lut $abc$87474$lut$aiger87473$18357.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
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|
Optimizing lut $abc$87474$lut$aiger87473$18357.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
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|
Optimizing lut $abc$87474$lut$aiger87473$17796.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
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|
Optimizing lut $abc$87474$lut$aiger87473$17796.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
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|
Optimizing lut $abc$87474$lut$aiger87473$17796.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
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|
Optimizing lut $abc$87474$lut$aiger87473$17261.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
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|
Optimizing lut $abc$87474$lut$aiger87473$17261.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
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|
Optimizing lut $abc$87474$lut$aiger87473$17261.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
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|
Optimizing lut $abc$87474$lut$aiger87473$17261.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
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|
Optimizing lut $abc$87474$lut$aiger87473$17261.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
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|
Optimizing lut $abc$87474$lut$aiger87473$17261.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
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|
Optimizing lut $abc$87474$lut$aiger87473$18292.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
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|
Optimizing lut $abc$87474$lut$aiger87473$18283.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
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|
Optimizing lut $abc$87474$lut$aiger87473$18283.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$18283.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$18283.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$18283.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
|
|
Optimizing lut $abc$87474$lut$aiger87473$18283.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
|
|
Optimizing lut $abc$87474$lut$aiger87473$17667.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$17667.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$17667.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$17667.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$17537.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$17537.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$17537.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$17537.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$17537.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$17537.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$15085.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$15085.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$17513.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$17513.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$17513.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$17513.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$17513.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$17513.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$17486.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$17486.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$17486.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$17486.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$17486.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
|
|
Optimizing lut $abc$87474$lut$aiger87473$17486.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$18257.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$18257.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$18257.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
|
|
Optimizing lut $abc$87474$lut$aiger87473$16753.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$16753.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$16753.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$16753.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$17427.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$17427.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$17427.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$14772.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$14772.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$18197.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$18197.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
|
|
Optimizing lut $abc$87474$lut$aiger87473$18084.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$18084.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$18084.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$18070.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$18070.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$18070.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$18070.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$18046.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$18046.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$18046.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$18046.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$18046.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
|
|
Optimizing lut $abc$87474$lut$aiger87473$18046.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
|
|
Optimizing lut $abc$87474$lut$aiger87473$18020.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$18020.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$18011.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$18011.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$18011.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$18011.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$18011.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$18011.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$17998.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$17998.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$17998.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$17998.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$17998.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
|
|
Optimizing lut $abc$87474$lut$aiger87473$17998.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
|
|
Optimizing lut $abc$87474$lut$aiger87473$16997.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$16997.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
|
|
Optimizing lut $abc$87474$lut$aiger87473$16997.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$16997.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$16997.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$16997.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
|
|
Optimizing lut $abc$87474$lut$aiger87473$16997.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$17005.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$17005.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
|
|
Optimizing lut $abc$87474$lut$aiger87473$17005.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$17005.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$17005.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$17005.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
|
|
Optimizing lut $abc$87474$lut$aiger87473$17005.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$17872.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$17872.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$17872.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$17872.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$17271.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$17271.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
|
|
Optimizing lut $abc$87474$lut$aiger87473$17271.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
|
|
Optimizing lut $abc$87474$lut$aiger87473$17271.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$17271.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
|
|
Optimizing lut $abc$87474$lut$aiger87473$17679.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$17679.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$17679.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$17679.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$16570.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$16570.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$16570.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
|
|
Optimizing lut $abc$87474$lut$aiger87473$16570.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$16570.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$16570.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$16878.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$16878.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$16878.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$16878.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$16878.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
|
|
Optimizing lut $abc$87474$lut$aiger87473$16878.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$17526.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$17526.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$17526.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$17526.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$17526.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$17526.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$16850.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$16850.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$16850.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$16850.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$16850.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$16850.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$17498.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$17498.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$17498.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$17498.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$17498.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
|
|
Optimizing lut $abc$87474$lut$aiger87473$17498.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
|
|
Optimizing lut $abc$87474$lut$aiger87473$16839.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$16839.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$16839.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$16839.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$16839.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$16839.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$13534.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$13534.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$11072.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$11072.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$11072.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$16809.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$16732.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$16671.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
|
|
Optimizing lut $abc$87474$lut$aiger87473$16671.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
|
|
Optimizing lut $abc$87474$lut$aiger87473$16671.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
|
|
Optimizing lut $abc$87474$lut$aiger87473$16671.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$16671.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
|
|
Optimizing lut $abc$87474$lut$aiger87473$16671.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
|
|
Optimizing lut $abc$87474$lut$aiger87473$17292.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$17292.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$17292.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
|
|
Optimizing lut $abc$87474$lut$aiger87473$15953.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$15506.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$15506.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$15506.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$15506.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$15506.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
|
|
Optimizing lut $abc$87474$lut$aiger87473$15506.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$17332.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$16890.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$16890.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$16890.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$16890.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$16890.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
|
|
Optimizing lut $abc$87474$lut$aiger87473$16890.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
|
|
Optimizing lut $abc$87474$lut$aiger87473$16391.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$16391.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
|
|
Optimizing lut $abc$87474$lut$aiger87473$16391.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
|
|
Optimizing lut $abc$87474$lut$aiger87473$16391.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$16391.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
|
|
Optimizing lut $abc$87474$lut$aiger87473$16179.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$16179.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$16099.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$16099.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$16099.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$16830.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
|
|
Optimizing lut $abc$87474$lut$aiger87473$16830.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
|
|
Optimizing lut $abc$87474$lut$aiger87473$16830.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
|
|
Optimizing lut $abc$87474$lut$aiger87473$16830.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$16830.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
|
|
Optimizing lut $abc$87474$lut$aiger87473$16830.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
|
|
Optimizing lut $abc$87474$lut$aiger87473$14873.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$14873.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$14873.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$16652.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
|
|
Optimizing lut $abc$87474$lut$aiger87473$16652.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
|
|
Optimizing lut $abc$87474$lut$aiger87473$16652.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
|
|
Optimizing lut $abc$87474$lut$aiger87473$16652.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$16652.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
|
|
Optimizing lut $abc$87474$lut$aiger87473$16652.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
|
|
Optimizing lut $abc$87474$lut$aiger87473$16578.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$16578.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$16578.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
|
|
Optimizing lut $abc$87474$lut$aiger87473$16578.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$16578.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$16578.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$13959.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$13959.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$17304.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$17304.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$17304.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$17304.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$17304.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
|
|
Optimizing lut $abc$87474$lut$aiger87473$17304.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
|
|
Optimizing lut $abc$87474$lut$aiger87473$17110.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$17087.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
|
|
Optimizing lut $abc$87474$lut$aiger87473$17087.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
|
|
Optimizing lut $abc$87474$lut$aiger87473$17087.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
|
|
Optimizing lut $abc$87474$lut$aiger87473$17087.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$17087.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
|
|
Optimizing lut $abc$87474$lut$aiger87473$17087.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
|
|
Optimizing lut $abc$87474$lut$aiger87473$15496.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$15496.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$15735.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$15735.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$15735.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$15735.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$15926.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$15926.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$15926.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$15926.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$17283.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
|
|
Optimizing lut $abc$87474$lut$aiger87473$17283.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$17283.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
|
|
Optimizing lut $abc$87474$lut$aiger87473$17283.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
|
|
Optimizing lut $abc$87474$lut$aiger87473$17283.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$17283.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
|
|
Optimizing lut $abc$87474$lut$aiger87473$15211.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$15211.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$17252.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
|
|
Optimizing lut $abc$87474$lut$aiger87473$17252.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
|
|
Optimizing lut $abc$87474$lut$aiger87473$17252.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
|
|
Optimizing lut $abc$87474$lut$aiger87473$17252.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$17252.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
|
|
Optimizing lut $abc$87474$lut$aiger87473$17252.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
|
|
Optimizing lut $abc$87474$lut$aiger87473$16477.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$16422.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$16403.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
|
|
Optimizing lut $abc$87474$lut$aiger87473$16403.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$16403.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
|
|
Optimizing lut $abc$87474$lut$aiger87473$16403.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
|
|
Optimizing lut $abc$87474$lut$aiger87473$16403.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$16403.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
|
|
Optimizing lut $abc$87474$lut$aiger87473$16220.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$16220.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$14779.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$14779.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$15068.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$15068.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$15068.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$15068.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$15068.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
|
|
Optimizing lut $abc$87474$lut$aiger87473$15068.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
|
|
Optimizing lut $abc$87474$lut$aiger87473$16191.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
|
|
Optimizing lut $abc$87474$lut$aiger87473$16191.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$16191.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
|
|
Optimizing lut $abc$87474$lut$aiger87473$16191.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
|
|
Optimizing lut $abc$87474$lut$aiger87473$16191.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$16191.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
|
|
Optimizing lut $abc$87474$lut$aiger87473$16083.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$16083.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$16083.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$16083.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$16013.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$16013.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$15995.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$15995.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$15978.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$15978.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$15978.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$15978.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$15964.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$15964.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$15747.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$15747.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$15747.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$15747.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$14531.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$14531.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$15407.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$15407.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$15938.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$15938.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$15938.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$15938.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$15838.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$15838.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$15305.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$15305.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$15305.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$15305.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$15305.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
|
|
Optimizing lut $abc$87474$lut$aiger87473$15305.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
|
|
Optimizing lut $abc$87474$lut$aiger87473$15576.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$15092.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$15092.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$13968.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$13968.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$15080.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$15080.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$15080.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$15080.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$15080.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
|
|
Optimizing lut $abc$87474$lut$aiger87473$15080.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
|
|
Optimizing lut $abc$87474$lut$aiger87473$13815.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$13815.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$13682.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$13682.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$13682.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$13682.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$13682.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$13660.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$13660.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$14885.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$14885.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$14885.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$14885.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$14885.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
|
|
Optimizing lut $abc$87474$lut$aiger87473$14885.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
|
|
Optimizing lut $abc$87474$lut$aiger87473$13651.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$15518.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$15518.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$15518.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$15518.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$15518.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
|
|
Optimizing lut $abc$87474$lut$aiger87473$15518.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
|
|
Optimizing lut $abc$87474$lut$aiger87473$14386.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$14386.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$14562.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$14562.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$14562.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$14562.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$14562.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$14562.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$14540.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$14540.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$15324.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$15324.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$14232.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$14232.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$15317.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$15317.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$15317.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$15317.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$15317.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
|
|
Optimizing lut $abc$87474$lut$aiger87473$15317.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
|
|
Optimizing lut $abc$87474$lut$aiger87473$14223.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$14223.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$14084.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$14084.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$14636.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$14636.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$13695.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$13695.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$13695.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$13695.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$13695.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$13695.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$13671.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$13671.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$13426.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$13426.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$13426.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$9636.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$9636.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$9636.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$9636.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$12989.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$13979.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$13979.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$13854.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$13854.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$13854.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$13854.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$13854.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$13854.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$9235.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$9235.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$9235.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$9235.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$14243.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$12342.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$12342.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$12342.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$12342.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$14575.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$14575.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$14575.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$14575.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$14575.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$14575.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$14551.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$14551.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$10408.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$10408.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$10408.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$10408.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$14279.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$14279.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$14279.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$14425.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$14425.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$14425.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$14425.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$14425.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$14425.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$10592.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$10592.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$10592.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$10592.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$10592.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$13303.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$13051.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$13051.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$13051.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$13051.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$13051.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$13051.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$11351.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$13000.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$13000.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$12885.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$12885.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$12885.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$12885.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$12885.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$12885.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$10881.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$10765.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$11717.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
|
|
Optimizing lut $abc$87474$lut$aiger87473$11717.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$11717.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$11717.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
|
|
Optimizing lut $abc$87474$lut$aiger87473$12354.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$12354.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$12354.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$12354.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$11687.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$12675.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$12675.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$12550.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$12550.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$12550.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$12550.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$12550.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$12550.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$12409.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$12409.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$12409.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$12409.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$12409.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$12409.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$11405.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$11405.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$11405.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$11042.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
|
|
Optimizing lut $abc$87474$lut$aiger87473$11042.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
|
|
Optimizing lut $abc$87474$lut$aiger87473$11042.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
|
|
Optimizing lut $abc$87474$lut$aiger87473$10735.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$10735.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$10735.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$6496.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$6496.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$6496.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$6511.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$6511.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$6511.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$6511.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$11362.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$11362.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$11265.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$9494.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$11208.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$11208.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$11208.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$11375.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
|
|
Optimizing lut $abc$87474$lut$aiger87473$11483.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$11483.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$11558.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$11558.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$11558.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$10460.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$9852.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$10000.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$10000.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$10000.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$10000.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$10000.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$11858.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$11858.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$11858.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$10069.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$9880.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$10705.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$10217.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
|
|
Optimizing lut $abc$87474$lut$aiger87473$10217.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
|
|
Optimizing lut $abc$87474$lut$aiger87473$10217.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
|
|
Optimizing lut $abc$87474$lut$aiger87473$10217.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
|
|
Optimizing lut $abc$87474$lut$aiger87473$10017.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$10017.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$10017.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$9925.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$9913.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$9905.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$9905.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$8567.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$10094.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$10094.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$10084.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$10084.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$8353.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
|
|
Optimizing lut $abc$87474$lut$aiger87473$8353.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$10609.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$10609.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$10609.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$10609.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$10480.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$10480.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$10480.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$8834.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$8834.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$10514.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$10514.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$10470.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$10470.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$10470.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$7621.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$7621.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$7621.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$8730.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$8755.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$8755.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$10294.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$10294.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$10294.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$10327.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$10327.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$10335.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$10335.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$10284.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$10284.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$10284.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$8691.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$8691.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$9252.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$9252.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$9252.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$9252.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$7810.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$9110.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$9110.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$9139.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$9139.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$9100.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$9100.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$9100.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$9329.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$9329.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$7919.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$7919.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$9365.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$9365.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$9319.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$9319.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$9319.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$9821.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$9821.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$9821.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$9750.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$9750.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$9704.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$9704.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$9714.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$9714.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$9714.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$8231.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$9519.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$9519.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$8129.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$8129.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$9509.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$9509.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$9509.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$9552.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$9552.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$8256.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$8256.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$6806.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$6806.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$6478.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$6478.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$6478.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$6478.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$6478.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$6526.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$6526.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$6526.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$7762.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$7762.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$7779.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$7779.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$7779.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$7779.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$7779.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$7779.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$7790.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$7790.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$7790.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$7790.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$7790.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$7790.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$7790.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$7858.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$6649.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$6649.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$6649.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$6649.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$6649.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$7909.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$7909.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$7933.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$7933.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$7979.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$7979.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$6956.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$6956.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$6956.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$8060.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$8060.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$8075.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$8075.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$8083.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$8083.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$8156.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$8140.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$8140.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$8140.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$8140.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$8140.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$8140.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$8987.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$8702.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$8702.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$8710.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$8710.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$8782.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$8782.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$8766.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$8766.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$8766.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$8766.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$8766.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$8766.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$8766.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$8379.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$8379.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$8379.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$7139.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$7139.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$7139.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$8411.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$8411.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$8816.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$8826.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$8826.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$8906.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$7579.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$7579.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$7579.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$7579.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$7597.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$7597.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$7597.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$7467.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$7467.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$7467.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$7260.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$7260.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$7260.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$7260.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$8515.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$8525.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$8525.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$8539.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$8539.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$8547.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$8547.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$8603.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$8603.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$8603.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$8603.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$8603.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$8603.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$8592.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$8592.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$8592.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$7722.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$7722.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$6543.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$6543.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$6543.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$6405.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$5435.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$5435.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$5469.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$5469.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$6423.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$6423.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$6415.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$6415.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$6415.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$6434.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$6434.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$6434.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$6434.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$6434.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$6434.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$6434.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$6445.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$6445.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$6445.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$6445.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$6445.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$6445.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$6445.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$4873.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$4873.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$6667.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$6667.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$6667.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$6667.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$6605.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$6605.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$6597.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$6597.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$6597.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$6613.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$6613.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$6850.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$6850.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$6865.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$6865.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$6865.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$5660.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$5660.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$6762.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$6762.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$6754.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$6754.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$6754.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$6770.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$6770.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$4774.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$4774.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$5786.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$5786.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$6907.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$6907.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$6899.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$6899.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$6899.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$6915.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$6915.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$6923.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$6923.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$7667.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
|
|
Optimizing lut $abc$87474$lut$aiger87473$7667.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
|
|
Optimizing lut $abc$87474$lut$aiger87473$7158.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$7158.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$7158.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$7084.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$7084.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$7076.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$7076.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$7076.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$7095.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$7095.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$7095.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$7095.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$7095.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$7095.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$7095.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$7106.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$7106.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$7106.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$7106.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$7106.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$7106.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$7106.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$5947.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$5947.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$7178.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$7178.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$7178.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$7178.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$7278.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$7278.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$7210.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$7210.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$7219.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$7219.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$7227.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$7227.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$7365.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$7365.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$7357.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$7357.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$7357.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$7373.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$7373.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$7381.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$7381.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$7452.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$7452.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$7452.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$7452.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$7638.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$7638.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$7638.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$5149.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$5149.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$6189.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$6189.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$6220.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$6220.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$7524.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$7524.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$7516.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$7516.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$7516.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$7535.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$7535.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$7535.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$7535.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$7535.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$7535.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$7535.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$7546.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$7546.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$7546.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$7546.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$7546.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$7546.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$7546.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$5566.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$5566.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$5558.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$5558.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$5558.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$4698.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$4698.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$5652.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$5652.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$5759.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$5759.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$5768.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$5768.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$5778.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$5778.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$5778.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$4892.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$5446.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$5446.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$5446.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$5446.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$5446.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$5446.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$5461.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$5461.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$4829.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$4829.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$4829.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$4829.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$4829.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$4829.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$4829.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$4857.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$4857.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$4865.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$4865.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$4688.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$4688.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$4732.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$4732.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$4758.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$4758.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$4750.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$4750.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$4750.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$4766.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$4766.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$4818.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$4818.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$4849.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$4849.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$4941.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$4941.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$3704.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$3704.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$3922.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$3922.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$4234.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$4234.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$3686.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$3686.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$4245.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$4245.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$4245.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$4267.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$4267.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$3714.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$3714.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$3944.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$3944.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$3978.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$3978.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$4326.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$4326.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$3738.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$3738.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$4359.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$4359.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$4359.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$3777.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$3777.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$4000.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$4000.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$3759.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$3759.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$5961.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$5898.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$5898.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$5910.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$5910.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$5910.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$5910.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$5910.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$5910.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$5928.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$5928.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$5920.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$5920.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$5920.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$5313.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$5313.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$6076.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$6076.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$6076.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$5991.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$5991.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$6009.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$6009.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$6001.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$6001.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$6001.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$5199.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$5276.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$5217.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$5217.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$5231.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$5231.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$4474.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$4474.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$3813.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$3813.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$5346.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$5286.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$5286.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$5305.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$5305.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$4441.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$4441.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$3792.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$3792.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$4452.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$4452.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$4452.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$3853.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$3853.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$5054.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$5054.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$6100.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$6100.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$6109.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$6109.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$6119.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$6119.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$6119.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$5046.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$5046.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$4521.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$4521.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$4521.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$4099.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$4099.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$3835.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$3835.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$5096.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$5096.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$6200.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$6200.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$6200.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$6200.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$6200.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$6200.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$6212.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$6212.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$6212.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$5107.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$5107.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$5107.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$5107.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$5107.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$5107.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$5107.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$5133.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$5133.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$5125.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$5125.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$5141.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$5141.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$4551.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$4551.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$4551.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$3863.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$3863.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$4123.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$4123.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$4562.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$4562.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$4562.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$19068.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger$o606.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$10408.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$19462.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$7752.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$12409.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$6405.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$9110.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$19051.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$7752.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$7762.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$16422.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$7762.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$6415.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$19018.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$14772.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$11042.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$87489.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$10408.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$7139.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$18999.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$6434.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$6445.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$87495.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$7779.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$7779.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$7790.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$14967.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$8755.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$8766.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$7858.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$7158.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$11746.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$87503.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$16391.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
|
|
Optimizing lut $abc$87474$lut$aiger87473$7178.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$7278.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$5652.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$1616.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$10000.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$15211.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$4688.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$12989.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$8603.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$10735.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$1646.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$13682.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$8755.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$3501.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$4688.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$5652.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$7210.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$6478.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger$o568.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$17110.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger$o24.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger$o15.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$13426.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$13651.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$7210.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$17098.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger$o565.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$11072.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$10592.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$6496.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$1782.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$7839.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$17087.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
|
|
Optimizing lut $abc$87474$lut$aiger87473$9494.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$4750.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$10631.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$87724.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$87528.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$20178.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$10017.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$11351.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger$o337.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$6526.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$18860.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$87715.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$18860.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$87549.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$17066.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$6543.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger$o342.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
|
|
Optimizing lut $abc$87474$lut$aiger$o345.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$87602.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
|
|
Optimizing lut $abc$87474$lut$aiger87473$13959.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$9509.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$6563.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$87604.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$87565.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$87566.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
|
|
Optimizing lut $abc$87474$lut$aiger87473$3669.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$87567.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$87682.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$7260.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$87568.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
|
|
Optimizing lut $abc$87474$lut$aiger$o363.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$8816.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$18822.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$13651.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$87571.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
|
|
Optimizing lut $abc$87474$lut$aiger87473$4818.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$4829.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$8379.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$87574.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
|
|
Optimizing lut $abc$87474$lut$aiger$o495.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$3686.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$87577.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
|
|
Optimizing lut $abc$87474$lut$aiger87473$5778.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$7278.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$5446.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$10765.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$4234.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$9519.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$87580.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
|
|
Optimizing lut $abc$87474$lut$aiger87473$18799.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$8826.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$4818.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$9235.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$4849.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$18783.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$3714.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$15667.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$6597.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$8826.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$8906.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$10460.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$10769.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$12257.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$87608.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
|
|
Optimizing lut $abc$87474$lut$aiger87473$3738.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$12760.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$4326.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$87620.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$8411.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$8411.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$4849.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$7909.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$7909.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$3759.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$2097.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$9519.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$87623.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$7316.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$4892.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$14279.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$18731.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$87599.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
|
|
Optimizing lut $abc$87474$lut$aiger87473$3792.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$10470.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$18725.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$4441.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$3813.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$10069.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$4941.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$4474.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$9866.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$10284.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$6649.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$3835.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$4941.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$8862.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$15085.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$5046.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$16925.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$14243.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$7357.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$10793.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$87620.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$10480.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$87621.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$3863.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$87623.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$5125.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$87624.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$17727.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$87625.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$87626.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$18607.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$2323.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger$o156.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$87627.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$87628.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$87629.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$10294.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$87630.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger$o156.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger$o157.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$8888.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$87631.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$16899.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$12916.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger$o159.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
|
|
Optimizing lut $abc$87474$lut$aiger87473$5910.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger$o159.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$87632.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$87633.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger$o160.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$19825.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger$o161.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$10084.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger$o162.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$5920.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$6705.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$87634.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$87635.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger$o458.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$18638.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$9905.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$87636.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$3922.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
|
|
Optimizing lut $abc$87474$lut$aiger87473$10094.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$16179.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$87637.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$87638.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$9235.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$2398.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$87640.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$87640.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$3922.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
|
|
Optimizing lut $abc$87474$lut$aiger87473$13897.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$87641.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$87644.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$87644.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$7979.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$7979.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$3944.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger$o169.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
|
|
Optimizing lut $abc$87474$lut$aiger$o169.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$18589.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$5910.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$10488.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$87647.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$87647.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$2415.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
|
|
Optimizing lut $abc$87474$lut$aiger87473$3944.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$9636.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$14223.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$5947.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$18613.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$2684.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$8483.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$5046.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$9329.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$87656.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$3978.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$7415.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$5961.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$2492.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$3978.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$10094.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$18576.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$16850.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$4000.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$16839.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$6754.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$9852.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$12581.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$4000.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$16830.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
|
|
Optimizing lut $abc$87474$lut$aiger87473$6001.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$5096.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$5107.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$5305.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$5096.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$87676.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$9866.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$18522.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$13854.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$14562.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$5125.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$5231.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$8515.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$8525.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger$o225.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$8525.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$7467.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$9880.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$10084.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$7477.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$6200.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$15496.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$87689.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$2677.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$2694.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$6806.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$13854.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$13081.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$19269.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$18056.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$4099.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$7506.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$8060.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$8060.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$19242.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$87680.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$18472.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$3863.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$19173.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$4123.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$13303.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$17537.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$16753.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$12438.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$6076.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$19532.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$18446.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
|
|
Optimizing lut $abc$87474$lut$aiger87473$7506.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$9319.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$7516.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$87699.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$87700.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$17513.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$11591.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$14531.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$18363.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$6850.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$13534.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$5231.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$19495.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$13815.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$19477.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$5258.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$9329.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$6119.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$11122.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$6865.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$6875.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$7535.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$19462.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$7546.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$9905.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$5199.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$19446.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$11265.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$8140.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$16316.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$12885.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$6899.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$19425.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$12885.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$7579.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$5276.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$5286.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$5286.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$4224.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$4234.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$9636.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$18363.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$19402.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$4245.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$3686.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
|
|
Optimizing lut $abc$87474$lut$aiger87473$18357.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
|
|
Optimizing lut $abc$87474$lut$aiger$o295.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$9925.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$87706.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$8592.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$8603.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$5305.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$19388.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$4267.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$4267.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$8156.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$8129.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$2958.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$8140.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$17427.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$7579.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$6189.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$16652.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
|
|
Optimizing lut $abc$87474$lut$aiger87473$6200.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$19365.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$6189.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$13051.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$3714.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$7597.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$5346.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$8129.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$13682.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$6212.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$4326.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$14468.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$3738.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$6956.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$18494.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
|
|
Optimizing lut $abc$87474$lut$aiger87473$4359.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$16671.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$19290.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$18548.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$9821.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$7621.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$13051.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$19290.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$11858.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$3759.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$14425.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$19269.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$7260.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$87498.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$16578.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
|
|
Optimizing lut $abc$87474$lut$aiger87473$19256.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
|
|
Optimizing lut $abc$87474$lut$aiger87473$7638.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$11687.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$16570.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
|
|
Optimizing lut $abc$87474$lut$aiger87473$15907.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$18197.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$6806.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$19242.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
|
|
Optimizing lut $abc$87474$lut$aiger87473$11405.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$19230.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$5435.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$3147.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$5446.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$9704.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$17313.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$5435.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$19202.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
|
|
Optimizing lut $abc$87474$lut$aiger87473$11558.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$4441.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$12550.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$12550.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$5461.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$7038.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$4452.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$3792.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$6300.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$11208.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$5461.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$18132.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$14425.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$9714.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$4474.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$3203.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$17367.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$3813.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$19173.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$19495.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$5486.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$14049.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$16106.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
|
|
Optimizing lut $abc$87474$lut$aiger87473$16516.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$17261.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$7076.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$16477.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$11613.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
|
|
Optimizing lut $abc$87474$lut$aiger87473$4521.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$8256.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$8256.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$17252.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
|
|
Optimizing lut $abc$87474$lut$aiger87473$9704.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$3835.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$4099.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$19256.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$87492.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$14386.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$12409.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$7095.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$7106.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$18084.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$4551.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$17271.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
|
|
Optimizing lut $abc$87474$lut$aiger87473$6376.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$7722.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$4562.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$19094.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $abc$87474$lut$aiger87473$9100.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$16477.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$8987.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$4123.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$5558.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
|
|
Optimizing lut $abc$87474$lut$aiger87473$8483.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$87474$lut$aiger87473$18541.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
|
|
Optimizing lut $abc$87474$lut$aiger87473$9110.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
|
|
Removed 0 unused cells and 7771 unused wires.
|
|
|
|
22.49. Executing AUTONAME pass.
|
|
Renamed 19378 objects in module spi_neuron_top.
|
|
<suppressed ~19378 debug messages>
|
|
|
|
22.50. Executing HIERARCHY pass (managing design hierarchy).
|
|
Attribute `top' found on module `spi_neuron_top'. Setting top module to spi_neuron_top.
|
|
|
|
22.50.1. Analyzing design hierarchy..
|
|
Top module: \spi_neuron_top
|
|
|
|
22.50.2. Analyzing design hierarchy..
|
|
Top module: \spi_neuron_top
|
|
Removed 0 unused modules.
|
|
|
|
22.51. Printing statistics.
|
|
|
|
=== spi_neuron_top ===
|
|
|
|
+----------Local Count, excluding submodules.
|
|
|
|
|
8673 wires
|
|
17641 wire bits
|
|
8673 public wires
|
|
17641 public wire bits
|
|
14 ports
|
|
50 port bits
|
|
19 cells
|
|
19 $scopeinfo
|
|
11137 submodules
|
|
1117 L6MUX21
|
|
6436 LUT4
|
|
2164 PFUMX
|
|
1420 TRELLIS_FF
|
|
|
|
=== design hierarchy ===
|
|
|
|
+----------Count including submodules.
|
|
|
|
|
19 spi_neuron_top
|
|
|
|
+----------Count including submodules.
|
|
|
|
|
8673 wires
|
|
17641 wire bits
|
|
8673 public wires
|
|
17641 public wire bits
|
|
14 ports
|
|
50 port bits
|
|
- memories
|
|
- memory bits
|
|
- processes
|
|
19 cells
|
|
19 $scopeinfo
|
|
11137 submodules
|
|
1117 L6MUX21
|
|
6436 LUT4
|
|
2164 PFUMX
|
|
1420 TRELLIS_FF
|
|
|
|
22.52. Executing CHECK pass (checking for obvious problems).
|
|
Checking module spi_neuron_top...
|
|
Found and reported 0 problems.
|
|
|
|
22.53. Executing JSON backend.
|
|
|
|
Warnings: 1 unique messages, 1 total
|
|
End of script. Logfile hash: c8074e544e, time: 4.80s, user: 3.16s, system: 0.13s, MEM: 316.88 MB peak
|
|
Yosys 0.68+post (git sha1 c12172fbae8af5e20f6fb52e3d4e92d56ed587b6, Release, AppleClang clang++ 21.0.0.21000101)
|
|
Time spent: 23% 1x abc9_exe (1 sec), 16% 1x abc (0 sec), ...
|