micheleandClaude Sonnet 5
9e1f16db47
sdram_arbiter_hier.v: fixes EXP-0093's own real, traced P&R timing failure (flat 21-way req_wdata mux, route-delay-dominated). Reuses sdram_arbiter_n.v unmodified, twice: 4 leaf instances (NUM_REQ=5, one per group) + 1 top instance (NUM_REQ=5: 4 groups + host, host bypassed/unpipelined), one real pipeline register stage between levels. Isolated verification (tb_sdram_arbiter_hier.v): 23/23 PASS. Two real bugs found and fixed via signal tracing: a testbench helper not waiting for grant before firing req, and a genuine RTL lost-pulse bug at the leaf-to-top boundary (a transient one-shot request could be dropped if the top level was busy with a different group) -- fixed with a sticky per-group pending_req_r latch. Wired into n16_system_ddr3_top.v (drop-in). Real, full P&R re-run: WNS improved -0.913ns -> -0.646ns, TNS -690ns -> -97.5ns, failing endpoints 3021 -> 771 -- substantial, measured improvement, confirming the arbiter was correctly root-caused (bottleneck moved elsewhere: neural_processor_packed.v's own already-thin-margin MAC datapath, eroded by N=16's higher overall congestion). Functional xsim still 32/32 PASS. Timing not yet fully closed -- real next steps documented, not yet attempted without further direction. Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01MUG92aM9m68TRc4rG55BcC
243 lines
12 KiB
Verilog
243 lines
12 KiB
Verilog
`timescale 1ns/1ps
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// ============================================================
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// EXP-0094 -- isolated correctness test for sdram_arbiter_hier.v,
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// NUM_REQ=21 (this project's real N=16 topology: N_GROUPS=4,
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// PES_PER_GROUP=4, +1 host), same real "one variable at a time"
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// discipline every other new module in this project follows -- verify
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// the new hierarchical arbiter in isolation BEFORE wiring it into
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// n16_system_ddr3_top.v and re-running a real P&R.
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//
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// Reuses tb_sdram_arbiter_n.v's own proven real methodology (same
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// `burst_mem_model32.v` mock controller, same one-shot-pulse requester
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// task mirroring packed_slot.v's/act_tile_fetch.v's real risky
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// pattern), scaled up and extended to specifically exercise the NEW
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// real risk this module introduces: cross-group AND within-group
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// simultaneous contention, verifying every response routes back to
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// the CORRECT requester -- the same class of bug (misrouted wide-bus
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// response) already found and fixed twice this session in similar
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// flattened-bus contexts (tb_systolic_group.v's arbiter offset,
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// EXP-0089; this module's own leaf/top slot-index un-concatenation).
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// ============================================================
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module tb;
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localparam BURST_LEN = 8;
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localparam ADDR_WIDTH = 25;
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localparam CLK_FREQ_MHZ = 64;
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localparam CLK_PERIOD_NS = 1000.0/CLK_FREQ_MHZ;
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localparam N_GROUPS = 4;
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localparam PES_PER_GROUP = 4;
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localparam NUM_REQ = N_GROUPS*(1+PES_PER_GROUP) + 1; // 21
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reg clk = 0;
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always #(CLK_PERIOD_NS/2.0) clk = ~clk;
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reg rst;
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wire ctrl_req, ctrl_wr;
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wire [ADDR_WIDTH-1:0] ctrl_addr;
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wire [32*BURST_LEN-1:0] ctrl_wdata, ctrl_rdata;
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wire [4*BURST_LEN-1:0] ctrl_wmask;
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wire ctrl_ready, ctrl_busy;
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burst_mem_model32 #(
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.BURST_LEN(BURST_LEN), .ADDR_WIDTH(ADDR_WIDTH)
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) u_mem (
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.clk(clk), .rst(rst),
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.req(ctrl_req), .wr(ctrl_wr), .addr(ctrl_addr), .wdata(ctrl_wdata), .wmask(ctrl_wmask),
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.rdata(ctrl_rdata), .ready(ctrl_ready), .busy(ctrl_busy)
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);
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reg [NUM_REQ-1:0] req_active, req_req, req_wr;
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wire [NUM_REQ-1:0] req_grant, req_ready, req_busy;
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reg [NUM_REQ*ADDR_WIDTH-1:0] req_addr;
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reg [NUM_REQ*32*BURST_LEN-1:0] req_wdata;
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reg [NUM_REQ*4*BURST_LEN-1:0] req_wmask;
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wire [NUM_REQ*32*BURST_LEN-1:0] req_rdata;
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sdram_arbiter_hier #(
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.N_GROUPS(N_GROUPS), .PES_PER_GROUP(PES_PER_GROUP),
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.ADDR_WIDTH(ADDR_WIDTH), .BURST_LEN(BURST_LEN)
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) u_arb (
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.clk(clk), .rst(rst),
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.req_active(req_active), .req_grant(req_grant),
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.req_req(req_req), .req_wr(req_wr), .req_addr(req_addr),
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.req_wdata(req_wdata), .req_wmask(req_wmask),
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.req_rdata(req_rdata), .req_ready(req_ready), .req_busy(req_busy),
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.ctrl_req(ctrl_req), .ctrl_wr(ctrl_wr), .ctrl_addr(ctrl_addr),
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.ctrl_wdata(ctrl_wdata), .ctrl_wmask(ctrl_wmask),
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.ctrl_rdata(ctrl_rdata), .ctrl_ready(ctrl_ready), .ctrl_busy(ctrl_busy)
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);
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integer errors, tests;
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// helper: real global slot index for group g's weight-fetch (local 0)
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// or PE p (local 1..PES_PER_GROUP), matching sdram_arbiter_hier.v's
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// own fixed slot-map convention exactly.
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function automatic integer wf_slot(input integer g);
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wf_slot = g;
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endfunction
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function automatic integer pe_slot(input integer g, input integer p);
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pe_slot = N_GROUPS + g*PES_PER_GROUP + p;
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endfunction
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// one-shot-pulse requester task -- REAL fix (found via signal
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// tracing, EXP-0094): the original version (copied verbatim from
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// tb_sdram_arbiter_n.v) fired req_req the SAME cycle as req_active,
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// unconditionally, NOT waiting for req_grant first. That happens to
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// work for a flat, single-level arbiter's own uncontended sequential
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// tests, but is NOT how real requesters in this project actually
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// behave -- confirmed via `act_tile_fetch.v`'s own real S_MEMWAIT
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// state ("ctrl_req is only issued after mem_grant is observed,
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// never blind", act_tile_fetch.v's own header + S_MEMWAIT: if
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// (mem_grant) ctrl_req<=1, a REGISTERED assign, taking effect the
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// cycle AFTER grant is seen). This module's own hierarchical design
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// introduces a real, legitimate extra lock-release lag (1-2 cycles)
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// after a prior transaction on a DIFFERENT slot completes, which a
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// same-cycle blind fire can race -- exactly the real EXP-0066 risk
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// class, just newly exercised by sequential-but-different-slot
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// traffic instead of only true simultaneous contention. Fixed to
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// match the real S_MEMWAIT sequencing (and this file's own already-
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// correct `concurrent_contention` task): wait for req_grant, THEN
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// one more posedge, THEN pulse req_req.
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task automatic one_shot_txn(
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input integer slot, input t_wr, input [ADDR_WIDTH-1:0] t_addr,
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input [32*BURST_LEN-1:0] t_wdata, output [32*BURST_LEN-1:0] t_rdata
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);
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begin
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@(posedge clk);
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req_active[slot] = 1'b1;
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req_wr[slot] = t_wr;
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req_addr[slot*ADDR_WIDTH +: ADDR_WIDTH] = t_addr;
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req_wdata[slot*32*BURST_LEN +: 32*BURST_LEN] = t_wdata;
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req_wmask[slot*4*BURST_LEN +: 4*BURST_LEN] = {(4*BURST_LEN){1'b0}};
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while (!req_grant[slot]) @(posedge clk);
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@(posedge clk);
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req_req[slot] = 1'b1;
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@(posedge clk);
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req_req[slot] = 1'b0;
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while (!req_ready[slot]) @(posedge clk);
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t_rdata = req_rdata[slot*32*BURST_LEN +: 32*BURST_LEN];
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req_active[slot] = 1'b0;
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end
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endtask
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reg [32*BURST_LEN-1:0] got, wpat;
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task automatic check_slot(input integer slot, input [ADDR_WIDTH-1:0] a, input [15:0] pattern);
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integer i;
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begin
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for (i = 0; i < BURST_LEN; i = i + 1)
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wpat[i*32 +: 32] = {pattern, pattern + i[15:0]};
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one_shot_txn(slot, 1'b1, a, wpat, got);
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one_shot_txn(slot, 1'b0, a, {(32*BURST_LEN){1'b0}}, got);
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tests = tests + 1;
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if (got !== wpat) begin
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$display("FAIL slot=%0d addr=%0d: got=%h expected=%h", slot, a, got, wpat);
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errors = errors + 1;
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end else begin
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$display("PASS slot=%0d addr=%0d: bit-exact", slot, a);
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end
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end
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endtask
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// concurrent-contention task: N requesters (given by the module-
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// level `csl`/`caddr`/`cpat` arrays, set by the caller just before
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// invoking this task -- Verilog-2001 tasks can't take dynamic array
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// args cleanly) all raise `active` the SAME cycle, each only
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// pulsing its own `req` once ITS OWN grant is observed (real,
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// established packed_slot.v-style S_MEMWAIT discipline, not a
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// blind simultaneous fire) -- then all read back bit-exact, proving
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// no cross-requester corruption/misrouting through either arbiter
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// level. Explicit, unrolled per-requester fork branches (n<=8 real
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// max used in this test) avoid the classic Verilog for-loop-inside-
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// fork variable-capture race entirely.
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reg [32*BURST_LEN-1:0] cwpat [0:7];
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integer csl [0:7];
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reg [ADDR_WIDTH-1:0] caddr [0:7];
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reg [15:0] cpat [0:7];
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task automatic concurrent_contention(input integer n);
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integer k, kk;
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begin
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for (k = 0; k < n; k = k + 1) begin
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for (kk = 0; kk < BURST_LEN; kk = kk + 1)
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cwpat[k][kk*32 +: 32] = {cpat[k], cpat[k] + kk[15:0]};
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req_addr[csl[k]*ADDR_WIDTH +: ADDR_WIDTH] = caddr[k];
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req_wdata[csl[k]*32*BURST_LEN +: 32*BURST_LEN] = cwpat[k];
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req_wr[csl[k]] = 1'b1;
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end
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@(posedge clk);
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for (k = 0; k < n; k = k + 1) req_active[csl[k]] = 1'b1;
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fork
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if (n > 0) begin while (!req_grant[csl[0]]) @(posedge clk); @(posedge clk); req_req[csl[0]]=1'b1; @(posedge clk); req_req[csl[0]]=1'b0; while(!req_ready[csl[0]]) @(posedge clk); req_active[csl[0]]=1'b0; end
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if (n > 1) begin while (!req_grant[csl[1]]) @(posedge clk); @(posedge clk); req_req[csl[1]]=1'b1; @(posedge clk); req_req[csl[1]]=1'b0; while(!req_ready[csl[1]]) @(posedge clk); req_active[csl[1]]=1'b0; end
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if (n > 2) begin while (!req_grant[csl[2]]) @(posedge clk); @(posedge clk); req_req[csl[2]]=1'b1; @(posedge clk); req_req[csl[2]]=1'b0; while(!req_ready[csl[2]]) @(posedge clk); req_active[csl[2]]=1'b0; end
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if (n > 3) begin while (!req_grant[csl[3]]) @(posedge clk); @(posedge clk); req_req[csl[3]]=1'b1; @(posedge clk); req_req[csl[3]]=1'b0; while(!req_ready[csl[3]]) @(posedge clk); req_active[csl[3]]=1'b0; end
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if (n > 4) begin while (!req_grant[csl[4]]) @(posedge clk); @(posedge clk); req_req[csl[4]]=1'b1; @(posedge clk); req_req[csl[4]]=1'b0; while(!req_ready[csl[4]]) @(posedge clk); req_active[csl[4]]=1'b0; end
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if (n > 5) begin while (!req_grant[csl[5]]) @(posedge clk); @(posedge clk); req_req[csl[5]]=1'b1; @(posedge clk); req_req[csl[5]]=1'b0; while(!req_ready[csl[5]]) @(posedge clk); req_active[csl[5]]=1'b0; end
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if (n > 6) begin while (!req_grant[csl[6]]) @(posedge clk); @(posedge clk); req_req[csl[6]]=1'b1; @(posedge clk); req_req[csl[6]]=1'b0; while(!req_ready[csl[6]]) @(posedge clk); req_active[csl[6]]=1'b0; end
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if (n > 7) begin while (!req_grant[csl[7]]) @(posedge clk); @(posedge clk); req_req[csl[7]]=1'b1; @(posedge clk); req_req[csl[7]]=1'b0; while(!req_ready[csl[7]]) @(posedge clk); req_active[csl[7]]=1'b0; end
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join
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tests = tests + 1;
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$display("PASS: %0d simultaneous requests completed (none silently lost)", n);
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for (k = 0; k < n; k = k + 1)
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check_slot(csl[k], caddr[k], cpat[k]);
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end
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endtask
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// real watchdog -- this testbench originally had none, and a real
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// protocol bug in a new module (unlike every other testbench in
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// this project, which uses a `wd` cycle-counted watchdog inside its
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// own completion-wait loop) spun forever burning CPU with zero
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// output instead of failing cleanly. Real, generalizable lesson.
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initial begin
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#500000;
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$display("FAIL: WATCHDOG TIMEOUT -- simulation did not complete within 500000ns");
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$finish;
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end
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initial begin
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errors = 0; tests = 0;
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rst = 1; req_active = 0; req_req = 0; req_wr = 0; req_addr = 0; req_wdata = 0; req_wmask = 0;
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repeat(5) @(posedge clk);
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rst = 0;
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@(posedge clk);
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$display("=== TEST 1: sequential single-requester, spanning weight-fetch/PE/host slots across all 4 groups ===");
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check_slot(wf_slot(0), 25'd0, 16'hA000);
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check_slot(pe_slot(0,0), 25'd8, 16'hA100);
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check_slot(pe_slot(0,3), 25'd16, 16'hA200);
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check_slot(wf_slot(2), 25'd24, 16'hA300);
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check_slot(pe_slot(2,1), 25'd32, 16'hA400);
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check_slot(NUM_REQ-1 /* host */, 25'd40, 16'hA500);
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$display("=== TEST 2: WITHIN-group contention (leaf-level arbitration) -- group 1's weight-fetch + all 4 PEs simultaneously ===");
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csl[0]=wf_slot(1); caddr[0]=25'd100; cpat[0]=16'hB000;
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csl[1]=pe_slot(1,0); caddr[1]=25'd108; cpat[1]=16'hB100;
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csl[2]=pe_slot(1,1); caddr[2]=25'd116; cpat[2]=16'hB200;
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csl[3]=pe_slot(1,2); caddr[3]=25'd124; cpat[3]=16'hB300;
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csl[4]=pe_slot(1,3); caddr[4]=25'd132; cpat[4]=16'hB400;
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concurrent_contention(5);
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$display("=== TEST 3: CROSS-group contention (top-level arbitration) -- all 4 groups' own weight-fetch simultaneously ===");
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csl[0]=wf_slot(0); caddr[0]=25'd200; cpat[0]=16'hC000;
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csl[1]=wf_slot(1); caddr[1]=25'd208; cpat[1]=16'hC100;
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csl[2]=wf_slot(2); caddr[2]=25'd216; cpat[2]=16'hC200;
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csl[3]=wf_slot(3); caddr[3]=25'd224; cpat[3]=16'hC300;
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concurrent_contention(4);
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$display("=== TEST 4: full contention -- one PE from EACH of the 4 groups, simultaneously, plus host at the same time (real, worst-case mixed cross-group + bypass-path contention) ===");
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csl[0]=pe_slot(0,2); caddr[0]=25'd300; cpat[0]=16'hD000;
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csl[1]=pe_slot(1,3); caddr[1]=25'd308; cpat[1]=16'hD100;
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csl[2]=pe_slot(2,0); caddr[2]=25'd316; cpat[2]=16'hD200;
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csl[3]=pe_slot(3,1); caddr[3]=25'd324; cpat[3]=16'hD300;
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csl[4]=NUM_REQ-1; caddr[4]=25'd332; cpat[4]=16'hD400;
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concurrent_contention(5);
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$display("=== %0d/%0d tests, %0d errors ===", tests-errors, tests, errors);
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if (errors == 0) $display("ALL TESTS PASSED (tb_sdram_arbiter_hier)");
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$finish;
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end
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endmodule
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