micheleandClaude Sonnet 5
5afa6a7477
New hardware/v3/rtl/np_packed_weight_reuse_top.v: flat structural synthesis wrapper around the EXP-0062-verified module chain (real SDR SDRAM controller -> layer_prefetch_ctrl.v -> layer_weight_buffer.v -> weight_tile_gather.v -> neural_processor_packed.v). Real Vivado post-route: 8/240 DSP48E1 (unchanged, memory path uses zero DSPs), WNS -2.502ns @ 200MHz -> Fmax ~133.3MHz, only -1.2% vs the isolated single core (134.9MHz, EXP-0059). Real memory-path control logic adds negligible Fmax cost at this scale. Full writeup in hardware/v2/logs/experiments.log EXP-0063. Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01MUG92aM9m68TRc4rG55BcC
150 lines
6.3 KiB
Verilog
150 lines
6.3 KiB
Verilog
`timescale 1ns/1ps
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// ============================================================
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// V3 -- synthesis top for the EXP-0062 verified weight-reuse memory
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// path + packed compute core, flat structural wiring (real modules,
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// real internal connections), for a real P&R resource/timing check.
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//
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// Control ports (pf_start/tile_req/operand_valid/...) are exposed
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// directly at the top level rather than internally sequenced -- the
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// closed-loop sequencing logic (what EXP-0062's testbench did
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// procedurally) is the still-not-built neural_director.v integration,
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// deliberately out of scope here. This module exists ONLY to let
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// Vivado see the REAL combined logic (SDRAM controller + prefetch +
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// weight buffer + tile gather + packed compute core) together for
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// utilization/timing purposes, matching EXP-0059's own single-core
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// out-of-context methodology.
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// ============================================================
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module np_packed_weight_reuse_top #(
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parameter DATA_WIDTH = 8,
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parameter P_IN = 8,
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parameter ACC_WIDTH = 32,
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parameter BURST_LEN = 8,
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parameter ROW_BITS = 13,
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parameter COL_BITS = 10,
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parameter BANK_BITS = 2,
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parameter ADDR_WIDTH = BANK_BITS + ROW_BITS + COL_BITS,
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parameter LAYER_BYTES = 128,
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parameter BUFADDRW = $clog2(LAYER_BYTES)
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)(
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input wire clk,
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input wire rst,
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// ---- layer_prefetch_ctrl.v control ----
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input wire pf_start,
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input wire [ADDR_WIDTH-1:0] pf_layer_base,
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output wire pf_busy,
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output wire pf_done,
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// ---- layer_weight_buffer.v control ----
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input wire consume_done,
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// ---- weight_tile_gather.v control ----
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input wire tile_req,
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input wire [BUFADDRW-1:0] tile_base,
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output wire tile_valid,
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// ---- neural_processor_packed.v job/operand control ----
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input wire job_valid,
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output wire job_ready,
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input wire [15:0] job_node_id_a,
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input wire [15:0] job_node_id_b,
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input wire signed [DATA_WIDTH-1:0] job_bias,
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input wire [1:0] job_activation,
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input wire operand_valid,
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output wire operand_ready,
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input wire signed [DATA_WIDTH*P_IN-1:0] input_data_a,
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input wire signed [DATA_WIDTH*P_IN-1:0] input_data_b,
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input wire tile_last,
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output wire result_valid,
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input wire result_ready,
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output wire signed [DATA_WIDTH-1:0] result_data_a,
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output wire signed [DATA_WIDTH-1:0] result_data_b,
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output wire [15:0] result_node_id_a,
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output wire [15:0] result_node_id_b,
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// ---- real SDRAM pins ----
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output wire sdram_cke,
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output wire sdram_cs_n,
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output wire sdram_ras_n,
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output wire sdram_cas_n,
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output wire sdram_we_n,
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output wire [BANK_BITS-1:0] sdram_ba,
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output wire [ROW_BITS-1:0] sdram_a,
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inout wire [15:0] sdram_dq,
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output wire [1:0] sdram_dqm
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);
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wire ctrl_req, ctrl_wr, ctrl_ready, ctrl_busy;
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wire [ADDR_WIDTH-1:0] ctrl_addr;
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wire [16*BURST_LEN-1:0] ctrl_wdata, ctrl_rdata;
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wire [2*BURST_LEN-1:0] ctrl_wmask;
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sdram_controller #(
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.CLK_FREQ_MHZ(64), .BURST_LEN(BURST_LEN),
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.ROW_BITS(ROW_BITS), .COL_BITS(COL_BITS), .BANK_BITS(BANK_BITS)
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) u_ctrl (
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.clk(clk), .rst(rst),
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.req(ctrl_req), .wr(ctrl_wr), .addr(ctrl_addr),
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.wdata(ctrl_wdata), .wmask(ctrl_wmask),
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.rdata(ctrl_rdata), .ready(ctrl_ready), .busy(ctrl_busy),
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.sdram_cke(sdram_cke), .sdram_cs_n(sdram_cs_n), .sdram_ras_n(sdram_ras_n),
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.sdram_cas_n(sdram_cas_n), .sdram_we_n(sdram_we_n),
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.sdram_ba(sdram_ba), .sdram_a(sdram_a), .sdram_dq(sdram_dq), .sdram_dqm(sdram_dqm)
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);
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wire pf_fill_we;
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wire [BUFADDRW-1:0] pf_fill_addr;
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wire [DATA_WIDTH-1:0] pf_fill_data;
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layer_prefetch_ctrl #(
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.DATA_WIDTH(DATA_WIDTH), .LAYER_BYTES(LAYER_BYTES), .BURST_LEN(BURST_LEN), .ADDR_WIDTH(ADDR_WIDTH)
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) u_pf (
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.clk(clk), .rst(rst),
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.start(pf_start), .layer_base(pf_layer_base), .busy(pf_busy), .done(pf_done),
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.fill_we(pf_fill_we), .fill_addr(pf_fill_addr), .fill_data(pf_fill_data),
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.ctrl_req(ctrl_req), .ctrl_wr(ctrl_wr), .ctrl_addr(ctrl_addr),
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.ctrl_wdata(ctrl_wdata), .ctrl_wmask(ctrl_wmask),
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.ctrl_rdata(ctrl_rdata), .ctrl_ready(ctrl_ready), .ctrl_busy(ctrl_busy)
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);
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wire [BUFADDRW-1:0] lwb_rd_addr;
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wire [DATA_WIDTH-1:0] lwb_rd_data;
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layer_weight_buffer #(.DATA_WIDTH(DATA_WIDTH), .LAYER_DEPTH(LAYER_BYTES)) u_lwb (
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.clk(clk), .rst(rst),
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.fill_we(pf_fill_we), .fill_addr(pf_fill_addr), .fill_data(pf_fill_data), .fill_done(pf_done),
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.rd_addr(lwb_rd_addr), .rd_data(lwb_rd_data), .consume_done(consume_done),
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.active_sel(), .swapped()
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);
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wire [DATA_WIDTH*P_IN-1:0] tile_data;
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weight_tile_gather #(
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.DATA_WIDTH(DATA_WIDTH), .P_IN(P_IN), .BUFADDRW(BUFADDRW)
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) u_gather (
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.clk(clk), .rst(rst),
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.tile_req(tile_req), .tile_base(tile_base),
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.tile_valid(tile_valid), .tile_data(tile_data),
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.rd_addr(lwb_rd_addr), .rd_data(lwb_rd_data)
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);
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wire [3:0] np_state;
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wire np_error;
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neural_processor_packed #(
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.DATA_WIDTH(DATA_WIDTH), .P_IN(P_IN), .ACC_WIDTH(ACC_WIDTH)
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) u_np (
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.clk(clk), .rst(rst),
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.job_valid(job_valid), .job_ready(job_ready),
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.job_node_id_a(job_node_id_a), .job_node_id_b(job_node_id_b),
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.job_bias(job_bias), .job_activation(job_activation),
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.operand_valid(operand_valid), .operand_ready(operand_ready),
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.input_data_a(input_data_a), .input_data_b(input_data_b),
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.weight_data(tile_data), .tile_last(tile_last),
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.result_valid(result_valid), .result_ready(result_ready),
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.result_data_a(result_data_a), .result_data_b(result_data_b),
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.result_node_id_a(result_node_id_a), .result_node_id_b(result_node_id_b),
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.np_state(np_state), .np_error(np_error)
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);
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endmodule
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