micheleandClaude Sonnet 5
8e014d8d49
FASE #1 hardware freeze for FPGA-Neural V2, N4/P8, single external SDRAM (Alliance Memory AS4C4M16SA-6TIN) serving weights, activations, and results through one physical sdram_controller.v instance. Removes the PSRAM dependency (hardware/v1/rtl/psram_controller.v + memory_interface.v) from the V2 physical path entirely -- V1 itself remains fully unmodified, the golden reference. New RTL: sdram_unified_backend.v (2-way W/AR arbitration over one SDRAM controller, real per-byte DQM write masking added to sdram_controller.v for correct single-byte result writes with no read-modify-write), nms_neural_multiprocessor_sdram_unified.v (the frozen top-level). Two real bugs found and fixed via full-system testing before being accepted (ERR-0023): a deadlock and an off-by-one data-shift bug in the new arbitration logic. Real results: N=4 and N=2 D-Stress bit-exact (256/256 neurons), 40 real AUTO REFRESH events interleaved with zero corruption, real Yosys+nextpnr-ecp5 synthesis/P&R for LFE5U-45F-8CABGA381 (149/245 TRELLIS_IO, a real 45-pin reduction from the prior dual-memory design). Timing is MARGINAL (1/8 P&R seeds >=80MHz), reported honestly rather than masked by the best seed. Real, sourced ball-level pinout for the SDRAM bus + clk/rst (39/149 signals, P&R-verified) using the official Lattice ECP5U-45 pinout CSV found on disk during this step's own pre-commit review -- corrects an earlier draft that wrongly assumed no real pinout data was available. Chip readiness: NO. Real, disclosed blockers remain (no physical host interface exists yet -- the RTL's own reg_* ports are a 110-pin raw test-harness bus; clock source/PLL decision; power/configuration component selection) -- see hardware/v2/docs/{HARDWARE_FREEZE, CHIP_READINESS,OPEN_ITEMS}.md for the complete, itemized status. Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
63 lines
2.1 KiB
Verilog
63 lines
2.1 KiB
Verilog
// ================================================================
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// SYNTHESIS-ONLY TIMING HARNESS -- NOT a functional deliverable.
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// Same pattern as harness_nms_activation_replicated.v /
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// hardware/v2/synthesis/harness_memory_manager.v: reduces
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// nms_activation_banked's wide ports to an LFSR-driven input side and
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// an XOR-checksum output side, keeping only clk/rst/seed/checksum as
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// real pins.
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// ================================================================
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module harness_nms_activation_banked #(
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parameter DATA_WIDTH = 8,
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parameter P_IN = 8,
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parameter N_SLOTS = 4,
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parameter N_BANKS = 4,
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parameter MAX_TILES = 16,
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parameter TIW = (MAX_TILES <= 1) ? 1 : $clog2(MAX_TILES)
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)(
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input wire clk,
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input wire rst,
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input wire [7:0] seed,
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output wire [7:0] checksum
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);
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reg [31:0] lfsr;
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always @(posedge clk) begin
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if (rst) lfsr <= {24'h0, seed} | 32'h1;
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else lfsr <= {lfsr[30:0], lfsr[31] ^ lfsr[21] ^ lfsr[1] ^ lfsr[0]};
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end
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wire fill_we = lfsr[0];
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wire [TIW-1:0] fill_tile_idx = lfsr[TIW-1:0];
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wire [DATA_WIDTH*P_IN-1:0] fill_data = {(DATA_WIDTH*P_IN/32+1){lfsr}};
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wire [N_SLOTS-1:0] req_valid = lfsr[N_SLOTS-1:0];
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wire [N_SLOTS*TIW-1:0] req_tile_idx_flat = {(N_SLOTS*TIW/32+1){lfsr}};
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wire [N_SLOTS-1:0] ack;
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wire [N_SLOTS*DATA_WIDTH*P_IN-1:0] rd_data_flat;
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nms_activation_banked #(
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.DATA_WIDTH(DATA_WIDTH), .P_IN(P_IN), .N_SLOTS(N_SLOTS), .N_BANKS(N_BANKS), .MAX_TILES(MAX_TILES)
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) dut (
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.clk(clk), .rst(rst),
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.fill_we(fill_we), .fill_tile_idx(fill_tile_idx), .fill_data(fill_data),
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.req_valid(req_valid), .req_tile_idx_flat(req_tile_idx_flat),
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.ack(ack), .rd_data_flat(rd_data_flat)
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);
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integer k;
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reg [7:0] chk;
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reg [7:0] chk_next;
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always @(posedge clk) begin
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if (rst) begin
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chk <= 8'h0;
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end else begin
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chk_next = chk ^ {7'h0, ack[0]};
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for (k = 0; k < N_SLOTS; k = k + 1)
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chk_next = chk_next ^ rd_data_flat[k*DATA_WIDTH*P_IN +: 8];
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chk <= chk_next;
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end
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end
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assign checksum = chk;
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endmodule
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