micheleandClaude Sonnet 5
fc0130e2e2
Three chapters (docs/latex/), sourced from the real project docs (BOM.md, PHYSICAL_REALIZATION.md, ARCHITECTURE_ANALYSIS.md, experiments.log) -- no invented numbers: - hardware.tex: board components, DDR3/FPGA/flash/ESP32, real pinout, SPI protocol, boot procedure. - architecture.tex: packed INT8 MAC core, N=8 hybrid systolic architecture (shared-weight broadcast), hierarchical arbiter, result writeback, why N=8 is the DDR3-bandwidth-bound sweet spot. - tests_timing.tex: verification methodology, real functional test results table, full real P&R signoff history (N=2 through N=16), the definitive N=8 signoff (WNS=0.000ns), and an honestly-caveated ESP32-S3 comparison (real historical ECP5 measurement vs. the superseded, never-verified Artix-7 projection). main.tex ties the three together as report chapters. Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01MUG92aM9m68TRc4rG55BcC
44 lines
835 B
TeX
44 lines
835 B
TeX
\documentclass[11pt,a4paper]{report}
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\usepackage[utf8]{inputenc}
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\usepackage[T1]{fontenc}
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\usepackage[italian]{babel}
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\usepackage[margin=2.5cm]{geometry}
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\usepackage{booktabs}
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\usepackage{longtable}
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\usepackage{array}
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\usepackage{xcolor}
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\usepackage{hyperref}
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\usepackage{amsmath}
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\usepackage{listings}
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\usepackage{caption}
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\hypersetup{
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colorlinks=true,
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linkcolor=blue!50!black,
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urlcolor=blue!50!black,
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citecolor=blue!50!black
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}
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\lstset{
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basicstyle=\ttfamily\small,
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breaklines=true,
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frame=single,
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columns=fullflexible
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}
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\title{FPGA-Neural \\ \large Acceleratore neurale su FPGA Xilinx Artix-7}
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\author{}
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\date{Stato al 2026-09-21 --- target reale definitivo: N=8}
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\begin{document}
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\maketitle
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\tableofcontents
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\input{hardware.tex}
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\input{architecture.tex}
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\input{tests_timing.tex}
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\end{document}
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