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FPGA-Neural/synth/ecp5/timing_closure/before/yosys_p8.log
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micheleandClaude Sonnet 5 55c827bedf feat: PSRAM page-mode reads + graph engine (Type #2) + real pinout/IRQ pins 
PSRAM page-mode read burst support in psram_controller.v: enables the
ISSI IS66WVE4M16EBLL-70BLI's page mode via its configuration-register
software-access sequence at boot (disabled by default on the real
chip), then keeps CE#/OE# asserted after a read so a same-page
continuation only pays tAPA (20ns) instead of a full tAA (70ns)
random access, with automatic tCEM-safe session closing. Only a WRITE
closes the page -- byte-enable changes do not, since
int8_memory_access.v alternates them on nearly every access and an
early implementation attempt that treated them as a close condition
measured a real regression (53.25->61.25 cycles/edge) before being
corrected (53.25->37.53 cycles/edge, +42% gather bandwidth).
sim/psram_model.v gained independent tAPA/tAA and tCEM enforcement
(with a real Verilog same-timestep event-ordering race found and
fixed via a #0 sync) so the regression proves real timing compliance,
not just data correctness. New sim/psram_page_mode_tb.v; full 26-file
regression suite re-run clean. Real nextpnr-ecp5 Fmax re-measured on
the full spi_neuron_top system: 75.73MHz (P2, up from 55.59MHz) and
65.13MHz (P8) -- still under the 80MHz target but not regressed, with
the critical path confirmed (not assumed) to remain entirely inside
neuron_parallel's accumulate chain, never psram_controller.

Also includes this session's other already-validated work: the graph
engine (Type #2 sparse-graph network: act_buffer, graph_engine,
netasm host assembler), real CABGA381 pinout (.lpf, place&route
verified) and physical IRQ_N/DATA_READY_N pins, and Phase 7 timing
closure logs -- all previously uncommitted, documented in WORKLOG.md.

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01LH3jPeJ3eFMfF2v8SQhpkk
2026-09-03 17:12:05 +02:00

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/----------------------------------------------------------------------------\
| yosys -- Yosys Open SYnthesis Suite |
| Copyright (C) 2012 - 2026 Claire Xenia Wolf <claire@yosyshq.com> |
| Distributed under an ISC-like license, type "license" to see terms |
\----------------------------------------------------------------------------/
Yosys 0.68+post (git sha1 c12172fbae8af5e20f6fb52e3d4e92d56ed587b6, Release, AppleClang clang++ 21.0.0.21000101)
-- Executing script file `synth/ecp5/timing_closure/before/synth_p8.ys' --
1. Executing Verilog-2005 frontend: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_slave.v
Parsing SystemVerilog input from `/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_slave.v' to AST representation.
Generating RTLIL representation for module `\spi_slave'.
Successfully finished Verilog frontend.
2. Executing Verilog-2005 frontend: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v
Parsing SystemVerilog input from `/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v' to AST representation.
Generating RTLIL representation for module `\spi_engine'.
Successfully finished Verilog frontend.
3. Executing Verilog-2005 frontend: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v
Parsing SystemVerilog input from `/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v' to AST representation.
Generating RTLIL representation for module `\layer_sequencer'.
Successfully finished Verilog frontend.
4. Executing Verilog-2005 frontend: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/act_buffer.v
Parsing SystemVerilog input from `/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/act_buffer.v' to AST representation.
Generating RTLIL representation for module `\act_buffer'.
Successfully finished Verilog frontend.
5. Executing Verilog-2005 frontend: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v
Parsing SystemVerilog input from `/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v' to AST representation.
Generating RTLIL representation for module `\graph_engine'.
Successfully finished Verilog frontend.
6. Executing Verilog-2005 frontend: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mem_arbiter.v
Parsing SystemVerilog input from `/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mem_arbiter.v' to AST representation.
Generating RTLIL representation for module `\mem_arbiter'.
Successfully finished Verilog frontend.
7. Executing Verilog-2005 frontend: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v
Parsing SystemVerilog input from `/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v' to AST representation.
Generating RTLIL representation for module `\neuron_memory'.
Successfully finished Verilog frontend.
8. Executing Verilog-2005 frontend: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/int8_memory_access.v
Parsing SystemVerilog input from `/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/int8_memory_access.v' to AST representation.
Generating RTLIL representation for module `\int8_memory_access'.
Successfully finished Verilog frontend.
9. Executing Verilog-2005 frontend: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/memory_interface.v
Parsing SystemVerilog input from `/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/memory_interface.v' to AST representation.
Generating RTLIL representation for module `\memory_interface'.
Successfully finished Verilog frontend.
10. Executing Verilog-2005 frontend: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/psram_controller.v
Parsing SystemVerilog input from `/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/psram_controller.v' to AST representation.
/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/psram_controller.v:93: Warning: Yosys has only limited support for tri-state logic at the moment.
Generating RTLIL representation for module `\psram_controller'.
Successfully finished Verilog frontend.
11. Executing Verilog-2005 frontend: /tmp/before_rewrite/neuron_parallel.v
Parsing SystemVerilog input from `/tmp/before_rewrite/neuron_parallel.v' to AST representation.
Generating RTLIL representation for module `\neuron_parallel'.
Successfully finished Verilog frontend.
12. Executing Verilog-2005 frontend: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v
Parsing SystemVerilog input from `/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v' to AST representation.
Generating RTLIL representation for module `\mac8'.
Successfully finished Verilog frontend.
13. Executing Verilog-2005 frontend: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v
Parsing SystemVerilog input from `/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v' to AST representation.
Generating RTLIL representation for module `\mac_unit'.
Successfully finished Verilog frontend.
14. Executing Verilog-2005 frontend: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_neuron_top.v
Parsing SystemVerilog input from `/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_neuron_top.v' to AST representation.
Generating RTLIL representation for module `\spi_neuron_top'.
Successfully finished Verilog frontend.
Parameter \PARALLEL = 8
15. Executing AST frontend in derive mode using pre-parsed AST for module `\spi_neuron_top'.
Parameter \PARALLEL = 8
Generating RTLIL representation for module `$paramod\spi_neuron_top\PARALLEL=s32'00000000000000000000000000001000'.
16. Executing HIERARCHY pass (managing design hierarchy).
16.1. Analyzing design hierarchy..
Top module: \spi_neuron_top
Used module: \spi_slave
Used module: \spi_engine
Used module: \layer_sequencer
Used module: \graph_engine
Used module: \neuron_parallel
Used module: \mac8
Used module: \mac_unit
Used module: \act_buffer
Used module: \neuron_memory
Used module: \int8_memory_access
Used module: \mem_arbiter
Used module: \memory_interface
Used module: \psram_controller
Parameter \DATA_WIDTH = 8
Parameter \N_INPUTS = 32
Parameter \PARALLEL = 8
Parameter \ACC_WIDTH = 32
16.2. Executing AST frontend in derive mode using pre-parsed AST for module `\neuron_parallel'.
Parameter \DATA_WIDTH = 8
Parameter \N_INPUTS = 32
Parameter \PARALLEL = 8
Parameter \ACC_WIDTH = 32
Generating RTLIL representation for module `$paramod$18f95495176adabb8b1efa1a4c23d17992af7212\neuron_parallel'.
Parameter \N_TOTAL = 4096
Parameter \DATA_WIDTH = 8
16.3. Executing AST frontend in derive mode using pre-parsed AST for module `\act_buffer'.
Parameter \N_TOTAL = 4096
Parameter \DATA_WIDTH = 8
Generating RTLIL representation for module `$paramod$c614a16d6b975c0ec2885ffa17a962bce4ddbcec\act_buffer'.
Parameter \DATA_WIDTH = 8
Parameter \ACC_WIDTH = 32
Parameter \PARALLEL = 8
16.4. Executing AST frontend in derive mode using pre-parsed AST for module `\mac8'.
Parameter \DATA_WIDTH = 8
Parameter \ACC_WIDTH = 32
Parameter \PARALLEL = 8
Generating RTLIL representation for module `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8'.
Parameter \DATA_WIDTH = 8
Parameter \N_INPUTS = 32
Parameter \PARALLEL = 8
Parameter \ACC_WIDTH = 32
Found cached RTLIL representation for module `$paramod$18f95495176adabb8b1efa1a4c23d17992af7212\neuron_parallel'.
Parameter \ADDR_WIDTH = 23
16.5. Executing AST frontend in derive mode using pre-parsed AST for module `\int8_memory_access'.
Parameter \ADDR_WIDTH = 23
Generating RTLIL representation for module `$paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010111'.
Parameter \DATA_WIDTH = 16
Parameter \ACC_WIDTH = 40
16.6. Executing AST frontend in derive mode using pre-parsed AST for module `\mac_unit'.
Parameter \DATA_WIDTH = 16
Parameter \ACC_WIDTH = 40
Generating RTLIL representation for module `$paramod$913793164bb5cb5821e69ced9b7f953b27ebd911\mac_unit'.
Parameter \DATA_WIDTH = 16
Parameter \ACC_WIDTH = 40
Found cached RTLIL representation for module `$paramod$913793164bb5cb5821e69ced9b7f953b27ebd911\mac_unit'.
Parameter \DATA_WIDTH = 16
Parameter \ACC_WIDTH = 40
Found cached RTLIL representation for module `$paramod$913793164bb5cb5821e69ced9b7f953b27ebd911\mac_unit'.
Parameter \DATA_WIDTH = 16
Parameter \ACC_WIDTH = 40
Found cached RTLIL representation for module `$paramod$913793164bb5cb5821e69ced9b7f953b27ebd911\mac_unit'.
Parameter \DATA_WIDTH = 16
Parameter \ACC_WIDTH = 40
Found cached RTLIL representation for module `$paramod$913793164bb5cb5821e69ced9b7f953b27ebd911\mac_unit'.
Parameter \DATA_WIDTH = 16
Parameter \ACC_WIDTH = 40
Found cached RTLIL representation for module `$paramod$913793164bb5cb5821e69ced9b7f953b27ebd911\mac_unit'.
Parameter \DATA_WIDTH = 16
Parameter \ACC_WIDTH = 40
Found cached RTLIL representation for module `$paramod$913793164bb5cb5821e69ced9b7f953b27ebd911\mac_unit'.
Parameter \DATA_WIDTH = 16
Parameter \ACC_WIDTH = 40
Found cached RTLIL representation for module `$paramod$913793164bb5cb5821e69ced9b7f953b27ebd911\mac_unit'.
Reprocessing module mac8 because instantiated module mac_unit has become available.
Generating RTLIL representation for module `\mac8'.
Parameter \ADDR_WIDTH = 23
Parameter \DATA_WIDTH = 8
Parameter \N_INPUTS = 32
Parameter \N_NEURONS = 1
Parameter \PARALLEL = 8
Parameter \N_TOTAL = 4096
16.7. Executing AST frontend in derive mode using pre-parsed AST for module `\spi_engine'.
Parameter \ADDR_WIDTH = 23
Parameter \DATA_WIDTH = 8
Parameter \N_INPUTS = 32
Parameter \N_NEURONS = 1
Parameter \PARALLEL = 8
Parameter \N_TOTAL = 4096
Generating RTLIL representation for module `$paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine'.
Parameter \ADDR_WIDTH = 23
Parameter \DATA_WIDTH = 8
Parameter \N_WIDTH = 1
Parameter \N_LAYERS = 4
16.8. Executing AST frontend in derive mode using pre-parsed AST for module `\layer_sequencer'.
Parameter \ADDR_WIDTH = 23
Parameter \DATA_WIDTH = 8
Parameter \N_WIDTH = 1
Parameter \N_LAYERS = 4
Generating RTLIL representation for module `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer'.
Parameter \ADDR_WIDTH = 23
Parameter \DATA_WIDTH = 8
Parameter \ACC_WIDTH = 32
Parameter \PARALLEL = 8
Parameter \MAX_CONN = 32
Parameter \N_TOTAL = 4096
16.9. Executing AST frontend in derive mode using pre-parsed AST for module `\graph_engine'.
Parameter \ADDR_WIDTH = 23
Parameter \DATA_WIDTH = 8
Parameter \ACC_WIDTH = 32
Parameter \PARALLEL = 8
Parameter \MAX_CONN = 32
Parameter \N_TOTAL = 4096
Generating RTLIL representation for module `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine'.
Parameter \ADDR_WIDTH = 23
Parameter \DATA_WIDTH = 8
Parameter \N_INPUTS = 32
Parameter \N_NEURONS = 1
Parameter \PARALLEL = 8
Parameter \ACC_WIDTH = 32
16.10. Executing AST frontend in derive mode using pre-parsed AST for module `\neuron_memory'.
Parameter \ADDR_WIDTH = 23
Parameter \DATA_WIDTH = 8
Parameter \N_INPUTS = 32
Parameter \N_NEURONS = 1
Parameter \PARALLEL = 8
Parameter \ACC_WIDTH = 32
Generating RTLIL representation for module `$paramod$79958c098f4e7efe85e0f2fccdc4f496fe8d2f0b\neuron_memory'.
Parameter \ADDR_WIDTH = 23
16.11. Executing AST frontend in derive mode using pre-parsed AST for module `\mem_arbiter'.
Parameter \ADDR_WIDTH = 23
Generating RTLIL representation for module `$paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010111'.
Parameter \ADDR_WIDTH = 23
Found cached RTLIL representation for module `$paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010111'.
Parameter \ADDR_WIDTH = 23
Parameter \DATA_WIDTH = 16
16.12. Executing AST frontend in derive mode using pre-parsed AST for module `\memory_interface'.
Parameter \ADDR_WIDTH = 23
Parameter \DATA_WIDTH = 16
Generating RTLIL representation for module `$paramod$b3f3d2413f22d50ebc275a55cbfefa4ff7d277a1\memory_interface'.
Parameter \ADDR_WIDTH = 23
Parameter \DATA_WIDTH = 16
Parameter \CLK_FREQ_MHZ = 80
16.13. Executing AST frontend in derive mode using pre-parsed AST for module `\psram_controller'.
Parameter \ADDR_WIDTH = 23
Parameter \DATA_WIDTH = 16
Parameter \CLK_FREQ_MHZ = 80
Generating RTLIL representation for module `$paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller'.
16.14. Analyzing design hierarchy..
Top module: \spi_neuron_top
Used module: \spi_slave
Used module: $paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine
Used module: $paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer
Used module: $paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine
Used module: \neuron_parallel
Used module: $paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8
Used module: \mac_unit
Used module: \act_buffer
Used module: $paramod$79958c098f4e7efe85e0f2fccdc4f496fe8d2f0b\neuron_memory
Used module: \int8_memory_access
Used module: $paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010111
Used module: $paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010111
Used module: $paramod$b3f3d2413f22d50ebc275a55cbfefa4ff7d277a1\memory_interface
Used module: $paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller
Parameter \DATA_WIDTH = 8
Parameter \ACC_WIDTH = 32
16.15. Executing AST frontend in derive mode using pre-parsed AST for module `\mac_unit'.
Parameter \DATA_WIDTH = 8
Parameter \ACC_WIDTH = 32
Generating RTLIL representation for module `$paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\mac_unit'.
Parameter \DATA_WIDTH = 8
Parameter \ACC_WIDTH = 32
Found cached RTLIL representation for module `$paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\mac_unit'.
Parameter \DATA_WIDTH = 8
Parameter \ACC_WIDTH = 32
Found cached RTLIL representation for module `$paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\mac_unit'.
Parameter \DATA_WIDTH = 8
Parameter \ACC_WIDTH = 32
Found cached RTLIL representation for module `$paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\mac_unit'.
Parameter \DATA_WIDTH = 8
Parameter \ACC_WIDTH = 32
Found cached RTLIL representation for module `$paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\mac_unit'.
Parameter \DATA_WIDTH = 8
Parameter \ACC_WIDTH = 32
Found cached RTLIL representation for module `$paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\mac_unit'.
Parameter \DATA_WIDTH = 8
Parameter \ACC_WIDTH = 32
Found cached RTLIL representation for module `$paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\mac_unit'.
Parameter \DATA_WIDTH = 8
Parameter \ACC_WIDTH = 32
Found cached RTLIL representation for module `$paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\mac_unit'.
Reprocessing module $paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8 because instantiated module $paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\mac_unit has become available.
Generating RTLIL representation for module `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8'.
Parameter \DATA_WIDTH = 8
Parameter \N_INPUTS = 32
Parameter \PARALLEL = 8
Parameter \ACC_WIDTH = 32
Found cached RTLIL representation for module `$paramod$18f95495176adabb8b1efa1a4c23d17992af7212\neuron_parallel'.
Parameter \N_TOTAL = 4096
Parameter \DATA_WIDTH = 8
Found cached RTLIL representation for module `$paramod$c614a16d6b975c0ec2885ffa17a962bce4ddbcec\act_buffer'.
Parameter \DATA_WIDTH = 8
Parameter \N_INPUTS = 32
Parameter \PARALLEL = 8
Parameter \ACC_WIDTH = 32
Found cached RTLIL representation for module `$paramod$18f95495176adabb8b1efa1a4c23d17992af7212\neuron_parallel'.
Parameter \ADDR_WIDTH = 23
Found cached RTLIL representation for module `$paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010111'.
16.16. Analyzing design hierarchy..
Top module: \spi_neuron_top
Used module: \spi_slave
Used module: $paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine
Used module: $paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer
Used module: $paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine
Used module: $paramod$18f95495176adabb8b1efa1a4c23d17992af7212\neuron_parallel
Used module: \mac8
Used module: \mac_unit
Used module: $paramod$c614a16d6b975c0ec2885ffa17a962bce4ddbcec\act_buffer
Used module: $paramod$79958c098f4e7efe85e0f2fccdc4f496fe8d2f0b\neuron_memory
Used module: $paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010111
Used module: $paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010111
Used module: $paramod$b3f3d2413f22d50ebc275a55cbfefa4ff7d277a1\memory_interface
Used module: $paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller
Parameter \DATA_WIDTH = 16
Parameter \ACC_WIDTH = 40
Found cached RTLIL representation for module `$paramod$913793164bb5cb5821e69ced9b7f953b27ebd911\mac_unit'.
Parameter \DATA_WIDTH = 16
Parameter \ACC_WIDTH = 40
Found cached RTLIL representation for module `$paramod$913793164bb5cb5821e69ced9b7f953b27ebd911\mac_unit'.
Parameter \DATA_WIDTH = 16
Parameter \ACC_WIDTH = 40
Found cached RTLIL representation for module `$paramod$913793164bb5cb5821e69ced9b7f953b27ebd911\mac_unit'.
Parameter \DATA_WIDTH = 16
Parameter \ACC_WIDTH = 40
Found cached RTLIL representation for module `$paramod$913793164bb5cb5821e69ced9b7f953b27ebd911\mac_unit'.
Parameter \DATA_WIDTH = 16
Parameter \ACC_WIDTH = 40
Found cached RTLIL representation for module `$paramod$913793164bb5cb5821e69ced9b7f953b27ebd911\mac_unit'.
Parameter \DATA_WIDTH = 16
Parameter \ACC_WIDTH = 40
Found cached RTLIL representation for module `$paramod$913793164bb5cb5821e69ced9b7f953b27ebd911\mac_unit'.
Parameter \DATA_WIDTH = 16
Parameter \ACC_WIDTH = 40
Found cached RTLIL representation for module `$paramod$913793164bb5cb5821e69ced9b7f953b27ebd911\mac_unit'.
Parameter \DATA_WIDTH = 16
Parameter \ACC_WIDTH = 40
Found cached RTLIL representation for module `$paramod$913793164bb5cb5821e69ced9b7f953b27ebd911\mac_unit'.
Parameter \DATA_WIDTH = 8
Parameter \ACC_WIDTH = 32
Parameter \PARALLEL = 8
Found cached RTLIL representation for module `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8'.
16.17. Analyzing design hierarchy..
Top module: \spi_neuron_top
Used module: \spi_slave
Used module: $paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine
Used module: $paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer
Used module: $paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine
Used module: $paramod$18f95495176adabb8b1efa1a4c23d17992af7212\neuron_parallel
Used module: $paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8
Used module: \mac_unit
Used module: $paramod$c614a16d6b975c0ec2885ffa17a962bce4ddbcec\act_buffer
Used module: $paramod$79958c098f4e7efe85e0f2fccdc4f496fe8d2f0b\neuron_memory
Used module: $paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010111
Used module: $paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010111
Used module: $paramod$b3f3d2413f22d50ebc275a55cbfefa4ff7d277a1\memory_interface
Used module: $paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller
Parameter \DATA_WIDTH = 8
Parameter \ACC_WIDTH = 32
Found cached RTLIL representation for module `$paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\mac_unit'.
Parameter \DATA_WIDTH = 8
Parameter \ACC_WIDTH = 32
Found cached RTLIL representation for module `$paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\mac_unit'.
Parameter \DATA_WIDTH = 8
Parameter \ACC_WIDTH = 32
Found cached RTLIL representation for module `$paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\mac_unit'.
Parameter \DATA_WIDTH = 8
Parameter \ACC_WIDTH = 32
Found cached RTLIL representation for module `$paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\mac_unit'.
Parameter \DATA_WIDTH = 8
Parameter \ACC_WIDTH = 32
Found cached RTLIL representation for module `$paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\mac_unit'.
Parameter \DATA_WIDTH = 8
Parameter \ACC_WIDTH = 32
Found cached RTLIL representation for module `$paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\mac_unit'.
Parameter \DATA_WIDTH = 8
Parameter \ACC_WIDTH = 32
Found cached RTLIL representation for module `$paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\mac_unit'.
Parameter \DATA_WIDTH = 8
Parameter \ACC_WIDTH = 32
Found cached RTLIL representation for module `$paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\mac_unit'.
16.18. Analyzing design hierarchy..
Top module: \spi_neuron_top
Used module: \spi_slave
Used module: $paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine
Used module: $paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer
Used module: $paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine
Used module: $paramod$18f95495176adabb8b1efa1a4c23d17992af7212\neuron_parallel
Used module: $paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8
Used module: $paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\mac_unit
Used module: $paramod$c614a16d6b975c0ec2885ffa17a962bce4ddbcec\act_buffer
Used module: $paramod$79958c098f4e7efe85e0f2fccdc4f496fe8d2f0b\neuron_memory
Used module: $paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010111
Used module: $paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010111
Used module: $paramod$b3f3d2413f22d50ebc275a55cbfefa4ff7d277a1\memory_interface
Used module: $paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller
16.19. Analyzing design hierarchy..
Top module: \spi_neuron_top
Used module: \spi_slave
Used module: $paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine
Used module: $paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer
Used module: $paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine
Used module: $paramod$18f95495176adabb8b1efa1a4c23d17992af7212\neuron_parallel
Used module: $paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8
Used module: $paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\mac_unit
Used module: $paramod$c614a16d6b975c0ec2885ffa17a962bce4ddbcec\act_buffer
Used module: $paramod$79958c098f4e7efe85e0f2fccdc4f496fe8d2f0b\neuron_memory
Used module: $paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010111
Used module: $paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010111
Used module: $paramod$b3f3d2413f22d50ebc275a55cbfefa4ff7d277a1\memory_interface
Used module: $paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller
Removing unused module `\mac8'.
Removing unused module `\mac_unit'.
Removing unused module `$paramod$913793164bb5cb5821e69ced9b7f953b27ebd911\mac_unit'.
Removing unused module `\neuron_parallel'.
Removing unused module `\psram_controller'.
Removing unused module `\memory_interface'.
Removing unused module `\int8_memory_access'.
Removing unused module `\neuron_memory'.
Removing unused module `\mem_arbiter'.
Removing unused module `\graph_engine'.
Removing unused module `\act_buffer'.
Removing unused module `\layer_sequencer'.
Removing unused module `\spi_engine'.
Removed 13 unused modules.
17. Executing SYNTH_LATTICE pass.
17.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v' to AST representation.
Generating RTLIL representation for module `\LUT4'.
Generating RTLIL representation for module `\$__ABC9_LUT5'.
Generating RTLIL representation for module `\$__ABC9_LUT6'.
Generating RTLIL representation for module `\$__ABC9_LUT7'.
Generating RTLIL representation for module `\L6MUX21'.
Generating RTLIL representation for module `\TRELLIS_RAM16X2'.
Generating RTLIL representation for module `\PFUMX'.
Generating RTLIL representation for module `\TRELLIS_DPR16X4'.
Generating RTLIL representation for module `\DPR16X4C'.
Generating RTLIL representation for module `\LUT2'.
Generating RTLIL representation for module `\TRELLIS_FF'.
Generating RTLIL representation for module `\TRELLIS_IO'.
Generating RTLIL representation for module `\INV'.
Generating RTLIL representation for module `\TRELLIS_COMB'.
Generating RTLIL representation for module `\VLO'.
Generating RTLIL representation for module `\VHI'.
Generating RTLIL representation for module `\FD1P3AX'.
Generating RTLIL representation for module `\FD1P3AY'.
Generating RTLIL representation for module `\FD1P3BX'.
Generating RTLIL representation for module `\FD1P3DX'.
Generating RTLIL representation for module `\FD1P3IX'.
Generating RTLIL representation for module `\FD1P3JX'.
Generating RTLIL representation for module `\FD1S3AX'.
Generating RTLIL representation for module `\FD1S3AY'.
Generating RTLIL representation for module `\FD1S3BX'.
Generating RTLIL representation for module `\FD1S3DX'.
Generating RTLIL representation for module `\FD1S3IX'.
Generating RTLIL representation for module `\FD1S3JX'.
Generating RTLIL representation for module `\IFS1P3BX'.
Generating RTLIL representation for module `\IFS1P3DX'.
Generating RTLIL representation for module `\IFS1P3IX'.
Generating RTLIL representation for module `\IFS1P3JX'.
Generating RTLIL representation for module `\OFS1P3BX'.
Generating RTLIL representation for module `\OFS1P3DX'.
Generating RTLIL representation for module `\OFS1P3IX'.
Generating RTLIL representation for module `\OFS1P3JX'.
Generating RTLIL representation for module `\IB'.
Generating RTLIL representation for module `\IBPU'.
Generating RTLIL representation for module `\IBPD'.
Generating RTLIL representation for module `\OB'.
Generating RTLIL representation for module `\OBZ'.
Generating RTLIL representation for module `\OBZPU'.
Generating RTLIL representation for module `\OBZPD'.
Generating RTLIL representation for module `\OBCO'.
Generating RTLIL representation for module `\BB'.
Generating RTLIL representation for module `\BBPU'.
Generating RTLIL representation for module `\BBPD'.
Generating RTLIL representation for module `\ILVDS'.
Generating RTLIL representation for module `\OLVDS'.
Generating RTLIL representation for module `\CCU2C'.
Generating RTLIL representation for module `\DP16KD'.
Replacing existing blackbox module `\FD1P3AX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:2.1-2.261.
Generating RTLIL representation for module `\FD1P3AX'.
Replacing existing blackbox module `\FD1P3AY' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:3.1-3.261.
Generating RTLIL representation for module `\FD1P3AY'.
Replacing existing blackbox module `\FD1P3BX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:4.1-4.261.
Generating RTLIL representation for module `\FD1P3BX'.
Replacing existing blackbox module `\FD1P3DX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:5.1-5.261.
Generating RTLIL representation for module `\FD1P3DX'.
Replacing existing blackbox module `\FD1P3IX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:6.1-6.261.
Generating RTLIL representation for module `\FD1P3IX'.
Replacing existing blackbox module `\FD1P3JX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:7.1-7.261.
Generating RTLIL representation for module `\FD1P3JX'.
Replacing existing blackbox module `\FD1S3AX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:8.1-8.261.
Generating RTLIL representation for module `\FD1S3AX'.
Replacing existing blackbox module `\FD1S3AY' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:9.1-9.261.
Generating RTLIL representation for module `\FD1S3AY'.
Replacing existing blackbox module `\FD1S3BX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:10.1-10.261.
Generating RTLIL representation for module `\FD1S3BX'.
Replacing existing blackbox module `\FD1S3DX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:11.1-11.261.
Generating RTLIL representation for module `\FD1S3DX'.
Replacing existing blackbox module `\FD1S3IX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:12.1-12.261.
Generating RTLIL representation for module `\FD1S3IX'.
Replacing existing blackbox module `\FD1S3JX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:13.1-13.261.
Generating RTLIL representation for module `\FD1S3JX'.
Replacing existing blackbox module `\IFS1P3BX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:26.1-26.301.
Generating RTLIL representation for module `\IFS1P3BX'.
Replacing existing blackbox module `\IFS1P3DX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:27.1-27.301.
Generating RTLIL representation for module `\IFS1P3DX'.
Replacing existing blackbox module `\IFS1P3IX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:28.1-28.301.
Generating RTLIL representation for module `\IFS1P3IX'.
Replacing existing blackbox module `\IFS1P3JX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:29.1-29.301.
Generating RTLIL representation for module `\IFS1P3JX'.
Replacing existing blackbox module `\OFS1P3BX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:31.1-31.302.
Generating RTLIL representation for module `\OFS1P3BX'.
Replacing existing blackbox module `\OFS1P3DX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:32.1-32.302.
Generating RTLIL representation for module `\OFS1P3DX'.
Replacing existing blackbox module `\OFS1P3IX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:33.1-33.302.
Generating RTLIL representation for module `\OFS1P3IX'.
Replacing existing blackbox module `\OFS1P3JX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:34.1-34.302.
Generating RTLIL representation for module `\OFS1P3JX'.
Replacing existing blackbox module `\IB' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:2.1-2.157.
Generating RTLIL representation for module `\IB'.
Replacing existing blackbox module `\IBPU' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:3.1-3.157.
Generating RTLIL representation for module `\IBPU'.
Replacing existing blackbox module `\IBPD' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:4.1-4.157.
Generating RTLIL representation for module `\IBPD'.
Replacing existing blackbox module `\OB' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:5.1-5.157.
Generating RTLIL representation for module `\OB'.
Replacing existing blackbox module `\OBZ' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:6.1-6.164.
Generating RTLIL representation for module `\OBZ'.
Replacing existing blackbox module `\OBZPU' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:7.1-7.164.
Generating RTLIL representation for module `\OBZPU'.
Replacing existing blackbox module `\OBZPD' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:8.1-8.164.
Generating RTLIL representation for module `\OBZPD'.
Replacing existing blackbox module `\OBCO' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:9.1-9.90.
Generating RTLIL representation for module `\OBCO'.
Replacing existing blackbox module `\BB' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:10.1-10.179.
Generating RTLIL representation for module `\BB'.
Replacing existing blackbox module `\BBPU' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:11.1-11.179.
Generating RTLIL representation for module `\BBPU'.
Replacing existing blackbox module `\BBPD' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:12.1-12.179.
Generating RTLIL representation for module `\BBPD'.
Replacing existing blackbox module `\ILVDS' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:13.1-13.139.
Generating RTLIL representation for module `\ILVDS'.
Replacing existing blackbox module `\OLVDS' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:14.1-14.146.
Generating RTLIL representation for module `\OLVDS'.
Successfully finished Verilog frontend.
17.2. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v' to AST representation.
Generating RTLIL representation for module `\GSR'.
Generating RTLIL representation for module `\PUR'.
Generating RTLIL representation for module `\SGSR'.
Generating RTLIL representation for module `\PDPW16KD'.
Generating RTLIL representation for module `\MULT18X18D'.
Generating RTLIL representation for module `\ALU54B'.
Generating RTLIL representation for module `\CLKDIVF'.
Generating RTLIL representation for module `\PCSCLKDIV'.
Generating RTLIL representation for module `\DCSC'.
Generating RTLIL representation for module `\DCCA'.
Generating RTLIL representation for module `\ECLKSYNCB'.
Generating RTLIL representation for module `\ECLKBRIDGECS'.
Generating RTLIL representation for module `\DELAYF'.
Generating RTLIL representation for module `\DELAYG'.
Generating RTLIL representation for module `\USRMCLK'.
Generating RTLIL representation for module `\DQSBUFM'.
Generating RTLIL representation for module `\DDRDLLA'.
Generating RTLIL representation for module `\DLLDELD'.
Generating RTLIL representation for module `\IDDRX1F'.
Generating RTLIL representation for module `\IDDRX2F'.
Generating RTLIL representation for module `\IDDR71B'.
Generating RTLIL representation for module `\IDDRX2DQA'.
Generating RTLIL representation for module `\ODDRX1F'.
Generating RTLIL representation for module `\ODDRX2F'.
Generating RTLIL representation for module `\ODDR71B'.
Generating RTLIL representation for module `\OSHX2A'.
Generating RTLIL representation for module `\TSHX2DQA'.
Generating RTLIL representation for module `\TSHX2DQSA'.
Generating RTLIL representation for module `\ODDRX2DQA'.
Generating RTLIL representation for module `\ODDRX2DQSB'.
Generating RTLIL representation for module `\EHXPLLL'.
Generating RTLIL representation for module `\DTR'.
Generating RTLIL representation for module `\OSCG'.
Generating RTLIL representation for module `\EXTREFB'.
Generating RTLIL representation for module `\JTAGG'.
Generating RTLIL representation for module `\DCUA'.
Successfully finished Verilog frontend.
17.3. Executing HIERARCHY pass (managing design hierarchy).
17.3.1. Analyzing design hierarchy..
Top module: \spi_neuron_top
Used module: \spi_slave
Used module: $paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine
Used module: $paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer
Used module: $paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine
Used module: $paramod$18f95495176adabb8b1efa1a4c23d17992af7212\neuron_parallel
Used module: $paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8
Used module: $paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\mac_unit
Used module: $paramod$c614a16d6b975c0ec2885ffa17a962bce4ddbcec\act_buffer
Used module: $paramod$79958c098f4e7efe85e0f2fccdc4f496fe8d2f0b\neuron_memory
Used module: $paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010111
Used module: $paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010111
Used module: $paramod$b3f3d2413f22d50ebc275a55cbfefa4ff7d277a1\memory_interface
Used module: $paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller
17.3.2. Analyzing design hierarchy..
Top module: \spi_neuron_top
Used module: \spi_slave
Used module: $paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine
Used module: $paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer
Used module: $paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine
Used module: $paramod$18f95495176adabb8b1efa1a4c23d17992af7212\neuron_parallel
Used module: $paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8
Used module: $paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\mac_unit
Used module: $paramod$c614a16d6b975c0ec2885ffa17a962bce4ddbcec\act_buffer
Used module: $paramod$79958c098f4e7efe85e0f2fccdc4f496fe8d2f0b\neuron_memory
Used module: $paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010111
Used module: $paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010111
Used module: $paramod$b3f3d2413f22d50ebc275a55cbfefa4ff7d277a1\memory_interface
Used module: $paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller
Removed 0 unused modules.
17.4. Executing PROC pass (convert processes to netlists).
17.4.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.
17.4.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 2 switch rules as full_case in process $proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/memory_interface.v:33$1239 in module $paramod$b3f3d2413f22d50ebc275a55cbfefa4ff7d277a1\memory_interface.
Removed 1 dead cases from process $proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mem_arbiter.v:90$1238 in module $paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010111.
Marked 4 switch rules as full_case in process $proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mem_arbiter.v:90$1238 in module $paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010111.
Marked 8 switch rules as full_case in process $proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:283$1118 in module $paramod$79958c098f4e7efe85e0f2fccdc4f496fe8d2f0b\neuron_memory.
Marked 11 switch rules as full_case in process $proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$869 in module $paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.
Marked 5 switch rules as full_case in process $proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:137$780 in module $paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.
Marked 13 switch rules as full_case in process $proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:315$760 in module $paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine.
Marked 4 switch rules as full_case in process $proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:263$755 in module $paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine.
Marked 3 switch rules as full_case in process $proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:242$753 in module $paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine.
Marked 6 switch rules as full_case in process $proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/psram_controller.v:99$1242 in module $paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller.
Marked 4 switch rules as full_case in process $proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/int8_memory_access.v:55$676 in module $paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010111.
Marked 1 switch rules as full_case in process $proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/act_buffer.v:55$644 in module $paramod$c614a16d6b975c0ec2885ffa17a962bce4ddbcec\act_buffer.
Marked 8 switch rules as full_case in process $proc$/tmp/before_rewrite/neuron_parallel.v:130$633 in module $paramod$18f95495176adabb8b1efa1a4c23d17992af7212\neuron_parallel.
Marked 6 switch rules as full_case in process $proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_slave.v:119$12 in module spi_slave.
Marked 1 switch rules as full_case in process $proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_slave.v:93$2 in module spi_slave.
Marked 1 switch rules as full_case in process $proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_slave.v:71$1 in module spi_slave.
Removed a total of 1 dead cases.
17.4.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 40 redundant assignments.
Promoted 110 assignments to connections.
17.4.4. Executing PROC_INIT pass (extract init attributes).
17.4.5. Executing PROC_ARST pass (detect async resets in processes).
17.4.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 1 switch.
<suppressed ~121 debug messages>
17.4.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$b3f3d2413f22d50ebc275a55cbfefa4ff7d277a1\memory_interface.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/memory_interface.v:33$1239'.
1/9: $0\mem_req[0:0]
2/9: $0\ready[0:0]
3/9: $0\mem_ub_n[0:0]
4/9: $0\mem_lb_n[0:0]
5/9: $0\rdata[15:0]
6/9: $0\mem_wdata[15:0]
7/9: $0\mem_addr[22:0]
8/9: $0\mem_wr[0:0]
9/9: $0\state[1:0]
Creating decoders for process `$paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010111.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mem_arbiter.v:90$1238'.
1/11: $0\c_ready[0:0]
2/11: $0\b_ready[0:0]
3/11: $0\a_ready[0:0]
4/11: $0\m_req[0:0]
5/11: $0\owner[1:0]
6/11: $0\m_wdata[7:0]
7/11: $0\m_addr[22:0]
8/11: $0\m_wr[0:0]
9/11: $0\c_rdata[7:0]
10/11: $0\b_rdata[7:0]
11/11: $0\a_rdata[7:0]
Creating decoders for process `$paramod$79958c098f4e7efe85e0f2fccdc4f496fe8d2f0b\neuron_memory.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:283$1118'.
1/42: $3$memwr$\y_reg$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:449$1116_EN[7:0]$1166
2/42: $3$memwr$\y_reg$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:449$1116_DATA[7:0]$1165
3/42: $3$memwr$\y_reg$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:449$1116_ADDR[0:0]$1164
4/42: $3$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:390$1115_EN[7:0]$1158
5/42: $3$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:390$1115_DATA[7:0]$1157
6/42: $3$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:390$1115_ADDR[5:0]$1156
7/42: $3$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:357$1114_EN[7:0]$1150
8/42: $3$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:357$1114_DATA[7:0]$1149
9/42: $3$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:357$1114_ADDR[5:0]$1148
10/42: $2$memwr$\y_reg$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:449$1116_EN[7:0]$1147
11/42: $2$memwr$\y_reg$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:449$1116_DATA[7:0]$1146
12/42: $2$memwr$\y_reg$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:449$1116_ADDR[0:0]$1145
13/42: $2$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:390$1115_EN[7:0]$1144
14/42: $2$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:390$1115_DATA[7:0]$1143
15/42: $2$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:390$1115_ADDR[5:0]$1142
16/42: $2$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:357$1114_EN[7:0]$1141
17/42: $2$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:357$1114_DATA[7:0]$1140
18/42: $2$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:357$1114_ADDR[5:0]$1139
19/42: $0\done[0:0]
20/42: $1\rst_i[31:0]
21/42: $1$memwr$\y_reg$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:304$1113_EN[7:0]$1129
22/42: $0\neuron_start[0:0]
23/42: $0\access_req[0:0]
24/42: $1$memwr$\y_reg$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:449$1116_EN[7:0]$1138
25/42: $1$memwr$\y_reg$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:449$1116_DATA[7:0]$1137
26/42: $1$memwr$\y_reg$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:449$1116_ADDR[0:0]$1136
27/42: $1$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:390$1115_EN[7:0]$1135
28/42: $1$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:390$1115_DATA[7:0]$1134
29/42: $1$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:390$1115_ADDR[5:0]$1133
30/42: $1$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:357$1114_EN[7:0]$1132
31/42: $1$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:357$1114_DATA[7:0]$1131
32/42: $1$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:357$1114_ADDR[5:0]$1130
33/42: $0\access_wdata[7:0]
34/42: $0\access_addr[22:0]
35/42: $0\access_wr[0:0]
36/42: $0\bias_group_addr[22:0]
37/42: $0\w_group_base[22:0]
38/42: $0\neuron_index[0:0]
39/42: $0\index[5:0]
40/42: $0\bias_reg[7:0]
41/42: $0\busy[0:0]
42/42: $0\state[3:0]
Creating decoders for process `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$869'.
1/108: $0\src_id_acc[15:0] [15:8]
2/108: $0\src_id_acc[15:0] [7:0]
3/108: $0\out_id_acc[15:0] [7:0]
4/108: $0\n_conn_acc[15:0] [7:0]
5/108: $0\conn_ptr_acc[23:0] [7:0]
6/108: $0\conn_ptr_acc[23:0] [23:16]
7/108: $2$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:496$865_DATA[7:0]$1014
8/108: $2$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:496$865_ADDR[5:0]$1013
9/108: $2$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:495$864_EN[7:0]$1012
10/108: $2$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:495$864_DATA[7:0]$1011
11/108: $2$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:495$864_ADDR[5:0]$1010
12/108: $1\ri[31:0]
13/108: $1$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$863_EN[7:0]$1003
14/108: $1$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$862_EN[7:0]$1002
15/108: $1$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$861_EN[7:0]$1001
16/108: $1$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$860_EN[7:0]$1000
17/108: $1$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$859_EN[7:0]$999
18/108: $1$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$858_EN[7:0]$998
19/108: $1$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$857_EN[7:0]$997
20/108: $1$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$856_EN[7:0]$996
21/108: $1$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$855_EN[7:0]$995
22/108: $1$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$854_EN[7:0]$994
23/108: $1$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$853_EN[7:0]$993
24/108: $1$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$852_EN[7:0]$992
25/108: $1$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$851_EN[7:0]$991
26/108: $1$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$850_EN[7:0]$990
27/108: $1$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$849_EN[7:0]$989
28/108: $1$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$848_EN[7:0]$988
29/108: $1$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$847_EN[7:0]$987
30/108: $1$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$846_EN[7:0]$986
31/108: $1$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$845_EN[7:0]$985
32/108: $1$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$844_EN[7:0]$984
33/108: $1$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$843_EN[7:0]$983
34/108: $1$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$842_EN[7:0]$982
35/108: $1$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$841_EN[7:0]$981
36/108: $1$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$840_EN[7:0]$980
37/108: $1$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$839_EN[7:0]$979
38/108: $1$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$838_EN[7:0]$978
39/108: $1$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$837_EN[7:0]$977
40/108: $1$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$836_EN[7:0]$976
41/108: $1$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$835_EN[7:0]$975
42/108: $1$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$834_EN[7:0]$974
43/108: $1$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$833_EN[7:0]$973
44/108: $1$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$832_EN[7:0]$972
45/108: $1$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$831_EN[7:0]$971
46/108: $1$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$830_EN[7:0]$970
47/108: $1$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$829_EN[7:0]$969
48/108: $1$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$828_EN[7:0]$968
49/108: $1$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$827_EN[7:0]$967
50/108: $1$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$826_EN[7:0]$966
51/108: $1$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$825_EN[7:0]$965
52/108: $1$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$824_EN[7:0]$964
53/108: $1$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$823_EN[7:0]$963
54/108: $1$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$822_EN[7:0]$962
55/108: $1$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$821_EN[7:0]$961
56/108: $1$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$820_EN[7:0]$960
57/108: $1$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$819_EN[7:0]$959
58/108: $1$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$818_EN[7:0]$958
59/108: $1$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$817_EN[7:0]$957
60/108: $1$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$816_EN[7:0]$956
61/108: $1$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$815_EN[7:0]$955
62/108: $1$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$814_EN[7:0]$954
63/108: $1$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$813_EN[7:0]$953
64/108: $1$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$812_EN[7:0]$952
65/108: $1$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$811_EN[7:0]$951
66/108: $1$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$810_EN[7:0]$950
67/108: $1$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$809_EN[7:0]$949
68/108: $1$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$808_EN[7:0]$948
69/108: $1$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$807_EN[7:0]$947
70/108: $1$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$806_EN[7:0]$946
71/108: $1$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$805_EN[7:0]$945
72/108: $1$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$804_EN[7:0]$944
73/108: $1$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$803_EN[7:0]$943
74/108: $1$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$802_EN[7:0]$942
75/108: $1$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$801_EN[7:0]$941
76/108: $1$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$800_EN[7:0]$940
77/108: $0\ram_req[0:0]
78/108: $0\neuron_start[0:0]
79/108: $0\act_wr_en[0:0]
80/108: $0\done[0:0]
81/108: $1$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:496$865_EN[7:0]$1009
82/108: $1$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:496$865_DATA[7:0]$1008
83/108: $1$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:496$865_ADDR[5:0]$1007
84/108: $1$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:495$864_EN[7:0]$1006
85/108: $1$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:495$864_DATA[7:0]$1005
86/108: $1$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:495$864_ADDR[5:0]$1004
87/108: $0\n_conn_padded_reg[15:0]
88/108: $0\activation_reg[1:0]
89/108: $0\bias_reg[7:0]
90/108: $0\act_wr_data[7:0]
91/108: $0\act_wr_addr[11:0]
92/108: $0\weight_acc[7:0]
93/108: $0\out_id_acc[15:0] [15:8]
94/108: $0\edge_byte_idx[1:0]
95/108: $0\conn_i[5:0]
96/108: $0\n_conn_acc[15:0] [15:8]
97/108: $0\conn_ptr_acc[23:0] [15:8]
98/108: $2$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:496$865_EN[7:0]$1015
99/108: $0\desc_addr[22:0]
100/108: $0\neuron_idx[15:0]
101/108: $0\in_idx[15:0]
102/108: $0\err[0:0]
103/108: $0\busy[0:0]
104/108: $0\desc_byte_idx[3:0]
105/108: $0\state[3:0]
106/108: $0\ram_wdata[7:0]
107/108: $0\ram_addr[22:0]
108/108: $0\ram_wr[0:0]
Creating decoders for process `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:137$780'.
1/32: $0\n_neurons_acc[15:0] [15:8]
2/32: $0\n_neurons_acc[15:0] [7:0]
3/32: $0\n_inputs_acc[15:0] [7:0]
4/32: $0\bias_addr_acc[23:0] [7:0]
5/32: $0\bias_addr_acc[23:0] [23:16]
6/32: $0\w_base_acc[23:0] [7:0]
7/32: $0\w_base_acc[23:0] [23:16]
8/32: $0\ram_req[0:0]
9/32: $0\nm_start[0:0]
10/32: $0\copy_idx[0:0]
11/32: $0\write_sel[0:0]
12/32: $0\cur_sel[0:0]
13/32: $0\n_inputs_acc[15:0] [15:8]
14/32: $0\bias_addr_acc[23:0] [15:8]
15/32: $0\activation_acc[7:0]
16/32: $0\w_base_acc[23:0] [15:8]
17/32: $0\seq_done[0:0]
18/32: $0\desc_byte_idx[3:0]
19/32: $0\desc_table_addr[22:0]
20/32: $0\num_layers_reg[7:0]
21/32: $0\layer_idx[7:0]
22/32: $0\nm_n_neurons[15:0]
23/32: $0\nm_n_inputs[15:0]
24/32: $0\nm_activation[1:0]
25/32: $0\nm_bias_addr[22:0]
26/32: $0\nm_w_base[22:0]
27/32: $0\nm_x_base[22:0]
28/32: $0\state[3:0]
29/32: $0\seq_busy[0:0]
30/32: $0\ram_wdata[7:0]
31/32: $0\ram_addr[22:0]
32/32: $0\ram_wr[0:0]
Creating decoders for process `$paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:315$760'.
1/36: $0\len_acc[15:0] [15:8]
2/36: $0\len_acc[15:0] [7:0]
3/36: $0\nm_soft_rst[0:0]
4/36: $0\nm_start[0:0]
5/36: $0\ram_req[0:0]
6/36: $0\status_snapshot[7:0]
7/36: $0\graph_mode[0:0]
8/36: $0\net_mode[0:0]
9/36: $0\resp_len[3:0]
10/36: $0\resp_index[3:0]
11/36: $0\cur_read_byte[7:0]
12/36: $0\pending_wdata[7:0]
13/36: $0\pending_write[0:0]
14/36: $0\cur_addr[22:0]
15/36: $0\len_remaining[15:0]
16/36: $0\run_start[0:0]
17/36: $0\addr_acc[23:0]
18/36: $0\byte_pos[1:0]
19/36: $0\opcode[7:0]
20/36: $0\state[3:0]
21/36: $0\n_out[15:0]
22/36: $0\num_neurons_graph[15:0]
23/36: $0\net_type[7:0]
24/36: $0\run_num_layers[7:0]
25/36: $0\buf_b_base[22:0]
26/36: $0\buf_a_base[22:0]
27/36: $0\table_base[22:0]
28/36: $0\n_neurons_real[15:0]
29/36: $0\n_inputs_real[15:0]
30/36: $0\activation[1:0]
31/36: $0\bias_addr[22:0]
32/36: $0\w_base[22:0]
33/36: $0\x_base[22:0]
34/36: $0\ram_wdata[7:0]
35/36: $0\ram_addr[22:0]
36/36: $0\ram_wr[0:0]
Creating decoders for process `$paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:263$755'.
1/4: $4\tx_byte_comb[7:0]
2/4: $3\tx_byte_comb[7:0]
3/4: $2\tx_byte_comb[7:0]
4/4: $1\tx_byte_comb[7:0]
Creating decoders for process `$paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:242$753'.
1/1: $0\status_done_sticky[0:0]
Creating decoders for process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:100$1312'.
Creating decoders for process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:100$1310'.
Creating decoders for process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:100$1308'.
Creating decoders for process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:100$1306'.
Creating decoders for process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:100$1304'.
Creating decoders for process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:100$1302'.
Creating decoders for process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:100$1300'.
Creating decoders for process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:81$1299'.
Creating decoders for process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:81$1298'.
Creating decoders for process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:81$1297'.
Creating decoders for process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:81$1296'.
Creating decoders for process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:81$1295'.
Creating decoders for process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:81$1294'.
Creating decoders for process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:81$1293'.
Creating decoders for process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:81$1292'.
Creating decoders for process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:40$1291'.
Creating decoders for process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:40$1290'.
Creating decoders for process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:40$1289'.
Creating decoders for process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:40$1288'.
Creating decoders for process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:40$1287'.
Creating decoders for process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:40$1286'.
Creating decoders for process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:40$1285'.
Creating decoders for process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:40$1284'.
Creating decoders for process `$paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/psram_controller.v:99$1242'.
1/18: $0\dq_oe[0:0]
2/18: $0\psram_zz_n[0:0]
3/18: $0\psram_ub_n[0:0]
4/18: $0\psram_lb_n[0:0]
5/18: $0\psram_we_n[0:0]
6/18: $0\psram_oe_n[0:0]
7/18: $0\psram_ce_n[0:0]
8/18: $0\mem_ready[0:0]
9/18: $0\dq_out[15:0]
10/18: $0\ub_reg[0:0]
11/18: $0\lb_reg[0:0]
12/18: $0\wr_reg[0:0]
13/18: $0\wdata_reg[15:0]
14/18: $0\address_reg[22:0]
15/18: $0\counter[13:0]
16/18: $0\psram_a[22:0]
17/18: $0\mem_rdata[15:0]
18/18: $0\state[2:0]
Creating decoders for process `$paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010111.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/int8_memory_access.v:55$676'.
1/10: $0\mem_req[0:0]
2/10: $0\ready[0:0]
3/10: $0\addr_reg[22:0]
4/10: $0\mem_ub_n[0:0]
5/10: $0\mem_lb_n[0:0]
6/10: $0\rdata[7:0]
7/10: $0\mem_wdata[15:0]
8/10: $0\mem_addr[22:0]
9/10: $0\mem_wr[0:0]
10/10: $0\state[1:0]
Creating decoders for process `$paramod$c614a16d6b975c0ec2885ffa17a962bce4ddbcec\act_buffer.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/act_buffer.v:60$651'.
Creating decoders for process `$paramod$c614a16d6b975c0ec2885ffa17a962bce4ddbcec\act_buffer.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/act_buffer.v:55$644'.
1/3: $1$memwr$\mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/act_buffer.v:57$643_EN[7:0]$650
2/3: $1$memwr$\mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/act_buffer.v:57$643_DATA[7:0]$649
3/3: $1$memwr$\mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/act_buffer.v:57$643_ADDR[11:0]$648
Creating decoders for process `$paramod$18f95495176adabb8b1efa1a4c23d17992af7212\neuron_parallel.$proc$/tmp/before_rewrite/neuron_parallel.v:130$633'.
1/5: $0\done[0:0]
2/5: $0\acc[31:0]
3/5: $0\group_index[1:0]
4/5: $0\busy[0:0]
5/5: $0\y[7:0]
Creating decoders for process `\spi_slave.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_slave.v:119$12'.
1/9: $0\cs_end[0:0]
2/9: $0\cs_start[0:0]
3/9: $0\tx_byte_req[0:0]
4/9: $0\rx_valid[0:0]
5/9: $0\tx_shift[7:0]
6/9: $0\rx_shift[7:0]
7/9: $0\bit_count[2:0]
8/9: $0\rx_byte[7:0]
9/9: $0\miso[0:0]
Creating decoders for process `\spi_slave.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_slave.v:93$2'.
1/2: $0\cs_n_prev[0:0]
2/2: $0\sclk_prev[0:0]
Creating decoders for process `\spi_slave.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_slave.v:71$1'.
1/3: $0\cs_n_sync[2:0]
2/3: $0\mosi_sync[2:0]
3/3: $0\sclk_sync[2:0]
17.4.8. Executing PROC_DLATCH pass (convert process syncs to latches).
No latch inferred for signal `$paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine.\tx_byte_comb' from process `$paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:263$755'.
No latch inferred for signal `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.\tree[24]' from process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:100$1312'.
No latch inferred for signal `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.\tree[17]' from process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:100$1310'.
No latch inferred for signal `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.\tree[16]' from process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:100$1308'.
No latch inferred for signal `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.\tree[11]' from process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:100$1306'.
No latch inferred for signal `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.\tree[10]' from process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:100$1304'.
No latch inferred for signal `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.\tree[9]' from process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:100$1302'.
No latch inferred for signal `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.\tree[8]' from process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:100$1300'.
No latch inferred for signal `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.\tree[7]' from process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:81$1299'.
No latch inferred for signal `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.\tree[6]' from process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:81$1298'.
No latch inferred for signal `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.\tree[5]' from process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:81$1297'.
No latch inferred for signal `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.\tree[4]' from process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:81$1296'.
No latch inferred for signal `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.\tree[3]' from process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:81$1295'.
No latch inferred for signal `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.\tree[2]' from process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:81$1294'.
No latch inferred for signal `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.\tree[1]' from process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:81$1293'.
No latch inferred for signal `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.\tree[0]' from process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:81$1292'.
No latch inferred for signal `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.\products[7]' from process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:40$1291'.
No latch inferred for signal `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.\products[6]' from process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:40$1290'.
No latch inferred for signal `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.\products[5]' from process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:40$1289'.
No latch inferred for signal `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.\products[4]' from process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:40$1288'.
No latch inferred for signal `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.\products[3]' from process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:40$1287'.
No latch inferred for signal `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.\products[2]' from process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:40$1286'.
No latch inferred for signal `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.\products[1]' from process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:40$1285'.
No latch inferred for signal `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.\products[0]' from process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:40$1284'.
17.4.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$b3f3d2413f22d50ebc275a55cbfefa4ff7d277a1\memory_interface.\state' using process `$paramod$b3f3d2413f22d50ebc275a55cbfefa4ff7d277a1\memory_interface.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/memory_interface.v:33$1239'.
created $dff cell `$procdff$5251' with positive edge clock.
Creating register for signal `$paramod$b3f3d2413f22d50ebc275a55cbfefa4ff7d277a1\memory_interface.\mem_req' using process `$paramod$b3f3d2413f22d50ebc275a55cbfefa4ff7d277a1\memory_interface.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/memory_interface.v:33$1239'.
created $dff cell `$procdff$5252' with positive edge clock.
Creating register for signal `$paramod$b3f3d2413f22d50ebc275a55cbfefa4ff7d277a1\memory_interface.\mem_wr' using process `$paramod$b3f3d2413f22d50ebc275a55cbfefa4ff7d277a1\memory_interface.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/memory_interface.v:33$1239'.
created $dff cell `$procdff$5253' with positive edge clock.
Creating register for signal `$paramod$b3f3d2413f22d50ebc275a55cbfefa4ff7d277a1\memory_interface.\mem_addr' using process `$paramod$b3f3d2413f22d50ebc275a55cbfefa4ff7d277a1\memory_interface.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/memory_interface.v:33$1239'.
created $dff cell `$procdff$5254' with positive edge clock.
Creating register for signal `$paramod$b3f3d2413f22d50ebc275a55cbfefa4ff7d277a1\memory_interface.\mem_wdata' using process `$paramod$b3f3d2413f22d50ebc275a55cbfefa4ff7d277a1\memory_interface.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/memory_interface.v:33$1239'.
created $dff cell `$procdff$5255' with positive edge clock.
Creating register for signal `$paramod$b3f3d2413f22d50ebc275a55cbfefa4ff7d277a1\memory_interface.\rdata' using process `$paramod$b3f3d2413f22d50ebc275a55cbfefa4ff7d277a1\memory_interface.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/memory_interface.v:33$1239'.
created $dff cell `$procdff$5256' with positive edge clock.
Creating register for signal `$paramod$b3f3d2413f22d50ebc275a55cbfefa4ff7d277a1\memory_interface.\ready' using process `$paramod$b3f3d2413f22d50ebc275a55cbfefa4ff7d277a1\memory_interface.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/memory_interface.v:33$1239'.
created $dff cell `$procdff$5257' with positive edge clock.
Creating register for signal `$paramod$b3f3d2413f22d50ebc275a55cbfefa4ff7d277a1\memory_interface.\mem_lb_n' using process `$paramod$b3f3d2413f22d50ebc275a55cbfefa4ff7d277a1\memory_interface.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/memory_interface.v:33$1239'.
created $dff cell `$procdff$5258' with positive edge clock.
Creating register for signal `$paramod$b3f3d2413f22d50ebc275a55cbfefa4ff7d277a1\memory_interface.\mem_ub_n' using process `$paramod$b3f3d2413f22d50ebc275a55cbfefa4ff7d277a1\memory_interface.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/memory_interface.v:33$1239'.
created $dff cell `$procdff$5259' with positive edge clock.
Creating register for signal `$paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010111.\a_rdata' using process `$paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010111.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mem_arbiter.v:90$1238'.
created $dff cell `$procdff$5260' with positive edge clock.
Creating register for signal `$paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010111.\a_ready' using process `$paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010111.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mem_arbiter.v:90$1238'.
created $dff cell `$procdff$5261' with positive edge clock.
Creating register for signal `$paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010111.\b_rdata' using process `$paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010111.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mem_arbiter.v:90$1238'.
created $dff cell `$procdff$5262' with positive edge clock.
Creating register for signal `$paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010111.\b_ready' using process `$paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010111.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mem_arbiter.v:90$1238'.
created $dff cell `$procdff$5263' with positive edge clock.
Creating register for signal `$paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010111.\c_rdata' using process `$paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010111.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mem_arbiter.v:90$1238'.
created $dff cell `$procdff$5264' with positive edge clock.
Creating register for signal `$paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010111.\c_ready' using process `$paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010111.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mem_arbiter.v:90$1238'.
created $dff cell `$procdff$5265' with positive edge clock.
Creating register for signal `$paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010111.\m_req' using process `$paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010111.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mem_arbiter.v:90$1238'.
created $dff cell `$procdff$5266' with positive edge clock.
Creating register for signal `$paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010111.\m_wr' using process `$paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010111.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mem_arbiter.v:90$1238'.
created $dff cell `$procdff$5267' with positive edge clock.
Creating register for signal `$paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010111.\m_addr' using process `$paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010111.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mem_arbiter.v:90$1238'.
created $dff cell `$procdff$5268' with positive edge clock.
Creating register for signal `$paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010111.\m_wdata' using process `$paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010111.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mem_arbiter.v:90$1238'.
created $dff cell `$procdff$5269' with positive edge clock.
Creating register for signal `$paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010111.\owner' using process `$paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010111.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mem_arbiter.v:90$1238'.
created $dff cell `$procdff$5270' with positive edge clock.
Creating register for signal `$paramod$79958c098f4e7efe85e0f2fccdc4f496fe8d2f0b\neuron_memory.\state' using process `$paramod$79958c098f4e7efe85e0f2fccdc4f496fe8d2f0b\neuron_memory.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:283$1118'.
created $dff cell `$procdff$5271' with positive edge clock.
Creating register for signal `$paramod$79958c098f4e7efe85e0f2fccdc4f496fe8d2f0b\neuron_memory.\busy' using process `$paramod$79958c098f4e7efe85e0f2fccdc4f496fe8d2f0b\neuron_memory.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:283$1118'.
created $dff cell `$procdff$5272' with positive edge clock.
Creating register for signal `$paramod$79958c098f4e7efe85e0f2fccdc4f496fe8d2f0b\neuron_memory.\done' using process `$paramod$79958c098f4e7efe85e0f2fccdc4f496fe8d2f0b\neuron_memory.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:283$1118'.
created $dff cell `$procdff$5273' with positive edge clock.
Creating register for signal `$paramod$79958c098f4e7efe85e0f2fccdc4f496fe8d2f0b\neuron_memory.\neuron_start' using process `$paramod$79958c098f4e7efe85e0f2fccdc4f496fe8d2f0b\neuron_memory.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:283$1118'.
created $dff cell `$procdff$5274' with positive edge clock.
Creating register for signal `$paramod$79958c098f4e7efe85e0f2fccdc4f496fe8d2f0b\neuron_memory.\bias_reg' using process `$paramod$79958c098f4e7efe85e0f2fccdc4f496fe8d2f0b\neuron_memory.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:283$1118'.
created $dff cell `$procdff$5275' with positive edge clock.
Creating register for signal `$paramod$79958c098f4e7efe85e0f2fccdc4f496fe8d2f0b\neuron_memory.\index' using process `$paramod$79958c098f4e7efe85e0f2fccdc4f496fe8d2f0b\neuron_memory.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:283$1118'.
created $dff cell `$procdff$5276' with positive edge clock.
Creating register for signal `$paramod$79958c098f4e7efe85e0f2fccdc4f496fe8d2f0b\neuron_memory.\neuron_index' using process `$paramod$79958c098f4e7efe85e0f2fccdc4f496fe8d2f0b\neuron_memory.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:283$1118'.
created $dff cell `$procdff$5277' with positive edge clock.
Creating register for signal `$paramod$79958c098f4e7efe85e0f2fccdc4f496fe8d2f0b\neuron_memory.\w_group_base' using process `$paramod$79958c098f4e7efe85e0f2fccdc4f496fe8d2f0b\neuron_memory.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:283$1118'.
created $dff cell `$procdff$5278' with positive edge clock.
Creating register for signal `$paramod$79958c098f4e7efe85e0f2fccdc4f496fe8d2f0b\neuron_memory.\bias_group_addr' using process `$paramod$79958c098f4e7efe85e0f2fccdc4f496fe8d2f0b\neuron_memory.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:283$1118'.
created $dff cell `$procdff$5279' with positive edge clock.
Creating register for signal `$paramod$79958c098f4e7efe85e0f2fccdc4f496fe8d2f0b\neuron_memory.\access_req' using process `$paramod$79958c098f4e7efe85e0f2fccdc4f496fe8d2f0b\neuron_memory.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:283$1118'.
created $dff cell `$procdff$5280' with positive edge clock.
Creating register for signal `$paramod$79958c098f4e7efe85e0f2fccdc4f496fe8d2f0b\neuron_memory.\access_wr' using process `$paramod$79958c098f4e7efe85e0f2fccdc4f496fe8d2f0b\neuron_memory.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:283$1118'.
created $dff cell `$procdff$5281' with positive edge clock.
Creating register for signal `$paramod$79958c098f4e7efe85e0f2fccdc4f496fe8d2f0b\neuron_memory.\access_addr' using process `$paramod$79958c098f4e7efe85e0f2fccdc4f496fe8d2f0b\neuron_memory.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:283$1118'.
created $dff cell `$procdff$5282' with positive edge clock.
Creating register for signal `$paramod$79958c098f4e7efe85e0f2fccdc4f496fe8d2f0b\neuron_memory.\access_wdata' using process `$paramod$79958c098f4e7efe85e0f2fccdc4f496fe8d2f0b\neuron_memory.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:283$1118'.
created $dff cell `$procdff$5283' with positive edge clock.
Creating register for signal `$paramod$79958c098f4e7efe85e0f2fccdc4f496fe8d2f0b\neuron_memory.\rst_i' using process `$paramod$79958c098f4e7efe85e0f2fccdc4f496fe8d2f0b\neuron_memory.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:283$1118'.
created $dff cell `$procdff$5284' with positive edge clock.
Creating register for signal `$paramod$79958c098f4e7efe85e0f2fccdc4f496fe8d2f0b\neuron_memory.$memwr$\y_reg$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:304$1113_EN' using process `$paramod$79958c098f4e7efe85e0f2fccdc4f496fe8d2f0b\neuron_memory.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:283$1118'.
created $dff cell `$procdff$5285' with positive edge clock.
Creating register for signal `$paramod$79958c098f4e7efe85e0f2fccdc4f496fe8d2f0b\neuron_memory.$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:357$1114_ADDR' using process `$paramod$79958c098f4e7efe85e0f2fccdc4f496fe8d2f0b\neuron_memory.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:283$1118'.
created $dff cell `$procdff$5286' with positive edge clock.
Creating register for signal `$paramod$79958c098f4e7efe85e0f2fccdc4f496fe8d2f0b\neuron_memory.$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:357$1114_DATA' using process `$paramod$79958c098f4e7efe85e0f2fccdc4f496fe8d2f0b\neuron_memory.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:283$1118'.
created $dff cell `$procdff$5287' with positive edge clock.
Creating register for signal `$paramod$79958c098f4e7efe85e0f2fccdc4f496fe8d2f0b\neuron_memory.$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:357$1114_EN' using process `$paramod$79958c098f4e7efe85e0f2fccdc4f496fe8d2f0b\neuron_memory.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:283$1118'.
created $dff cell `$procdff$5288' with positive edge clock.
Creating register for signal `$paramod$79958c098f4e7efe85e0f2fccdc4f496fe8d2f0b\neuron_memory.$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:390$1115_ADDR' using process `$paramod$79958c098f4e7efe85e0f2fccdc4f496fe8d2f0b\neuron_memory.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:283$1118'.
created $dff cell `$procdff$5289' with positive edge clock.
Creating register for signal `$paramod$79958c098f4e7efe85e0f2fccdc4f496fe8d2f0b\neuron_memory.$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:390$1115_DATA' using process `$paramod$79958c098f4e7efe85e0f2fccdc4f496fe8d2f0b\neuron_memory.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:283$1118'.
created $dff cell `$procdff$5290' with positive edge clock.
Creating register for signal `$paramod$79958c098f4e7efe85e0f2fccdc4f496fe8d2f0b\neuron_memory.$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:390$1115_EN' using process `$paramod$79958c098f4e7efe85e0f2fccdc4f496fe8d2f0b\neuron_memory.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:283$1118'.
created $dff cell `$procdff$5291' with positive edge clock.
Creating register for signal `$paramod$79958c098f4e7efe85e0f2fccdc4f496fe8d2f0b\neuron_memory.$memwr$\y_reg$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:449$1116_ADDR' using process `$paramod$79958c098f4e7efe85e0f2fccdc4f496fe8d2f0b\neuron_memory.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:283$1118'.
created $dff cell `$procdff$5292' with positive edge clock.
Creating register for signal `$paramod$79958c098f4e7efe85e0f2fccdc4f496fe8d2f0b\neuron_memory.$memwr$\y_reg$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:449$1116_DATA' using process `$paramod$79958c098f4e7efe85e0f2fccdc4f496fe8d2f0b\neuron_memory.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:283$1118'.
created $dff cell `$procdff$5293' with positive edge clock.
Creating register for signal `$paramod$79958c098f4e7efe85e0f2fccdc4f496fe8d2f0b\neuron_memory.$memwr$\y_reg$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:449$1116_EN' using process `$paramod$79958c098f4e7efe85e0f2fccdc4f496fe8d2f0b\neuron_memory.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:283$1118'.
created $dff cell `$procdff$5294' with positive edge clock.
Creating register for signal `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.\ram_req' using process `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$869'.
created $dff cell `$procdff$5295' with positive edge clock.
Creating register for signal `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.\ram_wr' using process `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$869'.
created $dff cell `$procdff$5296' with positive edge clock.
Creating register for signal `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.\ram_addr' using process `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$869'.
created $dff cell `$procdff$5297' with positive edge clock.
Creating register for signal `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.\ram_wdata' using process `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$869'.
created $dff cell `$procdff$5298' with positive edge clock.
Creating register for signal `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.\state' using process `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$869'.
created $dff cell `$procdff$5299' with positive edge clock.
Creating register for signal `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.\desc_byte_idx' using process `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$869'.
created $dff cell `$procdff$5300' with positive edge clock.
Creating register for signal `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.\busy' using process `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$869'.
created $dff cell `$procdff$5301' with positive edge clock.
Creating register for signal `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.\done' using process `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$869'.
created $dff cell `$procdff$5302' with positive edge clock.
Creating register for signal `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.\err' using process `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$869'.
created $dff cell `$procdff$5303' with positive edge clock.
Creating register for signal `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.\in_idx' using process `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$869'.
created $dff cell `$procdff$5304' with positive edge clock.
Creating register for signal `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.\neuron_idx' using process `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$869'.
created $dff cell `$procdff$5305' with positive edge clock.
Creating register for signal `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.\desc_addr' using process `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$869'.
created $dff cell `$procdff$5306' with positive edge clock.
Creating register for signal `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.\conn_ptr_acc' using process `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$869'.
created $dff cell `$procdff$5307' with positive edge clock.
Creating register for signal `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.\n_conn_acc' using process `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$869'.
created $dff cell `$procdff$5308' with positive edge clock.
Creating register for signal `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.\out_id_acc' using process `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$869'.
created $dff cell `$procdff$5309' with positive edge clock.
Creating register for signal `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.\conn_i' using process `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$869'.
created $dff cell `$procdff$5310' with positive edge clock.
Creating register for signal `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.\edge_byte_idx' using process `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$869'.
created $dff cell `$procdff$5311' with positive edge clock.
Creating register for signal `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.\src_id_acc' using process `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$869'.
created $dff cell `$procdff$5312' with positive edge clock.
Creating register for signal `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.\weight_acc' using process `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$869'.
created $dff cell `$procdff$5313' with positive edge clock.
Creating register for signal `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.\act_wr_en' using process `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$869'.
created $dff cell `$procdff$5314' with positive edge clock.
Creating register for signal `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.\act_wr_addr' using process `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$869'.
created $dff cell `$procdff$5315' with positive edge clock.
Creating register for signal `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.\act_wr_data' using process `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$869'.
created $dff cell `$procdff$5316' with positive edge clock.
Creating register for signal `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.\neuron_start' using process `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$869'.
created $dff cell `$procdff$5317' with positive edge clock.
Creating register for signal `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.\bias_reg' using process `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$869'.
created $dff cell `$procdff$5318' with positive edge clock.
Creating register for signal `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.\activation_reg' using process `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$869'.
created $dff cell `$procdff$5319' with positive edge clock.
Creating register for signal `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.\n_conn_padded_reg' using process `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$869'.
created $dff cell `$procdff$5320' with positive edge clock.
Creating register for signal `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.\ri' using process `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$869'.
created $dff cell `$procdff$5321' with positive edge clock.
Creating register for signal `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$800_EN' using process `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$869'.
created $dff cell `$procdff$5322' with positive edge clock.
Creating register for signal `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$801_EN' using process `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$869'.
created $dff cell `$procdff$5323' with positive edge clock.
Creating register for signal `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$802_EN' using process `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$869'.
created $dff cell `$procdff$5324' with positive edge clock.
Creating register for signal `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$803_EN' using process `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$869'.
created $dff cell `$procdff$5325' with positive edge clock.
Creating register for signal `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$804_EN' using process `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$869'.
created $dff cell `$procdff$5326' with positive edge clock.
Creating register for signal `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$805_EN' using process `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$869'.
created $dff cell `$procdff$5327' with positive edge clock.
Creating register for signal `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$806_EN' using process `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$869'.
created $dff cell `$procdff$5328' with positive edge clock.
Creating register for signal `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$807_EN' using process `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$869'.
created $dff cell `$procdff$5329' with positive edge clock.
Creating register for signal `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$808_EN' using process `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$869'.
created $dff cell `$procdff$5330' with positive edge clock.
Creating register for signal `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$809_EN' using process `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$869'.
created $dff cell `$procdff$5331' with positive edge clock.
Creating register for signal `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$810_EN' using process `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$869'.
created $dff cell `$procdff$5332' with positive edge clock.
Creating register for signal `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$811_EN' using process `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$869'.
created $dff cell `$procdff$5333' with positive edge clock.
Creating register for signal `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$812_EN' using process `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$869'.
created $dff cell `$procdff$5334' with positive edge clock.
Creating register for signal `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$813_EN' using process `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$869'.
created $dff cell `$procdff$5335' with positive edge clock.
Creating register for signal `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$814_EN' using process `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$869'.
created $dff cell `$procdff$5336' with positive edge clock.
Creating register for signal `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$815_EN' using process `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$869'.
created $dff cell `$procdff$5337' with positive edge clock.
Creating register for signal `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$816_EN' using process `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$869'.
created $dff cell `$procdff$5338' with positive edge clock.
Creating register for signal `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$817_EN' using process `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$869'.
created $dff cell `$procdff$5339' with positive edge clock.
Creating register for signal `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$818_EN' using process `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$869'.
created $dff cell `$procdff$5340' with positive edge clock.
Creating register for signal `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$819_EN' using process `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$869'.
created $dff cell `$procdff$5341' with positive edge clock.
Creating register for signal `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$820_EN' using process `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$869'.
created $dff cell `$procdff$5342' with positive edge clock.
Creating register for signal `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$821_EN' using process `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$869'.
created $dff cell `$procdff$5343' with positive edge clock.
Creating register for signal `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$822_EN' using process `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$869'.
created $dff cell `$procdff$5344' with positive edge clock.
Creating register for signal `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$823_EN' using process `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$869'.
created $dff cell `$procdff$5345' with positive edge clock.
Creating register for signal `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$824_EN' using process `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$869'.
created $dff cell `$procdff$5346' with positive edge clock.
Creating register for signal `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$825_EN' using process `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$869'.
created $dff cell `$procdff$5347' with positive edge clock.
Creating register for signal `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$826_EN' using process `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$869'.
created $dff cell `$procdff$5348' with positive edge clock.
Creating register for signal `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$827_EN' using process `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$869'.
created $dff cell `$procdff$5349' with positive edge clock.
Creating register for signal `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$828_EN' using process `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$869'.
created $dff cell `$procdff$5350' with positive edge clock.
Creating register for signal `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$829_EN' using process `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$869'.
created $dff cell `$procdff$5351' with positive edge clock.
Creating register for signal `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$830_EN' using process `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$869'.
created $dff cell `$procdff$5352' with positive edge clock.
Creating register for signal `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$831_EN' using process `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$869'.
created $dff cell `$procdff$5353' with positive edge clock.
Creating register for signal `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$832_EN' using process `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$869'.
created $dff cell `$procdff$5354' with positive edge clock.
Creating register for signal `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$833_EN' using process `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$869'.
created $dff cell `$procdff$5355' with positive edge clock.
Creating register for signal `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$834_EN' using process `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$869'.
created $dff cell `$procdff$5356' with positive edge clock.
Creating register for signal `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$835_EN' using process `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$869'.
created $dff cell `$procdff$5357' with positive edge clock.
Creating register for signal `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$836_EN' using process `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$869'.
created $dff cell `$procdff$5358' with positive edge clock.
Creating register for signal `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$837_EN' using process `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$869'.
created $dff cell `$procdff$5359' with positive edge clock.
Creating register for signal `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$838_EN' using process `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$869'.
created $dff cell `$procdff$5360' with positive edge clock.
Creating register for signal `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$839_EN' using process `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$869'.
created $dff cell `$procdff$5361' with positive edge clock.
Creating register for signal `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$840_EN' using process `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$869'.
created $dff cell `$procdff$5362' with positive edge clock.
Creating register for signal `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$841_EN' using process `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$869'.
created $dff cell `$procdff$5363' with positive edge clock.
Creating register for signal `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$842_EN' using process `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$869'.
created $dff cell `$procdff$5364' with positive edge clock.
Creating register for signal `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$843_EN' using process `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$869'.
created $dff cell `$procdff$5365' with positive edge clock.
Creating register for signal `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$844_EN' using process `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$869'.
created $dff cell `$procdff$5366' with positive edge clock.
Creating register for signal `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$845_EN' using process `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$869'.
created $dff cell `$procdff$5367' with positive edge clock.
Creating register for signal `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$846_EN' using process `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$869'.
created $dff cell `$procdff$5368' with positive edge clock.
Creating register for signal `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$847_EN' using process `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$869'.
created $dff cell `$procdff$5369' with positive edge clock.
Creating register for signal `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$848_EN' using process `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$869'.
created $dff cell `$procdff$5370' with positive edge clock.
Creating register for signal `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$849_EN' using process `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$869'.
created $dff cell `$procdff$5371' with positive edge clock.
Creating register for signal `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$850_EN' using process `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$869'.
created $dff cell `$procdff$5372' with positive edge clock.
Creating register for signal `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$851_EN' using process `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$869'.
created $dff cell `$procdff$5373' with positive edge clock.
Creating register for signal `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$852_EN' using process `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$869'.
created $dff cell `$procdff$5374' with positive edge clock.
Creating register for signal `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$853_EN' using process `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$869'.
created $dff cell `$procdff$5375' with positive edge clock.
Creating register for signal `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$854_EN' using process `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$869'.
created $dff cell `$procdff$5376' with positive edge clock.
Creating register for signal `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$855_EN' using process `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$869'.
created $dff cell `$procdff$5377' with positive edge clock.
Creating register for signal `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$856_EN' using process `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$869'.
created $dff cell `$procdff$5378' with positive edge clock.
Creating register for signal `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$857_EN' using process `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$869'.
created $dff cell `$procdff$5379' with positive edge clock.
Creating register for signal `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$858_EN' using process `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$869'.
created $dff cell `$procdff$5380' with positive edge clock.
Creating register for signal `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$859_EN' using process `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$869'.
created $dff cell `$procdff$5381' with positive edge clock.
Creating register for signal `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$860_EN' using process `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$869'.
created $dff cell `$procdff$5382' with positive edge clock.
Creating register for signal `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$861_EN' using process `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$869'.
created $dff cell `$procdff$5383' with positive edge clock.
Creating register for signal `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$862_EN' using process `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$869'.
created $dff cell `$procdff$5384' with positive edge clock.
Creating register for signal `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$863_EN' using process `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$869'.
created $dff cell `$procdff$5385' with positive edge clock.
Creating register for signal `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:495$864_ADDR' using process `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$869'.
created $dff cell `$procdff$5386' with positive edge clock.
Creating register for signal `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:495$864_DATA' using process `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$869'.
created $dff cell `$procdff$5387' with positive edge clock.
Creating register for signal `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:495$864_EN' using process `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$869'.
created $dff cell `$procdff$5388' with positive edge clock.
Creating register for signal `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:496$865_ADDR' using process `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$869'.
created $dff cell `$procdff$5389' with positive edge clock.
Creating register for signal `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:496$865_DATA' using process `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$869'.
created $dff cell `$procdff$5390' with positive edge clock.
Creating register for signal `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:496$865_EN' using process `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$869'.
created $dff cell `$procdff$5391' with positive edge clock.
Creating register for signal `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.\ram_req' using process `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:137$780'.
created $dff cell `$procdff$5392' with positive edge clock.
Creating register for signal `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.\ram_wr' using process `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:137$780'.
created $dff cell `$procdff$5393' with positive edge clock.
Creating register for signal `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.\ram_addr' using process `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:137$780'.
created $dff cell `$procdff$5394' with positive edge clock.
Creating register for signal `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.\ram_wdata' using process `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:137$780'.
created $dff cell `$procdff$5395' with positive edge clock.
Creating register for signal `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.\nm_start' using process `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:137$780'.
created $dff cell `$procdff$5396' with positive edge clock.
Creating register for signal `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.\seq_busy' using process `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:137$780'.
created $dff cell `$procdff$5397' with positive edge clock.
Creating register for signal `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.\seq_done' using process `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:137$780'.
created $dff cell `$procdff$5398' with positive edge clock.
Creating register for signal `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.\state' using process `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:137$780'.
created $dff cell `$procdff$5399' with positive edge clock.
Creating register for signal `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.\nm_x_base' using process `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:137$780'.
created $dff cell `$procdff$5400' with positive edge clock.
Creating register for signal `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.\nm_w_base' using process `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:137$780'.
created $dff cell `$procdff$5401' with positive edge clock.
Creating register for signal `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.\nm_bias_addr' using process `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:137$780'.
created $dff cell `$procdff$5402' with positive edge clock.
Creating register for signal `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.\nm_activation' using process `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:137$780'.
created $dff cell `$procdff$5403' with positive edge clock.
Creating register for signal `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.\nm_n_inputs' using process `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:137$780'.
created $dff cell `$procdff$5404' with positive edge clock.
Creating register for signal `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.\nm_n_neurons' using process `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:137$780'.
created $dff cell `$procdff$5405' with positive edge clock.
Creating register for signal `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.\layer_idx' using process `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:137$780'.
created $dff cell `$procdff$5406' with positive edge clock.
Creating register for signal `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.\num_layers_reg' using process `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:137$780'.
created $dff cell `$procdff$5407' with positive edge clock.
Creating register for signal `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.\desc_table_addr' using process `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:137$780'.
created $dff cell `$procdff$5408' with positive edge clock.
Creating register for signal `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.\desc_byte_idx' using process `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:137$780'.
created $dff cell `$procdff$5409' with positive edge clock.
Creating register for signal `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.\w_base_acc' using process `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:137$780'.
created $dff cell `$procdff$5410' with positive edge clock.
Creating register for signal `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.\bias_addr_acc' using process `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:137$780'.
created $dff cell `$procdff$5411' with positive edge clock.
Creating register for signal `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.\activation_acc' using process `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:137$780'.
created $dff cell `$procdff$5412' with positive edge clock.
Creating register for signal `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.\n_inputs_acc' using process `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:137$780'.
created $dff cell `$procdff$5413' with positive edge clock.
Creating register for signal `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.\n_neurons_acc' using process `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:137$780'.
created $dff cell `$procdff$5414' with positive edge clock.
Creating register for signal `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.\cur_sel' using process `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:137$780'.
created $dff cell `$procdff$5415' with positive edge clock.
Creating register for signal `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.\write_sel' using process `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:137$780'.
created $dff cell `$procdff$5416' with positive edge clock.
Creating register for signal `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.\copy_idx' using process `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:137$780'.
created $dff cell `$procdff$5417' with positive edge clock.
Creating register for signal `$paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine.\ram_req' using process `$paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:315$760'.
created $dff cell `$procdff$5418' with positive edge clock.
Creating register for signal `$paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine.\ram_wr' using process `$paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:315$760'.
created $dff cell `$procdff$5419' with positive edge clock.
Creating register for signal `$paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine.\ram_addr' using process `$paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:315$760'.
created $dff cell `$procdff$5420' with positive edge clock.
Creating register for signal `$paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine.\ram_wdata' using process `$paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:315$760'.
created $dff cell `$procdff$5421' with positive edge clock.
Creating register for signal `$paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine.\x_base' using process `$paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:315$760'.
created $dff cell `$procdff$5422' with positive edge clock.
Creating register for signal `$paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine.\w_base' using process `$paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:315$760'.
created $dff cell `$procdff$5423' with positive edge clock.
Creating register for signal `$paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine.\bias_addr' using process `$paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:315$760'.
created $dff cell `$procdff$5424' with positive edge clock.
Creating register for signal `$paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine.\activation' using process `$paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:315$760'.
created $dff cell `$procdff$5425' with positive edge clock.
Creating register for signal `$paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine.\n_inputs_real' using process `$paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:315$760'.
created $dff cell `$procdff$5426' with positive edge clock.
Creating register for signal `$paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine.\n_neurons_real' using process `$paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:315$760'.
created $dff cell `$procdff$5427' with positive edge clock.
Creating register for signal `$paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine.\nm_start' using process `$paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:315$760'.
created $dff cell `$procdff$5428' with positive edge clock.
Creating register for signal `$paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine.\nm_soft_rst' using process `$paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:315$760'.
created $dff cell `$procdff$5429' with positive edge clock.
Creating register for signal `$paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine.\table_base' using process `$paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:315$760'.
created $dff cell `$procdff$5430' with positive edge clock.
Creating register for signal `$paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine.\buf_a_base' using process `$paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:315$760'.
created $dff cell `$procdff$5431' with positive edge clock.
Creating register for signal `$paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine.\buf_b_base' using process `$paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:315$760'.
created $dff cell `$procdff$5432' with positive edge clock.
Creating register for signal `$paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine.\run_start' using process `$paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:315$760'.
created $dff cell `$procdff$5433' with positive edge clock.
Creating register for signal `$paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine.\run_num_layers' using process `$paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:315$760'.
created $dff cell `$procdff$5434' with positive edge clock.
Creating register for signal `$paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine.\net_type' using process `$paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:315$760'.
created $dff cell `$procdff$5435' with positive edge clock.
Creating register for signal `$paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine.\num_neurons_graph' using process `$paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:315$760'.
created $dff cell `$procdff$5436' with positive edge clock.
Creating register for signal `$paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine.\n_out' using process `$paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:315$760'.
created $dff cell `$procdff$5437' with positive edge clock.
Creating register for signal `$paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine.\state' using process `$paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:315$760'.
created $dff cell `$procdff$5438' with positive edge clock.
Creating register for signal `$paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine.\opcode' using process `$paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:315$760'.
created $dff cell `$procdff$5439' with positive edge clock.
Creating register for signal `$paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine.\byte_pos' using process `$paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:315$760'.
created $dff cell `$procdff$5440' with positive edge clock.
Creating register for signal `$paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine.\addr_acc' using process `$paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:315$760'.
created $dff cell `$procdff$5441' with positive edge clock.
Creating register for signal `$paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine.\len_acc' using process `$paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:315$760'.
created $dff cell `$procdff$5442' with positive edge clock.
Creating register for signal `$paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine.\len_remaining' using process `$paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:315$760'.
created $dff cell `$procdff$5443' with positive edge clock.
Creating register for signal `$paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine.\cur_addr' using process `$paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:315$760'.
created $dff cell `$procdff$5444' with positive edge clock.
Creating register for signal `$paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine.\pending_write' using process `$paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:315$760'.
created $dff cell `$procdff$5445' with positive edge clock.
Creating register for signal `$paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine.\pending_wdata' using process `$paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:315$760'.
created $dff cell `$procdff$5446' with positive edge clock.
Creating register for signal `$paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine.\cur_read_byte' using process `$paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:315$760'.
created $dff cell `$procdff$5447' with positive edge clock.
Creating register for signal `$paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine.\resp_index' using process `$paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:315$760'.
created $dff cell `$procdff$5448' with positive edge clock.
Creating register for signal `$paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine.\resp_len' using process `$paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:315$760'.
created $dff cell `$procdff$5449' with positive edge clock.
Creating register for signal `$paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine.\net_mode' using process `$paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:315$760'.
created $dff cell `$procdff$5450' with positive edge clock.
Creating register for signal `$paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine.\graph_mode' using process `$paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:315$760'.
created $dff cell `$procdff$5451' with positive edge clock.
Creating register for signal `$paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine.\status_snapshot' using process `$paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:315$760'.
created $dff cell `$procdff$5452' with positive edge clock.
Creating register for signal `$paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine.\status_done_sticky' using process `$paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:242$753'.
created $dff cell `$procdff$5453' with positive edge clock.
Creating register for signal `$paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller.\state' using process `$paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/psram_controller.v:99$1242'.
created $dff cell `$procdff$5454' with positive edge clock.
Creating register for signal `$paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller.\mem_rdata' using process `$paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/psram_controller.v:99$1242'.
created $dff cell `$procdff$5455' with positive edge clock.
Creating register for signal `$paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller.\mem_ready' using process `$paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/psram_controller.v:99$1242'.
created $dff cell `$procdff$5456' with positive edge clock.
Creating register for signal `$paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller.\psram_a' using process `$paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/psram_controller.v:99$1242'.
created $dff cell `$procdff$5457' with positive edge clock.
Creating register for signal `$paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller.\psram_ce_n' using process `$paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/psram_controller.v:99$1242'.
created $dff cell `$procdff$5458' with positive edge clock.
Creating register for signal `$paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller.\psram_oe_n' using process `$paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/psram_controller.v:99$1242'.
created $dff cell `$procdff$5459' with positive edge clock.
Creating register for signal `$paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller.\psram_we_n' using process `$paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/psram_controller.v:99$1242'.
created $dff cell `$procdff$5460' with positive edge clock.
Creating register for signal `$paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller.\psram_lb_n' using process `$paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/psram_controller.v:99$1242'.
created $dff cell `$procdff$5461' with positive edge clock.
Creating register for signal `$paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller.\psram_ub_n' using process `$paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/psram_controller.v:99$1242'.
created $dff cell `$procdff$5462' with positive edge clock.
Creating register for signal `$paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller.\psram_zz_n' using process `$paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/psram_controller.v:99$1242'.
created $dff cell `$procdff$5463' with positive edge clock.
Creating register for signal `$paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller.\counter' using process `$paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/psram_controller.v:99$1242'.
created $dff cell `$procdff$5464' with positive edge clock.
Creating register for signal `$paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller.\address_reg' using process `$paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/psram_controller.v:99$1242'.
created $dff cell `$procdff$5465' with positive edge clock.
Creating register for signal `$paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller.\wdata_reg' using process `$paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/psram_controller.v:99$1242'.
created $dff cell `$procdff$5466' with positive edge clock.
Creating register for signal `$paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller.\wr_reg' using process `$paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/psram_controller.v:99$1242'.
created $dff cell `$procdff$5467' with positive edge clock.
Creating register for signal `$paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller.\lb_reg' using process `$paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/psram_controller.v:99$1242'.
created $dff cell `$procdff$5468' with positive edge clock.
Creating register for signal `$paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller.\ub_reg' using process `$paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/psram_controller.v:99$1242'.
created $dff cell `$procdff$5469' with positive edge clock.
Creating register for signal `$paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller.\dq_out' using process `$paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/psram_controller.v:99$1242'.
created $dff cell `$procdff$5470' with positive edge clock.
Creating register for signal `$paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller.\dq_oe' using process `$paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/psram_controller.v:99$1242'.
created $dff cell `$procdff$5471' with positive edge clock.
Creating register for signal `$paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010111.\state' using process `$paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010111.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/int8_memory_access.v:55$676'.
created $dff cell `$procdff$5472' with positive edge clock.
Creating register for signal `$paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010111.\mem_req' using process `$paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010111.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/int8_memory_access.v:55$676'.
created $dff cell `$procdff$5473' with positive edge clock.
Creating register for signal `$paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010111.\mem_wr' using process `$paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010111.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/int8_memory_access.v:55$676'.
created $dff cell `$procdff$5474' with positive edge clock.
Creating register for signal `$paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010111.\mem_addr' using process `$paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010111.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/int8_memory_access.v:55$676'.
created $dff cell `$procdff$5475' with positive edge clock.
Creating register for signal `$paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010111.\mem_wdata' using process `$paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010111.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/int8_memory_access.v:55$676'.
created $dff cell `$procdff$5476' with positive edge clock.
Creating register for signal `$paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010111.\rdata' using process `$paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010111.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/int8_memory_access.v:55$676'.
created $dff cell `$procdff$5477' with positive edge clock.
Creating register for signal `$paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010111.\ready' using process `$paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010111.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/int8_memory_access.v:55$676'.
created $dff cell `$procdff$5478' with positive edge clock.
Creating register for signal `$paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010111.\mem_lb_n' using process `$paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010111.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/int8_memory_access.v:55$676'.
created $dff cell `$procdff$5479' with positive edge clock.
Creating register for signal `$paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010111.\mem_ub_n' using process `$paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010111.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/int8_memory_access.v:55$676'.
created $dff cell `$procdff$5480' with positive edge clock.
Creating register for signal `$paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010111.\addr_reg' using process `$paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010111.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/int8_memory_access.v:55$676'.
created $dff cell `$procdff$5481' with positive edge clock.
Creating register for signal `$paramod$c614a16d6b975c0ec2885ffa17a962bce4ddbcec\act_buffer.\rd_data' using process `$paramod$c614a16d6b975c0ec2885ffa17a962bce4ddbcec\act_buffer.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/act_buffer.v:60$651'.
created $dff cell `$procdff$5482' with positive edge clock.
Creating register for signal `$paramod$c614a16d6b975c0ec2885ffa17a962bce4ddbcec\act_buffer.$memwr$\mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/act_buffer.v:57$643_ADDR' using process `$paramod$c614a16d6b975c0ec2885ffa17a962bce4ddbcec\act_buffer.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/act_buffer.v:55$644'.
created $dff cell `$procdff$5483' with positive edge clock.
Creating register for signal `$paramod$c614a16d6b975c0ec2885ffa17a962bce4ddbcec\act_buffer.$memwr$\mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/act_buffer.v:57$643_DATA' using process `$paramod$c614a16d6b975c0ec2885ffa17a962bce4ddbcec\act_buffer.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/act_buffer.v:55$644'.
created $dff cell `$procdff$5484' with positive edge clock.
Creating register for signal `$paramod$c614a16d6b975c0ec2885ffa17a962bce4ddbcec\act_buffer.$memwr$\mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/act_buffer.v:57$643_EN' using process `$paramod$c614a16d6b975c0ec2885ffa17a962bce4ddbcec\act_buffer.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/act_buffer.v:55$644'.
created $dff cell `$procdff$5485' with positive edge clock.
Creating register for signal `$paramod$18f95495176adabb8b1efa1a4c23d17992af7212\neuron_parallel.\y' using process `$paramod$18f95495176adabb8b1efa1a4c23d17992af7212\neuron_parallel.$proc$/tmp/before_rewrite/neuron_parallel.v:130$633'.
created $dff cell `$procdff$5486' with positive edge clock.
Creating register for signal `$paramod$18f95495176adabb8b1efa1a4c23d17992af7212\neuron_parallel.\busy' using process `$paramod$18f95495176adabb8b1efa1a4c23d17992af7212\neuron_parallel.$proc$/tmp/before_rewrite/neuron_parallel.v:130$633'.
created $dff cell `$procdff$5487' with positive edge clock.
Creating register for signal `$paramod$18f95495176adabb8b1efa1a4c23d17992af7212\neuron_parallel.\done' using process `$paramod$18f95495176adabb8b1efa1a4c23d17992af7212\neuron_parallel.$proc$/tmp/before_rewrite/neuron_parallel.v:130$633'.
created $dff cell `$procdff$5488' with positive edge clock.
Creating register for signal `$paramod$18f95495176adabb8b1efa1a4c23d17992af7212\neuron_parallel.\group_index' using process `$paramod$18f95495176adabb8b1efa1a4c23d17992af7212\neuron_parallel.$proc$/tmp/before_rewrite/neuron_parallel.v:130$633'.
created $dff cell `$procdff$5489' with positive edge clock.
Creating register for signal `$paramod$18f95495176adabb8b1efa1a4c23d17992af7212\neuron_parallel.\acc' using process `$paramod$18f95495176adabb8b1efa1a4c23d17992af7212\neuron_parallel.$proc$/tmp/before_rewrite/neuron_parallel.v:130$633'.
created $dff cell `$procdff$5490' with positive edge clock.
Creating register for signal `\spi_slave.\miso' using process `\spi_slave.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_slave.v:119$12'.
created $dff cell `$procdff$5491' with positive edge clock.
Creating register for signal `\spi_slave.\rx_byte' using process `\spi_slave.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_slave.v:119$12'.
created $dff cell `$procdff$5492' with positive edge clock.
Creating register for signal `\spi_slave.\rx_valid' using process `\spi_slave.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_slave.v:119$12'.
created $dff cell `$procdff$5493' with positive edge clock.
Creating register for signal `\spi_slave.\tx_byte_req' using process `\spi_slave.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_slave.v:119$12'.
created $dff cell `$procdff$5494' with positive edge clock.
Creating register for signal `\spi_slave.\cs_start' using process `\spi_slave.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_slave.v:119$12'.
created $dff cell `$procdff$5495' with positive edge clock.
Creating register for signal `\spi_slave.\cs_end' using process `\spi_slave.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_slave.v:119$12'.
created $dff cell `$procdff$5496' with positive edge clock.
Creating register for signal `\spi_slave.\bit_count' using process `\spi_slave.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_slave.v:119$12'.
created $dff cell `$procdff$5497' with positive edge clock.
Creating register for signal `\spi_slave.\rx_shift' using process `\spi_slave.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_slave.v:119$12'.
created $dff cell `$procdff$5498' with positive edge clock.
Creating register for signal `\spi_slave.\tx_shift' using process `\spi_slave.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_slave.v:119$12'.
created $dff cell `$procdff$5499' with positive edge clock.
Creating register for signal `\spi_slave.\sclk_prev' using process `\spi_slave.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_slave.v:93$2'.
created $dff cell `$procdff$5500' with positive edge clock.
Creating register for signal `\spi_slave.\cs_n_prev' using process `\spi_slave.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_slave.v:93$2'.
created $dff cell `$procdff$5501' with positive edge clock.
Creating register for signal `\spi_slave.\sclk_sync' using process `\spi_slave.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_slave.v:71$1'.
created $dff cell `$procdff$5502' with positive edge clock.
Creating register for signal `\spi_slave.\mosi_sync' using process `\spi_slave.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_slave.v:71$1'.
created $dff cell `$procdff$5503' with positive edge clock.
Creating register for signal `\spi_slave.\cs_n_sync' using process `\spi_slave.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_slave.v:71$1'.
created $dff cell `$procdff$5504' with positive edge clock.
17.4.10. Executing PROC_MEMWR pass (convert process memory writes to cells).
17.4.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 5 empty switches in `$paramod$b3f3d2413f22d50ebc275a55cbfefa4ff7d277a1\memory_interface.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/memory_interface.v:33$1239'.
Removing empty process `$paramod$b3f3d2413f22d50ebc275a55cbfefa4ff7d277a1\memory_interface.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/memory_interface.v:33$1239'.
Found and cleaned up 8 empty switches in `$paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010111.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mem_arbiter.v:90$1238'.
Removing empty process `$paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010111.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mem_arbiter.v:90$1238'.
Found and cleaned up 10 empty switches in `$paramod$79958c098f4e7efe85e0f2fccdc4f496fe8d2f0b\neuron_memory.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:283$1118'.
Removing empty process `$paramod$79958c098f4e7efe85e0f2fccdc4f496fe8d2f0b\neuron_memory.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:283$1118'.
Found and cleaned up 19 empty switches in `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$869'.
Removing empty process `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$869'.
Found and cleaned up 10 empty switches in `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:137$780'.
Removing empty process `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:137$780'.
Found and cleaned up 29 empty switches in `$paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:315$760'.
Removing empty process `$paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:315$760'.
Found and cleaned up 4 empty switches in `$paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:263$755'.
Removing empty process `$paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:263$755'.
Found and cleaned up 4 empty switches in `$paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:242$753'.
Removing empty process `$paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:242$753'.
Removing empty process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:100$1312'.
Removing empty process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:100$1310'.
Removing empty process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:100$1308'.
Removing empty process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:100$1306'.
Removing empty process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:100$1304'.
Removing empty process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:100$1302'.
Removing empty process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:100$1300'.
Removing empty process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:81$1299'.
Removing empty process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:81$1298'.
Removing empty process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:81$1297'.
Removing empty process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:81$1296'.
Removing empty process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:81$1295'.
Removing empty process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:81$1294'.
Removing empty process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:81$1293'.
Removing empty process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:81$1292'.
Removing empty process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:40$1291'.
Removing empty process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:40$1290'.
Removing empty process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:40$1289'.
Removing empty process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:40$1288'.
Removing empty process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:40$1287'.
Removing empty process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:40$1286'.
Removing empty process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:40$1285'.
Removing empty process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:40$1284'.
Found and cleaned up 7 empty switches in `$paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/psram_controller.v:99$1242'.
Removing empty process `$paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/psram_controller.v:99$1242'.
Found and cleaned up 6 empty switches in `$paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010111.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/int8_memory_access.v:55$676'.
Removing empty process `$paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010111.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/int8_memory_access.v:55$676'.
Removing empty process `$paramod$c614a16d6b975c0ec2885ffa17a962bce4ddbcec\act_buffer.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/act_buffer.v:60$651'.
Found and cleaned up 1 empty switch in `$paramod$c614a16d6b975c0ec2885ffa17a962bce4ddbcec\act_buffer.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/act_buffer.v:55$644'.
Removing empty process `$paramod$c614a16d6b975c0ec2885ffa17a962bce4ddbcec\act_buffer.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/act_buffer.v:55$644'.
Found and cleaned up 9 empty switches in `$paramod$18f95495176adabb8b1efa1a4c23d17992af7212\neuron_parallel.$proc$/tmp/before_rewrite/neuron_parallel.v:130$633'.
Removing empty process `$paramod$18f95495176adabb8b1efa1a4c23d17992af7212\neuron_parallel.$proc$/tmp/before_rewrite/neuron_parallel.v:130$633'.
Found and cleaned up 8 empty switches in `\spi_slave.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_slave.v:119$12'.
Removing empty process `spi_slave.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_slave.v:119$12'.
Found and cleaned up 1 empty switch in `\spi_slave.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_slave.v:93$2'.
Removing empty process `spi_slave.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_slave.v:93$2'.
Found and cleaned up 1 empty switch in `\spi_slave.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_slave.v:71$1'.
Removing empty process `spi_slave.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_slave.v:71$1'.
Cleaned up 122 empty switches.
17.4.12. Executing OPT_EXPR pass (perform const folding).
Optimizing module spi_neuron_top.
Optimizing module $paramod$b3f3d2413f22d50ebc275a55cbfefa4ff7d277a1\memory_interface.
<suppressed ~8 debug messages>
Optimizing module $paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010111.
<suppressed ~5 debug messages>
Optimizing module $paramod$79958c098f4e7efe85e0f2fccdc4f496fe8d2f0b\neuron_memory.
<suppressed ~9 debug messages>
Optimizing module $paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.
<suppressed ~11 debug messages>
Optimizing module $paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.
<suppressed ~9 debug messages>
Optimizing module $paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine.
<suppressed ~19 debug messages>
Optimizing module $paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.
Optimizing module $paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller.
<suppressed ~4 debug messages>
Optimizing module $paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010111.
<suppressed ~15 debug messages>
Optimizing module $paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\mac_unit.
Optimizing module $paramod$c614a16d6b975c0ec2885ffa17a962bce4ddbcec\act_buffer.
Optimizing module $paramod$18f95495176adabb8b1efa1a4c23d17992af7212\neuron_parallel.
<suppressed ~1 debug messages>
Optimizing module spi_slave.
<suppressed ~8 debug messages>
17.5. Executing CHECK pass (checking for obvious problems).
Checking module spi_neuron_top...
Checking module $paramod$b3f3d2413f22d50ebc275a55cbfefa4ff7d277a1\memory_interface...
Checking module $paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010111...
Checking module $paramod$79958c098f4e7efe85e0f2fccdc4f496fe8d2f0b\neuron_memory...
Checking module $paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine...
Checking module $paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer...
Checking module $paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine...
Checking module $paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8...
Checking module $paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller...
Checking module $paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010111...
Checking module $paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\mac_unit...
Checking module $paramod$c614a16d6b975c0ec2885ffa17a962bce4ddbcec\act_buffer...
Checking module $paramod$18f95495176adabb8b1efa1a4c23d17992af7212\neuron_parallel...
Checking module spi_slave...
Found and reported 0 problems.
17.6. Executing FLATTEN pass (flatten design).
Deleting now unused module $paramod$b3f3d2413f22d50ebc275a55cbfefa4ff7d277a1\memory_interface.
Deleting now unused module $paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010111.
Deleting now unused module $paramod$79958c098f4e7efe85e0f2fccdc4f496fe8d2f0b\neuron_memory.
Deleting now unused module $paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.
Deleting now unused module $paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.
Deleting now unused module $paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine.
Deleting now unused module $paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.
Deleting now unused module $paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller.
Deleting now unused module $paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010111.
Deleting now unused module $paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\mac_unit.
Deleting now unused module $paramod$c614a16d6b975c0ec2885ffa17a962bce4ddbcec\act_buffer.
Deleting now unused module $paramod$18f95495176adabb8b1efa1a4c23d17992af7212\neuron_parallel.
Deleting now unused module spi_slave.
<suppressed ~22 debug messages>
17.7. Executing TRIBUF pass.
17.8. Executing DEMINOUT pass (demote inout ports to input or output).
17.9. Executing OPT_EXPR pass (perform const folding).
Optimizing module spi_neuron_top.
<suppressed ~48 debug messages>
17.10. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \spi_neuron_top..
Removed 148 unused cells and 1750 unused wires.
<suppressed ~226 debug messages>
17.11. Executing CHECK pass (checking for obvious problems).
Checking module spi_neuron_top...
Found and reported 0 problems.
17.12. Executing OPT pass (performing simple optimizations).
17.12.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module spi_neuron_top.
17.12.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\spi_neuron_top'.
Computing hashes of 2038 cells of `\spi_neuron_top'.
Finding duplicate cells in `\spi_neuron_top'.
Computing hashes of 1713 cells of `\spi_neuron_top'.
Finding duplicate cells in `\spi_neuron_top'.
Computing hashes of 1705 cells of `\spi_neuron_top'.
Finding duplicate cells in `\spi_neuron_top'.
<suppressed ~999 debug messages>
Removed a total of 333 cells.
17.12.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \spi_neuron_top..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Replacing known input bits on port A of cell $flatten\u_graph_engine.\u_neuron.$procmux$5065: \u_graph_engine.u_neuron.busy -> 1'0
Replacing known input bits on port A of cell $flatten\u_graph_engine.\u_neuron.$procmux$5063: \u_graph_engine.u_neuron.busy -> 1'1
Replacing known input bits on port A of cell $flatten\u_neuron_memory.\u_neuron.$procmux$5065: \u_neuron_memory.u_neuron.busy -> 1'0
Replacing known input bits on port A of cell $flatten\u_neuron_memory.\u_neuron.$procmux$5063: \u_neuron_memory.u_neuron.busy -> 1'1
Analyzing evaluation results.
dead port 1/2 on $mux $flatten\u_graph_engine.$procmux$2342.
dead port 1/2 on $mux $flatten\u_graph_engine.$procmux$2352.
dead port 1/2 on $mux $flatten\u_graph_engine.$procmux$2362.
dead port 1/2 on $mux $flatten\u_graph_engine.$procmux$2372.
dead port 1/2 on $mux $flatten\u_graph_engine.$procmux$2382.
dead port 1/2 on $mux $flatten\u_graph_engine.$procmux$2861.
dead port 2/2 on $mux $flatten\u_neuron_memory.$procmux$1764.
dead port 1/2 on $mux $flatten\u_neuron_memory.$procmux$1767.
dead port 2/2 on $mux $flatten\u_neuron_memory.$procmux$1773.
dead port 1/2 on $mux $flatten\u_neuron_memory.$procmux$1776.
dead port 2/2 on $mux $flatten\u_neuron_memory.$procmux$1782.
dead port 1/2 on $mux $flatten\u_neuron_memory.$procmux$1785.
dead port 2/2 on $mux $flatten\u_neuron_memory.$procmux$1794.
dead port 1/2 on $mux $flatten\u_neuron_memory.$procmux$1797.
dead port 2/2 on $mux $flatten\u_neuron_memory.$procmux$1806.
dead port 1/2 on $mux $flatten\u_neuron_memory.$procmux$1809.
dead port 2/2 on $mux $flatten\u_neuron_memory.$procmux$1818.
dead port 1/2 on $mux $flatten\u_neuron_memory.$procmux$1821.
dead port 2/2 on $mux $flatten\u_neuron_memory.$procmux$1831.
dead port 1/2 on $mux $flatten\u_neuron_memory.$procmux$1834.
dead port 2/2 on $mux $flatten\u_neuron_memory.$procmux$1844.
dead port 1/2 on $mux $flatten\u_neuron_memory.$procmux$1847.
dead port 2/2 on $mux $flatten\u_neuron_memory.$procmux$1857.
dead port 1/2 on $mux $flatten\u_neuron_memory.$procmux$1860.
dead port 1/2 on $mux $flatten\u_neuron_memory.$procmux$1866.
dead port 1/2 on $mux $flatten\u_neuron_memory.$procmux$1872.
dead port 1/2 on $mux $flatten\u_neuron_memory.$procmux$1878.
dead port 1/2 on $mux $flatten\u_neuron_memory.$procmux$1887.
dead port 1/2 on $mux $flatten\u_neuron_memory.$procmux$1896.
dead port 1/2 on $mux $flatten\u_neuron_memory.$procmux$1905.
dead port 1/2 on $mux $flatten\u_neuron_memory.$procmux$1915.
dead port 1/2 on $mux $flatten\u_neuron_memory.$procmux$1925.
dead port 1/2 on $mux $flatten\u_neuron_memory.$procmux$1935.
dead port 2/2 on $mux $flatten\u_spi_engine.$procmux$4637.
dead port 2/2 on $mux $flatten\u_spi_engine.$procmux$4639.
dead port 2/2 on $mux $flatten\u_spi_engine.$procmux$4647.
dead port 2/2 on $mux $flatten\u_spi_engine.$procmux$4649.
dead port 2/2 on $mux $flatten\u_spi_engine.$procmux$4657.
Removed 38 multiplexer ports.
<suppressed ~1376 debug messages>
17.12.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Optimizing cells in module \spi_neuron_top.
New ctrl vector for $pmux cell $flatten\u_layer_sequencer.$procmux$3248: $auto$opt_reduce.cc:137:opt_pmux$5599
Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$2359:
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$procmux$2359_Y
New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$procmux$2359_Y [0]
New connections: $flatten\u_graph_engine.$procmux$2359_Y [7:1] = { $flatten\u_graph_engine.$procmux$2359_Y [0] $flatten\u_graph_engine.$procmux$2359_Y [0] $flatten\u_graph_engine.$procmux$2359_Y [0] $flatten\u_graph_engine.$procmux$2359_Y [0] $flatten\u_graph_engine.$procmux$2359_Y [0] $flatten\u_graph_engine.$procmux$2359_Y [0] $flatten\u_graph_engine.$procmux$2359_Y [0] }
Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$2388:
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$863_EN[7:0]$933
New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$863_EN[7:0]$933 [0]
New connections: $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$863_EN[7:0]$933 [7:1] = { $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$863_EN[7:0]$933 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$863_EN[7:0]$933 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$863_EN[7:0]$933 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$863_EN[7:0]$933 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$863_EN[7:0]$933 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$863_EN[7:0]$933 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$863_EN[7:0]$933 [0] }
Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$2391:
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$862_EN[7:0]$932
New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$862_EN[7:0]$932 [0]
New connections: $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$862_EN[7:0]$932 [7:1] = { $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$862_EN[7:0]$932 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$862_EN[7:0]$932 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$862_EN[7:0]$932 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$862_EN[7:0]$932 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$862_EN[7:0]$932 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$862_EN[7:0]$932 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$862_EN[7:0]$932 [0] }
Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$2394:
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$861_EN[7:0]$931
New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$861_EN[7:0]$931 [0]
New connections: $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$861_EN[7:0]$931 [7:1] = { $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$861_EN[7:0]$931 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$861_EN[7:0]$931 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$861_EN[7:0]$931 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$861_EN[7:0]$931 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$861_EN[7:0]$931 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$861_EN[7:0]$931 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$861_EN[7:0]$931 [0] }
Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$2397:
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$860_EN[7:0]$930
New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$860_EN[7:0]$930 [0]
New connections: $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$860_EN[7:0]$930 [7:1] = { $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$860_EN[7:0]$930 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$860_EN[7:0]$930 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$860_EN[7:0]$930 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$860_EN[7:0]$930 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$860_EN[7:0]$930 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$860_EN[7:0]$930 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$860_EN[7:0]$930 [0] }
Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$2400:
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$859_EN[7:0]$929
New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$859_EN[7:0]$929 [0]
New connections: $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$859_EN[7:0]$929 [7:1] = { $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$859_EN[7:0]$929 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$859_EN[7:0]$929 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$859_EN[7:0]$929 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$859_EN[7:0]$929 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$859_EN[7:0]$929 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$859_EN[7:0]$929 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$859_EN[7:0]$929 [0] }
Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$2403:
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$858_EN[7:0]$928
New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$858_EN[7:0]$928 [0]
New connections: $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$858_EN[7:0]$928 [7:1] = { $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$858_EN[7:0]$928 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$858_EN[7:0]$928 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$858_EN[7:0]$928 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$858_EN[7:0]$928 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$858_EN[7:0]$928 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$858_EN[7:0]$928 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$858_EN[7:0]$928 [0] }
Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$2406:
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$857_EN[7:0]$927
New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$857_EN[7:0]$927 [0]
New connections: $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$857_EN[7:0]$927 [7:1] = { $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$857_EN[7:0]$927 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$857_EN[7:0]$927 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$857_EN[7:0]$927 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$857_EN[7:0]$927 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$857_EN[7:0]$927 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$857_EN[7:0]$927 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$857_EN[7:0]$927 [0] }
Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$2409:
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$856_EN[7:0]$926
New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$856_EN[7:0]$926 [0]
New connections: $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$856_EN[7:0]$926 [7:1] = { $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$856_EN[7:0]$926 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$856_EN[7:0]$926 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$856_EN[7:0]$926 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$856_EN[7:0]$926 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$856_EN[7:0]$926 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$856_EN[7:0]$926 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$856_EN[7:0]$926 [0] }
Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$2412:
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$855_EN[7:0]$925
New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$855_EN[7:0]$925 [0]
New connections: $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$855_EN[7:0]$925 [7:1] = { $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$855_EN[7:0]$925 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$855_EN[7:0]$925 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$855_EN[7:0]$925 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$855_EN[7:0]$925 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$855_EN[7:0]$925 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$855_EN[7:0]$925 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$855_EN[7:0]$925 [0] }
Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$2415:
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$854_EN[7:0]$924
New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$854_EN[7:0]$924 [0]
New connections: $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$854_EN[7:0]$924 [7:1] = { $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$854_EN[7:0]$924 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$854_EN[7:0]$924 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$854_EN[7:0]$924 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$854_EN[7:0]$924 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$854_EN[7:0]$924 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$854_EN[7:0]$924 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$854_EN[7:0]$924 [0] }
Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$2418:
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$853_EN[7:0]$923
New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$853_EN[7:0]$923 [0]
New connections: $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$853_EN[7:0]$923 [7:1] = { $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$853_EN[7:0]$923 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$853_EN[7:0]$923 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$853_EN[7:0]$923 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$853_EN[7:0]$923 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$853_EN[7:0]$923 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$853_EN[7:0]$923 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$853_EN[7:0]$923 [0] }
Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$2421:
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$852_EN[7:0]$922
New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$852_EN[7:0]$922 [0]
New connections: $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$852_EN[7:0]$922 [7:1] = { $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$852_EN[7:0]$922 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$852_EN[7:0]$922 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$852_EN[7:0]$922 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$852_EN[7:0]$922 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$852_EN[7:0]$922 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$852_EN[7:0]$922 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$852_EN[7:0]$922 [0] }
Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$2424:
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$851_EN[7:0]$921
New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$851_EN[7:0]$921 [0]
New connections: $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$851_EN[7:0]$921 [7:1] = { $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$851_EN[7:0]$921 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$851_EN[7:0]$921 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$851_EN[7:0]$921 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$851_EN[7:0]$921 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$851_EN[7:0]$921 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$851_EN[7:0]$921 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$851_EN[7:0]$921 [0] }
Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$2427:
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$850_EN[7:0]$920
New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$850_EN[7:0]$920 [0]
New connections: $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$850_EN[7:0]$920 [7:1] = { $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$850_EN[7:0]$920 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$850_EN[7:0]$920 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$850_EN[7:0]$920 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$850_EN[7:0]$920 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$850_EN[7:0]$920 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$850_EN[7:0]$920 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$850_EN[7:0]$920 [0] }
Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$2430:
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$849_EN[7:0]$919
New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$849_EN[7:0]$919 [0]
New connections: $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$849_EN[7:0]$919 [7:1] = { $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$849_EN[7:0]$919 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$849_EN[7:0]$919 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$849_EN[7:0]$919 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$849_EN[7:0]$919 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$849_EN[7:0]$919 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$849_EN[7:0]$919 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$849_EN[7:0]$919 [0] }
Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$2433:
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$848_EN[7:0]$918
New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$848_EN[7:0]$918 [0]
New connections: $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$848_EN[7:0]$918 [7:1] = { $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$848_EN[7:0]$918 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$848_EN[7:0]$918 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$848_EN[7:0]$918 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$848_EN[7:0]$918 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$848_EN[7:0]$918 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$848_EN[7:0]$918 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$848_EN[7:0]$918 [0] }
Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$2436:
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$847_EN[7:0]$917
New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$847_EN[7:0]$917 [0]
New connections: $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$847_EN[7:0]$917 [7:1] = { $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$847_EN[7:0]$917 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$847_EN[7:0]$917 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$847_EN[7:0]$917 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$847_EN[7:0]$917 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$847_EN[7:0]$917 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$847_EN[7:0]$917 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$847_EN[7:0]$917 [0] }
Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$2439:
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$846_EN[7:0]$916
New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$846_EN[7:0]$916 [0]
New connections: $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$846_EN[7:0]$916 [7:1] = { $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$846_EN[7:0]$916 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$846_EN[7:0]$916 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$846_EN[7:0]$916 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$846_EN[7:0]$916 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$846_EN[7:0]$916 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$846_EN[7:0]$916 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$846_EN[7:0]$916 [0] }
Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$2442:
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$845_EN[7:0]$915
New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$845_EN[7:0]$915 [0]
New connections: $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$845_EN[7:0]$915 [7:1] = { $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$845_EN[7:0]$915 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$845_EN[7:0]$915 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$845_EN[7:0]$915 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$845_EN[7:0]$915 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$845_EN[7:0]$915 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$845_EN[7:0]$915 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$845_EN[7:0]$915 [0] }
Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$2445:
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$844_EN[7:0]$914
New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$844_EN[7:0]$914 [0]
New connections: $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$844_EN[7:0]$914 [7:1] = { $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$844_EN[7:0]$914 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$844_EN[7:0]$914 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$844_EN[7:0]$914 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$844_EN[7:0]$914 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$844_EN[7:0]$914 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$844_EN[7:0]$914 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$844_EN[7:0]$914 [0] }
Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$2448:
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$843_EN[7:0]$913
New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$843_EN[7:0]$913 [0]
New connections: $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$843_EN[7:0]$913 [7:1] = { $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$843_EN[7:0]$913 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$843_EN[7:0]$913 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$843_EN[7:0]$913 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$843_EN[7:0]$913 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$843_EN[7:0]$913 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$843_EN[7:0]$913 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$843_EN[7:0]$913 [0] }
Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$2451:
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$842_EN[7:0]$912
New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$842_EN[7:0]$912 [0]
New connections: $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$842_EN[7:0]$912 [7:1] = { $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$842_EN[7:0]$912 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$842_EN[7:0]$912 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$842_EN[7:0]$912 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$842_EN[7:0]$912 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$842_EN[7:0]$912 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$842_EN[7:0]$912 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$842_EN[7:0]$912 [0] }
Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$2454:
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$841_EN[7:0]$911
New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$841_EN[7:0]$911 [0]
New connections: $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$841_EN[7:0]$911 [7:1] = { $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$841_EN[7:0]$911 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$841_EN[7:0]$911 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$841_EN[7:0]$911 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$841_EN[7:0]$911 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$841_EN[7:0]$911 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$841_EN[7:0]$911 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$841_EN[7:0]$911 [0] }
Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$2457:
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$840_EN[7:0]$910
New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$840_EN[7:0]$910 [0]
New connections: $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$840_EN[7:0]$910 [7:1] = { $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$840_EN[7:0]$910 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$840_EN[7:0]$910 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$840_EN[7:0]$910 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$840_EN[7:0]$910 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$840_EN[7:0]$910 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$840_EN[7:0]$910 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$840_EN[7:0]$910 [0] }
Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$2460:
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$839_EN[7:0]$909
New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$839_EN[7:0]$909 [0]
New connections: $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$839_EN[7:0]$909 [7:1] = { $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$839_EN[7:0]$909 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$839_EN[7:0]$909 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$839_EN[7:0]$909 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$839_EN[7:0]$909 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$839_EN[7:0]$909 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$839_EN[7:0]$909 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$839_EN[7:0]$909 [0] }
Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$2463:
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$838_EN[7:0]$908
New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$838_EN[7:0]$908 [0]
New connections: $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$838_EN[7:0]$908 [7:1] = { $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$838_EN[7:0]$908 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$838_EN[7:0]$908 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$838_EN[7:0]$908 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$838_EN[7:0]$908 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$838_EN[7:0]$908 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$838_EN[7:0]$908 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$838_EN[7:0]$908 [0] }
Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$2466:
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$837_EN[7:0]$907
New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$837_EN[7:0]$907 [0]
New connections: $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$837_EN[7:0]$907 [7:1] = { $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$837_EN[7:0]$907 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$837_EN[7:0]$907 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$837_EN[7:0]$907 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$837_EN[7:0]$907 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$837_EN[7:0]$907 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$837_EN[7:0]$907 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$837_EN[7:0]$907 [0] }
Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$2469:
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$836_EN[7:0]$906
New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$836_EN[7:0]$906 [0]
New connections: $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$836_EN[7:0]$906 [7:1] = { $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$836_EN[7:0]$906 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$836_EN[7:0]$906 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$836_EN[7:0]$906 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$836_EN[7:0]$906 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$836_EN[7:0]$906 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$836_EN[7:0]$906 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$836_EN[7:0]$906 [0] }
Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$2472:
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$835_EN[7:0]$905
New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$835_EN[7:0]$905 [0]
New connections: $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$835_EN[7:0]$905 [7:1] = { $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$835_EN[7:0]$905 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$835_EN[7:0]$905 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$835_EN[7:0]$905 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$835_EN[7:0]$905 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$835_EN[7:0]$905 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$835_EN[7:0]$905 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$835_EN[7:0]$905 [0] }
Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$2475:
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$834_EN[7:0]$904
New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$834_EN[7:0]$904 [0]
New connections: $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$834_EN[7:0]$904 [7:1] = { $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$834_EN[7:0]$904 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$834_EN[7:0]$904 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$834_EN[7:0]$904 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$834_EN[7:0]$904 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$834_EN[7:0]$904 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$834_EN[7:0]$904 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$834_EN[7:0]$904 [0] }
Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$2478:
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$833_EN[7:0]$903
New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$833_EN[7:0]$903 [0]
New connections: $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$833_EN[7:0]$903 [7:1] = { $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$833_EN[7:0]$903 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$833_EN[7:0]$903 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$833_EN[7:0]$903 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$833_EN[7:0]$903 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$833_EN[7:0]$903 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$833_EN[7:0]$903 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$833_EN[7:0]$903 [0] }
Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$2481:
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$832_EN[7:0]$902
New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$832_EN[7:0]$902 [0]
New connections: $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$832_EN[7:0]$902 [7:1] = { $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$832_EN[7:0]$902 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$832_EN[7:0]$902 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$832_EN[7:0]$902 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$832_EN[7:0]$902 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$832_EN[7:0]$902 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$832_EN[7:0]$902 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$832_EN[7:0]$902 [0] }
Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$2484:
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$831_EN[7:0]$901
New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$831_EN[7:0]$901 [0]
New connections: $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$831_EN[7:0]$901 [7:1] = { $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$831_EN[7:0]$901 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$831_EN[7:0]$901 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$831_EN[7:0]$901 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$831_EN[7:0]$901 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$831_EN[7:0]$901 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$831_EN[7:0]$901 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$831_EN[7:0]$901 [0] }
Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$2487:
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$830_EN[7:0]$900
New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$830_EN[7:0]$900 [0]
New connections: $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$830_EN[7:0]$900 [7:1] = { $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$830_EN[7:0]$900 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$830_EN[7:0]$900 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$830_EN[7:0]$900 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$830_EN[7:0]$900 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$830_EN[7:0]$900 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$830_EN[7:0]$900 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$830_EN[7:0]$900 [0] }
Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$2490:
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$829_EN[7:0]$899
New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$829_EN[7:0]$899 [0]
New connections: $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$829_EN[7:0]$899 [7:1] = { $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$829_EN[7:0]$899 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$829_EN[7:0]$899 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$829_EN[7:0]$899 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$829_EN[7:0]$899 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$829_EN[7:0]$899 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$829_EN[7:0]$899 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$829_EN[7:0]$899 [0] }
Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$2493:
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$828_EN[7:0]$898
New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$828_EN[7:0]$898 [0]
New connections: $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$828_EN[7:0]$898 [7:1] = { $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$828_EN[7:0]$898 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$828_EN[7:0]$898 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$828_EN[7:0]$898 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$828_EN[7:0]$898 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$828_EN[7:0]$898 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$828_EN[7:0]$898 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$828_EN[7:0]$898 [0] }
Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$2496:
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$827_EN[7:0]$897
New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$827_EN[7:0]$897 [0]
New connections: $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$827_EN[7:0]$897 [7:1] = { $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$827_EN[7:0]$897 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$827_EN[7:0]$897 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$827_EN[7:0]$897 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$827_EN[7:0]$897 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$827_EN[7:0]$897 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$827_EN[7:0]$897 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$827_EN[7:0]$897 [0] }
Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$2499:
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$826_EN[7:0]$896
New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$826_EN[7:0]$896 [0]
New connections: $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$826_EN[7:0]$896 [7:1] = { $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$826_EN[7:0]$896 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$826_EN[7:0]$896 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$826_EN[7:0]$896 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$826_EN[7:0]$896 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$826_EN[7:0]$896 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$826_EN[7:0]$896 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$826_EN[7:0]$896 [0] }
Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$2502:
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$825_EN[7:0]$895
New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$825_EN[7:0]$895 [0]
New connections: $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$825_EN[7:0]$895 [7:1] = { $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$825_EN[7:0]$895 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$825_EN[7:0]$895 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$825_EN[7:0]$895 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$825_EN[7:0]$895 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$825_EN[7:0]$895 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$825_EN[7:0]$895 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$825_EN[7:0]$895 [0] }
Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$2505:
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$824_EN[7:0]$894
New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$824_EN[7:0]$894 [0]
New connections: $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$824_EN[7:0]$894 [7:1] = { $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$824_EN[7:0]$894 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$824_EN[7:0]$894 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$824_EN[7:0]$894 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$824_EN[7:0]$894 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$824_EN[7:0]$894 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$824_EN[7:0]$894 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$824_EN[7:0]$894 [0] }
Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$2508:
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$823_EN[7:0]$893
New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$823_EN[7:0]$893 [0]
New connections: $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$823_EN[7:0]$893 [7:1] = { $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$823_EN[7:0]$893 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$823_EN[7:0]$893 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$823_EN[7:0]$893 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$823_EN[7:0]$893 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$823_EN[7:0]$893 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$823_EN[7:0]$893 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$823_EN[7:0]$893 [0] }
Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$2511:
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$822_EN[7:0]$892
New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$822_EN[7:0]$892 [0]
New connections: $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$822_EN[7:0]$892 [7:1] = { $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$822_EN[7:0]$892 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$822_EN[7:0]$892 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$822_EN[7:0]$892 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$822_EN[7:0]$892 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$822_EN[7:0]$892 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$822_EN[7:0]$892 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$822_EN[7:0]$892 [0] }
Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$2514:
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$821_EN[7:0]$891
New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$821_EN[7:0]$891 [0]
New connections: $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$821_EN[7:0]$891 [7:1] = { $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$821_EN[7:0]$891 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$821_EN[7:0]$891 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$821_EN[7:0]$891 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$821_EN[7:0]$891 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$821_EN[7:0]$891 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$821_EN[7:0]$891 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$821_EN[7:0]$891 [0] }
Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$2517:
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$820_EN[7:0]$890
New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$820_EN[7:0]$890 [0]
New connections: $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$820_EN[7:0]$890 [7:1] = { $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$820_EN[7:0]$890 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$820_EN[7:0]$890 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$820_EN[7:0]$890 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$820_EN[7:0]$890 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$820_EN[7:0]$890 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$820_EN[7:0]$890 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$820_EN[7:0]$890 [0] }
Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$2520:
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$819_EN[7:0]$889
New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$819_EN[7:0]$889 [0]
New connections: $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$819_EN[7:0]$889 [7:1] = { $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$819_EN[7:0]$889 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$819_EN[7:0]$889 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$819_EN[7:0]$889 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$819_EN[7:0]$889 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$819_EN[7:0]$889 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$819_EN[7:0]$889 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$819_EN[7:0]$889 [0] }
Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$2523:
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$818_EN[7:0]$888
New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$818_EN[7:0]$888 [0]
New connections: $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$818_EN[7:0]$888 [7:1] = { $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$818_EN[7:0]$888 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$818_EN[7:0]$888 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$818_EN[7:0]$888 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$818_EN[7:0]$888 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$818_EN[7:0]$888 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$818_EN[7:0]$888 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$818_EN[7:0]$888 [0] }
Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$2526:
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$817_EN[7:0]$887
New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$817_EN[7:0]$887 [0]
New connections: $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$817_EN[7:0]$887 [7:1] = { $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$817_EN[7:0]$887 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$817_EN[7:0]$887 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$817_EN[7:0]$887 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$817_EN[7:0]$887 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$817_EN[7:0]$887 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$817_EN[7:0]$887 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$817_EN[7:0]$887 [0] }
Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$2529:
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$816_EN[7:0]$886
New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$816_EN[7:0]$886 [0]
New connections: $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$816_EN[7:0]$886 [7:1] = { $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$816_EN[7:0]$886 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$816_EN[7:0]$886 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$816_EN[7:0]$886 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$816_EN[7:0]$886 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$816_EN[7:0]$886 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$816_EN[7:0]$886 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$816_EN[7:0]$886 [0] }
Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$2532:
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$815_EN[7:0]$885
New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$815_EN[7:0]$885 [0]
New connections: $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$815_EN[7:0]$885 [7:1] = { $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$815_EN[7:0]$885 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$815_EN[7:0]$885 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$815_EN[7:0]$885 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$815_EN[7:0]$885 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$815_EN[7:0]$885 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$815_EN[7:0]$885 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$815_EN[7:0]$885 [0] }
Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$2535:
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$814_EN[7:0]$884
New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$814_EN[7:0]$884 [0]
New connections: $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$814_EN[7:0]$884 [7:1] = { $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$814_EN[7:0]$884 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$814_EN[7:0]$884 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$814_EN[7:0]$884 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$814_EN[7:0]$884 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$814_EN[7:0]$884 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$814_EN[7:0]$884 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$814_EN[7:0]$884 [0] }
Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$2538:
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$813_EN[7:0]$883
New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$813_EN[7:0]$883 [0]
New connections: $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$813_EN[7:0]$883 [7:1] = { $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$813_EN[7:0]$883 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$813_EN[7:0]$883 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$813_EN[7:0]$883 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$813_EN[7:0]$883 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$813_EN[7:0]$883 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$813_EN[7:0]$883 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$813_EN[7:0]$883 [0] }
Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$2541:
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$812_EN[7:0]$882
New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$812_EN[7:0]$882 [0]
New connections: $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$812_EN[7:0]$882 [7:1] = { $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$812_EN[7:0]$882 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$812_EN[7:0]$882 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$812_EN[7:0]$882 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$812_EN[7:0]$882 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$812_EN[7:0]$882 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$812_EN[7:0]$882 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$812_EN[7:0]$882 [0] }
Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$2544:
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$811_EN[7:0]$881
New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$811_EN[7:0]$881 [0]
New connections: $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$811_EN[7:0]$881 [7:1] = { $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$811_EN[7:0]$881 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$811_EN[7:0]$881 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$811_EN[7:0]$881 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$811_EN[7:0]$881 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$811_EN[7:0]$881 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$811_EN[7:0]$881 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$811_EN[7:0]$881 [0] }
Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$2547:
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$810_EN[7:0]$880
New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$810_EN[7:0]$880 [0]
New connections: $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$810_EN[7:0]$880 [7:1] = { $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$810_EN[7:0]$880 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$810_EN[7:0]$880 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$810_EN[7:0]$880 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$810_EN[7:0]$880 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$810_EN[7:0]$880 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$810_EN[7:0]$880 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$810_EN[7:0]$880 [0] }
Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$2550:
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$809_EN[7:0]$879
New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$809_EN[7:0]$879 [0]
New connections: $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$809_EN[7:0]$879 [7:1] = { $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$809_EN[7:0]$879 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$809_EN[7:0]$879 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$809_EN[7:0]$879 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$809_EN[7:0]$879 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$809_EN[7:0]$879 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$809_EN[7:0]$879 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$809_EN[7:0]$879 [0] }
Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$2553:
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$808_EN[7:0]$878
New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$808_EN[7:0]$878 [0]
New connections: $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$808_EN[7:0]$878 [7:1] = { $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$808_EN[7:0]$878 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$808_EN[7:0]$878 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$808_EN[7:0]$878 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$808_EN[7:0]$878 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$808_EN[7:0]$878 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$808_EN[7:0]$878 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$808_EN[7:0]$878 [0] }
Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$2556:
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$807_EN[7:0]$877
New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$807_EN[7:0]$877 [0]
New connections: $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$807_EN[7:0]$877 [7:1] = { $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$807_EN[7:0]$877 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$807_EN[7:0]$877 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$807_EN[7:0]$877 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$807_EN[7:0]$877 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$807_EN[7:0]$877 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$807_EN[7:0]$877 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$807_EN[7:0]$877 [0] }
Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$2559:
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$806_EN[7:0]$876
New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$806_EN[7:0]$876 [0]
New connections: $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$806_EN[7:0]$876 [7:1] = { $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$806_EN[7:0]$876 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$806_EN[7:0]$876 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$806_EN[7:0]$876 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$806_EN[7:0]$876 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$806_EN[7:0]$876 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$806_EN[7:0]$876 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$806_EN[7:0]$876 [0] }
Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$2562:
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$805_EN[7:0]$875
New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$805_EN[7:0]$875 [0]
New connections: $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$805_EN[7:0]$875 [7:1] = { $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$805_EN[7:0]$875 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$805_EN[7:0]$875 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$805_EN[7:0]$875 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$805_EN[7:0]$875 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$805_EN[7:0]$875 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$805_EN[7:0]$875 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$805_EN[7:0]$875 [0] }
Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$2565:
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$804_EN[7:0]$874
New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$804_EN[7:0]$874 [0]
New connections: $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$804_EN[7:0]$874 [7:1] = { $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$804_EN[7:0]$874 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$804_EN[7:0]$874 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$804_EN[7:0]$874 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$804_EN[7:0]$874 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$804_EN[7:0]$874 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$804_EN[7:0]$874 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$804_EN[7:0]$874 [0] }
Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$2568:
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$803_EN[7:0]$873
New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$803_EN[7:0]$873 [0]
New connections: $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$803_EN[7:0]$873 [7:1] = { $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$803_EN[7:0]$873 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$803_EN[7:0]$873 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$803_EN[7:0]$873 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$803_EN[7:0]$873 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$803_EN[7:0]$873 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$803_EN[7:0]$873 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$803_EN[7:0]$873 [0] }
Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$2571:
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$802_EN[7:0]$872
New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$802_EN[7:0]$872 [0]
New connections: $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$802_EN[7:0]$872 [7:1] = { $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$802_EN[7:0]$872 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$802_EN[7:0]$872 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$802_EN[7:0]$872 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$802_EN[7:0]$872 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$802_EN[7:0]$872 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$802_EN[7:0]$872 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$802_EN[7:0]$872 [0] }
Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$2574:
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$801_EN[7:0]$871
New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$801_EN[7:0]$871 [0]
New connections: $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$801_EN[7:0]$871 [7:1] = { $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$801_EN[7:0]$871 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$801_EN[7:0]$871 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$801_EN[7:0]$871 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$801_EN[7:0]$871 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$801_EN[7:0]$871 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$801_EN[7:0]$871 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$801_EN[7:0]$871 [0] }
Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$2577:
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$800_EN[7:0]$870
New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$800_EN[7:0]$870 [0]
New connections: $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$800_EN[7:0]$870 [7:1] = { $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$800_EN[7:0]$870 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$800_EN[7:0]$870 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$800_EN[7:0]$870 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$800_EN[7:0]$870 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$800_EN[7:0]$870 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$800_EN[7:0]$870 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$800_EN[7:0]$870 [0] }
New ctrl vector for $pmux cell $flatten\u_graph_engine.$procmux$2581: { $auto$opt_reduce.cc:137:opt_pmux$5601 $flatten\u_graph_engine.$procmux$2586_CMP }
New ctrl vector for $pmux cell $flatten\u_spi_engine.$procmux$3869: $auto$opt_reduce.cc:137:opt_pmux$5603
New ctrl vector for $pmux cell $flatten\u_spi_engine.$procmux$3845: { $flatten\u_spi_engine.$procmux$3846_CMP $auto$opt_reduce.cc:137:opt_pmux$5605 }
New ctrl vector for $pmux cell $flatten\u_spi_engine.$procmux$4144: { $auto$opt_reduce.cc:137:opt_pmux$5607 $flatten\u_spi_engine.$procmux$4148_CMP $flatten\u_spi_engine.$procmux$4149_CMP $flatten\u_spi_engine.$procmux$4150_CMP $flatten\u_spi_engine.$procmux$4017_CTRL }
Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$2858:
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$procmux$2858_Y
New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$procmux$2858_Y [0]
New connections: $flatten\u_graph_engine.$procmux$2858_Y [7:1] = { $flatten\u_graph_engine.$procmux$2858_Y [0] $flatten\u_graph_engine.$procmux$2858_Y [0] $flatten\u_graph_engine.$procmux$2858_Y [0] $flatten\u_graph_engine.$procmux$2858_Y [0] $flatten\u_graph_engine.$procmux$2858_Y [0] $flatten\u_graph_engine.$procmux$2858_Y [0] $flatten\u_graph_engine.$procmux$2858_Y [0] }
New ctrl vector for $pmux cell $flatten\u_graph_engine.$procmux$3104: { $flatten\u_graph_engine.$procmux$2582_CMP $flatten\u_graph_engine.$procmux$2586_CMP $auto$opt_reduce.cc:137:opt_pmux$5609 }
New ctrl vector for $pmux cell $flatten\u_spi_engine.$procmux$3730: $auto$opt_reduce.cc:137:opt_pmux$5611
Consolidated identical input bits for $mux cell $flatten\u_graph_engine.\u_act_buffer.$procmux$5021:
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.\u_act_buffer.$0$memwr$\mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/act_buffer.v:57$643_EN[7:0]$647
New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.\u_act_buffer.$0$memwr$\mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/act_buffer.v:57$643_EN[7:0]$647 [0]
New connections: $flatten\u_graph_engine.\u_act_buffer.$0$memwr$\mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/act_buffer.v:57$643_EN[7:0]$647 [7:1] = { $flatten\u_graph_engine.\u_act_buffer.$0$memwr$\mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/act_buffer.v:57$643_EN[7:0]$647 [0] $flatten\u_graph_engine.\u_act_buffer.$0$memwr$\mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/act_buffer.v:57$643_EN[7:0]$647 [0] $flatten\u_graph_engine.\u_act_buffer.$0$memwr$\mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/act_buffer.v:57$643_EN[7:0]$647 [0] $flatten\u_graph_engine.\u_act_buffer.$0$memwr$\mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/act_buffer.v:57$643_EN[7:0]$647 [0] $flatten\u_graph_engine.\u_act_buffer.$0$memwr$\mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/act_buffer.v:57$643_EN[7:0]$647 [0] $flatten\u_graph_engine.\u_act_buffer.$0$memwr$\mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/act_buffer.v:57$643_EN[7:0]$647 [0] $flatten\u_graph_engine.\u_act_buffer.$0$memwr$\mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/act_buffer.v:57$643_EN[7:0]$647 [0] }
Consolidated identical input bits for $mux cell $flatten\u_neuron_memory.$procmux$1762:
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_neuron_memory.$procmux$1762_Y
New ports: A=1'0, B=1'1, Y=$flatten\u_neuron_memory.$procmux$1762_Y [0]
New connections: $flatten\u_neuron_memory.$procmux$1762_Y [7:1] = { $flatten\u_neuron_memory.$procmux$1762_Y [0] $flatten\u_neuron_memory.$procmux$1762_Y [0] $flatten\u_neuron_memory.$procmux$1762_Y [0] $flatten\u_neuron_memory.$procmux$1762_Y [0] $flatten\u_neuron_memory.$procmux$1762_Y [0] $flatten\u_neuron_memory.$procmux$1762_Y [0] $flatten\u_neuron_memory.$procmux$1762_Y [0] }
Consolidated identical input bits for $mux cell $flatten\u_neuron_memory.$procmux$1792:
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_neuron_memory.$procmux$1792_Y
New ports: A=1'0, B=1'1, Y=$flatten\u_neuron_memory.$procmux$1792_Y [0]
New connections: $flatten\u_neuron_memory.$procmux$1792_Y [7:1] = { $flatten\u_neuron_memory.$procmux$1792_Y [0] $flatten\u_neuron_memory.$procmux$1792_Y [0] $flatten\u_neuron_memory.$procmux$1792_Y [0] $flatten\u_neuron_memory.$procmux$1792_Y [0] $flatten\u_neuron_memory.$procmux$1792_Y [0] $flatten\u_neuron_memory.$procmux$1792_Y [0] $flatten\u_neuron_memory.$procmux$1792_Y [0] }
Consolidated identical input bits for $mux cell $flatten\u_neuron_memory.$procmux$1829:
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_neuron_memory.$procmux$1829_Y
New ports: A=1'0, B=1'1, Y=$flatten\u_neuron_memory.$procmux$1829_Y [0]
New connections: $flatten\u_neuron_memory.$procmux$1829_Y [7:1] = { $flatten\u_neuron_memory.$procmux$1829_Y [0] $flatten\u_neuron_memory.$procmux$1829_Y [0] $flatten\u_neuron_memory.$procmux$1829_Y [0] $flatten\u_neuron_memory.$procmux$1829_Y [0] $flatten\u_neuron_memory.$procmux$1829_Y [0] $flatten\u_neuron_memory.$procmux$1829_Y [0] $flatten\u_neuron_memory.$procmux$1829_Y [0] }
Consolidated identical input bits for $mux cell $flatten\u_neuron_memory.$procmux$1953:
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_neuron_memory.$0$memwr$\y_reg$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:304$1113_EN[7:0]$1119
New ports: A=1'0, B=1'1, Y=$flatten\u_neuron_memory.$0$memwr$\y_reg$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:304$1113_EN[7:0]$1119 [0]
New connections: $flatten\u_neuron_memory.$0$memwr$\y_reg$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:304$1113_EN[7:0]$1119 [7:1] = { $flatten\u_neuron_memory.$0$memwr$\y_reg$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:304$1113_EN[7:0]$1119 [0] $flatten\u_neuron_memory.$0$memwr$\y_reg$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:304$1113_EN[7:0]$1119 [0] $flatten\u_neuron_memory.$0$memwr$\y_reg$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:304$1113_EN[7:0]$1119 [0] $flatten\u_neuron_memory.$0$memwr$\y_reg$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:304$1113_EN[7:0]$1119 [0] $flatten\u_neuron_memory.$0$memwr$\y_reg$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:304$1113_EN[7:0]$1119 [0] $flatten\u_neuron_memory.$0$memwr$\y_reg$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:304$1113_EN[7:0]$1119 [0] $flatten\u_neuron_memory.$0$memwr$\y_reg$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:304$1113_EN[7:0]$1119 [0] }
New ctrl vector for $pmux cell $flatten\u_neuron_memory.$procmux$2168: { $flatten\u_neuron_memory.$procmux$1765_CMP $auto$opt_reduce.cc:137:opt_pmux$5613 $flatten\u_neuron_memory.$procmux$1985_CMP }
New ctrl vector for $pmux cell $flatten\u_spi_engine.$procmux$4609: $auto$opt_reduce.cc:137:opt_pmux$5615
New ctrl vector for $pmux cell $flatten\u_psram_ctrl.$procmux$4795: { $auto$opt_reduce.cc:137:opt_pmux$5617 $flatten\u_psram_ctrl.$procmux$4683_CMP }
New ctrl vector for $pmux cell $flatten\u_psram_ctrl.$procmux$4807: { $auto$opt_reduce.cc:137:opt_pmux$5619 $flatten\u_psram_ctrl.$procmux$4683_CMP }
Optimizing cells in module \spi_neuron_top.
Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$2635:
Old ports: A=$flatten\u_graph_engine.$2$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:496$865_EN[7:0]$1015, B=8'00000000, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:496$865_EN[7:0]$939
New ports: A=$flatten\u_graph_engine.$procmux$2858_Y [0], B=1'0, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:496$865_EN[7:0]$939 [0]
New connections: $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:496$865_EN[7:0]$939 [7:1] = { $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:496$865_EN[7:0]$939 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:496$865_EN[7:0]$939 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:496$865_EN[7:0]$939 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:496$865_EN[7:0]$939 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:496$865_EN[7:0]$939 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:496$865_EN[7:0]$939 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:496$865_EN[7:0]$939 [0] }
Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$2644:
Old ports: A=$flatten\u_graph_engine.$2$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:495$864_EN[7:0]$1012, B=8'00000000, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:495$864_EN[7:0]$936
New ports: A=$flatten\u_graph_engine.$procmux$2359_Y [0], B=1'0, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:495$864_EN[7:0]$936 [0]
New connections: $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:495$864_EN[7:0]$936 [7:1] = { $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:495$864_EN[7:0]$936 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:495$864_EN[7:0]$936 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:495$864_EN[7:0]$936 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:495$864_EN[7:0]$936 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:495$864_EN[7:0]$936 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:495$864_EN[7:0]$936 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:495$864_EN[7:0]$936 [0] }
Consolidated identical input bits for $mux cell $flatten\u_neuron_memory.$procmux$1863:
Old ports: A=8'00000000, B=$flatten\u_neuron_memory.$3$memwr$\y_reg$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:449$1116_EN[7:0]$1166, Y=$flatten\u_neuron_memory.$procmux$1863_Y
New ports: A=1'0, B=$flatten\u_neuron_memory.$procmux$1762_Y [0], Y=$flatten\u_neuron_memory.$procmux$1863_Y [0]
New connections: $flatten\u_neuron_memory.$procmux$1863_Y [7:1] = { $flatten\u_neuron_memory.$procmux$1863_Y [0] $flatten\u_neuron_memory.$procmux$1863_Y [0] $flatten\u_neuron_memory.$procmux$1863_Y [0] $flatten\u_neuron_memory.$procmux$1863_Y [0] $flatten\u_neuron_memory.$procmux$1863_Y [0] $flatten\u_neuron_memory.$procmux$1863_Y [0] $flatten\u_neuron_memory.$procmux$1863_Y [0] }
Consolidated identical input bits for $mux cell $flatten\u_neuron_memory.$procmux$1884:
Old ports: A=8'00000000, B=$flatten\u_neuron_memory.$3$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:390$1115_EN[7:0]$1158, Y=$flatten\u_neuron_memory.$procmux$1884_Y
New ports: A=1'0, B=$flatten\u_neuron_memory.$procmux$1792_Y [0], Y=$flatten\u_neuron_memory.$procmux$1884_Y [0]
New connections: $flatten\u_neuron_memory.$procmux$1884_Y [7:1] = { $flatten\u_neuron_memory.$procmux$1884_Y [0] $flatten\u_neuron_memory.$procmux$1884_Y [0] $flatten\u_neuron_memory.$procmux$1884_Y [0] $flatten\u_neuron_memory.$procmux$1884_Y [0] $flatten\u_neuron_memory.$procmux$1884_Y [0] $flatten\u_neuron_memory.$procmux$1884_Y [0] $flatten\u_neuron_memory.$procmux$1884_Y [0] }
Consolidated identical input bits for $mux cell $flatten\u_neuron_memory.$procmux$1912:
Old ports: A=8'00000000, B=$flatten\u_neuron_memory.$3$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:357$1114_EN[7:0]$1150, Y=$flatten\u_neuron_memory.$procmux$1912_Y
New ports: A=1'0, B=$flatten\u_neuron_memory.$procmux$1829_Y [0], Y=$flatten\u_neuron_memory.$procmux$1912_Y [0]
New connections: $flatten\u_neuron_memory.$procmux$1912_Y [7:1] = { $flatten\u_neuron_memory.$procmux$1912_Y [0] $flatten\u_neuron_memory.$procmux$1912_Y [0] $flatten\u_neuron_memory.$procmux$1912_Y [0] $flatten\u_neuron_memory.$procmux$1912_Y [0] $flatten\u_neuron_memory.$procmux$1912_Y [0] $flatten\u_neuron_memory.$procmux$1912_Y [0] $flatten\u_neuron_memory.$procmux$1912_Y [0] }
Optimizing cells in module \spi_neuron_top.
Consolidated identical input bits for $mux cell $flatten\u_neuron_memory.$procmux$1990:
Old ports: A=$flatten\u_neuron_memory.$2$memwr$\y_reg$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:449$1116_EN[7:0]$1147, B=8'00000000, Y=$flatten\u_neuron_memory.$0$memwr$\y_reg$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:449$1116_EN[7:0]$1128
New ports: A=$flatten\u_neuron_memory.$procmux$1863_Y [0], B=1'0, Y=$flatten\u_neuron_memory.$0$memwr$\y_reg$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:449$1116_EN[7:0]$1128 [0]
New connections: $flatten\u_neuron_memory.$0$memwr$\y_reg$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:449$1116_EN[7:0]$1128 [7:1] = { $flatten\u_neuron_memory.$0$memwr$\y_reg$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:449$1116_EN[7:0]$1128 [0] $flatten\u_neuron_memory.$0$memwr$\y_reg$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:449$1116_EN[7:0]$1128 [0] $flatten\u_neuron_memory.$0$memwr$\y_reg$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:449$1116_EN[7:0]$1128 [0] $flatten\u_neuron_memory.$0$memwr$\y_reg$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:449$1116_EN[7:0]$1128 [0] $flatten\u_neuron_memory.$0$memwr$\y_reg$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:449$1116_EN[7:0]$1128 [0] $flatten\u_neuron_memory.$0$memwr$\y_reg$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:449$1116_EN[7:0]$1128 [0] $flatten\u_neuron_memory.$0$memwr$\y_reg$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:449$1116_EN[7:0]$1128 [0] }
Consolidated identical input bits for $mux cell $flatten\u_neuron_memory.$procmux$1999:
Old ports: A=$flatten\u_neuron_memory.$2$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:390$1115_EN[7:0]$1144, B=8'00000000, Y=$flatten\u_neuron_memory.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:390$1115_EN[7:0]$1125
New ports: A=$flatten\u_neuron_memory.$procmux$1884_Y [0], B=1'0, Y=$flatten\u_neuron_memory.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:390$1115_EN[7:0]$1125 [0]
New connections: $flatten\u_neuron_memory.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:390$1115_EN[7:0]$1125 [7:1] = { $flatten\u_neuron_memory.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:390$1115_EN[7:0]$1125 [0] $flatten\u_neuron_memory.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:390$1115_EN[7:0]$1125 [0] $flatten\u_neuron_memory.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:390$1115_EN[7:0]$1125 [0] $flatten\u_neuron_memory.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:390$1115_EN[7:0]$1125 [0] $flatten\u_neuron_memory.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:390$1115_EN[7:0]$1125 [0] $flatten\u_neuron_memory.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:390$1115_EN[7:0]$1125 [0] $flatten\u_neuron_memory.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:390$1115_EN[7:0]$1125 [0] }
Consolidated identical input bits for $mux cell $flatten\u_neuron_memory.$procmux$2008:
Old ports: A=$flatten\u_neuron_memory.$2$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:357$1114_EN[7:0]$1141, B=8'00000000, Y=$flatten\u_neuron_memory.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:357$1114_EN[7:0]$1122
New ports: A=$flatten\u_neuron_memory.$procmux$1912_Y [0], B=1'0, Y=$flatten\u_neuron_memory.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:357$1114_EN[7:0]$1122 [0]
New connections: $flatten\u_neuron_memory.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:357$1114_EN[7:0]$1122 [7:1] = { $flatten\u_neuron_memory.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:357$1114_EN[7:0]$1122 [0] $flatten\u_neuron_memory.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:357$1114_EN[7:0]$1122 [0] $flatten\u_neuron_memory.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:357$1114_EN[7:0]$1122 [0] $flatten\u_neuron_memory.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:357$1114_EN[7:0]$1122 [0] $flatten\u_neuron_memory.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:357$1114_EN[7:0]$1122 [0] $flatten\u_neuron_memory.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:357$1114_EN[7:0]$1122 [0] $flatten\u_neuron_memory.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:357$1114_EN[7:0]$1122 [0] }
Optimizing cells in module \spi_neuron_top.
Performed a total of 90 changes.
17.12.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\spi_neuron_top'.
Computing hashes of 1678 cells of `\spi_neuron_top'.
Finding duplicate cells in `\spi_neuron_top'.
Computing hashes of 1584 cells of `\spi_neuron_top'.
Finding duplicate cells in `\spi_neuron_top'.
Computing hashes of 1581 cells of `\spi_neuron_top'.
Finding duplicate cells in `\spi_neuron_top'.
<suppressed ~291 debug messages>
Removed a total of 97 cells.
17.12.6. Executing OPT_DFF pass (perform DFF optimizations).
Setting constant 1-bit at position 0 on $flatten\u_psram_ctrl.$procdff$5463 ($dff) from module spi_neuron_top.
17.12.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \spi_neuron_top..
Removed 0 unused cells and 461 unused wires.
<suppressed ~1 debug messages>
17.12.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module spi_neuron_top.
17.12.9. Rerunning OPT passes. (Maybe there is more to do..)
17.12.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \spi_neuron_top..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~1223 debug messages>
17.12.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Optimizing cells in module \spi_neuron_top.
New ctrl vector for $pmux cell $flatten\u_spi_engine.$procmux$4085: { $flatten\u_spi_engine.$procmux$4086_CMP $flatten\u_spi_engine.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:218$749_Y $auto$opt_reduce.cc:137:opt_pmux$5621 $flatten\u_spi_engine.$procmux$3929_CMP $flatten\u_spi_engine.$procmux$3891_CMP $flatten\u_spi_engine.$procmux$3731_CMP $flatten\u_spi_engine.$procmux$3932_CMP $flatten\u_spi_engine.$procmux$3732_CMP $flatten\u_spi_engine.$procmux$3911_CMP $flatten\u_spi_engine.$procmux$3608_CMP $flatten\u_spi_engine.$procmux$3617_CMP $flatten\u_spi_engine.$procmux$3650_CMP $flatten\u_spi_engine.$procmux$3681_CMP }
New ctrl vector for $pmux cell $flatten\u_spi_engine.$procmux$3637: { $auto$opt_reduce.cc:137:opt_pmux$5623 $flatten\u_spi_engine.$procmux$3617_CMP }
New ctrl vector for $pmux cell $flatten\u_neuron_memory.$procmux$1969: { $flatten\u_neuron_memory.$procmux$1765_CMP $auto$opt_reduce.cc:137:opt_pmux$5625 $flatten\u_neuron_memory.$procmux$1985_CMP }
New ctrl vector for $pmux cell $flatten\u_neuron_memory.$procmux$2055: { $flatten\u_neuron_memory.$procmux$1765_CMP $auto$opt_reduce.cc:137:opt_pmux$5627 $flatten\u_neuron_memory.$procmux$1985_CMP }
New ctrl vector for $pmux cell $flatten\u_arbiter.$procmux$1668: { $auto$opt_reduce.cc:137:opt_pmux$5629 $flatten\u_arbiter.$procmux$1662_CMP }
New ctrl vector for $pmux cell $flatten\u_psram_ctrl.$procmux$4852: { $flatten\u_psram_ctrl.$procmux$4772_CMP $auto$opt_reduce.cc:137:opt_pmux$5631 $flatten\u_psram_ctrl.$procmux$4683_CMP $flatten\u_psram_ctrl.$procmux$4802_CMP }
Optimizing cells in module \spi_neuron_top.
Performed a total of 6 changes.
17.12.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\spi_neuron_top'.
Computing hashes of 1586 cells of `\spi_neuron_top'.
Finding duplicate cells in `\spi_neuron_top'.
Computing hashes of 1585 cells of `\spi_neuron_top'.
Finding duplicate cells in `\spi_neuron_top'.
<suppressed ~3 debug messages>
Removed a total of 1 cells.
17.12.13. Executing OPT_DFF pass (perform DFF optimizations).
17.12.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \spi_neuron_top..
Removed 0 unused cells and 1 unused wires.
<suppressed ~1 debug messages>
17.12.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module spi_neuron_top.
17.12.16. Rerunning OPT passes. (Maybe there is more to do..)
17.12.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \spi_neuron_top..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~1204 debug messages>
17.12.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Optimizing cells in module \spi_neuron_top.
Performed a total of 0 changes.
17.12.19. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\spi_neuron_top'.
Computing hashes of 1585 cells of `\spi_neuron_top'.
Finding duplicate cells in `\spi_neuron_top'.
Removed a total of 0 cells.
17.12.20. Executing OPT_DFF pass (perform DFF optimizations).
17.12.21. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \spi_neuron_top..
17.12.22. Executing OPT_EXPR pass (perform const folding).
Optimizing module spi_neuron_top.
17.12.23. Finished fast OPT passes. (There is nothing left to do.)
17.13. Executing FSM pass (extract and optimize FSM).
17.13.1. Executing FSM_DETECT pass (finding FSMs in design).
Found FSM state register spi_neuron_top.u_neuron_memory.state.
Not marking spi_neuron_top.u_neuron_memory.access_wdata as FSM state register:
Users of register don't seem to benefit from recoding.
Found FSM state register spi_neuron_top.u_graph_engine.state.
Found FSM state register spi_neuron_top.u_layer_sequencer.state.
Found FSM state register spi_neuron_top.u_neuron_memory.u_mem.state.
Found FSM state register spi_neuron_top.u_arbiter.owner.
Found FSM state register spi_neuron_top.u_spi_engine.resp_len.
Found FSM state register spi_neuron_top.u_spi_engine.state.
Found FSM state register spi_neuron_top.u_int8_access.state.
Found FSM state register spi_neuron_top.u_memory_if.state.
Found FSM state register spi_neuron_top.u_psram_ctrl.state.
17.13.2. Executing FSM_EXTRACT pass (extracting FSM from design).
Extracting FSM `\u_neuron_memory.state' from module `\spi_neuron_top'.
found $dff cell for state register: $flatten\u_neuron_memory.$procdff$5271
root of input selection tree: $flatten\u_neuron_memory.$0\state[3:0]
found reset state: 4'0000 (guessed from mux tree)
found ctrl input: \graph_rst
found ctrl input: $flatten\u_neuron_memory.$procmux$1765_CMP
found ctrl input: $flatten\u_neuron_memory.$procmux$1958_CMP
found ctrl input: $flatten\u_neuron_memory.$procmux$2157_CMP
found ctrl input: $flatten\u_neuron_memory.$procmux$1795_CMP
found ctrl input: $flatten\u_neuron_memory.$procmux$1832_CMP
found ctrl input: $flatten\u_neuron_memory.$procmux$1985_CMP
found state code: 4'0000
found ctrl input: \u_neuron_memory.u_neuron.done
found ctrl input: $flatten\u_neuron_memory.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:451$1168_Y
found state code: 4'0010
found state code: 4'0101
found ctrl input: \u_neuron_memory.u_mem.ready
found state code: 4'0100
found ctrl input: $flatten\u_neuron_memory.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:359$1152_Y
found state code: 4'0011
found ctrl input: \mux_nm_start
found state code: 4'0001
found ctrl output: $flatten\u_neuron_memory.$procmux$2157_CMP
found ctrl output: $flatten\u_neuron_memory.$procmux$1985_CMP
found ctrl output: $flatten\u_neuron_memory.$procmux$1958_CMP
found ctrl output: $flatten\u_neuron_memory.$procmux$1832_CMP
found ctrl output: $flatten\u_neuron_memory.$procmux$1795_CMP
found ctrl output: $flatten\u_neuron_memory.$procmux$1765_CMP
ctrl inputs: { $flatten\u_neuron_memory.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:359$1152_Y $flatten\u_neuron_memory.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:451$1168_Y \u_neuron_memory.u_mem.ready \u_neuron_memory.u_neuron.done \mux_nm_start \graph_rst }
ctrl outputs: { $flatten\u_neuron_memory.$0\state[3:0] $flatten\u_neuron_memory.$procmux$1765_CMP $flatten\u_neuron_memory.$procmux$1795_CMP $flatten\u_neuron_memory.$procmux$1832_CMP $flatten\u_neuron_memory.$procmux$1958_CMP $flatten\u_neuron_memory.$procmux$1985_CMP $flatten\u_neuron_memory.$procmux$2157_CMP }
transition: 4'0000 6'----00 -> 4'0000 10'0000000010
transition: 4'0000 6'----10 -> 4'0001 10'0001000010
transition: 4'0000 6'-----1 -> 4'0000 10'0000000010
transition: 4'0100 6'-----0 -> 4'0101 10'0101000100
transition: 4'0100 6'-----1 -> 4'0000 10'0000000100
transition: 4'0010 6'--0--0 -> 4'0010 10'0010010000
transition: 4'0010 6'0-1--0 -> 4'0010 10'0010010000
transition: 4'0010 6'1-1--0 -> 4'0011 10'0011010000
transition: 4'0010 6'-----1 -> 4'0000 10'0000010000
transition: 4'0001 6'--0--0 -> 4'0001 10'0001001000
transition: 4'0001 6'0-1--0 -> 4'0001 10'0001001000
transition: 4'0001 6'1-1--0 -> 4'0010 10'0010001000
transition: 4'0001 6'-----1 -> 4'0000 10'0000001000
transition: 4'0101 6'---0-0 -> 4'0101 10'0101100000
transition: 4'0101 6'-0-1-0 -> 4'0010 10'0010100000
transition: 4'0101 6'-1-1-0 -> 4'0000 10'0000100000
transition: 4'0101 6'-----1 -> 4'0000 10'0000100000
transition: 4'0011 6'--0--0 -> 4'0011 10'0011000001
transition: 4'0011 6'--1--0 -> 4'0100 10'0100000001
transition: 4'0011 6'-----1 -> 4'0000 10'0000000001
Extracting FSM `\u_graph_engine.state' from module `\spi_neuron_top'.
found $dff cell for state register: $flatten\u_graph_engine.$procdff$5299
root of input selection tree: $flatten\u_graph_engine.$0\state[3:0]
found reset state: 4'0000 (guessed from mux tree)
found ctrl input: \graph_rst
found ctrl input: $flatten\u_graph_engine.$procmux$2621_CMP
found ctrl input: $flatten\u_graph_engine.$procmux$2582_CMP
found ctrl input: $flatten\u_graph_engine.$procmux$2607_CMP
found ctrl input: $flatten\u_graph_engine.$procmux$2597_CMP
found ctrl input: $flatten\u_graph_engine.$procmux$2340_CMP
found ctrl input: $flatten\u_graph_engine.$procmux$2226_CMP
found ctrl input: $flatten\u_graph_engine.$procmux$2586_CMP
found ctrl input: $flatten\u_graph_engine.$procmux$2261_CMP
found ctrl input: $flatten\u_graph_engine.$procmux$2587_CMP
found ctrl input: $flatten\u_graph_engine.$procmux$2610_CMP
found ctrl input: $flatten\u_graph_engine.$procmux$2588_CMP
found ctrl input: $flatten\u_graph_engine.$procmux$2882_CTRL
found state code: 4'0000
found ctrl input: \u_arbiter.c_ready
found ctrl input: $flatten\u_graph_engine.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:527$1041_Y
found state code: 4'0011
found state code: 4'1011
found ctrl input: \u_graph_engine.u_neuron.done
found ctrl input: \u_graph_engine.is_output_sink
found state code: 4'1010
found state code: 4'1001
found ctrl input: $flatten\u_graph_engine.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:498$1038_Y
found state code: 4'0101
found state code: 4'1000
found ctrl input: $flatten\u_graph_engine.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:449$1030_Y
found ctrl input: $flatten\u_graph_engine.$logic_or$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:456$1035_Y
found state code: 4'0111
found state code: 4'1100
found ctrl input: $flatten\u_graph_engine.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:420$1026_Y
found state code: 4'0110
found ctrl input: $flatten\u_graph_engine.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:389$1021_Y
found state code: 4'0100
found ctrl input: $flatten\u_graph_engine.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:346$1018_Y
found state code: 4'0001
found state code: 4'0010
found ctrl input: \graph_run_start
found ctrl output: $flatten\u_graph_engine.$procmux$2882_CMP [1]
found ctrl output: $flatten\u_graph_engine.$procmux$2882_CMP [0]
found ctrl output: $flatten\u_graph_engine.$procmux$2621_CMP
found ctrl output: $flatten\u_graph_engine.$procmux$2610_CMP
found ctrl output: $flatten\u_graph_engine.$procmux$2607_CMP
found ctrl output: $flatten\u_graph_engine.$procmux$2597_CMP
found ctrl output: $flatten\u_graph_engine.$procmux$2588_CMP
found ctrl output: $flatten\u_graph_engine.$procmux$2587_CMP
found ctrl output: $flatten\u_graph_engine.$procmux$2586_CMP
found ctrl output: $flatten\u_graph_engine.$procmux$2582_CMP
found ctrl output: $flatten\u_graph_engine.$procmux$2340_CMP
found ctrl output: $flatten\u_graph_engine.$procmux$2261_CMP
found ctrl output: $flatten\u_graph_engine.$procmux$2226_CMP
ctrl inputs: { \u_graph_engine.is_output_sink $flatten\u_graph_engine.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:346$1018_Y $flatten\u_graph_engine.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:389$1021_Y $flatten\u_graph_engine.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:420$1026_Y $flatten\u_graph_engine.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:449$1030_Y $flatten\u_graph_engine.$logic_or$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:456$1035_Y $flatten\u_graph_engine.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:498$1038_Y $flatten\u_graph_engine.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:527$1041_Y $flatten\u_graph_engine.$procmux$2882_CTRL \u_graph_engine.u_neuron.done \u_arbiter.c_ready \graph_rst \graph_run_start }
ctrl outputs: { $flatten\u_graph_engine.$0\state[3:0] $flatten\u_graph_engine.$procmux$2226_CMP $flatten\u_graph_engine.$procmux$2261_CMP $flatten\u_graph_engine.$procmux$2340_CMP $flatten\u_graph_engine.$procmux$2582_CMP $flatten\u_graph_engine.$procmux$2586_CMP $flatten\u_graph_engine.$procmux$2587_CMP $flatten\u_graph_engine.$procmux$2588_CMP $flatten\u_graph_engine.$procmux$2597_CMP $flatten\u_graph_engine.$procmux$2607_CMP $flatten\u_graph_engine.$procmux$2610_CMP $flatten\u_graph_engine.$procmux$2621_CMP $flatten\u_graph_engine.$procmux$2882_CMP }
transition: 4'0000 13'-----------00 -> 4'0000 17'00000000000000001
transition: 4'0000 13'-----------01 -> 4'0001 17'00010000000000001
transition: 4'0000 13'-----------1- -> 4'0000 17'00000000000000001
transition: 4'1000 13'-----------0- -> 4'1001 17'10010000000100000
transition: 4'1000 13'-----------1- -> 4'0000 17'00000000000100000
transition: 4'0100 13'----------00- -> 4'0100 17'01000100000000000
transition: 4'0100 13'--0-------10- -> 4'0011 17'00110100000000000
transition: 4'0100 13'--1-------10- -> 4'0101 17'01010100000000000
transition: 4'0100 13'-----------1- -> 4'0000 17'00000100000000000
transition: 4'1100 13'-----------00 -> 4'1100 17'11000000000000010
transition: 4'1100 13'-----------01 -> 4'0001 17'00010000000000010
transition: 4'1100 13'-----------1- -> 4'0000 17'00000000000000010
transition: 4'0010 13'----------00- -> 4'0010 17'00100000000001000
transition: 4'0010 13'-0--------10- -> 4'0001 17'00010000000001000
transition: 4'0010 13'-1--------10- -> 4'0011 17'00110000000001000
transition: 4'0010 13'-----------1- -> 4'0000 17'00000000000001000
transition: 4'1010 13'-----------0- -> 4'1011 17'10110001000000000
transition: 4'1010 13'-----------1- -> 4'0000 17'00000001000000000
transition: 4'0110 13'----------00- -> 4'0110 17'01101000000000000
transition: 4'0110 13'----0-----10- -> 4'0101 17'01011000000000000
transition: 4'0110 13'----10----10- -> 4'0111 17'01111000000000000
transition: 4'0110 13'----11----10- -> 4'1100 17'11001000000000000
transition: 4'0110 13'-----------1- -> 4'0000 17'00001000000000000
transition: 4'0001 13'-----------0- -> 4'0010 17'00100000001000000
transition: 4'0001 13'-----------1- -> 4'0000 17'00000000001000000
transition: 4'1001 13'---------0-0- -> 4'1001 17'10010000000010000
transition: 4'1001 13'0------0-1-0- -> 4'0011 17'00110000000010000
transition: 4'1001 13'0------1-1-0- -> 4'0000 17'00000000000010000
transition: 4'1001 13'1--------1-0- -> 4'1010 17'10100000000010000
transition: 4'1001 13'-----------1- -> 4'0000 17'00000000000010000
transition: 4'0101 13'---0-------0- -> 4'0110 17'01100000100000000
transition: 4'0101 13'---1-------0- -> 4'1100 17'11000000100000000
transition: 4'0101 13'-----------1- -> 4'0000 17'00000000100000000
transition: 4'0011 13'-----------0- -> 4'0100 17'01000000010000000
transition: 4'0011 13'-----------1- -> 4'0000 17'00000000010000000
transition: 4'1011 13'----------00- -> 4'1011 17'10110000000000100
transition: 4'1011 13'-------0--10- -> 4'0011 17'00110000000000100
transition: 4'1011 13'-------1--10- -> 4'0000 17'00000000000000100
transition: 4'1011 13'-----------1- -> 4'0000 17'00000000000000100
transition: 4'0111 13'------0----0- -> 4'0101 17'01010010000000000
transition: 4'0111 13'------1----0- -> 4'1000 17'10000010000000000
transition: 4'0111 13'-----------1- -> 4'0000 17'00000010000000000
Extracting FSM `\u_layer_sequencer.state' from module `\spi_neuron_top'.
found $dff cell for state register: $flatten\u_layer_sequencer.$procdff$5399
root of input selection tree: $flatten\u_layer_sequencer.$0\state[3:0]
found reset state: 4'0000 (guessed from mux tree)
found ctrl input: \rst
found ctrl input: $flatten\u_layer_sequencer.$procmux$3270_CMP
found ctrl input: $flatten\u_layer_sequencer.$procmux$3249_CMP
found ctrl input: $flatten\u_layer_sequencer.$procmux$3273_CMP
found ctrl input: $flatten\u_layer_sequencer.$procmux$3259_CMP
found ctrl input: $flatten\u_layer_sequencer.$procmux$3126_CMP
found ctrl input: $flatten\u_layer_sequencer.$procmux$3250_CMP
found ctrl input: $flatten\u_layer_sequencer.$procmux$3290_CMP
found state code: 4'0000
found ctrl input: \u_arbiter.c_ready
found ctrl input: $flatten\u_layer_sequencer.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:301$793_Y
found state code: 4'0101
found ctrl input: $flatten\u_layer_sequencer.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:303$795_Y
found state code: 4'0001
found state code: 4'0110
found ctrl input: \u_neuron_memory.done
found state code: 4'0100
found ctrl input: $flatten\u_layer_sequencer.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:235$782_Y
found state code: 4'0011
found state code: 4'0010
found ctrl input: \seq_run_start
found ctrl output: $flatten\u_layer_sequencer.$procmux$3290_CMP
found ctrl output: $flatten\u_layer_sequencer.$procmux$3273_CMP
found ctrl output: $flatten\u_layer_sequencer.$procmux$3270_CMP
found ctrl output: $flatten\u_layer_sequencer.$procmux$3259_CMP
found ctrl output: $flatten\u_layer_sequencer.$procmux$3250_CMP
found ctrl output: $flatten\u_layer_sequencer.$procmux$3249_CMP
found ctrl output: $flatten\u_layer_sequencer.$procmux$3126_CMP
ctrl inputs: { $flatten\u_layer_sequencer.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:235$782_Y $flatten\u_layer_sequencer.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:301$793_Y $flatten\u_layer_sequencer.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:303$795_Y \u_neuron_memory.done \u_arbiter.c_ready \seq_run_start \rst }
ctrl outputs: { $flatten\u_layer_sequencer.$0\state[3:0] $flatten\u_layer_sequencer.$procmux$3126_CMP $flatten\u_layer_sequencer.$procmux$3249_CMP $flatten\u_layer_sequencer.$procmux$3250_CMP $flatten\u_layer_sequencer.$procmux$3259_CMP $flatten\u_layer_sequencer.$procmux$3270_CMP $flatten\u_layer_sequencer.$procmux$3273_CMP $flatten\u_layer_sequencer.$procmux$3290_CMP }
transition: 4'0000 7'-----00 -> 4'0000 11'00000000001
transition: 4'0000 7'-----10 -> 4'0001 11'00010000001
transition: 4'0000 7'------1 -> 4'0000 11'00000000001
transition: 4'0100 7'---0--0 -> 4'0100 11'01000000010
transition: 4'0100 7'---1--0 -> 4'0101 11'01010000010
transition: 4'0100 7'------1 -> 4'0000 11'00000000010
transition: 4'0010 7'----0-0 -> 4'0010 11'00101000000
transition: 4'0010 7'0---1-0 -> 4'0001 11'00011000000
transition: 4'0010 7'1---1-0 -> 4'0011 11'00111000000
transition: 4'0010 7'------1 -> 4'0000 11'00001000000
transition: 4'0110 7'----0-0 -> 4'0110 11'01100000100
transition: 4'0110 7'-0--1-0 -> 4'0101 11'01010000100
transition: 4'0110 7'-10-1-0 -> 4'0001 11'00010000100
transition: 4'0110 7'-11-1-0 -> 4'0000 11'00000000100
transition: 4'0110 7'------1 -> 4'0000 11'00000000100
transition: 4'0001 7'------0 -> 4'0010 11'00100010000
transition: 4'0001 7'------1 -> 4'0000 11'00000010000
transition: 4'0101 7'------0 -> 4'0110 11'01100100000
transition: 4'0101 7'------1 -> 4'0000 11'00000100000
transition: 4'0011 7'------0 -> 4'0100 11'01000001000
transition: 4'0011 7'------1 -> 4'0000 11'00000001000
Extracting FSM `\u_neuron_memory.u_mem.state' from module `\spi_neuron_top'.
found $dff cell for state register: $flatten\u_neuron_memory.\u_mem.$procdff$5472
root of input selection tree: $flatten\u_neuron_memory.\u_mem.$0\state[1:0]
found reset state: 2'00 (guessed from mux tree)
found ctrl input: \graph_rst
found ctrl input: $flatten\u_neuron_memory.\u_mem.$procmux$4931_CMP
found ctrl input: $flatten\u_neuron_memory.\u_mem.$procmux$4923_CMP
found state code: 2'00
found ctrl input: \u_arbiter.b_ready
found ctrl input: \u_neuron_memory.access_req
found state code: 2'01
found ctrl output: $flatten\u_neuron_memory.\u_mem.$procmux$4931_CMP
found ctrl output: $flatten\u_neuron_memory.\u_mem.$procmux$4923_CMP
ctrl inputs: { \u_neuron_memory.access_req \u_arbiter.b_ready \graph_rst }
ctrl outputs: { $flatten\u_neuron_memory.\u_mem.$procmux$4931_CMP $flatten\u_neuron_memory.\u_mem.$procmux$4923_CMP $flatten\u_neuron_memory.\u_mem.$0\state[1:0] }
transition: 2'00 3'0-0 -> 2'00 4'0100
transition: 2'00 3'1-0 -> 2'01 4'0101
transition: 2'00 3'--1 -> 2'00 4'0100
transition: 2'01 3'-00 -> 2'01 4'1001
transition: 2'01 3'-10 -> 2'00 4'1000
transition: 2'01 3'--1 -> 2'00 4'1000
Extracting FSM `\u_arbiter.owner' from module `\spi_neuron_top'.
found $dff cell for state register: $flatten\u_arbiter.$procdff$5270
root of input selection tree: $flatten\u_arbiter.$0\owner[1:0]
found reset state: 2'00 (guessed from mux tree)
found ctrl input: \rst
found ctrl input: $flatten\u_arbiter.$procmux$1662_CMP
found ctrl input: $auto$opt_reduce.cc:137:opt_pmux$5629
found ctrl input: \u_neuron_memory.u_mem.mem_req
found ctrl input: \portc_req
found ctrl input: \u_spi_engine.ram_req
found state code: 2'01
found state code: 2'11
found state code: 2'10
found ctrl input: \u_int8_access.ready
found state code: 2'00
found ctrl output: $flatten\u_arbiter.$procmux$1662_CMP
found ctrl output: $flatten\u_arbiter.$procmux$1646_CMP
found ctrl output: $flatten\u_arbiter.$procmux$1637_CMP
found ctrl output: $flatten\u_arbiter.$procmux$1629_CMP
ctrl inputs: { \u_spi_engine.ram_req \u_neuron_memory.u_mem.mem_req \u_int8_access.ready \portc_req \rst $auto$opt_reduce.cc:137:opt_pmux$5629 }
ctrl outputs: { $flatten\u_arbiter.$0\owner[1:0] $flatten\u_arbiter.$procmux$1629_CMP $flatten\u_arbiter.$procmux$1637_CMP $flatten\u_arbiter.$procmux$1646_CMP $flatten\u_arbiter.$procmux$1662_CMP }
transition: 2'00 6'00-00- -> 2'00 6'000001
transition: 2'00 6'10-00- -> 2'01 6'010001
transition: 2'00 6'-0-10- -> 2'11 6'110001
transition: 2'00 6'-1--0- -> 2'10 6'100001
transition: 2'00 6'----1- -> 2'00 6'000001
transition: 2'10 6'--0-0- -> 2'10 6'100100
transition: 2'10 6'--1-0- -> 2'00 6'000100
transition: 2'10 6'----1- -> 2'00 6'000100
transition: 2'01 6'--0-0- -> 2'01 6'010010
transition: 2'01 6'--1-0- -> 2'00 6'000010
transition: 2'01 6'----1- -> 2'00 6'000010
transition: 2'11 6'--0-0- -> 2'11 6'111000
transition: 2'11 6'--1-0- -> 2'00 6'001000
transition: 2'11 6'----1- -> 2'00 6'001000
Extracting FSM `\u_spi_engine.resp_len' from module `\spi_neuron_top'.
found $dff cell for state register: $flatten\u_spi_engine.$procdff$5449
root of input selection tree: $flatten\u_spi_engine.$0\resp_len[3:0]
found reset state: 4'0000 (guessed from mux tree)
found ctrl input: \rst
found ctrl input: \u_spi_slave.cs_end
found ctrl input: $flatten\u_spi_engine.$procmux$3681_CMP
found ctrl input: \u_spi_slave.rx_valid
found ctrl input: $auto$opt_reduce.cc:137:opt_pmux$5605
found ctrl input: $flatten\u_spi_engine.$procmux$3846_CMP
found state code: 4'0001
found state code: 4'1011
found state code: 4'0000
ctrl inputs: { \u_spi_slave.rx_valid \u_spi_slave.cs_end $flatten\u_spi_engine.$procmux$3681_CMP $flatten\u_spi_engine.$procmux$3846_CMP \rst $auto$opt_reduce.cc:137:opt_pmux$5605 }
ctrl outputs: $flatten\u_spi_engine.$0\resp_len[3:0]
transition: 4'0000 6'-00-0- -> 4'0000 4'0000
transition: 4'0000 6'001-0- -> 4'0000 4'0000
transition: 4'0000 6'101000 -> 4'0000 4'0000
transition: 4'0000 6'10110- -> 4'1011 4'1011
transition: 4'0000 6'101-01 -> 4'0001 4'0001
transition: 4'0000 6'-1--0- -> 4'0000 4'0000
transition: 4'0000 6'----1- -> 4'0000 4'0000
transition: 4'0001 6'-00-0- -> 4'0001 4'0001
transition: 4'0001 6'001-0- -> 4'0001 4'0001
transition: 4'0001 6'101000 -> 4'0001 4'0001
transition: 4'0001 6'10110- -> 4'1011 4'1011
transition: 4'0001 6'101-01 -> 4'0001 4'0001
transition: 4'0001 6'-1--0- -> 4'0001 4'0001
transition: 4'0001 6'----1- -> 4'0000 4'0000
transition: 4'1011 6'-00-0- -> 4'1011 4'1011
transition: 4'1011 6'001-0- -> 4'1011 4'1011
transition: 4'1011 6'101000 -> 4'1011 4'1011
transition: 4'1011 6'10110- -> 4'1011 4'1011
transition: 4'1011 6'101-01 -> 4'0001 4'0001
transition: 4'1011 6'-1--0- -> 4'1011 4'1011
transition: 4'1011 6'----1- -> 4'0000 4'0000
Extracting FSM `\u_spi_engine.state' from module `\spi_neuron_top'.
found $dff cell for state register: $flatten\u_spi_engine.$procdff$5438
root of input selection tree: $flatten\u_spi_engine.$0\state[3:0]
found reset state: 4'0000 (guessed from mux tree)
found ctrl input: \rst
found ctrl input: \u_spi_slave.cs_end
found ctrl input: $flatten\u_spi_engine.$procmux$3681_CMP
found ctrl input: $flatten\u_spi_engine.$procmux$3650_CMP
found ctrl input: $flatten\u_spi_engine.$procmux$3617_CMP
found ctrl input: $flatten\u_spi_engine.$procmux$3608_CMP
found ctrl input: $flatten\u_spi_engine.$procmux$3911_CMP
found ctrl input: $flatten\u_spi_engine.$procmux$3732_CMP
found ctrl input: $flatten\u_spi_engine.$procmux$3932_CMP
found ctrl input: $flatten\u_spi_engine.$procmux$3731_CMP
found ctrl input: $flatten\u_spi_engine.$procmux$3891_CMP
found ctrl input: $flatten\u_spi_engine.$procmux$3929_CMP
found ctrl input: $auto$opt_reduce.cc:137:opt_pmux$5621
found ctrl input: $flatten\u_spi_engine.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:218$749_Y
found ctrl input: $flatten\u_spi_engine.$procmux$4086_CMP
found state code: 4'0000
found ctrl input: \u_spi_slave.rx_valid
found ctrl input: $flatten\u_spi_engine.$procmux$4017_CTRL
found ctrl input: $flatten\u_spi_engine.$procmux$4150_CMP
found ctrl input: $flatten\u_spi_engine.$procmux$4149_CMP
found ctrl input: $flatten\u_spi_engine.$procmux$4148_CMP
found ctrl input: $auto$opt_reduce.cc:137:opt_pmux$5603
found state code: 4'1011
found state code: 4'0010
found state code: 4'0001
found state code: 4'1100
found state code: 4'1101
found state code: 4'1010
found ctrl input: $flatten\u_spi_engine.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:489$762_Y
found ctrl input: $flatten\u_spi_engine.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:493$763_Y
found state code: 4'0011
found ctrl input: $flatten\u_spi_engine.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:540$765_Y
found ctrl input: $flatten\u_spi_engine.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:545$766_Y
found ctrl input: $flatten\u_spi_engine.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:549$767_Y
found state code: 4'0111
found state code: 4'0100
found state code: 4'0101
found state code: 4'0110
found ctrl input: \u_arbiter.a_ready
found ctrl input: $flatten\u_spi_engine.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:601$771_Y
found state code: 4'1000
found state code: 4'1001
found ctrl input: $flatten\u_spi_engine.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:707$778_Y
found ctrl output: $flatten\u_spi_engine.$procmux$3732_CMP
found ctrl output: $flatten\u_spi_engine.$procmux$3731_CMP
found ctrl output: $flatten\u_spi_engine.$procmux$4095_CMP
found ctrl output: $flatten\u_spi_engine.$procmux$4086_CMP
found ctrl output: $flatten\u_spi_engine.$procmux$3650_CMP
found ctrl output: $flatten\u_spi_engine.$procmux$3782_CMP
found ctrl output: $flatten\u_spi_engine.$procmux$3608_CMP
found ctrl output: $flatten\u_spi_engine.$procmux$3617_CMP
found ctrl output: $flatten\u_spi_engine.$procmux$3932_CMP
found ctrl output: $flatten\u_spi_engine.$procmux$3929_CMP
found ctrl output: $flatten\u_spi_engine.$procmux$3911_CMP
found ctrl output: $flatten\u_spi_engine.$procmux$3891_CMP
found ctrl output: $flatten\u_spi_engine.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:218$749_Y
found ctrl output: $flatten\u_spi_engine.$procmux$3681_CMP
ctrl inputs: { \u_spi_slave.rx_valid \u_spi_slave.cs_end $flatten\u_spi_engine.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:489$762_Y $flatten\u_spi_engine.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:493$763_Y $flatten\u_spi_engine.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:540$765_Y $flatten\u_spi_engine.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:545$766_Y $flatten\u_spi_engine.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:549$767_Y $flatten\u_spi_engine.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:601$771_Y $flatten\u_spi_engine.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:707$778_Y $flatten\u_spi_engine.$procmux$4017_CTRL $flatten\u_spi_engine.$procmux$4148_CMP $flatten\u_spi_engine.$procmux$4149_CMP $flatten\u_spi_engine.$procmux$4150_CMP \u_arbiter.a_ready \rst $auto$opt_reduce.cc:137:opt_pmux$5603 $auto$opt_reduce.cc:137:opt_pmux$5621 }
ctrl outputs: { $flatten\u_spi_engine.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:218$749_Y $flatten\u_spi_engine.$0\state[3:0] $flatten\u_spi_engine.$procmux$3608_CMP $flatten\u_spi_engine.$procmux$3617_CMP $flatten\u_spi_engine.$procmux$3650_CMP $flatten\u_spi_engine.$procmux$3681_CMP $flatten\u_spi_engine.$procmux$3731_CMP $flatten\u_spi_engine.$procmux$3732_CMP $flatten\u_spi_engine.$procmux$3782_CMP $flatten\u_spi_engine.$procmux$3891_CMP $flatten\u_spi_engine.$procmux$3911_CMP $flatten\u_spi_engine.$procmux$3929_CMP $flatten\u_spi_engine.$procmux$3932_CMP $flatten\u_spi_engine.$procmux$4086_CMP $flatten\u_spi_engine.$procmux$4095_CMP }
transition: 4'0000 17'00------------0-- -> 4'0000 18'000000001000000000
transition: 4'0000 17'10-------0000-00- -> 4'1011 18'010110001000000000
transition: 4'0000 17'10------------01- -> 4'1010 18'010100001000000000
transition: 4'0000 17'10--------1---0-- -> 4'1101 18'011010001000000000
transition: 4'0000 17'10---------1--0-- -> 4'1100 18'011000001000000000
transition: 4'0000 17'10----------1-0-- -> 4'0001 18'000010001000000000
transition: 4'0000 17'10-------1----0-- -> 4'0010 18'000100001000000000
transition: 4'0000 17'-1------------0-- -> 4'0000 18'000000001000000000
transition: 4'0000 17'--------------1-- -> 4'0000 18'000000001000000000
transition: 4'1000 17'-0-----------00-- -> 4'1000 18'010000000000100000
transition: 4'1000 17'-0-----------10-- -> 4'1001 18'010010000000100000
transition: 4'1000 17'-1------------0-- -> 4'0000 18'000000000000100000
transition: 4'1000 17'--------------1-- -> 4'0000 18'000000000000100000
transition: 4'0100 17'00------------0-- -> 4'0100 18'001000000000010000
transition: 4'0100 17'10------------0-- -> 4'0101 18'001010000000010000
transition: 4'0100 17'-1------------0-- -> 4'0000 18'000000000000010000
transition: 4'0100 17'--------------1-- -> 4'0000 18'000000000000010000
transition: 4'1100 17'00------------0-- -> 4'1100 18'011000000001000000
transition: 4'1100 17'10------------0-- -> 4'1011 18'010110000001000000
transition: 4'1100 17'-1------------0-- -> 4'0000 18'000000000001000000
transition: 4'1100 17'--------------1-- -> 4'0000 18'000000000001000000
transition: 4'0010 17'00------------0-- -> 4'0010 18'000100100000000000
transition: 4'0010 17'100-----------0-- -> 4'0010 18'000100100000000000
transition: 4'0010 17'1010----------0-- -> 4'0011 18'000110100000000000
transition: 4'0010 17'1011----------0-- -> 4'1011 18'010110100000000000
transition: 4'0010 17'-1------------0-- -> 4'0000 18'000000100000000000
transition: 4'0010 17'--------------1-- -> 4'0000 18'000000100000000000
transition: 4'1010 17'00------------0-- -> 4'1010 18'110100000000000000
transition: 4'1010 17'10------0-----0-- -> 4'1010 18'110100000000000000
transition: 4'1010 17'10------1-----0-- -> 4'1011 18'110110000000000000
transition: 4'1010 17'-1------------0-- -> 4'0000 18'100000000000000000
transition: 4'1010 17'--------------1-- -> 4'0000 18'100000000000000000
transition: 4'0110 17'-0-----------00-- -> 4'0110 18'001100000000000100
transition: 4'0110 17'-0-----0-----10-- -> 4'0100 18'001000000000000100
transition: 4'0110 17'-0-----1-----10-- -> 4'1011 18'010110000000000100
transition: 4'0110 17'-1------------0-- -> 4'0000 18'000000000000000100
transition: 4'0110 17'--------------1-- -> 4'0000 18'000000000000000100
transition: 4'0001 17'00------------0-- -> 4'0001 18'000010010000000000
transition: 4'0001 17'10------------0-- -> 4'0010 18'000100010000000000
transition: 4'0001 17'-1------------0-- -> 4'0000 18'000000010000000000
transition: 4'0001 17'--------------1-- -> 4'0000 18'000000010000000000
transition: 4'1001 17'00------------0-- -> 4'1001 18'010010000000001000
transition: 4'1001 17'10-----0------0-- -> 4'0111 18'001110000000001000
transition: 4'1001 17'10-----1------0-- -> 4'1011 18'010110000000001000
transition: 4'1001 17'-1------------0-- -> 4'0000 18'000000000000001000
transition: 4'1001 17'--------------1-- -> 4'0000 18'000000000000001000
transition: 4'0101 17'-0------------0-- -> 4'0110 18'001100000010000000
transition: 4'0101 17'-1------------0-- -> 4'0000 18'000000000010000000
transition: 4'0101 17'--------------1-- -> 4'0000 18'000000000010000000
transition: 4'1101 17'00------------0-- -> 4'1101 18'011010000000000001
transition: 4'1101 17'10------------0-- -> 4'1011 18'010110000000000001
transition: 4'1101 17'-1------------0-- -> 4'0000 18'000000000000000001
transition: 4'1101 17'--------------1-- -> 4'0000 18'000000000000000001
transition: 4'0011 17'00------------0-- -> 4'0011 18'000111000000000000
transition: 4'0011 17'10--0---------0-- -> 4'0011 18'000111000000000000
transition: 4'0011 17'10--100-------0-- -> 4'0111 18'001111000000000000
transition: 4'0011 17'10--101-------0-- -> 4'0100 18'001001000000000000
transition: 4'0011 17'10--11--------0-- -> 4'1011 18'010111000000000000
transition: 4'0011 17'-1------------0-- -> 4'0000 18'000001000000000000
transition: 4'0011 17'--------------1-- -> 4'0000 18'000001000000000000
transition: 4'1011 17'-0------------0-- -> 4'1011 18'010110000000000010
transition: 4'1011 17'-1------------0-- -> 4'0000 18'000000000000000010
transition: 4'1011 17'--------------1-- -> 4'0000 18'000000000000000010
transition: 4'0111 17'-0------------0-- -> 4'1000 18'010000000100000000
transition: 4'0111 17'-1------------0-- -> 4'0000 18'000000000100000000
transition: 4'0111 17'--------------1-- -> 4'0000 18'000000000100000000
Extracting FSM `\u_int8_access.state' from module `\spi_neuron_top'.
found $dff cell for state register: $flatten\u_int8_access.$procdff$5472
root of input selection tree: $flatten\u_int8_access.$0\state[1:0]
found reset state: 2'00 (guessed from mux tree)
found ctrl input: \rst
found ctrl input: $flatten\u_int8_access.$procmux$4931_CMP
found ctrl input: $flatten\u_int8_access.$procmux$4923_CMP
found state code: 2'00
found ctrl input: \u_memory_if.ready
found ctrl input: \u_arbiter.m_req
found state code: 2'01
found ctrl output: $flatten\u_int8_access.$procmux$4931_CMP
found ctrl output: $flatten\u_int8_access.$procmux$4923_CMP
ctrl inputs: { \u_arbiter.m_req \u_memory_if.ready \rst }
ctrl outputs: { $flatten\u_int8_access.$0\state[1:0] $flatten\u_int8_access.$procmux$4923_CMP $flatten\u_int8_access.$procmux$4931_CMP }
transition: 2'00 3'0-0 -> 2'00 4'0010
transition: 2'00 3'1-0 -> 2'01 4'0110
transition: 2'00 3'--1 -> 2'00 4'0010
transition: 2'01 3'-00 -> 2'01 4'0101
transition: 2'01 3'-10 -> 2'00 4'0001
transition: 2'01 3'--1 -> 2'00 4'0001
Extracting FSM `\u_memory_if.state' from module `\spi_neuron_top'.
found $dff cell for state register: $flatten\u_memory_if.$procdff$5251
root of input selection tree: $flatten\u_memory_if.$0\state[1:0]
found reset state: 2'00 (guessed from mux tree)
found ctrl input: \rst
found ctrl input: $flatten\u_memory_if.$procmux$1556_CMP
found ctrl input: $flatten\u_memory_if.$procmux$1548_CMP
found state code: 2'00
found ctrl input: \u_psram_ctrl.mem_ready
found ctrl input: \u_int8_access.mem_req
found state code: 2'01
found ctrl output: $flatten\u_memory_if.$procmux$1556_CMP
found ctrl output: $flatten\u_memory_if.$procmux$1548_CMP
ctrl inputs: { \u_int8_access.mem_req \u_psram_ctrl.mem_ready \rst }
ctrl outputs: { $flatten\u_memory_if.$0\state[1:0] $flatten\u_memory_if.$procmux$1548_CMP $flatten\u_memory_if.$procmux$1556_CMP }
transition: 2'00 3'0-0 -> 2'00 4'0010
transition: 2'00 3'1-0 -> 2'01 4'0110
transition: 2'00 3'--1 -> 2'00 4'0010
transition: 2'01 3'-00 -> 2'01 4'0101
transition: 2'01 3'-10 -> 2'00 4'0001
transition: 2'01 3'--1 -> 2'00 4'0001
Extracting FSM `\u_psram_ctrl.state' from module `\spi_neuron_top'.
found $dff cell for state register: $flatten\u_psram_ctrl.$procdff$5454
root of input selection tree: $flatten\u_psram_ctrl.$0\state[2:0]
found reset state: 3'000 (guessed from mux tree)
found ctrl input: \rst
found ctrl input: $flatten\u_psram_ctrl.$procmux$4772_CMP
found ctrl input: $flatten\u_psram_ctrl.$procmux$4677_CMP
found ctrl input: $flatten\u_psram_ctrl.$procmux$4702_CMP
found ctrl input: $flatten\u_psram_ctrl.$procmux$4683_CMP
found ctrl input: $flatten\u_psram_ctrl.$procmux$4802_CMP
found state code: 3'000
found state code: 3'001
found ctrl input: $flatten\u_psram_ctrl.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/psram_controller.v:292$1245_Y
found state code: 3'100
found ctrl input: \u_memory_if.mem_req
found ctrl input: \u_memory_if.mem_wr
found state code: 3'010
found state code: 3'011
found ctrl input: $flatten\u_psram_ctrl.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/psram_controller.v:179$1243_Y
found ctrl output: $flatten\u_psram_ctrl.$procmux$4802_CMP
found ctrl output: $flatten\u_psram_ctrl.$procmux$4772_CMP
found ctrl output: $flatten\u_psram_ctrl.$procmux$4702_CMP
found ctrl output: $flatten\u_psram_ctrl.$procmux$4683_CMP
found ctrl output: $flatten\u_psram_ctrl.$procmux$4677_CMP
ctrl inputs: { \u_memory_if.mem_req \u_memory_if.mem_wr $flatten\u_psram_ctrl.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/psram_controller.v:179$1243_Y $flatten\u_psram_ctrl.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/psram_controller.v:292$1245_Y \rst }
ctrl outputs: { $flatten\u_psram_ctrl.$0\state[2:0] $flatten\u_psram_ctrl.$procmux$4677_CMP $flatten\u_psram_ctrl.$procmux$4683_CMP $flatten\u_psram_ctrl.$procmux$4702_CMP $flatten\u_psram_ctrl.$procmux$4772_CMP $flatten\u_psram_ctrl.$procmux$4802_CMP }
transition: 3'000 5'--0-0 -> 3'000 8'00000001
transition: 3'000 5'--1-0 -> 3'001 8'00100001
transition: 3'000 5'----1 -> 3'000 8'00000001
transition: 3'100 5'----0 -> 3'001 8'00100010
transition: 3'100 5'----1 -> 3'000 8'00000010
transition: 3'010 5'---00 -> 3'010 8'01000100
transition: 3'010 5'---10 -> 3'001 8'00100100
transition: 3'010 5'----1 -> 3'000 8'00000100
transition: 3'001 5'0---0 -> 3'001 8'00101000
transition: 3'001 5'10--0 -> 3'010 8'01001000
transition: 3'001 5'11--0 -> 3'011 8'01101000
transition: 3'001 5'----1 -> 3'000 8'00001000
transition: 3'011 5'---00 -> 3'011 8'01110000
transition: 3'011 5'---10 -> 3'100 8'10010000
transition: 3'011 5'----1 -> 3'000 8'00010000
17.13.3. Executing FSM_OPT pass (simple optimizations of FSMs).
Optimizing FSM `$fsm$\u_psram_ctrl.state$5700' from module `\spi_neuron_top'.
Optimizing FSM `$fsm$\u_memory_if.state$5696' from module `\spi_neuron_top'.
Optimizing FSM `$fsm$\u_int8_access.state$5692' from module `\spi_neuron_top'.
Optimizing FSM `$fsm$\u_spi_engine.state$5676' from module `\spi_neuron_top'.
Removing unused input signal $auto$opt_reduce.cc:137:opt_pmux$5621.
Optimizing FSM `$fsm$\u_spi_engine.resp_len$5674' from module `\spi_neuron_top'.
Optimizing FSM `$fsm$\u_arbiter.owner$5668' from module `\spi_neuron_top'.
Removing unused input signal $auto$opt_reduce.cc:137:opt_pmux$5629.
Optimizing FSM `$fsm$\u_neuron_memory.u_mem.state$5664' from module `\spi_neuron_top'.
Optimizing FSM `$fsm$\u_layer_sequencer.state$5655' from module `\spi_neuron_top'.
Optimizing FSM `$fsm$\u_graph_engine.state$5640' from module `\spi_neuron_top'.
Removing unused input signal $flatten\u_graph_engine.$procmux$2882_CTRL.
Optimizing FSM `$fsm$\u_neuron_memory.state$5632' from module `\spi_neuron_top'.
17.13.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \spi_neuron_top..
Removed 153 unused cells and 153 unused wires.
<suppressed ~154 debug messages>
17.13.5. Executing FSM_OPT pass (simple optimizations of FSMs).
Optimizing FSM `$fsm$\u_memory_if.state$5696' from module `\spi_neuron_top'.
Removing unused output signal $flatten\u_memory_if.$0\state[1:0] [0].
Removing unused output signal $flatten\u_memory_if.$0\state[1:0] [1].
Optimizing FSM `$fsm$\u_psram_ctrl.state$5700' from module `\spi_neuron_top'.
Removing unused output signal $flatten\u_psram_ctrl.$0\state[2:0] [0].
Removing unused output signal $flatten\u_psram_ctrl.$0\state[2:0] [1].
Removing unused output signal $flatten\u_psram_ctrl.$0\state[2:0] [2].
Optimizing FSM `$fsm$\u_neuron_memory.state$5632' from module `\spi_neuron_top'.
Removing unused output signal $flatten\u_neuron_memory.$0\state[3:0] [0].
Removing unused output signal $flatten\u_neuron_memory.$0\state[3:0] [1].
Removing unused output signal $flatten\u_neuron_memory.$0\state[3:0] [2].
Removing unused output signal $flatten\u_neuron_memory.$0\state[3:0] [3].
Optimizing FSM `$fsm$\u_graph_engine.state$5640' from module `\spi_neuron_top'.
Removing unused output signal $flatten\u_graph_engine.$0\state[3:0] [0].
Removing unused output signal $flatten\u_graph_engine.$0\state[3:0] [1].
Removing unused output signal $flatten\u_graph_engine.$0\state[3:0] [2].
Removing unused output signal $flatten\u_graph_engine.$0\state[3:0] [3].
Optimizing FSM `$fsm$\u_layer_sequencer.state$5655' from module `\spi_neuron_top'.
Removing unused output signal $flatten\u_layer_sequencer.$0\state[3:0] [0].
Removing unused output signal $flatten\u_layer_sequencer.$0\state[3:0] [1].
Removing unused output signal $flatten\u_layer_sequencer.$0\state[3:0] [2].
Removing unused output signal $flatten\u_layer_sequencer.$0\state[3:0] [3].
Optimizing FSM `$fsm$\u_neuron_memory.u_mem.state$5664' from module `\spi_neuron_top'.
Removing unused output signal $flatten\u_neuron_memory.\u_mem.$0\state[1:0] [0].
Removing unused output signal $flatten\u_neuron_memory.\u_mem.$0\state[1:0] [1].
Optimizing FSM `$fsm$\u_arbiter.owner$5668' from module `\spi_neuron_top'.
Removing unused output signal $flatten\u_arbiter.$0\owner[1:0] [0].
Removing unused output signal $flatten\u_arbiter.$0\owner[1:0] [1].
Optimizing FSM `$fsm$\u_spi_engine.resp_len$5674' from module `\spi_neuron_top'.
Optimizing FSM `$fsm$\u_spi_engine.state$5676' from module `\spi_neuron_top'.
Removing unused output signal $flatten\u_spi_engine.$procmux$4086_CMP.
Removing unused output signal $flatten\u_spi_engine.$0\state[3:0] [0].
Removing unused output signal $flatten\u_spi_engine.$0\state[3:0] [1].
Removing unused output signal $flatten\u_spi_engine.$0\state[3:0] [2].
Removing unused output signal $flatten\u_spi_engine.$0\state[3:0] [3].
Optimizing FSM `$fsm$\u_int8_access.state$5692' from module `\spi_neuron_top'.
Removing unused output signal $flatten\u_int8_access.$0\state[1:0] [0].
Removing unused output signal $flatten\u_int8_access.$0\state[1:0] [1].
17.13.6. Executing FSM_RECODE pass (re-assigning FSM state encoding).
Recoding FSM `$fsm$\u_memory_if.state$5696' from module `\spi_neuron_top' using `auto' encoding:
mapping auto encoding to `one-hot` for this FSM.
00 -> -1
01 -> 1-
Recoding FSM `$fsm$\u_psram_ctrl.state$5700' from module `\spi_neuron_top' using `auto' encoding:
mapping auto encoding to `one-hot` for this FSM.
000 -> ----1
100 -> ---1-
010 -> --1--
001 -> -1---
011 -> 1----
Recoding FSM `$fsm$\u_neuron_memory.state$5632' from module `\spi_neuron_top' using `auto' encoding:
mapping auto encoding to `one-hot` for this FSM.
0000 -> -----1
0100 -> ----1-
0010 -> ---1--
0001 -> --1---
0101 -> -1----
0011 -> 1-----
Recoding FSM `$fsm$\u_graph_engine.state$5640' from module `\spi_neuron_top' using `auto' encoding:
mapping auto encoding to `one-hot` for this FSM.
0000 -> ------------1
1000 -> -----------1-
0100 -> ----------1--
1100 -> ---------1---
0010 -> --------1----
1010 -> -------1-----
0110 -> ------1------
0001 -> -----1-------
1001 -> ----1--------
0101 -> ---1---------
0011 -> --1----------
1011 -> -1-----------
0111 -> 1------------
Recoding FSM `$fsm$\u_layer_sequencer.state$5655' from module `\spi_neuron_top' using `auto' encoding:
mapping auto encoding to `one-hot` for this FSM.
0000 -> ------1
0100 -> -----1-
0010 -> ----1--
0110 -> ---1---
0001 -> --1----
0101 -> -1-----
0011 -> 1------
Recoding FSM `$fsm$\u_neuron_memory.u_mem.state$5664' from module `\spi_neuron_top' using `auto' encoding:
mapping auto encoding to `one-hot` for this FSM.
00 -> -1
01 -> 1-
Recoding FSM `$fsm$\u_arbiter.owner$5668' from module `\spi_neuron_top' using `auto' encoding:
mapping auto encoding to `one-hot` for this FSM.
00 -> ---1
10 -> --1-
01 -> -1--
11 -> 1---
Recoding FSM `$fsm$\u_spi_engine.resp_len$5674' from module `\spi_neuron_top' using `auto' encoding:
mapping auto encoding to `one-hot` for this FSM.
0000 -> --1
0001 -> -1-
1011 -> 1--
Recoding FSM `$fsm$\u_spi_engine.state$5676' from module `\spi_neuron_top' using `auto' encoding:
mapping auto encoding to `one-hot` for this FSM.
0000 -> -------------1
1000 -> ------------1-
0100 -> -----------1--
1100 -> ----------1---
0010 -> ---------1----
1010 -> --------1-----
0110 -> -------1------
0001 -> ------1-------
1001 -> -----1--------
0101 -> ----1---------
1101 -> ---1----------
0011 -> --1-----------
1011 -> -1------------
0111 -> 1-------------
Recoding FSM `$fsm$\u_int8_access.state$5692' from module `\spi_neuron_top' using `auto' encoding:
mapping auto encoding to `one-hot` for this FSM.
00 -> -1
01 -> 1-
17.13.7. Executing FSM_INFO pass (dumping all available information on FSM cells).
FSM `$fsm$\u_memory_if.state$5696' from module `spi_neuron_top':
-------------------------------------
Information on FSM $fsm$\u_memory_if.state$5696 (\u_memory_if.state):
Number of input signals: 3
Number of output signals: 2
Number of state bits: 2
Input signals:
0: \rst
1: \u_psram_ctrl.mem_ready
2: \u_int8_access.mem_req
Output signals:
0: $flatten\u_memory_if.$procmux$1556_CMP
1: $flatten\u_memory_if.$procmux$1548_CMP
State encoding:
0: 2'-1 <RESET STATE>
1: 2'1-
Transition Table (state_in, ctrl_in, state_out, ctrl_out):
0: 0 3'0-0 -> 0 2'10
1: 0 3'--1 -> 0 2'10
2: 0 3'1-0 -> 1 2'10
3: 1 3'-10 -> 0 2'01
4: 1 3'--1 -> 0 2'01
5: 1 3'-00 -> 1 2'01
-------------------------------------
FSM `$fsm$\u_psram_ctrl.state$5700' from module `spi_neuron_top':
-------------------------------------
Information on FSM $fsm$\u_psram_ctrl.state$5700 (\u_psram_ctrl.state):
Number of input signals: 5
Number of output signals: 5
Number of state bits: 5
Input signals:
0: \rst
1: $flatten\u_psram_ctrl.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/psram_controller.v:292$1245_Y
2: $flatten\u_psram_ctrl.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/psram_controller.v:179$1243_Y
3: \u_memory_if.mem_wr
4: \u_memory_if.mem_req
Output signals:
0: $flatten\u_psram_ctrl.$procmux$4802_CMP
1: $flatten\u_psram_ctrl.$procmux$4772_CMP
2: $flatten\u_psram_ctrl.$procmux$4702_CMP
3: $flatten\u_psram_ctrl.$procmux$4683_CMP
4: $flatten\u_psram_ctrl.$procmux$4677_CMP
State encoding:
0: 5'----1 <RESET STATE>
1: 5'---1-
2: 5'--1--
3: 5'-1---
4: 5'1----
Transition Table (state_in, ctrl_in, state_out, ctrl_out):
0: 0 5'--0-0 -> 0 5'00001
1: 0 5'----1 -> 0 5'00001
2: 0 5'--1-0 -> 3 5'00001
3: 1 5'----1 -> 0 5'00010
4: 1 5'----0 -> 3 5'00010
5: 2 5'----1 -> 0 5'00100
6: 2 5'---00 -> 2 5'00100
7: 2 5'---10 -> 3 5'00100
8: 3 5'----1 -> 0 5'01000
9: 3 5'10--0 -> 2 5'01000
10: 3 5'0---0 -> 3 5'01000
11: 3 5'11--0 -> 4 5'01000
12: 4 5'----1 -> 0 5'10000
13: 4 5'---10 -> 1 5'10000
14: 4 5'---00 -> 4 5'10000
-------------------------------------
FSM `$fsm$\u_neuron_memory.state$5632' from module `spi_neuron_top':
-------------------------------------
Information on FSM $fsm$\u_neuron_memory.state$5632 (\u_neuron_memory.state):
Number of input signals: 6
Number of output signals: 6
Number of state bits: 6
Input signals:
0: \graph_rst
1: \mux_nm_start
2: \u_neuron_memory.u_neuron.done
3: \u_neuron_memory.u_mem.ready
4: $flatten\u_neuron_memory.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:451$1168_Y
5: $flatten\u_neuron_memory.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:359$1152_Y
Output signals:
0: $flatten\u_neuron_memory.$procmux$2157_CMP
1: $flatten\u_neuron_memory.$procmux$1985_CMP
2: $flatten\u_neuron_memory.$procmux$1958_CMP
3: $flatten\u_neuron_memory.$procmux$1832_CMP
4: $flatten\u_neuron_memory.$procmux$1795_CMP
5: $flatten\u_neuron_memory.$procmux$1765_CMP
State encoding:
0: 6'-----1 <RESET STATE>
1: 6'----1-
2: 6'---1--
3: 6'--1---
4: 6'-1----
5: 6'1-----
Transition Table (state_in, ctrl_in, state_out, ctrl_out):
0: 0 6'----00 -> 0 6'000010
1: 0 6'-----1 -> 0 6'000010
2: 0 6'----10 -> 3 6'000010
3: 1 6'-----1 -> 0 6'000100
4: 1 6'-----0 -> 4 6'000100
5: 2 6'-----1 -> 0 6'010000
6: 2 6'--0--0 -> 2 6'010000
7: 2 6'0-1--0 -> 2 6'010000
8: 2 6'1-1--0 -> 5 6'010000
9: 3 6'-----1 -> 0 6'001000
10: 3 6'1-1--0 -> 2 6'001000
11: 3 6'--0--0 -> 3 6'001000
12: 3 6'0-1--0 -> 3 6'001000
13: 4 6'-1-1-0 -> 0 6'100000
14: 4 6'-----1 -> 0 6'100000
15: 4 6'-0-1-0 -> 2 6'100000
16: 4 6'---0-0 -> 4 6'100000
17: 5 6'-----1 -> 0 6'000001
18: 5 6'--1--0 -> 1 6'000001
19: 5 6'--0--0 -> 5 6'000001
-------------------------------------
FSM `$fsm$\u_graph_engine.state$5640' from module `spi_neuron_top':
-------------------------------------
Information on FSM $fsm$\u_graph_engine.state$5640 (\u_graph_engine.state):
Number of input signals: 12
Number of output signals: 13
Number of state bits: 13
Input signals:
0: \graph_run_start
1: \graph_rst
2: \u_arbiter.c_ready
3: \u_graph_engine.u_neuron.done
4: $flatten\u_graph_engine.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:527$1041_Y
5: $flatten\u_graph_engine.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:498$1038_Y
6: $flatten\u_graph_engine.$logic_or$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:456$1035_Y
7: $flatten\u_graph_engine.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:449$1030_Y
8: $flatten\u_graph_engine.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:420$1026_Y
9: $flatten\u_graph_engine.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:389$1021_Y
10: $flatten\u_graph_engine.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:346$1018_Y
11: \u_graph_engine.is_output_sink
Output signals:
0: $flatten\u_graph_engine.$procmux$2882_CMP [0]
1: $flatten\u_graph_engine.$procmux$2882_CMP [1]
2: $flatten\u_graph_engine.$procmux$2621_CMP
3: $flatten\u_graph_engine.$procmux$2610_CMP
4: $flatten\u_graph_engine.$procmux$2607_CMP
5: $flatten\u_graph_engine.$procmux$2597_CMP
6: $flatten\u_graph_engine.$procmux$2588_CMP
7: $flatten\u_graph_engine.$procmux$2587_CMP
8: $flatten\u_graph_engine.$procmux$2586_CMP
9: $flatten\u_graph_engine.$procmux$2582_CMP
10: $flatten\u_graph_engine.$procmux$2340_CMP
11: $flatten\u_graph_engine.$procmux$2261_CMP
12: $flatten\u_graph_engine.$procmux$2226_CMP
State encoding:
0: 13'------------1 <RESET STATE>
1: 13'-----------1-
2: 13'----------1--
3: 13'---------1---
4: 13'--------1----
5: 13'-------1-----
6: 13'------1------
7: 13'-----1-------
8: 13'----1--------
9: 13'---1---------
10: 13'--1----------
11: 13'-1-----------
12: 13'1------------
Transition Table (state_in, ctrl_in, state_out, ctrl_out):
0: 0 12'----------00 -> 0 13'0000000000001
1: 0 12'----------1- -> 0 13'0000000000001
2: 0 12'----------01 -> 7 13'0000000000001
3: 1 12'----------1- -> 0 13'0000000100000
4: 1 12'----------0- -> 8 13'0000000100000
5: 2 12'----------1- -> 0 13'0100000000000
6: 2 12'---------00- -> 2 13'0100000000000
7: 2 12'--1------10- -> 9 13'0100000000000
8: 2 12'--0------10- -> 10 13'0100000000000
9: 3 12'----------1- -> 0 13'0000000000010
10: 3 12'----------00 -> 3 13'0000000000010
11: 3 12'----------01 -> 7 13'0000000000010
12: 4 12'----------1- -> 0 13'0000000001000
13: 4 12'---------00- -> 4 13'0000000001000
14: 4 12'-0-------10- -> 7 13'0000000001000
15: 4 12'-1-------10- -> 10 13'0000000001000
16: 5 12'----------1- -> 0 13'0001000000000
17: 5 12'----------0- -> 11 13'0001000000000
18: 6 12'----------1- -> 0 13'1000000000000
19: 6 12'----11---10- -> 3 13'1000000000000
20: 6 12'---------00- -> 6 13'1000000000000
21: 6 12'----0----10- -> 9 13'1000000000000
22: 6 12'----10---10- -> 12 13'1000000000000
23: 7 12'----------1- -> 0 13'0000001000000
24: 7 12'----------0- -> 4 13'0000001000000
25: 8 12'0------11-0- -> 0 13'0000000010000
26: 8 12'----------1- -> 0 13'0000000010000
27: 8 12'1-------1-0- -> 5 13'0000000010000
28: 8 12'--------0-0- -> 8 13'0000000010000
29: 8 12'0------01-0- -> 10 13'0000000010000
30: 9 12'----------1- -> 0 13'0000100000000
31: 9 12'---1------0- -> 3 13'0000100000000
32: 9 12'---0------0- -> 6 13'0000100000000
33: 10 12'----------1- -> 0 13'0000010000000
34: 10 12'----------0- -> 2 13'0000010000000
35: 11 12'-------1-10- -> 0 13'0000000000100
36: 11 12'----------1- -> 0 13'0000000000100
37: 11 12'-------0-10- -> 10 13'0000000000100
38: 11 12'---------00- -> 11 13'0000000000100
39: 12 12'----------1- -> 0 13'0010000000000
40: 12 12'------1---0- -> 1 13'0010000000000
41: 12 12'------0---0- -> 9 13'0010000000000
-------------------------------------
FSM `$fsm$\u_layer_sequencer.state$5655' from module `spi_neuron_top':
-------------------------------------
Information on FSM $fsm$\u_layer_sequencer.state$5655 (\u_layer_sequencer.state):
Number of input signals: 7
Number of output signals: 7
Number of state bits: 7
Input signals:
0: \rst
1: \seq_run_start
2: \u_arbiter.c_ready
3: \u_neuron_memory.done
4: $flatten\u_layer_sequencer.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:303$795_Y
5: $flatten\u_layer_sequencer.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:301$793_Y
6: $flatten\u_layer_sequencer.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:235$782_Y
Output signals:
0: $flatten\u_layer_sequencer.$procmux$3290_CMP
1: $flatten\u_layer_sequencer.$procmux$3273_CMP
2: $flatten\u_layer_sequencer.$procmux$3270_CMP
3: $flatten\u_layer_sequencer.$procmux$3259_CMP
4: $flatten\u_layer_sequencer.$procmux$3250_CMP
5: $flatten\u_layer_sequencer.$procmux$3249_CMP
6: $flatten\u_layer_sequencer.$procmux$3126_CMP
State encoding:
0: 7'------1 <RESET STATE>
1: 7'-----1-
2: 7'----1--
3: 7'---1---
4: 7'--1----
5: 7'-1-----
6: 7'1------
Transition Table (state_in, ctrl_in, state_out, ctrl_out):
0: 0 7'-----00 -> 0 7'0000001
1: 0 7'------1 -> 0 7'0000001
2: 0 7'-----10 -> 4 7'0000001
3: 1 7'------1 -> 0 7'0000010
4: 1 7'---0--0 -> 1 7'0000010
5: 1 7'---1--0 -> 5 7'0000010
6: 2 7'------1 -> 0 7'1000000
7: 2 7'----0-0 -> 2 7'1000000
8: 2 7'0---1-0 -> 4 7'1000000
9: 2 7'1---1-0 -> 6 7'1000000
10: 3 7'-11-1-0 -> 0 7'0000100
11: 3 7'------1 -> 0 7'0000100
12: 3 7'----0-0 -> 3 7'0000100
13: 3 7'-10-1-0 -> 4 7'0000100
14: 3 7'-0--1-0 -> 5 7'0000100
15: 4 7'------1 -> 0 7'0010000
16: 4 7'------0 -> 2 7'0010000
17: 5 7'------1 -> 0 7'0100000
18: 5 7'------0 -> 3 7'0100000
19: 6 7'------1 -> 0 7'0001000
20: 6 7'------0 -> 1 7'0001000
-------------------------------------
FSM `$fsm$\u_neuron_memory.u_mem.state$5664' from module `spi_neuron_top':
-------------------------------------
Information on FSM $fsm$\u_neuron_memory.u_mem.state$5664 (\u_neuron_memory.u_mem.state):
Number of input signals: 3
Number of output signals: 2
Number of state bits: 2
Input signals:
0: \graph_rst
1: \u_arbiter.b_ready
2: \u_neuron_memory.access_req
Output signals:
0: $flatten\u_neuron_memory.\u_mem.$procmux$4923_CMP
1: $flatten\u_neuron_memory.\u_mem.$procmux$4931_CMP
State encoding:
0: 2'-1 <RESET STATE>
1: 2'1-
Transition Table (state_in, ctrl_in, state_out, ctrl_out):
0: 0 3'0-0 -> 0 2'01
1: 0 3'--1 -> 0 2'01
2: 0 3'1-0 -> 1 2'01
3: 1 3'-10 -> 0 2'10
4: 1 3'--1 -> 0 2'10
5: 1 3'-00 -> 1 2'10
-------------------------------------
FSM `$fsm$\u_arbiter.owner$5668' from module `spi_neuron_top':
-------------------------------------
Information on FSM $fsm$\u_arbiter.owner$5668 (\u_arbiter.owner):
Number of input signals: 5
Number of output signals: 4
Number of state bits: 4
Input signals:
0: \rst
1: \portc_req
2: \u_int8_access.ready
3: \u_neuron_memory.u_mem.mem_req
4: \u_spi_engine.ram_req
Output signals:
0: $flatten\u_arbiter.$procmux$1662_CMP
1: $flatten\u_arbiter.$procmux$1646_CMP
2: $flatten\u_arbiter.$procmux$1637_CMP
3: $flatten\u_arbiter.$procmux$1629_CMP
State encoding:
0: 4'---1 <RESET STATE>
1: 4'--1-
2: 4'-1--
3: 4'1---
Transition Table (state_in, ctrl_in, state_out, ctrl_out):
0: 0 5'00-00 -> 0 4'0001
1: 0 5'----1 -> 0 4'0001
2: 0 5'-1--0 -> 1 4'0001
3: 0 5'10-00 -> 2 4'0001
4: 0 5'-0-10 -> 3 4'0001
5: 1 5'--1-0 -> 0 4'0100
6: 1 5'----1 -> 0 4'0100
7: 1 5'--0-0 -> 1 4'0100
8: 2 5'--1-0 -> 0 4'0010
9: 2 5'----1 -> 0 4'0010
10: 2 5'--0-0 -> 2 4'0010
11: 3 5'--1-0 -> 0 4'1000
12: 3 5'----1 -> 0 4'1000
13: 3 5'--0-0 -> 3 4'1000
-------------------------------------
FSM `$fsm$\u_spi_engine.resp_len$5674' from module `spi_neuron_top':
-------------------------------------
Information on FSM $fsm$\u_spi_engine.resp_len$5674 (\u_spi_engine.resp_len):
Number of input signals: 6
Number of output signals: 4
Number of state bits: 3
Input signals:
0: $auto$opt_reduce.cc:137:opt_pmux$5605
1: \rst
2: $flatten\u_spi_engine.$procmux$3846_CMP
3: $flatten\u_spi_engine.$procmux$3681_CMP
4: \u_spi_slave.cs_end
5: \u_spi_slave.rx_valid
Output signals:
0: $flatten\u_spi_engine.$0\resp_len[3:0] [0]
1: $flatten\u_spi_engine.$0\resp_len[3:0] [1]
2: $flatten\u_spi_engine.$0\resp_len[3:0] [2]
3: $flatten\u_spi_engine.$0\resp_len[3:0] [3]
State encoding:
0: 3'--1 <RESET STATE>
1: 3'-1-
2: 3'1--
Transition Table (state_in, ctrl_in, state_out, ctrl_out):
0: 0 6'101000 -> 0 4'0000
1: 0 6'-00-0- -> 0 4'0000
2: 0 6'001-0- -> 0 4'0000
3: 0 6'-1--0- -> 0 4'0000
4: 0 6'----1- -> 0 4'0000
5: 0 6'101-01 -> 1 4'0001
6: 0 6'10110- -> 2 4'1011
7: 1 6'----1- -> 0 4'0000
8: 1 6'101000 -> 1 4'0001
9: 1 6'101-01 -> 1 4'0001
10: 1 6'-00-0- -> 1 4'0001
11: 1 6'001-0- -> 1 4'0001
12: 1 6'-1--0- -> 1 4'0001
13: 1 6'10110- -> 2 4'1011
14: 2 6'----1- -> 0 4'0000
15: 2 6'101-01 -> 1 4'0001
16: 2 6'101000 -> 2 4'1011
17: 2 6'10110- -> 2 4'1011
18: 2 6'-00-0- -> 2 4'1011
19: 2 6'001-0- -> 2 4'1011
20: 2 6'-1--0- -> 2 4'1011
-------------------------------------
FSM `$fsm$\u_spi_engine.state$5676' from module `spi_neuron_top':
-------------------------------------
Information on FSM $fsm$\u_spi_engine.state$5676 (\u_spi_engine.state):
Number of input signals: 16
Number of output signals: 13
Number of state bits: 14
Input signals:
0: $auto$opt_reduce.cc:137:opt_pmux$5603
1: \rst
2: \u_arbiter.a_ready
3: $flatten\u_spi_engine.$procmux$4150_CMP
4: $flatten\u_spi_engine.$procmux$4149_CMP
5: $flatten\u_spi_engine.$procmux$4148_CMP
6: $flatten\u_spi_engine.$procmux$4017_CTRL
7: $flatten\u_spi_engine.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:707$778_Y
8: $flatten\u_spi_engine.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:601$771_Y
9: $flatten\u_spi_engine.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:549$767_Y
10: $flatten\u_spi_engine.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:545$766_Y
11: $flatten\u_spi_engine.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:540$765_Y
12: $flatten\u_spi_engine.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:493$763_Y
13: $flatten\u_spi_engine.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:489$762_Y
14: \u_spi_slave.cs_end
15: \u_spi_slave.rx_valid
Output signals:
0: $flatten\u_spi_engine.$procmux$4095_CMP
1: $flatten\u_spi_engine.$procmux$3932_CMP
2: $flatten\u_spi_engine.$procmux$3929_CMP
3: $flatten\u_spi_engine.$procmux$3911_CMP
4: $flatten\u_spi_engine.$procmux$3891_CMP
5: $flatten\u_spi_engine.$procmux$3782_CMP
6: $flatten\u_spi_engine.$procmux$3732_CMP
7: $flatten\u_spi_engine.$procmux$3731_CMP
8: $flatten\u_spi_engine.$procmux$3681_CMP
9: $flatten\u_spi_engine.$procmux$3650_CMP
10: $flatten\u_spi_engine.$procmux$3617_CMP
11: $flatten\u_spi_engine.$procmux$3608_CMP
12: $flatten\u_spi_engine.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:218$749_Y
State encoding:
0: 14'-------------1 <RESET STATE>
1: 14'------------1-
2: 14'-----------1--
3: 14'----------1---
4: 14'---------1----
5: 14'--------1-----
6: 14'-------1------
7: 14'------1-------
8: 14'-----1--------
9: 14'----1---------
10: 14'---1----------
11: 14'--1-----------
12: 14'-1------------
13: 14'1-------------
Transition Table (state_in, ctrl_in, state_out, ctrl_out):
0: 0 16'00------------0- -> 0 13'0000100000000
1: 0 16'-1------------0- -> 0 13'0000100000000
2: 0 16'--------------1- -> 0 13'0000100000000
3: 0 16'10---------1--0- -> 3 13'0000100000000
4: 0 16'10-------1----0- -> 4 13'0000100000000
5: 0 16'10------------01 -> 5 13'0000100000000
6: 0 16'10----------1-0- -> 7 13'0000100000000
7: 0 16'10--------1---0- -> 10 13'0000100000000
8: 0 16'10-------0000-00 -> 12 13'0000100000000
9: 1 16'-1------------0- -> 0 13'0000000010000
10: 1 16'--------------1- -> 0 13'0000000010000
11: 1 16'-0-----------00- -> 1 13'0000000010000
12: 1 16'-0-----------10- -> 8 13'0000000010000
13: 2 16'-1------------0- -> 0 13'0000000001000
14: 2 16'--------------1- -> 0 13'0000000001000
15: 2 16'00------------0- -> 2 13'0000000001000
16: 2 16'10------------0- -> 9 13'0000000001000
17: 3 16'-1------------0- -> 0 13'0000000100000
18: 3 16'--------------1- -> 0 13'0000000100000
19: 3 16'00------------0- -> 3 13'0000000100000
20: 3 16'10------------0- -> 12 13'0000000100000
21: 4 16'-1------------0- -> 0 13'0010000000000
22: 4 16'--------------1- -> 0 13'0010000000000
23: 4 16'100-----------0- -> 4 13'0010000000000
24: 4 16'00------------0- -> 4 13'0010000000000
25: 4 16'1010----------0- -> 11 13'0010000000000
26: 4 16'1011----------0- -> 12 13'0010000000000
27: 5 16'-1------------0- -> 0 13'1000000000000
28: 5 16'--------------1- -> 0 13'1000000000000
29: 5 16'10------0-----0- -> 5 13'1000000000000
30: 5 16'00------------0- -> 5 13'1000000000000
31: 5 16'10------1-----0- -> 12 13'1000000000000
32: 6 16'-1------------0- -> 0 13'0000000000010
33: 6 16'--------------1- -> 0 13'0000000000010
34: 6 16'-0-----0-----10- -> 2 13'0000000000010
35: 6 16'-0-----------00- -> 6 13'0000000000010
36: 6 16'-0-----1-----10- -> 12 13'0000000000010
37: 7 16'-1------------0- -> 0 13'0001000000000
38: 7 16'--------------1- -> 0 13'0001000000000
39: 7 16'10------------0- -> 4 13'0001000000000
40: 7 16'00------------0- -> 7 13'0001000000000
41: 8 16'-1------------0- -> 0 13'0000000000100
42: 8 16'--------------1- -> 0 13'0000000000100
43: 8 16'00------------0- -> 8 13'0000000000100
44: 8 16'10-----1------0- -> 12 13'0000000000100
45: 8 16'10-----0------0- -> 13 13'0000000000100
46: 9 16'-1------------0- -> 0 13'0000001000000
47: 9 16'--------------1- -> 0 13'0000001000000
48: 9 16'-0------------0- -> 6 13'0000001000000
49: 10 16'-1------------0- -> 0 13'0000000000001
50: 10 16'--------------1- -> 0 13'0000000000001
51: 10 16'00------------0- -> 10 13'0000000000001
52: 10 16'10------------0- -> 12 13'0000000000001
53: 11 16'-1------------0- -> 0 13'0100000000000
54: 11 16'--------------1- -> 0 13'0100000000000
55: 11 16'10--101-------0- -> 2 13'0100000000000
56: 11 16'10--0---------0- -> 11 13'0100000000000
57: 11 16'00------------0- -> 11 13'0100000000000
58: 11 16'10--11--------0- -> 12 13'0100000000000
59: 11 16'10--100-------0- -> 13 13'0100000000000
60: 12 16'-1------------0- -> 0 13'0000000000000
61: 12 16'--------------1- -> 0 13'0000000000000
62: 12 16'-0------------0- -> 12 13'0000000000000
63: 13 16'-1------------0- -> 0 13'0000010000000
64: 13 16'--------------1- -> 0 13'0000010000000
65: 13 16'-0------------0- -> 1 13'0000010000000
-------------------------------------
FSM `$fsm$\u_int8_access.state$5692' from module `spi_neuron_top':
-------------------------------------
Information on FSM $fsm$\u_int8_access.state$5692 (\u_int8_access.state):
Number of input signals: 3
Number of output signals: 2
Number of state bits: 2
Input signals:
0: \rst
1: \u_memory_if.ready
2: \u_arbiter.m_req
Output signals:
0: $flatten\u_int8_access.$procmux$4931_CMP
1: $flatten\u_int8_access.$procmux$4923_CMP
State encoding:
0: 2'-1 <RESET STATE>
1: 2'1-
Transition Table (state_in, ctrl_in, state_out, ctrl_out):
0: 0 3'0-0 -> 0 2'10
1: 0 3'--1 -> 0 2'10
2: 0 3'1-0 -> 1 2'10
3: 1 3'-10 -> 0 2'01
4: 1 3'--1 -> 0 2'01
5: 1 3'-00 -> 1 2'01
-------------------------------------
17.13.8. Executing FSM_MAP pass (mapping FSMs to basic logic).
Mapping FSM `$fsm$\u_memory_if.state$5696' from module `\spi_neuron_top'.
Mapping FSM `$fsm$\u_psram_ctrl.state$5700' from module `\spi_neuron_top'.
Mapping FSM `$fsm$\u_neuron_memory.state$5632' from module `\spi_neuron_top'.
Mapping FSM `$fsm$\u_graph_engine.state$5640' from module `\spi_neuron_top'.
Mapping FSM `$fsm$\u_layer_sequencer.state$5655' from module `\spi_neuron_top'.
Mapping FSM `$fsm$\u_neuron_memory.u_mem.state$5664' from module `\spi_neuron_top'.
Mapping FSM `$fsm$\u_arbiter.owner$5668' from module `\spi_neuron_top'.
Mapping FSM `$fsm$\u_spi_engine.resp_len$5674' from module `\spi_neuron_top'.
Mapping FSM `$fsm$\u_spi_engine.state$5676' from module `\spi_neuron_top'.
Mapping FSM `$fsm$\u_int8_access.state$5692' from module `\spi_neuron_top'.
17.14. Executing OPT pass (performing simple optimizations).
17.14.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module spi_neuron_top.
<suppressed ~71 debug messages>
17.14.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\spi_neuron_top'.
Computing hashes of 1804 cells of `\spi_neuron_top'.
Finding duplicate cells in `\spi_neuron_top'.
Computing hashes of 1742 cells of `\spi_neuron_top'.
Finding duplicate cells in `\spi_neuron_top'.
Computing hashes of 1734 cells of `\spi_neuron_top'.
Finding duplicate cells in `\spi_neuron_top'.
Computing hashes of 1732 cells of `\spi_neuron_top'.
Finding duplicate cells in `\spi_neuron_top'.
<suppressed ~216 debug messages>
Removed a total of 72 cells.
17.14.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \spi_neuron_top..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~1104 debug messages>
17.14.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Optimizing cells in module \spi_neuron_top.
Performed a total of 0 changes.
17.14.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\spi_neuron_top'.
Computing hashes of 1732 cells of `\spi_neuron_top'.
Finding duplicate cells in `\spi_neuron_top'.
Removed a total of 0 cells.
17.14.6. Executing OPT_DFF pass (perform DFF optimizations).
Adding SRST signal on $flatten\u_int8_access.$procdff$5481 ($dff) from module spi_neuron_top (D = $flatten\u_int8_access.$procmux$4939_Y, Q = \u_int8_access.addr_reg, rval = 23'00000000000000000000000).
Adding EN signal on $auto$ff.cc:337:slice$6437 ($sdff) from module spi_neuron_top (D = \u_arbiter.m_addr, Q = \u_int8_access.addr_reg).
Adding SRST signal on $flatten\u_spi_engine.$procdff$5453 ($dff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$4666_Y, Q = \u_spi_engine.status_done_sticky, rval = 1'0).
Adding EN signal on $auto$ff.cc:337:slice$6441 ($sdff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$4666_Y, Q = \u_spi_engine.status_done_sticky).
Adding SRST signal on $flatten\u_spi_engine.$procdff$5452 ($dff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$3763_Y, Q = \u_spi_engine.status_snapshot, rval = 8'00000000).
Adding EN signal on $auto$ff.cc:337:slice$6447 ($sdff) from module spi_neuron_top (D = { 5'00000 \u_graph_engine.err \u_spi_engine.status_done_sticky \u_spi_engine.busy_all }, Q = \u_spi_engine.status_snapshot).
Adding SRST signal on $flatten\u_spi_engine.$procdff$5451 ($dff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$3794_Y, Q = \u_spi_engine.graph_mode, rval = 1'0).
Adding SRST signal on $flatten\u_spi_engine.$procdff$5450 ($dff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$3825_Y, Q = \u_spi_engine.net_mode, rval = 1'0).
Adding SRST signal on $flatten\u_psram_ctrl.$procdff$5471 ($dff) from module spi_neuron_top (D = $flatten\u_psram_ctrl.$procmux$4676_Y, Q = \u_psram_ctrl.dq_oe, rval = 1'0).
Adding SRST signal on $flatten\u_psram_ctrl.$procdff$5470 ($dff) from module spi_neuron_top (D = $flatten\u_psram_ctrl.$procmux$4789_Y, Q = \u_psram_ctrl.dq_out, rval = 16'0000000000000000).
Adding EN signal on $auto$ff.cc:337:slice$6456 ($sdff) from module spi_neuron_top (D = \u_memory_if.mem_wdata, Q = \u_psram_ctrl.dq_out).
Adding SRST signal on $flatten\u_psram_ctrl.$procdff$5469 ($dff) from module spi_neuron_top (D = $flatten\u_psram_ctrl.$procmux$4795_Y, Q = \u_psram_ctrl.ub_reg, rval = 1'1).
Adding EN signal on $auto$ff.cc:337:slice$6460 ($sdff) from module spi_neuron_top (D = $flatten\u_psram_ctrl.$procmux$4795_Y, Q = \u_psram_ctrl.ub_reg).
Adding SRST signal on $flatten\u_psram_ctrl.$procdff$5468 ($dff) from module spi_neuron_top (D = $flatten\u_psram_ctrl.$procmux$4807_Y, Q = \u_psram_ctrl.lb_reg, rval = 1'1).
Adding EN signal on $auto$ff.cc:337:slice$6468 ($sdff) from module spi_neuron_top (D = $flatten\u_psram_ctrl.$procmux$4807_Y, Q = \u_psram_ctrl.lb_reg).
Adding SRST signal on $flatten\u_psram_ctrl.$procdff$5464 ($dff) from module spi_neuron_top (D = $flatten\u_psram_ctrl.$procmux$4852_Y, Q = \u_psram_ctrl.counter, rval = 14'00000000000000).
Adding EN signal on $auto$ff.cc:337:slice$6476 ($sdff) from module spi_neuron_top (D = $flatten\u_psram_ctrl.$procmux$4852_Y, Q = \u_psram_ctrl.counter).
Adding SRST signal on $flatten\u_psram_ctrl.$procdff$5462 ($dff) from module spi_neuron_top (D = $flatten\u_psram_ctrl.$procmux$4697_Y, Q = \u_psram_ctrl.psram_ub_n, rval = 1'1).
Adding SRST signal on $flatten\u_psram_ctrl.$procdff$5461 ($dff) from module spi_neuron_top (D = $flatten\u_psram_ctrl.$procmux$4711_Y, Q = \u_psram_ctrl.psram_lb_n, rval = 1'1).
Adding SRST signal on $flatten\u_psram_ctrl.$procdff$5460 ($dff) from module spi_neuron_top (D = $flatten\u_psram_ctrl.$procmux$4728_Y, Q = \u_psram_ctrl.psram_we_n, rval = 1'1).
Adding SRST signal on $flatten\u_psram_ctrl.$procdff$5459 ($dff) from module spi_neuron_top (D = $flatten\u_psram_ctrl.$procmux$4745_Y, Q = \u_psram_ctrl.psram_oe_n, rval = 1'1).
Adding SRST signal on $flatten\u_psram_ctrl.$procdff$5458 ($dff) from module spi_neuron_top (D = $flatten\u_psram_ctrl.$procmux$4758_Y, Q = \u_psram_ctrl.psram_ce_n, rval = 1'1).
Adding SRST signal on $flatten\u_psram_ctrl.$procdff$5457 ($dff) from module spi_neuron_top (D = $flatten\u_psram_ctrl.$procmux$4878_Y, Q = \u_psram_ctrl.psram_a, rval = 23'00000000000000000000000).
Adding EN signal on $auto$ff.cc:337:slice$6489 ($sdff) from module spi_neuron_top (D = \u_memory_if.mem_addr, Q = \u_psram_ctrl.psram_a).
Adding SRST signal on $flatten\u_psram_ctrl.$procdff$5456 ($dff) from module spi_neuron_top (D = $flatten\u_psram_ctrl.$procmux$4771_Y, Q = \u_psram_ctrl.mem_ready, rval = 1'0).
Adding SRST signal on $flatten\u_psram_ctrl.$procdff$5455 ($dff) from module spi_neuron_top (D = $flatten\u_psram_ctrl.$procmux$4889_Y, Q = \u_psram_ctrl.mem_rdata, rval = 16'0000000000000000).
Adding EN signal on $auto$ff.cc:337:slice$6494 ($sdff) from module spi_neuron_top (D = \psram_dq, Q = \u_psram_ctrl.mem_rdata).
Adding SRST signal on $flatten\u_spi_engine.$procdff$5448 ($dff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$3877_Y, Q = \u_spi_engine.resp_index, rval = 4'0000).
Adding EN signal on $auto$ff.cc:337:slice$6498 ($sdff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$3866_Y, Q = \u_spi_engine.resp_index).
Adding SRST signal on $flatten\u_spi_engine.$procdff$5447 ($dff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$3893_Y, Q = \u_spi_engine.cur_read_byte, rval = 8'00000000).
Adding EN signal on $auto$ff.cc:337:slice$6514 ($sdff) from module spi_neuron_top (D = \u_arbiter.a_rdata, Q = \u_spi_engine.cur_read_byte).
Adding SRST signal on $flatten\u_spi_engine.$procdff$5446 ($dff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$3913_Y, Q = \u_spi_engine.pending_wdata, rval = 8'00000000).
Adding EN signal on $auto$ff.cc:337:slice$6520 ($sdff) from module spi_neuron_top (D = \u_spi_slave.rx_byte, Q = \u_spi_engine.pending_wdata).
Adding SRST signal on $flatten\u_spi_engine.$procdff$5444 ($dff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$3943_Y, Q = \u_spi_engine.cur_addr, rval = 23'00000000000000000000000).
Adding EN signal on $auto$ff.cc:337:slice$6526 ($sdff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$3928_Y, Q = \u_spi_engine.cur_addr).
Adding SRST signal on $flatten\u_spi_engine.$procdff$5443 ($dff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$3967_Y, Q = \u_spi_engine.len_remaining, rval = 16'0000000000000000).
Adding EN signal on $auto$ff.cc:337:slice$6544 ($sdff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$3955_Y, Q = \u_spi_engine.len_remaining).
Adding SRST signal on $flatten\u_spi_engine.$procdff$5442 ($dff) from module spi_neuron_top (D = { $flatten\u_spi_engine.$procmux$3619_Y $flatten\u_spi_engine.$procmux$3652_Y }, Q = \u_spi_engine.len_acc, rval = 16'0000000000000000).
Adding EN signal on $auto$ff.cc:337:slice$6560 ($sdff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$3637_Y, Q = \u_spi_engine.len_acc [7:0]).
Adding EN signal on $auto$ff.cc:337:slice$6560 ($sdff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$3607_Y, Q = \u_spi_engine.len_acc [15:8]).
Adding SRST signal on $flatten\u_spi_engine.$procdff$5441 ($dff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$4022_Y, Q = \u_spi_engine.addr_acc, rval = 24'000000000000000000000000).
Adding EN signal on $auto$ff.cc:337:slice$6591 ($sdff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$4002_Y, Q = \u_spi_engine.addr_acc).
Adding SRST signal on $flatten\u_spi_engine.$procdff$5440 ($dff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$4055_Y, Q = \u_spi_engine.byte_pos, rval = 2'00).
Adding EN signal on $auto$ff.cc:337:slice$6607 ($sdff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$4043_Y, Q = \u_spi_engine.byte_pos).
Adding SRST signal on $flatten\u_spi_engine.$procdff$5439 ($dff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$4079_Y, Q = \u_spi_engine.opcode, rval = 8'00000000).
Adding EN signal on $auto$ff.cc:337:slice$6621 ($sdff) from module spi_neuron_top (D = \u_spi_slave.rx_byte, Q = \u_spi_engine.opcode).
Adding SRST signal on $flatten\u_spi_engine.$procdff$5437 ($dff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$4186_Y, Q = \u_spi_engine.n_out, rval = 16'0000000000000000).
Adding EN signal on $auto$ff.cc:337:slice$6627 ($sdff) from module spi_neuron_top (D = { \u_spi_engine.addr_acc [7:0] \u_spi_slave.rx_byte }, Q = \u_spi_engine.n_out).
Adding SRST signal on $flatten\u_spi_engine.$procdff$5436 ($dff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$4217_Y, Q = \u_spi_engine.num_neurons_graph, rval = 16'0000000000000000).
Adding EN signal on $auto$ff.cc:337:slice$6633 ($sdff) from module spi_neuron_top (D = { \u_spi_engine.addr_acc [7:0] \u_spi_slave.rx_byte }, Q = \u_spi_engine.num_neurons_graph).
Adding SRST signal on $flatten\u_spi_engine.$procdff$5435 ($dff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$4240_Y, Q = \u_spi_engine.net_type, rval = 8'00000001).
Adding EN signal on $auto$ff.cc:337:slice$6639 ($sdff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$4227_Y, Q = \u_spi_engine.net_type).
Adding SRST signal on $flatten\u_spi_engine.$procdff$5434 ($dff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$4256_Y, Q = \u_spi_engine.run_num_layers, rval = 8'00000000).
Adding EN signal on $auto$ff.cc:337:slice$6653 ($sdff) from module spi_neuron_top (D = \u_spi_slave.rx_byte, Q = \u_spi_engine.run_num_layers).
Adding SRST signal on $flatten\u_spi_engine.$procdff$5433 ($dff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$3709_Y, Q = \u_spi_engine.run_start, rval = 1'0).
Adding SRST signal on $flatten\u_spi_engine.$procdff$5432 ($dff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$4291_Y, Q = \u_spi_engine.buf_b_base, rval = 23'00000000000000000000000).
Adding EN signal on $auto$ff.cc:337:slice$6668 ($sdff) from module spi_neuron_top (D = { \u_spi_engine.addr_acc [14:0] \u_spi_slave.rx_byte }, Q = \u_spi_engine.buf_b_base).
Adding SRST signal on $flatten\u_spi_engine.$procdff$5431 ($dff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$4327_Y, Q = \u_spi_engine.buf_a_base, rval = 23'00000000000000000000000).
Adding EN signal on $auto$ff.cc:337:slice$6674 ($sdff) from module spi_neuron_top (D = { \u_spi_engine.addr_acc [14:0] \u_spi_slave.rx_byte }, Q = \u_spi_engine.buf_a_base).
Adding SRST signal on $flatten\u_spi_engine.$procdff$5430 ($dff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$4364_Y, Q = \u_spi_engine.table_base, rval = 23'00000000000000000000000).
Adding EN signal on $auto$ff.cc:337:slice$6680 ($sdff) from module spi_neuron_top (D = { \u_spi_engine.addr_acc [14:0] \u_spi_slave.rx_byte }, Q = \u_spi_engine.table_base).
Adding SRST signal on $flatten\u_spi_engine.$procdff$5429 ($dff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$3676_Y, Q = \u_spi_engine.nm_soft_rst, rval = 1'0).
Adding SRST signal on $flatten\u_spi_engine.$procdff$5428 ($dff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$3709_Y, Q = \u_spi_engine.nm_start, rval = 1'0).
Adding SRST signal on $flatten\u_spi_engine.$procdff$5427 ($dff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$4396_Y, Q = \u_spi_engine.n_neurons_real, rval = 16'0000000000000001).
Adding EN signal on $auto$ff.cc:337:slice$6702 ($sdff) from module spi_neuron_top (D = { \u_spi_engine.addr_acc [7:0] \u_spi_slave.rx_byte }, Q = \u_spi_engine.n_neurons_real).
Adding SRST signal on $flatten\u_spi_engine.$procdff$5426 ($dff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$4429_Y, Q = \u_spi_engine.n_inputs_real, rval = 16'0000000000100000).
Adding EN signal on $auto$ff.cc:337:slice$6708 ($sdff) from module spi_neuron_top (D = { \u_spi_engine.addr_acc [7:0] \u_spi_slave.rx_byte }, Q = \u_spi_engine.n_inputs_real).
Adding SRST signal on $flatten\u_spi_engine.$procdff$5425 ($dff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$4463_Y, Q = \u_spi_engine.activation, rval = 2'01).
Adding EN signal on $auto$ff.cc:337:slice$6714 ($sdff) from module spi_neuron_top (D = \u_spi_slave.rx_byte [1:0], Q = \u_spi_engine.activation).
Adding SRST signal on $flatten\u_spi_engine.$procdff$5424 ($dff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$4501_Y, Q = \u_spi_engine.bias_addr, rval = 23'00000000000000000000000).
Adding EN signal on $auto$ff.cc:337:slice$6720 ($sdff) from module spi_neuron_top (D = { \u_spi_engine.addr_acc [14:0] \u_spi_slave.rx_byte }, Q = \u_spi_engine.bias_addr).
Adding SRST signal on $flatten\u_spi_engine.$procdff$5423 ($dff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$4540_Y, Q = \u_spi_engine.w_base, rval = 23'00000000000000000000000).
Adding EN signal on $auto$ff.cc:337:slice$6726 ($sdff) from module spi_neuron_top (D = { \u_spi_engine.addr_acc [14:0] \u_spi_slave.rx_byte }, Q = \u_spi_engine.w_base).
Adding SRST signal on $flatten\u_spi_engine.$procdff$5422 ($dff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$4580_Y, Q = \u_spi_engine.x_base, rval = 23'00000000000000000000000).
Adding EN signal on $auto$ff.cc:337:slice$6732 ($sdff) from module spi_neuron_top (D = { \u_spi_engine.addr_acc [14:0] \u_spi_slave.rx_byte }, Q = \u_spi_engine.x_base).
Adding SRST signal on $flatten\u_spi_engine.$procdff$5421 ($dff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$4597_Y, Q = \u_spi_engine.ram_wdata, rval = 8'00000000).
Adding EN signal on $auto$ff.cc:337:slice$6738 ($sdff) from module spi_neuron_top (D = \u_spi_engine.pending_wdata, Q = \u_spi_engine.ram_wdata).
Adding SRST signal on $flatten\u_spi_engine.$procdff$5420 ($dff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$4613_Y, Q = \u_spi_engine.ram_addr, rval = 23'00000000000000000000000).
Adding EN signal on $auto$ff.cc:337:slice$6744 ($sdff) from module spi_neuron_top (D = \u_spi_engine.cur_addr, Q = \u_spi_engine.ram_addr).
Adding SRST signal on $flatten\u_spi_engine.$procdff$5419 ($dff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$4629_Y, Q = \u_spi_engine.ram_wr, rval = 1'0).
Adding EN signal on $auto$ff.cc:337:slice$6750 ($sdff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$4625_Y, Q = \u_spi_engine.ram_wr).
Adding SRST signal on $flatten\u_spi_engine.$procdff$5418 ($dff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$3730_Y, Q = \u_spi_engine.ram_req, rval = 1'0).
Adding SRST signal on $flatten\u_memory_if.$procdff$5259 ($dff) from module spi_neuron_top (D = $flatten\u_memory_if.$procmux$1564_Y, Q = \u_memory_if.mem_ub_n, rval = 1'1).
Adding EN signal on $auto$ff.cc:337:slice$6761 ($sdff) from module spi_neuron_top (D = \u_int8_access.mem_ub_n, Q = \u_memory_if.mem_ub_n).
Adding SRST signal on $flatten\u_memory_if.$procdff$5258 ($dff) from module spi_neuron_top (D = $flatten\u_memory_if.$procmux$1573_Y, Q = \u_memory_if.mem_lb_n, rval = 1'1).
Adding EN signal on $auto$ff.cc:337:slice$6765 ($sdff) from module spi_neuron_top (D = \u_int8_access.mem_lb_n, Q = \u_memory_if.mem_lb_n).
Adding SRST signal on $flatten\u_memory_if.$procdff$5257 ($dff) from module spi_neuron_top (D = $flatten\u_memory_if.$procmux$1553_Y, Q = \u_memory_if.ready, rval = 1'0).
Adding SRST signal on $flatten\u_memory_if.$procdff$5256 ($dff) from module spi_neuron_top (D = $flatten\u_memory_if.$procmux$1583_Y, Q = \u_memory_if.rdata, rval = 16'0000000000000000).
Adding EN signal on $auto$ff.cc:337:slice$6774 ($sdff) from module spi_neuron_top (D = \u_psram_ctrl.mem_rdata, Q = \u_memory_if.rdata).
Adding SRST signal on $flatten\u_memory_if.$procdff$5255 ($dff) from module spi_neuron_top (D = $flatten\u_memory_if.$procmux$1592_Y, Q = \u_memory_if.mem_wdata, rval = 16'0000000000000000).
Adding EN signal on $auto$ff.cc:337:slice$6780 ($sdff) from module spi_neuron_top (D = \u_int8_access.mem_wdata, Q = \u_memory_if.mem_wdata).
Adding SRST signal on $flatten\u_memory_if.$procdff$5254 ($dff) from module spi_neuron_top (D = $flatten\u_memory_if.$procmux$1601_Y, Q = \u_memory_if.mem_addr, rval = 23'00000000000000000000000).
Adding EN signal on $auto$ff.cc:337:slice$6784 ($sdff) from module spi_neuron_top (D = \u_int8_access.mem_addr, Q = \u_memory_if.mem_addr).
Adding SRST signal on $flatten\u_memory_if.$procdff$5253 ($dff) from module spi_neuron_top (D = $flatten\u_memory_if.$procmux$1610_Y, Q = \u_memory_if.mem_wr, rval = 1'0).
Adding EN signal on $auto$ff.cc:337:slice$6788 ($sdff) from module spi_neuron_top (D = \u_int8_access.mem_wr, Q = \u_memory_if.mem_wr).
Adding SRST signal on $flatten\u_memory_if.$procdff$5252 ($dff) from module spi_neuron_top (D = $flatten\u_memory_if.$procmux$1545_Y, Q = \u_memory_if.mem_req, rval = 1'0).
Adding SRST signal on $flatten\u_int8_access.$procdff$5480 ($dff) from module spi_neuron_top (D = $flatten\u_int8_access.$procmux$4945_Y, Q = \u_int8_access.mem_ub_n, rval = 1'1).
Adding EN signal on $auto$ff.cc:337:slice$6797 ($sdff) from module spi_neuron_top (D = $flatten\u_int8_access.$procmux$4945_Y, Q = \u_int8_access.mem_ub_n).
Adding SRST signal on $flatten\u_int8_access.$procdff$5479 ($dff) from module spi_neuron_top (D = $flatten\u_int8_access.$procmux$4957_Y, Q = \u_int8_access.mem_lb_n, rval = 1'1).
Adding EN signal on $auto$ff.cc:337:slice$6805 ($sdff) from module spi_neuron_top (D = $flatten\u_int8_access.$procmux$4957_Y, Q = \u_int8_access.mem_lb_n).
Adding SRST signal on $flatten\u_int8_access.$procdff$5478 ($dff) from module spi_neuron_top (D = $flatten\u_int8_access.$procmux$4928_Y, Q = \u_int8_access.ready, rval = 1'0).
Adding SRST signal on $flatten\u_int8_access.$procdff$5477 ($dff) from module spi_neuron_top (D = $flatten\u_int8_access.$procmux$4974_Y, Q = \u_int8_access.rdata, rval = 8'00000000).
Adding EN signal on $auto$ff.cc:337:slice$6818 ($sdff) from module spi_neuron_top (D = $flatten\u_int8_access.$procmux$4970_Y, Q = \u_int8_access.rdata).
Adding SRST signal on $flatten\u_int8_access.$procdff$5476 ($dff) from module spi_neuron_top (D = $flatten\u_int8_access.$procmux$4986_Y, Q = \u_int8_access.mem_wdata, rval = 16'0000000000000000).
Adding EN signal on $auto$ff.cc:337:slice$6822 ($sdff) from module spi_neuron_top (D = $flatten\u_int8_access.$procmux$4982_Y, Q = \u_int8_access.mem_wdata).
Adding SRST signal on $flatten\u_int8_access.$procdff$5475 ($dff) from module spi_neuron_top (D = $flatten\u_int8_access.$procmux$4995_Y, Q = \u_int8_access.mem_addr, rval = 23'00000000000000000000000).
Adding EN signal on $auto$ff.cc:337:slice$6826 ($sdff) from module spi_neuron_top (D = { 1'0 \u_arbiter.m_addr [22:1] }, Q = \u_int8_access.mem_addr).
Adding SRST signal on $flatten\u_int8_access.$procdff$5474 ($dff) from module spi_neuron_top (D = $flatten\u_int8_access.$procmux$5004_Y, Q = \u_int8_access.mem_wr, rval = 1'0).
Adding EN signal on $auto$ff.cc:337:slice$6830 ($sdff) from module spi_neuron_top (D = \u_arbiter.m_wr, Q = \u_int8_access.mem_wr).
Adding SRST signal on $flatten\u_int8_access.$procdff$5473 ($dff) from module spi_neuron_top (D = $flatten\u_int8_access.$procmux$4920_Y, Q = \u_int8_access.mem_req, rval = 1'0).
Adding SRST signal on $flatten\u_arbiter.$procdff$5269 ($dff) from module spi_neuron_top (D = $flatten\u_arbiter.$procmux$1699_Y, Q = \u_arbiter.m_wdata, rval = 8'00000000).
Adding EN signal on $auto$ff.cc:337:slice$6839 ($sdff) from module spi_neuron_top (D = $flatten\u_arbiter.$procmux$1697_Y, Q = \u_arbiter.m_wdata).
Adding SRST signal on $flatten\u_arbiter.$procdff$5268 ($dff) from module spi_neuron_top (D = $flatten\u_arbiter.$procmux$1715_Y, Q = \u_arbiter.m_addr, rval = 23'00000000000000000000000).
Adding EN signal on $auto$ff.cc:337:slice$6845 ($sdff) from module spi_neuron_top (D = $flatten\u_arbiter.$procmux$1713_Y, Q = \u_arbiter.m_addr).
Adding SRST signal on $flatten\u_arbiter.$procdff$5267 ($dff) from module spi_neuron_top (D = $flatten\u_arbiter.$procmux$1731_Y, Q = \u_arbiter.m_wr, rval = 1'0).
Adding EN signal on $auto$ff.cc:337:slice$6851 ($sdff) from module spi_neuron_top (D = $flatten\u_arbiter.$procmux$1729_Y, Q = \u_arbiter.m_wr).
Adding SRST signal on $flatten\u_arbiter.$procdff$5266 ($dff) from module spi_neuron_top (D = $flatten\u_arbiter.$procmux$1659_Y, Q = \u_arbiter.m_req, rval = 1'0).
Adding SRST signal on $flatten\u_arbiter.$procdff$5265 ($dff) from module spi_neuron_top (D = $flatten\u_arbiter.$procmux$1626_Y, Q = \u_arbiter.c_ready, rval = 1'0).
Adding SRST signal on $flatten\u_arbiter.$procdff$5264 ($dff) from module spi_neuron_top (D = $flatten\u_arbiter.$procmux$1738_Y, Q = \u_arbiter.c_rdata, rval = 8'00000000).
Adding EN signal on $auto$ff.cc:337:slice$6867 ($sdff) from module spi_neuron_top (D = \u_int8_access.rdata, Q = \u_arbiter.c_rdata).
Adding SRST signal on $flatten\u_arbiter.$procdff$5263 ($dff) from module spi_neuron_top (D = $flatten\u_arbiter.$procmux$1626_Y, Q = \u_arbiter.b_ready, rval = 1'0).
Adding SRST signal on $flatten\u_arbiter.$procdff$5262 ($dff) from module spi_neuron_top (D = $flatten\u_arbiter.$procmux$1746_Y, Q = \u_arbiter.b_rdata, rval = 8'00000000).
Adding EN signal on $auto$ff.cc:337:slice$6876 ($sdff) from module spi_neuron_top (D = \u_int8_access.rdata, Q = \u_arbiter.b_rdata).
Adding SRST signal on $flatten\u_arbiter.$procdff$5261 ($dff) from module spi_neuron_top (D = $flatten\u_arbiter.$procmux$1626_Y, Q = \u_arbiter.a_ready, rval = 1'0).
Adding SRST signal on $flatten\u_arbiter.$procdff$5260 ($dff) from module spi_neuron_top (D = $flatten\u_arbiter.$procmux$1755_Y, Q = \u_arbiter.a_rdata, rval = 8'00000000).
Adding EN signal on $auto$ff.cc:337:slice$6885 ($sdff) from module spi_neuron_top (D = \u_int8_access.rdata, Q = \u_arbiter.a_rdata).
Adding SRST signal on $flatten\u_neuron_memory.\u_neuron.$procdff$5486 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.\u_neuron.$procmux$5094_Y, Q = \u_neuron_memory.u_neuron.y, rval = 8'00000000).
Adding EN signal on $auto$ff.cc:337:slice$6889 ($sdff) from module spi_neuron_top (D = $flatten\u_neuron_memory.\u_neuron.$procmux$5087_Y, Q = \u_neuron_memory.u_neuron.y).
Adding SRST signal on $flatten\u_neuron_memory.\u_neuron.$procdff$5487 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.\u_neuron.$procmux$5068_Y, Q = \u_neuron_memory.u_neuron.busy, rval = 1'0).
Adding SRST signal on $flatten\u_neuron_memory.\u_neuron.$procdff$5488 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.\u_neuron.$procmux$5030_Y, Q = \u_neuron_memory.u_neuron.done, rval = 1'0).
Adding SRST signal on $flatten\u_neuron_memory.\u_neuron.$procdff$5489 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.\u_neuron.$procmux$5054_Y, Q = \u_neuron_memory.u_neuron.group_index, rval = 2'00).
Adding EN signal on $auto$ff.cc:337:slice$6901 ($sdff) from module spi_neuron_top (D = $flatten\u_neuron_memory.\u_neuron.$add$/tmp/before_rewrite/neuron_parallel.v:194$642_Y, Q = \u_neuron_memory.u_neuron.group_index).
Adding SRST signal on $flatten\u_neuron_memory.\u_neuron.$procdff$5490 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.\u_neuron.$procmux$5043_Y, Q = \u_neuron_memory.u_neuron.acc, rval = 0).
Adding EN signal on $auto$ff.cc:337:slice$6909 ($sdff) from module spi_neuron_top (D = $flatten\u_neuron_memory.\u_neuron.$procmux$5041_Y, Q = \u_neuron_memory.u_neuron.acc).
Adding SRST signal on $flatten\u_spi_slave.$procdff$5491 ($dff) from module spi_neuron_top (D = $flatten\u_spi_slave.$procmux$5231_Y, Q = \u_spi_slave.miso, rval = 1'0).
Adding EN signal on $auto$ff.cc:337:slice$6913 ($sdff) from module spi_neuron_top (D = $flatten\u_spi_slave.$procmux$5231_Y, Q = \u_spi_slave.miso).
Adding SRST signal on $flatten\u_spi_slave.$procdff$5492 ($dff) from module spi_neuron_top (D = $flatten\u_spi_slave.$procmux$5212_Y, Q = \u_spi_slave.rx_byte, rval = 8'00000000).
Adding EN signal on $auto$ff.cc:337:slice$6925 ($sdff) from module spi_neuron_top (D = { \u_spi_slave.rx_shift [6:0] \u_spi_slave.mosi_sync [2] }, Q = \u_spi_slave.rx_byte).
Adding SRST signal on $flatten\u_spi_slave.$procdff$5493 ($dff) from module spi_neuron_top (D = $flatten\u_spi_slave.$procmux$5135_Y, Q = \u_spi_slave.rx_valid, rval = 1'0).
Adding SRST signal on $flatten\u_spi_slave.$procdff$5496 ($dff) from module spi_neuron_top (D = $flatten\u_spi_slave.$procmux$5100_Y, Q = \u_spi_slave.cs_end, rval = 1'0).
Adding SRST signal on $flatten\u_spi_slave.$procdff$5497 ($dff) from module spi_neuron_top (D = $flatten\u_spi_slave.$procmux$5192_Y, Q = \u_spi_slave.bit_count, rval = 3'000).
Adding EN signal on $auto$ff.cc:337:slice$6943 ($sdff) from module spi_neuron_top (D = $flatten\u_spi_slave.$procmux$5185_Y, Q = \u_spi_slave.bit_count).
Adding SRST signal on $flatten\u_spi_slave.$procdff$5498 ($dff) from module spi_neuron_top (D = $flatten\u_spi_slave.$procmux$5178_Y, Q = \u_spi_slave.rx_shift, rval = 8'00000000).
Adding EN signal on $auto$ff.cc:337:slice$6953 ($sdff) from module spi_neuron_top (D = { \u_spi_slave.rx_shift [6:0] \u_spi_slave.mosi_sync [2] }, Q = \u_spi_slave.rx_shift).
Adding SRST signal on $flatten\u_spi_slave.$procdff$5499 ($dff) from module spi_neuron_top (D = $flatten\u_spi_slave.$procmux$5164_Y, Q = \u_spi_slave.tx_shift, rval = 8'00000000).
Adding EN signal on $auto$ff.cc:337:slice$6963 ($sdff) from module spi_neuron_top (D = $flatten\u_spi_slave.$procmux$5164_Y, Q = \u_spi_slave.tx_shift).
Adding SRST signal on $flatten\u_spi_slave.$procdff$5500 ($dff) from module spi_neuron_top (D = \u_spi_slave.sclk_sync [2], Q = \u_spi_slave.sclk_prev, rval = 1'0).
Adding SRST signal on $flatten\u_neuron_memory.\u_mem.$procdff$5473 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.\u_mem.$procmux$4920_Y, Q = \u_neuron_memory.u_mem.mem_req, rval = 1'0).
Adding SRST signal on $flatten\u_neuron_memory.\u_mem.$procdff$5474 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.\u_mem.$procmux$5004_Y, Q = \u_neuron_memory.u_mem.mem_wr, rval = 1'0).
Adding EN signal on $auto$ff.cc:337:slice$6981 ($sdff) from module spi_neuron_top (D = \u_neuron_memory.access_wr, Q = \u_neuron_memory.u_mem.mem_wr).
Adding SRST signal on $flatten\u_spi_slave.$procdff$5501 ($dff) from module spi_neuron_top (D = \u_spi_slave.cs_n_sync [2], Q = \u_spi_slave.cs_n_prev, rval = 1'1).
Adding SRST signal on $flatten\u_spi_slave.$procdff$5502 ($dff) from module spi_neuron_top (D = { \u_spi_slave.sclk_sync [1:0] \sclk }, Q = \u_spi_slave.sclk_sync, rval = 3'000).
Adding SRST signal on $flatten\u_neuron_memory.\u_mem.$procdff$5477 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.\u_mem.$procmux$4974_Y, Q = \u_neuron_memory.u_mem.rdata, rval = 8'00000000).
Adding EN signal on $auto$ff.cc:337:slice$6987 ($sdff) from module spi_neuron_top (D = $flatten\u_neuron_memory.\u_mem.$procmux$4970_Y, Q = \u_neuron_memory.u_mem.rdata).
Adding SRST signal on $flatten\u_neuron_memory.\u_mem.$procdff$5478 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.\u_mem.$procmux$4928_Y, Q = \u_neuron_memory.u_mem.ready, rval = 1'0).
Adding SRST signal on $flatten\u_spi_slave.$procdff$5503 ($dff) from module spi_neuron_top (D = { \u_spi_slave.mosi_sync [1:0] \mosi }, Q = \u_spi_slave.mosi_sync, rval = 3'000).
Adding SRST signal on $flatten\u_spi_slave.$procdff$5504 ($dff) from module spi_neuron_top (D = { \u_spi_slave.cs_n_sync [1:0] \cs_n }, Q = \u_spi_slave.cs_n_sync, rval = 3'111).
Adding EN signal on $flatten\u_neuron_memory.$procdff$5283 ($dff) from module spi_neuron_top (D = 8'00000000, Q = \u_neuron_memory.access_wdata).
Adding SRST signal on $flatten\u_neuron_memory.$procdff$5282 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$procmux$2026_Y, Q = \u_neuron_memory.access_addr, rval = 23'00000000000000000000000).
Adding EN signal on $auto$ff.cc:337:slice$6999 ($sdff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$procmux$2026_Y, Q = \u_neuron_memory.access_addr).
Adding SRST signal on $flatten\u_neuron_memory.$procdff$5281 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$procmux$2055_Y, Q = \u_neuron_memory.access_wr, rval = 1'0).
Adding EN signal on $auto$ff.cc:337:slice$7015 ($sdff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$procmux$2055_Y, Q = \u_neuron_memory.access_wr).
Adding SRST signal on $flatten\u_neuron_memory.$procdff$5280 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$procmux$1969_Y, Q = \u_neuron_memory.access_req, rval = 1'0).
Adding SRST signal on $flatten\u_neuron_memory.$procdff$5279 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$procmux$2084_Y, Q = \u_neuron_memory.bias_group_addr, rval = 23'00000000000000000000000).
Adding EN signal on $auto$ff.cc:337:slice$7032 ($sdff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$procmux$2084_Y, Q = \u_neuron_memory.bias_group_addr).
Adding SRST signal on $flatten\u_neuron_memory.$procdff$5278 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$procmux$2099_Y, Q = \u_neuron_memory.w_group_base, rval = 23'00000000000000000000000).
Adding EN signal on $auto$ff.cc:337:slice$7044 ($sdff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$procmux$2099_Y, Q = \u_neuron_memory.w_group_base).
Adding SRST signal on $flatten\u_neuron_memory.$procdff$5277 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$procmux$2114_Y, Q = \u_neuron_memory.neuron_index, rval = 1'0).
Adding EN signal on $auto$ff.cc:337:slice$7056 ($sdff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$procmux$2114_Y, Q = \u_neuron_memory.neuron_index).
Adding SRST signal on $flatten\u_neuron_memory.$procdff$5276 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$procmux$2129_Y, Q = \u_neuron_memory.index, rval = 6'000000).
Adding EN signal on $auto$ff.cc:337:slice$7068 ($sdff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$procmux$2129_Y, Q = \u_neuron_memory.index).
Adding SRST signal on $flatten\u_neuron_memory.$procdff$5275 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$procmux$2156_Y, Q = \u_neuron_memory.bias_reg, rval = 8'00000000).
Adding EN signal on $auto$ff.cc:337:slice$7086 ($sdff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.bias_reg).
Adding SRST signal on $flatten\u_neuron_memory.$procdff$5274 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$procmux$1957_Y, Q = \u_neuron_memory.neuron_start, rval = 1'0).
Adding SRST signal on $flatten\u_neuron_memory.$procdff$5273 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$procmux$1940_Y, Q = \u_neuron_memory.done, rval = 1'0).
Adding SRST signal on $flatten\u_neuron_memory.$procdff$5272 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$procmux$2168_Y, Q = \u_neuron_memory.busy, rval = 1'0).
Adding EN signal on $auto$ff.cc:337:slice$7098 ($sdff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$procmux$2168_Y, Q = \u_neuron_memory.busy).
Adding SRST signal on $flatten\u_layer_sequencer.$procdff$5413 ($dff) from module spi_neuron_top (D = { $flatten\u_layer_sequencer.$procmux$3320_Y $flatten\u_layer_sequencer.$procmux$3155_Y }, Q = \u_layer_sequencer.n_inputs_acc, rval = 16'0000000000000000).
Adding EN signal on $auto$ff.cc:337:slice$7108 ($sdff) from module spi_neuron_top (D = \u_arbiter.c_rdata, Q = \u_layer_sequencer.n_inputs_acc [15:8]).
Adding EN signal on $auto$ff.cc:337:slice$7108 ($sdff) from module spi_neuron_top (D = \u_arbiter.c_rdata, Q = \u_layer_sequencer.n_inputs_acc [7:0]).
Adding SRST signal on $flatten\u_layer_sequencer.$procdff$5412 ($dff) from module spi_neuron_top (D = $flatten\u_layer_sequencer.$procmux$3358_Y, Q = \u_layer_sequencer.activation_acc, rval = 8'00000000).
Adding EN signal on $auto$ff.cc:337:slice$7115 ($sdff) from module spi_neuron_top (D = \u_arbiter.c_rdata, Q = \u_layer_sequencer.activation_acc).
Adding SRST signal on $flatten\u_layer_sequencer.$procdff$5411 ($dff) from module spi_neuron_top (D = { $flatten\u_layer_sequencer.$procmux$3195_Y $flatten\u_layer_sequencer.$procmux$3340_Y $flatten\u_layer_sequencer.$procmux$3174_Y }, Q = \u_layer_sequencer.bias_addr_acc, rval = 24'000000000000000000000000).
Adding EN signal on $auto$ff.cc:337:slice$7119 ($sdff) from module spi_neuron_top (D = \u_arbiter.c_rdata, Q = \u_layer_sequencer.bias_addr_acc [15:8]).
Adding EN signal on $auto$ff.cc:337:slice$7119 ($sdff) from module spi_neuron_top (D = \u_arbiter.c_rdata, Q = \u_layer_sequencer.bias_addr_acc [23:16]).
Adding EN signal on $auto$ff.cc:337:slice$7119 ($sdff) from module spi_neuron_top (D = \u_arbiter.c_rdata, Q = \u_layer_sequencer.bias_addr_acc [7:0]).
Adding SRST signal on $flatten\u_layer_sequencer.$procdff$5410 ($dff) from module spi_neuron_top (D = { $flatten\u_layer_sequencer.$procmux$3241_Y $flatten\u_layer_sequencer.$procmux$3381_Y $flatten\u_layer_sequencer.$procmux$3217_Y }, Q = \u_layer_sequencer.w_base_acc, rval = 24'000000000000000000000000).
Adding EN signal on $auto$ff.cc:337:slice$7129 ($sdff) from module spi_neuron_top (D = \u_arbiter.c_rdata, Q = \u_layer_sequencer.w_base_acc [15:8]).
Adding EN signal on $auto$ff.cc:337:slice$7129 ($sdff) from module spi_neuron_top (D = \u_arbiter.c_rdata, Q = \u_layer_sequencer.w_base_acc [23:16]).
Adding EN signal on $auto$ff.cc:337:slice$7129 ($sdff) from module spi_neuron_top (D = \u_arbiter.c_rdata, Q = \u_layer_sequencer.w_base_acc [7:0]).
Adding SRST signal on $flatten\u_layer_sequencer.$procdff$5409 ($dff) from module spi_neuron_top (D = $flatten\u_layer_sequencer.$procmux$3409_Y, Q = \u_layer_sequencer.desc_byte_idx, rval = 4'0000).
Adding EN signal on $auto$ff.cc:337:slice$7139 ($sdff) from module spi_neuron_top (D = $flatten\u_layer_sequencer.$procmux$3409_Y, Q = \u_layer_sequencer.desc_byte_idx).
Adding SRST signal on $flatten\u_layer_sequencer.$procdff$5408 ($dff) from module spi_neuron_top (D = $flatten\u_layer_sequencer.$procmux$3432_Y, Q = \u_layer_sequencer.desc_table_addr, rval = 23'00000000000000000000000).
Adding EN signal on $auto$ff.cc:337:slice$7155 ($sdff) from module spi_neuron_top (D = $flatten\u_layer_sequencer.$procmux$3432_Y, Q = \u_layer_sequencer.desc_table_addr).
Adding SRST signal on $flatten\u_layer_sequencer.$procdff$5407 ($dff) from module spi_neuron_top (D = $flatten\u_layer_sequencer.$procmux$3449_Y, Q = \u_layer_sequencer.num_layers_reg, rval = 8'00000000).
Adding EN signal on $auto$ff.cc:337:slice$7169 ($sdff) from module spi_neuron_top (D = \u_spi_engine.run_num_layers, Q = \u_layer_sequencer.num_layers_reg).
Adding SRST signal on $flatten\u_layer_sequencer.$procdff$5406 ($dff) from module spi_neuron_top (D = $flatten\u_layer_sequencer.$procmux$3463_Y, Q = \u_layer_sequencer.layer_idx, rval = 8'00000000).
Adding EN signal on $auto$ff.cc:337:slice$7173 ($sdff) from module spi_neuron_top (D = $flatten\u_layer_sequencer.$procmux$3463_Y, Q = \u_layer_sequencer.layer_idx).
Adding SRST signal on $flatten\u_layer_sequencer.$procdff$5405 ($dff) from module spi_neuron_top (D = $flatten\u_layer_sequencer.$procmux$3475_Y, Q = \u_layer_sequencer.nm_n_neurons, rval = 16'0000000000000000).
Adding EN signal on $auto$ff.cc:337:slice$7187 ($sdff) from module spi_neuron_top (D = \u_layer_sequencer.n_neurons_acc, Q = \u_layer_sequencer.nm_n_neurons).
Adding SRST signal on $flatten\u_neuron_memory.\u_mem.$procdff$5481 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.\u_mem.$procmux$4939_Y, Q = \u_neuron_memory.u_mem.addr_reg, rval = 23'00000000000000000000000).
Adding EN signal on $auto$ff.cc:337:slice$7189 ($sdff) from module spi_neuron_top (D = \u_neuron_memory.access_addr, Q = \u_neuron_memory.u_mem.addr_reg).
Adding SRST signal on $flatten\u_graph_engine.\u_neuron.$procdff$5486 ($dff) from module spi_neuron_top (D = $flatten\u_graph_engine.\u_neuron.$procmux$5094_Y, Q = \u_graph_engine.u_neuron.y, rval = 8'00000000).
Adding EN signal on $auto$ff.cc:337:slice$7193 ($sdff) from module spi_neuron_top (D = $flatten\u_graph_engine.\u_neuron.$procmux$5087_Y, Q = \u_graph_engine.u_neuron.y).
Adding SRST signal on $flatten\u_graph_engine.\u_neuron.$procdff$5487 ($dff) from module spi_neuron_top (D = $flatten\u_graph_engine.\u_neuron.$procmux$5068_Y, Q = \u_graph_engine.u_neuron.busy, rval = 1'0).
Adding SRST signal on $flatten\u_graph_engine.\u_neuron.$procdff$5488 ($dff) from module spi_neuron_top (D = $flatten\u_graph_engine.\u_neuron.$procmux$5030_Y, Q = \u_graph_engine.u_neuron.done, rval = 1'0).
Adding SRST signal on $flatten\u_graph_engine.\u_neuron.$procdff$5489 ($dff) from module spi_neuron_top (D = $flatten\u_graph_engine.\u_neuron.$procmux$5054_Y, Q = \u_graph_engine.u_neuron.group_index, rval = 2'00).
Adding EN signal on $auto$ff.cc:337:slice$7205 ($sdff) from module spi_neuron_top (D = $flatten\u_graph_engine.\u_neuron.$add$/tmp/before_rewrite/neuron_parallel.v:194$642_Y, Q = \u_graph_engine.u_neuron.group_index).
Adding SRST signal on $flatten\u_graph_engine.\u_neuron.$procdff$5490 ($dff) from module spi_neuron_top (D = $flatten\u_graph_engine.\u_neuron.$procmux$5043_Y, Q = \u_graph_engine.u_neuron.acc, rval = 0).
Adding EN signal on $auto$ff.cc:337:slice$7213 ($sdff) from module spi_neuron_top (D = $flatten\u_graph_engine.\u_neuron.$procmux$5041_Y, Q = \u_graph_engine.u_neuron.acc).
Adding SRST signal on $flatten\u_graph_engine.$procdff$5320 ($dff) from module spi_neuron_top (D = $flatten\u_graph_engine.$procmux$2665_Y, Q = \u_graph_engine.n_conn_padded_reg, rval = 16'0000000000000000).
Adding EN signal on $auto$ff.cc:337:slice$7217 ($sdff) from module spi_neuron_top (D = { $flatten\u_graph_engine.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:394$1022_Y [15:3] 3'000 }, Q = \u_graph_engine.n_conn_padded_reg).
Adding SRST signal on $flatten\u_graph_engine.$procdff$5319 ($dff) from module spi_neuron_top (D = $flatten\u_graph_engine.$procmux$2683_Y, Q = \u_graph_engine.activation_reg, rval = 2'01).
Adding EN signal on $auto$ff.cc:337:slice$7221 ($sdff) from module spi_neuron_top (D = \u_arbiter.c_rdata [1:0], Q = \u_graph_engine.activation_reg).
Adding SRST signal on $flatten\u_graph_engine.$procdff$5318 ($dff) from module spi_neuron_top (D = $flatten\u_graph_engine.$procmux$2700_Y, Q = \u_graph_engine.bias_reg, rval = 8'00000000).
Adding EN signal on $auto$ff.cc:337:slice$7225 ($sdff) from module spi_neuron_top (D = \u_arbiter.c_rdata, Q = \u_graph_engine.bias_reg).
Adding SRST signal on $flatten\u_graph_engine.$procdff$5317 ($dff) from module spi_neuron_top (D = $flatten\u_graph_engine.$procmux$2596_Y, Q = \u_graph_engine.neuron_start, rval = 1'0).
Adding SRST signal on $flatten\u_graph_engine.$procdff$5316 ($dff) from module spi_neuron_top (D = $flatten\u_graph_engine.$procmux$2710_Y, Q = \u_graph_engine.act_wr_data, rval = 8'00000000).
Adding EN signal on $auto$ff.cc:337:slice$7230 ($sdff) from module spi_neuron_top (D = $flatten\u_graph_engine.$procmux$2710_Y, Q = \u_graph_engine.act_wr_data).
Adding SRST signal on $flatten\u_graph_engine.$procdff$5315 ($dff) from module spi_neuron_top (D = $flatten\u_graph_engine.$procmux$2723_Y, Q = \u_graph_engine.act_wr_addr, rval = 12'000000000000).
Adding EN signal on $auto$ff.cc:337:slice$7240 ($sdff) from module spi_neuron_top (D = $flatten\u_graph_engine.$procmux$2723_Y, Q = \u_graph_engine.act_wr_addr).
Adding SRST signal on $flatten\u_graph_engine.$procdff$5314 ($dff) from module spi_neuron_top (D = $flatten\u_graph_engine.$procmux$2606_Y, Q = \u_graph_engine.act_wr_en, rval = 1'0).
Adding SRST signal on $flatten\u_graph_engine.$procdff$5313 ($dff) from module spi_neuron_top (D = $flatten\u_graph_engine.$procmux$2741_Y, Q = \u_graph_engine.weight_acc, rval = 8'00000000).
Adding EN signal on $auto$ff.cc:337:slice$7251 ($sdff) from module spi_neuron_top (D = \u_arbiter.c_rdata, Q = \u_graph_engine.weight_acc).
Adding SRST signal on $flatten\u_graph_engine.$procdff$5312 ($dff) from module spi_neuron_top (D = { $flatten\u_graph_engine.$procmux$2225_Y $flatten\u_graph_engine.$procmux$2241_Y }, Q = \u_graph_engine.src_id_acc, rval = 16'0000000000000000).
Adding EN signal on $auto$ff.cc:337:slice$7255 ($sdff) from module spi_neuron_top (D = \u_arbiter.c_rdata, Q = \u_graph_engine.src_id_acc [7:0]).
Adding EN signal on $auto$ff.cc:337:slice$7255 ($sdff) from module spi_neuron_top (D = \u_arbiter.c_rdata, Q = \u_graph_engine.src_id_acc [15:8]).
Adding SRST signal on $flatten\u_graph_engine.$procdff$5311 ($dff) from module spi_neuron_top (D = $flatten\u_graph_engine.$procmux$2777_Y, Q = \u_graph_engine.edge_byte_idx, rval = 2'00).
Adding EN signal on $auto$ff.cc:337:slice$7262 ($sdff) from module spi_neuron_top (D = $flatten\u_graph_engine.$procmux$2777_Y, Q = \u_graph_engine.edge_byte_idx).
Adding SRST signal on $flatten\u_graph_engine.$procdff$5310 ($dff) from module spi_neuron_top (D = $flatten\u_graph_engine.$procmux$2796_Y, Q = \u_graph_engine.conn_i, rval = 6'000000).
Adding EN signal on $auto$ff.cc:337:slice$7274 ($sdff) from module spi_neuron_top (D = $flatten\u_graph_engine.$procmux$2796_Y, Q = \u_graph_engine.conn_i).
Adding SRST signal on $flatten\u_graph_engine.$procdff$5309 ($dff) from module spi_neuron_top (D = { $flatten\u_graph_engine.$procmux$2761_Y $flatten\u_graph_engine.$procmux$2260_Y }, Q = \u_graph_engine.out_id_acc, rval = 16'0000000000000000).
Adding EN signal on $auto$ff.cc:337:slice$7284 ($sdff) from module spi_neuron_top (D = \u_arbiter.c_rdata, Q = \u_graph_engine.out_id_acc [15:8]).
Adding EN signal on $auto$ff.cc:337:slice$7284 ($sdff) from module spi_neuron_top (D = \u_arbiter.c_rdata, Q = \u_graph_engine.out_id_acc [7:0]).
Adding SRST signal on $flatten\u_graph_engine.$procdff$5308 ($dff) from module spi_neuron_top (D = { $flatten\u_graph_engine.$procmux$2824_Y $flatten\u_graph_engine.$procmux$2281_Y }, Q = \u_graph_engine.n_conn_acc, rval = 16'0000000000000000).
Adding EN signal on $auto$ff.cc:337:slice$7291 ($sdff) from module spi_neuron_top (D = \u_arbiter.c_rdata, Q = \u_graph_engine.n_conn_acc [15:8]).
Adding EN signal on $auto$ff.cc:337:slice$7291 ($sdff) from module spi_neuron_top (D = \u_arbiter.c_rdata, Q = \u_graph_engine.n_conn_acc [7:0]).
Adding SRST signal on $flatten\u_graph_engine.$procdff$5307 ($dff) from module spi_neuron_top (D = { $flatten\u_graph_engine.$procmux$2329_Y $flatten\u_graph_engine.$procmux$2848_Y $flatten\u_graph_engine.$procmux$2304_Y }, Q = \u_graph_engine.conn_ptr_acc, rval = 24'000000000000000000000000).
Adding EN signal on $auto$ff.cc:337:slice$7298 ($sdff) from module spi_neuron_top (D = \u_arbiter.c_rdata, Q = \u_graph_engine.conn_ptr_acc [15:8]).
Adding EN signal on $auto$ff.cc:337:slice$7298 ($sdff) from module spi_neuron_top (D = \u_arbiter.c_rdata, Q = \u_graph_engine.conn_ptr_acc [23:16]).
Adding EN signal on $auto$ff.cc:337:slice$7298 ($sdff) from module spi_neuron_top (D = \u_arbiter.c_rdata, Q = \u_graph_engine.conn_ptr_acc [7:0]).
Adding SRST signal on $flatten\u_graph_engine.$procdff$5306 ($dff) from module spi_neuron_top (D = $flatten\u_graph_engine.$procmux$2869_Y, Q = \u_graph_engine.desc_addr, rval = 23'00000000000000000000000).
Adding EN signal on $auto$ff.cc:337:slice$7308 ($sdff) from module spi_neuron_top (D = $flatten\u_graph_engine.$procmux$2869_Y, Q = \u_graph_engine.desc_addr).
Adding SRST signal on $flatten\u_graph_engine.$procdff$5305 ($dff) from module spi_neuron_top (D = $flatten\u_graph_engine.$procmux$2892_Y, Q = \u_graph_engine.neuron_idx, rval = 16'0000000000000000).
Adding EN signal on $auto$ff.cc:337:slice$7322 ($sdff) from module spi_neuron_top (D = $flatten\u_graph_engine.$procmux$2892_Y, Q = \u_graph_engine.neuron_idx).
Adding SRST signal on $flatten\u_graph_engine.$procdff$5304 ($dff) from module spi_neuron_top (D = $flatten\u_graph_engine.$procmux$2924_Y, Q = \u_graph_engine.in_idx, rval = 16'0000000000000000).
Adding EN signal on $auto$ff.cc:337:slice$7336 ($sdff) from module spi_neuron_top (D = $flatten\u_graph_engine.$procmux$2924_Y, Q = \u_graph_engine.in_idx).
Adding SRST signal on $flatten\u_graph_engine.$procdff$5303 ($dff) from module spi_neuron_top (D = $flatten\u_graph_engine.$procmux$2946_Y, Q = \u_graph_engine.err, rval = 1'0).
Adding EN signal on $auto$ff.cc:337:slice$7348 ($sdff) from module spi_neuron_top (D = $flatten\u_graph_engine.$procmux$2946_Y, Q = \u_graph_engine.err).
Adding SRST signal on $flatten\u_graph_engine.$procdff$5302 ($dff) from module spi_neuron_top (D = $flatten\u_graph_engine.$procmux$2620_Y, Q = \u_graph_engine.done, rval = 1'0).
Adding SRST signal on $flatten\u_graph_engine.$procdff$5301 ($dff) from module spi_neuron_top (D = $flatten\u_graph_engine.$procmux$2964_Y, Q = \u_graph_engine.busy, rval = 1'0).
Adding EN signal on $auto$ff.cc:337:slice$7365 ($sdff) from module spi_neuron_top (D = $flatten\u_graph_engine.$procmux$2964_Y, Q = \u_graph_engine.busy).
Adding SRST signal on $flatten\u_graph_engine.$procdff$5300 ($dff) from module spi_neuron_top (D = $flatten\u_graph_engine.$procmux$3000_Y, Q = \u_graph_engine.desc_byte_idx, rval = 4'0000).
Adding EN signal on $auto$ff.cc:337:slice$7387 ($sdff) from module spi_neuron_top (D = $flatten\u_graph_engine.$procmux$3000_Y, Q = \u_graph_engine.desc_byte_idx).
Adding SRST signal on $flatten\u_graph_engine.$procdff$5298 ($dff) from module spi_neuron_top (D = $flatten\u_graph_engine.$procmux$3084_Y, Q = \u_graph_engine.ram_wdata, rval = 8'00000000).
Adding EN signal on $auto$ff.cc:337:slice$7407 ($sdff) from module spi_neuron_top (D = \u_graph_engine.u_neuron.y, Q = \u_graph_engine.ram_wdata).
Adding SRST signal on $flatten\u_graph_engine.$procdff$5297 ($dff) from module spi_neuron_top (D = $flatten\u_graph_engine.$procmux$3091_Y, Q = \u_graph_engine.ram_addr, rval = 23'00000000000000000000000).
Adding EN signal on $auto$ff.cc:337:slice$7409 ($sdff) from module spi_neuron_top (D = $flatten\u_graph_engine.$procmux$3091_Y, Q = \u_graph_engine.ram_addr).
Adding SRST signal on $flatten\u_graph_engine.$procdff$5296 ($dff) from module spi_neuron_top (D = $flatten\u_graph_engine.$procmux$3104_Y, Q = \u_graph_engine.ram_wr, rval = 1'0).
Adding EN signal on $auto$ff.cc:337:slice$7417 ($sdff) from module spi_neuron_top (D = $flatten\u_graph_engine.$procmux$3104_Y, Q = \u_graph_engine.ram_wr).
Adding SRST signal on $flatten\u_graph_engine.$procdff$5295 ($dff) from module spi_neuron_top (D = $flatten\u_graph_engine.$procmux$2581_Y, Q = \u_graph_engine.ram_req, rval = 1'0).
Adding SRST signal on $flatten\u_layer_sequencer.$procdff$5392 ($dff) from module spi_neuron_top (D = $flatten\u_layer_sequencer.$procmux$3248_Y, Q = \u_layer_sequencer.ram_req, rval = 1'0).
Adding SRST signal on $flatten\u_layer_sequencer.$procdff$5393 ($dff) from module spi_neuron_top (D = $flatten\u_layer_sequencer.$procmux$3588_Y, Q = \u_layer_sequencer.ram_wr, rval = 1'0).
Adding EN signal on $auto$ff.cc:337:slice$7427 ($sdff) from module spi_neuron_top (D = $flatten\u_layer_sequencer.$procmux$3588_Y, Q = \u_layer_sequencer.ram_wr).
Adding SRST signal on $flatten\u_layer_sequencer.$procdff$5394 ($dff) from module spi_neuron_top (D = $flatten\u_layer_sequencer.$procmux$3580_Y, Q = \u_layer_sequencer.ram_addr, rval = 23'00000000000000000000000).
Adding EN signal on $auto$ff.cc:337:slice$7431 ($sdff) from module spi_neuron_top (D = $flatten\u_layer_sequencer.$procmux$3580_Y, Q = \u_layer_sequencer.ram_addr).
Adding SRST signal on $flatten\u_layer_sequencer.$procdff$5395 ($dff) from module spi_neuron_top (D = $flatten\u_layer_sequencer.$procmux$3573_Y, Q = \u_layer_sequencer.ram_wdata, rval = 8'00000000).
Adding EN signal on $auto$ff.cc:337:slice$7435 ($sdff) from module spi_neuron_top (D = $flatten\u_layer_sequencer.$shiftx$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:291$791_Y, Q = \u_layer_sequencer.ram_wdata).
Adding SRST signal on $flatten\u_layer_sequencer.$procdff$5396 ($dff) from module spi_neuron_top (D = $flatten\u_layer_sequencer.$procmux$3258_Y, Q = \u_layer_sequencer.nm_start, rval = 1'0).
Adding SRST signal on $flatten\u_layer_sequencer.$procdff$5397 ($dff) from module spi_neuron_top (D = $flatten\u_layer_sequencer.$procmux$3563_Y, Q = \u_layer_sequencer.seq_busy, rval = 1'0).
Adding EN signal on $auto$ff.cc:337:slice$7438 ($sdff) from module spi_neuron_top (D = $flatten\u_layer_sequencer.$procmux$3563_Y, Q = \u_layer_sequencer.seq_busy).
Adding SRST signal on $flatten\u_layer_sequencer.$procdff$5398 ($dff) from module spi_neuron_top (D = $flatten\u_layer_sequencer.$procmux$3389_Y, Q = \u_layer_sequencer.seq_done, rval = 1'0).
Adding SRST signal on $flatten\u_layer_sequencer.$procdff$5404 ($dff) from module spi_neuron_top (D = $flatten\u_layer_sequencer.$procmux$3484_Y, Q = \u_layer_sequencer.nm_n_inputs, rval = 16'0000000000000000).
Adding EN signal on $auto$ff.cc:337:slice$7461 ($sdff) from module spi_neuron_top (D = \u_layer_sequencer.n_inputs_acc, Q = \u_layer_sequencer.nm_n_inputs).
Adding SRST signal on $flatten\u_layer_sequencer.$procdff$5400 ($dff) from module spi_neuron_top (D = $flatten\u_layer_sequencer.$procmux$3520_Y, Q = \u_layer_sequencer.nm_x_base, rval = 23'00000000000000000000000).
Adding EN signal on $auto$ff.cc:337:slice$7463 ($sdff) from module spi_neuron_top (D = $flatten\u_layer_sequencer.$ternary$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:259$786_Y, Q = \u_layer_sequencer.nm_x_base).
Adding SRST signal on $flatten\u_layer_sequencer.$procdff$5414 ($dff) from module spi_neuron_top (D = { $flatten\u_layer_sequencer.$procmux$3125_Y $flatten\u_layer_sequencer.$procmux$3139_Y }, Q = \u_layer_sequencer.n_neurons_acc, rval = 16'0000000000000000).
Adding EN signal on $auto$ff.cc:337:slice$7465 ($sdff) from module spi_neuron_top (D = \u_arbiter.c_rdata, Q = \u_layer_sequencer.n_neurons_acc [15:8]).
Adding EN signal on $auto$ff.cc:337:slice$7465 ($sdff) from module spi_neuron_top (D = \u_arbiter.c_rdata, Q = \u_layer_sequencer.n_neurons_acc [7:0]).
Adding SRST signal on $flatten\u_layer_sequencer.$procdff$5415 ($dff) from module spi_neuron_top (D = $flatten\u_layer_sequencer.$procmux$3303_Y, Q = \u_layer_sequencer.cur_sel, rval = 1'0).
Adding EN signal on $auto$ff.cc:337:slice$7472 ($sdff) from module spi_neuron_top (D = \u_layer_sequencer.write_sel, Q = \u_layer_sequencer.cur_sel).
Adding SRST signal on $flatten\u_layer_sequencer.$procdff$5416 ($dff) from module spi_neuron_top (D = $flatten\u_layer_sequencer.$procmux$3286_Y, Q = \u_layer_sequencer.write_sel, rval = 1'0).
Adding EN signal on $auto$ff.cc:337:slice$7478 ($sdff) from module spi_neuron_top (D = $flatten\u_layer_sequencer.$procmux$3286_Y, Q = \u_layer_sequencer.write_sel).
Adding SRST signal on $flatten\u_layer_sequencer.$procdff$5417 ($dff) from module spi_neuron_top (D = $flatten\u_layer_sequencer.$procmux$3269_Y, Q = \u_layer_sequencer.copy_idx, rval = 1'0).
Adding EN signal on $auto$ff.cc:337:slice$7492 ($sdff) from module spi_neuron_top (D = $flatten\u_layer_sequencer.$procmux$3269_Y, Q = \u_layer_sequencer.copy_idx).
Adding SRST signal on $flatten\u_layer_sequencer.$procdff$5401 ($dff) from module spi_neuron_top (D = $flatten\u_layer_sequencer.$procmux$3511_Y, Q = \u_layer_sequencer.nm_w_base, rval = 23'00000000000000000000000).
Adding EN signal on $auto$ff.cc:337:slice$7504 ($sdff) from module spi_neuron_top (D = \u_layer_sequencer.w_base_acc [22:0], Q = \u_layer_sequencer.nm_w_base).
Adding SRST signal on $flatten\u_layer_sequencer.$procdff$5402 ($dff) from module spi_neuron_top (D = $flatten\u_layer_sequencer.$procmux$3502_Y, Q = \u_layer_sequencer.nm_bias_addr, rval = 23'00000000000000000000000).
Adding EN signal on $auto$ff.cc:337:slice$7506 ($sdff) from module spi_neuron_top (D = \u_layer_sequencer.bias_addr_acc [22:0], Q = \u_layer_sequencer.nm_bias_addr).
Adding SRST signal on $flatten\u_layer_sequencer.$procdff$5403 ($dff) from module spi_neuron_top (D = $flatten\u_layer_sequencer.$procmux$3493_Y, Q = \u_layer_sequencer.nm_activation, rval = 2'01).
Adding EN signal on $auto$ff.cc:337:slice$7508 ($sdff) from module spi_neuron_top (D = \u_layer_sequencer.activation_acc [1:0], Q = \u_layer_sequencer.nm_activation).
Setting constant 0-bit at position 0 on $auto$ff.cc:337:slice$7218 ($sdffe) from module spi_neuron_top.
Setting constant 0-bit at position 1 on $auto$ff.cc:337:slice$7218 ($sdffe) from module spi_neuron_top.
Setting constant 0-bit at position 2 on $auto$ff.cc:337:slice$7218 ($sdffe) from module spi_neuron_top.
Setting constant 0-bit at position 0 on $auto$ff.cc:337:slice$6998 ($dffe) from module spi_neuron_top.
Setting constant 0-bit at position 1 on $auto$ff.cc:337:slice$6998 ($dffe) from module spi_neuron_top.
Setting constant 0-bit at position 2 on $auto$ff.cc:337:slice$6998 ($dffe) from module spi_neuron_top.
Setting constant 0-bit at position 3 on $auto$ff.cc:337:slice$6998 ($dffe) from module spi_neuron_top.
Setting constant 0-bit at position 4 on $auto$ff.cc:337:slice$6998 ($dffe) from module spi_neuron_top.
Setting constant 0-bit at position 5 on $auto$ff.cc:337:slice$6998 ($dffe) from module spi_neuron_top.
Setting constant 0-bit at position 6 on $auto$ff.cc:337:slice$6998 ($dffe) from module spi_neuron_top.
Setting constant 0-bit at position 7 on $auto$ff.cc:337:slice$6998 ($dffe) from module spi_neuron_top.
Setting constant 0-bit at position 22 on $auto$ff.cc:337:slice$6827 ($sdffe) from module spi_neuron_top.
Setting constant 0-bit at position 3 on $auto$ff.cc:337:slice$6448 ($sdffe) from module spi_neuron_top.
Setting constant 0-bit at position 4 on $auto$ff.cc:337:slice$6448 ($sdffe) from module spi_neuron_top.
Setting constant 0-bit at position 5 on $auto$ff.cc:337:slice$6448 ($sdffe) from module spi_neuron_top.
Setting constant 0-bit at position 6 on $auto$ff.cc:337:slice$6448 ($sdffe) from module spi_neuron_top.
Setting constant 0-bit at position 7 on $auto$ff.cc:337:slice$6448 ($sdffe) from module spi_neuron_top.
17.14.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \spi_neuron_top..
Removed 481 unused cells and 631 unused wires.
<suppressed ~482 debug messages>
17.14.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module spi_neuron_top.
<suppressed ~46 debug messages>
17.14.9. Rerunning OPT passes. (Maybe there is more to do..)
17.14.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \spi_neuron_top..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~541 debug messages>
17.14.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Optimizing cells in module \spi_neuron_top.
Performed a total of 0 changes.
17.14.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\spi_neuron_top'.
Computing hashes of 1653 cells of `\spi_neuron_top'.
Finding duplicate cells in `\spi_neuron_top'.
Computing hashes of 1511 cells of `\spi_neuron_top'.
Finding duplicate cells in `\spi_neuron_top'.
Computing hashes of 1499 cells of `\spi_neuron_top'.
Finding duplicate cells in `\spi_neuron_top'.
<suppressed ~462 debug messages>
Removed a total of 154 cells.
17.14.13. Executing OPT_DFF pass (perform DFF optimizations).
Setting constant 0-bit at position 22 on $auto$ff.cc:337:slice$6785 ($sdffe) from module spi_neuron_top.
Setting constant 0-bit at position 2 on $flatten\u_spi_engine.$procdff$5449 ($dff) from module spi_neuron_top.
17.14.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \spi_neuron_top..
Removed 0 unused cells and 154 unused wires.
<suppressed ~1 debug messages>
17.14.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module spi_neuron_top.
17.14.16. Rerunning OPT passes. (Maybe there is more to do..)
17.14.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \spi_neuron_top..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~550 debug messages>
17.14.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Optimizing cells in module \spi_neuron_top.
Performed a total of 0 changes.
17.14.19. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\spi_neuron_top'.
Computing hashes of 1499 cells of `\spi_neuron_top'.
Finding duplicate cells in `\spi_neuron_top'.
Removed a total of 0 cells.
17.14.20. Executing OPT_DFF pass (perform DFF optimizations).
Setting constant 0-bit at position 22 on $auto$ff.cc:337:slice$6490 ($sdffe) from module spi_neuron_top.
17.14.21. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \spi_neuron_top..
17.14.22. Executing OPT_EXPR pass (perform const folding).
Optimizing module spi_neuron_top.
17.14.23. Rerunning OPT passes. (Maybe there is more to do..)
17.14.24. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \spi_neuron_top..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~550 debug messages>
17.14.25. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Optimizing cells in module \spi_neuron_top.
Performed a total of 0 changes.
17.14.26. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\spi_neuron_top'.
Computing hashes of 1499 cells of `\spi_neuron_top'.
Finding duplicate cells in `\spi_neuron_top'.
Removed a total of 0 cells.
17.14.27. Executing OPT_DFF pass (perform DFF optimizations).
17.14.28. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \spi_neuron_top..
17.14.29. Executing OPT_EXPR pass (perform const folding).
Optimizing module spi_neuron_top.
17.14.30. Finished fast OPT passes. (There is nothing left to do.)
17.15. Executing WREDUCE pass (reducing word size of cells).
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:215$1056 (u_graph_engine.w_mem).
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:214$1057 (u_graph_engine.x_mem).
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:215$1058 (u_graph_engine.w_mem).
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:214$1059 (u_graph_engine.x_mem).
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:215$1060 (u_graph_engine.w_mem).
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:214$1061 (u_graph_engine.x_mem).
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:215$1062 (u_graph_engine.w_mem).
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:214$1063 (u_graph_engine.x_mem).
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:215$1064 (u_graph_engine.w_mem).
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:214$1065 (u_graph_engine.x_mem).
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:215$1066 (u_graph_engine.w_mem).
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:214$1067 (u_graph_engine.x_mem).
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:215$1068 (u_graph_engine.w_mem).
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:214$1069 (u_graph_engine.x_mem).
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:215$1070 (u_graph_engine.w_mem).
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:214$1071 (u_graph_engine.x_mem).
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:215$1072 (u_graph_engine.w_mem).
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:214$1073 (u_graph_engine.x_mem).
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:215$1074 (u_graph_engine.w_mem).
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:214$1075 (u_graph_engine.x_mem).
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:215$1076 (u_graph_engine.w_mem).
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:214$1077 (u_graph_engine.x_mem).
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:215$1078 (u_graph_engine.w_mem).
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:214$1079 (u_graph_engine.x_mem).
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:215$1080 (u_graph_engine.w_mem).
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:214$1081 (u_graph_engine.x_mem).
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:215$1082 (u_graph_engine.w_mem).
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:214$1083 (u_graph_engine.x_mem).
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:215$1084 (u_graph_engine.w_mem).
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:214$1085 (u_graph_engine.x_mem).
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:215$1086 (u_graph_engine.w_mem).
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:214$1087 (u_graph_engine.x_mem).
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:215$1088 (u_graph_engine.w_mem).
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:214$1089 (u_graph_engine.x_mem).
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:215$1090 (u_graph_engine.w_mem).
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:214$1091 (u_graph_engine.x_mem).
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:215$1092 (u_graph_engine.w_mem).
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:214$1093 (u_graph_engine.x_mem).
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:215$1094 (u_graph_engine.w_mem).
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:214$1095 (u_graph_engine.x_mem).
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:215$1096 (u_graph_engine.w_mem).
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:214$1097 (u_graph_engine.x_mem).
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:215$1098 (u_graph_engine.w_mem).
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:214$1099 (u_graph_engine.x_mem).
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:215$1100 (u_graph_engine.w_mem).
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:214$1101 (u_graph_engine.x_mem).
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:215$1102 (u_graph_engine.w_mem).
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:214$1103 (u_graph_engine.x_mem).
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:215$1104 (u_graph_engine.w_mem).
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:214$1105 (u_graph_engine.x_mem).
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:215$1106 (u_graph_engine.w_mem).
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:214$1107 (u_graph_engine.x_mem).
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:215$1108 (u_graph_engine.w_mem).
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:214$1109 (u_graph_engine.x_mem).
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:215$1110 (u_graph_engine.w_mem).
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:214$1111 (u_graph_engine.x_mem).
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:215$1112 (u_graph_engine.w_mem).
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:215$1054 (u_graph_engine.w_mem).
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:214$1053 (u_graph_engine.x_mem).
Removed top 1 address bits (of 6) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$5573 (u_graph_engine.x_mem).
Removed top 1 address bits (of 6) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$5574 (u_graph_engine.w_mem).
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:214$1055 (u_graph_engine.x_mem).
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:214$1049 (u_graph_engine.x_mem).
Removed top 28 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_spi_engine.$auto$mem.cc:351:emit$1542 ($flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1540).
Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$5509 (u_graph_engine.x_mem).
Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$5510 (u_graph_engine.w_mem).
Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$5511 (u_graph_engine.x_mem).
Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$5512 (u_graph_engine.w_mem).
Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$5513 (u_graph_engine.x_mem).
Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$5514 (u_graph_engine.w_mem).
Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$5515 (u_graph_engine.x_mem).
Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$5516 (u_graph_engine.w_mem).
Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$5517 (u_graph_engine.x_mem).
Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$5518 (u_graph_engine.w_mem).
Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$5519 (u_graph_engine.x_mem).
Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$5520 (u_graph_engine.w_mem).
Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$5521 (u_graph_engine.x_mem).
Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$5522 (u_graph_engine.w_mem).
Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$5523 (u_graph_engine.x_mem).
Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$5524 (u_graph_engine.w_mem).
Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$5525 (u_graph_engine.x_mem).
Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$5526 (u_graph_engine.w_mem).
Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$5527 (u_graph_engine.x_mem).
Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$5528 (u_graph_engine.w_mem).
Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$5529 (u_graph_engine.x_mem).
Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$5530 (u_graph_engine.w_mem).
Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$5531 (u_graph_engine.x_mem).
Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$5532 (u_graph_engine.w_mem).
Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$5533 (u_graph_engine.x_mem).
Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$5534 (u_graph_engine.w_mem).
Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$5535 (u_graph_engine.x_mem).
Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$5536 (u_graph_engine.w_mem).
Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$5537 (u_graph_engine.x_mem).
Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$5538 (u_graph_engine.w_mem).
Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$5539 (u_graph_engine.x_mem).
Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$5540 (u_graph_engine.w_mem).
Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$5541 (u_graph_engine.x_mem).
Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$5542 (u_graph_engine.w_mem).
Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$5543 (u_graph_engine.x_mem).
Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$5544 (u_graph_engine.w_mem).
Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$5545 (u_graph_engine.x_mem).
Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$5546 (u_graph_engine.w_mem).
Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$5547 (u_graph_engine.x_mem).
Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$5548 (u_graph_engine.w_mem).
Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$5549 (u_graph_engine.x_mem).
Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$5550 (u_graph_engine.w_mem).
Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$5551 (u_graph_engine.x_mem).
Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$5552 (u_graph_engine.w_mem).
Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$5553 (u_graph_engine.x_mem).
Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$5554 (u_graph_engine.w_mem).
Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$5555 (u_graph_engine.x_mem).
Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$5556 (u_graph_engine.w_mem).
Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$5557 (u_graph_engine.x_mem).
Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$5558 (u_graph_engine.w_mem).
Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$5559 (u_graph_engine.x_mem).
Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$5560 (u_graph_engine.w_mem).
Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$5561 (u_graph_engine.x_mem).
Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$5562 (u_graph_engine.w_mem).
Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$5563 (u_graph_engine.x_mem).
Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$5564 (u_graph_engine.w_mem).
Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$5565 (u_graph_engine.x_mem).
Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$5566 (u_graph_engine.w_mem).
Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$5567 (u_graph_engine.x_mem).
Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$5568 (u_graph_engine.w_mem).
Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$5569 (u_graph_engine.x_mem).
Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$5570 (u_graph_engine.w_mem).
Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$5571 (u_graph_engine.x_mem).
Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$5572 (u_graph_engine.w_mem).
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:129$1173 (u_neuron_memory.x_mem).
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:130$1174 (u_neuron_memory.w_mem).
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:129$1175 (u_neuron_memory.x_mem).
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:130$1176 (u_neuron_memory.w_mem).
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:129$1177 (u_neuron_memory.x_mem).
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:130$1178 (u_neuron_memory.w_mem).
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:129$1179 (u_neuron_memory.x_mem).
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:130$1180 (u_neuron_memory.w_mem).
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:129$1181 (u_neuron_memory.x_mem).
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:130$1182 (u_neuron_memory.w_mem).
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:129$1183 (u_neuron_memory.x_mem).
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:130$1184 (u_neuron_memory.w_mem).
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:129$1185 (u_neuron_memory.x_mem).
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:130$1186 (u_neuron_memory.w_mem).
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:129$1187 (u_neuron_memory.x_mem).
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:130$1188 (u_neuron_memory.w_mem).
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:129$1189 (u_neuron_memory.x_mem).
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:130$1190 (u_neuron_memory.w_mem).
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:129$1191 (u_neuron_memory.x_mem).
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:130$1192 (u_neuron_memory.w_mem).
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:129$1193 (u_neuron_memory.x_mem).
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:130$1194 (u_neuron_memory.w_mem).
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:129$1195 (u_neuron_memory.x_mem).
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:130$1196 (u_neuron_memory.w_mem).
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:129$1197 (u_neuron_memory.x_mem).
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:130$1198 (u_neuron_memory.w_mem).
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:129$1199 (u_neuron_memory.x_mem).
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:130$1200 (u_neuron_memory.w_mem).
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:129$1201 (u_neuron_memory.x_mem).
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:130$1202 (u_neuron_memory.w_mem).
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:129$1203 (u_neuron_memory.x_mem).
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:130$1204 (u_neuron_memory.w_mem).
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:129$1205 (u_neuron_memory.x_mem).
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:130$1206 (u_neuron_memory.w_mem).
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:129$1207 (u_neuron_memory.x_mem).
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:130$1208 (u_neuron_memory.w_mem).
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:129$1209 (u_neuron_memory.x_mem).
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:130$1210 (u_neuron_memory.w_mem).
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:129$1211 (u_neuron_memory.x_mem).
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:130$1212 (u_neuron_memory.w_mem).
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:129$1213 (u_neuron_memory.x_mem).
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:130$1214 (u_neuron_memory.w_mem).
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:129$1215 (u_neuron_memory.x_mem).
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:130$1216 (u_neuron_memory.w_mem).
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:129$1217 (u_neuron_memory.x_mem).
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:130$1218 (u_neuron_memory.w_mem).
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:129$1219 (u_neuron_memory.x_mem).
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:130$1220 (u_neuron_memory.w_mem).
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:129$1221 (u_neuron_memory.x_mem).
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:130$1222 (u_neuron_memory.w_mem).
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:129$1223 (u_neuron_memory.x_mem).
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:130$1224 (u_neuron_memory.w_mem).
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:129$1225 (u_neuron_memory.x_mem).
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:130$1226 (u_neuron_memory.w_mem).
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:129$1227 (u_neuron_memory.x_mem).
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:130$1228 (u_neuron_memory.w_mem).
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:129$1229 (u_neuron_memory.x_mem).
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:130$1230 (u_neuron_memory.w_mem).
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:129$1231 (u_neuron_memory.x_mem).
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:130$1232 (u_neuron_memory.w_mem).
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:129$1233 (u_neuron_memory.x_mem).
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:130$1234 (u_neuron_memory.w_mem).
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:129$1235 (u_neuron_memory.x_mem).
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:130$1236 (u_neuron_memory.w_mem).
Removed top 32 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\y_reg$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:140$1237 (u_neuron_memory.y_reg).
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:215$1050 (u_graph_engine.w_mem).
Removed top 32 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_neuron_memory.$auto$proc_memwr.cc:45:proc_memwr$5505 (u_neuron_memory.y_reg).
Removed top 1 address bits (of 6) from memory init port spi_neuron_top.$flatten\u_neuron_memory.$auto$proc_memwr.cc:45:proc_memwr$5506 (u_neuron_memory.x_mem).
Removed top 1 address bits (of 6) from memory init port spi_neuron_top.$flatten\u_neuron_memory.$auto$proc_memwr.cc:45:proc_memwr$5507 (u_neuron_memory.w_mem).
Removed top 1 address bits (of 1) from memory init port spi_neuron_top.$flatten\u_neuron_memory.$auto$proc_memwr.cc:45:proc_memwr$5508 (u_neuron_memory.y_reg).
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:214$1051 (u_graph_engine.x_mem).
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:215$1052 (u_graph_engine.w_mem).
Removed top 1 bits (of 3) from FF cell spi_neuron_top.$auto$ff.cc:337:slice$7514 ($dff).
Removed top 1 bits (of 2) from port B of cell spi_neuron_top.$auto$opt_dff.cc:320:make_patterns_logic$7313 ($ne).
Removed top 1 bits (of 8) from FF cell spi_neuron_top.$auto$ff.cc:337:slice$7302 ($sdffe).
Removed top 22 bits (of 23) from FF cell spi_neuron_top.$auto$ff.cc:337:slice$7190 ($sdffe).
Removed top 1 bits (of 8) from FF cell spi_neuron_top.$auto$ff.cc:337:slice$7133 ($sdffe).
Removed top 1 bits (of 8) from FF cell spi_neuron_top.$auto$ff.cc:337:slice$7123 ($sdffe).
Removed top 6 bits (of 8) from FF cell spi_neuron_top.$auto$ff.cc:337:slice$7116 ($sdffe).
Removed top 1 bits (of 2) from port B of cell spi_neuron_top.$auto$opt_dff.cc:320:make_patterns_logic$7022 ($ne).
Removed top 1 bits (of 2) from port B of cell spi_neuron_top.$auto$opt_dff.cc:320:make_patterns_logic$7020 ($ne).
Removed top 1 bits (of 2) from port B of cell spi_neuron_top.$auto$opt_dff.cc:320:make_patterns_logic$6966 ($ne).
Removed top 1 bits (of 8) from FF cell spi_neuron_top.$auto$ff.cc:337:slice$6964 ($sdffe).
Removed top 1 bits (of 8) from FF cell spi_neuron_top.$auto$ff.cc:337:slice$6954 ($sdffe).
Removed top 1 bits (of 2) from port B of cell spi_neuron_top.$auto$opt_dff.cc:320:make_patterns_logic$6800 ($ne).
Removed top 1 bits (of 2) from port B of cell spi_neuron_top.$auto$opt_dff.cc:320:make_patterns_logic$6648 ($ne).
Removed top 1 bits (of 2) from port B of cell spi_neuron_top.$auto$opt_dff.cc:320:make_patterns_logic$6602 ($ne).
Removed top 8 bits (of 24) from FF cell spi_neuron_top.$auto$ff.cc:337:slice$6592 ($sdffe).
Removed top 1 bits (of 2) from port B of cell spi_neuron_top.$auto$opt_dff.cc:320:make_patterns_logic$6565 ($ne).
Removed top 1 bits (of 2) from port B of cell spi_neuron_top.$auto$opt_dff.cc:320:make_patterns_logic$6555 ($ne).
Removed top 1 bits (of 2) from port B of cell spi_neuron_top.$auto$opt_dff.cc:320:make_patterns_logic$6539 ($ne).
Removed top 1 bits (of 2) from port B of cell spi_neuron_top.$auto$opt_dff.cc:320:make_patterns_logic$6537 ($ne).
Removed top 1 bits (of 2) from port B of cell spi_neuron_top.$auto$opt_dff.cc:320:make_patterns_logic$6509 ($ne).
Removed top 1 bits (of 2) from port B of cell spi_neuron_top.$auto$opt_dff.cc:320:make_patterns_logic$6507 ($ne).
Removed top 1 bits (of 2) from port B of cell spi_neuron_top.$auto$opt_dff.cc:320:make_patterns_logic$6465 ($ne).
Removed top 22 bits (of 23) from FF cell spi_neuron_top.$auto$ff.cc:337:slice$6438 ($sdffe).
Removed top 1 bits (of 4) from port B of cell spi_neuron_top.$auto$fsm_map.cc:77:implement_pattern_cache$6374 ($eq).
Removed top 1 bits (of 3) from port B of cell spi_neuron_top.$auto$fsm_map.cc:77:implement_pattern_cache$6335 ($eq).
Removed top 2 bits (of 4) from port B of cell spi_neuron_top.$auto$fsm_map.cc:77:implement_pattern_cache$6265 ($eq).
Removed top 2 bits (of 4) from port B of cell spi_neuron_top.$auto$fsm_map.cc:77:implement_pattern_cache$6234 ($eq).
Removed top 1 bits (of 3) from port B of cell spi_neuron_top.$auto$fsm_map.cc:77:implement_pattern_cache$6106 ($eq).
Removed top 1 bits (of 3) from port B of cell spi_neuron_top.$auto$fsm_map.cc:77:implement_pattern_cache$6034 ($eq).
Removed top 1 bits (of 3) from port B of cell spi_neuron_top.$auto$fsm_map.cc:77:implement_pattern_cache$6029 ($eq).
Removed top 2 bits (of 4) from port B of cell spi_neuron_top.$auto$fsm_map.cc:77:implement_pattern_cache$5961 ($eq).
Removed top 1 bits (of 3) from port B of cell spi_neuron_top.$auto$fsm_map.cc:77:implement_pattern_cache$5953 ($eq).
Removed top 1 bits (of 3) from port B of cell spi_neuron_top.$auto$fsm_map.cc:77:implement_pattern_cache$5949 ($eq).
Removed top 1 bits (of 3) from port B of cell spi_neuron_top.$auto$fsm_map.cc:77:implement_pattern_cache$5936 ($eq).
Removed top 1 bits (of 3) from port B of cell spi_neuron_top.$auto$fsm_map.cc:77:implement_pattern_cache$5922 ($eq).
Removed top 1 bits (of 2) from port B of cell spi_neuron_top.$auto$fsm_map.cc:77:implement_pattern_cache$5916 ($eq).
Removed top 1 bits (of 4) from port B of cell spi_neuron_top.$auto$fsm_map.cc:77:implement_pattern_cache$5861 ($eq).
Removed top 1 bits (of 3) from port B of cell spi_neuron_top.$auto$fsm_map.cc:77:implement_pattern_cache$5826 ($eq).
Removed top 1 bits (of 3) from port B of cell spi_neuron_top.$auto$fsm_map.cc:77:implement_pattern_cache$5801 ($eq).
Removed top 15 bits (of 16) from mux cell spi_neuron_top.$ternary$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_neuron_top.v:289$620 ($mux).
Removed top 11 bits (of 14) from port B of cell spi_neuron_top.$flatten\u_psram_ctrl.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/psram_controller.v:292$1245 ($eq).
Removed top 23 bits (of 32) from port B of cell spi_neuron_top.$flatten\u_neuron_memory.\u_neuron.$shiftx$/tmp/before_rewrite/neuron_parallel.v:101$627 ($shiftx).
Removed top 23 bits (of 32) from port B of cell spi_neuron_top.$flatten\u_neuron_memory.\u_neuron.$shiftx$/tmp/before_rewrite/neuron_parallel.v:107$631 ($shiftx).
Removed top 24 bits (of 32) from port B of cell spi_neuron_top.$flatten\u_neuron_memory.\u_neuron.$add$/tmp/before_rewrite/neuron_parallel.v:128$632 ($add).
Removed top 24 bits (of 32) from port B of cell spi_neuron_top.$flatten\u_neuron_memory.\u_neuron.$lt$/tmp/before_rewrite/neuron_parallel.v:165$639 ($lt).
Removed top 31 bits (of 32) from port B of cell spi_neuron_top.$flatten\u_neuron_memory.\u_neuron.$le$/tmp/before_rewrite/neuron_parallel.v:176$640 ($le).
Removed top 24 bits (of 32) from port B of cell spi_neuron_top.$flatten\u_neuron_memory.\u_neuron.$gt$/tmp/before_rewrite/neuron_parallel.v:178$641 ($gt).
Converting cell spi_neuron_top.$flatten\u_neuron_memory.\u_neuron.\u_mac8.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101$1307 ($add) from unsigned to signed.
Removed top 16 bits (of 32) from port A of cell spi_neuron_top.$flatten\u_neuron_memory.\u_neuron.\u_mac8.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101$1307 ($add).
Removed top 16 bits (of 32) from port B of cell spi_neuron_top.$flatten\u_neuron_memory.\u_neuron.\u_mac8.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101$1307 ($add).
Removed top 15 bits (of 32) from port Y of cell spi_neuron_top.$flatten\u_neuron_memory.\u_neuron.\u_mac8.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101$1307 ($add).
Converting cell spi_neuron_top.$flatten\u_neuron_memory.\u_neuron.\u_mac8.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101$1305 ($add) from unsigned to signed.
Removed top 16 bits (of 32) from port A of cell spi_neuron_top.$flatten\u_neuron_memory.\u_neuron.\u_mac8.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101$1305 ($add).
Removed top 16 bits (of 32) from port B of cell spi_neuron_top.$flatten\u_neuron_memory.\u_neuron.\u_mac8.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101$1305 ($add).
Removed top 15 bits (of 32) from port Y of cell spi_neuron_top.$flatten\u_neuron_memory.\u_neuron.\u_mac8.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101$1305 ($add).
Converting cell spi_neuron_top.$flatten\u_neuron_memory.\u_neuron.\u_mac8.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101$1303 ($add) from unsigned to signed.
Removed top 16 bits (of 32) from port A of cell spi_neuron_top.$flatten\u_neuron_memory.\u_neuron.\u_mac8.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101$1303 ($add).
Removed top 16 bits (of 32) from port B of cell spi_neuron_top.$flatten\u_neuron_memory.\u_neuron.\u_mac8.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101$1303 ($add).
Removed top 15 bits (of 32) from port Y of cell spi_neuron_top.$flatten\u_neuron_memory.\u_neuron.\u_mac8.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101$1303 ($add).
Converting cell spi_neuron_top.$flatten\u_neuron_memory.\u_neuron.\u_mac8.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101$1301 ($add) from unsigned to signed.
Removed top 16 bits (of 32) from port A of cell spi_neuron_top.$flatten\u_neuron_memory.\u_neuron.\u_mac8.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101$1301 ($add).
Removed top 16 bits (of 32) from port B of cell spi_neuron_top.$flatten\u_neuron_memory.\u_neuron.\u_mac8.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101$1301 ($add).
Removed top 15 bits (of 32) from port Y of cell spi_neuron_top.$flatten\u_neuron_memory.\u_neuron.\u_mac8.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101$1301 ($add).
Removed top 1 bits (of 6) from mux cell spi_neuron_top.$flatten\u_neuron_memory.$procmux$2014 ($mux).
Removed top 1 bits (of 6) from mux cell spi_neuron_top.$flatten\u_neuron_memory.$procmux$2005 ($mux).
Removed cell spi_neuron_top.$flatten\u_neuron_memory.$procmux$1996 ($mux).
Removed top 1 bits (of 6) from mux cell spi_neuron_top.$flatten\u_neuron_memory.$procmux$1932 ($mux).
Removed top 1 bits (of 6) from mux cell spi_neuron_top.$flatten\u_neuron_memory.$procmux$1902 ($mux).
Removed cell spi_neuron_top.$flatten\u_neuron_memory.$procmux$1875 ($mux).
Removed top 1 bits (of 6) from mux cell spi_neuron_top.$flatten\u_neuron_memory.$procmux$1816 ($mux).
Removed cell spi_neuron_top.$flatten\u_neuron_memory.$procmux$1780 ($mux).
Removed top 23 bits (of 32) from port B of cell spi_neuron_top.$flatten\u_graph_engine.\u_neuron.$shiftx$/tmp/before_rewrite/neuron_parallel.v:101$627 ($shiftx).
Removed top 23 bits (of 32) from port B of cell spi_neuron_top.$flatten\u_graph_engine.\u_neuron.$shiftx$/tmp/before_rewrite/neuron_parallel.v:107$631 ($shiftx).
Removed top 24 bits (of 32) from port B of cell spi_neuron_top.$flatten\u_graph_engine.\u_neuron.$add$/tmp/before_rewrite/neuron_parallel.v:128$632 ($add).
Removed top 24 bits (of 32) from port B of cell spi_neuron_top.$flatten\u_graph_engine.\u_neuron.$lt$/tmp/before_rewrite/neuron_parallel.v:165$639 ($lt).
Removed top 31 bits (of 32) from port B of cell spi_neuron_top.$flatten\u_graph_engine.\u_neuron.$le$/tmp/before_rewrite/neuron_parallel.v:176$640 ($le).
Removed top 24 bits (of 32) from port B of cell spi_neuron_top.$flatten\u_graph_engine.\u_neuron.$gt$/tmp/before_rewrite/neuron_parallel.v:178$641 ($gt).
Converting cell spi_neuron_top.$flatten\u_graph_engine.\u_neuron.\u_mac8.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101$1307 ($add) from unsigned to signed.
Removed top 16 bits (of 32) from port A of cell spi_neuron_top.$flatten\u_graph_engine.\u_neuron.\u_mac8.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101$1307 ($add).
Removed top 16 bits (of 32) from port B of cell spi_neuron_top.$flatten\u_graph_engine.\u_neuron.\u_mac8.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101$1307 ($add).
Removed top 15 bits (of 32) from port Y of cell spi_neuron_top.$flatten\u_graph_engine.\u_neuron.\u_mac8.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101$1307 ($add).
Converting cell spi_neuron_top.$flatten\u_graph_engine.\u_neuron.\u_mac8.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101$1305 ($add) from unsigned to signed.
Removed top 16 bits (of 32) from port A of cell spi_neuron_top.$flatten\u_graph_engine.\u_neuron.\u_mac8.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101$1305 ($add).
Removed top 16 bits (of 32) from port B of cell spi_neuron_top.$flatten\u_graph_engine.\u_neuron.\u_mac8.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101$1305 ($add).
Removed top 15 bits (of 32) from port Y of cell spi_neuron_top.$flatten\u_graph_engine.\u_neuron.\u_mac8.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101$1305 ($add).
Converting cell spi_neuron_top.$flatten\u_graph_engine.\u_neuron.\u_mac8.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101$1303 ($add) from unsigned to signed.
Removed top 16 bits (of 32) from port A of cell spi_neuron_top.$flatten\u_graph_engine.\u_neuron.\u_mac8.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101$1303 ($add).
Removed top 16 bits (of 32) from port B of cell spi_neuron_top.$flatten\u_graph_engine.\u_neuron.\u_mac8.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101$1303 ($add).
Removed top 15 bits (of 32) from port Y of cell spi_neuron_top.$flatten\u_graph_engine.\u_neuron.\u_mac8.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101$1303 ($add).
Converting cell spi_neuron_top.$flatten\u_graph_engine.\u_neuron.\u_mac8.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101$1301 ($add) from unsigned to signed.
Removed top 16 bits (of 32) from port A of cell spi_neuron_top.$flatten\u_graph_engine.\u_neuron.\u_mac8.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101$1301 ($add).
Removed top 16 bits (of 32) from port B of cell spi_neuron_top.$flatten\u_graph_engine.\u_neuron.\u_mac8.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101$1301 ($add).
Removed top 15 bits (of 32) from port Y of cell spi_neuron_top.$flatten\u_graph_engine.\u_neuron.\u_mac8.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101$1301 ($add).
Removed top 3 bits (of 4) from port B of cell spi_neuron_top.$flatten\u_graph_engine.$procmux$2845_CMP0 ($eq).
Removed top 2 bits (of 4) from port B of cell spi_neuron_top.$flatten\u_graph_engine.$procmux$2821_CMP0 ($eq).
Removed top 1 bits (of 4) from port B of cell spi_neuron_top.$flatten\u_graph_engine.$procmux$2758_CMP0 ($eq).
Removed top 1 bits (of 4) from port B of cell spi_neuron_top.$flatten\u_graph_engine.$procmux$2680_CMP0 ($eq).
Removed top 1 bits (of 6) from mux cell spi_neuron_top.$flatten\u_graph_engine.$procmux$2641 ($mux).
Removed top 1 bits (of 6) from mux cell spi_neuron_top.$flatten\u_graph_engine.$procmux$2349 ($mux).
Removed top 2 bits (of 4) from port B of cell spi_neuron_top.$flatten\u_graph_engine.$procmux$2301_CMP0 ($eq).
Removed top 1 bits (of 4) from port B of cell spi_neuron_top.$flatten\u_graph_engine.$procmux$2278_CMP0 ($eq).
Removed top 1 bits (of 4) from port B of cell spi_neuron_top.$flatten\u_graph_engine.$procmux$2257_CMP0 ($eq).
Removed top 1 bits (of 2) from port B of cell spi_neuron_top.$flatten\u_graph_engine.$procmux$2238_CMP0 ($eq).
Removed top 28 bits (of 32) from port B of cell spi_neuron_top.$flatten\u_graph_engine.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:533$1043 ($add).
Removed top 9 bits (of 32) from port Y of cell spi_neuron_top.$flatten\u_graph_engine.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:533$1043 ($add).
Removed top 15 bits (of 16) from port B of cell spi_neuron_top.$flatten\u_graph_engine.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:532$1042 ($add).
Removed top 15 bits (of 16) from port B of cell spi_neuron_top.$flatten\u_graph_engine.$sub$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:527$1040 ($sub).
Removed top 1 bits (of 2) from port B of cell spi_neuron_top.$flatten\u_graph_engine.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:478$1036 ($add).
Removed top 3 bits (of 16) from port B of cell spi_neuron_top.$flatten\u_graph_engine.$ge$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:458$1034 ($ge).
Removed top 3 bits (of 16) from port B of cell spi_neuron_top.$flatten\u_graph_engine.$ge$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:457$1032 ($ge).
Removed top 9 bits (of 32) from port Y of cell spi_neuron_top.$flatten\u_graph_engine.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:430$1029 ($add).
Removed top 9 bits (of 32) from port A of cell spi_neuron_top.$flatten\u_graph_engine.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:430$1029 ($add).
Removed top 24 bits (of 32) from port B of cell spi_neuron_top.$flatten\u_graph_engine.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:430$1028 ($add).
Removed top 9 bits (of 32) from port Y of cell spi_neuron_top.$flatten\u_graph_engine.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:430$1028 ($add).
Removed top 3 bits (of 4) from port B of cell spi_neuron_top.$flatten\u_graph_engine.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:401$1025 ($add).
Removed top 29 bits (of 32) from port B of cell spi_neuron_top.$flatten\u_graph_engine.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:394$1022 ($add).
Removed top 16 bits (of 32) from port Y of cell spi_neuron_top.$flatten\u_graph_engine.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:394$1022 ($add).
Removed top 15 bits (of 16) from port B of cell spi_neuron_top.$flatten\u_graph_engine.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:350$1019 ($add).
Removed top 15 bits (of 16) from port B of cell spi_neuron_top.$flatten\u_graph_engine.$sub$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:346$1017 ($sub).
Removed top 3 bits (of 4) from port B of cell spi_neuron_top.$flatten\u_layer_sequencer.$procmux$3378_CMP0 ($eq).
Removed top 1 bits (of 4) from port B of cell spi_neuron_top.$flatten\u_layer_sequencer.$procmux$3355_CMP0 ($eq).
Removed top 1 bits (of 4) from port B of cell spi_neuron_top.$flatten\u_layer_sequencer.$procmux$3337_CMP0 ($eq).
Removed top 1 bits (of 4) from port B of cell spi_neuron_top.$flatten\u_layer_sequencer.$procmux$3317_CMP0 ($eq).
Removed top 2 bits (of 4) from port B of cell spi_neuron_top.$flatten\u_layer_sequencer.$procmux$3214_CMP0 ($eq).
Removed top 2 bits (of 4) from port B of cell spi_neuron_top.$flatten\u_layer_sequencer.$procmux$3192_CMP0 ($eq).
Removed top 1 bits (of 4) from port B of cell spi_neuron_top.$flatten\u_layer_sequencer.$procmux$3171_CMP0 ($eq).
Removed top 28 bits (of 32) from port B of cell spi_neuron_top.$flatten\u_layer_sequencer.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:317$798 ($add).
Removed top 9 bits (of 32) from port Y of cell spi_neuron_top.$flatten\u_layer_sequencer.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:317$798 ($add).
Removed top 7 bits (of 8) from port B of cell spi_neuron_top.$flatten\u_layer_sequencer.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:316$797 ($add).
Removed top 7 bits (of 8) from port B of cell spi_neuron_top.$flatten\u_layer_sequencer.$sub$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:303$794 ($sub).
Removed top 27 bits (of 32) from port B of cell spi_neuron_top.$flatten\u_layer_sequencer.$shiftx$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:291$791 ($shiftx).
Removed top 3 bits (of 4) from port B of cell spi_neuron_top.$flatten\u_layer_sequencer.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:239$783 ($add).
Removed top 2 bits (of 8) from port B of cell spi_neuron_top.$flatten\u_spi_engine.$procmux$4656_CMP0 ($eq).
Removed top 2 bits (of 8) from port B of cell spi_neuron_top.$flatten\u_spi_engine.$procmux$4648_CMP0 ($eq).
Removed top 2 bits (of 8) from port B of cell spi_neuron_top.$flatten\u_spi_engine.$procmux$4638_CMP0 ($eq).
Removed top 7 bits (of 8) from port B of cell spi_neuron_top.$flatten\u_spi_engine.$procmux$4530_CMP0 ($eq).
Removed top 6 bits (of 8) from port B of cell spi_neuron_top.$flatten\u_spi_engine.$procmux$4491_CMP0 ($eq).
Removed top 5 bits (of 8) from port B of cell spi_neuron_top.$flatten\u_spi_engine.$procmux$4453_CMP0 ($eq).
Removed top 5 bits (of 8) from port B of cell spi_neuron_top.$flatten\u_spi_engine.$procmux$4419_CMP0 ($eq).
Removed top 4 bits (of 8) from port B of cell spi_neuron_top.$flatten\u_spi_engine.$procmux$4386_CMP0 ($eq).
Removed top 6 bits (of 8) from port B of cell spi_neuron_top.$flatten\u_spi_engine.$procmux$4354_CMP0 ($eq).
Removed top 5 bits (of 8) from port B of cell spi_neuron_top.$flatten\u_spi_engine.$procmux$4317_CMP0 ($eq).
Removed top 5 bits (of 8) from port B of cell spi_neuron_top.$flatten\u_spi_engine.$procmux$4281_CMP0 ($eq).
Removed top 4 bits (of 8) from port B of cell spi_neuron_top.$flatten\u_spi_engine.$procmux$4235_CMP0 ($eq).
Removed top 4 bits (of 8) from port B of cell spi_neuron_top.$flatten\u_spi_engine.$procmux$4207_CMP0 ($eq).
Removed top 4 bits (of 8) from port B of cell spi_neuron_top.$flatten\u_spi_engine.$procmux$4176_CMP0 ($eq).
Removed top 3 bits (of 8) from port B of cell spi_neuron_top.$flatten\u_spi_engine.$procmux$4150_CMP0 ($eq).
Removed top 2 bits (of 8) from port B of cell spi_neuron_top.$flatten\u_spi_engine.$procmux$4149_CMP0 ($eq).
Removed top 3 bits (of 8) from port B of cell spi_neuron_top.$flatten\u_spi_engine.$procmux$4148_CMP0 ($eq).
Removed top 6 bits (of 8) from port B of cell spi_neuron_top.$flatten\u_spi_engine.$procmux$4017_CMP1 ($eq).
Removed top 7 bits (of 8) from port B of cell spi_neuron_top.$flatten\u_spi_engine.$procmux$4017_CMP0 ($eq).
Removed top 8 bits (of 24) from mux cell spi_neuron_top.$flatten\u_spi_engine.$procmux$4002 ($pmux).
Removed top 8 bits (of 24) from mux cell spi_neuron_top.$flatten\u_spi_engine.$procmux$4000 ($mux).
Removed top 2 bits (of 8) from port B of cell spi_neuron_top.$flatten\u_spi_engine.$procmux$3848_CMP0 ($eq).
Removed top 2 bits (of 8) from port B of cell spi_neuron_top.$flatten\u_spi_engine.$procmux$3847_CMP0 ($eq).
Removed top 2 bits (of 8) from port B of cell spi_neuron_top.$flatten\u_spi_engine.$procmux$3846_CMP0 ($eq).
Removed top 2 bits (of 8) from port B of cell spi_neuron_top.$flatten\u_spi_engine.$procmux$3712_CMP0 ($eq).
Removed top 3 bits (of 4) from port B of cell spi_neuron_top.$flatten\u_spi_engine.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:710$779 ($add).
Removed top 3 bits (of 4) from port B of cell spi_neuron_top.$flatten\u_spi_engine.$sub$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:707$777 ($sub).
Removed top 6 bits (of 8) from port B of cell spi_neuron_top.$flatten\u_spi_engine.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:674$776 ($eq).
Removed top 15 bits (of 16) from port B of cell spi_neuron_top.$flatten\u_spi_engine.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:644$774 ($eq).
Removed top 15 bits (of 16) from port B of cell spi_neuron_top.$flatten\u_spi_engine.$sub$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:642$773 ($sub).
Removed top 1 bits (of 2) from port B of cell spi_neuron_top.$flatten\u_spi_engine.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:561$768 ($add).
Removed top 7 bits (of 8) from port B of cell spi_neuron_top.$flatten\u_spi_engine.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:549$767 ($eq).
Removed top 1 bits (of 2) from port B of cell spi_neuron_top.$flatten\u_spi_engine.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:540$765 ($eq).
Removed top 3 bits (of 8) from port B of cell spi_neuron_top.$flatten\u_spi_engine.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:493$763 ($eq).
Removed top 24 bits (of 32) from port B of cell spi_neuron_top.$flatten\u_spi_engine.$shiftx$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:277$759 ($shiftx).
Removed top 31 bits (of 32) from port B of cell spi_neuron_top.$flatten\u_spi_engine.$lt$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:276$756 ($lt).
Removed top 1 bits (of 8) from mux cell spi_neuron_top.$flatten\u_spi_slave.$procmux$5164 ($mux).
Removed top 1 bits (of 8) from mux cell spi_neuron_top.$flatten\u_spi_slave.$procmux$5161 ($mux).
Removed top 1 bits (of 8) from mux cell spi_neuron_top.$flatten\u_spi_slave.$procmux$5158 ($mux).
Removed top 1 bits (of 8) from mux cell spi_neuron_top.$flatten\u_spi_slave.$procmux$5156 ($mux).
Removed top 1 bits (of 8) from mux cell spi_neuron_top.$flatten\u_spi_slave.$procmux$5153 ($mux).
Removed top 1 bits (of 8) from mux cell spi_neuron_top.$flatten\u_spi_slave.$procmux$5151 ($mux).
Removed top 2 bits (of 3) from port B of cell spi_neuron_top.$flatten\u_spi_slave.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_slave.v:173$14 ($add).
Removed top 15 bits (of 16) from FF cell spi_neuron_top.$auto$ff.cc:337:slice$7188 ($sdffe).
Removed top 15 bits (of 16) from FF cell spi_neuron_top.$auto$ff.cc:337:slice$6703 ($sdffe).
Removed top 1 bits (of 16) from FF cell spi_neuron_top.$auto$ff.cc:337:slice$6592 ($sdffe).
Removed top 8 bits (of 24) from mux cell spi_neuron_top.$flatten\u_spi_engine.$procmux$4018 ($mux).
Removed top 8 bits (of 24) from mux cell spi_neuron_top.$flatten\u_spi_engine.$procmux$4004 ($mux).
Removed top 1 bits (of 16) from mux cell spi_neuron_top.$flatten\u_spi_engine.$procmux$4002 ($pmux).
Removed top 1 bits (of 16) from mux cell spi_neuron_top.$flatten\u_spi_engine.$procmux$4000 ($mux).
Removed top 7 bits (of 8) from FF cell spi_neuron_top.$auto$ff.cc:337:slice$7469 ($sdffe).
Removed top 1 bits (of 16) from mux cell spi_neuron_top.$flatten\u_spi_engine.$procmux$4018 ($mux).
Removed top 9 bits (of 24) from mux cell spi_neuron_top.$flatten\u_spi_engine.$procmux$4016 ($mux).
Removed top 1 bits (of 16) from mux cell spi_neuron_top.$flatten\u_spi_engine.$procmux$4004 ($mux).
Removed cell spi_neuron_top.$auto$ff.cc:337:slice$7466 ($sdffe).
Removed top 9 bits (of 32) from wire spi_neuron_top.$flatten\u_graph_engine.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:533$1043_Y.
Removed top 1 bits (of 6) from wire spi_neuron_top.$flatten\u_neuron_memory.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:357$1114_ADDR[5:0]$1120.
Removed top 1 bits (of 6) from wire spi_neuron_top.$flatten\u_neuron_memory.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:390$1115_ADDR[5:0]$1123.
Removed top 1 bits (of 6) from wire spi_neuron_top.$flatten\u_neuron_memory.$2$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:357$1114_ADDR[5:0]$1139.
Removed top 1 bits (of 6) from wire spi_neuron_top.$flatten\u_neuron_memory.$2$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:390$1115_ADDR[5:0]$1142.
Removed top 1 bits (of 6) from wire spi_neuron_top.$flatten\u_neuron_memory.$3$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:390$1115_ADDR[5:0]$1156.
Removed top 1 bits (of 6) from wire spi_neuron_top.$flatten\u_graph_engine.$2$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:496$865_ADDR[5:0]$1013.
Removed top 16 bits (of 32) from wire spi_neuron_top.$flatten\u_graph_engine.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:394$1022_Y.
Removed top 9 bits (of 24) from wire spi_neuron_top.$flatten\u_spi_engine.$procmux$4018_Y.
Removed top 9 bits (of 24) from wire spi_neuron_top.$flatten\u_spi_engine.$procmux$4016_Y.
Removed top 9 bits (of 24) from wire spi_neuron_top.$flatten\u_spi_engine.$procmux$4004_Y.
Removed top 9 bits (of 24) from wire spi_neuron_top.$flatten\u_spi_engine.$procmux$4002_Y.
Removed top 9 bits (of 24) from wire spi_neuron_top.$flatten\u_spi_engine.$procmux$4000_Y.
Removed top 9 bits (of 32) from wire spi_neuron_top.$flatten\u_layer_sequencer.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:317$798_Y.
Removed top 9 bits (of 32) from wire spi_neuron_top.$flatten\u_graph_engine.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:430$1028_Y.
Removed top 1 bits (of 8) from wire spi_neuron_top.$flatten\u_spi_slave.$procmux$5164_Y.
Removed top 1 bits (of 8) from wire spi_neuron_top.$flatten\u_spi_slave.$procmux$5161_Y.
Removed top 1 bits (of 8) from wire spi_neuron_top.$flatten\u_spi_slave.$procmux$5158_Y.
Removed top 1 bits (of 8) from wire spi_neuron_top.$flatten\u_spi_slave.$procmux$5156_Y.
Removed top 1 bits (of 8) from wire spi_neuron_top.$flatten\u_spi_slave.$procmux$5153_Y.
Removed top 1 bits (of 8) from wire spi_neuron_top.$flatten\u_spi_slave.$procmux$5151_Y.
Removed top 1 bits (of 6) from wire spi_neuron_top.$flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:496$865_ADDR[5:0]$937.
Removed top 9 bits (of 32) from wire spi_neuron_top.$flatten\u_graph_engine.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:430$1029_Y.
Removed top 15 bits (of 16) from wire spi_neuron_top.n_neurons_real.
Removed top 15 bits (of 16) from wire spi_neuron_top.seq_nm_n_neurons.
Removed top 15 bits (of 16) from wire spi_neuron_top.mux_nm_n_neurons.
Removed top 1 bits (of 23) from wire spi_neuron_top.i8_mem_addr.
Removed top 1 bits (of 23) from wire spi_neuron_top.psram_mem_addr.
17.16. Executing PEEPOPT pass (run peephole optimizers).
shiftpow2 pattern in spi_neuron_top: shift=$flatten\u_graph_engine.\u_neuron.$shiftx$/tmp/before_rewrite/neuron_parallel.v:107$631, index=\u_graph_engine.u_neuron.group_index, stride=64, width=64, ways=4
shiftpow2 pattern in spi_neuron_top: shift=$flatten\u_graph_engine.\u_neuron.$shiftx$/tmp/before_rewrite/neuron_parallel.v:101$627, index=\u_graph_engine.u_neuron.group_index, stride=64, width=64, ways=4
shiftpow2 pattern in spi_neuron_top: shift=$flatten\u_layer_sequencer.$shiftx$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:291$791, index=\u_layer_sequencer.copy_idx, stride=8, width=8, ways=2
shiftpow2 pattern in spi_neuron_top: shift=$flatten\u_neuron_memory.\u_neuron.$shiftx$/tmp/before_rewrite/neuron_parallel.v:107$631, index=\u_neuron_memory.u_neuron.group_index, stride=64, width=64, ways=4
shiftpow2 pattern in spi_neuron_top: shift=$flatten\u_neuron_memory.\u_neuron.$shiftx$/tmp/before_rewrite/neuron_parallel.v:101$627, index=\u_neuron_memory.u_neuron.group_index, stride=64, width=64, ways=4
17.17. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \spi_neuron_top..
Removed 2 unused cells and 33 unused wires.
<suppressed ~3 debug messages>
17.18. Executing SHARE pass (SAT-based resource sharing).
Found 17 cells in module spi_neuron_top that may be considered for resource sharing.
Analyzing resource sharing options for $flatten\u_neuron_memory.\u_neuron.\u_mac8.\GEN_MAC[7].u_mac.$mul$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:16$1249 ($mul):
Cell is always active. Therefore no sharing is possible.
Analyzing resource sharing options for $flatten\u_neuron_memory.\u_neuron.\u_mac8.\GEN_MAC[6].u_mac.$mul$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:16$1249 ($mul):
Cell is always active. Therefore no sharing is possible.
Analyzing resource sharing options for $flatten\u_neuron_memory.\u_neuron.\u_mac8.\GEN_MAC[5].u_mac.$mul$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:16$1249 ($mul):
Cell is always active. Therefore no sharing is possible.
Analyzing resource sharing options for $flatten\u_neuron_memory.\u_neuron.\u_mac8.\GEN_MAC[4].u_mac.$mul$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:16$1249 ($mul):
Cell is always active. Therefore no sharing is possible.
Analyzing resource sharing options for $flatten\u_neuron_memory.\u_neuron.\u_mac8.\GEN_MAC[3].u_mac.$mul$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:16$1249 ($mul):
Cell is always active. Therefore no sharing is possible.
Analyzing resource sharing options for $flatten\u_neuron_memory.\u_neuron.\u_mac8.\GEN_MAC[2].u_mac.$mul$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:16$1249 ($mul):
Cell is always active. Therefore no sharing is possible.
Analyzing resource sharing options for $flatten\u_neuron_memory.\u_neuron.\u_mac8.\GEN_MAC[1].u_mac.$mul$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:16$1249 ($mul):
Cell is always active. Therefore no sharing is possible.
Analyzing resource sharing options for $flatten\u_neuron_memory.\u_neuron.\u_mac8.\GEN_MAC[0].u_mac.$mul$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:16$1249 ($mul):
Cell is always active. Therefore no sharing is possible.
Analyzing resource sharing options for $flatten\u_graph_engine.\u_neuron.\u_mac8.\GEN_MAC[7].u_mac.$mul$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:16$1249 ($mul):
Cell is always active. Therefore no sharing is possible.
Analyzing resource sharing options for $flatten\u_graph_engine.\u_neuron.\u_mac8.\GEN_MAC[6].u_mac.$mul$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:16$1249 ($mul):
Cell is always active. Therefore no sharing is possible.
Analyzing resource sharing options for $flatten\u_graph_engine.\u_neuron.\u_mac8.\GEN_MAC[5].u_mac.$mul$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:16$1249 ($mul):
Cell is always active. Therefore no sharing is possible.
Analyzing resource sharing options for $flatten\u_graph_engine.\u_neuron.\u_mac8.\GEN_MAC[4].u_mac.$mul$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:16$1249 ($mul):
Cell is always active. Therefore no sharing is possible.
Analyzing resource sharing options for $flatten\u_graph_engine.\u_neuron.\u_mac8.\GEN_MAC[3].u_mac.$mul$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:16$1249 ($mul):
Cell is always active. Therefore no sharing is possible.
Analyzing resource sharing options for $flatten\u_graph_engine.\u_neuron.\u_mac8.\GEN_MAC[2].u_mac.$mul$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:16$1249 ($mul):
Cell is always active. Therefore no sharing is possible.
Analyzing resource sharing options for $flatten\u_graph_engine.\u_neuron.\u_mac8.\GEN_MAC[1].u_mac.$mul$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:16$1249 ($mul):
Cell is always active. Therefore no sharing is possible.
Analyzing resource sharing options for $flatten\u_graph_engine.\u_neuron.\u_mac8.\GEN_MAC[0].u_mac.$mul$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:16$1249 ($mul):
Cell is always active. Therefore no sharing is possible.
Analyzing resource sharing options for $flatten\u_spi_engine.$auto$mem.cc:305:emit$1541 ($memrd_v2):
Found 2 activation_patterns using ctrl signal { \u_spi_slave.cs_n_sync [2] \u_spi_slave.sclk_rise \u_spi_slave.sclk_fall \u_spi_slave.cs_fell \u_spi_slave.cs_rose $flatten\u_spi_slave.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_slave.v:182$15_Y \u_spi_engine.state [5] $flatten\u_spi_engine.$procmux$4638_CMP }.
No candidates found.
17.19. Executing TECHMAP pass (map to technology primitives).
17.19.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/cmp2lut.v
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/cmp2lut.v' to AST representation.
Generating RTLIL representation for module `\_90_lut_cmp_'.
Successfully finished Verilog frontend.
17.19.2. Continuing TECHMAP pass.
Using template $paramod$e284bc47c88f6e32a7d40296f7bdff7bac057394\_90_lut_cmp_ for cells of type $lt.
No more expansions possible.
<suppressed ~166 debug messages>
17.20. Executing OPT_EXPR pass (perform const folding).
Optimizing module spi_neuron_top.
17.21. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \spi_neuron_top..
Removed 0 unused cells and 3 unused wires.
<suppressed ~1 debug messages>
17.22. Executing TECHMAP pass (map to technology primitives).
17.22.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/mul2dsp.v
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/mul2dsp.v' to AST representation.
Generating RTLIL representation for module `\_80_mul'.
Generating RTLIL representation for module `\_90_soft_mul'.
Successfully finished Verilog frontend.
17.22.2. Continuing TECHMAP pass.
Using template $paramod$cc733e0dbb038034434917c1e0de96998ec4103f\_80_mul for cells of type $mul.
No more expansions possible.
<suppressed ~100 debug messages>
17.23. Executing TECHMAP pass (map to technology primitives).
17.23.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/dsp_map_18x18.v
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/dsp_map_18x18.v' to AST representation.
Generating RTLIL representation for module `$__MUL18X18'.
Successfully finished Verilog frontend.
17.23.2. Continuing TECHMAP pass.
Using template $paramod$ea686d7c43b0ae12a4f0d39aec4e01bcc4449b23$__MUL18X18 for cells of type $__MUL18X18.
No more expansions possible.
<suppressed ~38 debug messages>
17.24. Executing ALUMACC pass (create $alu and $macc cells).
Extracting $alu and $macc cells in module spi_neuron_top:
creating $macc model for $flatten\u_layer_sequencer.$sub$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:301$792 ($sub).
creating $macc model for $flatten\u_layer_sequencer.$sub$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:303$794 ($sub).
creating $macc model for $flatten\u_graph_engine.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:430$1029 ($add).
creating $macc model for $flatten\u_graph_engine.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:430$1028 ($add).
creating $macc model for $flatten\u_spi_slave.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_slave.v:173$14 ($add).
creating $macc model for $flatten\u_graph_engine.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:401$1025 ($add).
creating $macc model for $flatten\u_graph_engine.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:394$1022 ($add).
creating $macc model for $flatten\u_graph_engine.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:366$1020 ($add).
creating $macc model for $flatten\u_graph_engine.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:350$1019 ($add).
creating $macc model for $flatten\u_layer_sequencer.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:316$797 ($add).
creating $macc model for $flatten\u_graph_engine.$sub$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:346$1017 ($sub).
creating $macc model for $flatten\u_graph_engine.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:332$1016 ($add).
creating $macc model for $flatten\u_layer_sequencer.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:290$788 ($add).
creating $macc model for $flatten\u_graph_engine.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:478$1036 ($add).
creating $macc model for $flatten\u_graph_engine.$sub$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:498$1037 ($sub).
creating $macc model for $flatten\u_graph_engine.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:502$1039 ($add).
creating $macc model for $flatten\u_graph_engine.$sub$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:527$1040 ($sub).
creating $macc model for $flatten\u_spi_engine.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:710$779 ($add).
creating $macc model for $flatten\u_spi_engine.$sub$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:707$777 ($sub).
creating $macc model for $flatten\u_spi_engine.$sub$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:642$773 ($sub).
creating $macc model for $flatten\u_spi_engine.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:641$772 ($add).
creating $macc model for $flatten\u_spi_engine.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:561$768 ($add).
creating $macc model for $flatten\u_graph_engine.\u_neuron.\u_mac8.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101$1301 ($add).
creating $macc model for $flatten\u_graph_engine.\u_neuron.\u_mac8.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101$1303 ($add).
creating $macc model for $flatten\u_graph_engine.\u_neuron.\u_mac8.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101$1305 ($add).
creating $macc model for $flatten\u_graph_engine.\u_neuron.\u_mac8.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101$1307 ($add).
creating $macc model for $flatten\u_graph_engine.\u_neuron.\u_mac8.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101$1309 ($add).
creating $macc model for $flatten\u_graph_engine.\u_neuron.\u_mac8.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101$1311 ($add).
creating $macc model for $flatten\u_graph_engine.\u_neuron.\u_mac8.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101$1313 ($add).
creating $macc model for $flatten\u_graph_engine.\u_neuron.$add$/tmp/before_rewrite/neuron_parallel.v:194$642 ($add).
creating $macc model for $flatten\u_graph_engine.\u_neuron.$sub$/tmp/before_rewrite/neuron_parallel.v:152$636 ($sub).
creating $macc model for $flatten\u_graph_engine.\u_neuron.$add$/tmp/before_rewrite/neuron_parallel.v:128$632 ($add).
creating $macc model for $flatten\u_graph_engine.\u_neuron.\u_mac8.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:115$1283 ($add).
creating $macc model for $flatten\u_neuron_memory.$sub$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:359$1151 ($sub).
creating $macc model for $flatten\u_neuron_memory.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:371$1153 ($add).
creating $macc model for $flatten\u_neuron_memory.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:373$1154 ($add).
creating $macc model for $flatten\u_neuron_memory.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:373$1155 ($add).
creating $macc model for $flatten\u_neuron_memory.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:404$1162 ($add).
creating $macc model for $flatten\u_neuron_memory.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:404$1163 ($add).
creating $macc model for $flatten\u_neuron_memory.$sub$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:451$1167 ($sub).
creating $macc model for $flatten\u_neuron_memory.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:464$1169 ($add).
creating $macc model for $flatten\u_neuron_memory.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:465$1170 ($add).
creating $macc model for $flatten\u_neuron_memory.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:466$1171 ($add).
creating $macc model for $flatten\u_layer_sequencer.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:317$798 ($add).
creating $macc model for $flatten\u_layer_sequencer.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:326$799 ($add).
creating $macc model for $flatten\u_graph_engine.$sub$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:177$868 ($sub).
creating $macc model for $flatten\u_graph_engine.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:532$1042 ($add).
creating $macc model for $flatten\u_neuron_memory.\u_neuron.\u_mac8.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101$1301 ($add).
creating $macc model for $flatten\u_neuron_memory.\u_neuron.\u_mac8.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101$1303 ($add).
creating $macc model for $flatten\u_neuron_memory.\u_neuron.\u_mac8.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101$1305 ($add).
creating $macc model for $flatten\u_neuron_memory.\u_neuron.\u_mac8.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101$1307 ($add).
creating $macc model for $flatten\u_neuron_memory.\u_neuron.\u_mac8.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101$1309 ($add).
creating $macc model for $flatten\u_neuron_memory.\u_neuron.\u_mac8.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101$1311 ($add).
creating $macc model for $flatten\u_neuron_memory.\u_neuron.\u_mac8.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101$1313 ($add).
creating $macc model for $flatten\u_neuron_memory.\u_neuron.$add$/tmp/before_rewrite/neuron_parallel.v:194$642 ($add).
creating $macc model for $flatten\u_neuron_memory.\u_neuron.$sub$/tmp/before_rewrite/neuron_parallel.v:152$636 ($sub).
creating $macc model for $flatten\u_neuron_memory.\u_neuron.$add$/tmp/before_rewrite/neuron_parallel.v:128$632 ($add).
creating $macc model for $flatten\u_neuron_memory.\u_neuron.\u_mac8.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:115$1283 ($add).
creating $macc model for $flatten\u_graph_engine.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:550$1044 ($add).
creating $macc model for $flatten\u_psram_ctrl.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/psram_controller.v:186$1244 ($add).
creating $macc model for $flatten\u_graph_engine.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:533$1043 ($add).
creating $macc model for $flatten\u_layer_sequencer.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:211$781 ($add).
creating $macc model for $flatten\u_graph_engine.$sub$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:175$866 ($sub).
creating $macc model for $flatten\u_layer_sequencer.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:239$783 ($add).
merging $macc model for $flatten\u_neuron_memory.\u_neuron.\u_mac8.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101$1313 into $flatten\u_neuron_memory.\u_neuron.\u_mac8.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:115$1283.
merging $macc model for $flatten\u_neuron_memory.\u_neuron.\u_mac8.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101$1309 into $flatten\u_neuron_memory.\u_neuron.\u_mac8.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:115$1283.
merging $macc model for $flatten\u_neuron_memory.\u_neuron.\u_mac8.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101$1311 into $flatten\u_neuron_memory.\u_neuron.\u_mac8.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:115$1283.
merging $macc model for $flatten\u_neuron_memory.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:404$1162 into $flatten\u_neuron_memory.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:404$1163.
merging $macc model for $flatten\u_neuron_memory.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:373$1154 into $flatten\u_neuron_memory.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:373$1155.
merging $macc model for $flatten\u_graph_engine.\u_neuron.\u_mac8.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101$1313 into $flatten\u_graph_engine.\u_neuron.\u_mac8.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:115$1283.
merging $macc model for $flatten\u_graph_engine.\u_neuron.\u_mac8.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101$1309 into $flatten\u_graph_engine.\u_neuron.\u_mac8.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:115$1283.
merging $macc model for $flatten\u_graph_engine.\u_neuron.\u_mac8.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101$1311 into $flatten\u_graph_engine.\u_neuron.\u_mac8.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:115$1283.
merging $macc model for $flatten\u_graph_engine.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:430$1028 into $flatten\u_graph_engine.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:430$1029.
creating $alu model for $macc $flatten\u_neuron_memory.\u_neuron.$add$/tmp/before_rewrite/neuron_parallel.v:194$642.
creating $alu model for $macc $flatten\u_neuron_memory.\u_neuron.$sub$/tmp/before_rewrite/neuron_parallel.v:152$636.
creating $alu model for $macc $flatten\u_neuron_memory.\u_neuron.$add$/tmp/before_rewrite/neuron_parallel.v:128$632.
creating $alu model for $macc $flatten\u_neuron_memory.\u_neuron.\u_mac8.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101$1307.
creating $alu model for $macc $flatten\u_neuron_memory.\u_neuron.\u_mac8.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101$1305.
creating $alu model for $macc $flatten\u_neuron_memory.\u_neuron.\u_mac8.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101$1303.
creating $alu model for $macc $flatten\u_neuron_memory.\u_neuron.\u_mac8.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101$1301.
creating $alu model for $macc $flatten\u_graph_engine.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:532$1042.
creating $alu model for $macc $flatten\u_graph_engine.$sub$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:177$868.
creating $alu model for $macc $flatten\u_layer_sequencer.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:326$799.
creating $alu model for $macc $flatten\u_layer_sequencer.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:317$798.
creating $alu model for $macc $flatten\u_neuron_memory.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:466$1171.
creating $alu model for $macc $flatten\u_neuron_memory.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:465$1170.
creating $alu model for $macc $flatten\u_neuron_memory.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:464$1169.
creating $alu model for $macc $flatten\u_neuron_memory.$sub$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:451$1167.
creating $alu model for $macc $flatten\u_neuron_memory.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:404$1163.
creating $alu model for $macc $flatten\u_graph_engine.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:550$1044.
creating $alu model for $macc $flatten\u_neuron_memory.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:373$1155.
creating $alu model for $macc $flatten\u_psram_ctrl.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/psram_controller.v:186$1244.
creating $alu model for $macc $flatten\u_neuron_memory.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:371$1153.
creating $alu model for $macc $flatten\u_neuron_memory.$sub$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:359$1151.
creating $alu model for $macc $flatten\u_graph_engine.\u_neuron.$add$/tmp/before_rewrite/neuron_parallel.v:128$632.
creating $alu model for $macc $flatten\u_graph_engine.\u_neuron.$sub$/tmp/before_rewrite/neuron_parallel.v:152$636.
creating $alu model for $macc $flatten\u_graph_engine.\u_neuron.$add$/tmp/before_rewrite/neuron_parallel.v:194$642.
creating $alu model for $macc $flatten\u_graph_engine.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:533$1043.
creating $alu model for $macc $flatten\u_graph_engine.$sub$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:175$866.
creating $alu model for $macc $flatten\u_layer_sequencer.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:211$781.
creating $alu model for $macc $flatten\u_graph_engine.\u_neuron.\u_mac8.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101$1307.
creating $alu model for $macc $flatten\u_graph_engine.\u_neuron.\u_mac8.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101$1305.
creating $alu model for $macc $flatten\u_graph_engine.\u_neuron.\u_mac8.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101$1303.
creating $alu model for $macc $flatten\u_graph_engine.\u_neuron.\u_mac8.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101$1301.
creating $alu model for $macc $flatten\u_spi_engine.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:561$768.
creating $alu model for $macc $flatten\u_spi_engine.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:641$772.
creating $alu model for $macc $flatten\u_spi_engine.$sub$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:642$773.
creating $alu model for $macc $flatten\u_spi_engine.$sub$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:707$777.
creating $alu model for $macc $flatten\u_spi_engine.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:710$779.
creating $alu model for $macc $flatten\u_graph_engine.$sub$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:527$1040.
creating $alu model for $macc $flatten\u_graph_engine.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:502$1039.
creating $alu model for $macc $flatten\u_graph_engine.$sub$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:498$1037.
creating $alu model for $macc $flatten\u_graph_engine.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:478$1036.
creating $alu model for $macc $flatten\u_layer_sequencer.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:290$788.
creating $alu model for $macc $flatten\u_graph_engine.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:332$1016.
creating $alu model for $macc $flatten\u_graph_engine.$sub$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:346$1017.
creating $alu model for $macc $flatten\u_layer_sequencer.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:316$797.
creating $alu model for $macc $flatten\u_graph_engine.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:350$1019.
creating $alu model for $macc $flatten\u_graph_engine.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:366$1020.
creating $alu model for $macc $flatten\u_graph_engine.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:394$1022.
creating $alu model for $macc $flatten\u_graph_engine.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:401$1025.
creating $alu model for $macc $flatten\u_spi_slave.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_slave.v:173$14.
creating $alu model for $macc $flatten\u_layer_sequencer.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:239$783.
creating $alu model for $macc $flatten\u_layer_sequencer.$sub$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:303$794.
creating $alu model for $macc $flatten\u_layer_sequencer.$sub$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:301$792.
creating $macc cell for $flatten\u_graph_engine.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:430$1029: $auto$alumacc.cc:399:replace_macc$7584
creating $macc cell for $flatten\u_graph_engine.\u_neuron.\u_mac8.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:115$1283: $auto$alumacc.cc:399:replace_macc$7585
creating $macc cell for $flatten\u_neuron_memory.\u_neuron.\u_mac8.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:115$1283: $auto$alumacc.cc:399:replace_macc$7586
creating $alu model for $flatten\u_graph_engine.$ge$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:458$1034 ($ge): new $alu
creating $alu model for $flatten\u_graph_engine.$ge$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:457$1032 ($ge): new $alu
creating $alu model for $flatten\u_graph_engine.$ge$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:456$1031 ($ge): new $alu
creating $alu model for $flatten\u_graph_engine.$ge$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:176$867 ($ge): merged with $flatten\u_graph_engine.$sub$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:177$868.
creating $alu model for $flatten\u_graph_engine.\u_neuron.$gt$/tmp/before_rewrite/neuron_parallel.v:178$641 ($gt): new $alu
creating $alu model for $flatten\u_graph_engine.\u_neuron.$le$/tmp/before_rewrite/neuron_parallel.v:176$640 ($le): new $alu
creating $alu model for $flatten\u_graph_engine.\u_neuron.$lt$/tmp/before_rewrite/neuron_parallel.v:165$639 ($lt): new $alu
creating $alu model for $flatten\u_neuron_memory.\u_neuron.$gt$/tmp/before_rewrite/neuron_parallel.v:178$641 ($gt): new $alu
creating $alu model for $flatten\u_neuron_memory.\u_neuron.$le$/tmp/before_rewrite/neuron_parallel.v:176$640 ($le): new $alu
creating $alu model for $flatten\u_neuron_memory.\u_neuron.$lt$/tmp/before_rewrite/neuron_parallel.v:165$639 ($lt): new $alu
creating $alu model for $flatten\u_spi_engine.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:644$774 ($eq): merged with $flatten\u_spi_engine.$sub$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:642$773.
creating $alu cell for $flatten\u_neuron_memory.\u_neuron.$lt$/tmp/before_rewrite/neuron_parallel.v:165$639: $auto$alumacc.cc:548:replace_alu$7596
creating $alu cell for $flatten\u_neuron_memory.\u_neuron.$le$/tmp/before_rewrite/neuron_parallel.v:176$640: $auto$alumacc.cc:548:replace_alu$7603
creating $alu cell for $flatten\u_neuron_memory.\u_neuron.$gt$/tmp/before_rewrite/neuron_parallel.v:178$641: $auto$alumacc.cc:548:replace_alu$7614
creating $alu cell for $flatten\u_graph_engine.\u_neuron.$lt$/tmp/before_rewrite/neuron_parallel.v:165$639: $auto$alumacc.cc:548:replace_alu$7627
creating $alu cell for $flatten\u_graph_engine.\u_neuron.$le$/tmp/before_rewrite/neuron_parallel.v:176$640: $auto$alumacc.cc:548:replace_alu$7634
creating $alu cell for $flatten\u_graph_engine.\u_neuron.$gt$/tmp/before_rewrite/neuron_parallel.v:178$641: $auto$alumacc.cc:548:replace_alu$7645
creating $alu cell for $flatten\u_graph_engine.$ge$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:456$1031: $auto$alumacc.cc:548:replace_alu$7658
creating $alu cell for $flatten\u_graph_engine.$ge$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:457$1032: $auto$alumacc.cc:548:replace_alu$7671
creating $alu cell for $flatten\u_graph_engine.$ge$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:458$1034: $auto$alumacc.cc:548:replace_alu$7684
creating $alu cell for $flatten\u_layer_sequencer.$sub$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:301$792: $auto$alumacc.cc:548:replace_alu$7697
creating $alu cell for $flatten\u_layer_sequencer.$sub$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:303$794: $auto$alumacc.cc:548:replace_alu$7700
creating $alu cell for $flatten\u_layer_sequencer.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:239$783: $auto$alumacc.cc:548:replace_alu$7703
creating $alu cell for $flatten\u_spi_slave.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_slave.v:173$14: $auto$alumacc.cc:548:replace_alu$7706
creating $alu cell for $flatten\u_graph_engine.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:401$1025: $auto$alumacc.cc:548:replace_alu$7709
creating $alu cell for $flatten\u_graph_engine.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:394$1022: $auto$alumacc.cc:548:replace_alu$7712
creating $alu cell for $flatten\u_graph_engine.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:366$1020: $auto$alumacc.cc:548:replace_alu$7715
creating $alu cell for $flatten\u_graph_engine.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:350$1019: $auto$alumacc.cc:548:replace_alu$7718
creating $alu cell for $flatten\u_layer_sequencer.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:316$797: $auto$alumacc.cc:548:replace_alu$7721
creating $alu cell for $flatten\u_graph_engine.$sub$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:346$1017: $auto$alumacc.cc:548:replace_alu$7724
creating $alu cell for $flatten\u_graph_engine.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:332$1016: $auto$alumacc.cc:548:replace_alu$7727
creating $alu cell for $flatten\u_layer_sequencer.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:290$788: $auto$alumacc.cc:548:replace_alu$7730
creating $alu cell for $flatten\u_graph_engine.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:478$1036: $auto$alumacc.cc:548:replace_alu$7733
creating $alu cell for $flatten\u_graph_engine.$sub$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:498$1037: $auto$alumacc.cc:548:replace_alu$7736
creating $alu cell for $flatten\u_graph_engine.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:502$1039: $auto$alumacc.cc:548:replace_alu$7739
creating $alu cell for $flatten\u_graph_engine.$sub$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:527$1040: $auto$alumacc.cc:548:replace_alu$7742
creating $alu cell for $flatten\u_spi_engine.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:710$779: $auto$alumacc.cc:548:replace_alu$7745
creating $alu cell for $flatten\u_spi_engine.$sub$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:707$777: $auto$alumacc.cc:548:replace_alu$7748
creating $alu cell for $flatten\u_spi_engine.$sub$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:642$773, $flatten\u_spi_engine.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:644$774: $auto$alumacc.cc:548:replace_alu$7751
creating $alu cell for $flatten\u_spi_engine.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:641$772: $auto$alumacc.cc:548:replace_alu$7756
creating $alu cell for $flatten\u_spi_engine.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:561$768: $auto$alumacc.cc:548:replace_alu$7759
creating $alu cell for $flatten\u_graph_engine.\u_neuron.\u_mac8.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101$1301: $auto$alumacc.cc:548:replace_alu$7762
creating $alu cell for $flatten\u_graph_engine.\u_neuron.\u_mac8.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101$1303: $auto$alumacc.cc:548:replace_alu$7765
creating $alu cell for $flatten\u_graph_engine.\u_neuron.\u_mac8.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101$1305: $auto$alumacc.cc:548:replace_alu$7768
creating $alu cell for $flatten\u_graph_engine.\u_neuron.\u_mac8.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101$1307: $auto$alumacc.cc:548:replace_alu$7771
creating $alu cell for $flatten\u_layer_sequencer.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:211$781: $auto$alumacc.cc:548:replace_alu$7774
creating $alu cell for $flatten\u_graph_engine.$sub$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:175$866: $auto$alumacc.cc:548:replace_alu$7777
creating $alu cell for $flatten\u_graph_engine.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:533$1043: $auto$alumacc.cc:548:replace_alu$7780
creating $alu cell for $flatten\u_graph_engine.\u_neuron.$add$/tmp/before_rewrite/neuron_parallel.v:194$642: $auto$alumacc.cc:548:replace_alu$7783
creating $alu cell for $flatten\u_graph_engine.\u_neuron.$sub$/tmp/before_rewrite/neuron_parallel.v:152$636: $auto$alumacc.cc:548:replace_alu$7786
creating $alu cell for $flatten\u_graph_engine.\u_neuron.$add$/tmp/before_rewrite/neuron_parallel.v:128$632: $auto$alumacc.cc:548:replace_alu$7789
creating $alu cell for $flatten\u_neuron_memory.$sub$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:359$1151: $auto$alumacc.cc:548:replace_alu$7792
creating $alu cell for $flatten\u_neuron_memory.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:371$1153: $auto$alumacc.cc:548:replace_alu$7795
creating $alu cell for $flatten\u_psram_ctrl.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/psram_controller.v:186$1244: $auto$alumacc.cc:548:replace_alu$7798
creating $alu cell for $flatten\u_neuron_memory.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:373$1155: $auto$alumacc.cc:548:replace_alu$7801
creating $alu cell for $flatten\u_graph_engine.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:550$1044: $auto$alumacc.cc:548:replace_alu$7804
creating $alu cell for $flatten\u_neuron_memory.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:404$1163: $auto$alumacc.cc:548:replace_alu$7807
creating $alu cell for $flatten\u_neuron_memory.$sub$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:451$1167: $auto$alumacc.cc:548:replace_alu$7810
creating $alu cell for $flatten\u_neuron_memory.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:464$1169: $auto$alumacc.cc:548:replace_alu$7813
creating $alu cell for $flatten\u_neuron_memory.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:465$1170: $auto$alumacc.cc:548:replace_alu$7816
creating $alu cell for $flatten\u_neuron_memory.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:466$1171: $auto$alumacc.cc:548:replace_alu$7819
creating $alu cell for $flatten\u_layer_sequencer.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:317$798: $auto$alumacc.cc:548:replace_alu$7822
creating $alu cell for $flatten\u_layer_sequencer.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:326$799: $auto$alumacc.cc:548:replace_alu$7825
creating $alu cell for $flatten\u_graph_engine.$sub$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:177$868, $flatten\u_graph_engine.$ge$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:176$867: $auto$alumacc.cc:548:replace_alu$7828
creating $alu cell for $flatten\u_graph_engine.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:532$1042: $auto$alumacc.cc:548:replace_alu$7841
creating $alu cell for $flatten\u_neuron_memory.\u_neuron.\u_mac8.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101$1301: $auto$alumacc.cc:548:replace_alu$7844
creating $alu cell for $flatten\u_neuron_memory.\u_neuron.\u_mac8.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101$1303: $auto$alumacc.cc:548:replace_alu$7847
creating $alu cell for $flatten\u_neuron_memory.\u_neuron.\u_mac8.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101$1305: $auto$alumacc.cc:548:replace_alu$7850
creating $alu cell for $flatten\u_neuron_memory.\u_neuron.\u_mac8.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101$1307: $auto$alumacc.cc:548:replace_alu$7853
creating $alu cell for $flatten\u_neuron_memory.\u_neuron.$add$/tmp/before_rewrite/neuron_parallel.v:128$632: $auto$alumacc.cc:548:replace_alu$7856
creating $alu cell for $flatten\u_neuron_memory.\u_neuron.$sub$/tmp/before_rewrite/neuron_parallel.v:152$636: $auto$alumacc.cc:548:replace_alu$7859
creating $alu cell for $flatten\u_neuron_memory.\u_neuron.$add$/tmp/before_rewrite/neuron_parallel.v:194$642: $auto$alumacc.cc:548:replace_alu$7862
created 61 $alu and 3 $macc cells.
17.25. Executing OPT pass (performing simple optimizations).
17.25.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module spi_neuron_top.
<suppressed ~10 debug messages>
17.25.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\spi_neuron_top'.
Computing hashes of 1532 cells of `\spi_neuron_top'.
Finding duplicate cells in `\spi_neuron_top'.
Removed a total of 0 cells.
17.25.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \spi_neuron_top..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~546 debug messages>
17.25.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Optimizing cells in module \spi_neuron_top.
Optimizing cells in module \spi_neuron_top.
Performed a total of 1 changes.
17.25.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\spi_neuron_top'.
Computing hashes of 1532 cells of `\spi_neuron_top'.
Finding duplicate cells in `\spi_neuron_top'.
Removed a total of 0 cells.
17.25.6. Executing OPT_DFF pass (perform DFF optimizations).
17.25.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \spi_neuron_top..
Removed 11 unused cells and 160 unused wires.
<suppressed ~20 debug messages>
17.25.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module spi_neuron_top.
17.25.9. Rerunning OPT passes. (Maybe there is more to do..)
17.25.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \spi_neuron_top..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~548 debug messages>
17.25.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Optimizing cells in module \spi_neuron_top.
Performed a total of 0 changes.
17.25.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\spi_neuron_top'.
Computing hashes of 1519 cells of `\spi_neuron_top'.
Finding duplicate cells in `\spi_neuron_top'.
Removed a total of 0 cells.
17.25.13. Executing OPT_DFF pass (perform DFF optimizations).
17.25.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \spi_neuron_top..
17.25.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module spi_neuron_top.
17.25.16. Finished fast OPT passes. (There is nothing left to do.)
17.26. Executing MEMORY pass.
17.26.1. Executing OPT_MEM pass (optimize memories).
spi_neuron_top.$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1540: removing const-0 lane 6
spi_neuron_top.$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1540: removing const-0 lane 7
Performed a total of 1 transformations.
17.26.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations).
Performed a total of 992 transformations.
17.26.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths).
Analyzing spi_neuron_top.u_graph_engine.x_mem write port 0.
Analyzing spi_neuron_top.u_graph_engine.x_mem write port 1.
Analyzing spi_neuron_top.u_graph_engine.x_mem write port 2.
Analyzing spi_neuron_top.u_graph_engine.x_mem write port 3.
Analyzing spi_neuron_top.u_graph_engine.x_mem write port 4.
Analyzing spi_neuron_top.u_graph_engine.x_mem write port 5.
Analyzing spi_neuron_top.u_graph_engine.x_mem write port 6.
Analyzing spi_neuron_top.u_graph_engine.x_mem write port 7.
Analyzing spi_neuron_top.u_graph_engine.x_mem write port 8.
Analyzing spi_neuron_top.u_graph_engine.x_mem write port 9.
Analyzing spi_neuron_top.u_graph_engine.x_mem write port 10.
Analyzing spi_neuron_top.u_graph_engine.x_mem write port 11.
Analyzing spi_neuron_top.u_graph_engine.x_mem write port 12.
Analyzing spi_neuron_top.u_graph_engine.x_mem write port 13.
Analyzing spi_neuron_top.u_graph_engine.x_mem write port 14.
Analyzing spi_neuron_top.u_graph_engine.x_mem write port 15.
Analyzing spi_neuron_top.u_graph_engine.x_mem write port 16.
Analyzing spi_neuron_top.u_graph_engine.x_mem write port 17.
Analyzing spi_neuron_top.u_graph_engine.x_mem write port 18.
Analyzing spi_neuron_top.u_graph_engine.x_mem write port 19.
Analyzing spi_neuron_top.u_graph_engine.x_mem write port 20.
Analyzing spi_neuron_top.u_graph_engine.x_mem write port 21.
Analyzing spi_neuron_top.u_graph_engine.x_mem write port 22.
Analyzing spi_neuron_top.u_graph_engine.x_mem write port 23.
Analyzing spi_neuron_top.u_graph_engine.x_mem write port 24.
Analyzing spi_neuron_top.u_graph_engine.x_mem write port 25.
Analyzing spi_neuron_top.u_graph_engine.x_mem write port 26.
Analyzing spi_neuron_top.u_graph_engine.x_mem write port 27.
Analyzing spi_neuron_top.u_graph_engine.x_mem write port 28.
Analyzing spi_neuron_top.u_graph_engine.x_mem write port 29.
Analyzing spi_neuron_top.u_graph_engine.x_mem write port 30.
Analyzing spi_neuron_top.u_graph_engine.x_mem write port 31.
Analyzing spi_neuron_top.u_graph_engine.x_mem write port 32.
Analyzing spi_neuron_top.u_graph_engine.w_mem write port 0.
Analyzing spi_neuron_top.u_graph_engine.w_mem write port 1.
Analyzing spi_neuron_top.u_graph_engine.w_mem write port 2.
Analyzing spi_neuron_top.u_graph_engine.w_mem write port 3.
Analyzing spi_neuron_top.u_graph_engine.w_mem write port 4.
Analyzing spi_neuron_top.u_graph_engine.w_mem write port 5.
Analyzing spi_neuron_top.u_graph_engine.w_mem write port 6.
Analyzing spi_neuron_top.u_graph_engine.w_mem write port 7.
Analyzing spi_neuron_top.u_graph_engine.w_mem write port 8.
Analyzing spi_neuron_top.u_graph_engine.w_mem write port 9.
Analyzing spi_neuron_top.u_graph_engine.w_mem write port 10.
Analyzing spi_neuron_top.u_graph_engine.w_mem write port 11.
Analyzing spi_neuron_top.u_graph_engine.w_mem write port 12.
Analyzing spi_neuron_top.u_graph_engine.w_mem write port 13.
Analyzing spi_neuron_top.u_graph_engine.w_mem write port 14.
Analyzing spi_neuron_top.u_graph_engine.w_mem write port 15.
Analyzing spi_neuron_top.u_graph_engine.w_mem write port 16.
Analyzing spi_neuron_top.u_graph_engine.w_mem write port 17.
Analyzing spi_neuron_top.u_graph_engine.w_mem write port 18.
Analyzing spi_neuron_top.u_graph_engine.w_mem write port 19.
Analyzing spi_neuron_top.u_graph_engine.w_mem write port 20.
Analyzing spi_neuron_top.u_graph_engine.w_mem write port 21.
Analyzing spi_neuron_top.u_graph_engine.w_mem write port 22.
Analyzing spi_neuron_top.u_graph_engine.w_mem write port 23.
Analyzing spi_neuron_top.u_graph_engine.w_mem write port 24.
Analyzing spi_neuron_top.u_graph_engine.w_mem write port 25.
Analyzing spi_neuron_top.u_graph_engine.w_mem write port 26.
Analyzing spi_neuron_top.u_graph_engine.w_mem write port 27.
Analyzing spi_neuron_top.u_graph_engine.w_mem write port 28.
Analyzing spi_neuron_top.u_graph_engine.w_mem write port 29.
Analyzing spi_neuron_top.u_graph_engine.w_mem write port 30.
Analyzing spi_neuron_top.u_graph_engine.w_mem write port 31.
Analyzing spi_neuron_top.u_graph_engine.w_mem write port 32.
Analyzing spi_neuron_top.u_graph_engine.u_act_buffer.mem write port 0.
Analyzing spi_neuron_top.u_neuron_memory.y_reg write port 0.
Analyzing spi_neuron_top.u_neuron_memory.y_reg write port 1.
Analyzing spi_neuron_top.u_neuron_memory.x_mem write port 0.
Analyzing spi_neuron_top.u_neuron_memory.w_mem write port 0.
17.26.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs).
17.26.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd).
Checking read port `$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1540'[0] in module `\spi_neuron_top': no output FF found.
Checking read port `\u_graph_engine.x_mem'[0] in module `\spi_neuron_top': no output FF found.
Checking read port `\u_graph_engine.x_mem'[1] in module `\spi_neuron_top': no output FF found.
Checking read port `\u_graph_engine.x_mem'[2] in module `\spi_neuron_top': no output FF found.
Checking read port `\u_graph_engine.x_mem'[3] in module `\spi_neuron_top': no output FF found.
Checking read port `\u_graph_engine.x_mem'[4] in module `\spi_neuron_top': no output FF found.
Checking read port `\u_graph_engine.x_mem'[5] in module `\spi_neuron_top': no output FF found.
Checking read port `\u_graph_engine.x_mem'[6] in module `\spi_neuron_top': no output FF found.
Checking read port `\u_graph_engine.x_mem'[7] in module `\spi_neuron_top': no output FF found.
Checking read port `\u_graph_engine.x_mem'[8] in module `\spi_neuron_top': no output FF found.
Checking read port `\u_graph_engine.x_mem'[9] in module `\spi_neuron_top': no output FF found.
Checking read port `\u_graph_engine.x_mem'[10] in module `\spi_neuron_top': no output FF found.
Checking read port `\u_graph_engine.x_mem'[11] in module `\spi_neuron_top': no output FF found.
Checking read port `\u_graph_engine.x_mem'[12] in module `\spi_neuron_top': no output FF found.
Checking read port `\u_graph_engine.x_mem'[13] in module `\spi_neuron_top': no output FF found.
Checking read port `\u_graph_engine.x_mem'[14] in module `\spi_neuron_top': no output FF found.
Checking read port `\u_graph_engine.x_mem'[15] in module `\spi_neuron_top': no output FF found.
Checking read port `\u_graph_engine.x_mem'[16] in module `\spi_neuron_top': no output FF found.
Checking read port `\u_graph_engine.x_mem'[17] in module `\spi_neuron_top': no output FF found.
Checking read port `\u_graph_engine.x_mem'[18] in module `\spi_neuron_top': no output FF found.
Checking read port `\u_graph_engine.x_mem'[19] in module `\spi_neuron_top': no output FF found.
Checking read port `\u_graph_engine.x_mem'[20] in module `\spi_neuron_top': no output FF found.
Checking read port `\u_graph_engine.x_mem'[21] in module `\spi_neuron_top': no output FF found.
Checking read port `\u_graph_engine.x_mem'[22] in module `\spi_neuron_top': no output FF found.
Checking read port `\u_graph_engine.x_mem'[23] in module `\spi_neuron_top': no output FF found.
Checking read port `\u_graph_engine.x_mem'[24] in module `\spi_neuron_top': no output FF found.
Checking read port `\u_graph_engine.x_mem'[25] in module `\spi_neuron_top': no output FF found.
Checking read port `\u_graph_engine.x_mem'[26] in module `\spi_neuron_top': no output FF found.
Checking read port `\u_graph_engine.x_mem'[27] in module `\spi_neuron_top': no output FF found.
Checking read port `\u_graph_engine.x_mem'[28] in module `\spi_neuron_top': no output FF found.
Checking read port `\u_graph_engine.x_mem'[29] in module `\spi_neuron_top': no output FF found.
Checking read port `\u_graph_engine.x_mem'[30] in module `\spi_neuron_top': no output FF found.
Checking read port `\u_graph_engine.x_mem'[31] in module `\spi_neuron_top': no output FF found.
Checking read port `\u_graph_engine.w_mem'[0] in module `\spi_neuron_top': no output FF found.
Checking read port `\u_graph_engine.w_mem'[1] in module `\spi_neuron_top': no output FF found.
Checking read port `\u_graph_engine.w_mem'[2] in module `\spi_neuron_top': no output FF found.
Checking read port `\u_graph_engine.w_mem'[3] in module `\spi_neuron_top': no output FF found.
Checking read port `\u_graph_engine.w_mem'[4] in module `\spi_neuron_top': no output FF found.
Checking read port `\u_graph_engine.w_mem'[5] in module `\spi_neuron_top': no output FF found.
Checking read port `\u_graph_engine.w_mem'[6] in module `\spi_neuron_top': no output FF found.
Checking read port `\u_graph_engine.w_mem'[7] in module `\spi_neuron_top': no output FF found.
Checking read port `\u_graph_engine.w_mem'[8] in module `\spi_neuron_top': no output FF found.
Checking read port `\u_graph_engine.w_mem'[9] in module `\spi_neuron_top': no output FF found.
Checking read port `\u_graph_engine.w_mem'[10] in module `\spi_neuron_top': no output FF found.
Checking read port `\u_graph_engine.w_mem'[11] in module `\spi_neuron_top': no output FF found.
Checking read port `\u_graph_engine.w_mem'[12] in module `\spi_neuron_top': no output FF found.
Checking read port `\u_graph_engine.w_mem'[13] in module `\spi_neuron_top': no output FF found.
Checking read port `\u_graph_engine.w_mem'[14] in module `\spi_neuron_top': no output FF found.
Checking read port `\u_graph_engine.w_mem'[15] in module `\spi_neuron_top': no output FF found.
Checking read port `\u_graph_engine.w_mem'[16] in module `\spi_neuron_top': no output FF found.
Checking read port `\u_graph_engine.w_mem'[17] in module `\spi_neuron_top': no output FF found.
Checking read port `\u_graph_engine.w_mem'[18] in module `\spi_neuron_top': no output FF found.
Checking read port `\u_graph_engine.w_mem'[19] in module `\spi_neuron_top': no output FF found.
Checking read port `\u_graph_engine.w_mem'[20] in module `\spi_neuron_top': no output FF found.
Checking read port `\u_graph_engine.w_mem'[21] in module `\spi_neuron_top': no output FF found.
Checking read port `\u_graph_engine.w_mem'[22] in module `\spi_neuron_top': no output FF found.
Checking read port `\u_graph_engine.w_mem'[23] in module `\spi_neuron_top': no output FF found.
Checking read port `\u_graph_engine.w_mem'[24] in module `\spi_neuron_top': no output FF found.
Checking read port `\u_graph_engine.w_mem'[25] in module `\spi_neuron_top': no output FF found.
Checking read port `\u_graph_engine.w_mem'[26] in module `\spi_neuron_top': no output FF found.
Checking read port `\u_graph_engine.w_mem'[27] in module `\spi_neuron_top': no output FF found.
Checking read port `\u_graph_engine.w_mem'[28] in module `\spi_neuron_top': no output FF found.
Checking read port `\u_graph_engine.w_mem'[29] in module `\spi_neuron_top': no output FF found.
Checking read port `\u_graph_engine.w_mem'[30] in module `\spi_neuron_top': no output FF found.
Checking read port `\u_graph_engine.w_mem'[31] in module `\spi_neuron_top': no output FF found.
Checking read port `\u_graph_engine.u_act_buffer.mem'[0] in module `\spi_neuron_top': merging output FF to cell.
Write port 0: non-transparent.
Checking read port `\u_neuron_memory.y_reg'[0] in module `\spi_neuron_top': no output FF found.
Checking read port `\u_neuron_memory.x_mem'[0] in module `\spi_neuron_top': no output FF found.
Checking read port `\u_neuron_memory.x_mem'[1] in module `\spi_neuron_top': no output FF found.
Checking read port `\u_neuron_memory.x_mem'[2] in module `\spi_neuron_top': no output FF found.
Checking read port `\u_neuron_memory.x_mem'[3] in module `\spi_neuron_top': no output FF found.
Checking read port `\u_neuron_memory.x_mem'[4] in module `\spi_neuron_top': no output FF found.
Checking read port `\u_neuron_memory.x_mem'[5] in module `\spi_neuron_top': no output FF found.
Checking read port `\u_neuron_memory.x_mem'[6] in module `\spi_neuron_top': no output FF found.
Checking read port `\u_neuron_memory.x_mem'[7] in module `\spi_neuron_top': no output FF found.
Checking read port `\u_neuron_memory.x_mem'[8] in module `\spi_neuron_top': no output FF found.
Checking read port `\u_neuron_memory.x_mem'[9] in module `\spi_neuron_top': no output FF found.
Checking read port `\u_neuron_memory.x_mem'[10] in module `\spi_neuron_top': no output FF found.
Checking read port `\u_neuron_memory.x_mem'[11] in module `\spi_neuron_top': no output FF found.
Checking read port `\u_neuron_memory.x_mem'[12] in module `\spi_neuron_top': no output FF found.
Checking read port `\u_neuron_memory.x_mem'[13] in module `\spi_neuron_top': no output FF found.
Checking read port `\u_neuron_memory.x_mem'[14] in module `\spi_neuron_top': no output FF found.
Checking read port `\u_neuron_memory.x_mem'[15] in module `\spi_neuron_top': no output FF found.
Checking read port `\u_neuron_memory.x_mem'[16] in module `\spi_neuron_top': no output FF found.
Checking read port `\u_neuron_memory.x_mem'[17] in module `\spi_neuron_top': no output FF found.
Checking read port `\u_neuron_memory.x_mem'[18] in module `\spi_neuron_top': no output FF found.
Checking read port `\u_neuron_memory.x_mem'[19] in module `\spi_neuron_top': no output FF found.
Checking read port `\u_neuron_memory.x_mem'[20] in module `\spi_neuron_top': no output FF found.
Checking read port `\u_neuron_memory.x_mem'[21] in module `\spi_neuron_top': no output FF found.
Checking read port `\u_neuron_memory.x_mem'[22] in module `\spi_neuron_top': no output FF found.
Checking read port `\u_neuron_memory.x_mem'[23] in module `\spi_neuron_top': no output FF found.
Checking read port `\u_neuron_memory.x_mem'[24] in module `\spi_neuron_top': no output FF found.
Checking read port `\u_neuron_memory.x_mem'[25] in module `\spi_neuron_top': no output FF found.
Checking read port `\u_neuron_memory.x_mem'[26] in module `\spi_neuron_top': no output FF found.
Checking read port `\u_neuron_memory.x_mem'[27] in module `\spi_neuron_top': no output FF found.
Checking read port `\u_neuron_memory.x_mem'[28] in module `\spi_neuron_top': no output FF found.
Checking read port `\u_neuron_memory.x_mem'[29] in module `\spi_neuron_top': no output FF found.
Checking read port `\u_neuron_memory.x_mem'[30] in module `\spi_neuron_top': no output FF found.
Checking read port `\u_neuron_memory.x_mem'[31] in module `\spi_neuron_top': no output FF found.
Checking read port `\u_neuron_memory.w_mem'[0] in module `\spi_neuron_top': no output FF found.
Checking read port `\u_neuron_memory.w_mem'[1] in module `\spi_neuron_top': no output FF found.
Checking read port `\u_neuron_memory.w_mem'[2] in module `\spi_neuron_top': no output FF found.
Checking read port `\u_neuron_memory.w_mem'[3] in module `\spi_neuron_top': no output FF found.
Checking read port `\u_neuron_memory.w_mem'[4] in module `\spi_neuron_top': no output FF found.
Checking read port `\u_neuron_memory.w_mem'[5] in module `\spi_neuron_top': no output FF found.
Checking read port `\u_neuron_memory.w_mem'[6] in module `\spi_neuron_top': no output FF found.
Checking read port `\u_neuron_memory.w_mem'[7] in module `\spi_neuron_top': no output FF found.
Checking read port `\u_neuron_memory.w_mem'[8] in module `\spi_neuron_top': no output FF found.
Checking read port `\u_neuron_memory.w_mem'[9] in module `\spi_neuron_top': no output FF found.
Checking read port `\u_neuron_memory.w_mem'[10] in module `\spi_neuron_top': no output FF found.
Checking read port `\u_neuron_memory.w_mem'[11] in module `\spi_neuron_top': no output FF found.
Checking read port `\u_neuron_memory.w_mem'[12] in module `\spi_neuron_top': no output FF found.
Checking read port `\u_neuron_memory.w_mem'[13] in module `\spi_neuron_top': no output FF found.
Checking read port `\u_neuron_memory.w_mem'[14] in module `\spi_neuron_top': no output FF found.
Checking read port `\u_neuron_memory.w_mem'[15] in module `\spi_neuron_top': no output FF found.
Checking read port `\u_neuron_memory.w_mem'[16] in module `\spi_neuron_top': no output FF found.
Checking read port `\u_neuron_memory.w_mem'[17] in module `\spi_neuron_top': no output FF found.
Checking read port `\u_neuron_memory.w_mem'[18] in module `\spi_neuron_top': no output FF found.
Checking read port `\u_neuron_memory.w_mem'[19] in module `\spi_neuron_top': no output FF found.
Checking read port `\u_neuron_memory.w_mem'[20] in module `\spi_neuron_top': no output FF found.
Checking read port `\u_neuron_memory.w_mem'[21] in module `\spi_neuron_top': no output FF found.
Checking read port `\u_neuron_memory.w_mem'[22] in module `\spi_neuron_top': no output FF found.
Checking read port `\u_neuron_memory.w_mem'[23] in module `\spi_neuron_top': no output FF found.
Checking read port `\u_neuron_memory.w_mem'[24] in module `\spi_neuron_top': no output FF found.
Checking read port `\u_neuron_memory.w_mem'[25] in module `\spi_neuron_top': no output FF found.
Checking read port `\u_neuron_memory.w_mem'[26] in module `\spi_neuron_top': no output FF found.
Checking read port `\u_neuron_memory.w_mem'[27] in module `\spi_neuron_top': no output FF found.
Checking read port `\u_neuron_memory.w_mem'[28] in module `\spi_neuron_top': no output FF found.
Checking read port `\u_neuron_memory.w_mem'[29] in module `\spi_neuron_top': no output FF found.
Checking read port `\u_neuron_memory.w_mem'[30] in module `\spi_neuron_top': no output FF found.
Checking read port `\u_neuron_memory.w_mem'[31] in module `\spi_neuron_top': no output FF found.
Checking read port address `$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1540'[0] in module `\spi_neuron_top': merged address FF to cell.
Checking read port address `\u_graph_engine.x_mem'[0] in module `\spi_neuron_top': no address FF found.
Checking read port address `\u_graph_engine.x_mem'[1] in module `\spi_neuron_top': no address FF found.
Checking read port address `\u_graph_engine.x_mem'[2] in module `\spi_neuron_top': no address FF found.
Checking read port address `\u_graph_engine.x_mem'[3] in module `\spi_neuron_top': no address FF found.
Checking read port address `\u_graph_engine.x_mem'[4] in module `\spi_neuron_top': no address FF found.
Checking read port address `\u_graph_engine.x_mem'[5] in module `\spi_neuron_top': no address FF found.
Checking read port address `\u_graph_engine.x_mem'[6] in module `\spi_neuron_top': no address FF found.
Checking read port address `\u_graph_engine.x_mem'[7] in module `\spi_neuron_top': no address FF found.
Checking read port address `\u_graph_engine.x_mem'[8] in module `\spi_neuron_top': no address FF found.
Checking read port address `\u_graph_engine.x_mem'[9] in module `\spi_neuron_top': no address FF found.
Checking read port address `\u_graph_engine.x_mem'[10] in module `\spi_neuron_top': no address FF found.
Checking read port address `\u_graph_engine.x_mem'[11] in module `\spi_neuron_top': no address FF found.
Checking read port address `\u_graph_engine.x_mem'[12] in module `\spi_neuron_top': no address FF found.
Checking read port address `\u_graph_engine.x_mem'[13] in module `\spi_neuron_top': no address FF found.
Checking read port address `\u_graph_engine.x_mem'[14] in module `\spi_neuron_top': no address FF found.
Checking read port address `\u_graph_engine.x_mem'[15] in module `\spi_neuron_top': no address FF found.
Checking read port address `\u_graph_engine.x_mem'[16] in module `\spi_neuron_top': no address FF found.
Checking read port address `\u_graph_engine.x_mem'[17] in module `\spi_neuron_top': no address FF found.
Checking read port address `\u_graph_engine.x_mem'[18] in module `\spi_neuron_top': no address FF found.
Checking read port address `\u_graph_engine.x_mem'[19] in module `\spi_neuron_top': no address FF found.
Checking read port address `\u_graph_engine.x_mem'[20] in module `\spi_neuron_top': no address FF found.
Checking read port address `\u_graph_engine.x_mem'[21] in module `\spi_neuron_top': no address FF found.
Checking read port address `\u_graph_engine.x_mem'[22] in module `\spi_neuron_top': no address FF found.
Checking read port address `\u_graph_engine.x_mem'[23] in module `\spi_neuron_top': no address FF found.
Checking read port address `\u_graph_engine.x_mem'[24] in module `\spi_neuron_top': no address FF found.
Checking read port address `\u_graph_engine.x_mem'[25] in module `\spi_neuron_top': no address FF found.
Checking read port address `\u_graph_engine.x_mem'[26] in module `\spi_neuron_top': no address FF found.
Checking read port address `\u_graph_engine.x_mem'[27] in module `\spi_neuron_top': no address FF found.
Checking read port address `\u_graph_engine.x_mem'[28] in module `\spi_neuron_top': no address FF found.
Checking read port address `\u_graph_engine.x_mem'[29] in module `\spi_neuron_top': no address FF found.
Checking read port address `\u_graph_engine.x_mem'[30] in module `\spi_neuron_top': no address FF found.
Checking read port address `\u_graph_engine.x_mem'[31] in module `\spi_neuron_top': no address FF found.
Checking read port address `\u_graph_engine.w_mem'[0] in module `\spi_neuron_top': no address FF found.
Checking read port address `\u_graph_engine.w_mem'[1] in module `\spi_neuron_top': no address FF found.
Checking read port address `\u_graph_engine.w_mem'[2] in module `\spi_neuron_top': no address FF found.
Checking read port address `\u_graph_engine.w_mem'[3] in module `\spi_neuron_top': no address FF found.
Checking read port address `\u_graph_engine.w_mem'[4] in module `\spi_neuron_top': no address FF found.
Checking read port address `\u_graph_engine.w_mem'[5] in module `\spi_neuron_top': no address FF found.
Checking read port address `\u_graph_engine.w_mem'[6] in module `\spi_neuron_top': no address FF found.
Checking read port address `\u_graph_engine.w_mem'[7] in module `\spi_neuron_top': no address FF found.
Checking read port address `\u_graph_engine.w_mem'[8] in module `\spi_neuron_top': no address FF found.
Checking read port address `\u_graph_engine.w_mem'[9] in module `\spi_neuron_top': no address FF found.
Checking read port address `\u_graph_engine.w_mem'[10] in module `\spi_neuron_top': no address FF found.
Checking read port address `\u_graph_engine.w_mem'[11] in module `\spi_neuron_top': no address FF found.
Checking read port address `\u_graph_engine.w_mem'[12] in module `\spi_neuron_top': no address FF found.
Checking read port address `\u_graph_engine.w_mem'[13] in module `\spi_neuron_top': no address FF found.
Checking read port address `\u_graph_engine.w_mem'[14] in module `\spi_neuron_top': no address FF found.
Checking read port address `\u_graph_engine.w_mem'[15] in module `\spi_neuron_top': no address FF found.
Checking read port address `\u_graph_engine.w_mem'[16] in module `\spi_neuron_top': no address FF found.
Checking read port address `\u_graph_engine.w_mem'[17] in module `\spi_neuron_top': no address FF found.
Checking read port address `\u_graph_engine.w_mem'[18] in module `\spi_neuron_top': no address FF found.
Checking read port address `\u_graph_engine.w_mem'[19] in module `\spi_neuron_top': no address FF found.
Checking read port address `\u_graph_engine.w_mem'[20] in module `\spi_neuron_top': no address FF found.
Checking read port address `\u_graph_engine.w_mem'[21] in module `\spi_neuron_top': no address FF found.
Checking read port address `\u_graph_engine.w_mem'[22] in module `\spi_neuron_top': no address FF found.
Checking read port address `\u_graph_engine.w_mem'[23] in module `\spi_neuron_top': no address FF found.
Checking read port address `\u_graph_engine.w_mem'[24] in module `\spi_neuron_top': no address FF found.
Checking read port address `\u_graph_engine.w_mem'[25] in module `\spi_neuron_top': no address FF found.
Checking read port address `\u_graph_engine.w_mem'[26] in module `\spi_neuron_top': no address FF found.
Checking read port address `\u_graph_engine.w_mem'[27] in module `\spi_neuron_top': no address FF found.
Checking read port address `\u_graph_engine.w_mem'[28] in module `\spi_neuron_top': no address FF found.
Checking read port address `\u_graph_engine.w_mem'[29] in module `\spi_neuron_top': no address FF found.
Checking read port address `\u_graph_engine.w_mem'[30] in module `\spi_neuron_top': no address FF found.
Checking read port address `\u_graph_engine.w_mem'[31] in module `\spi_neuron_top': no address FF found.
Checking read port address `\u_neuron_memory.y_reg'[0] in module `\spi_neuron_top': no address FF found.
Checking read port address `\u_neuron_memory.x_mem'[0] in module `\spi_neuron_top': no address FF found.
Checking read port address `\u_neuron_memory.x_mem'[1] in module `\spi_neuron_top': no address FF found.
Checking read port address `\u_neuron_memory.x_mem'[2] in module `\spi_neuron_top': no address FF found.
Checking read port address `\u_neuron_memory.x_mem'[3] in module `\spi_neuron_top': no address FF found.
Checking read port address `\u_neuron_memory.x_mem'[4] in module `\spi_neuron_top': no address FF found.
Checking read port address `\u_neuron_memory.x_mem'[5] in module `\spi_neuron_top': no address FF found.
Checking read port address `\u_neuron_memory.x_mem'[6] in module `\spi_neuron_top': no address FF found.
Checking read port address `\u_neuron_memory.x_mem'[7] in module `\spi_neuron_top': no address FF found.
Checking read port address `\u_neuron_memory.x_mem'[8] in module `\spi_neuron_top': no address FF found.
Checking read port address `\u_neuron_memory.x_mem'[9] in module `\spi_neuron_top': no address FF found.
Checking read port address `\u_neuron_memory.x_mem'[10] in module `\spi_neuron_top': no address FF found.
Checking read port address `\u_neuron_memory.x_mem'[11] in module `\spi_neuron_top': no address FF found.
Checking read port address `\u_neuron_memory.x_mem'[12] in module `\spi_neuron_top': no address FF found.
Checking read port address `\u_neuron_memory.x_mem'[13] in module `\spi_neuron_top': no address FF found.
Checking read port address `\u_neuron_memory.x_mem'[14] in module `\spi_neuron_top': no address FF found.
Checking read port address `\u_neuron_memory.x_mem'[15] in module `\spi_neuron_top': no address FF found.
Checking read port address `\u_neuron_memory.x_mem'[16] in module `\spi_neuron_top': no address FF found.
Checking read port address `\u_neuron_memory.x_mem'[17] in module `\spi_neuron_top': no address FF found.
Checking read port address `\u_neuron_memory.x_mem'[18] in module `\spi_neuron_top': no address FF found.
Checking read port address `\u_neuron_memory.x_mem'[19] in module `\spi_neuron_top': no address FF found.
Checking read port address `\u_neuron_memory.x_mem'[20] in module `\spi_neuron_top': no address FF found.
Checking read port address `\u_neuron_memory.x_mem'[21] in module `\spi_neuron_top': no address FF found.
Checking read port address `\u_neuron_memory.x_mem'[22] in module `\spi_neuron_top': no address FF found.
Checking read port address `\u_neuron_memory.x_mem'[23] in module `\spi_neuron_top': no address FF found.
Checking read port address `\u_neuron_memory.x_mem'[24] in module `\spi_neuron_top': no address FF found.
Checking read port address `\u_neuron_memory.x_mem'[25] in module `\spi_neuron_top': no address FF found.
Checking read port address `\u_neuron_memory.x_mem'[26] in module `\spi_neuron_top': no address FF found.
Checking read port address `\u_neuron_memory.x_mem'[27] in module `\spi_neuron_top': no address FF found.
Checking read port address `\u_neuron_memory.x_mem'[28] in module `\spi_neuron_top': no address FF found.
Checking read port address `\u_neuron_memory.x_mem'[29] in module `\spi_neuron_top': no address FF found.
Checking read port address `\u_neuron_memory.x_mem'[30] in module `\spi_neuron_top': no address FF found.
Checking read port address `\u_neuron_memory.x_mem'[31] in module `\spi_neuron_top': no address FF found.
Checking read port address `\u_neuron_memory.w_mem'[0] in module `\spi_neuron_top': no address FF found.
Checking read port address `\u_neuron_memory.w_mem'[1] in module `\spi_neuron_top': no address FF found.
Checking read port address `\u_neuron_memory.w_mem'[2] in module `\spi_neuron_top': no address FF found.
Checking read port address `\u_neuron_memory.w_mem'[3] in module `\spi_neuron_top': no address FF found.
Checking read port address `\u_neuron_memory.w_mem'[4] in module `\spi_neuron_top': no address FF found.
Checking read port address `\u_neuron_memory.w_mem'[5] in module `\spi_neuron_top': no address FF found.
Checking read port address `\u_neuron_memory.w_mem'[6] in module `\spi_neuron_top': no address FF found.
Checking read port address `\u_neuron_memory.w_mem'[7] in module `\spi_neuron_top': no address FF found.
Checking read port address `\u_neuron_memory.w_mem'[8] in module `\spi_neuron_top': no address FF found.
Checking read port address `\u_neuron_memory.w_mem'[9] in module `\spi_neuron_top': no address FF found.
Checking read port address `\u_neuron_memory.w_mem'[10] in module `\spi_neuron_top': no address FF found.
Checking read port address `\u_neuron_memory.w_mem'[11] in module `\spi_neuron_top': no address FF found.
Checking read port address `\u_neuron_memory.w_mem'[12] in module `\spi_neuron_top': no address FF found.
Checking read port address `\u_neuron_memory.w_mem'[13] in module `\spi_neuron_top': no address FF found.
Checking read port address `\u_neuron_memory.w_mem'[14] in module `\spi_neuron_top': no address FF found.
Checking read port address `\u_neuron_memory.w_mem'[15] in module `\spi_neuron_top': no address FF found.
Checking read port address `\u_neuron_memory.w_mem'[16] in module `\spi_neuron_top': no address FF found.
Checking read port address `\u_neuron_memory.w_mem'[17] in module `\spi_neuron_top': no address FF found.
Checking read port address `\u_neuron_memory.w_mem'[18] in module `\spi_neuron_top': no address FF found.
Checking read port address `\u_neuron_memory.w_mem'[19] in module `\spi_neuron_top': no address FF found.
Checking read port address `\u_neuron_memory.w_mem'[20] in module `\spi_neuron_top': no address FF found.
Checking read port address `\u_neuron_memory.w_mem'[21] in module `\spi_neuron_top': no address FF found.
Checking read port address `\u_neuron_memory.w_mem'[22] in module `\spi_neuron_top': no address FF found.
Checking read port address `\u_neuron_memory.w_mem'[23] in module `\spi_neuron_top': no address FF found.
Checking read port address `\u_neuron_memory.w_mem'[24] in module `\spi_neuron_top': no address FF found.
Checking read port address `\u_neuron_memory.w_mem'[25] in module `\spi_neuron_top': no address FF found.
Checking read port address `\u_neuron_memory.w_mem'[26] in module `\spi_neuron_top': no address FF found.
Checking read port address `\u_neuron_memory.w_mem'[27] in module `\spi_neuron_top': no address FF found.
Checking read port address `\u_neuron_memory.w_mem'[28] in module `\spi_neuron_top': no address FF found.
Checking read port address `\u_neuron_memory.w_mem'[29] in module `\spi_neuron_top': no address FF found.
Checking read port address `\u_neuron_memory.w_mem'[30] in module `\spi_neuron_top': no address FF found.
Checking read port address `\u_neuron_memory.w_mem'[31] in module `\spi_neuron_top': no address FF found.
17.26.6. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \spi_neuron_top..
Removed 1 unused cells and 9 unused wires.
<suppressed ~2 debug messages>
17.26.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells).
Consolidating read ports of memory spi_neuron_top.u_graph_engine.x_mem by address:
Merging ports 0, 1 (address 5'00001).
Merging ports 0, 2 (address 5'00000).
Merging ports 0, 3 (address 5'00000).
Merging ports 0, 28 (address 5'00000).
Merging ports 0, 29 (address 5'00000).
Merging ports 0, 30 (address 5'00000).
Merging ports 0, 31 (address 5'00000).
Merging ports 4, 5 (address 5'11111).
Merging ports 4, 6 (address 5'11110).
Merging ports 4, 7 (address 5'11100).
Merging ports 4, 8 (address 5'11100).
Merging ports 4, 9 (address 5'11000).
Merging ports 4, 10 (address 5'11000).
Merging ports 4, 11 (address 5'11000).
Merging ports 4, 12 (address 5'11000).
Merging ports 4, 13 (address 5'10000).
Merging ports 4, 14 (address 5'10000).
Merging ports 4, 15 (address 5'10000).
Merging ports 4, 16 (address 5'10000).
Merging ports 4, 17 (address 5'10000).
Merging ports 4, 18 (address 5'10000).
Merging ports 4, 19 (address 5'10000).
Merging ports 4, 20 (address 5'10000).
Merging ports 22, 23 (address 5'01101).
Merging ports 24, 25 (address 5'01011).
Merging ports 24, 26 (address 5'01010).
Merging ports 24, 27 (address 5'01000).
Consolidating read ports of memory spi_neuron_top.u_graph_engine.x_mem by address:
Merging ports 0, 2 (address 5'00000).
Merging ports 0, 3 (address 5'00000).
Merging ports 0, 4 (address 5'00000).
Consolidating read ports of memory spi_neuron_top.u_graph_engine.x_mem by address:
Consolidating write ports of memory spi_neuron_top.u_graph_engine.x_mem by address:
Merging ports 0, 1 (address 5'00000).
Merging ports 0, 2 (address 5'00000).
Merging ports 0, 3 (address 5'00000).
Merging ports 0, 4 (address 5'00000).
Merging ports 0, 5 (address 5'00000).
Merging ports 0, 6 (address 5'00000).
Merging ports 0, 7 (address 5'00000).
Merging ports 0, 8 (address 5'00000).
Merging ports 0, 9 (address 5'00000).
Merging ports 0, 10 (address 5'00000).
Merging ports 0, 11 (address 5'00000).
Merging ports 0, 12 (address 5'00000).
Merging ports 0, 13 (address 5'00000).
Merging ports 0, 14 (address 5'00000).
Merging ports 0, 15 (address 5'00000).
Merging ports 0, 16 (address 5'00000).
Merging ports 18, 19 (address 5'10010).
Merging ports 20, 21 (address 5'10100).
Merging ports 20, 22 (address 5'10100).
Merging ports 20, 23 (address 5'10100).
Merging ports 24, 25 (address 5'11000).
Merging ports 24, 26 (address 5'11000).
Merging ports 24, 27 (address 5'11000).
Merging ports 24, 28 (address 5'11000).
Merging ports 24, 29 (address 5'11000).
Merging ports 24, 30 (address 5'11000).
Merging ports 24, 31 (address 5'11000).
Consolidating write ports of memory spi_neuron_top.u_graph_engine.x_mem by address:
Merging ports 1, 2 (address 5'10001).
Merging ports 1, 3 (address 5'10000).
Merging ports 1, 4 (address 5'10000).
Consolidating write ports of memory spi_neuron_top.u_graph_engine.x_mem by address:
Consolidating read ports of memory spi_neuron_top.u_graph_engine.w_mem by address:
Merging ports 0, 1 (address 5'00001).
Merging ports 0, 2 (address 5'00000).
Merging ports 0, 27 (address 5'00000).
Merging ports 0, 28 (address 5'00000).
Merging ports 0, 29 (address 5'00000).
Merging ports 0, 30 (address 5'00000).
Merging ports 0, 31 (address 5'00000).
Merging ports 3, 4 (address 5'11111).
Merging ports 3, 5 (address 5'11110).
Merging ports 3, 6 (address 5'11100).
Merging ports 3, 7 (address 5'11100).
Merging ports 3, 8 (address 5'11000).
Merging ports 3, 9 (address 5'11000).
Merging ports 3, 10 (address 5'11000).
Merging ports 3, 11 (address 5'11000).
Merging ports 3, 12 (address 5'10000).
Merging ports 3, 13 (address 5'10000).
Merging ports 3, 14 (address 5'10000).
Merging ports 3, 15 (address 5'10000).
Merging ports 3, 16 (address 5'10000).
Merging ports 3, 17 (address 5'10000).
Merging ports 3, 18 (address 5'10000).
Merging ports 3, 19 (address 5'10000).
Merging ports 21, 22 (address 5'01101).
Merging ports 23, 24 (address 5'01011).
Merging ports 23, 25 (address 5'01010).
Merging ports 23, 26 (address 5'01000).
Consolidating read ports of memory spi_neuron_top.u_graph_engine.w_mem by address:
Merging ports 0, 2 (address 5'00000).
Merging ports 0, 3 (address 5'00000).
Merging ports 0, 4 (address 5'00000).
Consolidating read ports of memory spi_neuron_top.u_graph_engine.w_mem by address:
Consolidating write ports of memory spi_neuron_top.u_graph_engine.w_mem by address:
Merging ports 0, 1 (address 5'00000).
Merging ports 0, 2 (address 5'00000).
Merging ports 0, 3 (address 5'00000).
Merging ports 0, 4 (address 5'00000).
Merging ports 0, 5 (address 5'00000).
Merging ports 0, 6 (address 5'00000).
Merging ports 0, 7 (address 5'00000).
Merging ports 0, 8 (address 5'00000).
Merging ports 0, 9 (address 5'00000).
Merging ports 0, 10 (address 5'00000).
Merging ports 0, 11 (address 5'00000).
Merging ports 0, 12 (address 5'00000).
Merging ports 0, 13 (address 5'00000).
Merging ports 0, 14 (address 5'00000).
Merging ports 0, 15 (address 5'00000).
Merging ports 0, 16 (address 5'00000).
Merging ports 18, 19 (address 5'10010).
Merging ports 20, 21 (address 5'10100).
Merging ports 20, 22 (address 5'10100).
Merging ports 20, 23 (address 5'10100).
Merging ports 24, 25 (address 5'11000).
Merging ports 24, 26 (address 5'11000).
Merging ports 24, 27 (address 5'11000).
Merging ports 24, 28 (address 5'11000).
Merging ports 24, 29 (address 5'11000).
Merging ports 24, 30 (address 5'11000).
Merging ports 24, 31 (address 5'11000).
Consolidating write ports of memory spi_neuron_top.u_graph_engine.w_mem by address:
Merging ports 1, 2 (address 5'10001).
Merging ports 1, 3 (address 5'10000).
Merging ports 1, 4 (address 5'10000).
Consolidating write ports of memory spi_neuron_top.u_graph_engine.w_mem by address:
Consolidating write ports of memory spi_neuron_top.u_neuron_memory.y_reg by address:
Consolidating read ports of memory spi_neuron_top.u_neuron_memory.x_mem by address:
Merging ports 0, 1 (address 5'11111).
Merging ports 0, 2 (address 5'11110).
Merging ports 0, 3 (address 5'11100).
Merging ports 0, 4 (address 5'11100).
Merging ports 0, 5 (address 5'11000).
Merging ports 0, 6 (address 5'11000).
Merging ports 0, 7 (address 5'11000).
Merging ports 0, 8 (address 5'11000).
Merging ports 0, 9 (address 5'10000).
Merging ports 0, 10 (address 5'10000).
Merging ports 0, 11 (address 5'10000).
Merging ports 0, 12 (address 5'10000).
Merging ports 0, 13 (address 5'10000).
Merging ports 0, 14 (address 5'10000).
Merging ports 0, 15 (address 5'10000).
Merging ports 0, 16 (address 5'10000).
Merging ports 18, 19 (address 5'01101).
Merging ports 20, 21 (address 5'01011).
Merging ports 20, 22 (address 5'01010).
Merging ports 20, 23 (address 5'01000).
Merging ports 24, 25 (address 5'00111).
Merging ports 24, 26 (address 5'00110).
Merging ports 24, 27 (address 5'00100).
Merging ports 24, 28 (address 5'00100).
Merging ports 24, 29 (address 5'00000).
Merging ports 24, 30 (address 5'00000).
Merging ports 24, 31 (address 5'00000).
Consolidating read ports of memory spi_neuron_top.u_neuron_memory.x_mem by address:
Merging ports 1, 2 (address 5'01110).
Merging ports 1, 3 (address 5'01100).
Merging ports 1, 4 (address 5'01000).
Consolidating read ports of memory spi_neuron_top.u_neuron_memory.x_mem by address:
Consolidating read ports of memory spi_neuron_top.u_neuron_memory.w_mem by address:
Merging ports 0, 1 (address 5'11111).
Merging ports 0, 2 (address 5'11110).
Merging ports 0, 3 (address 5'11100).
Merging ports 0, 4 (address 5'11100).
Merging ports 0, 5 (address 5'11000).
Merging ports 0, 6 (address 5'11000).
Merging ports 0, 7 (address 5'11000).
Merging ports 0, 8 (address 5'11000).
Merging ports 0, 9 (address 5'10000).
Merging ports 0, 10 (address 5'10000).
Merging ports 0, 11 (address 5'10000).
Merging ports 0, 12 (address 5'10000).
Merging ports 0, 13 (address 5'10000).
Merging ports 0, 14 (address 5'10000).
Merging ports 0, 15 (address 5'10000).
Merging ports 0, 16 (address 5'10000).
Merging ports 18, 19 (address 5'01101).
Merging ports 20, 21 (address 5'01011).
Merging ports 20, 22 (address 5'01010).
Merging ports 20, 23 (address 5'01000).
Merging ports 24, 25 (address 5'00111).
Merging ports 24, 26 (address 5'00110).
Merging ports 24, 27 (address 5'00100).
Merging ports 24, 28 (address 5'00100).
Merging ports 24, 29 (address 5'00000).
Merging ports 24, 30 (address 5'00000).
Merging ports 24, 31 (address 5'00000).
Consolidating read ports of memory spi_neuron_top.u_neuron_memory.w_mem by address:
Merging ports 1, 2 (address 5'01110).
Merging ports 1, 3 (address 5'01100).
Merging ports 1, 4 (address 5'01000).
Consolidating read ports of memory spi_neuron_top.u_neuron_memory.w_mem by address:
Consolidating write ports of memory spi_neuron_top.u_graph_engine.x_mem using sat-based resource sharing:
Consolidating write ports of memory spi_neuron_top.u_graph_engine.w_mem using sat-based resource sharing:
Consolidating write ports of memory spi_neuron_top.u_neuron_memory.y_reg using sat-based resource sharing:
Checking group clocked with posedge \clk, width 8: ports 0, 1.
Common input cone for all EN signals: 5 cells.
Size of unconstrained SAT problem: 42 variables, 115 clauses
Merging port 1 into port 0.
17.26.8. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide).
Performed a total of 0 transformations.
17.26.9. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \spi_neuron_top..
Removed 1 unused cells and 113 unused wires.
<suppressed ~2 debug messages>
17.26.10. Executing MEMORY_COLLECT pass (generating $mem cells).
17.27. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \spi_neuron_top..
17.28. Executing MEMORY_LIBMAP pass (mapping memories to cells).
using FF mapping for memory spi_neuron_top.$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1540
using FF mapping for memory spi_neuron_top.u_neuron_memory.x_mem
using FF mapping for memory spi_neuron_top.u_neuron_memory.w_mem
using FF mapping for memory spi_neuron_top.u_neuron_memory.y_reg
using FF mapping for memory spi_neuron_top.u_graph_engine.x_mem
using FF mapping for memory spi_neuron_top.u_graph_engine.w_mem
mapping memory spi_neuron_top.u_graph_engine.u_act_buffer.mem via $__DP16KD_
<suppressed ~910 debug messages>
17.29. Executing TECHMAP pass (map to technology primitives).
17.29.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/lutrams_map_trellis.v
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/lutrams_map_trellis.v' to AST representation.
Generating RTLIL representation for module `$__TRELLIS_DPR16X4_'.
Successfully finished Verilog frontend.
17.29.2. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/brams_map_16kd.v
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/brams_map_16kd.v' to AST representation.
Generating RTLIL representation for module `$__DP16KD_'.
Generating RTLIL representation for module `$__PDPW16KD_'.
Successfully finished Verilog frontend.
17.29.3. Continuing TECHMAP pass.
Using template $paramod$c4aea9a221b3d95ca47d9df3d018cdac65e6baac$__DP16KD_ for cells of type $__DP16KD_.
No more expansions possible.
<suppressed ~36 debug messages>
17.30. Executing OPT pass (performing simple optimizations).
17.30.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module spi_neuron_top.
<suppressed ~357 debug messages>
17.30.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\spi_neuron_top'.
Computing hashes of 1187 cells of `\spi_neuron_top'.
Finding duplicate cells in `\spi_neuron_top'.
Removed a total of 0 cells.
17.30.3. Executing OPT_DFF pass (perform DFF optimizations).
Removing always-active EN on $auto$mem.cc:1169:emulate_transparency$8277 ($dffe) from module spi_neuron_top.
17.30.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \spi_neuron_top..
Removed 14 unused cells and 278 unused wires.
<suppressed ~15 debug messages>
17.30.5. Rerunning OPT passes. (Removed registers in this run.)
17.30.6. Executing OPT_EXPR pass (perform const folding).
Optimizing module spi_neuron_top.
<suppressed ~1 debug messages>
17.30.7. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\spi_neuron_top'.
Computing hashes of 1172 cells of `\spi_neuron_top'.
Finding duplicate cells in `\spi_neuron_top'.
Removed a total of 0 cells.
17.30.8. Executing OPT_DFF pass (perform DFF optimizations).
17.30.9. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \spi_neuron_top..
Removed 0 unused cells and 1 unused wires.
<suppressed ~1 debug messages>
17.30.10. Finished fast OPT passes.
17.31. Executing MEMORY_MAP pass (converting memories to logic and flip-flops).
Mapping memory $flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1540 in module \spi_neuron_top:
created 16 $dff cells and 0 static cells of width 6.
Extracted data FF from read port 0 of spi_neuron_top.$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1540: $$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1540$rdreg[0]
read interface: 1 $dff and 15 $mux cells.
write interface: 0 write mux blocks.
Mapping memory \u_neuron_memory.x_mem in module \spi_neuron_top:
created 32 $dff cells and 0 static cells of width 8.
read interface: 0 $dff and 1 $mux cells.
write interface: 32 write mux blocks.
Mapping memory \u_neuron_memory.w_mem in module \spi_neuron_top:
created 32 $dff cells and 0 static cells of width 8.
read interface: 0 $dff and 1 $mux cells.
write interface: 32 write mux blocks.
Mapping memory \u_neuron_memory.y_reg in module \spi_neuron_top:
created 1 $dff cells and 0 static cells of width 8.
read interface: 0 $dff and 0 $mux cells.
write interface: 1 write mux blocks.
Mapping memory \u_graph_engine.x_mem in module \spi_neuron_top:
created 32 $dff cells and 0 static cells of width 8.
read interface: 0 $dff and 1 $mux cells.
write interface: 96 write mux blocks.
Mapping memory \u_graph_engine.w_mem in module \spi_neuron_top:
created 32 $dff cells and 0 static cells of width 8.
read interface: 0 $dff and 1 $mux cells.
write interface: 96 write mux blocks.
17.32. Executing OPT pass (performing simple optimizations).
17.32.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module spi_neuron_top.
<suppressed ~224 debug messages>
17.32.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\spi_neuron_top'.
Computing hashes of 1734 cells of `\spi_neuron_top'.
Finding duplicate cells in `\spi_neuron_top'.
Computing hashes of 1702 cells of `\spi_neuron_top'.
Finding duplicate cells in `\spi_neuron_top'.
<suppressed ~96 debug messages>
Removed a total of 32 cells.
17.32.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \spi_neuron_top..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Replacing known input bits on port B of cell $auto$memory_share.cc:454:consolidate_wr_using_sat$8269: $auto$rtlil.cc:3271:ReduceOr$8263 -> 1'1
Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~662 debug messages>
17.32.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Optimizing cells in module \spi_neuron_top.
Consolidated identical input bits for $mux cell $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1540$rdmux[0][3][5]$8615:
Old ports: A=6'000001, B=6'000000, Y=$memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1540$rdmux[0][2][2]$b$8596
New ports: A=1'1, B=1'0, Y=$memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1540$rdmux[0][2][2]$b$8596 [0]
New connections: $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1540$rdmux[0][2][2]$b$8596 [5:1] = 5'00000
Consolidated identical input bits for $mux cell $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1540$rdmux[0][3][4]$8612:
Old ports: A=6'010000, B=6'000000, Y=$memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1540$rdmux[0][2][2]$a$8595
New ports: A=1'1, B=1'0, Y=$memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1540$rdmux[0][2][2]$a$8595 [4]
New connections: { $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1540$rdmux[0][2][2]$a$8595 [5] $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1540$rdmux[0][2][2]$a$8595 [3:0] } = 5'00000
Consolidated identical input bits for $mux cell $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1540$rdmux[0][3][3]$8609:
Old ports: A=6'000000, B=6'000001, Y=$memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1540$rdmux[0][2][1]$b$8593
New ports: A=1'0, B=1'1, Y=$memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1540$rdmux[0][2][1]$b$8593 [0]
New connections: $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1540$rdmux[0][2][1]$b$8593 [5:1] = 5'00000
Consolidated identical input bits for $mux cell $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1540$rdmux[0][3][1]$8603:
Old ports: A=6'100000, B=6'000001, Y=$memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1540$rdmux[0][2][0]$b$8590
New ports: A=2'10, B=2'01, Y={ $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1540$rdmux[0][2][0]$b$8590 [5] $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1540$rdmux[0][2][0]$b$8590 [0] }
New connections: $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1540$rdmux[0][2][0]$b$8590 [4:1] = 4'0000
Consolidated identical input bits for $mux cell $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1540$rdmux[0][3][0]$8600:
Old ports: A=6'010111, B=6'000000, Y=$memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1540$rdmux[0][2][0]$a$8589
New ports: A=1'1, B=1'0, Y=$memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1540$rdmux[0][2][0]$a$8589 [0]
New connections: $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1540$rdmux[0][2][0]$a$8589 [5:1] = { 1'0 $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1540$rdmux[0][2][0]$a$8589 [0] 1'0 $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1540$rdmux[0][2][0]$a$8589 [0] $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1540$rdmux[0][2][0]$a$8589 [0] }
New ctrl vector for $pmux cell $flatten\u_graph_engine.$procmux$2869: $auto$opt_reduce.cc:137:opt_pmux$10161
New ctrl vector for $pmux cell $flatten\u_graph_engine.$procmux$2892: $auto$opt_reduce.cc:137:opt_pmux$10163
New ctrl vector for $pmux cell $flatten\u_spi_engine.$procmux$4002: \u_spi_engine.state [4]
New ctrl vector for $pmux cell $flatten\u_graph_engine.$procmux$2946: $auto$opt_reduce.cc:137:opt_pmux$10165
New ctrl vector for $pmux cell $flatten\u_graph_engine.$procmux$2964: { $auto$opt_reduce.cc:137:opt_pmux$10169 $auto$opt_reduce.cc:137:opt_pmux$10167 }
New ctrl vector for $pmux cell $flatten\u_graph_engine.$procmux$3000: { $auto$opt_reduce.cc:137:opt_pmux$10171 \u_graph_engine.state [2] }
New ctrl vector for $pmux cell $flatten\u_graph_engine.$procmux$3104: $auto$opt_reduce.cc:137:opt_pmux$10173
New ctrl vector for $pmux cell $flatten\u_spi_engine.$procmux$3928: $auto$opt_reduce.cc:137:opt_pmux$10175
Consolidated identical input bits for $pmux cell $flatten\u_neuron_memory.$procmux$2055:
Old ports: A=1'0, B=2'00, Y=$flatten\u_neuron_memory.$procmux$2055_Y
New connections: $flatten\u_neuron_memory.$procmux$2055_Y = 1'0
New ctrl vector for $pmux cell $flatten\u_neuron_memory.$procmux$2129: { \u_neuron_memory.state [2] \u_neuron_memory.state [3] }
New ctrl vector for $pmux cell $flatten\u_neuron_memory.$procmux$2168: \u_neuron_memory.state [0]
New ctrl vector for $pmux cell $flatten\u_layer_sequencer.$procmux$3409: \u_layer_sequencer.state [2]
New ctrl vector for $pmux cell $flatten\u_spi_engine.$procmux$3955: $auto$opt_reduce.cc:137:opt_pmux$10177
New ctrl vector for $pmux cell $flatten\u_psram_ctrl.$procmux$4852: { \u_psram_ctrl.state [0] $auto$opt_reduce.cc:137:opt_pmux$5631 }
New input vector for $reduce_or cell $auto$opt_reduce.cc:131:opt_pmux$10172: { \u_graph_engine.state [10:9] \u_graph_engine.state [7] }
Optimizing cells in module \spi_neuron_top.
Consolidated identical input bits for $mux cell $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1540$rdmux[0][2][2]$8594:
Old ports: A=$memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1540$rdmux[0][2][2]$a$8595, B=$memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1540$rdmux[0][2][2]$b$8596, Y=$memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1540$rdmux[0][1][1]$a$8586
New ports: A={ $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1540$rdmux[0][2][2]$a$8595 [4] 1'0 }, B={ 1'0 $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1540$rdmux[0][2][2]$b$8596 [0] }, Y={ $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1540$rdmux[0][1][1]$a$8586 [4] $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1540$rdmux[0][1][1]$a$8586 [0] }
New connections: { $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1540$rdmux[0][1][1]$a$8586 [5] $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1540$rdmux[0][1][1]$a$8586 [3:1] } = 4'0000
Consolidated identical input bits for $mux cell $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1540$rdmux[0][2][1]$8591:
Old ports: A=6'001000, B=$memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1540$rdmux[0][2][1]$b$8593, Y=$memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1540$rdmux[0][1][0]$b$8584
New ports: A=2'10, B={ 1'0 $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1540$rdmux[0][2][1]$b$8593 [0] }, Y={ $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1540$rdmux[0][1][0]$b$8584 [3] $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1540$rdmux[0][1][0]$b$8584 [0] }
New connections: { $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1540$rdmux[0][1][0]$b$8584 [5:4] $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1540$rdmux[0][1][0]$b$8584 [2:1] } = 4'0000
Consolidated identical input bits for $mux cell $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1540$rdmux[0][2][0]$8588:
Old ports: A=$memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1540$rdmux[0][2][0]$a$8589, B=$memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1540$rdmux[0][2][0]$b$8590, Y=$memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1540$rdmux[0][1][0]$a$8583
New ports: A={ 1'0 $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1540$rdmux[0][2][0]$a$8589 [0] $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1540$rdmux[0][2][0]$a$8589 [0] }, B={ $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1540$rdmux[0][2][0]$b$8590 [5] 1'0 $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1540$rdmux[0][2][0]$b$8590 [0] }, Y={ $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1540$rdmux[0][1][0]$a$8583 [5] $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1540$rdmux[0][1][0]$a$8583 [1:0] }
New connections: $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1540$rdmux[0][1][0]$a$8583 [4:2] = { $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1540$rdmux[0][1][0]$a$8583 [1] 1'0 $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1540$rdmux[0][1][0]$a$8583 [1] }
Optimizing cells in module \spi_neuron_top.
Consolidated identical input bits for $mux cell $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1540$rdmux[0][1][1]$8585:
Old ports: A=$memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1540$rdmux[0][1][1]$a$8586, B=6'000000, Y=$memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1540$rdmux[0][0][0]$b$8581
New ports: A={ $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1540$rdmux[0][1][1]$a$8586 [4] $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1540$rdmux[0][1][1]$a$8586 [0] }, B=2'00, Y={ $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1540$rdmux[0][0][0]$b$8581 [4] $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1540$rdmux[0][0][0]$b$8581 [0] }
New connections: { $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1540$rdmux[0][0][0]$b$8581 [5] $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1540$rdmux[0][0][0]$b$8581 [3:1] } = 4'0000
Consolidated identical input bits for $mux cell $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1540$rdmux[0][1][0]$8582:
Old ports: A=$memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1540$rdmux[0][1][0]$a$8583, B=$memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1540$rdmux[0][1][0]$b$8584, Y=$memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1540$rdmux[0][0][0]$a$8580
New ports: A={ $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1540$rdmux[0][1][0]$a$8583 [5] 1'0 $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1540$rdmux[0][1][0]$a$8583 [1:0] }, B={ 1'0 $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1540$rdmux[0][1][0]$b$8584 [3] 1'0 $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1540$rdmux[0][1][0]$b$8584 [0] }, Y={ $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1540$rdmux[0][0][0]$a$8580 [5] $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1540$rdmux[0][0][0]$a$8580 [3] $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1540$rdmux[0][0][0]$a$8580 [1:0] }
New connections: { $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1540$rdmux[0][0][0]$a$8580 [4] $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1540$rdmux[0][0][0]$a$8580 [2] } = { $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1540$rdmux[0][0][0]$a$8580 [1] $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1540$rdmux[0][0][0]$a$8580 [1] }
Optimizing cells in module \spi_neuron_top.
Consolidated identical input bits for $mux cell $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1540$rdmux[0][0][0]$8579:
Old ports: A=$memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1540$rdmux[0][0][0]$a$8580, B=$memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1540$rdmux[0][0][0]$b$8581, Y=$$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1540$rdreg[0]$d
New ports: A={ $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1540$rdmux[0][0][0]$a$8580 [5] $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1540$rdmux[0][0][0]$a$8580 [1] $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1540$rdmux[0][0][0]$a$8580 [3] $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1540$rdmux[0][0][0]$a$8580 [1:0] }, B={ 1'0 $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1540$rdmux[0][0][0]$b$8581 [4] 2'00 $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1540$rdmux[0][0][0]$b$8581 [0] }, Y={ $$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1540$rdreg[0]$d [5:3] $$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1540$rdreg[0]$d [1:0] }
New connections: $$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1540$rdreg[0]$d [2] = $$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1540$rdreg[0]$d [1]
Optimizing cells in module \spi_neuron_top.
Performed a total of 26 changes.
17.32.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\spi_neuron_top'.
Computing hashes of 1710 cells of `\spi_neuron_top'.
Finding duplicate cells in `\spi_neuron_top'.
Computing hashes of 1703 cells of `\spi_neuron_top'.
Finding duplicate cells in `\spi_neuron_top'.
<suppressed ~21 debug messages>
Removed a total of 7 cells.
17.32.6. Executing OPT_DFF pass (perform DFF optimizations).
Adding EN signal on $auto$ff.cc:337:slice$7309 ($sdffe) from module spi_neuron_top (D = $flatten\u_graph_engine.$procmux$2869_Y, Q = \u_graph_engine.desc_addr).
Adding EN signal on $auto$ff.cc:337:slice$7323 ($sdffe) from module spi_neuron_top (D = $flatten\u_graph_engine.$procmux$2892_Y, Q = \u_graph_engine.neuron_idx).
Adding EN signal on $auto$ff.cc:337:slice$7366 ($sdffe) from module spi_neuron_top (D = $flatten\u_graph_engine.$procmux$2964_Y, Q = \u_graph_engine.busy).
Adding EN signal on $auto$ff.cc:337:slice$7388 ($sdffe) from module spi_neuron_top (D = $flatten\u_graph_engine.$procmux$3000_Y, Q = \u_graph_engine.desc_byte_idx).
Adding SRST signal on $$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1540$rdreg[0] ($dff) from module spi_neuron_top (D = $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1540$rdmux[0][2][0]$b$8590 [5], Q = $flatten\u_spi_engine.$4\tx_byte_comb[7:0] [5], rval = 1'0).
Adding SRST signal on $$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1540$rdreg[0] ($dff) from module spi_neuron_top (D = $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1540$rdmux[0][1][0]$b$8584 [3], Q = $flatten\u_spi_engine.$4\tx_byte_comb[7:0] [3], rval = 1'0).
17.32.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \spi_neuron_top..
Removed 0 unused cells and 411 unused wires.
<suppressed ~1 debug messages>
17.32.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module spi_neuron_top.
<suppressed ~6 debug messages>
17.32.9. Rerunning OPT passes. (Maybe there is more to do..)
17.32.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \spi_neuron_top..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~645 debug messages>
17.32.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Optimizing cells in module \spi_neuron_top.
New input vector for $reduce_and cell $auto$opt_dff.cc:337:make_patterns_logic$10182: { $auto$opt_dff.cc:319:make_patterns_logic$7234 $auto$opt_dff.cc:319:make_patterns_logic$7310 $auto$opt_dff.cc:319:make_patterns_logic$7312 $auto$opt_dff.cc:319:make_patterns_logic$7314 $auto$opt_dff.cc:319:make_patterns_logic$7318 $auto$opt_dff.cc:319:make_patterns_logic$10179 }
New input vector for $reduce_and cell $auto$opt_dff.cc:337:make_patterns_logic$10187: { $auto$opt_dff.cc:319:make_patterns_logic$7234 $auto$opt_dff.cc:319:make_patterns_logic$7310 $auto$opt_dff.cc:319:make_patterns_logic$7312 $auto$opt_dff.cc:319:make_patterns_logic$7314 $auto$opt_dff.cc:319:make_patterns_logic$7318 $auto$opt_dff.cc:319:make_patterns_logic$10184 }
New input vector for $reduce_and cell $auto$opt_dff.cc:337:make_patterns_logic$10192: { $auto$opt_dff.cc:319:make_patterns_logic$7234 $auto$opt_dff.cc:319:make_patterns_logic$7266 $auto$opt_dff.cc:319:make_patterns_logic$7312 $auto$opt_dff.cc:319:make_patterns_logic$7314 $auto$opt_dff.cc:319:make_patterns_logic$7318 $auto$opt_dff.cc:319:make_patterns_logic$7356 $auto$opt_dff.cc:319:make_patterns_logic$7358 $auto$opt_dff.cc:319:make_patterns_logic$7360 $auto$opt_dff.cc:319:make_patterns_logic$7367 $auto$opt_dff.cc:319:make_patterns_logic$10189 }
New input vector for $reduce_and cell $auto$opt_dff.cc:337:make_patterns_logic$10197: { $auto$opt_dff.cc:319:make_patterns_logic$7232 $auto$opt_dff.cc:319:make_patterns_logic$7234 $auto$opt_dff.cc:319:make_patterns_logic$7264 $auto$opt_dff.cc:319:make_patterns_logic$7314 $auto$opt_dff.cc:319:make_patterns_logic$7318 $auto$opt_dff.cc:319:make_patterns_logic$7397 $auto$opt_dff.cc:319:make_patterns_logic$7399 $auto$opt_dff.cc:319:make_patterns_logic$7403 $auto$opt_dff.cc:319:make_patterns_logic$10194 }
New ctrl vector for $pmux cell $flatten\u_graph_engine.$procmux$2964: $auto$opt_reduce.cc:137:opt_pmux$10210
New ctrl vector for $pmux cell $flatten\u_graph_engine.$procmux$3000: \u_graph_engine.state [2]
New input vector for $reduce_or cell $auto$opt_reduce.cc:131:opt_pmux$10209: { \u_graph_engine.state [11] \u_graph_engine.state [9:8] \u_graph_engine.state [6] }
Optimizing cells in module \spi_neuron_top.
Performed a total of 7 changes.
17.32.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\spi_neuron_top'.
Computing hashes of 1712 cells of `\spi_neuron_top'.
Finding duplicate cells in `\spi_neuron_top'.
Computing hashes of 1710 cells of `\spi_neuron_top'.
Finding duplicate cells in `\spi_neuron_top'.
Computing hashes of 1709 cells of `\spi_neuron_top'.
Finding duplicate cells in `\spi_neuron_top'.
<suppressed ~9 debug messages>
Removed a total of 3 cells.
17.32.13. Executing OPT_DFF pass (perform DFF optimizations).
Adding EN signal on $memory\u_graph_engine.w_mem[19]$9747 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.w_mem$wrmux[19][2][0]$y$10015, Q = \u_graph_engine.w_mem[19]).
Adding EN signal on $memory\u_neuron_memory.x_mem[0]$8624 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.x_mem[0]).
Adding EN signal on $memory\u_neuron_memory.x_mem[1]$8626 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.x_mem[1]).
Adding EN signal on $memory\u_neuron_memory.x_mem[2]$8628 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.x_mem[2]).
Adding EN signal on $memory\u_neuron_memory.x_mem[3]$8630 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.x_mem[3]).
Adding EN signal on $memory\u_neuron_memory.x_mem[4]$8632 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.x_mem[4]).
Adding EN signal on $memory\u_neuron_memory.x_mem[5]$8634 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.x_mem[5]).
Adding EN signal on $memory\u_neuron_memory.x_mem[6]$8636 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.x_mem[6]).
Adding EN signal on $memory\u_neuron_memory.x_mem[7]$8638 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.x_mem[7]).
Adding EN signal on $memory\u_neuron_memory.x_mem[8]$8640 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.x_mem[8]).
Adding EN signal on $memory\u_neuron_memory.x_mem[9]$8642 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.x_mem[9]).
Adding EN signal on $memory\u_neuron_memory.x_mem[10]$8644 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.x_mem[10]).
Adding EN signal on $memory\u_neuron_memory.x_mem[11]$8646 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.x_mem[11]).
Adding EN signal on $memory\u_neuron_memory.x_mem[12]$8648 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.x_mem[12]).
Adding EN signal on $memory\u_neuron_memory.x_mem[13]$8650 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.x_mem[13]).
Adding EN signal on $memory\u_neuron_memory.x_mem[14]$8652 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.x_mem[14]).
Adding EN signal on $memory\u_neuron_memory.x_mem[15]$8654 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.x_mem[15]).
Adding EN signal on $memory\u_neuron_memory.x_mem[16]$8656 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.x_mem[16]).
Adding EN signal on $memory\u_neuron_memory.x_mem[17]$8658 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.x_mem[17]).
Adding EN signal on $memory\u_neuron_memory.x_mem[18]$8660 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.x_mem[18]).
Adding EN signal on $memory\u_neuron_memory.x_mem[19]$8662 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.x_mem[19]).
Adding EN signal on $memory\u_neuron_memory.x_mem[20]$8664 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.x_mem[20]).
Adding EN signal on $memory\u_neuron_memory.x_mem[21]$8666 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.x_mem[21]).
Adding EN signal on $memory\u_neuron_memory.x_mem[22]$8668 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.x_mem[22]).
Adding EN signal on $memory\u_neuron_memory.x_mem[23]$8670 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.x_mem[23]).
Adding EN signal on $memory\u_neuron_memory.x_mem[24]$8672 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.x_mem[24]).
Adding EN signal on $memory\u_neuron_memory.x_mem[25]$8674 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.x_mem[25]).
Adding EN signal on $memory\u_neuron_memory.x_mem[26]$8676 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.x_mem[26]).
Adding EN signal on $memory\u_neuron_memory.x_mem[27]$8678 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.x_mem[27]).
Adding EN signal on $memory\u_neuron_memory.x_mem[28]$8680 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.x_mem[28]).
Adding EN signal on $memory\u_neuron_memory.x_mem[29]$8682 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.x_mem[29]).
Adding EN signal on $memory\u_neuron_memory.x_mem[30]$8684 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.x_mem[30]).
Adding EN signal on $memory\u_neuron_memory.x_mem[31]$8686 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.x_mem[31]).
Adding EN signal on $memory\u_graph_engine.w_mem[15]$9739 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.w_mem$wrmux[15][2][0]$y$9967, Q = \u_graph_engine.w_mem[15]).
Adding EN signal on $memory\u_graph_engine.w_mem[14]$9737 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.w_mem$wrmux[14][2][0]$y$9955, Q = \u_graph_engine.w_mem[14]).
Adding EN signal on $memory\u_graph_engine.w_mem[13]$9735 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.w_mem$wrmux[13][2][0]$y$9943, Q = \u_graph_engine.w_mem[13]).
Adding EN signal on $memory\u_neuron_memory.w_mem[0]$8935 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.w_mem[0]).
Adding EN signal on $memory\u_neuron_memory.w_mem[1]$8937 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.w_mem[1]).
Adding EN signal on $memory\u_neuron_memory.w_mem[2]$8939 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.w_mem[2]).
Adding EN signal on $memory\u_neuron_memory.w_mem[3]$8941 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.w_mem[3]).
Adding EN signal on $memory\u_neuron_memory.w_mem[4]$8943 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.w_mem[4]).
Adding EN signal on $memory\u_neuron_memory.w_mem[5]$8945 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.w_mem[5]).
Adding EN signal on $memory\u_neuron_memory.w_mem[6]$8947 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.w_mem[6]).
Adding EN signal on $memory\u_neuron_memory.w_mem[7]$8949 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.w_mem[7]).
Adding EN signal on $memory\u_neuron_memory.w_mem[8]$8951 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.w_mem[8]).
Adding EN signal on $memory\u_neuron_memory.w_mem[9]$8953 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.w_mem[9]).
Adding EN signal on $memory\u_neuron_memory.w_mem[10]$8955 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.w_mem[10]).
Adding EN signal on $memory\u_neuron_memory.w_mem[11]$8957 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.w_mem[11]).
Adding EN signal on $memory\u_neuron_memory.w_mem[12]$8959 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.w_mem[12]).
Adding EN signal on $memory\u_neuron_memory.w_mem[13]$8961 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.w_mem[13]).
Adding EN signal on $memory\u_neuron_memory.w_mem[14]$8963 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.w_mem[14]).
Adding EN signal on $memory\u_neuron_memory.w_mem[15]$8965 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.w_mem[15]).
Adding EN signal on $memory\u_neuron_memory.w_mem[16]$8967 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.w_mem[16]).
Adding EN signal on $memory\u_neuron_memory.w_mem[17]$8969 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.w_mem[17]).
Adding EN signal on $memory\u_neuron_memory.w_mem[18]$8971 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.w_mem[18]).
Adding EN signal on $memory\u_neuron_memory.w_mem[19]$8973 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.w_mem[19]).
Adding EN signal on $memory\u_neuron_memory.w_mem[20]$8975 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.w_mem[20]).
Adding EN signal on $memory\u_neuron_memory.w_mem[21]$8977 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.w_mem[21]).
Adding EN signal on $memory\u_neuron_memory.w_mem[22]$8979 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.w_mem[22]).
Adding EN signal on $memory\u_neuron_memory.w_mem[23]$8981 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.w_mem[23]).
Adding EN signal on $memory\u_neuron_memory.w_mem[24]$8983 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.w_mem[24]).
Adding EN signal on $memory\u_neuron_memory.w_mem[25]$8985 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.w_mem[25]).
Adding EN signal on $memory\u_neuron_memory.w_mem[26]$8987 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.w_mem[26]).
Adding EN signal on $memory\u_neuron_memory.w_mem[27]$8989 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.w_mem[27]).
Adding EN signal on $memory\u_neuron_memory.w_mem[28]$8991 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.w_mem[28]).
Adding EN signal on $memory\u_neuron_memory.w_mem[29]$8993 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.w_mem[29]).
Adding EN signal on $memory\u_neuron_memory.w_mem[30]$8995 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.w_mem[30]).
Adding EN signal on $memory\u_neuron_memory.w_mem[31]$8997 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.w_mem[31]).
Adding EN signal on $memory\u_graph_engine.w_mem[16]$9741 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.w_mem$wrmux[16][2][0]$y$9979, Q = \u_graph_engine.w_mem[16]).
Adding EN signal on $memory\u_neuron_memory.y_reg[0]$9130 ($dff) from module spi_neuron_top (D = $auto$rtlil.cc:3402:Mux$8267, Q = \u_neuron_memory.y_reg[0]).
Adding SRST signal on $auto$ff.cc:337:slice$10290 ($dffe) from module spi_neuron_top (D = \u_neuron_memory.u_neuron.y, Q = \u_neuron_memory.y_reg[0], rval = 8'00000000).
Adding EN signal on $memory\u_graph_engine.w_mem[20]$9749 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.w_mem$wrmux[20][2][0]$y$10027, Q = \u_graph_engine.w_mem[20]).
Adding EN signal on $memory\u_graph_engine.x_mem[0]$9138 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.x_mem$wrmux[0][2][0]$y$9236, Q = \u_graph_engine.x_mem[0]).
Adding EN signal on $memory\u_graph_engine.x_mem[1]$9140 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.x_mem$wrmux[1][2][0]$y$9254, Q = \u_graph_engine.x_mem[1]).
Adding EN signal on $memory\u_graph_engine.x_mem[2]$9142 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.x_mem$wrmux[2][2][0]$y$9272, Q = \u_graph_engine.x_mem[2]).
Adding EN signal on $memory\u_graph_engine.x_mem[3]$9144 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.x_mem$wrmux[3][2][0]$y$9288, Q = \u_graph_engine.x_mem[3]).
Adding EN signal on $memory\u_graph_engine.x_mem[4]$9146 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.x_mem$wrmux[4][2][0]$y$9306, Q = \u_graph_engine.x_mem[4]).
Adding EN signal on $memory\u_graph_engine.x_mem[5]$9148 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.x_mem$wrmux[5][2][0]$y$9320, Q = \u_graph_engine.x_mem[5]).
Adding EN signal on $memory\u_graph_engine.x_mem[6]$9150 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.x_mem$wrmux[6][2][0]$y$9334, Q = \u_graph_engine.x_mem[6]).
Adding EN signal on $memory\u_graph_engine.x_mem[7]$9152 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.x_mem$wrmux[7][2][0]$y$9348, Q = \u_graph_engine.x_mem[7]).
Adding EN signal on $memory\u_graph_engine.x_mem[8]$9154 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.x_mem$wrmux[8][2][0]$y$9368, Q = \u_graph_engine.x_mem[8]).
Adding EN signal on $memory\u_graph_engine.x_mem[9]$9156 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.x_mem$wrmux[9][2][0]$y$9382, Q = \u_graph_engine.x_mem[9]).
Adding EN signal on $memory\u_graph_engine.x_mem[10]$9158 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.x_mem$wrmux[10][2][0]$y$9396, Q = \u_graph_engine.x_mem[10]).
Adding EN signal on $memory\u_graph_engine.x_mem[11]$9160 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.x_mem$wrmux[11][2][0]$y$9410, Q = \u_graph_engine.x_mem[11]).
Adding EN signal on $memory\u_graph_engine.x_mem[12]$9162 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.x_mem$wrmux[12][2][0]$y$9426, Q = \u_graph_engine.x_mem[12]).
Adding EN signal on $memory\u_graph_engine.x_mem[13]$9164 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.x_mem$wrmux[13][2][0]$y$9440, Q = \u_graph_engine.x_mem[13]).
Adding EN signal on $memory\u_graph_engine.x_mem[14]$9166 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.x_mem$wrmux[14][2][0]$y$9454, Q = \u_graph_engine.x_mem[14]).
Adding EN signal on $memory\u_graph_engine.x_mem[15]$9168 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.x_mem$wrmux[15][2][0]$y$9468, Q = \u_graph_engine.x_mem[15]).
Adding EN signal on $memory\u_graph_engine.x_mem[16]$9170 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.x_mem$wrmux[16][2][0]$y$9490, Q = \u_graph_engine.x_mem[16]).
Adding EN signal on $memory\u_graph_engine.x_mem[17]$9172 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.x_mem$wrmux[17][2][0]$y$9504, Q = \u_graph_engine.x_mem[17]).
Adding EN signal on $memory\u_graph_engine.x_mem[18]$9174 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.x_mem$wrmux[18][2][0]$y$9518, Q = \u_graph_engine.x_mem[18]).
Adding EN signal on $memory\u_graph_engine.x_mem[19]$9176 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.x_mem$wrmux[19][2][0]$y$9532, Q = \u_graph_engine.x_mem[19]).
Adding EN signal on $memory\u_graph_engine.x_mem[20]$9178 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.x_mem$wrmux[20][2][0]$y$9548, Q = \u_graph_engine.x_mem[20]).
Adding EN signal on $memory\u_graph_engine.x_mem[21]$9180 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.x_mem$wrmux[21][2][0]$y$9562, Q = \u_graph_engine.x_mem[21]).
Adding EN signal on $memory\u_graph_engine.x_mem[22]$9182 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.x_mem$wrmux[22][2][0]$y$9576, Q = \u_graph_engine.x_mem[22]).
Adding EN signal on $memory\u_graph_engine.x_mem[23]$9184 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.x_mem$wrmux[23][2][0]$y$9590, Q = \u_graph_engine.x_mem[23]).
Adding EN signal on $memory\u_graph_engine.x_mem[24]$9186 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.x_mem$wrmux[24][2][0]$y$9608, Q = \u_graph_engine.x_mem[24]).
Adding EN signal on $memory\u_graph_engine.x_mem[25]$9188 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.x_mem$wrmux[25][2][0]$y$9622, Q = \u_graph_engine.x_mem[25]).
Adding EN signal on $memory\u_graph_engine.x_mem[26]$9190 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.x_mem$wrmux[26][2][0]$y$9636, Q = \u_graph_engine.x_mem[26]).
Adding EN signal on $memory\u_graph_engine.x_mem[27]$9192 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.x_mem$wrmux[27][2][0]$y$9650, Q = \u_graph_engine.x_mem[27]).
Adding EN signal on $memory\u_graph_engine.x_mem[28]$9194 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.x_mem$wrmux[28][2][0]$y$9666, Q = \u_graph_engine.x_mem[28]).
Adding EN signal on $memory\u_graph_engine.x_mem[29]$9196 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.x_mem$wrmux[29][2][0]$y$9680, Q = \u_graph_engine.x_mem[29]).
Adding EN signal on $memory\u_graph_engine.x_mem[30]$9198 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.x_mem$wrmux[30][2][0]$y$9694, Q = \u_graph_engine.x_mem[30]).
Adding EN signal on $memory\u_graph_engine.x_mem[31]$9200 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.x_mem$wrmux[31][2][0]$y$9708, Q = \u_graph_engine.x_mem[31]).
Adding EN signal on $memory\u_graph_engine.w_mem[17]$9743 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.w_mem$wrmux[17][2][0]$y$9991, Q = \u_graph_engine.w_mem[17]).
Adding EN signal on $memory\u_graph_engine.w_mem[21]$9751 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.w_mem$wrmux[21][2][0]$y$10039, Q = \u_graph_engine.w_mem[21]).
Adding EN signal on $memory\u_graph_engine.w_mem[22]$9753 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.w_mem$wrmux[22][2][0]$y$10051, Q = \u_graph_engine.w_mem[22]).
Adding EN signal on $memory\u_graph_engine.w_mem[23]$9755 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.w_mem$wrmux[23][2][0]$y$10063, Q = \u_graph_engine.w_mem[23]).
Adding EN signal on $memory\u_graph_engine.w_mem[12]$9733 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.w_mem$wrmux[12][2][0]$y$9931, Q = \u_graph_engine.w_mem[12]).
Adding EN signal on $memory\u_graph_engine.w_mem[24]$9757 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.w_mem$wrmux[24][2][0]$y$10075, Q = \u_graph_engine.w_mem[24]).
Adding EN signal on $memory\u_graph_engine.w_mem[11]$9731 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.w_mem$wrmux[11][2][0]$y$9919, Q = \u_graph_engine.w_mem[11]).
Adding EN signal on $memory\u_graph_engine.w_mem[25]$9759 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.w_mem$wrmux[25][2][0]$y$10087, Q = \u_graph_engine.w_mem[25]).
Adding EN signal on $memory\u_graph_engine.w_mem[26]$9761 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.w_mem$wrmux[26][2][0]$y$10099, Q = \u_graph_engine.w_mem[26]).
Adding EN signal on $memory\u_graph_engine.w_mem[27]$9763 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.w_mem$wrmux[27][2][0]$y$10111, Q = \u_graph_engine.w_mem[27]).
Adding EN signal on $memory\u_graph_engine.w_mem[10]$9729 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.w_mem$wrmux[10][2][0]$y$9907, Q = \u_graph_engine.w_mem[10]).
Adding EN signal on $memory\u_graph_engine.w_mem[28]$9765 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.w_mem$wrmux[28][2][0]$y$10123, Q = \u_graph_engine.w_mem[28]).
Adding EN signal on $memory\u_graph_engine.w_mem[29]$9767 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.w_mem$wrmux[29][2][0]$y$10135, Q = \u_graph_engine.w_mem[29]).
Adding EN signal on $memory\u_graph_engine.w_mem[30]$9769 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.w_mem$wrmux[30][2][0]$y$10147, Q = \u_graph_engine.w_mem[30]).
Adding EN signal on $memory\u_graph_engine.w_mem[31]$9771 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.w_mem$wrmux[31][2][0]$y$10159, Q = \u_graph_engine.w_mem[31]).
Adding EN signal on $memory\u_graph_engine.w_mem[18]$9745 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.w_mem$wrmux[18][2][0]$y$10003, Q = \u_graph_engine.w_mem[18]).
Adding EN signal on $memory\u_graph_engine.w_mem[0]$9709 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.w_mem$wrmux[0][2][0]$y$9787, Q = \u_graph_engine.w_mem[0]).
Adding EN signal on $memory\u_graph_engine.w_mem[1]$9711 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.w_mem$wrmux[1][2][0]$y$9799, Q = \u_graph_engine.w_mem[1]).
Adding EN signal on $memory\u_graph_engine.w_mem[2]$9713 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.w_mem$wrmux[2][2][0]$y$9811, Q = \u_graph_engine.w_mem[2]).
Adding EN signal on $memory\u_graph_engine.w_mem[3]$9715 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.w_mem$wrmux[3][2][0]$y$9823, Q = \u_graph_engine.w_mem[3]).
Adding EN signal on $memory\u_graph_engine.w_mem[4]$9717 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.w_mem$wrmux[4][2][0]$y$9835, Q = \u_graph_engine.w_mem[4]).
Adding EN signal on $memory\u_graph_engine.w_mem[5]$9719 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.w_mem$wrmux[5][2][0]$y$9847, Q = \u_graph_engine.w_mem[5]).
Adding EN signal on $memory\u_graph_engine.w_mem[6]$9721 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.w_mem$wrmux[6][2][0]$y$9859, Q = \u_graph_engine.w_mem[6]).
Adding EN signal on $memory\u_graph_engine.w_mem[7]$9723 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.w_mem$wrmux[7][2][0]$y$9871, Q = \u_graph_engine.w_mem[7]).
Adding EN signal on $memory\u_graph_engine.w_mem[8]$9725 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.w_mem$wrmux[8][2][0]$y$9883, Q = \u_graph_engine.w_mem[8]).
Adding EN signal on $memory\u_graph_engine.w_mem[9]$9727 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.w_mem$wrmux[9][2][0]$y$9895, Q = \u_graph_engine.w_mem[9]).
Setting constant 0-bit at position 0 on $auto$ff.cc:337:slice$7016 ($sdffe) from module spi_neuron_top.
17.32.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \spi_neuron_top..
Removed 73 unused cells and 82 unused wires.
<suppressed ~74 debug messages>
17.32.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module spi_neuron_top.
<suppressed ~128 debug messages>
17.32.16. Rerunning OPT passes. (Maybe there is more to do..)
17.32.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \spi_neuron_top..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~450 debug messages>
17.32.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Optimizing cells in module \spi_neuron_top.
Performed a total of 0 changes.
17.32.19. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\spi_neuron_top'.
Computing hashes of 1635 cells of `\spi_neuron_top'.
Finding duplicate cells in `\spi_neuron_top'.
Computing hashes of 1603 cells of `\spi_neuron_top'.
Finding duplicate cells in `\spi_neuron_top'.
<suppressed ~96 debug messages>
Removed a total of 32 cells.
17.32.20. Executing OPT_DFF pass (perform DFF optimizations).
Adding SRST signal on $auto$ff.cc:337:slice$10451 ($dffe) from module spi_neuron_top (D = \u_graph_engine.weight_acc, Q = \u_graph_engine.w_mem[4], rval = 8'00000000).
Adding SRST signal on $auto$ff.cc:337:slice$10454 ($dffe) from module spi_neuron_top (D = \u_graph_engine.weight_acc, Q = \u_graph_engine.w_mem[5], rval = 8'00000000).
Adding SRST signal on $auto$ff.cc:337:slice$10457 ($dffe) from module spi_neuron_top (D = \u_graph_engine.weight_acc, Q = \u_graph_engine.w_mem[6], rval = 8'00000000).
Adding SRST signal on $auto$ff.cc:337:slice$10211 ($dffe) from module spi_neuron_top (D = \u_graph_engine.weight_acc, Q = \u_graph_engine.w_mem[19], rval = 8'00000000).
Adding SRST signal on $auto$ff.cc:337:slice$10460 ($dffe) from module spi_neuron_top (D = \u_graph_engine.weight_acc, Q = \u_graph_engine.w_mem[7], rval = 8'00000000).
Adding SRST signal on $auto$ff.cc:337:slice$10246 ($dffe) from module spi_neuron_top (D = \u_graph_engine.weight_acc, Q = \u_graph_engine.w_mem[15], rval = 8'00000000).
Adding SRST signal on $auto$ff.cc:337:slice$10249 ($dffe) from module spi_neuron_top (D = \u_graph_engine.weight_acc, Q = \u_graph_engine.w_mem[14], rval = 8'00000000).
Adding SRST signal on $auto$ff.cc:337:slice$10463 ($dffe) from module spi_neuron_top (D = \u_graph_engine.weight_acc, Q = \u_graph_engine.w_mem[8], rval = 8'00000000).
Adding SRST signal on $auto$ff.cc:337:slice$10466 ($dffe) from module spi_neuron_top (D = \u_graph_engine.weight_acc, Q = \u_graph_engine.w_mem[9], rval = 8'00000000).
Adding SRST signal on $auto$ff.cc:337:slice$10252 ($dffe) from module spi_neuron_top (D = \u_graph_engine.weight_acc, Q = \u_graph_engine.w_mem[13], rval = 8'00000000).
Adding SRST signal on $auto$ff.cc:337:slice$10287 ($dffe) from module spi_neuron_top (D = \u_graph_engine.weight_acc, Q = \u_graph_engine.w_mem[16], rval = 8'00000000).
Adding SRST signal on $auto$ff.cc:337:slice$10292 ($dffe) from module spi_neuron_top (D = \u_graph_engine.weight_acc, Q = \u_graph_engine.w_mem[20], rval = 8'00000000).
Adding SRST signal on $auto$ff.cc:337:slice$10295 ($dffe) from module spi_neuron_top (D = \u_graph_engine.u_act_buffer.rd_data, Q = \u_graph_engine.x_mem[0], rval = 8'00000000).
Adding SRST signal on $auto$ff.cc:337:slice$10298 ($dffe) from module spi_neuron_top (D = \u_graph_engine.u_act_buffer.rd_data, Q = \u_graph_engine.x_mem[1], rval = 8'00000000).
Adding SRST signal on $auto$ff.cc:337:slice$10301 ($dffe) from module spi_neuron_top (D = \u_graph_engine.u_act_buffer.rd_data, Q = \u_graph_engine.x_mem[2], rval = 8'00000000).
Adding SRST signal on $auto$ff.cc:337:slice$10304 ($dffe) from module spi_neuron_top (D = \u_graph_engine.u_act_buffer.rd_data, Q = \u_graph_engine.x_mem[3], rval = 8'00000000).
Adding SRST signal on $auto$ff.cc:337:slice$10307 ($dffe) from module spi_neuron_top (D = \u_graph_engine.u_act_buffer.rd_data, Q = \u_graph_engine.x_mem[4], rval = 8'00000000).
Adding SRST signal on $auto$ff.cc:337:slice$10310 ($dffe) from module spi_neuron_top (D = \u_graph_engine.u_act_buffer.rd_data, Q = \u_graph_engine.x_mem[5], rval = 8'00000000).
Adding SRST signal on $auto$ff.cc:337:slice$10313 ($dffe) from module spi_neuron_top (D = \u_graph_engine.u_act_buffer.rd_data, Q = \u_graph_engine.x_mem[6], rval = 8'00000000).
Adding SRST signal on $auto$ff.cc:337:slice$10316 ($dffe) from module spi_neuron_top (D = \u_graph_engine.u_act_buffer.rd_data, Q = \u_graph_engine.x_mem[7], rval = 8'00000000).
Adding SRST signal on $auto$ff.cc:337:slice$10319 ($dffe) from module spi_neuron_top (D = \u_graph_engine.u_act_buffer.rd_data, Q = \u_graph_engine.x_mem[8], rval = 8'00000000).
Adding SRST signal on $auto$ff.cc:337:slice$10322 ($dffe) from module spi_neuron_top (D = \u_graph_engine.u_act_buffer.rd_data, Q = \u_graph_engine.x_mem[9], rval = 8'00000000).
Adding SRST signal on $auto$ff.cc:337:slice$10325 ($dffe) from module spi_neuron_top (D = \u_graph_engine.u_act_buffer.rd_data, Q = \u_graph_engine.x_mem[10], rval = 8'00000000).
Adding SRST signal on $auto$ff.cc:337:slice$10328 ($dffe) from module spi_neuron_top (D = \u_graph_engine.u_act_buffer.rd_data, Q = \u_graph_engine.x_mem[11], rval = 8'00000000).
Adding SRST signal on $auto$ff.cc:337:slice$10331 ($dffe) from module spi_neuron_top (D = \u_graph_engine.u_act_buffer.rd_data, Q = \u_graph_engine.x_mem[12], rval = 8'00000000).
Adding SRST signal on $auto$ff.cc:337:slice$10334 ($dffe) from module spi_neuron_top (D = \u_graph_engine.u_act_buffer.rd_data, Q = \u_graph_engine.x_mem[13], rval = 8'00000000).
Adding SRST signal on $auto$ff.cc:337:slice$10337 ($dffe) from module spi_neuron_top (D = \u_graph_engine.u_act_buffer.rd_data, Q = \u_graph_engine.x_mem[14], rval = 8'00000000).
Adding SRST signal on $auto$ff.cc:337:slice$10340 ($dffe) from module spi_neuron_top (D = \u_graph_engine.u_act_buffer.rd_data, Q = \u_graph_engine.x_mem[15], rval = 8'00000000).
Adding SRST signal on $auto$ff.cc:337:slice$10343 ($dffe) from module spi_neuron_top (D = \u_graph_engine.u_act_buffer.rd_data, Q = \u_graph_engine.x_mem[16], rval = 8'00000000).
Adding SRST signal on $auto$ff.cc:337:slice$10346 ($dffe) from module spi_neuron_top (D = \u_graph_engine.u_act_buffer.rd_data, Q = \u_graph_engine.x_mem[17], rval = 8'00000000).
Adding SRST signal on $auto$ff.cc:337:slice$10349 ($dffe) from module spi_neuron_top (D = \u_graph_engine.u_act_buffer.rd_data, Q = \u_graph_engine.x_mem[18], rval = 8'00000000).
Adding SRST signal on $auto$ff.cc:337:slice$10352 ($dffe) from module spi_neuron_top (D = \u_graph_engine.u_act_buffer.rd_data, Q = \u_graph_engine.x_mem[19], rval = 8'00000000).
Adding SRST signal on $auto$ff.cc:337:slice$10355 ($dffe) from module spi_neuron_top (D = \u_graph_engine.u_act_buffer.rd_data, Q = \u_graph_engine.x_mem[20], rval = 8'00000000).
Adding SRST signal on $auto$ff.cc:337:slice$10358 ($dffe) from module spi_neuron_top (D = \u_graph_engine.u_act_buffer.rd_data, Q = \u_graph_engine.x_mem[21], rval = 8'00000000).
Adding SRST signal on $auto$ff.cc:337:slice$10361 ($dffe) from module spi_neuron_top (D = \u_graph_engine.u_act_buffer.rd_data, Q = \u_graph_engine.x_mem[22], rval = 8'00000000).
Adding SRST signal on $auto$ff.cc:337:slice$10364 ($dffe) from module spi_neuron_top (D = \u_graph_engine.u_act_buffer.rd_data, Q = \u_graph_engine.x_mem[23], rval = 8'00000000).
Adding SRST signal on $auto$ff.cc:337:slice$10367 ($dffe) from module spi_neuron_top (D = \u_graph_engine.u_act_buffer.rd_data, Q = \u_graph_engine.x_mem[24], rval = 8'00000000).
Adding SRST signal on $auto$ff.cc:337:slice$10370 ($dffe) from module spi_neuron_top (D = \u_graph_engine.u_act_buffer.rd_data, Q = \u_graph_engine.x_mem[25], rval = 8'00000000).
Adding SRST signal on $auto$ff.cc:337:slice$10373 ($dffe) from module spi_neuron_top (D = \u_graph_engine.u_act_buffer.rd_data, Q = \u_graph_engine.x_mem[26], rval = 8'00000000).
Adding SRST signal on $auto$ff.cc:337:slice$10376 ($dffe) from module spi_neuron_top (D = \u_graph_engine.u_act_buffer.rd_data, Q = \u_graph_engine.x_mem[27], rval = 8'00000000).
Adding SRST signal on $auto$ff.cc:337:slice$10379 ($dffe) from module spi_neuron_top (D = \u_graph_engine.u_act_buffer.rd_data, Q = \u_graph_engine.x_mem[28], rval = 8'00000000).
Adding SRST signal on $auto$ff.cc:337:slice$10382 ($dffe) from module spi_neuron_top (D = \u_graph_engine.u_act_buffer.rd_data, Q = \u_graph_engine.x_mem[29], rval = 8'00000000).
Adding SRST signal on $auto$ff.cc:337:slice$10385 ($dffe) from module spi_neuron_top (D = \u_graph_engine.u_act_buffer.rd_data, Q = \u_graph_engine.x_mem[30], rval = 8'00000000).
Adding SRST signal on $auto$ff.cc:337:slice$10388 ($dffe) from module spi_neuron_top (D = \u_graph_engine.u_act_buffer.rd_data, Q = \u_graph_engine.x_mem[31], rval = 8'00000000).
Adding SRST signal on $auto$ff.cc:337:slice$10391 ($dffe) from module spi_neuron_top (D = \u_graph_engine.weight_acc, Q = \u_graph_engine.w_mem[17], rval = 8'00000000).
Adding SRST signal on $auto$ff.cc:337:slice$10394 ($dffe) from module spi_neuron_top (D = \u_graph_engine.weight_acc, Q = \u_graph_engine.w_mem[21], rval = 8'00000000).
Adding SRST signal on $auto$ff.cc:337:slice$10397 ($dffe) from module spi_neuron_top (D = \u_graph_engine.weight_acc, Q = \u_graph_engine.w_mem[22], rval = 8'00000000).
Adding SRST signal on $auto$ff.cc:337:slice$10400 ($dffe) from module spi_neuron_top (D = \u_graph_engine.weight_acc, Q = \u_graph_engine.w_mem[23], rval = 8'00000000).
Adding SRST signal on $auto$ff.cc:337:slice$10403 ($dffe) from module spi_neuron_top (D = \u_graph_engine.weight_acc, Q = \u_graph_engine.w_mem[12], rval = 8'00000000).
Adding SRST signal on $auto$ff.cc:337:slice$10406 ($dffe) from module spi_neuron_top (D = \u_graph_engine.weight_acc, Q = \u_graph_engine.w_mem[24], rval = 8'00000000).
Adding SRST signal on $auto$ff.cc:337:slice$10409 ($dffe) from module spi_neuron_top (D = \u_graph_engine.weight_acc, Q = \u_graph_engine.w_mem[11], rval = 8'00000000).
Adding SRST signal on $auto$ff.cc:337:slice$10412 ($dffe) from module spi_neuron_top (D = \u_graph_engine.weight_acc, Q = \u_graph_engine.w_mem[25], rval = 8'00000000).
Adding SRST signal on $auto$ff.cc:337:slice$10415 ($dffe) from module spi_neuron_top (D = \u_graph_engine.weight_acc, Q = \u_graph_engine.w_mem[26], rval = 8'00000000).
Adding SRST signal on $auto$ff.cc:337:slice$10418 ($dffe) from module spi_neuron_top (D = \u_graph_engine.weight_acc, Q = \u_graph_engine.w_mem[27], rval = 8'00000000).
Adding SRST signal on $auto$ff.cc:337:slice$10421 ($dffe) from module spi_neuron_top (D = \u_graph_engine.weight_acc, Q = \u_graph_engine.w_mem[10], rval = 8'00000000).
Adding SRST signal on $auto$ff.cc:337:slice$10424 ($dffe) from module spi_neuron_top (D = \u_graph_engine.weight_acc, Q = \u_graph_engine.w_mem[28], rval = 8'00000000).
Adding SRST signal on $auto$ff.cc:337:slice$10427 ($dffe) from module spi_neuron_top (D = \u_graph_engine.weight_acc, Q = \u_graph_engine.w_mem[29], rval = 8'00000000).
Adding SRST signal on $auto$ff.cc:337:slice$10430 ($dffe) from module spi_neuron_top (D = \u_graph_engine.weight_acc, Q = \u_graph_engine.w_mem[30], rval = 8'00000000).
Adding SRST signal on $auto$ff.cc:337:slice$10433 ($dffe) from module spi_neuron_top (D = \u_graph_engine.weight_acc, Q = \u_graph_engine.w_mem[31], rval = 8'00000000).
Adding SRST signal on $auto$ff.cc:337:slice$10436 ($dffe) from module spi_neuron_top (D = \u_graph_engine.weight_acc, Q = \u_graph_engine.w_mem[18], rval = 8'00000000).
Adding SRST signal on $auto$ff.cc:337:slice$10439 ($dffe) from module spi_neuron_top (D = \u_graph_engine.weight_acc, Q = \u_graph_engine.w_mem[0], rval = 8'00000000).
Adding SRST signal on $auto$ff.cc:337:slice$10442 ($dffe) from module spi_neuron_top (D = \u_graph_engine.weight_acc, Q = \u_graph_engine.w_mem[1], rval = 8'00000000).
Adding SRST signal on $auto$ff.cc:337:slice$10445 ($dffe) from module spi_neuron_top (D = \u_graph_engine.weight_acc, Q = \u_graph_engine.w_mem[2], rval = 8'00000000).
Adding SRST signal on $auto$ff.cc:337:slice$10448 ($dffe) from module spi_neuron_top (D = \u_graph_engine.weight_acc, Q = \u_graph_engine.w_mem[3], rval = 8'00000000).
Setting constant 0-bit at position 0 on $auto$ff.cc:337:slice$6982 ($sdffe) from module spi_neuron_top.
17.32.21. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \spi_neuron_top..
Removed 64 unused cells and 160 unused wires.
<suppressed ~65 debug messages>
17.32.22. Executing OPT_EXPR pass (perform const folding).
Optimizing module spi_neuron_top.
17.32.23. Rerunning OPT passes. (Maybe there is more to do..)
17.32.24. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \spi_neuron_top..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~290 debug messages>
17.32.25. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Optimizing cells in module \spi_neuron_top.
Performed a total of 0 changes.
17.32.26. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\spi_neuron_top'.
Computing hashes of 1538 cells of `\spi_neuron_top'.
Finding duplicate cells in `\spi_neuron_top'.
Removed a total of 0 cells.
17.32.27. Executing OPT_DFF pass (perform DFF optimizations).
17.32.28. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \spi_neuron_top..
17.32.29. Executing OPT_EXPR pass (perform const folding).
Optimizing module spi_neuron_top.
17.32.30. Finished fast OPT passes. (There is nothing left to do.)
17.33. Executing TECHMAP pass (map to technology primitives).
17.33.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/techmap.v
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/techmap.v' to AST representation.
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
Generating RTLIL representation for module `\_90_simplemap_various'.
Generating RTLIL representation for module `\_90_simplemap_registers'.
Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
Generating RTLIL representation for module `\_90_shift_shiftx'.
Generating RTLIL representation for module `\_90_fa'.
Generating RTLIL representation for module `\_90_lcu_brent_kung'.
Generating RTLIL representation for module `\_90_alu'.
Generating RTLIL representation for module `\_90_macc'.
Generating RTLIL representation for module `\_90_alumacc'.
Generating RTLIL representation for module `$__div_mod_u'.
Generating RTLIL representation for module `$__div_mod_trunc'.
Generating RTLIL representation for module `\_90_div'.
Generating RTLIL representation for module `\_90_mod'.
Generating RTLIL representation for module `$__div_mod_floor'.
Generating RTLIL representation for module `\_90_divfloor'.
Generating RTLIL representation for module `\_90_modfloor'.
Generating RTLIL representation for module `\_90_pow'.
Generating RTLIL representation for module `\_90_demux'.
Generating RTLIL representation for module `\_90_lut'.
Generating RTLIL representation for module `$connect'.
Generating RTLIL representation for module `$input_port'.
Successfully finished Verilog frontend.
17.33.2. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v' to AST representation.
Generating RTLIL representation for module `\_80_ccu2c_alu'.
Successfully finished Verilog frontend.
17.33.3. Continuing TECHMAP pass.
Using extmapper simplemap for cells of type $sdffce.
Using extmapper simplemap for cells of type $reduce_bool.
Using extmapper simplemap for cells of type $dffe.
Using extmapper simplemap for cells of type $reduce_or.
Using extmapper simplemap for cells of type $dff.
Using extmapper simplemap for cells of type $not.
Using extmapper simplemap for cells of type $sdff.
Using extmapper simplemap for cells of type $reduce_and.
Using extmapper simplemap for cells of type $ne.
Using extmapper simplemap for cells of type $sdffe.
Using extmapper simplemap for cells of type $and.
Using template $paramod$78e969f2586efcf3a5b0b0440bcca0db83d5cca2\_90_alu for cells of type $alu.
Using template $paramod$fc972a7a46956c1788f3cb5257b53c8f1df2d0cc\_90_alu for cells of type $alu.
Using extmapper simplemap for cells of type $mux.
Using extmapper simplemap for cells of type $eq.
Using template $paramod$175e67c02b86e96b1288b9dc100122520d7240d8\_90_alu for cells of type $alu.
Using template $paramod$ba698a254f9a5947e85cbe7beae6b161eefc5386\_90_alu for cells of type $alu.
Using template $paramod$8fdcfe020be5e507ba05385ffd706e02b549d39d\_80_ccu2c_alu for cells of type $alu.
Using template $paramod$2470b7ea32c975a55c3ab8b283381b72d09e16d3\_80_ccu2c_alu for cells of type $alu.
Using template $paramod$2af30114e9bd4ccb04dad757b3f0a8f6bf0615b0\_80_ccu2c_alu for cells of type $alu.
Using extmapper simplemap for cells of type $or.
Using template $paramod$6df0329addda9228fcc2546de2aaf14ad26c98e1\_80_ccu2c_alu for cells of type $alu.
Using template $paramod$7945baf943a7eaf2bd95deee6e66976c53d43b8d\_80_ccu2c_alu for cells of type $alu.
Using template $paramod$36fdbc18fab0758c8553dda57bd33e3f8f3e8765\_80_ccu2c_alu for cells of type $alu.
Using template $paramod$7bdc7d89ea9376c9c454fd05d9b64ca6288b61c9\_80_ccu2c_alu for cells of type $alu.
Using template $paramod$bb2d74554e7f3344a65c51a9d0fb34626611aac9\_80_ccu2c_alu for cells of type $alu.
Using template $paramod$713617589782cfade849bb573b5c36106c4b708f\_80_ccu2c_alu for cells of type $alu.
Using template $paramod$32efbfac1c4dc57230cf86180788fdfd12e3b511\_80_ccu2c_alu for cells of type $alu.
Using template $paramod$a04dd9d4d8b430140c4ff94b50470fb380fda2a0\_80_ccu2c_alu for cells of type $alu.
Using template $paramod$a1665ef28c749ebcdbe9aecd466e644647b56463\_80_ccu2c_alu for cells of type $alu.
Using template $paramod$8742280fdebca84e1c87f2a86ed84f62d558f4cc\_90_alu for cells of type $alu.
Using template $paramod$32a7b7b86c07519b7537abc18e96f0331f97914d\_90_alu for cells of type $alu.
Using template $paramod$c3cd1564c35d873179656addd6052d7ea8b6d991\_80_ccu2c_alu for cells of type $alu.
Using template $paramod$a460ba4831a5c553df03ee15bf45a690343e194f\_80_ccu2c_alu for cells of type $alu.
Using template $paramod$3ef7d3dd227da7627a99c5e5a6a4deb817573e39\_90_alu for cells of type $alu.
Using template $paramod$403a3c2fa431a154c52a6a5429d7a6260b5d144f\_80_ccu2c_alu for cells of type $alu.
Using extmapper simplemap for cells of type $xor.
Using template $paramod$5d0bb5be5579f553e9e7790fdead1e778acc7812\_80_ccu2c_alu for cells of type $alu.
Using template $paramod$6694d39cad831bc5688fe7ffaed39b79bdf33392\_80_ccu2c_alu for cells of type $alu.
Using extmapper maccmap for cells of type $macc_v2.
add \u_neuron_memory.u_neuron.acc (32 bits, signed)
add \u_neuron_memory.u_neuron.u_mac8.tree[8] [16:0] (17 bits, signed)
add \u_neuron_memory.u_neuron.u_mac8.tree[10] [16:0] (17 bits, signed)
add \u_neuron_memory.u_neuron.u_mac8.tree[9] [16:0] (17 bits, signed)
add \u_neuron_memory.u_neuron.u_mac8.tree[11] [16:0] (17 bits, signed)
add \u_graph_engine.u_neuron.acc (32 bits, signed)
add \u_graph_engine.u_neuron.u_mac8.tree[8] [16:0] (17 bits, signed)
add \u_graph_engine.u_neuron.u_mac8.tree[10] [16:0] (17 bits, signed)
add \u_graph_engine.u_neuron.u_mac8.tree[9] [16:0] (17 bits, signed)
add \u_graph_engine.u_neuron.u_mac8.tree[11] [16:0] (17 bits, signed)
add \u_graph_engine.conn_ptr_acc [22:0] (23 bits, unsigned)
add \u_graph_engine.edge_byte_idx (2 bits, unsigned)
add { \u_graph_engine.conn_i 2'00 } (8 bits, unsigned)
Using extmapper simplemap for cells of type $bmux.
Using extmapper simplemap for cells of type $logic_not.
Using extmapper simplemap for cells of type $pmux.
Using extmapper simplemap for cells of type $tribuf.
Using extmapper simplemap for cells of type $logic_and.
Using extmapper simplemap for cells of type $logic_or.
Using template $paramod$constmap:1c62fa0501c71c523e718f52047352464d16f12e$paramod$a50ae57e8afac966c737391c51ad88342606b747\_90_shift_shiftx for cells of type $shiftx.
Using extmapper simplemap for cells of type $lut.
Using template $paramod$448756c9a9dfaa49080ce4b90c6cc182883e181f\_80_ccu2c_alu for cells of type $alu.
Using template $paramod\_90_fa\WIDTH=32'00000000000000000000000000100000 for cells of type $fa.
Using template $paramod$fbc7873bff55778c0b3173955b7e4bce1d9d6834\_80_ccu2c_alu for cells of type $alu.
Using template $paramod\_90_fa\WIDTH=32'00000000000000000000000000000011 for cells of type $fa.
Using template $paramod\_90_lcu_brent_kung\WIDTH=32'00000000000000000000000000000011 for cells of type $lcu.
Using extmapper simplemap for cells of type $pos.
Using template $paramod\_90_fa\WIDTH=32'00000000000000000000000000000001 for cells of type $fa.
Using template $paramod\_90_lcu_brent_kung\WIDTH=32'00000000000000000000000000000001 for cells of type $lcu.
Using template $paramod\_90_fa\WIDTH=32'00000000000000000000000000000010 for cells of type $fa.
Using template $paramod\_90_lcu_brent_kung\WIDTH=32'00000000000000000000000000000010 for cells of type $lcu.
Using template $paramod\_90_fa\WIDTH=32'00000000000000000000000000000100 for cells of type $fa.
Using template $paramod\_90_lcu_brent_kung\WIDTH=32'00000000000000000000000000000100 for cells of type $lcu.
No more expansions possible.
<suppressed ~5278 debug messages>
17.34. Executing OPT pass (performing simple optimizations).
17.34.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module spi_neuron_top.
<suppressed ~3844 debug messages>
17.34.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\spi_neuron_top'.
Computing hashes of 10726 cells of `\spi_neuron_top'.
Finding duplicate cells in `\spi_neuron_top'.
Computing hashes of 10224 cells of `\spi_neuron_top'.
Finding duplicate cells in `\spi_neuron_top'.
Computing hashes of 10101 cells of `\spi_neuron_top'.
Finding duplicate cells in `\spi_neuron_top'.
Computing hashes of 10077 cells of `\spi_neuron_top'.
Finding duplicate cells in `\spi_neuron_top'.
Computing hashes of 10071 cells of `\spi_neuron_top'.
Finding duplicate cells in `\spi_neuron_top'.
Computing hashes of 10069 cells of `\spi_neuron_top'.
Finding duplicate cells in `\spi_neuron_top'.
<suppressed ~1971 debug messages>
Removed a total of 657 cells.
17.34.3. Executing OPT_DFF pass (perform DFF optimizations).
Adding SRST signal on $auto$ff.cc:337:slice$16176 ($_SDFF_PP0_) from module spi_neuron_top (D = $auto$simplemap.cc:189:logic_reduce$17965, Q = \u_psram_ctrl.dq_oe, rval = 1'0).
Adding SRST signal on $auto$ff.cc:337:slice$16126 ($_SDFF_PP1_) from module spi_neuron_top (D = $auto$simplemap.cc:189:logic_reduce$17955, Q = \u_psram_ctrl.psram_ub_n, rval = 1'1).
Adding SRST signal on $auto$ff.cc:337:slice$16125 ($_SDFF_PP1_) from module spi_neuron_top (D = $auto$simplemap.cc:189:logic_reduce$17938, Q = \u_psram_ctrl.psram_lb_n, rval = 1'1).
Adding SRST signal on $auto$ff.cc:337:slice$16124 ($_SDFF_PP1_) from module spi_neuron_top (D = $auto$simplemap.cc:189:logic_reduce$17921, Q = \u_psram_ctrl.psram_we_n, rval = 1'1).
Adding SRST signal on $auto$ff.cc:337:slice$16123 ($_SDFF_PP1_) from module spi_neuron_top (D = $auto$simplemap.cc:189:logic_reduce$17910, Q = \u_psram_ctrl.psram_oe_n, rval = 1'1).
Adding SRST signal on $auto$ff.cc:337:slice$16122 ($_SDFF_PP1_) from module spi_neuron_top (D = $auto$simplemap.cc:189:logic_reduce$17900, Q = \u_psram_ctrl.psram_ce_n, rval = 1'1).
Adding SRST signal on $auto$ff.cc:337:slice$16119 ($_SDFF_PP0_) from module spi_neuron_top (D = $auto$simplemap.cc:189:logic_reduce$17884, Q = \u_psram_ctrl.mem_ready, rval = 1'0).
Adding SRST signal on $auto$ff.cc:337:slice$15012 ($_SDFF_PP0_) from module spi_neuron_top (D = $auto$simplemap.cc:189:logic_reduce$18665, Q = \u_neuron_memory.access_req, rval = 1'0).
Adding SRST signal on $auto$ff.cc:337:slice$14602 ($_SDFF_PP0_) from module spi_neuron_top (D = $auto$simplemap.cc:189:logic_reduce$19264, Q = \u_graph_engine.act_wr_en, rval = 1'0).
Adding SRST signal on $auto$ff.cc:337:slice$14351 ($_SDFF_PP0_) from module spi_neuron_top (D = $auto$simplemap.cc:189:logic_reduce$19254, Q = \u_graph_engine.done, rval = 1'0).
Adding SRST signal on $auto$ff.cc:337:slice$14272 ($_SDFF_PP0_) from module spi_neuron_top (D = $auto$simplemap.cc:189:logic_reduce$19274, Q = \u_graph_engine.ram_req, rval = 1'0).
Adding SRST signal on $auto$ff.cc:337:slice$11717 ($_DFF_P_) from module spi_neuron_top (D = $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1540$rdmux[0][0][0]$a$8580 [1], Q = $flatten\u_spi_engine.$4\tx_byte_comb[7:0] [2], rval = 1'0).
17.34.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \spi_neuron_top..
Removed 2056 unused cells and 4658 unused wires.
<suppressed ~2057 debug messages>
17.34.5. Rerunning OPT passes. (Removed registers in this run.)
17.34.6. Executing OPT_EXPR pass (perform const folding).
Optimizing module spi_neuron_top.
<suppressed ~1 debug messages>
17.34.7. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\spi_neuron_top'.
Computing hashes of 8034 cells of `\spi_neuron_top'.
Finding duplicate cells in `\spi_neuron_top'.
Computing hashes of 8030 cells of `\spi_neuron_top'.
Finding duplicate cells in `\spi_neuron_top'.
Computing hashes of 8027 cells of `\spi_neuron_top'.
Finding duplicate cells in `\spi_neuron_top'.
<suppressed ~21 debug messages>
Removed a total of 7 cells.
17.34.8. Executing OPT_DFF pass (perform DFF optimizations).
17.34.9. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \spi_neuron_top..
Removed 0 unused cells and 7 unused wires.
<suppressed ~1 debug messages>
17.34.10. Finished fast OPT passes.
17.35. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \spi_neuron_top..
17.36. Executing DFFLEGALIZE pass (convert FFs to types supported by the target).
17.37. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\spi_neuron_top'.
Computing hashes of 9067 cells of `\spi_neuron_top'.
Finding duplicate cells in `\spi_neuron_top'.
Computing hashes of 8580 cells of `\spi_neuron_top'.
Finding duplicate cells in `\spi_neuron_top'.
Computing hashes of 8093 cells of `\spi_neuron_top'.
Finding duplicate cells in `\spi_neuron_top'.
<suppressed ~2922 debug messages>
Removed a total of 974 cells.
17.38. Executing TECHMAP pass (map to technology primitives).
17.38.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v' to AST representation.
Generating RTLIL representation for module `$_DFF_N_'.
Generating RTLIL representation for module `$_DFF_P_'.
Generating RTLIL representation for module `$_DFFE_NN_'.
Generating RTLIL representation for module `$_DFFE_PN_'.
Generating RTLIL representation for module `$_DFFE_NP_'.
Generating RTLIL representation for module `$_DFFE_PP_'.
Generating RTLIL representation for module `$_DFF_NP0_'.
Generating RTLIL representation for module `$_DFF_NP1_'.
Generating RTLIL representation for module `$_DFF_PP0_'.
Generating RTLIL representation for module `$_DFF_PP1_'.
Generating RTLIL representation for module `$_SDFF_NP0_'.
Generating RTLIL representation for module `$_SDFF_NP1_'.
Generating RTLIL representation for module `$_SDFF_PP0_'.
Generating RTLIL representation for module `$_SDFF_PP1_'.
Generating RTLIL representation for module `$_DFFE_NP0P_'.
Generating RTLIL representation for module `$_DFFE_NP1P_'.
Generating RTLIL representation for module `$_DFFE_PP0P_'.
Generating RTLIL representation for module `$_DFFE_PP1P_'.
Generating RTLIL representation for module `$_DFFE_NP0N_'.
Generating RTLIL representation for module `$_DFFE_NP1N_'.
Generating RTLIL representation for module `$_DFFE_PP0N_'.
Generating RTLIL representation for module `$_DFFE_PP1N_'.
Generating RTLIL representation for module `$_SDFFE_NP0P_'.
Generating RTLIL representation for module `$_SDFFE_NP1P_'.
Generating RTLIL representation for module `$_SDFFE_PP0P_'.
Generating RTLIL representation for module `$_SDFFE_PP1P_'.
Generating RTLIL representation for module `$_SDFFE_NP0N_'.
Generating RTLIL representation for module `$_SDFFE_NP1N_'.
Generating RTLIL representation for module `$_SDFFE_PP0N_'.
Generating RTLIL representation for module `$_SDFFE_PP1N_'.
Generating RTLIL representation for module `$_ALDFF_NP_'.
Generating RTLIL representation for module `$_ALDFF_PP_'.
Generating RTLIL representation for module `$_ALDFFE_NPN_'.
Generating RTLIL representation for module `$_ALDFFE_NPP_'.
Generating RTLIL representation for module `$_ALDFFE_PPN_'.
Generating RTLIL representation for module `$_ALDFFE_PPP_'.
Generating RTLIL representation for module `\FD1P3AX'.
Generating RTLIL representation for module `\FD1P3AY'.
Generating RTLIL representation for module `\FD1P3BX'.
Generating RTLIL representation for module `\FD1P3DX'.
Generating RTLIL representation for module `\FD1P3IX'.
Generating RTLIL representation for module `\FD1P3JX'.
Generating RTLIL representation for module `\FD1S3AX'.
Generating RTLIL representation for module `\FD1S3AY'.
Generating RTLIL representation for module `\FD1S3BX'.
Generating RTLIL representation for module `\FD1S3DX'.
Generating RTLIL representation for module `\FD1S3IX'.
Generating RTLIL representation for module `\FD1S3JX'.
Generating RTLIL representation for module `\IFS1P3BX'.
Generating RTLIL representation for module `\IFS1P3DX'.
Generating RTLIL representation for module `\IFS1P3IX'.
Generating RTLIL representation for module `\IFS1P3JX'.
Generating RTLIL representation for module `\OFS1P3BX'.
Generating RTLIL representation for module `\OFS1P3DX'.
Generating RTLIL representation for module `\OFS1P3IX'.
Generating RTLIL representation for module `\OFS1P3JX'.
Generating RTLIL representation for module `\IB'.
Generating RTLIL representation for module `\IBPU'.
Generating RTLIL representation for module `\IBPD'.
Generating RTLIL representation for module `\OB'.
Generating RTLIL representation for module `\OBZ'.
Generating RTLIL representation for module `\OBZPU'.
Generating RTLIL representation for module `\OBZPD'.
Generating RTLIL representation for module `\OBCO'.
Generating RTLIL representation for module `\BB'.
Generating RTLIL representation for module `\BBPU'.
Generating RTLIL representation for module `\BBPD'.
Generating RTLIL representation for module `\ILVDS'.
Generating RTLIL representation for module `\OLVDS'.
Successfully finished Verilog frontend.
17.38.2. Continuing TECHMAP pass.
Using template $_SDFF_PP0_ for cells of type $_SDFF_PP0_.
Using template $_SDFF_PP1_ for cells of type $_SDFF_PP1_.
Using template $paramod$_DFF_P_\_TECHMAP_WIREINIT_Q_=1'x for cells of type $_DFF_P_.
Using template $_SDFFE_PP0P_ for cells of type $_SDFFE_PP0P_.
Using template $_SDFFE_PP1P_ for cells of type $_SDFFE_PP1P_.
Using template $paramod$_DFFE_PP_\_TECHMAP_WIREINIT_Q_=1'x for cells of type $_DFFE_PP_.
No more expansions possible.
<suppressed ~2492 debug messages>
17.39. Executing OPT_EXPR pass (perform const folding).
Optimizing module spi_neuron_top.
<suppressed ~18 debug messages>
17.40. Executing SIMPLEMAP pass (map simple cells to gate primitives).
17.41. Executing LATTICE_GSR pass (implement FF init values).
Handling GSR in spi_neuron_top.
17.42. Executing ATTRMVCP pass (move or copy attributes).
17.43. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \spi_neuron_top..
Removed 0 unused cells and 14627 unused wires.
<suppressed ~1 debug messages>
17.44. Executing CHECK pass (checking for obvious problems).
Checking module spi_neuron_top...
Found and reported 0 problems.
17.45. Executing TECHMAP pass (map to technology primitives).
17.45.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/latches_map.v
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/latches_map.v' to AST representation.
Generating RTLIL representation for module `$_DLATCH_N_'.
Generating RTLIL representation for module `$_DLATCH_P_'.
Successfully finished Verilog frontend.
17.45.2. Continuing TECHMAP pass.
No more expansions possible.
<suppressed ~4 debug messages>
17.46. Executing ABC9 pass.
17.46.1. Executing ABC9_OPS pass (helper functions for ABC9).
17.46.2. Executing ABC9_OPS pass (helper functions for ABC9).
17.46.3. Executing SCC pass (detecting logic loops).
Found 0 SCCs in module spi_neuron_top.
Found 0 SCCs.
17.46.4. Executing ABC9_OPS pass (helper functions for ABC9).
17.46.5. Executing TECHMAP pass (map to technology primitives).
17.46.5.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/techmap.v
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/techmap.v' to AST representation.
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
Generating RTLIL representation for module `\_90_simplemap_various'.
Generating RTLIL representation for module `\_90_simplemap_registers'.
Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
Generating RTLIL representation for module `\_90_shift_shiftx'.
Generating RTLIL representation for module `\_90_fa'.
Generating RTLIL representation for module `\_90_lcu_brent_kung'.
Generating RTLIL representation for module `\_90_alu'.
Generating RTLIL representation for module `\_90_macc'.
Generating RTLIL representation for module `\_90_alumacc'.
Generating RTLIL representation for module `$__div_mod_u'.
Generating RTLIL representation for module `$__div_mod_trunc'.
Generating RTLIL representation for module `\_90_div'.
Generating RTLIL representation for module `\_90_mod'.
Generating RTLIL representation for module `$__div_mod_floor'.
Generating RTLIL representation for module `\_90_divfloor'.
Generating RTLIL representation for module `\_90_modfloor'.
Generating RTLIL representation for module `\_90_pow'.
Generating RTLIL representation for module `\_90_demux'.
Generating RTLIL representation for module `\_90_lut'.
Generating RTLIL representation for module `$connect'.
Generating RTLIL representation for module `$input_port'.
Successfully finished Verilog frontend.
17.46.5.2. Continuing TECHMAP pass.
No more expansions possible.
<suppressed ~166 debug messages>
17.46.6. Executing OPT pass (performing simple optimizations).
17.46.6.1. Executing OPT_EXPR pass (perform const folding).
17.46.6.2. Executing OPT_MERGE pass (detect identical cells).
Removed a total of 0 cells.
17.46.6.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Removed 0 multiplexer ports.
17.46.6.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Performed a total of 0 changes.
17.46.6.5. Executing OPT_MERGE pass (detect identical cells).
Removed a total of 0 cells.
17.46.6.6. Executing OPT_DFF pass (perform DFF optimizations).
17.46.6.7. Executing OPT_CLEAN pass (remove unused cells and wires).
17.46.6.8. Executing OPT_EXPR pass (perform const folding).
17.46.6.9. Finished fast OPT passes. (There is nothing left to do.)
17.46.7. Executing TECHMAP pass (map to technology primitives).
17.46.7.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/abc9_map.v
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/abc9_map.v' to AST representation.
Successfully finished Verilog frontend.
17.46.7.2. Continuing TECHMAP pass.
No more expansions possible.
<suppressed ~2 debug messages>
17.46.8. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/abc9_model.v
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/abc9_model.v' to AST representation.
Generating RTLIL representation for module `$__ABC9_DELAY'.
Generating RTLIL representation for module `$__ABC9_SCC_BREAKER'.
Generating RTLIL representation for module `$__DFF_N__$abc9_flop'.
Generating RTLIL representation for module `$__DFF_P__$abc9_flop'.
Successfully finished Verilog frontend.
17.46.9. Executing ABC9_OPS pass (helper functions for ABC9).
<suppressed ~2 debug messages>
17.46.10. Executing ABC9_OPS pass (helper functions for ABC9).
17.46.11. Executing ABC9_OPS pass (helper functions for ABC9).
<suppressed ~2 debug messages>
17.46.12. Executing TECHMAP pass (map to technology primitives).
17.46.12.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/techmap.v
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/techmap.v' to AST representation.
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
Generating RTLIL representation for module `\_90_simplemap_various'.
Generating RTLIL representation for module `\_90_simplemap_registers'.
Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
Generating RTLIL representation for module `\_90_shift_shiftx'.
Generating RTLIL representation for module `\_90_fa'.
Generating RTLIL representation for module `\_90_lcu_brent_kung'.
Generating RTLIL representation for module `\_90_alu'.
Generating RTLIL representation for module `\_90_macc'.
Generating RTLIL representation for module `\_90_alumacc'.
Generating RTLIL representation for module `$__div_mod_u'.
Generating RTLIL representation for module `$__div_mod_trunc'.
Generating RTLIL representation for module `\_90_div'.
Generating RTLIL representation for module `\_90_mod'.
Generating RTLIL representation for module `$__div_mod_floor'.
Generating RTLIL representation for module `\_90_divfloor'.
Generating RTLIL representation for module `\_90_modfloor'.
Generating RTLIL representation for module `\_90_pow'.
Generating RTLIL representation for module `\_90_demux'.
Generating RTLIL representation for module `\_90_lut'.
Generating RTLIL representation for module `$connect'.
Generating RTLIL representation for module `$input_port'.
Successfully finished Verilog frontend.
17.46.12.2. Continuing TECHMAP pass.
Using template $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C for cells of type $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C.
Using extmapper simplemap for cells of type $or.
Using extmapper simplemap for cells of type $and.
Using extmapper simplemap for cells of type $not.
Using extmapper simplemap for cells of type $xor.
Using template $paramod\LUT2\INIT=4'1010 for cells of type LUT2.
Using template $paramod\LUT4\INIT=16'1001011010101010 for cells of type LUT4.
Using extmapper simplemap for cells of type $mux.
No more expansions possible.
<suppressed ~205 debug messages>
17.46.13. Executing OPT pass (performing simple optimizations).
17.46.13.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module spi_neuron_top.
<suppressed ~18 debug messages>
17.46.13.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\spi_neuron_top'.
Computing hashes of 59 cells of `\spi_neuron_top'.
Finding duplicate cells in `\spi_neuron_top'.
Computing hashes of 57 cells of `\spi_neuron_top'.
Finding duplicate cells in `\spi_neuron_top'.
<suppressed ~6 debug messages>
Removed a total of 2 cells.
17.46.13.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \spi_neuron_top..
Creating internal representation of mux trees.
No muxes found in this module.
Removed 0 multiplexer ports.
17.46.13.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Optimizing cells in module \spi_neuron_top.
Performed a total of 0 changes.
17.46.13.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\spi_neuron_top'.
Computing hashes of 57 cells of `\spi_neuron_top'.
Finding duplicate cells in `\spi_neuron_top'.
Removed a total of 0 cells.
17.46.13.6. Executing OPT_DFF pass (perform DFF optimizations).
17.46.13.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \spi_neuron_top..
Removed 0 unused cells and 55 unused wires.
<suppressed ~1 debug messages>
17.46.13.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module spi_neuron_top.
17.46.13.9. Rerunning OPT passes. (Maybe there is more to do..)
17.46.13.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \spi_neuron_top..
Creating internal representation of mux trees.
No muxes found in this module.
Removed 0 multiplexer ports.
17.46.13.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Optimizing cells in module \spi_neuron_top.
Performed a total of 0 changes.
17.46.13.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\spi_neuron_top'.
Computing hashes of 57 cells of `\spi_neuron_top'.
Finding duplicate cells in `\spi_neuron_top'.
Removed a total of 0 cells.
17.46.13.13. Executing OPT_DFF pass (perform DFF optimizations).
17.46.13.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \spi_neuron_top..
17.46.13.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module spi_neuron_top.
17.46.13.16. Finished fast OPT passes. (There is nothing left to do.)
17.46.14. Executing AIGMAP pass (map logic to AIG).
Module spi_neuron_top: replaced 18 cells with 120 new cells, skipped 39 cells.
replaced 3 cell types:
14 $_MUX_
2 $_OR_
2 $_XOR_
not replaced 3 cell types:
4 $_AND_
4 $_NOT_
31 $specify2
17.46.15. Executing AIGMAP pass (map logic to AIG).
Module spi_neuron_top: replaced 3345 cells with 20181 new cells, skipped 4732 cells.
replaced 4 cell types:
1767 $_MUX_
33 $_ORNOT_
1034 $_OR_
511 $_XOR_
not replaced 8 cell types:
1340 $_AND_
482 $_NOT_
16 $_TBUF_
31 $scopeinfo
2399 TRELLIS_FF
2 DP16KD
16 MULT18X18D
446 $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C
17.46.15.1. Executing ABC9_OPS pass (helper functions for ABC9).
17.46.15.2. Executing ABC9_OPS pass (helper functions for ABC9).
17.46.15.3. Executing XAIGER backend.
<suppressed ~11 debug messages>
Extracted 9241 AND gates and 27718 wires from module `spi_neuron_top' to a netlist network with 2684 inputs and 1614 outputs.
17.46.15.4. Executing ABC9_EXE pass (technology mapping using ABC9).
17.46.15.5. Executing ABC9.
Running ABC command: "<yosys-exe-dir>/yosys-abc" -s -f <abc-temp-dir>/abc.script 2>&1
ABC: ======== ABC command line "source <abc-temp-dir>/abc.script"
ABC: + read_lut <abc-temp-dir>/input.lut
ABC: + read_box <abc-temp-dir>/input.box
ABC: + &read <abc-temp-dir>/input.xaig
ABC: + &ps
ABC: <abc-temp-dir>/input : i/o = 2684/ 1614 and = 8155 lev = 21 (1.26) mem = 0.24 MB box = 446 bb = 0
ABC: Warning: AIG with boxes has internal fanout in 0 complex flops and 4 carries.
ABC: + &scorr
ABC: Warning: The network is combinational.
ABC: + &sweep
ABC: + &dc2
ABC: + &dch -f -r
ABC: + &ps
ABC: <abc-temp-dir>/input : i/o = 2684/ 1614 and = 12513 lev = 36 (1.17) mem = 0.29 MB ch = 1870 box = 446 bb = 0
ABC: cst = 0 cls = 1821 lit = 1870 unused = 12844 proof = 0
ABC: Warning: AIG with boxes has internal fanout in 0 complex flops and 4 carries.
ABC: + &if -W 300 -v
ABC: K = 7. Memory (bytes): Truth = 0. Cut = 76. Obj = 156. Set = 780. CutMin = no
ABC: Node = 12513. Ch = 1821. Total mem = 3.64 MB. Peak cut mem = 0.17 MB.
ABC: P: Del = 6301.00. Ar = 5834.0. Edge = 8458. Cut = 123868. T = 0.01 sec
ABC: P: Del = 6301.00. Ar = 5678.0. Edge = 8456. Cut = 123524. T = 0.01 sec
ABC: P: Del = 6301.00. Ar = 3632.0. Edge = 9233. Cut = 173962. T = 0.02 sec
ABC: F: Del = 6294.00. Ar = 2865.0. Edge = 8214. Cut = 157953. T = 0.01 sec
ABC: A: Del = 6294.00. Ar = 2845.0. Edge = 7918. Cut = 158135. T = 0.02 sec
ABC: A: Del = 6294.00. Ar = 2828.0. Edge = 7935. Cut = 156820. T = 0.02 sec
ABC: Total time = 0.09 sec
ABC: + &write -n <abc-temp-dir>/output.aig
ABC: + &mfs
ABC: + &ps -l
ABC: <abc-temp-dir>/input : i/o = 2684/ 1614 and = 9667 lev = 20 (1.15) mem = 0.26 MB box = 444 bb = 0
ABC: Mapping (K=6) : lut = 2069 edge = 7597 lev = 7 (0.53) levB = 24 mem = 0.12 MB
ABC: LUT = 2069 : 2=213 10.3 % 3=798 38.6 % 4=533 25.8 % 5=505 24.4 % 6=20 1.0 % Ave = 3.67
ABC: + &write -n <abc-temp-dir>/output.aig
ABC: + &verify
ABC: Networks are equivalent. Time = 0.14 sec
ABC: + time
ABC: elapse: 2.13 seconds, total: 2.13 seconds
17.46.15.6. Executing AIGER frontend.
<suppressed ~10 debug messages>
Removed 16979 unused cells and 26112 unused wires.
17.46.15.7. Executing ABC_OPS_REINTEGRATE pass (reintegrate ABC mapped design into module).
ABC RESULTS: $lut cells: 2075
ABC RESULTS: $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C cells: 444
ABC RESULTS: input signals: 167
ABC RESULTS: output signals: 439
<suppressed ~8598 debug messages>
Removing temp directory.
17.46.16. Executing TECHMAP pass (map to technology primitives).
17.46.16.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/abc9_unmap.v
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/abc9_unmap.v' to AST representation.
Generating RTLIL representation for module `$__DFF_x__$abc9_flop'.
Generating RTLIL representation for module `$__ABC9_SCC_BREAKER'.
Successfully finished Verilog frontend.
17.46.16.2. Continuing TECHMAP pass.
Using template $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C for cells of type $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C.
No more expansions possible.
<suppressed ~450 debug messages>
Removed 399 unused cells and 32322 unused wires.
17.47. Executing TECHMAP pass (map to technology primitives).
17.47.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v' to AST representation.
Generating RTLIL representation for module `$_DFF_N_'.
Generating RTLIL representation for module `$_DFF_P_'.
Generating RTLIL representation for module `$_DFFE_NN_'.
Generating RTLIL representation for module `$_DFFE_PN_'.
Generating RTLIL representation for module `$_DFFE_NP_'.
Generating RTLIL representation for module `$_DFFE_PP_'.
Generating RTLIL representation for module `$_DFF_NP0_'.
Generating RTLIL representation for module `$_DFF_NP1_'.
Generating RTLIL representation for module `$_DFF_PP0_'.
Generating RTLIL representation for module `$_DFF_PP1_'.
Generating RTLIL representation for module `$_SDFF_NP0_'.
Generating RTLIL representation for module `$_SDFF_NP1_'.
Generating RTLIL representation for module `$_SDFF_PP0_'.
Generating RTLIL representation for module `$_SDFF_PP1_'.
Generating RTLIL representation for module `$_DFFE_NP0P_'.
Generating RTLIL representation for module `$_DFFE_NP1P_'.
Generating RTLIL representation for module `$_DFFE_PP0P_'.
Generating RTLIL representation for module `$_DFFE_PP1P_'.
Generating RTLIL representation for module `$_DFFE_NP0N_'.
Generating RTLIL representation for module `$_DFFE_NP1N_'.
Generating RTLIL representation for module `$_DFFE_PP0N_'.
Generating RTLIL representation for module `$_DFFE_PP1N_'.
Generating RTLIL representation for module `$_SDFFE_NP0P_'.
Generating RTLIL representation for module `$_SDFFE_NP1P_'.
Generating RTLIL representation for module `$_SDFFE_PP0P_'.
Generating RTLIL representation for module `$_SDFFE_PP1P_'.
Generating RTLIL representation for module `$_SDFFE_NP0N_'.
Generating RTLIL representation for module `$_SDFFE_NP1N_'.
Generating RTLIL representation for module `$_SDFFE_PP0N_'.
Generating RTLIL representation for module `$_SDFFE_PP1N_'.
Generating RTLIL representation for module `$_ALDFF_NP_'.
Generating RTLIL representation for module `$_ALDFF_PP_'.
Generating RTLIL representation for module `$_ALDFFE_NPN_'.
Generating RTLIL representation for module `$_ALDFFE_NPP_'.
Generating RTLIL representation for module `$_ALDFFE_PPN_'.
Generating RTLIL representation for module `$_ALDFFE_PPP_'.
Generating RTLIL representation for module `\FD1P3AX'.
Generating RTLIL representation for module `\FD1P3AY'.
Generating RTLIL representation for module `\FD1P3BX'.
Generating RTLIL representation for module `\FD1P3DX'.
Generating RTLIL representation for module `\FD1P3IX'.
Generating RTLIL representation for module `\FD1P3JX'.
Generating RTLIL representation for module `\FD1S3AX'.
Generating RTLIL representation for module `\FD1S3AY'.
Generating RTLIL representation for module `\FD1S3BX'.
Generating RTLIL representation for module `\FD1S3DX'.
Generating RTLIL representation for module `\FD1S3IX'.
Generating RTLIL representation for module `\FD1S3JX'.
Generating RTLIL representation for module `\IFS1P3BX'.
Generating RTLIL representation for module `\IFS1P3DX'.
Generating RTLIL representation for module `\IFS1P3IX'.
Generating RTLIL representation for module `\IFS1P3JX'.
Generating RTLIL representation for module `\OFS1P3BX'.
Generating RTLIL representation for module `\OFS1P3DX'.
Generating RTLIL representation for module `\OFS1P3IX'.
Generating RTLIL representation for module `\OFS1P3JX'.
Generating RTLIL representation for module `\IB'.
Generating RTLIL representation for module `\IBPU'.
Generating RTLIL representation for module `\IBPD'.
Generating RTLIL representation for module `\OB'.
Generating RTLIL representation for module `\OBZ'.
Generating RTLIL representation for module `\OBZPU'.
Generating RTLIL representation for module `\OBZPD'.
Generating RTLIL representation for module `\OBCO'.
Generating RTLIL representation for module `\BB'.
Generating RTLIL representation for module `\BBPU'.
Generating RTLIL representation for module `\BBPD'.
Generating RTLIL representation for module `\ILVDS'.
Generating RTLIL representation for module `\OLVDS'.
Generating RTLIL representation for module `$lut'.
Successfully finished Verilog frontend.
17.47.2. Continuing TECHMAP pass.
Using template $paramod$4282def8dbd6df3d1248ad282c629bee684502c2$lut for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1001 for cells of type $lut.
Using template $paramod$69f20e0703606f2ffd2ee27cd26f815bd5eeb6e9$lut for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11101000 for cells of type $lut.
Using template $paramod$354c6e12bb192c5ea1375ea4c9e81a221c8f7991$lut for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01101001 for cells of type $lut.
Using template $paramod$21a9cf1c7cffed4ea7970972274e8bcced7c7005$lut for cells of type $lut.
Using template $paramod$142e854f92b6d714434fbdbb8149d8417cb5fb13$lut for cells of type $lut.
Using template $paramod$f05d4b8888c79762c43743d193b4196209b4613e$lut for cells of type $lut.
Using template $paramod$334a35f6fabc805b711c522405e5a57237b4958b$lut for cells of type $lut.
Using template $paramod$2f3577571d5c3142f074016ee0edb7ccc9033855$lut for cells of type $lut.
Using template $paramod$59dbfef3d2e0c7721ec21b9ce3ac17369e5a83a5$lut for cells of type $lut.
Using template $paramod$8133645849acf2279193def0d1b65972d5a7eed2$lut for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0001 for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0010 for cells of type $lut.
Using template $paramod$89dffaba5f5e7d225ffad4faa3c59e4e92b36c80$lut for cells of type $lut.
Using template $paramod$1b4942fad7257f60532954b1eb94a6b84f2e5ae3$lut for cells of type $lut.
Using template $paramod$db738be77b96326a46ff06b19713ffc9bc25345a$lut for cells of type $lut.
Using template $paramod$2d9c03629f235f9d280d876ccd58e51659259274$lut for cells of type $lut.
Using template $paramod$9aaf4b372e04ab3d0ad800f237c4b5bae7dadda8$lut for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11011000 for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11100010 for cells of type $lut.
Using template $paramod$fa45f28daf300aaa781ee4b9baa5ce968b1d8c66$lut for cells of type $lut.
Using template $paramod$873c285bdccf0ac2b60d2304ea5cd14bf211d2a6$lut for cells of type $lut.
Using template $paramod$6e238df02989b317f10820a22773676e71120644$lut for cells of type $lut.
Using template $paramod$53ce561f80f32d4298a3beadc88b6c5c78293221$lut for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10101100 for cells of type $lut.
Using template $paramod$8512f4fb47fa9596f76cdbe5b407a5b54df368e7$lut for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01100000 for cells of type $lut.
Using template $paramod$df196ed0a1da5c4a58c5e08a1dac304fd3fccaab$lut for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1000 for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0100 for cells of type $lut.
Using template $paramod$f8f63b209b7230e81958663ff24fef1613156af7$lut for cells of type $lut.
Using template $paramod$23b135911b7c14b5b19b5329e5903bcf58b44188$lut for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10111111 for cells of type $lut.
Using template $paramod$69cd07689187c617289e4eda75b267345c09f795$lut for cells of type $lut.
Using template $paramod$2014354416722209de7d48370ab008bc2278a034$lut for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11001010 for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1110 for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00010000 for cells of type $lut.
Using template $paramod$20ed9f6c34376098741386313f53f0d9dde2d47d$lut for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10111000 for cells of type $lut.
Using template $paramod$3718b46f9fc8e7db62b1202aeaec21c3331ed565$lut for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01000000 for cells of type $lut.
Using template $paramod$edc5a73130589b9210f4bdf92e14bdcacac8945d$lut for cells of type $lut.
Using template $paramod$e3e4230bb990723642112b292aa705ee0cbad0d4$lut for cells of type $lut.
Using template $paramod$571404c0889eaf57f492cb5e37f8acb5df5852f9$lut for cells of type $lut.
Using template $paramod$f9813472aa48e533b3838c6f2316dc2e78c66111$lut for cells of type $lut.
Using template $paramod$b2e8d279775d333b39e310bd45fd5952acdde290$lut for cells of type $lut.
Using template $paramod$e571785b36429a4ddda31d31c603f79bc5044f24$lut for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00001000 for cells of type $lut.
Using template $paramod$47b2f5a9f58cb4be072657772748a1ab82d6819a$lut for cells of type $lut.
Using template $paramod$cf52221ef2d451442dd7d72d5c8ad598e89310e9$lut for cells of type $lut.
Using template $paramod$272652f6c6fbe9a75eff76e45cc7e2788835518b$lut for cells of type $lut.
Using template $paramod$658b9ed803f0d3d335616d3858b53e0a2522f1e8$lut for cells of type $lut.
Using template $paramod$364c9ffbffac467d60dfec81bba4e18476c15602$lut for cells of type $lut.
Using template $paramod$f405ee362848dd1a47c58160f854302f6ecf95ff$lut for cells of type $lut.
Using template $paramod$535894650e163be6d7ba33c318478229111914d3$lut for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00101000 for cells of type $lut.
Using template $paramod$fd0cad4cc279ba7818b18175b73724f968330d2a$lut for cells of type $lut.
Using template $paramod$ba018320c09b6ecbdc95fc97480f4fe931c8f33f$lut for cells of type $lut.
Using template $paramod$101238f3d8d49ab12a9b49a2f01cd503b26e9c61$lut for cells of type $lut.
Using template $paramod$85b779ce5ab505dbf25e5e046fb43ca2b76b878b$lut for cells of type $lut.
Using template $paramod$9bdc414229f06e785dc8fd97a243faa9336e164a$lut for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000010 for cells of type $lut.
Using template $paramod$213c194ed908474cb37eba4425b73aced3c959dc$lut for cells of type $lut.
Using template $paramod$5f2c184e719bd4e5fefb9f913b84bd9e97cd57c5$lut for cells of type $lut.
Using template $paramod$17d0f5800c5f64fa392606fd7bbde9f3f932b963$lut for cells of type $lut.
Using template $paramod$6d6beead1425af15cf78b27fd9b11b41b5d4bce8$lut for cells of type $lut.
Using template $paramod$17d4fb2077cb7df6fab11c907c67b6f08f6e17ae$lut for cells of type $lut.
Using template $paramod$eba7de026ff587370e320127e266317dae097a89$lut for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000001 for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10000000 for cells of type $lut.
Using template $paramod$251994398653c4cf8de320f1e306e535d5d2d624$lut for cells of type $lut.
Using template $paramod$de81bb4f24bddd9c01fb4a8d2c0db4e04ac2517e$lut for cells of type $lut.
Using template $paramod$0f31ab84fdfd9592cc83273fda52360695fa911e$lut for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11110010 for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11100000 for cells of type $lut.
Using template $paramod$722bfd9af0ae56ca9d1d12a221cb5ede16461f26$lut for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1101 for cells of type $lut.
Using template $paramod$a76326805bbb30a33bf46239f93b537676c24ad2$lut for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10101011 for cells of type $lut.
Using template $paramod$fee012b92df74541b277e340e6596737f818902d$lut for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11011100 for cells of type $lut.
Using template $paramod$c1a19a87ccbbb03d43a72335db63f692ddf82cc1$lut for cells of type $lut.
Using template $paramod$cd8c7d2723a222b682a2fd78a214901053a6577d$lut for cells of type $lut.
Using template $paramod$965f8f2fa1a796a6c51222eabb50fbd26e97d98b$lut for cells of type $lut.
Using template $paramod$e5e9da8fed769f971686eed8c5eea50e61f73aaa$lut for cells of type $lut.
Using template $paramod$6036593eb6f7d1618fdaa514fe11339bec63f433$lut for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1011 for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11110111 for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11101010 for cells of type $lut.
Using template $paramod$ad823946862e656cf7f96d606b18b8f972dc6d6c$lut for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0111 for cells of type $lut.
Using template $paramod$af4bc2a77e08a2bcfb751a0b02b8f9398359979b$lut for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11111110 for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00100000 for cells of type $lut.
Using template $paramod$acb55385383eb6e0dd46a2fd1eab59cbc9d127ed$lut for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11100100 for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10111010 for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000100 for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11110100 for cells of type $lut.
Using template $paramod$c307720af3518f2c0f3dfbbab50341ca419b75eb$lut for cells of type $lut.
Using template $paramod$11426815751623871d46bc9f1667ef33eaf7eced$lut for cells of type $lut.
Using template $paramod$7e3d8ac009723e554811ad53385162c0e6a41625$lut for cells of type $lut.
Using template $paramod$5ce0414f30742591cfbc3ba73903b522793ddcd1$lut for cells of type $lut.
Using template $paramod$260195b3556bd478f2b5f2910450bd50d685bbe2$lut for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11110001 for cells of type $lut.
Using template $paramod$5dc745bb48e2cf535179547ba13f0fe5364d6d54$lut for cells of type $lut.
Using template $paramod$ffc80aea4aa44f0166b2d4713ba5912f56e92991$lut for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11111101 for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10100010 for cells of type $lut.
Using template $paramod$3c64762f56d2dfc9226156923515f492b69b41a9$lut for cells of type $lut.
Using template $paramod$106b4d877d926f41bd5171be21de0765aec0f89c$lut for cells of type $lut.
Using template $paramod$e0286d7bdebdb6346cb367bb1962e01892ba2e32$lut for cells of type $lut.
Using template $paramod$f176067fa36e2eba8bbf04c3cb0fb3aa337e56cb$lut for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01010001 for cells of type $lut.
Using template $paramod$b89c522b7f70adaee1a35d80e932f38159b6a445$lut for cells of type $lut.
Using template $paramod$f3b603d1450c2c61ce732232fcb5fe1f2884aa83$lut for cells of type $lut.
Using template $paramod$850f48dac4014f6ce06187aa7664648cd494a38b$lut for cells of type $lut.
Using template $paramod$15c6bfc31af3fb8d66360f5028be453375363deb$lut for cells of type $lut.
Using template $paramod$08bef9b5ac3107e0490c4b78b8fe4edf46d39216$lut for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11111011 for cells of type $lut.
Using template $paramod$dbbe0ea5aadf61e5da6ebbf1f47442d5facdca4e$lut for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11111000 for cells of type $lut.
Using template $paramod$f4e3e92a4c91ccc38cbcadd03ed0b5769fbf8483$lut for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0110 for cells of type $lut.
Using template $paramod$5b4b4ed558983d9f3ab4c896a7a011d129b0db9a$lut for cells of type $lut.
Using template $paramod$25f748a39f13f638a0dd44b265e145242e43bbc5$lut for cells of type $lut.
Using template $paramod$7e9df0afb32b76fe5fce0691b8752aca650057fa$lut for cells of type $lut.
Using template $paramod$47a8214374025465e226fa66bee690ff33268a25$lut for cells of type $lut.
Using template $paramod$fda6887b37f599177ed9cb69271d882b63df7e66$lut for cells of type $lut.
Using template $paramod$65ed928f276bb5c401ea86a9f3a0e35366c7261e$lut for cells of type $lut.
Using template $paramod$c804510587673ea9effea3633f70afe50850f176$lut for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01101010 for cells of type $lut.
Using template $paramod$8fb7c2a4174bbb0f9870bcb831d0cc7f5057f41f$lut for cells of type $lut.
Using template $paramod$8e44661def013b6bf9fe6f8b049ef2c838d749f9$lut for cells of type $lut.
Using template $paramod$81df3b5b0c68f16cd64a76012a4213a1b5a86efa$lut for cells of type $lut.
Using template $paramod$1cabbe2f17ea824b0f9f091fd1dc13fff0b3a362$lut for cells of type $lut.
Using template $paramod$bf60f6ec407ee294958b6566514fc3125ec42258$lut for cells of type $lut.
Using template $paramod$5230997e711671eb080ae3ffb7dd6504f5b33365$lut for cells of type $lut.
Using template $paramod$e51a8a571bee774247b38f52d6e85fd62ae52cea$lut for cells of type $lut.
Using template $paramod$b384dc73c0775b5f6f92a9b94aaf5890a74d4097$lut for cells of type $lut.
Using template $paramod$9d1915f40715c7f715525567f7dfd63744c26c4a$lut for cells of type $lut.
Using template $paramod$b4f15f202f50520dbc381cd0880ac94f830f05a8$lut for cells of type $lut.
Using template $paramod$373d637619c29cb9150902df9528107e5f3b8288$lut for cells of type $lut.
Using template $paramod$3a76ae1ac16567d84de882ad5b89dd62763f5d7e$lut for cells of type $lut.
Using template $paramod$ae847b3caa0d009b4b5d7e5047ef425662ce7a78$lut for cells of type $lut.
Using template $paramod$76bd41a9a8efaf6cf387246ec03651601adee5e3$lut for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10101110 for cells of type $lut.
Using template $paramod$8e7b1ec7df4c8852d827365421a6d41e55bd7752$lut for cells of type $lut.
Using template $paramod$228e7968edba70367b6b9d961263814d7f7c612c$lut for cells of type $lut.
Using template $paramod$0c822c65361ce832091b6c90f1a02f1ee0b109d4$lut for cells of type $lut.
Using template $paramod$88a379586ab99d22384fb6ffdcafb4a7aae8da78$lut for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10001011 for cells of type $lut.
Using template $paramod$a9fc6e1212e2c97f661279eebf7fa89d410eb14a$lut for cells of type $lut.
Using template $paramod$1bf2057bd0198df093f02a0db6737166edb9eb39$lut for cells of type $lut.
Using template $paramod$4217385c795f6ab62eb168be8f9deadb7111639b$lut for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11010100 for cells of type $lut.
Using template $paramod$b9f1cc075fd5e1dc13f6aa9fc152bf79a0f71ef7$lut for cells of type $lut.
Using template $paramod$a4404e742e43b8bf8bde71df8b64cbe0c6ba02bd$lut for cells of type $lut.
Using template $paramod$478e33feeac3aa53ff57d491aada044b8aedceae$lut for cells of type $lut.
Using template $paramod$ab8bb87959c5d7cfa27886cee1355b38e054a61a$lut for cells of type $lut.
Using template $paramod$4658fedcd7ebe2858c93f54b88221dcf68c6bb6c$lut for cells of type $lut.
Using template $paramod$0cfa02b8e619bfc1aba4a45bcc0909421d0ed179$lut for cells of type $lut.
Using template $paramod$ed4b624f477a67dbd878e676981471b9a7808c29$lut for cells of type $lut.
Using template $paramod$992bdc10cff2c6edd722994f0e1044bc863f79f7$lut for cells of type $lut.
Using template $paramod$b86b68a00733dbecb31d58a14a13683475a2002a$lut for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10010000 for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01001110 for cells of type $lut.
Using template $paramod$d575d3554e876f643193272ee6813447059f103f$lut for cells of type $lut.
Using template $paramod$4d7f17f71543a1e7fc1835bd79c4827a43f2e844$lut for cells of type $lut.
Using template $paramod$65d5d5c1e01bf41ee659754efba932f3d99198e5$lut for cells of type $lut.
Using template $paramod$e6049326c8634f79a905c381bb150ca718b543fa$lut for cells of type $lut.
Using template $paramod$daac9b1e7bb2ac018f7132a3fbe0026ddd7b1a71$lut for cells of type $lut.
Using template $paramod$79fa5dc7b758560fe794c69b8a91c5bbe4b5db3e$lut for cells of type $lut.
Using template $paramod$24b67fade1852074c0ac6a4c585dd4228e286f08$lut for cells of type $lut.
Using template $paramod$477da4277c03c2ef33b36398805e65ce04b52e70$lut for cells of type $lut.
Using template $paramod$6e1e2bf7f29cfe416c0ceb4dc5c676edd2a3b996$lut for cells of type $lut.
Using template $paramod$b1c1fcc81573437ec158d7c629938862148f7151$lut for cells of type $lut.
Using template $paramod$8702d826849a5d8af6dd5fde2d287a6443f7d076$lut for cells of type $lut.
Using template $paramod$72043e0aa7fa64cb454e3c2ca3dbe1636171896a$lut for cells of type $lut.
Using template $paramod$af763bca85949884aefa417266a961f9c91132de$lut for cells of type $lut.
Using template $paramod$8a77a4b825e7cd0e2a0cbe1bb8ec99794d7f5906$lut for cells of type $lut.
Using template $paramod$45d35c067ded9854bad436d064758afc38659286$lut for cells of type $lut.
Using template $paramod$c24ed72ebb67e9ead6029e42e909ef7fc0abbb11$lut for cells of type $lut.
Using template $paramod$001d9634602f00137f774620efde4c651c7a59ca$lut for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00001110 for cells of type $lut.
Using template $paramod$3830fbfbec2ed4d6e3e957e17e4fca97b7adef1f$lut for cells of type $lut.
Using template $paramod$7aa8140c7d6de3160b21e7ff84e0f93f69f7fcc6$lut for cells of type $lut.
Using template $paramod$94ac66a11090dca84889e55fcf03297912a5b7ec$lut for cells of type $lut.
Using template $paramod$66caeb00a39d236782a97659e3bd99621b74681b$lut for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00010011 for cells of type $lut.
Using template $paramod$df29fe9e6d6d694a9cc5697e4251bf7d8cd4d8e4$lut for cells of type $lut.
Using template $paramod$fca001e3e0b52158a872e76e56c01ec10dfbb1de$lut for cells of type $lut.
Using template $paramod$9943bc8845ec6caf7afa256c0a4d1e541a8b4c41$lut for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10000010 for cells of type $lut.
Using template $paramod$3a75385b1beb239786b9fcdc898b53110e63595f$lut for cells of type $lut.
Using template $paramod$e5477ee47846ce208224b9029657ffd8771566cb$lut for cells of type $lut.
Using template $paramod$210534b73e432a1d89abd2ae048c31c7f92e6092$lut for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00101011 for cells of type $lut.
Using template $paramod$fd904e9e35cfd343a9df248824bd3f1408724879$lut for cells of type $lut.
Using template $paramod$a547ebbcb936a0942e18c1762283837f76f0003a$lut for cells of type $lut.
Using template $paramod$446d5374f1a9a50c11eb107999155fc0219be593$lut for cells of type $lut.
Using template $paramod$a16c3add4d1b8f45e003cec32fa5f9877413f790$lut for cells of type $lut.
Using template $paramod$24a071e37fb30533686475161ae3a85ccfc2f924$lut for cells of type $lut.
Using template $paramod$053427f7f5ea07d59a8194fc808f0dbdb8dee48b$lut for cells of type $lut.
Using template $paramod$e4b9bd705416a24da0fb7793aacf194000cd6ca6$lut for cells of type $lut.
Using template $paramod$9d12c15405e25608417ce779d7fe1b86619365f9$lut for cells of type $lut.
Using template $paramod$c9994e2a733aa21e4bfe57075af37a9c5257c791$lut for cells of type $lut.
Using template $paramod$5a2475f0ff8adfa6c48e46c1977dad3962daa33d$lut for cells of type $lut.
Using template $paramod$bab3258ad21cb83a958fbc51f2a3a88704f4353a$lut for cells of type $lut.
Using template $paramod$52adc4306ced619ca2f6304c7a7bbf71ea42dfec$lut for cells of type $lut.
Using template $paramod$25778dc227058ce4d08c7139853cde1896fb97bd$lut for cells of type $lut.
Using template $paramod$a03ef989f8f4e1878ce2f5c4e0e3d2dfb54307ef$lut for cells of type $lut.
Using template $paramod$691e5d89fa42ac31086ffa9583f01739cd14cecd$lut for cells of type $lut.
Using template $paramod$c68110307ed3a83d1f1d050a34218c458bce2221$lut for cells of type $lut.
Using template $paramod$856d39e7e3d7f684f4fddef2de69af230893be00$lut for cells of type $lut.
Using template $paramod$aff322071f8e330405c91c2a23611b4bceb72d04$lut for cells of type $lut.
Using template $paramod$71d951b20e73043168c1656217d126e617052faa$lut for cells of type $lut.
Using template $paramod$5e9374f44a27c3f8a1c38af244ec43ceb4fb8d4f$lut for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00110001 for cells of type $lut.
Using template $paramod$ce02e2afa3256c1c2c45460d429171d794707fae$lut for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11000101 for cells of type $lut.
Using template $paramod$94d2f1f461ef911482e15efdba185521de732c99$lut for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01110010 for cells of type $lut.
Using template $paramod$64c98a93c00f2932cdb01ce29e3a216b58ad51fe$lut for cells of type $lut.
Using template $paramod$1fb263bbfd72e189ea4c9a7f3de6e386d5560311$lut for cells of type $lut.
Using template $paramod$9feab87b47f9b0347a10de4b271dee8df9fb602d$lut for cells of type $lut.
Using template $paramod$d4b8f08be5022193a69dfe31654c06b8c2e1ac1d$lut for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00001011 for cells of type $lut.
Using template $paramod$e484b1e0bd351ba5af34f5fd66a8e850cc5b8335$lut for cells of type $lut.
Using template $paramod$ec81262755b5faeae9efcdd7371cb9491a86822d$lut for cells of type $lut.
Using template $paramod$0fa351d24d2713ce0a93e46f5deedd65d95d22b8$lut for cells of type $lut.
Using template $paramod$25003f26a78bb2f583f23824f1e0b8cc16b88761$lut for cells of type $lut.
Using template $paramod$d546db88fc169832512e499a9cdf9a41b89ab74e$lut for cells of type $lut.
Using template $paramod$0498819220bb36cfd5ba6facabe8eab892920bd6$lut for cells of type $lut.
Using template $paramod$63adfd7f010aebf4643ba93b2dbe21144284e1e6$lut for cells of type $lut.
Using template $paramod$a50c854edddc8ebaebc58b330fdd1445acaa5865$lut for cells of type $lut.
Using template $paramod$81d8a60fd95b1a9f9ef71c12a774ae6988cb9fd5$lut for cells of type $lut.
Using template $paramod$04b674496422df8889c01c3744b94097628ccfbc$lut for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00101110 for cells of type $lut.
Using template $paramod$ec6c71d259df49ae0842190ffaff1179e43a8db4$lut for cells of type $lut.
Using template $paramod$290541634e6c79e21042e339be1ae55a6712f931$lut for cells of type $lut.
Using template $paramod$e46703b423a661cd7d311c41833ea655969702cc$lut for cells of type $lut.
Using template $paramod$764f077a69bdc32449880eb7993086f6ef26b3ee$lut for cells of type $lut.
Using template $paramod$047d0df6c87b7042d6d894454cb0917def4e9363$lut for cells of type $lut.
Using template $paramod$b4410865e8124402796f9dfbf73ef8d279fdbd08$lut for cells of type $lut.
Using template $paramod$f969aefcb5fdd29444244ce17e4806b1ebc6f568$lut for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01000101 for cells of type $lut.
Using template $paramod$3fd3cd243a8b2f71b0ffe04bdaebf6ad83bcc78e$lut for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10100011 for cells of type $lut.
Using template $paramod$d7c634c964a868577f926c0690c937ab5b147f6e$lut for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10110000 for cells of type $lut.
Using template $paramod$f921ab2c451d17e196d1dcad0b6d434881387fe3$lut for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000001\LUT=2'01 for cells of type $lut.
No more expansions possible.
<suppressed ~5478 debug messages>
17.48. Executing OPT_LUT_INS pass (discard unused LUT inputs).
Optimizing LUTs in spi_neuron_top.
Optimizing lut $abc$73446$lut$aiger$o5011.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
Optimizing lut $abc$73446$lut$aiger73445$11008.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$73446$lut$aiger$o4682.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
Optimizing lut $abc$73446$lut$aiger$o4188.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
Optimizing lut $abc$73446$lut$aiger$o4972.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$73446$lut$aiger$o5204.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
Optimizing lut $abc$73446$lut$aiger73445$11844.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$73446$lut$aiger$o4381.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$73446$lut$aiger73445$10805.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$73446$lut$aiger73445$11261.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$73446$lut$aiger73445$11796.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$73446$lut$aiger73445$10782.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$73446$lut$aiger$o5054.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
Optimizing lut $abc$73446$lut$aiger$o5305.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
Optimizing lut $abc$73446$lut$aiger73445$9529.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$73446$lut$aiger73445$10732.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$73446$lut$aiger73445$10065.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$73446$lut$aiger73445$11663.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$73446$lut$aiger$o5148.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$73466.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$73483.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$73484.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$73446$lut$aiger73445$4277.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
Optimizing lut $abc$73446$lut$aiger73445$4103.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$73785.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$73479.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$73446$lut$aiger73445$11591.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$73501.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$73505.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$73446$lut$aiger73445$10028.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
Optimizing lut $abc$73446$lut$aiger73445$6244.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$73446$lut$aiger73445$10294.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$73446$lut$aiger$o5011.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$73446$lut$aiger73445$11039.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$73446$lut$aiger73445$11039.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$73527.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$73528.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$73446$lut$aiger73445$6291.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$73446$lut$aiger$o5122.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
Optimizing lut $abc$73446$lut$aiger$o4685.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
Optimizing lut $abc$73446$lut$aiger$o4685.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$73446$lut$aiger$o5122.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$73446$lut$aiger$o5373.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
Optimizing lut $abc$73446$lut$aiger$o5373.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$73446$lut$aiger73445$8576.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$73446$lut$aiger73445$6320.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$73446$lut$aiger73445$11008.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
Optimizing lut $abc$73446$lut$aiger73445$12070.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$73446$lut$aiger$o4605.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$73493.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$73784.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$73446$lut$aiger73445$12070.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
Optimizing lut $abc$73446$lut$aiger73445$11482.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$73446$lut$aiger73445$11482.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
Optimizing lut $abc$73446$lut$aiger73445$6385.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$73577.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$73446$lut$aiger$o4931.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
Optimizing lut $abc$73446$lut$aiger73445$6401.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$73446$lut$aiger$o4260.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$73587.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
Optimizing lut $abc$73446$lut$aiger73445$12025.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$73446$lut$aiger73445$12025.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
Optimizing lut $abc$73446$lut$aiger$o4583.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
Optimizing lut $abc$73446$lut$aiger$o4583.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$73446$lut$aiger73445$9156.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$73602.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
Optimizing lut $abc$73446$lut$aiger73445$9156.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$73610.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$73446$lut$aiger73445$6468.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
Optimizing lut $abc$73446$lut$aiger73445$6468.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$73446$lut$aiger$o4980.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
Optimizing lut $abc$73446$lut$aiger$o4980.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$73446$lut$aiger$o5351.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
Optimizing lut $abc$73446$lut$aiger$o5351.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$73617.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
Optimizing lut $abc$73446$lut$aiger73445$6481.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$73446$lut$aiger$o4188.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$73446$lut$aiger73445$10422.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$73446$lut$aiger$o4311.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$73446$lut$aiger73445$10511.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$73446$lut$aiger73445$10511.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
Optimizing lut $abc$73446$lut$aiger73445$6524.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$73446$lut$aiger73445$6528.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
Optimizing lut $abc$73446$lut$aiger73445$9963.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$73446$lut$aiger73445$9963.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
Optimizing lut $abc$73446$lut$aiger$o5230.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
Optimizing lut $abc$73446$lut$aiger$o5230.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$73446$lut$aiger73445$8463.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$73446$lut$aiger$o4219.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$73446$lut$aiger$o4219.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$73495.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$73533.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$73446$lut$aiger$o5331.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
Optimizing lut $abc$73446$lut$aiger$o5331.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$73446$lut$aiger$o4626.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
Optimizing lut $abc$73446$lut$aiger$o4244.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$73446$lut$aiger$o4250.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$73446$lut$aiger$o4266.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$73446$lut$aiger73445$6592.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
Optimizing lut $abc$73446$lut$aiger$o4575.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
Optimizing lut $abc$73446$lut$aiger$o4575.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$73446$lut$aiger$o5175.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
Optimizing lut $abc$73446$lut$aiger$o5204.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$73446$lut$aiger$o4828.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
Optimizing lut $abc$73446$lut$aiger$o4828.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$73446$lut$aiger73445$11297.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$73446$lut$aiger73445$11297.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
Optimizing lut $abc$73446$lut$aiger73445$11844.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
Optimizing lut $abc$73446$lut$aiger$o4774.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
Optimizing lut $abc$73446$lut$aiger$o4774.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$73446$lut$aiger73445$10422.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
Optimizing lut $abc$73446$lut$aiger73445$9186.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
Optimizing lut $abc$73446$lut$aiger73445$9702.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$73446$lut$aiger73445$9702.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
Optimizing lut $abc$73446$lut$aiger73445$9186.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$73446$lut$aiger$o4581.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
Optimizing lut $abc$73446$lut$aiger73445$11261.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
Optimizing lut $abc$73446$lut$aiger$o4467.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
Optimizing lut $abc$73446$lut$aiger$o4467.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$73446$lut$aiger73445$11796.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
Optimizing lut $abc$73446$lut$aiger73445$10782.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
Optimizing lut $abc$73446$lut$aiger$o4770.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$73446$lut$aiger$o4622.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$73446$lut$aiger$o5054.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$73446$lut$aiger$o5305.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$73745.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
Optimizing lut $abc$73446$lut$aiger$o5175.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$73446$lut$aiger73445$9529.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
Optimizing lut $abc$73446$lut$aiger73445$10743.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
Optimizing lut $abc$73446$lut$aiger73445$10732.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
Optimizing lut $abc$73446$lut$aiger$o4931.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$73772.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
Optimizing lut $abc$73446$lut$aiger$o4928.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
Optimizing lut $abc$73446$lut$aiger$o4928.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$73446$lut$aiger73445$8952.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$73446$lut$aiger$o5287.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
Optimizing lut $abc$73446$lut$aiger$o5287.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$73787.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$73446$lut$aiger73445$10065.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
Optimizing lut $abc$73446$lut$aiger73445$11663.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
Optimizing lut $abc$73446$lut$aiger73445$8654.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$73446$lut$aiger73445$6102.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
Optimizing lut $abc$73446$lut$aiger73445$6102.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
Optimizing lut $abc$73446$lut$aiger$o5148.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$73446$lut$aiger$o4093.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$73446$lut$aiger$o5272.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
Optimizing lut $abc$73446$lut$aiger$o5272.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$73446$lut$aiger73445$10294.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
Optimizing lut $abc$73446$lut$aiger73445$8684.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$73448.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$73446$lut$aiger73445$11591.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$73465.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$73616.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
Optimizing lut $abc$73446$lut$aiger73445$4270.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$73475.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$73446$lut$aiger73445$4114.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$73446$lut$aiger$o4030.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$73482.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$73472.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$73446$lut$aiger73445$4023.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$73446$lut$aiger73445$4052.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Removed 0 unused cells and 4656 unused wires.
17.49. Executing AUTONAME pass.
Renamed 9379 objects in module spi_neuron_top.
<suppressed ~9379 debug messages>
17.50. Executing HIERARCHY pass (managing design hierarchy).
Attribute `top' found on module `spi_neuron_top'. Setting top module to spi_neuron_top.
17.50.1. Analyzing design hierarchy..
Top module: \spi_neuron_top
17.50.2. Analyzing design hierarchy..
Top module: \spi_neuron_top
Removed 0 unused modules.
17.51. Printing statistics.
=== spi_neuron_top ===
+----------Local Count, excluding submodules.
|
3986 wires
17748 wire bits
3986 public wires
17748 public wire bits
14 ports
51 port bits
65 cells
16 $_TBUF_
31 $scopeinfo
2 DP16KD
16 MULT18X18D
6051 submodules
444 CCU2C
20 L6MUX21
2643 LUT4
545 PFUMX
2399 TRELLIS_FF
=== design hierarchy ===
+----------Count including submodules.
|
65 spi_neuron_top
+----------Count including submodules.
|
3986 wires
17748 wire bits
3986 public wires
17748 public wire bits
14 ports
51 port bits
- memories
- memory bits
- processes
65 cells
16 $_TBUF_
31 $scopeinfo
2 DP16KD
16 MULT18X18D
6051 submodules
444 CCU2C
20 L6MUX21
2643 LUT4
545 PFUMX
2399 TRELLIS_FF
17.52. Executing CHECK pass (checking for obvious problems).
Checking module spi_neuron_top...
Found and reported 0 problems.
17.53. Executing JSON backend.
18. Printing statistics.
=== spi_neuron_top ===
+----------Local Count, excluding submodules.
|
3986 wires
17748 wire bits
3986 public wires
17748 public wire bits
14 ports
51 port bits
6116 cells
16 $_TBUF_
31 $scopeinfo
444 CCU2C
2 DP16KD
20 L6MUX21
2643 LUT4
16 MULT18X18D
545 PFUMX
2399 TRELLIS_FF
Warnings: 1 unique messages, 1 total
End of script. Logfile hash: 66d89e2564, time: 3.95s, user: 1.94s, system: 0.05s, MEM: 172.97 MB peak
Yosys 0.68+post (git sha1 c12172fbae8af5e20f6fb52e3d4e92d56ed587b6, Release, AppleClang clang++ 21.0.0.21000101)
Time spent: 52% 1x abc9_exe (2 sec), 7% 12x techmap (0 sec), ...
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