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FPGA-Neural/hardware/v1/constraints/spi_neuron_top.lpf
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micheleandClaude Sonnet 5 dc0b331d3e feat(v2): scaffold hardware/v1 frozen baseline + M1 Neural Processor 
Begins the V2 Neural Multiprocessor / Dataflow architecture per
docs/v2-description.md, per explicit user request to freeze V1 and
start V2 development, copying from V1 what's needed.

Scaffold:
- hardware/v1/: byte-exact, read-only copy of the current V1 codebase
  (rtl, testbenches, tools, constraints, a representative subset of
  synthesis results, and reference docs) -- verified identical via
  diff/cmp against the live top-level tree before being made
  filesystem-read-only. The live top-level tree is untouched and
  remains the project's "production" V1 (see hardware/v1/README.md
  and hardware/v2/logs/decisions.log DEC-0001 for why copy-not-move).
- hardware/v2/: mandatory structure (rtl/sim/constraints/synthesis/
  reports/scripts/logs/docs) plus the full logging system required by
  the spec (development/architecture/simulation/synthesis/timing/
  benchmark/decisions/experiments/errors.log).

M1 -- Neural Processor (hardware/v2/rtl/neural_processor.v):
- 8-stage pipelined perceptron unit (P_IN=8): input align, 8
  multipliers, 3-level adder tree, accumulator, bias+activation, INT8
  saturation. Genuine 1-tile/cycle throughput, not just a wider
  combinational datapath.
- 7-state FSM (NP_IDLE..NP_ERROR per docs/v2-description.md §6, with
  4 baseline states merged into NP_WAIT_OPERANDS -- see
  decisions.log DEC-0002); valid/ready/data/last stream interfaces
  per §7.
- Bit-exact vs the frozen hardware/v1/rtl/neuron_parallel.v + mac8.v
  + mac_unit.v: 7/7 tests pass (hardware/v2/sim/tb_neural_processor.v),
  covering regular/mixed-sign/extreme-INT8 vectors, both activations,
  a zero-idle-gap back-to-back-tiles throughput check, and an 8-tile
  job -- verified with Verilator (see below for why).
- Real synthesis + place&route (Yosys + nextpnr-ecp5): 0 CHECK
  problems, Fmax 183.12 MHz at ACC_WIDTH=32 (PASS at 80MHz, ~3x V1's
  isolated PARALLEL=8 Fmax of 61.71 MHz) and 176.21 MHz at ACC_WIDTH=24
  (a user-requested comparison experiment, also bit-exact-verified;
  see experiments.log EXP-0001/EXP-0002 and benchmark.log).

Three real bugs found and resolved during M1 development (full
diagnostic record in errors.log):
- Two independent, reproducible Icarus Verilog v13.0 scheduling
  defects (ERR-0001, ERR-0002) that silently produced wrong simulation
  results for standard sequential Verilog -- confirmed via Verilator
  5.050 giving correct results on the same minimal repros. Verilator
  is now the trusted simulator for hardware/v2/ (decisions.log
  DEC-0004); Icarus's affected protocol-violation check was removed
  from the RTL and deferred architecturally to the Neural Director
  (DEC-0003) rather than chased further.
- One real RTL bug (ERR-0003): last0 wasn't gated like valid0,
  letting a "last tile" tag leak into the pipeline ahead of its
  actual valid tile on back-to-back jobs. Fixed and verified.

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
2026-09-05 14:06:53 +02:00

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BLOCK ASYNCPATHS;
BLOCK RESETPATHS;
LOCATE COMP "clk" SITE "H5";
IOBUF PORT "clk" IO_TYPE=LVCMOS33;
LOCATE COMP "cs_n" SITE "B3";
IOBUF PORT "cs_n" IO_TYPE=LVCMOS33;
LOCATE COMP "data_ready_n" SITE "C3";
IOBUF PORT "data_ready_n" IO_TYPE=LVCMOS33;
LOCATE COMP "flash_cs_n" SITE "E4";
IOBUF PORT "flash_cs_n" IO_TYPE=LVCMOS33;
LOCATE COMP "flash_miso" SITE "D5";
IOBUF PORT "flash_miso" IO_TYPE=LVCMOS33;
LOCATE COMP "flash_mosi" SITE "D3";
IOBUF PORT "flash_mosi" IO_TYPE=LVCMOS33;
LOCATE COMP "flash_sclk" SITE "E3";
IOBUF PORT "flash_sclk" IO_TYPE=LVCMOS33;
LOCATE COMP "irq_n" SITE "C4";
IOBUF PORT "irq_n" IO_TYPE=LVCMOS33;
LOCATE COMP "miso" SITE "A3";
IOBUF PORT "miso" IO_TYPE=LVCMOS33;
LOCATE COMP "mosi" SITE "C5";
IOBUF PORT "mosi" IO_TYPE=LVCMOS33;
LOCATE COMP "psram_a[0]" SITE "E16";
IOBUF PORT "psram_a[0]" IO_TYPE=LVCMOS33;
LOCATE COMP "psram_a[10]" SITE "H17";
IOBUF PORT "psram_a[10]" IO_TYPE=LVCMOS33;
LOCATE COMP "psram_a[11]" SITE "H18";
IOBUF PORT "psram_a[11]" IO_TYPE=LVCMOS33;
LOCATE COMP "psram_a[12]" SITE "J16";
IOBUF PORT "psram_a[12]" IO_TYPE=LVCMOS33;
LOCATE COMP "psram_a[13]" SITE "J17";
IOBUF PORT "psram_a[13]" IO_TYPE=LVCMOS33;
LOCATE COMP "psram_a[14]" SITE "C20";
IOBUF PORT "psram_a[14]" IO_TYPE=LVCMOS33;
LOCATE COMP "psram_a[15]" SITE "D19";
IOBUF PORT "psram_a[15]" IO_TYPE=LVCMOS33;
LOCATE COMP "psram_a[16]" SITE "E19";
IOBUF PORT "psram_a[16]" IO_TYPE=LVCMOS33;
LOCATE COMP "psram_a[17]" SITE "E20";
IOBUF PORT "psram_a[17]" IO_TYPE=LVCMOS33;
LOCATE COMP "psram_a[18]" SITE "F19";
IOBUF PORT "psram_a[18]" IO_TYPE=LVCMOS33;
LOCATE COMP "psram_a[19]" SITE "F20";
IOBUF PORT "psram_a[19]" IO_TYPE=LVCMOS33;
LOCATE COMP "psram_a[1]" SITE "F16";
IOBUF PORT "psram_a[1]" IO_TYPE=LVCMOS33;
LOCATE COMP "psram_a[20]" SITE "G20";
IOBUF PORT "psram_a[20]" IO_TYPE=LVCMOS33;
LOCATE COMP "psram_a[21]" SITE "H20";
IOBUF PORT "psram_a[21]" IO_TYPE=LVCMOS33;
LOCATE COMP "psram_a[22]" SITE "P18";
IOBUF PORT "psram_a[22]" IO_TYPE=LVCMOS33;
LOCATE COMP "psram_a[2]" SITE "D18";
IOBUF PORT "psram_a[2]" IO_TYPE=LVCMOS33;
LOCATE COMP "psram_a[3]" SITE "E17";
IOBUF PORT "psram_a[3]" IO_TYPE=LVCMOS33;
LOCATE COMP "psram_a[4]" SITE "E18";
IOBUF PORT "psram_a[4]" IO_TYPE=LVCMOS33;
LOCATE COMP "psram_a[5]" SITE "F18";
IOBUF PORT "psram_a[5]" IO_TYPE=LVCMOS33;
LOCATE COMP "psram_a[6]" SITE "F17";
IOBUF PORT "psram_a[6]" IO_TYPE=LVCMOS33;
LOCATE COMP "psram_a[7]" SITE "G16";
IOBUF PORT "psram_a[7]" IO_TYPE=LVCMOS33;
LOCATE COMP "psram_a[8]" SITE "G18";
IOBUF PORT "psram_a[8]" IO_TYPE=LVCMOS33;
LOCATE COMP "psram_a[9]" SITE "H16";
IOBUF PORT "psram_a[9]" IO_TYPE=LVCMOS33;
LOCATE COMP "psram_ce_n" SITE "N17";
IOBUF PORT "psram_ce_n" IO_TYPE=LVCMOS33;
LOCATE COMP "psram_dq[0]" SITE "K18";
IOBUF PORT "psram_dq[0]" IO_TYPE=LVCMOS33;
LOCATE COMP "psram_dq[10]" SITE "L17";
IOBUF PORT "psram_dq[10]" IO_TYPE=LVCMOS33;
LOCATE COMP "psram_dq[11]" SITE "M18";
IOBUF PORT "psram_dq[11]" IO_TYPE=LVCMOS33;
LOCATE COMP "psram_dq[12]" SITE "M17";
IOBUF PORT "psram_dq[12]" IO_TYPE=LVCMOS33;
LOCATE COMP "psram_dq[13]" SITE "N16";
IOBUF PORT "psram_dq[13]" IO_TYPE=LVCMOS33;
LOCATE COMP "psram_dq[14]" SITE "N18";
IOBUF PORT "psram_dq[14]" IO_TYPE=LVCMOS33;
LOCATE COMP "psram_dq[15]" SITE "P17";
IOBUF PORT "psram_dq[15]" IO_TYPE=LVCMOS33;
LOCATE COMP "psram_dq[1]" SITE "C18";
IOBUF PORT "psram_dq[1]" IO_TYPE=LVCMOS33;
LOCATE COMP "psram_dq[2]" SITE "D17";
IOBUF PORT "psram_dq[2]" IO_TYPE=LVCMOS33;
LOCATE COMP "psram_dq[3]" SITE "D20";
IOBUF PORT "psram_dq[3]" IO_TYPE=LVCMOS33;
LOCATE COMP "psram_dq[4]" SITE "G19";
IOBUF PORT "psram_dq[4]" IO_TYPE=LVCMOS33;
LOCATE COMP "psram_dq[5]" SITE "J18";
IOBUF PORT "psram_dq[5]" IO_TYPE=LVCMOS33;
LOCATE COMP "psram_dq[6]" SITE "J19";
IOBUF PORT "psram_dq[6]" IO_TYPE=LVCMOS33;
LOCATE COMP "psram_dq[7]" SITE "J20";
IOBUF PORT "psram_dq[7]" IO_TYPE=LVCMOS33;
LOCATE COMP "psram_dq[8]" SITE "K19";
IOBUF PORT "psram_dq[8]" IO_TYPE=LVCMOS33;
LOCATE COMP "psram_dq[9]" SITE "K20";
IOBUF PORT "psram_dq[9]" IO_TYPE=LVCMOS33;
LOCATE COMP "psram_lb_n" SITE "T16";
IOBUF PORT "psram_lb_n" IO_TYPE=LVCMOS33;
LOCATE COMP "psram_oe_n" SITE "R16";
IOBUF PORT "psram_oe_n" IO_TYPE=LVCMOS33;
LOCATE COMP "psram_ub_n" SITE "N19";
IOBUF PORT "psram_ub_n" IO_TYPE=LVCMOS33;
LOCATE COMP "psram_we_n" SITE "R17";
IOBUF PORT "psram_we_n" IO_TYPE=LVCMOS33;
LOCATE COMP "psram_zz_n" SITE "N20";
IOBUF PORT "psram_zz_n" IO_TYPE=LVCMOS33;
LOCATE COMP "rst" SITE "B4";
IOBUF PORT "rst" IO_TYPE=LVCMOS33;
LOCATE COMP "sclk" SITE "B5";
IOBUF PORT "sclk" IO_TYPE=LVCMOS33;
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