micheleandClaude Sonnet 5
55c827bedf
PSRAM page-mode read burst support in psram_controller.v: enables the ISSI IS66WVE4M16EBLL-70BLI's page mode via its configuration-register software-access sequence at boot (disabled by default on the real chip), then keeps CE#/OE# asserted after a read so a same-page continuation only pays tAPA (20ns) instead of a full tAA (70ns) random access, with automatic tCEM-safe session closing. Only a WRITE closes the page -- byte-enable changes do not, since int8_memory_access.v alternates them on nearly every access and an early implementation attempt that treated them as a close condition measured a real regression (53.25->61.25 cycles/edge) before being corrected (53.25->37.53 cycles/edge, +42% gather bandwidth). sim/psram_model.v gained independent tAPA/tAA and tCEM enforcement (with a real Verilog same-timestep event-ordering race found and fixed via a #0 sync) so the regression proves real timing compliance, not just data correctness. New sim/psram_page_mode_tb.v; full 26-file regression suite re-run clean. Real nextpnr-ecp5 Fmax re-measured on the full spi_neuron_top system: 75.73MHz (P2, up from 55.59MHz) and 65.13MHz (P8) -- still under the 80MHz target but not regressed, with the critical path confirmed (not assumed) to remain entirely inside neuron_parallel's accumulate chain, never psram_controller. Also includes this session's other already-validated work: the graph engine (Type #2 sparse-graph network: act_buffer, graph_engine, netasm host assembler), real CABGA381 pinout (.lpf, place&route verified) and physical IRQ_N/DATA_READY_N pins, and Phase 7 timing closure logs -- all previously uncommitted, documented in WORKLOG.md. Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01LH3jPeJ3eFMfF2v8SQhpkk
7186 lines
723 KiB
Plaintext
7186 lines
723 KiB
Plaintext
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/----------------------------------------------------------------------------\
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| yosys -- Yosys Open SYnthesis Suite |
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| Copyright (C) 2012 - 2026 Claire Xenia Wolf <claire@yosyshq.com> |
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| Distributed under an ISC-like license, type "license" to see terms |
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\----------------------------------------------------------------------------/
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Yosys 0.68+post (git sha1 c12172fbae8af5e20f6fb52e3d4e92d56ed587b6, Release, AppleClang clang++ 21.0.0.21000101)
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-- Executing script file `synth/ecp5/timing_closure/before/synth_p2.ys' --
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1. Executing Verilog-2005 frontend: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_slave.v
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Parsing SystemVerilog input from `/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_slave.v' to AST representation.
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Generating RTLIL representation for module `\spi_slave'.
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Successfully finished Verilog frontend.
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2. Executing Verilog-2005 frontend: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v
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Parsing SystemVerilog input from `/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v' to AST representation.
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Generating RTLIL representation for module `\spi_engine'.
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Successfully finished Verilog frontend.
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3. Executing Verilog-2005 frontend: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v
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Parsing SystemVerilog input from `/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v' to AST representation.
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Generating RTLIL representation for module `\layer_sequencer'.
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Successfully finished Verilog frontend.
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4. Executing Verilog-2005 frontend: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/act_buffer.v
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Parsing SystemVerilog input from `/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/act_buffer.v' to AST representation.
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Generating RTLIL representation for module `\act_buffer'.
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Successfully finished Verilog frontend.
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5. Executing Verilog-2005 frontend: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v
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Parsing SystemVerilog input from `/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v' to AST representation.
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Generating RTLIL representation for module `\graph_engine'.
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Successfully finished Verilog frontend.
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6. Executing Verilog-2005 frontend: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mem_arbiter.v
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Parsing SystemVerilog input from `/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mem_arbiter.v' to AST representation.
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Generating RTLIL representation for module `\mem_arbiter'.
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Successfully finished Verilog frontend.
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7. Executing Verilog-2005 frontend: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v
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Parsing SystemVerilog input from `/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v' to AST representation.
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Generating RTLIL representation for module `\neuron_memory'.
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Successfully finished Verilog frontend.
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8. Executing Verilog-2005 frontend: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/int8_memory_access.v
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Parsing SystemVerilog input from `/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/int8_memory_access.v' to AST representation.
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Generating RTLIL representation for module `\int8_memory_access'.
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Successfully finished Verilog frontend.
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9. Executing Verilog-2005 frontend: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/memory_interface.v
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Parsing SystemVerilog input from `/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/memory_interface.v' to AST representation.
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Generating RTLIL representation for module `\memory_interface'.
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Successfully finished Verilog frontend.
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10. Executing Verilog-2005 frontend: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/psram_controller.v
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Parsing SystemVerilog input from `/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/psram_controller.v' to AST representation.
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/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/psram_controller.v:93: Warning: Yosys has only limited support for tri-state logic at the moment.
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Generating RTLIL representation for module `\psram_controller'.
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Successfully finished Verilog frontend.
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11. Executing Verilog-2005 frontend: /tmp/before_rewrite/neuron_parallel.v
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Parsing SystemVerilog input from `/tmp/before_rewrite/neuron_parallel.v' to AST representation.
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Generating RTLIL representation for module `\neuron_parallel'.
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Successfully finished Verilog frontend.
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12. Executing Verilog-2005 frontend: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v
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Parsing SystemVerilog input from `/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v' to AST representation.
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Generating RTLIL representation for module `\mac8'.
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Successfully finished Verilog frontend.
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13. Executing Verilog-2005 frontend: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v
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Parsing SystemVerilog input from `/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v' to AST representation.
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Generating RTLIL representation for module `\mac_unit'.
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Successfully finished Verilog frontend.
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14. Executing Verilog-2005 frontend: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_neuron_top.v
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Parsing SystemVerilog input from `/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_neuron_top.v' to AST representation.
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Generating RTLIL representation for module `\spi_neuron_top'.
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Successfully finished Verilog frontend.
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Parameter \PARALLEL = 2
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15. Executing AST frontend in derive mode using pre-parsed AST for module `\spi_neuron_top'.
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Parameter \PARALLEL = 2
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Generating RTLIL representation for module `$paramod\spi_neuron_top\PARALLEL=s32'00000000000000000000000000000010'.
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16. Executing HIERARCHY pass (managing design hierarchy).
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16.1. Analyzing design hierarchy..
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Top module: \spi_neuron_top
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Used module: \spi_slave
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Used module: \spi_engine
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Used module: \layer_sequencer
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Used module: \graph_engine
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Used module: \neuron_parallel
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Used module: \mac8
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Used module: \mac_unit
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Used module: \act_buffer
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Used module: \neuron_memory
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Used module: \int8_memory_access
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Used module: \mem_arbiter
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Used module: \memory_interface
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Used module: \psram_controller
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Parameter \DATA_WIDTH = 8
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Parameter \N_INPUTS = 32
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Parameter \PARALLEL = 8
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Parameter \ACC_WIDTH = 32
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16.2. Executing AST frontend in derive mode using pre-parsed AST for module `\neuron_parallel'.
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Parameter \DATA_WIDTH = 8
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Parameter \N_INPUTS = 32
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Parameter \PARALLEL = 8
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Parameter \ACC_WIDTH = 32
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Generating RTLIL representation for module `$paramod$18f95495176adabb8b1efa1a4c23d17992af7212\neuron_parallel'.
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Parameter \N_TOTAL = 4096
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Parameter \DATA_WIDTH = 8
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16.3. Executing AST frontend in derive mode using pre-parsed AST for module `\act_buffer'.
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Parameter \N_TOTAL = 4096
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Parameter \DATA_WIDTH = 8
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Generating RTLIL representation for module `$paramod$c614a16d6b975c0ec2885ffa17a962bce4ddbcec\act_buffer'.
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Parameter \DATA_WIDTH = 8
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Parameter \ACC_WIDTH = 32
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Parameter \PARALLEL = 8
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16.4. Executing AST frontend in derive mode using pre-parsed AST for module `\mac8'.
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Parameter \DATA_WIDTH = 8
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Parameter \ACC_WIDTH = 32
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Parameter \PARALLEL = 8
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Generating RTLIL representation for module `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8'.
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Parameter \DATA_WIDTH = 8
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Parameter \N_INPUTS = 32
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Parameter \PARALLEL = 8
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Parameter \ACC_WIDTH = 32
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Found cached RTLIL representation for module `$paramod$18f95495176adabb8b1efa1a4c23d17992af7212\neuron_parallel'.
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Parameter \ADDR_WIDTH = 23
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16.5. Executing AST frontend in derive mode using pre-parsed AST for module `\int8_memory_access'.
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Parameter \ADDR_WIDTH = 23
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Generating RTLIL representation for module `$paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010111'.
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Parameter \DATA_WIDTH = 16
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Parameter \ACC_WIDTH = 40
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16.6. Executing AST frontend in derive mode using pre-parsed AST for module `\mac_unit'.
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Parameter \DATA_WIDTH = 16
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Parameter \ACC_WIDTH = 40
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Generating RTLIL representation for module `$paramod$913793164bb5cb5821e69ced9b7f953b27ebd911\mac_unit'.
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Parameter \DATA_WIDTH = 16
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Parameter \ACC_WIDTH = 40
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Found cached RTLIL representation for module `$paramod$913793164bb5cb5821e69ced9b7f953b27ebd911\mac_unit'.
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Parameter \DATA_WIDTH = 16
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Parameter \ACC_WIDTH = 40
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Found cached RTLIL representation for module `$paramod$913793164bb5cb5821e69ced9b7f953b27ebd911\mac_unit'.
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Parameter \DATA_WIDTH = 16
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Parameter \ACC_WIDTH = 40
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Found cached RTLIL representation for module `$paramod$913793164bb5cb5821e69ced9b7f953b27ebd911\mac_unit'.
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Parameter \DATA_WIDTH = 16
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Parameter \ACC_WIDTH = 40
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Found cached RTLIL representation for module `$paramod$913793164bb5cb5821e69ced9b7f953b27ebd911\mac_unit'.
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Parameter \DATA_WIDTH = 16
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Parameter \ACC_WIDTH = 40
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Found cached RTLIL representation for module `$paramod$913793164bb5cb5821e69ced9b7f953b27ebd911\mac_unit'.
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Parameter \DATA_WIDTH = 16
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Parameter \ACC_WIDTH = 40
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Found cached RTLIL representation for module `$paramod$913793164bb5cb5821e69ced9b7f953b27ebd911\mac_unit'.
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Parameter \DATA_WIDTH = 16
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Parameter \ACC_WIDTH = 40
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Found cached RTLIL representation for module `$paramod$913793164bb5cb5821e69ced9b7f953b27ebd911\mac_unit'.
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Reprocessing module mac8 because instantiated module mac_unit has become available.
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Generating RTLIL representation for module `\mac8'.
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Parameter \ADDR_WIDTH = 23
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Parameter \DATA_WIDTH = 8
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Parameter \N_INPUTS = 32
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Parameter \N_NEURONS = 1
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Parameter \PARALLEL = 2
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Parameter \N_TOTAL = 4096
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16.7. Executing AST frontend in derive mode using pre-parsed AST for module `\spi_engine'.
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Parameter \ADDR_WIDTH = 23
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Parameter \DATA_WIDTH = 8
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Parameter \N_INPUTS = 32
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Parameter \N_NEURONS = 1
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Parameter \PARALLEL = 2
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Parameter \N_TOTAL = 4096
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Generating RTLIL representation for module `$paramod$dd4f06a4ba98f945361f3a45f42984e592ac1bec\spi_engine'.
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Parameter \ADDR_WIDTH = 23
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Parameter \DATA_WIDTH = 8
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Parameter \N_WIDTH = 1
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Parameter \N_LAYERS = 4
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16.8. Executing AST frontend in derive mode using pre-parsed AST for module `\layer_sequencer'.
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Parameter \ADDR_WIDTH = 23
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Parameter \DATA_WIDTH = 8
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Parameter \N_WIDTH = 1
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Parameter \N_LAYERS = 4
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Generating RTLIL representation for module `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer'.
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Parameter \ADDR_WIDTH = 23
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Parameter \DATA_WIDTH = 8
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Parameter \ACC_WIDTH = 32
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Parameter \PARALLEL = 2
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Parameter \MAX_CONN = 32
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Parameter \N_TOTAL = 4096
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16.9. Executing AST frontend in derive mode using pre-parsed AST for module `\graph_engine'.
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Parameter \ADDR_WIDTH = 23
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Parameter \DATA_WIDTH = 8
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Parameter \ACC_WIDTH = 32
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Parameter \PARALLEL = 2
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Parameter \MAX_CONN = 32
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Parameter \N_TOTAL = 4096
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Generating RTLIL representation for module `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine'.
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Parameter \ADDR_WIDTH = 23
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Parameter \DATA_WIDTH = 8
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Parameter \N_INPUTS = 32
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Parameter \N_NEURONS = 1
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Parameter \PARALLEL = 2
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Parameter \ACC_WIDTH = 32
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16.10. Executing AST frontend in derive mode using pre-parsed AST for module `\neuron_memory'.
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Parameter \ADDR_WIDTH = 23
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Parameter \DATA_WIDTH = 8
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Parameter \N_INPUTS = 32
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Parameter \N_NEURONS = 1
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Parameter \PARALLEL = 2
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Parameter \ACC_WIDTH = 32
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Generating RTLIL representation for module `$paramod$80f5e68183ca7884165c68cdb28403ede9957037\neuron_memory'.
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Parameter \ADDR_WIDTH = 23
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16.11. Executing AST frontend in derive mode using pre-parsed AST for module `\mem_arbiter'.
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Parameter \ADDR_WIDTH = 23
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Generating RTLIL representation for module `$paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010111'.
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Parameter \ADDR_WIDTH = 23
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Found cached RTLIL representation for module `$paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010111'.
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Parameter \ADDR_WIDTH = 23
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Parameter \DATA_WIDTH = 16
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16.12. Executing AST frontend in derive mode using pre-parsed AST for module `\memory_interface'.
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Parameter \ADDR_WIDTH = 23
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Parameter \DATA_WIDTH = 16
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Generating RTLIL representation for module `$paramod$b3f3d2413f22d50ebc275a55cbfefa4ff7d277a1\memory_interface'.
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Parameter \ADDR_WIDTH = 23
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Parameter \DATA_WIDTH = 16
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Parameter \CLK_FREQ_MHZ = 80
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16.13. Executing AST frontend in derive mode using pre-parsed AST for module `\psram_controller'.
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Parameter \ADDR_WIDTH = 23
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Parameter \DATA_WIDTH = 16
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Parameter \CLK_FREQ_MHZ = 80
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Generating RTLIL representation for module `$paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller'.
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16.14. Analyzing design hierarchy..
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Top module: \spi_neuron_top
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Used module: \spi_slave
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Used module: $paramod$dd4f06a4ba98f945361f3a45f42984e592ac1bec\spi_engine
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Used module: $paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer
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Used module: $paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine
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Used module: \neuron_parallel
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Used module: $paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8
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Used module: \mac_unit
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Used module: \act_buffer
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Used module: $paramod$80f5e68183ca7884165c68cdb28403ede9957037\neuron_memory
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Used module: \int8_memory_access
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Used module: $paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010111
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Used module: $paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010111
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Used module: $paramod$b3f3d2413f22d50ebc275a55cbfefa4ff7d277a1\memory_interface
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Used module: $paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller
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Parameter \DATA_WIDTH = 8
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Parameter \ACC_WIDTH = 32
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16.15. Executing AST frontend in derive mode using pre-parsed AST for module `\mac_unit'.
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Parameter \DATA_WIDTH = 8
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Parameter \ACC_WIDTH = 32
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Generating RTLIL representation for module `$paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\mac_unit'.
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Parameter \DATA_WIDTH = 8
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Parameter \ACC_WIDTH = 32
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Found cached RTLIL representation for module `$paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\mac_unit'.
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Parameter \DATA_WIDTH = 8
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Parameter \ACC_WIDTH = 32
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Found cached RTLIL representation for module `$paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\mac_unit'.
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Parameter \DATA_WIDTH = 8
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Parameter \ACC_WIDTH = 32
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Found cached RTLIL representation for module `$paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\mac_unit'.
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Parameter \DATA_WIDTH = 8
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Parameter \ACC_WIDTH = 32
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Found cached RTLIL representation for module `$paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\mac_unit'.
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Parameter \DATA_WIDTH = 8
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Parameter \ACC_WIDTH = 32
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Found cached RTLIL representation for module `$paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\mac_unit'.
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Parameter \DATA_WIDTH = 8
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Parameter \ACC_WIDTH = 32
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Found cached RTLIL representation for module `$paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\mac_unit'.
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Parameter \DATA_WIDTH = 8
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Parameter \ACC_WIDTH = 32
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Found cached RTLIL representation for module `$paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\mac_unit'.
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Reprocessing module $paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8 because instantiated module $paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\mac_unit has become available.
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Generating RTLIL representation for module `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8'.
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Parameter \DATA_WIDTH = 8
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Parameter \N_INPUTS = 32
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Parameter \PARALLEL = 2
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Parameter \ACC_WIDTH = 32
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16.16. Executing AST frontend in derive mode using pre-parsed AST for module `\neuron_parallel'.
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Parameter \DATA_WIDTH = 8
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Parameter \N_INPUTS = 32
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Parameter \PARALLEL = 2
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Parameter \ACC_WIDTH = 32
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Generating RTLIL representation for module `$paramod$bcb9324e2b7cabc82145d6a09db8d736ca601b00\neuron_parallel'.
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Parameter \N_TOTAL = 4096
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Parameter \DATA_WIDTH = 8
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Found cached RTLIL representation for module `$paramod$c614a16d6b975c0ec2885ffa17a962bce4ddbcec\act_buffer'.
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Parameter \DATA_WIDTH = 8
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Parameter \N_INPUTS = 32
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Parameter \PARALLEL = 2
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Parameter \ACC_WIDTH = 32
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Found cached RTLIL representation for module `$paramod$bcb9324e2b7cabc82145d6a09db8d736ca601b00\neuron_parallel'.
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Parameter \ADDR_WIDTH = 23
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Found cached RTLIL representation for module `$paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010111'.
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16.17. Analyzing design hierarchy..
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Top module: \spi_neuron_top
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Used module: \spi_slave
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Used module: $paramod$dd4f06a4ba98f945361f3a45f42984e592ac1bec\spi_engine
|
|
Used module: $paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer
|
|
Used module: $paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine
|
|
Used module: $paramod$bcb9324e2b7cabc82145d6a09db8d736ca601b00\neuron_parallel
|
|
Used module: \mac8
|
|
Used module: \mac_unit
|
|
Used module: $paramod$c614a16d6b975c0ec2885ffa17a962bce4ddbcec\act_buffer
|
|
Used module: $paramod$80f5e68183ca7884165c68cdb28403ede9957037\neuron_memory
|
|
Used module: $paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010111
|
|
Used module: $paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010111
|
|
Used module: $paramod$b3f3d2413f22d50ebc275a55cbfefa4ff7d277a1\memory_interface
|
|
Used module: $paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller
|
|
Parameter \DATA_WIDTH = 16
|
|
Parameter \ACC_WIDTH = 40
|
|
Found cached RTLIL representation for module `$paramod$913793164bb5cb5821e69ced9b7f953b27ebd911\mac_unit'.
|
|
Parameter \DATA_WIDTH = 16
|
|
Parameter \ACC_WIDTH = 40
|
|
Found cached RTLIL representation for module `$paramod$913793164bb5cb5821e69ced9b7f953b27ebd911\mac_unit'.
|
|
Parameter \DATA_WIDTH = 16
|
|
Parameter \ACC_WIDTH = 40
|
|
Found cached RTLIL representation for module `$paramod$913793164bb5cb5821e69ced9b7f953b27ebd911\mac_unit'.
|
|
Parameter \DATA_WIDTH = 16
|
|
Parameter \ACC_WIDTH = 40
|
|
Found cached RTLIL representation for module `$paramod$913793164bb5cb5821e69ced9b7f953b27ebd911\mac_unit'.
|
|
Parameter \DATA_WIDTH = 16
|
|
Parameter \ACC_WIDTH = 40
|
|
Found cached RTLIL representation for module `$paramod$913793164bb5cb5821e69ced9b7f953b27ebd911\mac_unit'.
|
|
Parameter \DATA_WIDTH = 16
|
|
Parameter \ACC_WIDTH = 40
|
|
Found cached RTLIL representation for module `$paramod$913793164bb5cb5821e69ced9b7f953b27ebd911\mac_unit'.
|
|
Parameter \DATA_WIDTH = 16
|
|
Parameter \ACC_WIDTH = 40
|
|
Found cached RTLIL representation for module `$paramod$913793164bb5cb5821e69ced9b7f953b27ebd911\mac_unit'.
|
|
Parameter \DATA_WIDTH = 16
|
|
Parameter \ACC_WIDTH = 40
|
|
Found cached RTLIL representation for module `$paramod$913793164bb5cb5821e69ced9b7f953b27ebd911\mac_unit'.
|
|
Parameter \DATA_WIDTH = 8
|
|
Parameter \ACC_WIDTH = 32
|
|
Parameter \PARALLEL = 2
|
|
|
|
16.18. Executing AST frontend in derive mode using pre-parsed AST for module `\mac8'.
|
|
Parameter \DATA_WIDTH = 8
|
|
Parameter \ACC_WIDTH = 32
|
|
Parameter \PARALLEL = 2
|
|
Generating RTLIL representation for module `$paramod$8f592f3125e8f7c96bc997ed58933554526412a5\mac8'.
|
|
|
|
16.19. Analyzing design hierarchy..
|
|
Top module: \spi_neuron_top
|
|
Used module: \spi_slave
|
|
Used module: $paramod$dd4f06a4ba98f945361f3a45f42984e592ac1bec\spi_engine
|
|
Used module: $paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer
|
|
Used module: $paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine
|
|
Used module: $paramod$bcb9324e2b7cabc82145d6a09db8d736ca601b00\neuron_parallel
|
|
Used module: $paramod$8f592f3125e8f7c96bc997ed58933554526412a5\mac8
|
|
Used module: \mac_unit
|
|
Used module: $paramod$c614a16d6b975c0ec2885ffa17a962bce4ddbcec\act_buffer
|
|
Used module: $paramod$80f5e68183ca7884165c68cdb28403ede9957037\neuron_memory
|
|
Used module: $paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010111
|
|
Used module: $paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010111
|
|
Used module: $paramod$b3f3d2413f22d50ebc275a55cbfefa4ff7d277a1\memory_interface
|
|
Used module: $paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller
|
|
Parameter \DATA_WIDTH = 8
|
|
Parameter \ACC_WIDTH = 32
|
|
Found cached RTLIL representation for module `$paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\mac_unit'.
|
|
Parameter \DATA_WIDTH = 8
|
|
Parameter \ACC_WIDTH = 32
|
|
Found cached RTLIL representation for module `$paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\mac_unit'.
|
|
|
|
16.20. Analyzing design hierarchy..
|
|
Top module: \spi_neuron_top
|
|
Used module: \spi_slave
|
|
Used module: $paramod$dd4f06a4ba98f945361f3a45f42984e592ac1bec\spi_engine
|
|
Used module: $paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer
|
|
Used module: $paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine
|
|
Used module: $paramod$bcb9324e2b7cabc82145d6a09db8d736ca601b00\neuron_parallel
|
|
Used module: $paramod$8f592f3125e8f7c96bc997ed58933554526412a5\mac8
|
|
Used module: $paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\mac_unit
|
|
Used module: $paramod$c614a16d6b975c0ec2885ffa17a962bce4ddbcec\act_buffer
|
|
Used module: $paramod$80f5e68183ca7884165c68cdb28403ede9957037\neuron_memory
|
|
Used module: $paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010111
|
|
Used module: $paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010111
|
|
Used module: $paramod$b3f3d2413f22d50ebc275a55cbfefa4ff7d277a1\memory_interface
|
|
Used module: $paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller
|
|
|
|
16.21. Analyzing design hierarchy..
|
|
Top module: \spi_neuron_top
|
|
Used module: \spi_slave
|
|
Used module: $paramod$dd4f06a4ba98f945361f3a45f42984e592ac1bec\spi_engine
|
|
Used module: $paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer
|
|
Used module: $paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine
|
|
Used module: $paramod$bcb9324e2b7cabc82145d6a09db8d736ca601b00\neuron_parallel
|
|
Used module: $paramod$8f592f3125e8f7c96bc997ed58933554526412a5\mac8
|
|
Used module: $paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\mac_unit
|
|
Used module: $paramod$c614a16d6b975c0ec2885ffa17a962bce4ddbcec\act_buffer
|
|
Used module: $paramod$80f5e68183ca7884165c68cdb28403ede9957037\neuron_memory
|
|
Used module: $paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010111
|
|
Used module: $paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010111
|
|
Used module: $paramod$b3f3d2413f22d50ebc275a55cbfefa4ff7d277a1\memory_interface
|
|
Used module: $paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller
|
|
Removing unused module `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8'.
|
|
Removing unused module `\mac8'.
|
|
Removing unused module `$paramod$18f95495176adabb8b1efa1a4c23d17992af7212\neuron_parallel'.
|
|
Removing unused module `\mac_unit'.
|
|
Removing unused module `$paramod$913793164bb5cb5821e69ced9b7f953b27ebd911\mac_unit'.
|
|
Removing unused module `\neuron_parallel'.
|
|
Removing unused module `\psram_controller'.
|
|
Removing unused module `\memory_interface'.
|
|
Removing unused module `\int8_memory_access'.
|
|
Removing unused module `\neuron_memory'.
|
|
Removing unused module `\mem_arbiter'.
|
|
Removing unused module `\graph_engine'.
|
|
Removing unused module `\act_buffer'.
|
|
Removing unused module `\layer_sequencer'.
|
|
Removing unused module `\spi_engine'.
|
|
Removed 15 unused modules.
|
|
|
|
17. Executing SYNTH_LATTICE pass.
|
|
|
|
17.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v
|
|
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v' to AST representation.
|
|
Generating RTLIL representation for module `\LUT4'.
|
|
Generating RTLIL representation for module `\$__ABC9_LUT5'.
|
|
Generating RTLIL representation for module `\$__ABC9_LUT6'.
|
|
Generating RTLIL representation for module `\$__ABC9_LUT7'.
|
|
Generating RTLIL representation for module `\L6MUX21'.
|
|
Generating RTLIL representation for module `\TRELLIS_RAM16X2'.
|
|
Generating RTLIL representation for module `\PFUMX'.
|
|
Generating RTLIL representation for module `\TRELLIS_DPR16X4'.
|
|
Generating RTLIL representation for module `\DPR16X4C'.
|
|
Generating RTLIL representation for module `\LUT2'.
|
|
Generating RTLIL representation for module `\TRELLIS_FF'.
|
|
Generating RTLIL representation for module `\TRELLIS_IO'.
|
|
Generating RTLIL representation for module `\INV'.
|
|
Generating RTLIL representation for module `\TRELLIS_COMB'.
|
|
Generating RTLIL representation for module `\VLO'.
|
|
Generating RTLIL representation for module `\VHI'.
|
|
Generating RTLIL representation for module `\FD1P3AX'.
|
|
Generating RTLIL representation for module `\FD1P3AY'.
|
|
Generating RTLIL representation for module `\FD1P3BX'.
|
|
Generating RTLIL representation for module `\FD1P3DX'.
|
|
Generating RTLIL representation for module `\FD1P3IX'.
|
|
Generating RTLIL representation for module `\FD1P3JX'.
|
|
Generating RTLIL representation for module `\FD1S3AX'.
|
|
Generating RTLIL representation for module `\FD1S3AY'.
|
|
Generating RTLIL representation for module `\FD1S3BX'.
|
|
Generating RTLIL representation for module `\FD1S3DX'.
|
|
Generating RTLIL representation for module `\FD1S3IX'.
|
|
Generating RTLIL representation for module `\FD1S3JX'.
|
|
Generating RTLIL representation for module `\IFS1P3BX'.
|
|
Generating RTLIL representation for module `\IFS1P3DX'.
|
|
Generating RTLIL representation for module `\IFS1P3IX'.
|
|
Generating RTLIL representation for module `\IFS1P3JX'.
|
|
Generating RTLIL representation for module `\OFS1P3BX'.
|
|
Generating RTLIL representation for module `\OFS1P3DX'.
|
|
Generating RTLIL representation for module `\OFS1P3IX'.
|
|
Generating RTLIL representation for module `\OFS1P3JX'.
|
|
Generating RTLIL representation for module `\IB'.
|
|
Generating RTLIL representation for module `\IBPU'.
|
|
Generating RTLIL representation for module `\IBPD'.
|
|
Generating RTLIL representation for module `\OB'.
|
|
Generating RTLIL representation for module `\OBZ'.
|
|
Generating RTLIL representation for module `\OBZPU'.
|
|
Generating RTLIL representation for module `\OBZPD'.
|
|
Generating RTLIL representation for module `\OBCO'.
|
|
Generating RTLIL representation for module `\BB'.
|
|
Generating RTLIL representation for module `\BBPU'.
|
|
Generating RTLIL representation for module `\BBPD'.
|
|
Generating RTLIL representation for module `\ILVDS'.
|
|
Generating RTLIL representation for module `\OLVDS'.
|
|
Generating RTLIL representation for module `\CCU2C'.
|
|
Generating RTLIL representation for module `\DP16KD'.
|
|
Replacing existing blackbox module `\FD1P3AX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:2.1-2.261.
|
|
Generating RTLIL representation for module `\FD1P3AX'.
|
|
Replacing existing blackbox module `\FD1P3AY' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:3.1-3.261.
|
|
Generating RTLIL representation for module `\FD1P3AY'.
|
|
Replacing existing blackbox module `\FD1P3BX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:4.1-4.261.
|
|
Generating RTLIL representation for module `\FD1P3BX'.
|
|
Replacing existing blackbox module `\FD1P3DX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:5.1-5.261.
|
|
Generating RTLIL representation for module `\FD1P3DX'.
|
|
Replacing existing blackbox module `\FD1P3IX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:6.1-6.261.
|
|
Generating RTLIL representation for module `\FD1P3IX'.
|
|
Replacing existing blackbox module `\FD1P3JX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:7.1-7.261.
|
|
Generating RTLIL representation for module `\FD1P3JX'.
|
|
Replacing existing blackbox module `\FD1S3AX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:8.1-8.261.
|
|
Generating RTLIL representation for module `\FD1S3AX'.
|
|
Replacing existing blackbox module `\FD1S3AY' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:9.1-9.261.
|
|
Generating RTLIL representation for module `\FD1S3AY'.
|
|
Replacing existing blackbox module `\FD1S3BX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:10.1-10.261.
|
|
Generating RTLIL representation for module `\FD1S3BX'.
|
|
Replacing existing blackbox module `\FD1S3DX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:11.1-11.261.
|
|
Generating RTLIL representation for module `\FD1S3DX'.
|
|
Replacing existing blackbox module `\FD1S3IX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:12.1-12.261.
|
|
Generating RTLIL representation for module `\FD1S3IX'.
|
|
Replacing existing blackbox module `\FD1S3JX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:13.1-13.261.
|
|
Generating RTLIL representation for module `\FD1S3JX'.
|
|
Replacing existing blackbox module `\IFS1P3BX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:26.1-26.301.
|
|
Generating RTLIL representation for module `\IFS1P3BX'.
|
|
Replacing existing blackbox module `\IFS1P3DX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:27.1-27.301.
|
|
Generating RTLIL representation for module `\IFS1P3DX'.
|
|
Replacing existing blackbox module `\IFS1P3IX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:28.1-28.301.
|
|
Generating RTLIL representation for module `\IFS1P3IX'.
|
|
Replacing existing blackbox module `\IFS1P3JX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:29.1-29.301.
|
|
Generating RTLIL representation for module `\IFS1P3JX'.
|
|
Replacing existing blackbox module `\OFS1P3BX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:31.1-31.302.
|
|
Generating RTLIL representation for module `\OFS1P3BX'.
|
|
Replacing existing blackbox module `\OFS1P3DX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:32.1-32.302.
|
|
Generating RTLIL representation for module `\OFS1P3DX'.
|
|
Replacing existing blackbox module `\OFS1P3IX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:33.1-33.302.
|
|
Generating RTLIL representation for module `\OFS1P3IX'.
|
|
Replacing existing blackbox module `\OFS1P3JX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:34.1-34.302.
|
|
Generating RTLIL representation for module `\OFS1P3JX'.
|
|
Replacing existing blackbox module `\IB' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:2.1-2.157.
|
|
Generating RTLIL representation for module `\IB'.
|
|
Replacing existing blackbox module `\IBPU' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:3.1-3.157.
|
|
Generating RTLIL representation for module `\IBPU'.
|
|
Replacing existing blackbox module `\IBPD' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:4.1-4.157.
|
|
Generating RTLIL representation for module `\IBPD'.
|
|
Replacing existing blackbox module `\OB' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:5.1-5.157.
|
|
Generating RTLIL representation for module `\OB'.
|
|
Replacing existing blackbox module `\OBZ' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:6.1-6.164.
|
|
Generating RTLIL representation for module `\OBZ'.
|
|
Replacing existing blackbox module `\OBZPU' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:7.1-7.164.
|
|
Generating RTLIL representation for module `\OBZPU'.
|
|
Replacing existing blackbox module `\OBZPD' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:8.1-8.164.
|
|
Generating RTLIL representation for module `\OBZPD'.
|
|
Replacing existing blackbox module `\OBCO' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:9.1-9.90.
|
|
Generating RTLIL representation for module `\OBCO'.
|
|
Replacing existing blackbox module `\BB' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:10.1-10.179.
|
|
Generating RTLIL representation for module `\BB'.
|
|
Replacing existing blackbox module `\BBPU' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:11.1-11.179.
|
|
Generating RTLIL representation for module `\BBPU'.
|
|
Replacing existing blackbox module `\BBPD' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:12.1-12.179.
|
|
Generating RTLIL representation for module `\BBPD'.
|
|
Replacing existing blackbox module `\ILVDS' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:13.1-13.139.
|
|
Generating RTLIL representation for module `\ILVDS'.
|
|
Replacing existing blackbox module `\OLVDS' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:14.1-14.146.
|
|
Generating RTLIL representation for module `\OLVDS'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
17.2. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v
|
|
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v' to AST representation.
|
|
Generating RTLIL representation for module `\GSR'.
|
|
Generating RTLIL representation for module `\PUR'.
|
|
Generating RTLIL representation for module `\SGSR'.
|
|
Generating RTLIL representation for module `\PDPW16KD'.
|
|
Generating RTLIL representation for module `\MULT18X18D'.
|
|
Generating RTLIL representation for module `\ALU54B'.
|
|
Generating RTLIL representation for module `\CLKDIVF'.
|
|
Generating RTLIL representation for module `\PCSCLKDIV'.
|
|
Generating RTLIL representation for module `\DCSC'.
|
|
Generating RTLIL representation for module `\DCCA'.
|
|
Generating RTLIL representation for module `\ECLKSYNCB'.
|
|
Generating RTLIL representation for module `\ECLKBRIDGECS'.
|
|
Generating RTLIL representation for module `\DELAYF'.
|
|
Generating RTLIL representation for module `\DELAYG'.
|
|
Generating RTLIL representation for module `\USRMCLK'.
|
|
Generating RTLIL representation for module `\DQSBUFM'.
|
|
Generating RTLIL representation for module `\DDRDLLA'.
|
|
Generating RTLIL representation for module `\DLLDELD'.
|
|
Generating RTLIL representation for module `\IDDRX1F'.
|
|
Generating RTLIL representation for module `\IDDRX2F'.
|
|
Generating RTLIL representation for module `\IDDR71B'.
|
|
Generating RTLIL representation for module `\IDDRX2DQA'.
|
|
Generating RTLIL representation for module `\ODDRX1F'.
|
|
Generating RTLIL representation for module `\ODDRX2F'.
|
|
Generating RTLIL representation for module `\ODDR71B'.
|
|
Generating RTLIL representation for module `\OSHX2A'.
|
|
Generating RTLIL representation for module `\TSHX2DQA'.
|
|
Generating RTLIL representation for module `\TSHX2DQSA'.
|
|
Generating RTLIL representation for module `\ODDRX2DQA'.
|
|
Generating RTLIL representation for module `\ODDRX2DQSB'.
|
|
Generating RTLIL representation for module `\EHXPLLL'.
|
|
Generating RTLIL representation for module `\DTR'.
|
|
Generating RTLIL representation for module `\OSCG'.
|
|
Generating RTLIL representation for module `\EXTREFB'.
|
|
Generating RTLIL representation for module `\JTAGG'.
|
|
Generating RTLIL representation for module `\DCUA'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
17.3. Executing HIERARCHY pass (managing design hierarchy).
|
|
|
|
17.3.1. Analyzing design hierarchy..
|
|
Top module: \spi_neuron_top
|
|
Used module: \spi_slave
|
|
Used module: $paramod$dd4f06a4ba98f945361f3a45f42984e592ac1bec\spi_engine
|
|
Used module: $paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer
|
|
Used module: $paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine
|
|
Used module: $paramod$bcb9324e2b7cabc82145d6a09db8d736ca601b00\neuron_parallel
|
|
Used module: $paramod$8f592f3125e8f7c96bc997ed58933554526412a5\mac8
|
|
Used module: $paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\mac_unit
|
|
Used module: $paramod$c614a16d6b975c0ec2885ffa17a962bce4ddbcec\act_buffer
|
|
Used module: $paramod$80f5e68183ca7884165c68cdb28403ede9957037\neuron_memory
|
|
Used module: $paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010111
|
|
Used module: $paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010111
|
|
Used module: $paramod$b3f3d2413f22d50ebc275a55cbfefa4ff7d277a1\memory_interface
|
|
Used module: $paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller
|
|
|
|
17.3.2. Analyzing design hierarchy..
|
|
Top module: \spi_neuron_top
|
|
Used module: \spi_slave
|
|
Used module: $paramod$dd4f06a4ba98f945361f3a45f42984e592ac1bec\spi_engine
|
|
Used module: $paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer
|
|
Used module: $paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine
|
|
Used module: $paramod$bcb9324e2b7cabc82145d6a09db8d736ca601b00\neuron_parallel
|
|
Used module: $paramod$8f592f3125e8f7c96bc997ed58933554526412a5\mac8
|
|
Used module: $paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\mac_unit
|
|
Used module: $paramod$c614a16d6b975c0ec2885ffa17a962bce4ddbcec\act_buffer
|
|
Used module: $paramod$80f5e68183ca7884165c68cdb28403ede9957037\neuron_memory
|
|
Used module: $paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010111
|
|
Used module: $paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010111
|
|
Used module: $paramod$b3f3d2413f22d50ebc275a55cbfefa4ff7d277a1\memory_interface
|
|
Used module: $paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller
|
|
Removed 0 unused modules.
|
|
|
|
17.4. Executing PROC pass (convert processes to netlists).
|
|
|
|
17.4.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
|
|
Cleaned up 0 empty switches.
|
|
|
|
17.4.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
|
|
Marked 2 switch rules as full_case in process $proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/memory_interface.v:33$1239 in module $paramod$b3f3d2413f22d50ebc275a55cbfefa4ff7d277a1\memory_interface.
|
|
Removed 1 dead cases from process $proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mem_arbiter.v:90$1238 in module $paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010111.
|
|
Marked 4 switch rules as full_case in process $proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mem_arbiter.v:90$1238 in module $paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010111.
|
|
Marked 8 switch rules as full_case in process $proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:283$1118 in module $paramod$80f5e68183ca7884165c68cdb28403ede9957037\neuron_memory.
|
|
Marked 11 switch rules as full_case in process $proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$869 in module $paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.
|
|
Marked 5 switch rules as full_case in process $proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:137$780 in module $paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.
|
|
Marked 13 switch rules as full_case in process $proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:315$760 in module $paramod$dd4f06a4ba98f945361f3a45f42984e592ac1bec\spi_engine.
|
|
Marked 4 switch rules as full_case in process $proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:263$755 in module $paramod$dd4f06a4ba98f945361f3a45f42984e592ac1bec\spi_engine.
|
|
Marked 3 switch rules as full_case in process $proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:242$753 in module $paramod$dd4f06a4ba98f945361f3a45f42984e592ac1bec\spi_engine.
|
|
Marked 6 switch rules as full_case in process $proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/psram_controller.v:99$1242 in module $paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller.
|
|
Marked 4 switch rules as full_case in process $proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/int8_memory_access.v:55$676 in module $paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010111.
|
|
Marked 1 switch rules as full_case in process $proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/act_buffer.v:55$644 in module $paramod$c614a16d6b975c0ec2885ffa17a962bce4ddbcec\act_buffer.
|
|
Marked 8 switch rules as full_case in process $proc$/tmp/before_rewrite/neuron_parallel.v:130$1324 in module $paramod$bcb9324e2b7cabc82145d6a09db8d736ca601b00\neuron_parallel.
|
|
Marked 6 switch rules as full_case in process $proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_slave.v:119$12 in module spi_slave.
|
|
Marked 1 switch rules as full_case in process $proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_slave.v:93$2 in module spi_slave.
|
|
Marked 1 switch rules as full_case in process $proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_slave.v:71$1 in module spi_slave.
|
|
Removed a total of 1 dead cases.
|
|
|
|
17.4.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
|
|
Removed 40 redundant assignments.
|
|
Promoted 92 assignments to connections.
|
|
|
|
17.4.4. Executing PROC_INIT pass (extract init attributes).
|
|
|
|
17.4.5. Executing PROC_ARST pass (detect async resets in processes).
|
|
|
|
17.4.6. Executing PROC_ROM pass (convert switches to ROMs).
|
|
Converted 1 switch.
|
|
<suppressed ~121 debug messages>
|
|
|
|
17.4.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
|
|
Creating decoders for process `$paramod$b3f3d2413f22d50ebc275a55cbfefa4ff7d277a1\memory_interface.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/memory_interface.v:33$1239'.
|
|
1/9: $0\mem_req[0:0]
|
|
2/9: $0\ready[0:0]
|
|
3/9: $0\mem_ub_n[0:0]
|
|
4/9: $0\mem_lb_n[0:0]
|
|
5/9: $0\rdata[15:0]
|
|
6/9: $0\mem_wdata[15:0]
|
|
7/9: $0\mem_addr[22:0]
|
|
8/9: $0\mem_wr[0:0]
|
|
9/9: $0\state[1:0]
|
|
Creating decoders for process `$paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010111.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mem_arbiter.v:90$1238'.
|
|
1/11: $0\c_ready[0:0]
|
|
2/11: $0\b_ready[0:0]
|
|
3/11: $0\a_ready[0:0]
|
|
4/11: $0\m_req[0:0]
|
|
5/11: $0\owner[1:0]
|
|
6/11: $0\m_wdata[7:0]
|
|
7/11: $0\m_addr[22:0]
|
|
8/11: $0\m_wr[0:0]
|
|
9/11: $0\c_rdata[7:0]
|
|
10/11: $0\b_rdata[7:0]
|
|
11/11: $0\a_rdata[7:0]
|
|
Creating decoders for process `$paramod$80f5e68183ca7884165c68cdb28403ede9957037\neuron_memory.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:283$1118'.
|
|
1/42: $3$memwr$\y_reg$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:449$1116_EN[7:0]$1166
|
|
2/42: $3$memwr$\y_reg$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:449$1116_DATA[7:0]$1165
|
|
3/42: $3$memwr$\y_reg$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:449$1116_ADDR[0:0]$1164
|
|
4/42: $3$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:390$1115_EN[7:0]$1158
|
|
5/42: $3$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:390$1115_DATA[7:0]$1157
|
|
6/42: $3$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:390$1115_ADDR[5:0]$1156
|
|
7/42: $3$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:357$1114_EN[7:0]$1150
|
|
8/42: $3$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:357$1114_DATA[7:0]$1149
|
|
9/42: $3$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:357$1114_ADDR[5:0]$1148
|
|
10/42: $2$memwr$\y_reg$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:449$1116_EN[7:0]$1147
|
|
11/42: $2$memwr$\y_reg$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:449$1116_DATA[7:0]$1146
|
|
12/42: $2$memwr$\y_reg$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:449$1116_ADDR[0:0]$1145
|
|
13/42: $2$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:390$1115_EN[7:0]$1144
|
|
14/42: $2$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:390$1115_DATA[7:0]$1143
|
|
15/42: $2$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:390$1115_ADDR[5:0]$1142
|
|
16/42: $2$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:357$1114_EN[7:0]$1141
|
|
17/42: $2$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:357$1114_DATA[7:0]$1140
|
|
18/42: $2$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:357$1114_ADDR[5:0]$1139
|
|
19/42: $0\done[0:0]
|
|
20/42: $1\rst_i[31:0]
|
|
21/42: $1$memwr$\y_reg$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:304$1113_EN[7:0]$1129
|
|
22/42: $0\neuron_start[0:0]
|
|
23/42: $0\access_req[0:0]
|
|
24/42: $1$memwr$\y_reg$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:449$1116_EN[7:0]$1138
|
|
25/42: $1$memwr$\y_reg$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:449$1116_DATA[7:0]$1137
|
|
26/42: $1$memwr$\y_reg$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:449$1116_ADDR[0:0]$1136
|
|
27/42: $1$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:390$1115_EN[7:0]$1135
|
|
28/42: $1$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:390$1115_DATA[7:0]$1134
|
|
29/42: $1$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:390$1115_ADDR[5:0]$1133
|
|
30/42: $1$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:357$1114_EN[7:0]$1132
|
|
31/42: $1$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:357$1114_DATA[7:0]$1131
|
|
32/42: $1$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:357$1114_ADDR[5:0]$1130
|
|
33/42: $0\access_wdata[7:0]
|
|
34/42: $0\access_addr[22:0]
|
|
35/42: $0\access_wr[0:0]
|
|
36/42: $0\bias_group_addr[22:0]
|
|
37/42: $0\w_group_base[22:0]
|
|
38/42: $0\neuron_index[0:0]
|
|
39/42: $0\index[5:0]
|
|
40/42: $0\bias_reg[7:0]
|
|
41/42: $0\busy[0:0]
|
|
42/42: $0\state[3:0]
|
|
Creating decoders for process `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$869'.
|
|
1/108: $0\src_id_acc[15:0] [15:8]
|
|
2/108: $0\src_id_acc[15:0] [7:0]
|
|
3/108: $0\out_id_acc[15:0] [7:0]
|
|
4/108: $0\n_conn_acc[15:0] [7:0]
|
|
5/108: $0\conn_ptr_acc[23:0] [7:0]
|
|
6/108: $0\conn_ptr_acc[23:0] [23:16]
|
|
7/108: $2$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:496$865_DATA[7:0]$1014
|
|
8/108: $2$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:496$865_ADDR[5:0]$1013
|
|
9/108: $2$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:495$864_EN[7:0]$1012
|
|
10/108: $2$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:495$864_DATA[7:0]$1011
|
|
11/108: $2$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:495$864_ADDR[5:0]$1010
|
|
12/108: $1\ri[31:0]
|
|
13/108: $1$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$863_EN[7:0]$1003
|
|
14/108: $1$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$862_EN[7:0]$1002
|
|
15/108: $1$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$861_EN[7:0]$1001
|
|
16/108: $1$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$860_EN[7:0]$1000
|
|
17/108: $1$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$859_EN[7:0]$999
|
|
18/108: $1$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$858_EN[7:0]$998
|
|
19/108: $1$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$857_EN[7:0]$997
|
|
20/108: $1$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$856_EN[7:0]$996
|
|
21/108: $1$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$855_EN[7:0]$995
|
|
22/108: $1$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$854_EN[7:0]$994
|
|
23/108: $1$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$853_EN[7:0]$993
|
|
24/108: $1$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$852_EN[7:0]$992
|
|
25/108: $1$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$851_EN[7:0]$991
|
|
26/108: $1$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$850_EN[7:0]$990
|
|
27/108: $1$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$849_EN[7:0]$989
|
|
28/108: $1$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$848_EN[7:0]$988
|
|
29/108: $1$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$847_EN[7:0]$987
|
|
30/108: $1$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$846_EN[7:0]$986
|
|
31/108: $1$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$845_EN[7:0]$985
|
|
32/108: $1$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$844_EN[7:0]$984
|
|
33/108: $1$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$843_EN[7:0]$983
|
|
34/108: $1$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$842_EN[7:0]$982
|
|
35/108: $1$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$841_EN[7:0]$981
|
|
36/108: $1$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$840_EN[7:0]$980
|
|
37/108: $1$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$839_EN[7:0]$979
|
|
38/108: $1$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$838_EN[7:0]$978
|
|
39/108: $1$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$837_EN[7:0]$977
|
|
40/108: $1$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$836_EN[7:0]$976
|
|
41/108: $1$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$835_EN[7:0]$975
|
|
42/108: $1$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$834_EN[7:0]$974
|
|
43/108: $1$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$833_EN[7:0]$973
|
|
44/108: $1$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$832_EN[7:0]$972
|
|
45/108: $1$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$831_EN[7:0]$971
|
|
46/108: $1$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$830_EN[7:0]$970
|
|
47/108: $1$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$829_EN[7:0]$969
|
|
48/108: $1$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$828_EN[7:0]$968
|
|
49/108: $1$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$827_EN[7:0]$967
|
|
50/108: $1$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$826_EN[7:0]$966
|
|
51/108: $1$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$825_EN[7:0]$965
|
|
52/108: $1$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$824_EN[7:0]$964
|
|
53/108: $1$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$823_EN[7:0]$963
|
|
54/108: $1$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$822_EN[7:0]$962
|
|
55/108: $1$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$821_EN[7:0]$961
|
|
56/108: $1$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$820_EN[7:0]$960
|
|
57/108: $1$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$819_EN[7:0]$959
|
|
58/108: $1$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$818_EN[7:0]$958
|
|
59/108: $1$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$817_EN[7:0]$957
|
|
60/108: $1$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$816_EN[7:0]$956
|
|
61/108: $1$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$815_EN[7:0]$955
|
|
62/108: $1$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$814_EN[7:0]$954
|
|
63/108: $1$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$813_EN[7:0]$953
|
|
64/108: $1$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$812_EN[7:0]$952
|
|
65/108: $1$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$811_EN[7:0]$951
|
|
66/108: $1$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$810_EN[7:0]$950
|
|
67/108: $1$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$809_EN[7:0]$949
|
|
68/108: $1$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$808_EN[7:0]$948
|
|
69/108: $1$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$807_EN[7:0]$947
|
|
70/108: $1$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$806_EN[7:0]$946
|
|
71/108: $1$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$805_EN[7:0]$945
|
|
72/108: $1$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$804_EN[7:0]$944
|
|
73/108: $1$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$803_EN[7:0]$943
|
|
74/108: $1$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$802_EN[7:0]$942
|
|
75/108: $1$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$801_EN[7:0]$941
|
|
76/108: $1$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$800_EN[7:0]$940
|
|
77/108: $0\ram_req[0:0]
|
|
78/108: $0\neuron_start[0:0]
|
|
79/108: $0\act_wr_en[0:0]
|
|
80/108: $0\done[0:0]
|
|
81/108: $1$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:496$865_EN[7:0]$1009
|
|
82/108: $1$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:496$865_DATA[7:0]$1008
|
|
83/108: $1$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:496$865_ADDR[5:0]$1007
|
|
84/108: $1$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:495$864_EN[7:0]$1006
|
|
85/108: $1$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:495$864_DATA[7:0]$1005
|
|
86/108: $1$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:495$864_ADDR[5:0]$1004
|
|
87/108: $0\n_conn_padded_reg[15:0]
|
|
88/108: $0\activation_reg[1:0]
|
|
89/108: $0\bias_reg[7:0]
|
|
90/108: $0\act_wr_data[7:0]
|
|
91/108: $0\act_wr_addr[11:0]
|
|
92/108: $0\weight_acc[7:0]
|
|
93/108: $0\out_id_acc[15:0] [15:8]
|
|
94/108: $0\edge_byte_idx[1:0]
|
|
95/108: $0\conn_i[5:0]
|
|
96/108: $0\n_conn_acc[15:0] [15:8]
|
|
97/108: $0\conn_ptr_acc[23:0] [15:8]
|
|
98/108: $2$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:496$865_EN[7:0]$1015
|
|
99/108: $0\desc_addr[22:0]
|
|
100/108: $0\neuron_idx[15:0]
|
|
101/108: $0\in_idx[15:0]
|
|
102/108: $0\err[0:0]
|
|
103/108: $0\busy[0:0]
|
|
104/108: $0\desc_byte_idx[3:0]
|
|
105/108: $0\state[3:0]
|
|
106/108: $0\ram_wdata[7:0]
|
|
107/108: $0\ram_addr[22:0]
|
|
108/108: $0\ram_wr[0:0]
|
|
Creating decoders for process `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:137$780'.
|
|
1/32: $0\n_neurons_acc[15:0] [15:8]
|
|
2/32: $0\n_neurons_acc[15:0] [7:0]
|
|
3/32: $0\n_inputs_acc[15:0] [7:0]
|
|
4/32: $0\bias_addr_acc[23:0] [7:0]
|
|
5/32: $0\bias_addr_acc[23:0] [23:16]
|
|
6/32: $0\w_base_acc[23:0] [7:0]
|
|
7/32: $0\w_base_acc[23:0] [23:16]
|
|
8/32: $0\ram_req[0:0]
|
|
9/32: $0\nm_start[0:0]
|
|
10/32: $0\copy_idx[0:0]
|
|
11/32: $0\write_sel[0:0]
|
|
12/32: $0\cur_sel[0:0]
|
|
13/32: $0\n_inputs_acc[15:0] [15:8]
|
|
14/32: $0\bias_addr_acc[23:0] [15:8]
|
|
15/32: $0\activation_acc[7:0]
|
|
16/32: $0\w_base_acc[23:0] [15:8]
|
|
17/32: $0\seq_done[0:0]
|
|
18/32: $0\desc_byte_idx[3:0]
|
|
19/32: $0\desc_table_addr[22:0]
|
|
20/32: $0\num_layers_reg[7:0]
|
|
21/32: $0\layer_idx[7:0]
|
|
22/32: $0\nm_n_neurons[15:0]
|
|
23/32: $0\nm_n_inputs[15:0]
|
|
24/32: $0\nm_activation[1:0]
|
|
25/32: $0\nm_bias_addr[22:0]
|
|
26/32: $0\nm_w_base[22:0]
|
|
27/32: $0\nm_x_base[22:0]
|
|
28/32: $0\state[3:0]
|
|
29/32: $0\seq_busy[0:0]
|
|
30/32: $0\ram_wdata[7:0]
|
|
31/32: $0\ram_addr[22:0]
|
|
32/32: $0\ram_wr[0:0]
|
|
Creating decoders for process `$paramod$dd4f06a4ba98f945361f3a45f42984e592ac1bec\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:315$760'.
|
|
1/36: $0\len_acc[15:0] [15:8]
|
|
2/36: $0\len_acc[15:0] [7:0]
|
|
3/36: $0\nm_soft_rst[0:0]
|
|
4/36: $0\nm_start[0:0]
|
|
5/36: $0\ram_req[0:0]
|
|
6/36: $0\status_snapshot[7:0]
|
|
7/36: $0\graph_mode[0:0]
|
|
8/36: $0\net_mode[0:0]
|
|
9/36: $0\resp_len[3:0]
|
|
10/36: $0\resp_index[3:0]
|
|
11/36: $0\cur_read_byte[7:0]
|
|
12/36: $0\pending_wdata[7:0]
|
|
13/36: $0\pending_write[0:0]
|
|
14/36: $0\cur_addr[22:0]
|
|
15/36: $0\len_remaining[15:0]
|
|
16/36: $0\run_start[0:0]
|
|
17/36: $0\addr_acc[23:0]
|
|
18/36: $0\byte_pos[1:0]
|
|
19/36: $0\opcode[7:0]
|
|
20/36: $0\state[3:0]
|
|
21/36: $0\n_out[15:0]
|
|
22/36: $0\num_neurons_graph[15:0]
|
|
23/36: $0\net_type[7:0]
|
|
24/36: $0\run_num_layers[7:0]
|
|
25/36: $0\buf_b_base[22:0]
|
|
26/36: $0\buf_a_base[22:0]
|
|
27/36: $0\table_base[22:0]
|
|
28/36: $0\n_neurons_real[15:0]
|
|
29/36: $0\n_inputs_real[15:0]
|
|
30/36: $0\activation[1:0]
|
|
31/36: $0\bias_addr[22:0]
|
|
32/36: $0\w_base[22:0]
|
|
33/36: $0\x_base[22:0]
|
|
34/36: $0\ram_wdata[7:0]
|
|
35/36: $0\ram_addr[22:0]
|
|
36/36: $0\ram_wr[0:0]
|
|
Creating decoders for process `$paramod$dd4f06a4ba98f945361f3a45f42984e592ac1bec\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:263$755'.
|
|
1/4: $4\tx_byte_comb[7:0]
|
|
2/4: $3\tx_byte_comb[7:0]
|
|
3/4: $2\tx_byte_comb[7:0]
|
|
4/4: $1\tx_byte_comb[7:0]
|
|
Creating decoders for process `$paramod$dd4f06a4ba98f945361f3a45f42984e592ac1bec\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:242$753'.
|
|
1/1: $0\status_done_sticky[0:0]
|
|
Creating decoders for process `$paramod$8f592f3125e8f7c96bc997ed58933554526412a5\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:100$1347'.
|
|
Creating decoders for process `$paramod$8f592f3125e8f7c96bc997ed58933554526412a5\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:81$1346'.
|
|
Creating decoders for process `$paramod$8f592f3125e8f7c96bc997ed58933554526412a5\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:81$1345'.
|
|
Creating decoders for process `$paramod$8f592f3125e8f7c96bc997ed58933554526412a5\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:40$1344'.
|
|
Creating decoders for process `$paramod$8f592f3125e8f7c96bc997ed58933554526412a5\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:40$1343'.
|
|
Creating decoders for process `$paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/psram_controller.v:99$1242'.
|
|
1/18: $0\dq_oe[0:0]
|
|
2/18: $0\psram_zz_n[0:0]
|
|
3/18: $0\psram_ub_n[0:0]
|
|
4/18: $0\psram_lb_n[0:0]
|
|
5/18: $0\psram_we_n[0:0]
|
|
6/18: $0\psram_oe_n[0:0]
|
|
7/18: $0\psram_ce_n[0:0]
|
|
8/18: $0\mem_ready[0:0]
|
|
9/18: $0\dq_out[15:0]
|
|
10/18: $0\ub_reg[0:0]
|
|
11/18: $0\lb_reg[0:0]
|
|
12/18: $0\wr_reg[0:0]
|
|
13/18: $0\wdata_reg[15:0]
|
|
14/18: $0\address_reg[22:0]
|
|
15/18: $0\counter[13:0]
|
|
16/18: $0\psram_a[22:0]
|
|
17/18: $0\mem_rdata[15:0]
|
|
18/18: $0\state[2:0]
|
|
Creating decoders for process `$paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010111.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/int8_memory_access.v:55$676'.
|
|
1/10: $0\mem_req[0:0]
|
|
2/10: $0\ready[0:0]
|
|
3/10: $0\addr_reg[22:0]
|
|
4/10: $0\mem_ub_n[0:0]
|
|
5/10: $0\mem_lb_n[0:0]
|
|
6/10: $0\rdata[7:0]
|
|
7/10: $0\mem_wdata[15:0]
|
|
8/10: $0\mem_addr[22:0]
|
|
9/10: $0\mem_wr[0:0]
|
|
10/10: $0\state[1:0]
|
|
Creating decoders for process `$paramod$c614a16d6b975c0ec2885ffa17a962bce4ddbcec\act_buffer.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/act_buffer.v:60$651'.
|
|
Creating decoders for process `$paramod$c614a16d6b975c0ec2885ffa17a962bce4ddbcec\act_buffer.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/act_buffer.v:55$644'.
|
|
1/3: $1$memwr$\mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/act_buffer.v:57$643_EN[7:0]$650
|
|
2/3: $1$memwr$\mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/act_buffer.v:57$643_DATA[7:0]$649
|
|
3/3: $1$memwr$\mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/act_buffer.v:57$643_ADDR[11:0]$648
|
|
Creating decoders for process `$paramod$bcb9324e2b7cabc82145d6a09db8d736ca601b00\neuron_parallel.$proc$/tmp/before_rewrite/neuron_parallel.v:130$1324'.
|
|
1/5: $0\done[0:0]
|
|
2/5: $0\acc[31:0]
|
|
3/5: $0\group_index[3:0]
|
|
4/5: $0\busy[0:0]
|
|
5/5: $0\y[7:0]
|
|
Creating decoders for process `\spi_slave.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_slave.v:119$12'.
|
|
1/9: $0\cs_end[0:0]
|
|
2/9: $0\cs_start[0:0]
|
|
3/9: $0\tx_byte_req[0:0]
|
|
4/9: $0\rx_valid[0:0]
|
|
5/9: $0\tx_shift[7:0]
|
|
6/9: $0\rx_shift[7:0]
|
|
7/9: $0\bit_count[2:0]
|
|
8/9: $0\rx_byte[7:0]
|
|
9/9: $0\miso[0:0]
|
|
Creating decoders for process `\spi_slave.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_slave.v:93$2'.
|
|
1/2: $0\cs_n_prev[0:0]
|
|
2/2: $0\sclk_prev[0:0]
|
|
Creating decoders for process `\spi_slave.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_slave.v:71$1'.
|
|
1/3: $0\cs_n_sync[2:0]
|
|
2/3: $0\mosi_sync[2:0]
|
|
3/3: $0\sclk_sync[2:0]
|
|
|
|
17.4.8. Executing PROC_DLATCH pass (convert process syncs to latches).
|
|
No latch inferred for signal `$paramod$dd4f06a4ba98f945361f3a45f42984e592ac1bec\spi_engine.\tx_byte_comb' from process `$paramod$dd4f06a4ba98f945361f3a45f42984e592ac1bec\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:263$755'.
|
|
No latch inferred for signal `$paramod$8f592f3125e8f7c96bc997ed58933554526412a5\mac8.\tree[2]' from process `$paramod$8f592f3125e8f7c96bc997ed58933554526412a5\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:100$1347'.
|
|
No latch inferred for signal `$paramod$8f592f3125e8f7c96bc997ed58933554526412a5\mac8.\tree[1]' from process `$paramod$8f592f3125e8f7c96bc997ed58933554526412a5\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:81$1346'.
|
|
No latch inferred for signal `$paramod$8f592f3125e8f7c96bc997ed58933554526412a5\mac8.\tree[0]' from process `$paramod$8f592f3125e8f7c96bc997ed58933554526412a5\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:81$1345'.
|
|
No latch inferred for signal `$paramod$8f592f3125e8f7c96bc997ed58933554526412a5\mac8.\products[1]' from process `$paramod$8f592f3125e8f7c96bc997ed58933554526412a5\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:40$1344'.
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No latch inferred for signal `$paramod$8f592f3125e8f7c96bc997ed58933554526412a5\mac8.\products[0]' from process `$paramod$8f592f3125e8f7c96bc997ed58933554526412a5\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:40$1343'.
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17.4.9. Executing PROC_DFF pass (convert process syncs to FFs).
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Creating register for signal `$paramod$b3f3d2413f22d50ebc275a55cbfefa4ff7d277a1\memory_interface.\state' using process `$paramod$b3f3d2413f22d50ebc275a55cbfefa4ff7d277a1\memory_interface.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/memory_interface.v:33$1239'.
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|
created $dff cell `$procdff$5286' with positive edge clock.
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|
Creating register for signal `$paramod$b3f3d2413f22d50ebc275a55cbfefa4ff7d277a1\memory_interface.\mem_req' using process `$paramod$b3f3d2413f22d50ebc275a55cbfefa4ff7d277a1\memory_interface.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/memory_interface.v:33$1239'.
|
|
created $dff cell `$procdff$5287' with positive edge clock.
|
|
Creating register for signal `$paramod$b3f3d2413f22d50ebc275a55cbfefa4ff7d277a1\memory_interface.\mem_wr' using process `$paramod$b3f3d2413f22d50ebc275a55cbfefa4ff7d277a1\memory_interface.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/memory_interface.v:33$1239'.
|
|
created $dff cell `$procdff$5288' with positive edge clock.
|
|
Creating register for signal `$paramod$b3f3d2413f22d50ebc275a55cbfefa4ff7d277a1\memory_interface.\mem_addr' using process `$paramod$b3f3d2413f22d50ebc275a55cbfefa4ff7d277a1\memory_interface.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/memory_interface.v:33$1239'.
|
|
created $dff cell `$procdff$5289' with positive edge clock.
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|
Creating register for signal `$paramod$b3f3d2413f22d50ebc275a55cbfefa4ff7d277a1\memory_interface.\mem_wdata' using process `$paramod$b3f3d2413f22d50ebc275a55cbfefa4ff7d277a1\memory_interface.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/memory_interface.v:33$1239'.
|
|
created $dff cell `$procdff$5290' with positive edge clock.
|
|
Creating register for signal `$paramod$b3f3d2413f22d50ebc275a55cbfefa4ff7d277a1\memory_interface.\rdata' using process `$paramod$b3f3d2413f22d50ebc275a55cbfefa4ff7d277a1\memory_interface.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/memory_interface.v:33$1239'.
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|
created $dff cell `$procdff$5291' with positive edge clock.
|
|
Creating register for signal `$paramod$b3f3d2413f22d50ebc275a55cbfefa4ff7d277a1\memory_interface.\ready' using process `$paramod$b3f3d2413f22d50ebc275a55cbfefa4ff7d277a1\memory_interface.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/memory_interface.v:33$1239'.
|
|
created $dff cell `$procdff$5292' with positive edge clock.
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|
Creating register for signal `$paramod$b3f3d2413f22d50ebc275a55cbfefa4ff7d277a1\memory_interface.\mem_lb_n' using process `$paramod$b3f3d2413f22d50ebc275a55cbfefa4ff7d277a1\memory_interface.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/memory_interface.v:33$1239'.
|
|
created $dff cell `$procdff$5293' with positive edge clock.
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|
Creating register for signal `$paramod$b3f3d2413f22d50ebc275a55cbfefa4ff7d277a1\memory_interface.\mem_ub_n' using process `$paramod$b3f3d2413f22d50ebc275a55cbfefa4ff7d277a1\memory_interface.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/memory_interface.v:33$1239'.
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|
created $dff cell `$procdff$5294' with positive edge clock.
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|
Creating register for signal `$paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010111.\a_rdata' using process `$paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010111.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mem_arbiter.v:90$1238'.
|
|
created $dff cell `$procdff$5295' with positive edge clock.
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|
Creating register for signal `$paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010111.\a_ready' using process `$paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010111.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mem_arbiter.v:90$1238'.
|
|
created $dff cell `$procdff$5296' with positive edge clock.
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|
Creating register for signal `$paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010111.\b_rdata' using process `$paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010111.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mem_arbiter.v:90$1238'.
|
|
created $dff cell `$procdff$5297' with positive edge clock.
|
|
Creating register for signal `$paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010111.\b_ready' using process `$paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010111.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mem_arbiter.v:90$1238'.
|
|
created $dff cell `$procdff$5298' with positive edge clock.
|
|
Creating register for signal `$paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010111.\c_rdata' using process `$paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010111.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mem_arbiter.v:90$1238'.
|
|
created $dff cell `$procdff$5299' with positive edge clock.
|
|
Creating register for signal `$paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010111.\c_ready' using process `$paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010111.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mem_arbiter.v:90$1238'.
|
|
created $dff cell `$procdff$5300' with positive edge clock.
|
|
Creating register for signal `$paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010111.\m_req' using process `$paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010111.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mem_arbiter.v:90$1238'.
|
|
created $dff cell `$procdff$5301' with positive edge clock.
|
|
Creating register for signal `$paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010111.\m_wr' using process `$paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010111.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mem_arbiter.v:90$1238'.
|
|
created $dff cell `$procdff$5302' with positive edge clock.
|
|
Creating register for signal `$paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010111.\m_addr' using process `$paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010111.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mem_arbiter.v:90$1238'.
|
|
created $dff cell `$procdff$5303' with positive edge clock.
|
|
Creating register for signal `$paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010111.\m_wdata' using process `$paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010111.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mem_arbiter.v:90$1238'.
|
|
created $dff cell `$procdff$5304' with positive edge clock.
|
|
Creating register for signal `$paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010111.\owner' using process `$paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010111.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mem_arbiter.v:90$1238'.
|
|
created $dff cell `$procdff$5305' with positive edge clock.
|
|
Creating register for signal `$paramod$80f5e68183ca7884165c68cdb28403ede9957037\neuron_memory.\state' using process `$paramod$80f5e68183ca7884165c68cdb28403ede9957037\neuron_memory.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:283$1118'.
|
|
created $dff cell `$procdff$5306' with positive edge clock.
|
|
Creating register for signal `$paramod$80f5e68183ca7884165c68cdb28403ede9957037\neuron_memory.\busy' using process `$paramod$80f5e68183ca7884165c68cdb28403ede9957037\neuron_memory.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:283$1118'.
|
|
created $dff cell `$procdff$5307' with positive edge clock.
|
|
Creating register for signal `$paramod$80f5e68183ca7884165c68cdb28403ede9957037\neuron_memory.\done' using process `$paramod$80f5e68183ca7884165c68cdb28403ede9957037\neuron_memory.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:283$1118'.
|
|
created $dff cell `$procdff$5308' with positive edge clock.
|
|
Creating register for signal `$paramod$80f5e68183ca7884165c68cdb28403ede9957037\neuron_memory.\neuron_start' using process `$paramod$80f5e68183ca7884165c68cdb28403ede9957037\neuron_memory.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:283$1118'.
|
|
created $dff cell `$procdff$5309' with positive edge clock.
|
|
Creating register for signal `$paramod$80f5e68183ca7884165c68cdb28403ede9957037\neuron_memory.\bias_reg' using process `$paramod$80f5e68183ca7884165c68cdb28403ede9957037\neuron_memory.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:283$1118'.
|
|
created $dff cell `$procdff$5310' with positive edge clock.
|
|
Creating register for signal `$paramod$80f5e68183ca7884165c68cdb28403ede9957037\neuron_memory.\index' using process `$paramod$80f5e68183ca7884165c68cdb28403ede9957037\neuron_memory.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:283$1118'.
|
|
created $dff cell `$procdff$5311' with positive edge clock.
|
|
Creating register for signal `$paramod$80f5e68183ca7884165c68cdb28403ede9957037\neuron_memory.\neuron_index' using process `$paramod$80f5e68183ca7884165c68cdb28403ede9957037\neuron_memory.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:283$1118'.
|
|
created $dff cell `$procdff$5312' with positive edge clock.
|
|
Creating register for signal `$paramod$80f5e68183ca7884165c68cdb28403ede9957037\neuron_memory.\w_group_base' using process `$paramod$80f5e68183ca7884165c68cdb28403ede9957037\neuron_memory.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:283$1118'.
|
|
created $dff cell `$procdff$5313' with positive edge clock.
|
|
Creating register for signal `$paramod$80f5e68183ca7884165c68cdb28403ede9957037\neuron_memory.\bias_group_addr' using process `$paramod$80f5e68183ca7884165c68cdb28403ede9957037\neuron_memory.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:283$1118'.
|
|
created $dff cell `$procdff$5314' with positive edge clock.
|
|
Creating register for signal `$paramod$80f5e68183ca7884165c68cdb28403ede9957037\neuron_memory.\access_req' using process `$paramod$80f5e68183ca7884165c68cdb28403ede9957037\neuron_memory.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:283$1118'.
|
|
created $dff cell `$procdff$5315' with positive edge clock.
|
|
Creating register for signal `$paramod$80f5e68183ca7884165c68cdb28403ede9957037\neuron_memory.\access_wr' using process `$paramod$80f5e68183ca7884165c68cdb28403ede9957037\neuron_memory.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:283$1118'.
|
|
created $dff cell `$procdff$5316' with positive edge clock.
|
|
Creating register for signal `$paramod$80f5e68183ca7884165c68cdb28403ede9957037\neuron_memory.\access_addr' using process `$paramod$80f5e68183ca7884165c68cdb28403ede9957037\neuron_memory.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:283$1118'.
|
|
created $dff cell `$procdff$5317' with positive edge clock.
|
|
Creating register for signal `$paramod$80f5e68183ca7884165c68cdb28403ede9957037\neuron_memory.\access_wdata' using process `$paramod$80f5e68183ca7884165c68cdb28403ede9957037\neuron_memory.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:283$1118'.
|
|
created $dff cell `$procdff$5318' with positive edge clock.
|
|
Creating register for signal `$paramod$80f5e68183ca7884165c68cdb28403ede9957037\neuron_memory.\rst_i' using process `$paramod$80f5e68183ca7884165c68cdb28403ede9957037\neuron_memory.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:283$1118'.
|
|
created $dff cell `$procdff$5319' with positive edge clock.
|
|
Creating register for signal `$paramod$80f5e68183ca7884165c68cdb28403ede9957037\neuron_memory.$memwr$\y_reg$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:304$1113_EN' using process `$paramod$80f5e68183ca7884165c68cdb28403ede9957037\neuron_memory.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:283$1118'.
|
|
created $dff cell `$procdff$5320' with positive edge clock.
|
|
Creating register for signal `$paramod$80f5e68183ca7884165c68cdb28403ede9957037\neuron_memory.$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:357$1114_ADDR' using process `$paramod$80f5e68183ca7884165c68cdb28403ede9957037\neuron_memory.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:283$1118'.
|
|
created $dff cell `$procdff$5321' with positive edge clock.
|
|
Creating register for signal `$paramod$80f5e68183ca7884165c68cdb28403ede9957037\neuron_memory.$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:357$1114_DATA' using process `$paramod$80f5e68183ca7884165c68cdb28403ede9957037\neuron_memory.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:283$1118'.
|
|
created $dff cell `$procdff$5322' with positive edge clock.
|
|
Creating register for signal `$paramod$80f5e68183ca7884165c68cdb28403ede9957037\neuron_memory.$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:357$1114_EN' using process `$paramod$80f5e68183ca7884165c68cdb28403ede9957037\neuron_memory.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:283$1118'.
|
|
created $dff cell `$procdff$5323' with positive edge clock.
|
|
Creating register for signal `$paramod$80f5e68183ca7884165c68cdb28403ede9957037\neuron_memory.$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:390$1115_ADDR' using process `$paramod$80f5e68183ca7884165c68cdb28403ede9957037\neuron_memory.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:283$1118'.
|
|
created $dff cell `$procdff$5324' with positive edge clock.
|
|
Creating register for signal `$paramod$80f5e68183ca7884165c68cdb28403ede9957037\neuron_memory.$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:390$1115_DATA' using process `$paramod$80f5e68183ca7884165c68cdb28403ede9957037\neuron_memory.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:283$1118'.
|
|
created $dff cell `$procdff$5325' with positive edge clock.
|
|
Creating register for signal `$paramod$80f5e68183ca7884165c68cdb28403ede9957037\neuron_memory.$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:390$1115_EN' using process `$paramod$80f5e68183ca7884165c68cdb28403ede9957037\neuron_memory.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:283$1118'.
|
|
created $dff cell `$procdff$5326' with positive edge clock.
|
|
Creating register for signal `$paramod$80f5e68183ca7884165c68cdb28403ede9957037\neuron_memory.$memwr$\y_reg$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:449$1116_ADDR' using process `$paramod$80f5e68183ca7884165c68cdb28403ede9957037\neuron_memory.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:283$1118'.
|
|
created $dff cell `$procdff$5327' with positive edge clock.
|
|
Creating register for signal `$paramod$80f5e68183ca7884165c68cdb28403ede9957037\neuron_memory.$memwr$\y_reg$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:449$1116_DATA' using process `$paramod$80f5e68183ca7884165c68cdb28403ede9957037\neuron_memory.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:283$1118'.
|
|
created $dff cell `$procdff$5328' with positive edge clock.
|
|
Creating register for signal `$paramod$80f5e68183ca7884165c68cdb28403ede9957037\neuron_memory.$memwr$\y_reg$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:449$1116_EN' using process `$paramod$80f5e68183ca7884165c68cdb28403ede9957037\neuron_memory.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:283$1118'.
|
|
created $dff cell `$procdff$5329' with positive edge clock.
|
|
Creating register for signal `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.\ram_req' using process `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$869'.
|
|
created $dff cell `$procdff$5330' with positive edge clock.
|
|
Creating register for signal `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.\ram_wr' using process `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$869'.
|
|
created $dff cell `$procdff$5331' with positive edge clock.
|
|
Creating register for signal `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.\ram_addr' using process `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$869'.
|
|
created $dff cell `$procdff$5332' with positive edge clock.
|
|
Creating register for signal `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.\ram_wdata' using process `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$869'.
|
|
created $dff cell `$procdff$5333' with positive edge clock.
|
|
Creating register for signal `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.\state' using process `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$869'.
|
|
created $dff cell `$procdff$5334' with positive edge clock.
|
|
Creating register for signal `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.\desc_byte_idx' using process `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$869'.
|
|
created $dff cell `$procdff$5335' with positive edge clock.
|
|
Creating register for signal `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.\busy' using process `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$869'.
|
|
created $dff cell `$procdff$5336' with positive edge clock.
|
|
Creating register for signal `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.\done' using process `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$869'.
|
|
created $dff cell `$procdff$5337' with positive edge clock.
|
|
Creating register for signal `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.\err' using process `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$869'.
|
|
created $dff cell `$procdff$5338' with positive edge clock.
|
|
Creating register for signal `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.\in_idx' using process `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$869'.
|
|
created $dff cell `$procdff$5339' with positive edge clock.
|
|
Creating register for signal `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.\neuron_idx' using process `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$869'.
|
|
created $dff cell `$procdff$5340' with positive edge clock.
|
|
Creating register for signal `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.\desc_addr' using process `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$869'.
|
|
created $dff cell `$procdff$5341' with positive edge clock.
|
|
Creating register for signal `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.\conn_ptr_acc' using process `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$869'.
|
|
created $dff cell `$procdff$5342' with positive edge clock.
|
|
Creating register for signal `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.\n_conn_acc' using process `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$869'.
|
|
created $dff cell `$procdff$5343' with positive edge clock.
|
|
Creating register for signal `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.\out_id_acc' using process `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$869'.
|
|
created $dff cell `$procdff$5344' with positive edge clock.
|
|
Creating register for signal `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.\conn_i' using process `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$869'.
|
|
created $dff cell `$procdff$5345' with positive edge clock.
|
|
Creating register for signal `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.\edge_byte_idx' using process `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$869'.
|
|
created $dff cell `$procdff$5346' with positive edge clock.
|
|
Creating register for signal `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.\src_id_acc' using process `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$869'.
|
|
created $dff cell `$procdff$5347' with positive edge clock.
|
|
Creating register for signal `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.\weight_acc' using process `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$869'.
|
|
created $dff cell `$procdff$5348' with positive edge clock.
|
|
Creating register for signal `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.\act_wr_en' using process `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$869'.
|
|
created $dff cell `$procdff$5349' with positive edge clock.
|
|
Creating register for signal `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.\act_wr_addr' using process `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$869'.
|
|
created $dff cell `$procdff$5350' with positive edge clock.
|
|
Creating register for signal `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.\act_wr_data' using process `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$869'.
|
|
created $dff cell `$procdff$5351' with positive edge clock.
|
|
Creating register for signal `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.\neuron_start' using process `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$869'.
|
|
created $dff cell `$procdff$5352' with positive edge clock.
|
|
Creating register for signal `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.\bias_reg' using process `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$869'.
|
|
created $dff cell `$procdff$5353' with positive edge clock.
|
|
Creating register for signal `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.\activation_reg' using process `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$869'.
|
|
created $dff cell `$procdff$5354' with positive edge clock.
|
|
Creating register for signal `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.\n_conn_padded_reg' using process `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$869'.
|
|
created $dff cell `$procdff$5355' with positive edge clock.
|
|
Creating register for signal `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.\ri' using process `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$869'.
|
|
created $dff cell `$procdff$5356' with positive edge clock.
|
|
Creating register for signal `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$800_EN' using process `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$869'.
|
|
created $dff cell `$procdff$5357' with positive edge clock.
|
|
Creating register for signal `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$801_EN' using process `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$869'.
|
|
created $dff cell `$procdff$5358' with positive edge clock.
|
|
Creating register for signal `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$802_EN' using process `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$869'.
|
|
created $dff cell `$procdff$5359' with positive edge clock.
|
|
Creating register for signal `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$803_EN' using process `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$869'.
|
|
created $dff cell `$procdff$5360' with positive edge clock.
|
|
Creating register for signal `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$804_EN' using process `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$869'.
|
|
created $dff cell `$procdff$5361' with positive edge clock.
|
|
Creating register for signal `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$805_EN' using process `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$869'.
|
|
created $dff cell `$procdff$5362' with positive edge clock.
|
|
Creating register for signal `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$806_EN' using process `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$869'.
|
|
created $dff cell `$procdff$5363' with positive edge clock.
|
|
Creating register for signal `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$807_EN' using process `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$869'.
|
|
created $dff cell `$procdff$5364' with positive edge clock.
|
|
Creating register for signal `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$808_EN' using process `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$869'.
|
|
created $dff cell `$procdff$5365' with positive edge clock.
|
|
Creating register for signal `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$809_EN' using process `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$869'.
|
|
created $dff cell `$procdff$5366' with positive edge clock.
|
|
Creating register for signal `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$810_EN' using process `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$869'.
|
|
created $dff cell `$procdff$5367' with positive edge clock.
|
|
Creating register for signal `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$811_EN' using process `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$869'.
|
|
created $dff cell `$procdff$5368' with positive edge clock.
|
|
Creating register for signal `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$812_EN' using process `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$869'.
|
|
created $dff cell `$procdff$5369' with positive edge clock.
|
|
Creating register for signal `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$813_EN' using process `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$869'.
|
|
created $dff cell `$procdff$5370' with positive edge clock.
|
|
Creating register for signal `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$814_EN' using process `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$869'.
|
|
created $dff cell `$procdff$5371' with positive edge clock.
|
|
Creating register for signal `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$815_EN' using process `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$869'.
|
|
created $dff cell `$procdff$5372' with positive edge clock.
|
|
Creating register for signal `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$816_EN' using process `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$869'.
|
|
created $dff cell `$procdff$5373' with positive edge clock.
|
|
Creating register for signal `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$817_EN' using process `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$869'.
|
|
created $dff cell `$procdff$5374' with positive edge clock.
|
|
Creating register for signal `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$818_EN' using process `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$869'.
|
|
created $dff cell `$procdff$5375' with positive edge clock.
|
|
Creating register for signal `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$819_EN' using process `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$869'.
|
|
created $dff cell `$procdff$5376' with positive edge clock.
|
|
Creating register for signal `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$820_EN' using process `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$869'.
|
|
created $dff cell `$procdff$5377' with positive edge clock.
|
|
Creating register for signal `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$821_EN' using process `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$869'.
|
|
created $dff cell `$procdff$5378' with positive edge clock.
|
|
Creating register for signal `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$822_EN' using process `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$869'.
|
|
created $dff cell `$procdff$5379' with positive edge clock.
|
|
Creating register for signal `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$823_EN' using process `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$869'.
|
|
created $dff cell `$procdff$5380' with positive edge clock.
|
|
Creating register for signal `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$824_EN' using process `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$869'.
|
|
created $dff cell `$procdff$5381' with positive edge clock.
|
|
Creating register for signal `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$825_EN' using process `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$869'.
|
|
created $dff cell `$procdff$5382' with positive edge clock.
|
|
Creating register for signal `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$826_EN' using process `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$869'.
|
|
created $dff cell `$procdff$5383' with positive edge clock.
|
|
Creating register for signal `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$827_EN' using process `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$869'.
|
|
created $dff cell `$procdff$5384' with positive edge clock.
|
|
Creating register for signal `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$828_EN' using process `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$869'.
|
|
created $dff cell `$procdff$5385' with positive edge clock.
|
|
Creating register for signal `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$829_EN' using process `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$869'.
|
|
created $dff cell `$procdff$5386' with positive edge clock.
|
|
Creating register for signal `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$830_EN' using process `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$869'.
|
|
created $dff cell `$procdff$5387' with positive edge clock.
|
|
Creating register for signal `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$831_EN' using process `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$869'.
|
|
created $dff cell `$procdff$5388' with positive edge clock.
|
|
Creating register for signal `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$832_EN' using process `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$869'.
|
|
created $dff cell `$procdff$5389' with positive edge clock.
|
|
Creating register for signal `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$833_EN' using process `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$869'.
|
|
created $dff cell `$procdff$5390' with positive edge clock.
|
|
Creating register for signal `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$834_EN' using process `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$869'.
|
|
created $dff cell `$procdff$5391' with positive edge clock.
|
|
Creating register for signal `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$835_EN' using process `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$869'.
|
|
created $dff cell `$procdff$5392' with positive edge clock.
|
|
Creating register for signal `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$836_EN' using process `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$869'.
|
|
created $dff cell `$procdff$5393' with positive edge clock.
|
|
Creating register for signal `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$837_EN' using process `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$869'.
|
|
created $dff cell `$procdff$5394' with positive edge clock.
|
|
Creating register for signal `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$838_EN' using process `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$869'.
|
|
created $dff cell `$procdff$5395' with positive edge clock.
|
|
Creating register for signal `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$839_EN' using process `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$869'.
|
|
created $dff cell `$procdff$5396' with positive edge clock.
|
|
Creating register for signal `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$840_EN' using process `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$869'.
|
|
created $dff cell `$procdff$5397' with positive edge clock.
|
|
Creating register for signal `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$841_EN' using process `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$869'.
|
|
created $dff cell `$procdff$5398' with positive edge clock.
|
|
Creating register for signal `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$842_EN' using process `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$869'.
|
|
created $dff cell `$procdff$5399' with positive edge clock.
|
|
Creating register for signal `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$843_EN' using process `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$869'.
|
|
created $dff cell `$procdff$5400' with positive edge clock.
|
|
Creating register for signal `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$844_EN' using process `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$869'.
|
|
created $dff cell `$procdff$5401' with positive edge clock.
|
|
Creating register for signal `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$845_EN' using process `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$869'.
|
|
created $dff cell `$procdff$5402' with positive edge clock.
|
|
Creating register for signal `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$846_EN' using process `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$869'.
|
|
created $dff cell `$procdff$5403' with positive edge clock.
|
|
Creating register for signal `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$847_EN' using process `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$869'.
|
|
created $dff cell `$procdff$5404' with positive edge clock.
|
|
Creating register for signal `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$848_EN' using process `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$869'.
|
|
created $dff cell `$procdff$5405' with positive edge clock.
|
|
Creating register for signal `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$849_EN' using process `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$869'.
|
|
created $dff cell `$procdff$5406' with positive edge clock.
|
|
Creating register for signal `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$850_EN' using process `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$869'.
|
|
created $dff cell `$procdff$5407' with positive edge clock.
|
|
Creating register for signal `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$851_EN' using process `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$869'.
|
|
created $dff cell `$procdff$5408' with positive edge clock.
|
|
Creating register for signal `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$852_EN' using process `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$869'.
|
|
created $dff cell `$procdff$5409' with positive edge clock.
|
|
Creating register for signal `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$853_EN' using process `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$869'.
|
|
created $dff cell `$procdff$5410' with positive edge clock.
|
|
Creating register for signal `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$854_EN' using process `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$869'.
|
|
created $dff cell `$procdff$5411' with positive edge clock.
|
|
Creating register for signal `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$855_EN' using process `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$869'.
|
|
created $dff cell `$procdff$5412' with positive edge clock.
|
|
Creating register for signal `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$856_EN' using process `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$869'.
|
|
created $dff cell `$procdff$5413' with positive edge clock.
|
|
Creating register for signal `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$857_EN' using process `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$869'.
|
|
created $dff cell `$procdff$5414' with positive edge clock.
|
|
Creating register for signal `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$858_EN' using process `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$869'.
|
|
created $dff cell `$procdff$5415' with positive edge clock.
|
|
Creating register for signal `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$859_EN' using process `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$869'.
|
|
created $dff cell `$procdff$5416' with positive edge clock.
|
|
Creating register for signal `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$860_EN' using process `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$869'.
|
|
created $dff cell `$procdff$5417' with positive edge clock.
|
|
Creating register for signal `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$861_EN' using process `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$869'.
|
|
created $dff cell `$procdff$5418' with positive edge clock.
|
|
Creating register for signal `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$862_EN' using process `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$869'.
|
|
created $dff cell `$procdff$5419' with positive edge clock.
|
|
Creating register for signal `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$863_EN' using process `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$869'.
|
|
created $dff cell `$procdff$5420' with positive edge clock.
|
|
Creating register for signal `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:495$864_ADDR' using process `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$869'.
|
|
created $dff cell `$procdff$5421' with positive edge clock.
|
|
Creating register for signal `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:495$864_DATA' using process `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$869'.
|
|
created $dff cell `$procdff$5422' with positive edge clock.
|
|
Creating register for signal `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:495$864_EN' using process `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$869'.
|
|
created $dff cell `$procdff$5423' with positive edge clock.
|
|
Creating register for signal `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:496$865_ADDR' using process `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$869'.
|
|
created $dff cell `$procdff$5424' with positive edge clock.
|
|
Creating register for signal `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:496$865_DATA' using process `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$869'.
|
|
created $dff cell `$procdff$5425' with positive edge clock.
|
|
Creating register for signal `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:496$865_EN' using process `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$869'.
|
|
created $dff cell `$procdff$5426' with positive edge clock.
|
|
Creating register for signal `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.\ram_req' using process `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:137$780'.
|
|
created $dff cell `$procdff$5427' with positive edge clock.
|
|
Creating register for signal `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.\ram_wr' using process `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:137$780'.
|
|
created $dff cell `$procdff$5428' with positive edge clock.
|
|
Creating register for signal `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.\ram_addr' using process `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:137$780'.
|
|
created $dff cell `$procdff$5429' with positive edge clock.
|
|
Creating register for signal `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.\ram_wdata' using process `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:137$780'.
|
|
created $dff cell `$procdff$5430' with positive edge clock.
|
|
Creating register for signal `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.\nm_start' using process `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:137$780'.
|
|
created $dff cell `$procdff$5431' with positive edge clock.
|
|
Creating register for signal `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.\seq_busy' using process `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:137$780'.
|
|
created $dff cell `$procdff$5432' with positive edge clock.
|
|
Creating register for signal `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.\seq_done' using process `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:137$780'.
|
|
created $dff cell `$procdff$5433' with positive edge clock.
|
|
Creating register for signal `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.\state' using process `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:137$780'.
|
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created $dff cell `$procdff$5434' with positive edge clock.
|
|
Creating register for signal `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.\nm_x_base' using process `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:137$780'.
|
|
created $dff cell `$procdff$5435' with positive edge clock.
|
|
Creating register for signal `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.\nm_w_base' using process `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:137$780'.
|
|
created $dff cell `$procdff$5436' with positive edge clock.
|
|
Creating register for signal `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.\nm_bias_addr' using process `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:137$780'.
|
|
created $dff cell `$procdff$5437' with positive edge clock.
|
|
Creating register for signal `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.\nm_activation' using process `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:137$780'.
|
|
created $dff cell `$procdff$5438' with positive edge clock.
|
|
Creating register for signal `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.\nm_n_inputs' using process `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:137$780'.
|
|
created $dff cell `$procdff$5439' with positive edge clock.
|
|
Creating register for signal `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.\nm_n_neurons' using process `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:137$780'.
|
|
created $dff cell `$procdff$5440' with positive edge clock.
|
|
Creating register for signal `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.\layer_idx' using process `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:137$780'.
|
|
created $dff cell `$procdff$5441' with positive edge clock.
|
|
Creating register for signal `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.\num_layers_reg' using process `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:137$780'.
|
|
created $dff cell `$procdff$5442' with positive edge clock.
|
|
Creating register for signal `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.\desc_table_addr' using process `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:137$780'.
|
|
created $dff cell `$procdff$5443' with positive edge clock.
|
|
Creating register for signal `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.\desc_byte_idx' using process `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:137$780'.
|
|
created $dff cell `$procdff$5444' with positive edge clock.
|
|
Creating register for signal `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.\w_base_acc' using process `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:137$780'.
|
|
created $dff cell `$procdff$5445' with positive edge clock.
|
|
Creating register for signal `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.\bias_addr_acc' using process `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:137$780'.
|
|
created $dff cell `$procdff$5446' with positive edge clock.
|
|
Creating register for signal `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.\activation_acc' using process `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:137$780'.
|
|
created $dff cell `$procdff$5447' with positive edge clock.
|
|
Creating register for signal `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.\n_inputs_acc' using process `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:137$780'.
|
|
created $dff cell `$procdff$5448' with positive edge clock.
|
|
Creating register for signal `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.\n_neurons_acc' using process `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:137$780'.
|
|
created $dff cell `$procdff$5449' with positive edge clock.
|
|
Creating register for signal `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.\cur_sel' using process `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:137$780'.
|
|
created $dff cell `$procdff$5450' with positive edge clock.
|
|
Creating register for signal `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.\write_sel' using process `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:137$780'.
|
|
created $dff cell `$procdff$5451' with positive edge clock.
|
|
Creating register for signal `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.\copy_idx' using process `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:137$780'.
|
|
created $dff cell `$procdff$5452' with positive edge clock.
|
|
Creating register for signal `$paramod$dd4f06a4ba98f945361f3a45f42984e592ac1bec\spi_engine.\ram_req' using process `$paramod$dd4f06a4ba98f945361f3a45f42984e592ac1bec\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:315$760'.
|
|
created $dff cell `$procdff$5453' with positive edge clock.
|
|
Creating register for signal `$paramod$dd4f06a4ba98f945361f3a45f42984e592ac1bec\spi_engine.\ram_wr' using process `$paramod$dd4f06a4ba98f945361f3a45f42984e592ac1bec\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:315$760'.
|
|
created $dff cell `$procdff$5454' with positive edge clock.
|
|
Creating register for signal `$paramod$dd4f06a4ba98f945361f3a45f42984e592ac1bec\spi_engine.\ram_addr' using process `$paramod$dd4f06a4ba98f945361f3a45f42984e592ac1bec\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:315$760'.
|
|
created $dff cell `$procdff$5455' with positive edge clock.
|
|
Creating register for signal `$paramod$dd4f06a4ba98f945361f3a45f42984e592ac1bec\spi_engine.\ram_wdata' using process `$paramod$dd4f06a4ba98f945361f3a45f42984e592ac1bec\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:315$760'.
|
|
created $dff cell `$procdff$5456' with positive edge clock.
|
|
Creating register for signal `$paramod$dd4f06a4ba98f945361f3a45f42984e592ac1bec\spi_engine.\x_base' using process `$paramod$dd4f06a4ba98f945361f3a45f42984e592ac1bec\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:315$760'.
|
|
created $dff cell `$procdff$5457' with positive edge clock.
|
|
Creating register for signal `$paramod$dd4f06a4ba98f945361f3a45f42984e592ac1bec\spi_engine.\w_base' using process `$paramod$dd4f06a4ba98f945361f3a45f42984e592ac1bec\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:315$760'.
|
|
created $dff cell `$procdff$5458' with positive edge clock.
|
|
Creating register for signal `$paramod$dd4f06a4ba98f945361f3a45f42984e592ac1bec\spi_engine.\bias_addr' using process `$paramod$dd4f06a4ba98f945361f3a45f42984e592ac1bec\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:315$760'.
|
|
created $dff cell `$procdff$5459' with positive edge clock.
|
|
Creating register for signal `$paramod$dd4f06a4ba98f945361f3a45f42984e592ac1bec\spi_engine.\activation' using process `$paramod$dd4f06a4ba98f945361f3a45f42984e592ac1bec\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:315$760'.
|
|
created $dff cell `$procdff$5460' with positive edge clock.
|
|
Creating register for signal `$paramod$dd4f06a4ba98f945361f3a45f42984e592ac1bec\spi_engine.\n_inputs_real' using process `$paramod$dd4f06a4ba98f945361f3a45f42984e592ac1bec\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:315$760'.
|
|
created $dff cell `$procdff$5461' with positive edge clock.
|
|
Creating register for signal `$paramod$dd4f06a4ba98f945361f3a45f42984e592ac1bec\spi_engine.\n_neurons_real' using process `$paramod$dd4f06a4ba98f945361f3a45f42984e592ac1bec\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:315$760'.
|
|
created $dff cell `$procdff$5462' with positive edge clock.
|
|
Creating register for signal `$paramod$dd4f06a4ba98f945361f3a45f42984e592ac1bec\spi_engine.\nm_start' using process `$paramod$dd4f06a4ba98f945361f3a45f42984e592ac1bec\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:315$760'.
|
|
created $dff cell `$procdff$5463' with positive edge clock.
|
|
Creating register for signal `$paramod$dd4f06a4ba98f945361f3a45f42984e592ac1bec\spi_engine.\nm_soft_rst' using process `$paramod$dd4f06a4ba98f945361f3a45f42984e592ac1bec\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:315$760'.
|
|
created $dff cell `$procdff$5464' with positive edge clock.
|
|
Creating register for signal `$paramod$dd4f06a4ba98f945361f3a45f42984e592ac1bec\spi_engine.\table_base' using process `$paramod$dd4f06a4ba98f945361f3a45f42984e592ac1bec\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:315$760'.
|
|
created $dff cell `$procdff$5465' with positive edge clock.
|
|
Creating register for signal `$paramod$dd4f06a4ba98f945361f3a45f42984e592ac1bec\spi_engine.\buf_a_base' using process `$paramod$dd4f06a4ba98f945361f3a45f42984e592ac1bec\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:315$760'.
|
|
created $dff cell `$procdff$5466' with positive edge clock.
|
|
Creating register for signal `$paramod$dd4f06a4ba98f945361f3a45f42984e592ac1bec\spi_engine.\buf_b_base' using process `$paramod$dd4f06a4ba98f945361f3a45f42984e592ac1bec\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:315$760'.
|
|
created $dff cell `$procdff$5467' with positive edge clock.
|
|
Creating register for signal `$paramod$dd4f06a4ba98f945361f3a45f42984e592ac1bec\spi_engine.\run_start' using process `$paramod$dd4f06a4ba98f945361f3a45f42984e592ac1bec\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:315$760'.
|
|
created $dff cell `$procdff$5468' with positive edge clock.
|
|
Creating register for signal `$paramod$dd4f06a4ba98f945361f3a45f42984e592ac1bec\spi_engine.\run_num_layers' using process `$paramod$dd4f06a4ba98f945361f3a45f42984e592ac1bec\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:315$760'.
|
|
created $dff cell `$procdff$5469' with positive edge clock.
|
|
Creating register for signal `$paramod$dd4f06a4ba98f945361f3a45f42984e592ac1bec\spi_engine.\net_type' using process `$paramod$dd4f06a4ba98f945361f3a45f42984e592ac1bec\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:315$760'.
|
|
created $dff cell `$procdff$5470' with positive edge clock.
|
|
Creating register for signal `$paramod$dd4f06a4ba98f945361f3a45f42984e592ac1bec\spi_engine.\num_neurons_graph' using process `$paramod$dd4f06a4ba98f945361f3a45f42984e592ac1bec\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:315$760'.
|
|
created $dff cell `$procdff$5471' with positive edge clock.
|
|
Creating register for signal `$paramod$dd4f06a4ba98f945361f3a45f42984e592ac1bec\spi_engine.\n_out' using process `$paramod$dd4f06a4ba98f945361f3a45f42984e592ac1bec\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:315$760'.
|
|
created $dff cell `$procdff$5472' with positive edge clock.
|
|
Creating register for signal `$paramod$dd4f06a4ba98f945361f3a45f42984e592ac1bec\spi_engine.\state' using process `$paramod$dd4f06a4ba98f945361f3a45f42984e592ac1bec\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:315$760'.
|
|
created $dff cell `$procdff$5473' with positive edge clock.
|
|
Creating register for signal `$paramod$dd4f06a4ba98f945361f3a45f42984e592ac1bec\spi_engine.\opcode' using process `$paramod$dd4f06a4ba98f945361f3a45f42984e592ac1bec\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:315$760'.
|
|
created $dff cell `$procdff$5474' with positive edge clock.
|
|
Creating register for signal `$paramod$dd4f06a4ba98f945361f3a45f42984e592ac1bec\spi_engine.\byte_pos' using process `$paramod$dd4f06a4ba98f945361f3a45f42984e592ac1bec\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:315$760'.
|
|
created $dff cell `$procdff$5475' with positive edge clock.
|
|
Creating register for signal `$paramod$dd4f06a4ba98f945361f3a45f42984e592ac1bec\spi_engine.\addr_acc' using process `$paramod$dd4f06a4ba98f945361f3a45f42984e592ac1bec\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:315$760'.
|
|
created $dff cell `$procdff$5476' with positive edge clock.
|
|
Creating register for signal `$paramod$dd4f06a4ba98f945361f3a45f42984e592ac1bec\spi_engine.\len_acc' using process `$paramod$dd4f06a4ba98f945361f3a45f42984e592ac1bec\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:315$760'.
|
|
created $dff cell `$procdff$5477' with positive edge clock.
|
|
Creating register for signal `$paramod$dd4f06a4ba98f945361f3a45f42984e592ac1bec\spi_engine.\len_remaining' using process `$paramod$dd4f06a4ba98f945361f3a45f42984e592ac1bec\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:315$760'.
|
|
created $dff cell `$procdff$5478' with positive edge clock.
|
|
Creating register for signal `$paramod$dd4f06a4ba98f945361f3a45f42984e592ac1bec\spi_engine.\cur_addr' using process `$paramod$dd4f06a4ba98f945361f3a45f42984e592ac1bec\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:315$760'.
|
|
created $dff cell `$procdff$5479' with positive edge clock.
|
|
Creating register for signal `$paramod$dd4f06a4ba98f945361f3a45f42984e592ac1bec\spi_engine.\pending_write' using process `$paramod$dd4f06a4ba98f945361f3a45f42984e592ac1bec\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:315$760'.
|
|
created $dff cell `$procdff$5480' with positive edge clock.
|
|
Creating register for signal `$paramod$dd4f06a4ba98f945361f3a45f42984e592ac1bec\spi_engine.\pending_wdata' using process `$paramod$dd4f06a4ba98f945361f3a45f42984e592ac1bec\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:315$760'.
|
|
created $dff cell `$procdff$5481' with positive edge clock.
|
|
Creating register for signal `$paramod$dd4f06a4ba98f945361f3a45f42984e592ac1bec\spi_engine.\cur_read_byte' using process `$paramod$dd4f06a4ba98f945361f3a45f42984e592ac1bec\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:315$760'.
|
|
created $dff cell `$procdff$5482' with positive edge clock.
|
|
Creating register for signal `$paramod$dd4f06a4ba98f945361f3a45f42984e592ac1bec\spi_engine.\resp_index' using process `$paramod$dd4f06a4ba98f945361f3a45f42984e592ac1bec\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:315$760'.
|
|
created $dff cell `$procdff$5483' with positive edge clock.
|
|
Creating register for signal `$paramod$dd4f06a4ba98f945361f3a45f42984e592ac1bec\spi_engine.\resp_len' using process `$paramod$dd4f06a4ba98f945361f3a45f42984e592ac1bec\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:315$760'.
|
|
created $dff cell `$procdff$5484' with positive edge clock.
|
|
Creating register for signal `$paramod$dd4f06a4ba98f945361f3a45f42984e592ac1bec\spi_engine.\net_mode' using process `$paramod$dd4f06a4ba98f945361f3a45f42984e592ac1bec\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:315$760'.
|
|
created $dff cell `$procdff$5485' with positive edge clock.
|
|
Creating register for signal `$paramod$dd4f06a4ba98f945361f3a45f42984e592ac1bec\spi_engine.\graph_mode' using process `$paramod$dd4f06a4ba98f945361f3a45f42984e592ac1bec\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:315$760'.
|
|
created $dff cell `$procdff$5486' with positive edge clock.
|
|
Creating register for signal `$paramod$dd4f06a4ba98f945361f3a45f42984e592ac1bec\spi_engine.\status_snapshot' using process `$paramod$dd4f06a4ba98f945361f3a45f42984e592ac1bec\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:315$760'.
|
|
created $dff cell `$procdff$5487' with positive edge clock.
|
|
Creating register for signal `$paramod$dd4f06a4ba98f945361f3a45f42984e592ac1bec\spi_engine.\status_done_sticky' using process `$paramod$dd4f06a4ba98f945361f3a45f42984e592ac1bec\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:242$753'.
|
|
created $dff cell `$procdff$5488' with positive edge clock.
|
|
Creating register for signal `$paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller.\state' using process `$paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/psram_controller.v:99$1242'.
|
|
created $dff cell `$procdff$5489' with positive edge clock.
|
|
Creating register for signal `$paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller.\mem_rdata' using process `$paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/psram_controller.v:99$1242'.
|
|
created $dff cell `$procdff$5490' with positive edge clock.
|
|
Creating register for signal `$paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller.\mem_ready' using process `$paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/psram_controller.v:99$1242'.
|
|
created $dff cell `$procdff$5491' with positive edge clock.
|
|
Creating register for signal `$paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller.\psram_a' using process `$paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/psram_controller.v:99$1242'.
|
|
created $dff cell `$procdff$5492' with positive edge clock.
|
|
Creating register for signal `$paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller.\psram_ce_n' using process `$paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/psram_controller.v:99$1242'.
|
|
created $dff cell `$procdff$5493' with positive edge clock.
|
|
Creating register for signal `$paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller.\psram_oe_n' using process `$paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/psram_controller.v:99$1242'.
|
|
created $dff cell `$procdff$5494' with positive edge clock.
|
|
Creating register for signal `$paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller.\psram_we_n' using process `$paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/psram_controller.v:99$1242'.
|
|
created $dff cell `$procdff$5495' with positive edge clock.
|
|
Creating register for signal `$paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller.\psram_lb_n' using process `$paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/psram_controller.v:99$1242'.
|
|
created $dff cell `$procdff$5496' with positive edge clock.
|
|
Creating register for signal `$paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller.\psram_ub_n' using process `$paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/psram_controller.v:99$1242'.
|
|
created $dff cell `$procdff$5497' with positive edge clock.
|
|
Creating register for signal `$paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller.\psram_zz_n' using process `$paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/psram_controller.v:99$1242'.
|
|
created $dff cell `$procdff$5498' with positive edge clock.
|
|
Creating register for signal `$paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller.\counter' using process `$paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/psram_controller.v:99$1242'.
|
|
created $dff cell `$procdff$5499' with positive edge clock.
|
|
Creating register for signal `$paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller.\address_reg' using process `$paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/psram_controller.v:99$1242'.
|
|
created $dff cell `$procdff$5500' with positive edge clock.
|
|
Creating register for signal `$paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller.\wdata_reg' using process `$paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/psram_controller.v:99$1242'.
|
|
created $dff cell `$procdff$5501' with positive edge clock.
|
|
Creating register for signal `$paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller.\wr_reg' using process `$paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/psram_controller.v:99$1242'.
|
|
created $dff cell `$procdff$5502' with positive edge clock.
|
|
Creating register for signal `$paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller.\lb_reg' using process `$paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/psram_controller.v:99$1242'.
|
|
created $dff cell `$procdff$5503' with positive edge clock.
|
|
Creating register for signal `$paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller.\ub_reg' using process `$paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/psram_controller.v:99$1242'.
|
|
created $dff cell `$procdff$5504' with positive edge clock.
|
|
Creating register for signal `$paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller.\dq_out' using process `$paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/psram_controller.v:99$1242'.
|
|
created $dff cell `$procdff$5505' with positive edge clock.
|
|
Creating register for signal `$paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller.\dq_oe' using process `$paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/psram_controller.v:99$1242'.
|
|
created $dff cell `$procdff$5506' with positive edge clock.
|
|
Creating register for signal `$paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010111.\state' using process `$paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010111.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/int8_memory_access.v:55$676'.
|
|
created $dff cell `$procdff$5507' with positive edge clock.
|
|
Creating register for signal `$paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010111.\mem_req' using process `$paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010111.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/int8_memory_access.v:55$676'.
|
|
created $dff cell `$procdff$5508' with positive edge clock.
|
|
Creating register for signal `$paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010111.\mem_wr' using process `$paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010111.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/int8_memory_access.v:55$676'.
|
|
created $dff cell `$procdff$5509' with positive edge clock.
|
|
Creating register for signal `$paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010111.\mem_addr' using process `$paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010111.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/int8_memory_access.v:55$676'.
|
|
created $dff cell `$procdff$5510' with positive edge clock.
|
|
Creating register for signal `$paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010111.\mem_wdata' using process `$paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010111.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/int8_memory_access.v:55$676'.
|
|
created $dff cell `$procdff$5511' with positive edge clock.
|
|
Creating register for signal `$paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010111.\rdata' using process `$paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010111.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/int8_memory_access.v:55$676'.
|
|
created $dff cell `$procdff$5512' with positive edge clock.
|
|
Creating register for signal `$paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010111.\ready' using process `$paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010111.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/int8_memory_access.v:55$676'.
|
|
created $dff cell `$procdff$5513' with positive edge clock.
|
|
Creating register for signal `$paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010111.\mem_lb_n' using process `$paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010111.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/int8_memory_access.v:55$676'.
|
|
created $dff cell `$procdff$5514' with positive edge clock.
|
|
Creating register for signal `$paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010111.\mem_ub_n' using process `$paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010111.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/int8_memory_access.v:55$676'.
|
|
created $dff cell `$procdff$5515' with positive edge clock.
|
|
Creating register for signal `$paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010111.\addr_reg' using process `$paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010111.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/int8_memory_access.v:55$676'.
|
|
created $dff cell `$procdff$5516' with positive edge clock.
|
|
Creating register for signal `$paramod$c614a16d6b975c0ec2885ffa17a962bce4ddbcec\act_buffer.\rd_data' using process `$paramod$c614a16d6b975c0ec2885ffa17a962bce4ddbcec\act_buffer.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/act_buffer.v:60$651'.
|
|
created $dff cell `$procdff$5517' with positive edge clock.
|
|
Creating register for signal `$paramod$c614a16d6b975c0ec2885ffa17a962bce4ddbcec\act_buffer.$memwr$\mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/act_buffer.v:57$643_ADDR' using process `$paramod$c614a16d6b975c0ec2885ffa17a962bce4ddbcec\act_buffer.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/act_buffer.v:55$644'.
|
|
created $dff cell `$procdff$5518' with positive edge clock.
|
|
Creating register for signal `$paramod$c614a16d6b975c0ec2885ffa17a962bce4ddbcec\act_buffer.$memwr$\mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/act_buffer.v:57$643_DATA' using process `$paramod$c614a16d6b975c0ec2885ffa17a962bce4ddbcec\act_buffer.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/act_buffer.v:55$644'.
|
|
created $dff cell `$procdff$5519' with positive edge clock.
|
|
Creating register for signal `$paramod$c614a16d6b975c0ec2885ffa17a962bce4ddbcec\act_buffer.$memwr$\mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/act_buffer.v:57$643_EN' using process `$paramod$c614a16d6b975c0ec2885ffa17a962bce4ddbcec\act_buffer.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/act_buffer.v:55$644'.
|
|
created $dff cell `$procdff$5520' with positive edge clock.
|
|
Creating register for signal `$paramod$bcb9324e2b7cabc82145d6a09db8d736ca601b00\neuron_parallel.\y' using process `$paramod$bcb9324e2b7cabc82145d6a09db8d736ca601b00\neuron_parallel.$proc$/tmp/before_rewrite/neuron_parallel.v:130$1324'.
|
|
created $dff cell `$procdff$5521' with positive edge clock.
|
|
Creating register for signal `$paramod$bcb9324e2b7cabc82145d6a09db8d736ca601b00\neuron_parallel.\busy' using process `$paramod$bcb9324e2b7cabc82145d6a09db8d736ca601b00\neuron_parallel.$proc$/tmp/before_rewrite/neuron_parallel.v:130$1324'.
|
|
created $dff cell `$procdff$5522' with positive edge clock.
|
|
Creating register for signal `$paramod$bcb9324e2b7cabc82145d6a09db8d736ca601b00\neuron_parallel.\done' using process `$paramod$bcb9324e2b7cabc82145d6a09db8d736ca601b00\neuron_parallel.$proc$/tmp/before_rewrite/neuron_parallel.v:130$1324'.
|
|
created $dff cell `$procdff$5523' with positive edge clock.
|
|
Creating register for signal `$paramod$bcb9324e2b7cabc82145d6a09db8d736ca601b00\neuron_parallel.\group_index' using process `$paramod$bcb9324e2b7cabc82145d6a09db8d736ca601b00\neuron_parallel.$proc$/tmp/before_rewrite/neuron_parallel.v:130$1324'.
|
|
created $dff cell `$procdff$5524' with positive edge clock.
|
|
Creating register for signal `$paramod$bcb9324e2b7cabc82145d6a09db8d736ca601b00\neuron_parallel.\acc' using process `$paramod$bcb9324e2b7cabc82145d6a09db8d736ca601b00\neuron_parallel.$proc$/tmp/before_rewrite/neuron_parallel.v:130$1324'.
|
|
created $dff cell `$procdff$5525' with positive edge clock.
|
|
Creating register for signal `\spi_slave.\miso' using process `\spi_slave.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_slave.v:119$12'.
|
|
created $dff cell `$procdff$5526' with positive edge clock.
|
|
Creating register for signal `\spi_slave.\rx_byte' using process `\spi_slave.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_slave.v:119$12'.
|
|
created $dff cell `$procdff$5527' with positive edge clock.
|
|
Creating register for signal `\spi_slave.\rx_valid' using process `\spi_slave.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_slave.v:119$12'.
|
|
created $dff cell `$procdff$5528' with positive edge clock.
|
|
Creating register for signal `\spi_slave.\tx_byte_req' using process `\spi_slave.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_slave.v:119$12'.
|
|
created $dff cell `$procdff$5529' with positive edge clock.
|
|
Creating register for signal `\spi_slave.\cs_start' using process `\spi_slave.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_slave.v:119$12'.
|
|
created $dff cell `$procdff$5530' with positive edge clock.
|
|
Creating register for signal `\spi_slave.\cs_end' using process `\spi_slave.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_slave.v:119$12'.
|
|
created $dff cell `$procdff$5531' with positive edge clock.
|
|
Creating register for signal `\spi_slave.\bit_count' using process `\spi_slave.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_slave.v:119$12'.
|
|
created $dff cell `$procdff$5532' with positive edge clock.
|
|
Creating register for signal `\spi_slave.\rx_shift' using process `\spi_slave.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_slave.v:119$12'.
|
|
created $dff cell `$procdff$5533' with positive edge clock.
|
|
Creating register for signal `\spi_slave.\tx_shift' using process `\spi_slave.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_slave.v:119$12'.
|
|
created $dff cell `$procdff$5534' with positive edge clock.
|
|
Creating register for signal `\spi_slave.\sclk_prev' using process `\spi_slave.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_slave.v:93$2'.
|
|
created $dff cell `$procdff$5535' with positive edge clock.
|
|
Creating register for signal `\spi_slave.\cs_n_prev' using process `\spi_slave.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_slave.v:93$2'.
|
|
created $dff cell `$procdff$5536' with positive edge clock.
|
|
Creating register for signal `\spi_slave.\sclk_sync' using process `\spi_slave.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_slave.v:71$1'.
|
|
created $dff cell `$procdff$5537' with positive edge clock.
|
|
Creating register for signal `\spi_slave.\mosi_sync' using process `\spi_slave.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_slave.v:71$1'.
|
|
created $dff cell `$procdff$5538' with positive edge clock.
|
|
Creating register for signal `\spi_slave.\cs_n_sync' using process `\spi_slave.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_slave.v:71$1'.
|
|
created $dff cell `$procdff$5539' with positive edge clock.
|
|
|
|
17.4.10. Executing PROC_MEMWR pass (convert process memory writes to cells).
|
|
|
|
17.4.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
|
|
Found and cleaned up 5 empty switches in `$paramod$b3f3d2413f22d50ebc275a55cbfefa4ff7d277a1\memory_interface.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/memory_interface.v:33$1239'.
|
|
Removing empty process `$paramod$b3f3d2413f22d50ebc275a55cbfefa4ff7d277a1\memory_interface.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/memory_interface.v:33$1239'.
|
|
Found and cleaned up 8 empty switches in `$paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010111.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mem_arbiter.v:90$1238'.
|
|
Removing empty process `$paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010111.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mem_arbiter.v:90$1238'.
|
|
Found and cleaned up 10 empty switches in `$paramod$80f5e68183ca7884165c68cdb28403ede9957037\neuron_memory.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:283$1118'.
|
|
Removing empty process `$paramod$80f5e68183ca7884165c68cdb28403ede9957037\neuron_memory.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:283$1118'.
|
|
Found and cleaned up 19 empty switches in `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$869'.
|
|
Removing empty process `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$869'.
|
|
Found and cleaned up 10 empty switches in `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:137$780'.
|
|
Removing empty process `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:137$780'.
|
|
Found and cleaned up 29 empty switches in `$paramod$dd4f06a4ba98f945361f3a45f42984e592ac1bec\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:315$760'.
|
|
Removing empty process `$paramod$dd4f06a4ba98f945361f3a45f42984e592ac1bec\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:315$760'.
|
|
Found and cleaned up 4 empty switches in `$paramod$dd4f06a4ba98f945361f3a45f42984e592ac1bec\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:263$755'.
|
|
Removing empty process `$paramod$dd4f06a4ba98f945361f3a45f42984e592ac1bec\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:263$755'.
|
|
Found and cleaned up 4 empty switches in `$paramod$dd4f06a4ba98f945361f3a45f42984e592ac1bec\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:242$753'.
|
|
Removing empty process `$paramod$dd4f06a4ba98f945361f3a45f42984e592ac1bec\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:242$753'.
|
|
Removing empty process `$paramod$8f592f3125e8f7c96bc997ed58933554526412a5\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:100$1347'.
|
|
Removing empty process `$paramod$8f592f3125e8f7c96bc997ed58933554526412a5\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:81$1346'.
|
|
Removing empty process `$paramod$8f592f3125e8f7c96bc997ed58933554526412a5\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:81$1345'.
|
|
Removing empty process `$paramod$8f592f3125e8f7c96bc997ed58933554526412a5\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:40$1344'.
|
|
Removing empty process `$paramod$8f592f3125e8f7c96bc997ed58933554526412a5\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:40$1343'.
|
|
Found and cleaned up 7 empty switches in `$paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/psram_controller.v:99$1242'.
|
|
Removing empty process `$paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/psram_controller.v:99$1242'.
|
|
Found and cleaned up 6 empty switches in `$paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010111.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/int8_memory_access.v:55$676'.
|
|
Removing empty process `$paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010111.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/int8_memory_access.v:55$676'.
|
|
Removing empty process `$paramod$c614a16d6b975c0ec2885ffa17a962bce4ddbcec\act_buffer.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/act_buffer.v:60$651'.
|
|
Found and cleaned up 1 empty switch in `$paramod$c614a16d6b975c0ec2885ffa17a962bce4ddbcec\act_buffer.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/act_buffer.v:55$644'.
|
|
Removing empty process `$paramod$c614a16d6b975c0ec2885ffa17a962bce4ddbcec\act_buffer.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/act_buffer.v:55$644'.
|
|
Found and cleaned up 9 empty switches in `$paramod$bcb9324e2b7cabc82145d6a09db8d736ca601b00\neuron_parallel.$proc$/tmp/before_rewrite/neuron_parallel.v:130$1324'.
|
|
Removing empty process `$paramod$bcb9324e2b7cabc82145d6a09db8d736ca601b00\neuron_parallel.$proc$/tmp/before_rewrite/neuron_parallel.v:130$1324'.
|
|
Found and cleaned up 8 empty switches in `\spi_slave.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_slave.v:119$12'.
|
|
Removing empty process `spi_slave.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_slave.v:119$12'.
|
|
Found and cleaned up 1 empty switch in `\spi_slave.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_slave.v:93$2'.
|
|
Removing empty process `spi_slave.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_slave.v:93$2'.
|
|
Found and cleaned up 1 empty switch in `\spi_slave.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_slave.v:71$1'.
|
|
Removing empty process `spi_slave.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_slave.v:71$1'.
|
|
Cleaned up 122 empty switches.
|
|
|
|
17.4.12. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module spi_neuron_top.
|
|
Optimizing module $paramod$b3f3d2413f22d50ebc275a55cbfefa4ff7d277a1\memory_interface.
|
|
<suppressed ~8 debug messages>
|
|
Optimizing module $paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010111.
|
|
<suppressed ~5 debug messages>
|
|
Optimizing module $paramod$80f5e68183ca7884165c68cdb28403ede9957037\neuron_memory.
|
|
<suppressed ~9 debug messages>
|
|
Optimizing module $paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.
|
|
<suppressed ~11 debug messages>
|
|
Optimizing module $paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.
|
|
<suppressed ~9 debug messages>
|
|
Optimizing module $paramod$dd4f06a4ba98f945361f3a45f42984e592ac1bec\spi_engine.
|
|
<suppressed ~19 debug messages>
|
|
Optimizing module $paramod$8f592f3125e8f7c96bc997ed58933554526412a5\mac8.
|
|
Optimizing module $paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller.
|
|
<suppressed ~4 debug messages>
|
|
Optimizing module $paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010111.
|
|
<suppressed ~15 debug messages>
|
|
Optimizing module $paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\mac_unit.
|
|
Optimizing module $paramod$c614a16d6b975c0ec2885ffa17a962bce4ddbcec\act_buffer.
|
|
Optimizing module $paramod$bcb9324e2b7cabc82145d6a09db8d736ca601b00\neuron_parallel.
|
|
<suppressed ~1 debug messages>
|
|
Optimizing module spi_slave.
|
|
<suppressed ~8 debug messages>
|
|
|
|
17.5. Executing CHECK pass (checking for obvious problems).
|
|
Checking module spi_neuron_top...
|
|
Checking module $paramod$b3f3d2413f22d50ebc275a55cbfefa4ff7d277a1\memory_interface...
|
|
Checking module $paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010111...
|
|
Checking module $paramod$80f5e68183ca7884165c68cdb28403ede9957037\neuron_memory...
|
|
Checking module $paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine...
|
|
Checking module $paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer...
|
|
Checking module $paramod$dd4f06a4ba98f945361f3a45f42984e592ac1bec\spi_engine...
|
|
Checking module $paramod$8f592f3125e8f7c96bc997ed58933554526412a5\mac8...
|
|
Checking module $paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller...
|
|
Checking module $paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010111...
|
|
Checking module $paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\mac_unit...
|
|
Checking module $paramod$c614a16d6b975c0ec2885ffa17a962bce4ddbcec\act_buffer...
|
|
Checking module $paramod$bcb9324e2b7cabc82145d6a09db8d736ca601b00\neuron_parallel...
|
|
Checking module spi_slave...
|
|
Found and reported 0 problems.
|
|
|
|
17.6. Executing FLATTEN pass (flatten design).
|
|
Deleting now unused module $paramod$b3f3d2413f22d50ebc275a55cbfefa4ff7d277a1\memory_interface.
|
|
Deleting now unused module $paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010111.
|
|
Deleting now unused module $paramod$80f5e68183ca7884165c68cdb28403ede9957037\neuron_memory.
|
|
Deleting now unused module $paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.
|
|
Deleting now unused module $paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.
|
|
Deleting now unused module $paramod$dd4f06a4ba98f945361f3a45f42984e592ac1bec\spi_engine.
|
|
Deleting now unused module $paramod$8f592f3125e8f7c96bc997ed58933554526412a5\mac8.
|
|
Deleting now unused module $paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller.
|
|
Deleting now unused module $paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010111.
|
|
Deleting now unused module $paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\mac_unit.
|
|
Deleting now unused module $paramod$c614a16d6b975c0ec2885ffa17a962bce4ddbcec\act_buffer.
|
|
Deleting now unused module $paramod$bcb9324e2b7cabc82145d6a09db8d736ca601b00\neuron_parallel.
|
|
Deleting now unused module spi_slave.
|
|
<suppressed ~16 debug messages>
|
|
|
|
17.7. Executing TRIBUF pass.
|
|
|
|
17.8. Executing DEMINOUT pass (demote inout ports to input or output).
|
|
|
|
17.9. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module spi_neuron_top.
|
|
<suppressed ~36 debug messages>
|
|
|
|
17.10. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \spi_neuron_top..
|
|
Removed 148 unused cells and 1598 unused wires.
|
|
<suppressed ~182 debug messages>
|
|
|
|
17.11. Executing CHECK pass (checking for obvious problems).
|
|
Checking module spi_neuron_top...
|
|
Found and reported 0 problems.
|
|
|
|
17.12. Executing OPT pass (performing simple optimizations).
|
|
|
|
17.12.1. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module spi_neuron_top.
|
|
|
|
17.12.2. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\spi_neuron_top'.
|
|
Computing hashes of 2002 cells of `\spi_neuron_top'.
|
|
Finding duplicate cells in `\spi_neuron_top'.
|
|
Computing hashes of 1677 cells of `\spi_neuron_top'.
|
|
Finding duplicate cells in `\spi_neuron_top'.
|
|
Computing hashes of 1669 cells of `\spi_neuron_top'.
|
|
Finding duplicate cells in `\spi_neuron_top'.
|
|
<suppressed ~999 debug messages>
|
|
Removed a total of 333 cells.
|
|
|
|
17.12.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \spi_neuron_top..
|
|
Creating internal representation of mux trees.
|
|
Evaluating internal representation of mux trees.
|
|
Replacing known input bits on port A of cell $flatten\u_graph_engine.\u_neuron.$procmux$5100: \u_graph_engine.u_neuron.busy -> 1'0
|
|
Replacing known input bits on port A of cell $flatten\u_graph_engine.\u_neuron.$procmux$5098: \u_graph_engine.u_neuron.busy -> 1'1
|
|
Replacing known input bits on port A of cell $flatten\u_neuron_memory.\u_neuron.$procmux$5100: \u_neuron_memory.u_neuron.busy -> 1'0
|
|
Replacing known input bits on port A of cell $flatten\u_neuron_memory.\u_neuron.$procmux$5098: \u_neuron_memory.u_neuron.busy -> 1'1
|
|
Analyzing evaluation results.
|
|
dead port 1/2 on $mux $flatten\u_graph_engine.$procmux$2377.
|
|
dead port 1/2 on $mux $flatten\u_graph_engine.$procmux$2387.
|
|
dead port 1/2 on $mux $flatten\u_graph_engine.$procmux$2397.
|
|
dead port 1/2 on $mux $flatten\u_graph_engine.$procmux$2407.
|
|
dead port 1/2 on $mux $flatten\u_graph_engine.$procmux$2417.
|
|
dead port 1/2 on $mux $flatten\u_graph_engine.$procmux$2896.
|
|
dead port 2/2 on $mux $flatten\u_neuron_memory.$procmux$1799.
|
|
dead port 1/2 on $mux $flatten\u_neuron_memory.$procmux$1802.
|
|
dead port 2/2 on $mux $flatten\u_neuron_memory.$procmux$1808.
|
|
dead port 1/2 on $mux $flatten\u_neuron_memory.$procmux$1811.
|
|
dead port 2/2 on $mux $flatten\u_neuron_memory.$procmux$1817.
|
|
dead port 1/2 on $mux $flatten\u_neuron_memory.$procmux$1820.
|
|
dead port 2/2 on $mux $flatten\u_neuron_memory.$procmux$1829.
|
|
dead port 1/2 on $mux $flatten\u_neuron_memory.$procmux$1832.
|
|
dead port 2/2 on $mux $flatten\u_neuron_memory.$procmux$1841.
|
|
dead port 1/2 on $mux $flatten\u_neuron_memory.$procmux$1844.
|
|
dead port 2/2 on $mux $flatten\u_neuron_memory.$procmux$1853.
|
|
dead port 1/2 on $mux $flatten\u_neuron_memory.$procmux$1856.
|
|
dead port 2/2 on $mux $flatten\u_neuron_memory.$procmux$1866.
|
|
dead port 1/2 on $mux $flatten\u_neuron_memory.$procmux$1869.
|
|
dead port 2/2 on $mux $flatten\u_neuron_memory.$procmux$1879.
|
|
dead port 1/2 on $mux $flatten\u_neuron_memory.$procmux$1882.
|
|
dead port 2/2 on $mux $flatten\u_neuron_memory.$procmux$1892.
|
|
dead port 1/2 on $mux $flatten\u_neuron_memory.$procmux$1895.
|
|
dead port 1/2 on $mux $flatten\u_neuron_memory.$procmux$1901.
|
|
dead port 1/2 on $mux $flatten\u_neuron_memory.$procmux$1907.
|
|
dead port 1/2 on $mux $flatten\u_neuron_memory.$procmux$1913.
|
|
dead port 1/2 on $mux $flatten\u_neuron_memory.$procmux$1922.
|
|
dead port 1/2 on $mux $flatten\u_neuron_memory.$procmux$1931.
|
|
dead port 1/2 on $mux $flatten\u_neuron_memory.$procmux$1940.
|
|
dead port 1/2 on $mux $flatten\u_neuron_memory.$procmux$1950.
|
|
dead port 1/2 on $mux $flatten\u_neuron_memory.$procmux$1960.
|
|
dead port 1/2 on $mux $flatten\u_neuron_memory.$procmux$1970.
|
|
dead port 2/2 on $mux $flatten\u_spi_engine.$procmux$4672.
|
|
dead port 2/2 on $mux $flatten\u_spi_engine.$procmux$4674.
|
|
dead port 2/2 on $mux $flatten\u_spi_engine.$procmux$4682.
|
|
dead port 2/2 on $mux $flatten\u_spi_engine.$procmux$4684.
|
|
dead port 2/2 on $mux $flatten\u_spi_engine.$procmux$4692.
|
|
Removed 38 multiplexer ports.
|
|
<suppressed ~1376 debug messages>
|
|
|
|
17.12.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \spi_neuron_top.
|
|
New ctrl vector for $pmux cell $flatten\u_layer_sequencer.$procmux$3283: $auto$opt_reduce.cc:137:opt_pmux$5628
|
|
Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$2394:
|
|
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$procmux$2394_Y
|
|
New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$procmux$2394_Y [0]
|
|
New connections: $flatten\u_graph_engine.$procmux$2394_Y [7:1] = { $flatten\u_graph_engine.$procmux$2394_Y [0] $flatten\u_graph_engine.$procmux$2394_Y [0] $flatten\u_graph_engine.$procmux$2394_Y [0] $flatten\u_graph_engine.$procmux$2394_Y [0] $flatten\u_graph_engine.$procmux$2394_Y [0] $flatten\u_graph_engine.$procmux$2394_Y [0] $flatten\u_graph_engine.$procmux$2394_Y [0] }
|
|
Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$2423:
|
|
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$863_EN[7:0]$933
|
|
New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$863_EN[7:0]$933 [0]
|
|
New connections: $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$863_EN[7:0]$933 [7:1] = { $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$863_EN[7:0]$933 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$863_EN[7:0]$933 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$863_EN[7:0]$933 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$863_EN[7:0]$933 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$863_EN[7:0]$933 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$863_EN[7:0]$933 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$863_EN[7:0]$933 [0] }
|
|
Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$2426:
|
|
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$862_EN[7:0]$932
|
|
New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$862_EN[7:0]$932 [0]
|
|
New connections: $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$862_EN[7:0]$932 [7:1] = { $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$862_EN[7:0]$932 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$862_EN[7:0]$932 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$862_EN[7:0]$932 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$862_EN[7:0]$932 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$862_EN[7:0]$932 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$862_EN[7:0]$932 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$862_EN[7:0]$932 [0] }
|
|
Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$2429:
|
|
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$861_EN[7:0]$931
|
|
New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$861_EN[7:0]$931 [0]
|
|
New connections: $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$861_EN[7:0]$931 [7:1] = { $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$861_EN[7:0]$931 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$861_EN[7:0]$931 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$861_EN[7:0]$931 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$861_EN[7:0]$931 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$861_EN[7:0]$931 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$861_EN[7:0]$931 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$861_EN[7:0]$931 [0] }
|
|
Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$2432:
|
|
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$860_EN[7:0]$930
|
|
New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$860_EN[7:0]$930 [0]
|
|
New connections: $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$860_EN[7:0]$930 [7:1] = { $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$860_EN[7:0]$930 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$860_EN[7:0]$930 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$860_EN[7:0]$930 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$860_EN[7:0]$930 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$860_EN[7:0]$930 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$860_EN[7:0]$930 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$860_EN[7:0]$930 [0] }
|
|
Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$2435:
|
|
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$859_EN[7:0]$929
|
|
New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$859_EN[7:0]$929 [0]
|
|
New connections: $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$859_EN[7:0]$929 [7:1] = { $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$859_EN[7:0]$929 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$859_EN[7:0]$929 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$859_EN[7:0]$929 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$859_EN[7:0]$929 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$859_EN[7:0]$929 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$859_EN[7:0]$929 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$859_EN[7:0]$929 [0] }
|
|
Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$2438:
|
|
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$858_EN[7:0]$928
|
|
New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$858_EN[7:0]$928 [0]
|
|
New connections: $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$858_EN[7:0]$928 [7:1] = { $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$858_EN[7:0]$928 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$858_EN[7:0]$928 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$858_EN[7:0]$928 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$858_EN[7:0]$928 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$858_EN[7:0]$928 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$858_EN[7:0]$928 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$858_EN[7:0]$928 [0] }
|
|
Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$2441:
|
|
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$857_EN[7:0]$927
|
|
New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$857_EN[7:0]$927 [0]
|
|
New connections: $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$857_EN[7:0]$927 [7:1] = { $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$857_EN[7:0]$927 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$857_EN[7:0]$927 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$857_EN[7:0]$927 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$857_EN[7:0]$927 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$857_EN[7:0]$927 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$857_EN[7:0]$927 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$857_EN[7:0]$927 [0] }
|
|
Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$2444:
|
|
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$856_EN[7:0]$926
|
|
New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$856_EN[7:0]$926 [0]
|
|
New connections: $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$856_EN[7:0]$926 [7:1] = { $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$856_EN[7:0]$926 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$856_EN[7:0]$926 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$856_EN[7:0]$926 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$856_EN[7:0]$926 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$856_EN[7:0]$926 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$856_EN[7:0]$926 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$856_EN[7:0]$926 [0] }
|
|
Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$2447:
|
|
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$855_EN[7:0]$925
|
|
New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$855_EN[7:0]$925 [0]
|
|
New connections: $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$855_EN[7:0]$925 [7:1] = { $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$855_EN[7:0]$925 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$855_EN[7:0]$925 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$855_EN[7:0]$925 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$855_EN[7:0]$925 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$855_EN[7:0]$925 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$855_EN[7:0]$925 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$855_EN[7:0]$925 [0] }
|
|
Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$2450:
|
|
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$854_EN[7:0]$924
|
|
New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$854_EN[7:0]$924 [0]
|
|
New connections: $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$854_EN[7:0]$924 [7:1] = { $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$854_EN[7:0]$924 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$854_EN[7:0]$924 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$854_EN[7:0]$924 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$854_EN[7:0]$924 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$854_EN[7:0]$924 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$854_EN[7:0]$924 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$854_EN[7:0]$924 [0] }
|
|
Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$2453:
|
|
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$853_EN[7:0]$923
|
|
New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$853_EN[7:0]$923 [0]
|
|
New connections: $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$853_EN[7:0]$923 [7:1] = { $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$853_EN[7:0]$923 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$853_EN[7:0]$923 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$853_EN[7:0]$923 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$853_EN[7:0]$923 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$853_EN[7:0]$923 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$853_EN[7:0]$923 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$853_EN[7:0]$923 [0] }
|
|
Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$2456:
|
|
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$852_EN[7:0]$922
|
|
New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$852_EN[7:0]$922 [0]
|
|
New connections: $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$852_EN[7:0]$922 [7:1] = { $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$852_EN[7:0]$922 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$852_EN[7:0]$922 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$852_EN[7:0]$922 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$852_EN[7:0]$922 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$852_EN[7:0]$922 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$852_EN[7:0]$922 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$852_EN[7:0]$922 [0] }
|
|
Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$2459:
|
|
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$851_EN[7:0]$921
|
|
New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$851_EN[7:0]$921 [0]
|
|
New connections: $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$851_EN[7:0]$921 [7:1] = { $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$851_EN[7:0]$921 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$851_EN[7:0]$921 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$851_EN[7:0]$921 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$851_EN[7:0]$921 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$851_EN[7:0]$921 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$851_EN[7:0]$921 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$851_EN[7:0]$921 [0] }
|
|
Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$2462:
|
|
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$850_EN[7:0]$920
|
|
New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$850_EN[7:0]$920 [0]
|
|
New connections: $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$850_EN[7:0]$920 [7:1] = { $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$850_EN[7:0]$920 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$850_EN[7:0]$920 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$850_EN[7:0]$920 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$850_EN[7:0]$920 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$850_EN[7:0]$920 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$850_EN[7:0]$920 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$850_EN[7:0]$920 [0] }
|
|
Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$2465:
|
|
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$849_EN[7:0]$919
|
|
New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$849_EN[7:0]$919 [0]
|
|
New connections: $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$849_EN[7:0]$919 [7:1] = { $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$849_EN[7:0]$919 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$849_EN[7:0]$919 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$849_EN[7:0]$919 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$849_EN[7:0]$919 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$849_EN[7:0]$919 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$849_EN[7:0]$919 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$849_EN[7:0]$919 [0] }
|
|
Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$2468:
|
|
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$848_EN[7:0]$918
|
|
New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$848_EN[7:0]$918 [0]
|
|
New connections: $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$848_EN[7:0]$918 [7:1] = { $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$848_EN[7:0]$918 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$848_EN[7:0]$918 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$848_EN[7:0]$918 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$848_EN[7:0]$918 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$848_EN[7:0]$918 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$848_EN[7:0]$918 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$848_EN[7:0]$918 [0] }
|
|
Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$2471:
|
|
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$847_EN[7:0]$917
|
|
New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$847_EN[7:0]$917 [0]
|
|
New connections: $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$847_EN[7:0]$917 [7:1] = { $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$847_EN[7:0]$917 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$847_EN[7:0]$917 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$847_EN[7:0]$917 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$847_EN[7:0]$917 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$847_EN[7:0]$917 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$847_EN[7:0]$917 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$847_EN[7:0]$917 [0] }
|
|
Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$2474:
|
|
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$846_EN[7:0]$916
|
|
New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$846_EN[7:0]$916 [0]
|
|
New connections: $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$846_EN[7:0]$916 [7:1] = { $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$846_EN[7:0]$916 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$846_EN[7:0]$916 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$846_EN[7:0]$916 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$846_EN[7:0]$916 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$846_EN[7:0]$916 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$846_EN[7:0]$916 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$846_EN[7:0]$916 [0] }
|
|
Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$2477:
|
|
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$845_EN[7:0]$915
|
|
New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$845_EN[7:0]$915 [0]
|
|
New connections: $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$845_EN[7:0]$915 [7:1] = { $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$845_EN[7:0]$915 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$845_EN[7:0]$915 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$845_EN[7:0]$915 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$845_EN[7:0]$915 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$845_EN[7:0]$915 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$845_EN[7:0]$915 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$845_EN[7:0]$915 [0] }
|
|
Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$2480:
|
|
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$844_EN[7:0]$914
|
|
New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$844_EN[7:0]$914 [0]
|
|
New connections: $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$844_EN[7:0]$914 [7:1] = { $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$844_EN[7:0]$914 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$844_EN[7:0]$914 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$844_EN[7:0]$914 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$844_EN[7:0]$914 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$844_EN[7:0]$914 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$844_EN[7:0]$914 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$844_EN[7:0]$914 [0] }
|
|
Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$2483:
|
|
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$843_EN[7:0]$913
|
|
New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$843_EN[7:0]$913 [0]
|
|
New connections: $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$843_EN[7:0]$913 [7:1] = { $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$843_EN[7:0]$913 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$843_EN[7:0]$913 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$843_EN[7:0]$913 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$843_EN[7:0]$913 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$843_EN[7:0]$913 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$843_EN[7:0]$913 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$843_EN[7:0]$913 [0] }
|
|
Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$2486:
|
|
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$842_EN[7:0]$912
|
|
New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$842_EN[7:0]$912 [0]
|
|
New connections: $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$842_EN[7:0]$912 [7:1] = { $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$842_EN[7:0]$912 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$842_EN[7:0]$912 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$842_EN[7:0]$912 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$842_EN[7:0]$912 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$842_EN[7:0]$912 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$842_EN[7:0]$912 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$842_EN[7:0]$912 [0] }
|
|
Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$2489:
|
|
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$841_EN[7:0]$911
|
|
New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$841_EN[7:0]$911 [0]
|
|
New connections: $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$841_EN[7:0]$911 [7:1] = { $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$841_EN[7:0]$911 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$841_EN[7:0]$911 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$841_EN[7:0]$911 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$841_EN[7:0]$911 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$841_EN[7:0]$911 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$841_EN[7:0]$911 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$841_EN[7:0]$911 [0] }
|
|
Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$2492:
|
|
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$840_EN[7:0]$910
|
|
New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$840_EN[7:0]$910 [0]
|
|
New connections: $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$840_EN[7:0]$910 [7:1] = { $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$840_EN[7:0]$910 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$840_EN[7:0]$910 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$840_EN[7:0]$910 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$840_EN[7:0]$910 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$840_EN[7:0]$910 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$840_EN[7:0]$910 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$840_EN[7:0]$910 [0] }
|
|
Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$2495:
|
|
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$839_EN[7:0]$909
|
|
New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$839_EN[7:0]$909 [0]
|
|
New connections: $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$839_EN[7:0]$909 [7:1] = { $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$839_EN[7:0]$909 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$839_EN[7:0]$909 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$839_EN[7:0]$909 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$839_EN[7:0]$909 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$839_EN[7:0]$909 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$839_EN[7:0]$909 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$839_EN[7:0]$909 [0] }
|
|
Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$2498:
|
|
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$838_EN[7:0]$908
|
|
New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$838_EN[7:0]$908 [0]
|
|
New connections: $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$838_EN[7:0]$908 [7:1] = { $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$838_EN[7:0]$908 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$838_EN[7:0]$908 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$838_EN[7:0]$908 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$838_EN[7:0]$908 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$838_EN[7:0]$908 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$838_EN[7:0]$908 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$838_EN[7:0]$908 [0] }
|
|
Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$2501:
|
|
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$837_EN[7:0]$907
|
|
New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$837_EN[7:0]$907 [0]
|
|
New connections: $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$837_EN[7:0]$907 [7:1] = { $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$837_EN[7:0]$907 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$837_EN[7:0]$907 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$837_EN[7:0]$907 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$837_EN[7:0]$907 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$837_EN[7:0]$907 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$837_EN[7:0]$907 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$837_EN[7:0]$907 [0] }
|
|
Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$2504:
|
|
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$836_EN[7:0]$906
|
|
New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$836_EN[7:0]$906 [0]
|
|
New connections: $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$836_EN[7:0]$906 [7:1] = { $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$836_EN[7:0]$906 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$836_EN[7:0]$906 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$836_EN[7:0]$906 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$836_EN[7:0]$906 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$836_EN[7:0]$906 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$836_EN[7:0]$906 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$836_EN[7:0]$906 [0] }
|
|
Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$2507:
|
|
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$835_EN[7:0]$905
|
|
New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$835_EN[7:0]$905 [0]
|
|
New connections: $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$835_EN[7:0]$905 [7:1] = { $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$835_EN[7:0]$905 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$835_EN[7:0]$905 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$835_EN[7:0]$905 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$835_EN[7:0]$905 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$835_EN[7:0]$905 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$835_EN[7:0]$905 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$835_EN[7:0]$905 [0] }
|
|
Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$2510:
|
|
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$834_EN[7:0]$904
|
|
New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$834_EN[7:0]$904 [0]
|
|
New connections: $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$834_EN[7:0]$904 [7:1] = { $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$834_EN[7:0]$904 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$834_EN[7:0]$904 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$834_EN[7:0]$904 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$834_EN[7:0]$904 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$834_EN[7:0]$904 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$834_EN[7:0]$904 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$834_EN[7:0]$904 [0] }
|
|
Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$2513:
|
|
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$833_EN[7:0]$903
|
|
New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$833_EN[7:0]$903 [0]
|
|
New connections: $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$833_EN[7:0]$903 [7:1] = { $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$833_EN[7:0]$903 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$833_EN[7:0]$903 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$833_EN[7:0]$903 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$833_EN[7:0]$903 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$833_EN[7:0]$903 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$833_EN[7:0]$903 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$833_EN[7:0]$903 [0] }
|
|
Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$2516:
|
|
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$832_EN[7:0]$902
|
|
New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$832_EN[7:0]$902 [0]
|
|
New connections: $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$832_EN[7:0]$902 [7:1] = { $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$832_EN[7:0]$902 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$832_EN[7:0]$902 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$832_EN[7:0]$902 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$832_EN[7:0]$902 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$832_EN[7:0]$902 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$832_EN[7:0]$902 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$832_EN[7:0]$902 [0] }
|
|
Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$2519:
|
|
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$831_EN[7:0]$901
|
|
New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$831_EN[7:0]$901 [0]
|
|
New connections: $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$831_EN[7:0]$901 [7:1] = { $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$831_EN[7:0]$901 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$831_EN[7:0]$901 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$831_EN[7:0]$901 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$831_EN[7:0]$901 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$831_EN[7:0]$901 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$831_EN[7:0]$901 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$831_EN[7:0]$901 [0] }
|
|
Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$2522:
|
|
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$830_EN[7:0]$900
|
|
New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$830_EN[7:0]$900 [0]
|
|
New connections: $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$830_EN[7:0]$900 [7:1] = { $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$830_EN[7:0]$900 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$830_EN[7:0]$900 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$830_EN[7:0]$900 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$830_EN[7:0]$900 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$830_EN[7:0]$900 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$830_EN[7:0]$900 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$830_EN[7:0]$900 [0] }
|
|
Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$2525:
|
|
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$829_EN[7:0]$899
|
|
New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$829_EN[7:0]$899 [0]
|
|
New connections: $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$829_EN[7:0]$899 [7:1] = { $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$829_EN[7:0]$899 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$829_EN[7:0]$899 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$829_EN[7:0]$899 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$829_EN[7:0]$899 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$829_EN[7:0]$899 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$829_EN[7:0]$899 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$829_EN[7:0]$899 [0] }
|
|
Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$2528:
|
|
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$828_EN[7:0]$898
|
|
New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$828_EN[7:0]$898 [0]
|
|
New connections: $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$828_EN[7:0]$898 [7:1] = { $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$828_EN[7:0]$898 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$828_EN[7:0]$898 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$828_EN[7:0]$898 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$828_EN[7:0]$898 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$828_EN[7:0]$898 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$828_EN[7:0]$898 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$828_EN[7:0]$898 [0] }
|
|
Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$2531:
|
|
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$827_EN[7:0]$897
|
|
New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$827_EN[7:0]$897 [0]
|
|
New connections: $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$827_EN[7:0]$897 [7:1] = { $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$827_EN[7:0]$897 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$827_EN[7:0]$897 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$827_EN[7:0]$897 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$827_EN[7:0]$897 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$827_EN[7:0]$897 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$827_EN[7:0]$897 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$827_EN[7:0]$897 [0] }
|
|
Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$2534:
|
|
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$826_EN[7:0]$896
|
|
New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$826_EN[7:0]$896 [0]
|
|
New connections: $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$826_EN[7:0]$896 [7:1] = { $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$826_EN[7:0]$896 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$826_EN[7:0]$896 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$826_EN[7:0]$896 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$826_EN[7:0]$896 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$826_EN[7:0]$896 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$826_EN[7:0]$896 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$826_EN[7:0]$896 [0] }
|
|
Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$2537:
|
|
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$825_EN[7:0]$895
|
|
New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$825_EN[7:0]$895 [0]
|
|
New connections: $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$825_EN[7:0]$895 [7:1] = { $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$825_EN[7:0]$895 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$825_EN[7:0]$895 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$825_EN[7:0]$895 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$825_EN[7:0]$895 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$825_EN[7:0]$895 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$825_EN[7:0]$895 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$825_EN[7:0]$895 [0] }
|
|
Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$2540:
|
|
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$824_EN[7:0]$894
|
|
New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$824_EN[7:0]$894 [0]
|
|
New connections: $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$824_EN[7:0]$894 [7:1] = { $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$824_EN[7:0]$894 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$824_EN[7:0]$894 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$824_EN[7:0]$894 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$824_EN[7:0]$894 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$824_EN[7:0]$894 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$824_EN[7:0]$894 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$824_EN[7:0]$894 [0] }
|
|
Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$2543:
|
|
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$823_EN[7:0]$893
|
|
New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$823_EN[7:0]$893 [0]
|
|
New connections: $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$823_EN[7:0]$893 [7:1] = { $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$823_EN[7:0]$893 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$823_EN[7:0]$893 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$823_EN[7:0]$893 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$823_EN[7:0]$893 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$823_EN[7:0]$893 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$823_EN[7:0]$893 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$823_EN[7:0]$893 [0] }
|
|
Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$2546:
|
|
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$822_EN[7:0]$892
|
|
New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$822_EN[7:0]$892 [0]
|
|
New connections: $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$822_EN[7:0]$892 [7:1] = { $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$822_EN[7:0]$892 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$822_EN[7:0]$892 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$822_EN[7:0]$892 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$822_EN[7:0]$892 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$822_EN[7:0]$892 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$822_EN[7:0]$892 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$822_EN[7:0]$892 [0] }
|
|
Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$2549:
|
|
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$821_EN[7:0]$891
|
|
New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$821_EN[7:0]$891 [0]
|
|
New connections: $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$821_EN[7:0]$891 [7:1] = { $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$821_EN[7:0]$891 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$821_EN[7:0]$891 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$821_EN[7:0]$891 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$821_EN[7:0]$891 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$821_EN[7:0]$891 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$821_EN[7:0]$891 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$821_EN[7:0]$891 [0] }
|
|
Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$2552:
|
|
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$820_EN[7:0]$890
|
|
New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$820_EN[7:0]$890 [0]
|
|
New connections: $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$820_EN[7:0]$890 [7:1] = { $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$820_EN[7:0]$890 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$820_EN[7:0]$890 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$820_EN[7:0]$890 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$820_EN[7:0]$890 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$820_EN[7:0]$890 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$820_EN[7:0]$890 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$820_EN[7:0]$890 [0] }
|
|
Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$2555:
|
|
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$819_EN[7:0]$889
|
|
New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$819_EN[7:0]$889 [0]
|
|
New connections: $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$819_EN[7:0]$889 [7:1] = { $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$819_EN[7:0]$889 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$819_EN[7:0]$889 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$819_EN[7:0]$889 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$819_EN[7:0]$889 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$819_EN[7:0]$889 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$819_EN[7:0]$889 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$819_EN[7:0]$889 [0] }
|
|
Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$2558:
|
|
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$818_EN[7:0]$888
|
|
New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$818_EN[7:0]$888 [0]
|
|
New connections: $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$818_EN[7:0]$888 [7:1] = { $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$818_EN[7:0]$888 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$818_EN[7:0]$888 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$818_EN[7:0]$888 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$818_EN[7:0]$888 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$818_EN[7:0]$888 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$818_EN[7:0]$888 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$818_EN[7:0]$888 [0] }
|
|
Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$2561:
|
|
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$817_EN[7:0]$887
|
|
New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$817_EN[7:0]$887 [0]
|
|
New connections: $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$817_EN[7:0]$887 [7:1] = { $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$817_EN[7:0]$887 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$817_EN[7:0]$887 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$817_EN[7:0]$887 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$817_EN[7:0]$887 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$817_EN[7:0]$887 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$817_EN[7:0]$887 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$817_EN[7:0]$887 [0] }
|
|
Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$2564:
|
|
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$816_EN[7:0]$886
|
|
New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$816_EN[7:0]$886 [0]
|
|
New connections: $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$816_EN[7:0]$886 [7:1] = { $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$816_EN[7:0]$886 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$816_EN[7:0]$886 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$816_EN[7:0]$886 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$816_EN[7:0]$886 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$816_EN[7:0]$886 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$816_EN[7:0]$886 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$816_EN[7:0]$886 [0] }
|
|
Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$2567:
|
|
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$815_EN[7:0]$885
|
|
New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$815_EN[7:0]$885 [0]
|
|
New connections: $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$815_EN[7:0]$885 [7:1] = { $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$815_EN[7:0]$885 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$815_EN[7:0]$885 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$815_EN[7:0]$885 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$815_EN[7:0]$885 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$815_EN[7:0]$885 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$815_EN[7:0]$885 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$815_EN[7:0]$885 [0] }
|
|
Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$2570:
|
|
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$814_EN[7:0]$884
|
|
New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$814_EN[7:0]$884 [0]
|
|
New connections: $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$814_EN[7:0]$884 [7:1] = { $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$814_EN[7:0]$884 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$814_EN[7:0]$884 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$814_EN[7:0]$884 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$814_EN[7:0]$884 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$814_EN[7:0]$884 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$814_EN[7:0]$884 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$814_EN[7:0]$884 [0] }
|
|
Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$2573:
|
|
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$813_EN[7:0]$883
|
|
New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$813_EN[7:0]$883 [0]
|
|
New connections: $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$813_EN[7:0]$883 [7:1] = { $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$813_EN[7:0]$883 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$813_EN[7:0]$883 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$813_EN[7:0]$883 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$813_EN[7:0]$883 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$813_EN[7:0]$883 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$813_EN[7:0]$883 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$813_EN[7:0]$883 [0] }
|
|
Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$2576:
|
|
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$812_EN[7:0]$882
|
|
New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$812_EN[7:0]$882 [0]
|
|
New connections: $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$812_EN[7:0]$882 [7:1] = { $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$812_EN[7:0]$882 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$812_EN[7:0]$882 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$812_EN[7:0]$882 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$812_EN[7:0]$882 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$812_EN[7:0]$882 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$812_EN[7:0]$882 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$812_EN[7:0]$882 [0] }
|
|
Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$2579:
|
|
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$811_EN[7:0]$881
|
|
New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$811_EN[7:0]$881 [0]
|
|
New connections: $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$811_EN[7:0]$881 [7:1] = { $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$811_EN[7:0]$881 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$811_EN[7:0]$881 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$811_EN[7:0]$881 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$811_EN[7:0]$881 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$811_EN[7:0]$881 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$811_EN[7:0]$881 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$811_EN[7:0]$881 [0] }
|
|
Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$2582:
|
|
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$810_EN[7:0]$880
|
|
New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$810_EN[7:0]$880 [0]
|
|
New connections: $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$810_EN[7:0]$880 [7:1] = { $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$810_EN[7:0]$880 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$810_EN[7:0]$880 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$810_EN[7:0]$880 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$810_EN[7:0]$880 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$810_EN[7:0]$880 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$810_EN[7:0]$880 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$810_EN[7:0]$880 [0] }
|
|
Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$2585:
|
|
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$809_EN[7:0]$879
|
|
New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$809_EN[7:0]$879 [0]
|
|
New connections: $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$809_EN[7:0]$879 [7:1] = { $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$809_EN[7:0]$879 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$809_EN[7:0]$879 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$809_EN[7:0]$879 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$809_EN[7:0]$879 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$809_EN[7:0]$879 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$809_EN[7:0]$879 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$809_EN[7:0]$879 [0] }
|
|
Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$2588:
|
|
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$808_EN[7:0]$878
|
|
New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$808_EN[7:0]$878 [0]
|
|
New connections: $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$808_EN[7:0]$878 [7:1] = { $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$808_EN[7:0]$878 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$808_EN[7:0]$878 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$808_EN[7:0]$878 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$808_EN[7:0]$878 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$808_EN[7:0]$878 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$808_EN[7:0]$878 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$808_EN[7:0]$878 [0] }
|
|
Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$2591:
|
|
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$807_EN[7:0]$877
|
|
New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$807_EN[7:0]$877 [0]
|
|
New connections: $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$807_EN[7:0]$877 [7:1] = { $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$807_EN[7:0]$877 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$807_EN[7:0]$877 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$807_EN[7:0]$877 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$807_EN[7:0]$877 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$807_EN[7:0]$877 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$807_EN[7:0]$877 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$807_EN[7:0]$877 [0] }
|
|
Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$2594:
|
|
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$806_EN[7:0]$876
|
|
New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$806_EN[7:0]$876 [0]
|
|
New connections: $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$806_EN[7:0]$876 [7:1] = { $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$806_EN[7:0]$876 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$806_EN[7:0]$876 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$806_EN[7:0]$876 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$806_EN[7:0]$876 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$806_EN[7:0]$876 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$806_EN[7:0]$876 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$806_EN[7:0]$876 [0] }
|
|
Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$2597:
|
|
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$805_EN[7:0]$875
|
|
New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$805_EN[7:0]$875 [0]
|
|
New connections: $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$805_EN[7:0]$875 [7:1] = { $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$805_EN[7:0]$875 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$805_EN[7:0]$875 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$805_EN[7:0]$875 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$805_EN[7:0]$875 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$805_EN[7:0]$875 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$805_EN[7:0]$875 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$805_EN[7:0]$875 [0] }
|
|
Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$2600:
|
|
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$804_EN[7:0]$874
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|
New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$804_EN[7:0]$874 [0]
|
|
New connections: $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$804_EN[7:0]$874 [7:1] = { $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$804_EN[7:0]$874 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$804_EN[7:0]$874 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$804_EN[7:0]$874 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$804_EN[7:0]$874 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$804_EN[7:0]$874 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$804_EN[7:0]$874 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$804_EN[7:0]$874 [0] }
|
|
Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$2603:
|
|
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$803_EN[7:0]$873
|
|
New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$803_EN[7:0]$873 [0]
|
|
New connections: $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$803_EN[7:0]$873 [7:1] = { $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$803_EN[7:0]$873 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$803_EN[7:0]$873 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$803_EN[7:0]$873 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$803_EN[7:0]$873 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$803_EN[7:0]$873 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$803_EN[7:0]$873 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$803_EN[7:0]$873 [0] }
|
|
Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$2606:
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|
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$802_EN[7:0]$872
|
|
New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$802_EN[7:0]$872 [0]
|
|
New connections: $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$802_EN[7:0]$872 [7:1] = { $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$802_EN[7:0]$872 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$802_EN[7:0]$872 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$802_EN[7:0]$872 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$802_EN[7:0]$872 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$802_EN[7:0]$872 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$802_EN[7:0]$872 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$802_EN[7:0]$872 [0] }
|
|
Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$2609:
|
|
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$801_EN[7:0]$871
|
|
New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$801_EN[7:0]$871 [0]
|
|
New connections: $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$801_EN[7:0]$871 [7:1] = { $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$801_EN[7:0]$871 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$801_EN[7:0]$871 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$801_EN[7:0]$871 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$801_EN[7:0]$871 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$801_EN[7:0]$871 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$801_EN[7:0]$871 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$801_EN[7:0]$871 [0] }
|
|
Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$2612:
|
|
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$800_EN[7:0]$870
|
|
New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$800_EN[7:0]$870 [0]
|
|
New connections: $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$800_EN[7:0]$870 [7:1] = { $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$800_EN[7:0]$870 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$800_EN[7:0]$870 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$800_EN[7:0]$870 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$800_EN[7:0]$870 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$800_EN[7:0]$870 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$800_EN[7:0]$870 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$800_EN[7:0]$870 [0] }
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New ctrl vector for $pmux cell $flatten\u_graph_engine.$procmux$2616: { $auto$opt_reduce.cc:137:opt_pmux$5630 $flatten\u_graph_engine.$procmux$2621_CMP }
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New ctrl vector for $pmux cell $flatten\u_spi_engine.$procmux$3880: { $flatten\u_spi_engine.$procmux$3881_CMP $auto$opt_reduce.cc:137:opt_pmux$5632 }
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|
Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$2893:
|
|
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$procmux$2893_Y
|
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New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$procmux$2893_Y [0]
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New connections: $flatten\u_graph_engine.$procmux$2893_Y [7:1] = { $flatten\u_graph_engine.$procmux$2893_Y [0] $flatten\u_graph_engine.$procmux$2893_Y [0] $flatten\u_graph_engine.$procmux$2893_Y [0] $flatten\u_graph_engine.$procmux$2893_Y [0] $flatten\u_graph_engine.$procmux$2893_Y [0] $flatten\u_graph_engine.$procmux$2893_Y [0] $flatten\u_graph_engine.$procmux$2893_Y [0] }
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New ctrl vector for $pmux cell $flatten\u_spi_engine.$procmux$4179: { $auto$opt_reduce.cc:137:opt_pmux$5634 $flatten\u_spi_engine.$procmux$4183_CMP $flatten\u_spi_engine.$procmux$4184_CMP $flatten\u_spi_engine.$procmux$4185_CMP $flatten\u_spi_engine.$procmux$4052_CTRL }
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New ctrl vector for $pmux cell $flatten\u_spi_engine.$procmux$3904: $auto$opt_reduce.cc:137:opt_pmux$5636
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|
New ctrl vector for $pmux cell $flatten\u_graph_engine.$procmux$3139: { $flatten\u_graph_engine.$procmux$2617_CMP $flatten\u_graph_engine.$procmux$2621_CMP $auto$opt_reduce.cc:137:opt_pmux$5638 }
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New ctrl vector for $pmux cell $flatten\u_spi_engine.$procmux$3765: $auto$opt_reduce.cc:137:opt_pmux$5640
|
|
Consolidated identical input bits for $mux cell $flatten\u_graph_engine.\u_act_buffer.$procmux$5056:
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Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.\u_act_buffer.$0$memwr$\mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/act_buffer.v:57$643_EN[7:0]$647
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New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.\u_act_buffer.$0$memwr$\mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/act_buffer.v:57$643_EN[7:0]$647 [0]
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New connections: $flatten\u_graph_engine.\u_act_buffer.$0$memwr$\mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/act_buffer.v:57$643_EN[7:0]$647 [7:1] = { $flatten\u_graph_engine.\u_act_buffer.$0$memwr$\mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/act_buffer.v:57$643_EN[7:0]$647 [0] $flatten\u_graph_engine.\u_act_buffer.$0$memwr$\mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/act_buffer.v:57$643_EN[7:0]$647 [0] $flatten\u_graph_engine.\u_act_buffer.$0$memwr$\mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/act_buffer.v:57$643_EN[7:0]$647 [0] $flatten\u_graph_engine.\u_act_buffer.$0$memwr$\mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/act_buffer.v:57$643_EN[7:0]$647 [0] $flatten\u_graph_engine.\u_act_buffer.$0$memwr$\mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/act_buffer.v:57$643_EN[7:0]$647 [0] $flatten\u_graph_engine.\u_act_buffer.$0$memwr$\mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/act_buffer.v:57$643_EN[7:0]$647 [0] $flatten\u_graph_engine.\u_act_buffer.$0$memwr$\mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/act_buffer.v:57$643_EN[7:0]$647 [0] }
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Consolidated identical input bits for $mux cell $flatten\u_neuron_memory.$procmux$1797:
|
|
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_neuron_memory.$procmux$1797_Y
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New ports: A=1'0, B=1'1, Y=$flatten\u_neuron_memory.$procmux$1797_Y [0]
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New connections: $flatten\u_neuron_memory.$procmux$1797_Y [7:1] = { $flatten\u_neuron_memory.$procmux$1797_Y [0] $flatten\u_neuron_memory.$procmux$1797_Y [0] $flatten\u_neuron_memory.$procmux$1797_Y [0] $flatten\u_neuron_memory.$procmux$1797_Y [0] $flatten\u_neuron_memory.$procmux$1797_Y [0] $flatten\u_neuron_memory.$procmux$1797_Y [0] $flatten\u_neuron_memory.$procmux$1797_Y [0] }
|
|
Consolidated identical input bits for $mux cell $flatten\u_neuron_memory.$procmux$1827:
|
|
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_neuron_memory.$procmux$1827_Y
|
|
New ports: A=1'0, B=1'1, Y=$flatten\u_neuron_memory.$procmux$1827_Y [0]
|
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New connections: $flatten\u_neuron_memory.$procmux$1827_Y [7:1] = { $flatten\u_neuron_memory.$procmux$1827_Y [0] $flatten\u_neuron_memory.$procmux$1827_Y [0] $flatten\u_neuron_memory.$procmux$1827_Y [0] $flatten\u_neuron_memory.$procmux$1827_Y [0] $flatten\u_neuron_memory.$procmux$1827_Y [0] $flatten\u_neuron_memory.$procmux$1827_Y [0] $flatten\u_neuron_memory.$procmux$1827_Y [0] }
|
|
Consolidated identical input bits for $mux cell $flatten\u_neuron_memory.$procmux$1864:
|
|
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_neuron_memory.$procmux$1864_Y
|
|
New ports: A=1'0, B=1'1, Y=$flatten\u_neuron_memory.$procmux$1864_Y [0]
|
|
New connections: $flatten\u_neuron_memory.$procmux$1864_Y [7:1] = { $flatten\u_neuron_memory.$procmux$1864_Y [0] $flatten\u_neuron_memory.$procmux$1864_Y [0] $flatten\u_neuron_memory.$procmux$1864_Y [0] $flatten\u_neuron_memory.$procmux$1864_Y [0] $flatten\u_neuron_memory.$procmux$1864_Y [0] $flatten\u_neuron_memory.$procmux$1864_Y [0] $flatten\u_neuron_memory.$procmux$1864_Y [0] }
|
|
Consolidated identical input bits for $mux cell $flatten\u_neuron_memory.$procmux$1988:
|
|
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_neuron_memory.$0$memwr$\y_reg$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:304$1113_EN[7:0]$1119
|
|
New ports: A=1'0, B=1'1, Y=$flatten\u_neuron_memory.$0$memwr$\y_reg$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:304$1113_EN[7:0]$1119 [0]
|
|
New connections: $flatten\u_neuron_memory.$0$memwr$\y_reg$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:304$1113_EN[7:0]$1119 [7:1] = { $flatten\u_neuron_memory.$0$memwr$\y_reg$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:304$1113_EN[7:0]$1119 [0] $flatten\u_neuron_memory.$0$memwr$\y_reg$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:304$1113_EN[7:0]$1119 [0] $flatten\u_neuron_memory.$0$memwr$\y_reg$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:304$1113_EN[7:0]$1119 [0] $flatten\u_neuron_memory.$0$memwr$\y_reg$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:304$1113_EN[7:0]$1119 [0] $flatten\u_neuron_memory.$0$memwr$\y_reg$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:304$1113_EN[7:0]$1119 [0] $flatten\u_neuron_memory.$0$memwr$\y_reg$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:304$1113_EN[7:0]$1119 [0] $flatten\u_neuron_memory.$0$memwr$\y_reg$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:304$1113_EN[7:0]$1119 [0] }
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New ctrl vector for $pmux cell $flatten\u_neuron_memory.$procmux$2203: { $flatten\u_neuron_memory.$procmux$1800_CMP $auto$opt_reduce.cc:137:opt_pmux$5642 $flatten\u_neuron_memory.$procmux$2020_CMP }
|
|
New ctrl vector for $pmux cell $flatten\u_spi_engine.$procmux$4644: $auto$opt_reduce.cc:137:opt_pmux$5644
|
|
New ctrl vector for $pmux cell $flatten\u_psram_ctrl.$procmux$4830: { $auto$opt_reduce.cc:137:opt_pmux$5646 $flatten\u_psram_ctrl.$procmux$4718_CMP }
|
|
New ctrl vector for $pmux cell $flatten\u_psram_ctrl.$procmux$4842: { $auto$opt_reduce.cc:137:opt_pmux$5648 $flatten\u_psram_ctrl.$procmux$4718_CMP }
|
|
Optimizing cells in module \spi_neuron_top.
|
|
Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$2670:
|
|
Old ports: A=$flatten\u_graph_engine.$2$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:496$865_EN[7:0]$1015, B=8'00000000, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:496$865_EN[7:0]$939
|
|
New ports: A=$flatten\u_graph_engine.$procmux$2893_Y [0], B=1'0, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:496$865_EN[7:0]$939 [0]
|
|
New connections: $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:496$865_EN[7:0]$939 [7:1] = { $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:496$865_EN[7:0]$939 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:496$865_EN[7:0]$939 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:496$865_EN[7:0]$939 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:496$865_EN[7:0]$939 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:496$865_EN[7:0]$939 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:496$865_EN[7:0]$939 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:496$865_EN[7:0]$939 [0] }
|
|
Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$2679:
|
|
Old ports: A=$flatten\u_graph_engine.$2$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:495$864_EN[7:0]$1012, B=8'00000000, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:495$864_EN[7:0]$936
|
|
New ports: A=$flatten\u_graph_engine.$procmux$2394_Y [0], B=1'0, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:495$864_EN[7:0]$936 [0]
|
|
New connections: $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:495$864_EN[7:0]$936 [7:1] = { $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:495$864_EN[7:0]$936 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:495$864_EN[7:0]$936 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:495$864_EN[7:0]$936 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:495$864_EN[7:0]$936 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:495$864_EN[7:0]$936 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:495$864_EN[7:0]$936 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:495$864_EN[7:0]$936 [0] }
|
|
Consolidated identical input bits for $mux cell $flatten\u_neuron_memory.$procmux$1898:
|
|
Old ports: A=8'00000000, B=$flatten\u_neuron_memory.$3$memwr$\y_reg$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:449$1116_EN[7:0]$1166, Y=$flatten\u_neuron_memory.$procmux$1898_Y
|
|
New ports: A=1'0, B=$flatten\u_neuron_memory.$procmux$1797_Y [0], Y=$flatten\u_neuron_memory.$procmux$1898_Y [0]
|
|
New connections: $flatten\u_neuron_memory.$procmux$1898_Y [7:1] = { $flatten\u_neuron_memory.$procmux$1898_Y [0] $flatten\u_neuron_memory.$procmux$1898_Y [0] $flatten\u_neuron_memory.$procmux$1898_Y [0] $flatten\u_neuron_memory.$procmux$1898_Y [0] $flatten\u_neuron_memory.$procmux$1898_Y [0] $flatten\u_neuron_memory.$procmux$1898_Y [0] $flatten\u_neuron_memory.$procmux$1898_Y [0] }
|
|
Consolidated identical input bits for $mux cell $flatten\u_neuron_memory.$procmux$1919:
|
|
Old ports: A=8'00000000, B=$flatten\u_neuron_memory.$3$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:390$1115_EN[7:0]$1158, Y=$flatten\u_neuron_memory.$procmux$1919_Y
|
|
New ports: A=1'0, B=$flatten\u_neuron_memory.$procmux$1827_Y [0], Y=$flatten\u_neuron_memory.$procmux$1919_Y [0]
|
|
New connections: $flatten\u_neuron_memory.$procmux$1919_Y [7:1] = { $flatten\u_neuron_memory.$procmux$1919_Y [0] $flatten\u_neuron_memory.$procmux$1919_Y [0] $flatten\u_neuron_memory.$procmux$1919_Y [0] $flatten\u_neuron_memory.$procmux$1919_Y [0] $flatten\u_neuron_memory.$procmux$1919_Y [0] $flatten\u_neuron_memory.$procmux$1919_Y [0] $flatten\u_neuron_memory.$procmux$1919_Y [0] }
|
|
Consolidated identical input bits for $mux cell $flatten\u_neuron_memory.$procmux$1947:
|
|
Old ports: A=8'00000000, B=$flatten\u_neuron_memory.$3$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:357$1114_EN[7:0]$1150, Y=$flatten\u_neuron_memory.$procmux$1947_Y
|
|
New ports: A=1'0, B=$flatten\u_neuron_memory.$procmux$1864_Y [0], Y=$flatten\u_neuron_memory.$procmux$1947_Y [0]
|
|
New connections: $flatten\u_neuron_memory.$procmux$1947_Y [7:1] = { $flatten\u_neuron_memory.$procmux$1947_Y [0] $flatten\u_neuron_memory.$procmux$1947_Y [0] $flatten\u_neuron_memory.$procmux$1947_Y [0] $flatten\u_neuron_memory.$procmux$1947_Y [0] $flatten\u_neuron_memory.$procmux$1947_Y [0] $flatten\u_neuron_memory.$procmux$1947_Y [0] $flatten\u_neuron_memory.$procmux$1947_Y [0] }
|
|
Optimizing cells in module \spi_neuron_top.
|
|
Consolidated identical input bits for $mux cell $flatten\u_neuron_memory.$procmux$2025:
|
|
Old ports: A=$flatten\u_neuron_memory.$2$memwr$\y_reg$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:449$1116_EN[7:0]$1147, B=8'00000000, Y=$flatten\u_neuron_memory.$0$memwr$\y_reg$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:449$1116_EN[7:0]$1128
|
|
New ports: A=$flatten\u_neuron_memory.$procmux$1898_Y [0], B=1'0, Y=$flatten\u_neuron_memory.$0$memwr$\y_reg$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:449$1116_EN[7:0]$1128 [0]
|
|
New connections: $flatten\u_neuron_memory.$0$memwr$\y_reg$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:449$1116_EN[7:0]$1128 [7:1] = { $flatten\u_neuron_memory.$0$memwr$\y_reg$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:449$1116_EN[7:0]$1128 [0] $flatten\u_neuron_memory.$0$memwr$\y_reg$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:449$1116_EN[7:0]$1128 [0] $flatten\u_neuron_memory.$0$memwr$\y_reg$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:449$1116_EN[7:0]$1128 [0] $flatten\u_neuron_memory.$0$memwr$\y_reg$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:449$1116_EN[7:0]$1128 [0] $flatten\u_neuron_memory.$0$memwr$\y_reg$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:449$1116_EN[7:0]$1128 [0] $flatten\u_neuron_memory.$0$memwr$\y_reg$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:449$1116_EN[7:0]$1128 [0] $flatten\u_neuron_memory.$0$memwr$\y_reg$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:449$1116_EN[7:0]$1128 [0] }
|
|
Consolidated identical input bits for $mux cell $flatten\u_neuron_memory.$procmux$2034:
|
|
Old ports: A=$flatten\u_neuron_memory.$2$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:390$1115_EN[7:0]$1144, B=8'00000000, Y=$flatten\u_neuron_memory.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:390$1115_EN[7:0]$1125
|
|
New ports: A=$flatten\u_neuron_memory.$procmux$1919_Y [0], B=1'0, Y=$flatten\u_neuron_memory.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:390$1115_EN[7:0]$1125 [0]
|
|
New connections: $flatten\u_neuron_memory.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:390$1115_EN[7:0]$1125 [7:1] = { $flatten\u_neuron_memory.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:390$1115_EN[7:0]$1125 [0] $flatten\u_neuron_memory.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:390$1115_EN[7:0]$1125 [0] $flatten\u_neuron_memory.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:390$1115_EN[7:0]$1125 [0] $flatten\u_neuron_memory.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:390$1115_EN[7:0]$1125 [0] $flatten\u_neuron_memory.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:390$1115_EN[7:0]$1125 [0] $flatten\u_neuron_memory.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:390$1115_EN[7:0]$1125 [0] $flatten\u_neuron_memory.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:390$1115_EN[7:0]$1125 [0] }
|
|
Consolidated identical input bits for $mux cell $flatten\u_neuron_memory.$procmux$2043:
|
|
Old ports: A=$flatten\u_neuron_memory.$2$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:357$1114_EN[7:0]$1141, B=8'00000000, Y=$flatten\u_neuron_memory.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:357$1114_EN[7:0]$1122
|
|
New ports: A=$flatten\u_neuron_memory.$procmux$1947_Y [0], B=1'0, Y=$flatten\u_neuron_memory.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:357$1114_EN[7:0]$1122 [0]
|
|
New connections: $flatten\u_neuron_memory.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:357$1114_EN[7:0]$1122 [7:1] = { $flatten\u_neuron_memory.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:357$1114_EN[7:0]$1122 [0] $flatten\u_neuron_memory.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:357$1114_EN[7:0]$1122 [0] $flatten\u_neuron_memory.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:357$1114_EN[7:0]$1122 [0] $flatten\u_neuron_memory.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:357$1114_EN[7:0]$1122 [0] $flatten\u_neuron_memory.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:357$1114_EN[7:0]$1122 [0] $flatten\u_neuron_memory.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:357$1114_EN[7:0]$1122 [0] $flatten\u_neuron_memory.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:357$1114_EN[7:0]$1122 [0] }
|
|
Optimizing cells in module \spi_neuron_top.
|
|
Performed a total of 90 changes.
|
|
|
|
17.12.5. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\spi_neuron_top'.
|
|
Computing hashes of 1642 cells of `\spi_neuron_top'.
|
|
Finding duplicate cells in `\spi_neuron_top'.
|
|
Computing hashes of 1548 cells of `\spi_neuron_top'.
|
|
Finding duplicate cells in `\spi_neuron_top'.
|
|
Computing hashes of 1545 cells of `\spi_neuron_top'.
|
|
Finding duplicate cells in `\spi_neuron_top'.
|
|
<suppressed ~291 debug messages>
|
|
Removed a total of 97 cells.
|
|
|
|
17.12.6. Executing OPT_DFF pass (perform DFF optimizations).
|
|
Setting constant 1-bit at position 0 on $flatten\u_psram_ctrl.$procdff$5498 ($dff) from module spi_neuron_top.
|
|
|
|
17.12.7. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \spi_neuron_top..
|
|
Removed 0 unused cells and 461 unused wires.
|
|
<suppressed ~1 debug messages>
|
|
|
|
17.12.8. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module spi_neuron_top.
|
|
|
|
17.12.9. Rerunning OPT passes. (Maybe there is more to do..)
|
|
|
|
17.12.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \spi_neuron_top..
|
|
Creating internal representation of mux trees.
|
|
Evaluating internal representation of mux trees.
|
|
Analyzing evaluation results.
|
|
Removed 0 multiplexer ports.
|
|
<suppressed ~1223 debug messages>
|
|
|
|
17.12.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \spi_neuron_top.
|
|
New ctrl vector for $pmux cell $flatten\u_spi_engine.$procmux$4120: { $flatten\u_spi_engine.$procmux$4121_CMP $flatten\u_spi_engine.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:218$749_Y $auto$opt_reduce.cc:137:opt_pmux$5650 $flatten\u_spi_engine.$procmux$3964_CMP $flatten\u_spi_engine.$procmux$3926_CMP $flatten\u_spi_engine.$procmux$3766_CMP $flatten\u_spi_engine.$procmux$3967_CMP $flatten\u_spi_engine.$procmux$3767_CMP $flatten\u_spi_engine.$procmux$3946_CMP $flatten\u_spi_engine.$procmux$3643_CMP $flatten\u_spi_engine.$procmux$3652_CMP $flatten\u_spi_engine.$procmux$3685_CMP $flatten\u_spi_engine.$procmux$3716_CMP }
|
|
New ctrl vector for $pmux cell $flatten\u_spi_engine.$procmux$3672: { $auto$opt_reduce.cc:137:opt_pmux$5652 $flatten\u_spi_engine.$procmux$3652_CMP }
|
|
New ctrl vector for $pmux cell $flatten\u_neuron_memory.$procmux$2004: { $flatten\u_neuron_memory.$procmux$1800_CMP $auto$opt_reduce.cc:137:opt_pmux$5654 $flatten\u_neuron_memory.$procmux$2020_CMP }
|
|
New ctrl vector for $pmux cell $flatten\u_neuron_memory.$procmux$2090: { $flatten\u_neuron_memory.$procmux$1800_CMP $auto$opt_reduce.cc:137:opt_pmux$5656 $flatten\u_neuron_memory.$procmux$2020_CMP }
|
|
New ctrl vector for $pmux cell $flatten\u_arbiter.$procmux$1703: { $auto$opt_reduce.cc:137:opt_pmux$5658 $flatten\u_arbiter.$procmux$1697_CMP }
|
|
New ctrl vector for $pmux cell $flatten\u_psram_ctrl.$procmux$4887: { $flatten\u_psram_ctrl.$procmux$4807_CMP $auto$opt_reduce.cc:137:opt_pmux$5660 $flatten\u_psram_ctrl.$procmux$4718_CMP $flatten\u_psram_ctrl.$procmux$4837_CMP }
|
|
Optimizing cells in module \spi_neuron_top.
|
|
Performed a total of 6 changes.
|
|
|
|
17.12.12. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\spi_neuron_top'.
|
|
Computing hashes of 1550 cells of `\spi_neuron_top'.
|
|
Finding duplicate cells in `\spi_neuron_top'.
|
|
Computing hashes of 1549 cells of `\spi_neuron_top'.
|
|
Finding duplicate cells in `\spi_neuron_top'.
|
|
<suppressed ~3 debug messages>
|
|
Removed a total of 1 cells.
|
|
|
|
17.12.13. Executing OPT_DFF pass (perform DFF optimizations).
|
|
|
|
17.12.14. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \spi_neuron_top..
|
|
Removed 0 unused cells and 1 unused wires.
|
|
<suppressed ~1 debug messages>
|
|
|
|
17.12.15. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module spi_neuron_top.
|
|
|
|
17.12.16. Rerunning OPT passes. (Maybe there is more to do..)
|
|
|
|
17.12.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \spi_neuron_top..
|
|
Creating internal representation of mux trees.
|
|
Evaluating internal representation of mux trees.
|
|
Analyzing evaluation results.
|
|
Removed 0 multiplexer ports.
|
|
<suppressed ~1204 debug messages>
|
|
|
|
17.12.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \spi_neuron_top.
|
|
Performed a total of 0 changes.
|
|
|
|
17.12.19. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\spi_neuron_top'.
|
|
Computing hashes of 1549 cells of `\spi_neuron_top'.
|
|
Finding duplicate cells in `\spi_neuron_top'.
|
|
Removed a total of 0 cells.
|
|
|
|
17.12.20. Executing OPT_DFF pass (perform DFF optimizations).
|
|
|
|
17.12.21. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \spi_neuron_top..
|
|
|
|
17.12.22. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module spi_neuron_top.
|
|
|
|
17.12.23. Finished fast OPT passes. (There is nothing left to do.)
|
|
|
|
17.13. Executing FSM pass (extract and optimize FSM).
|
|
|
|
17.13.1. Executing FSM_DETECT pass (finding FSMs in design).
|
|
Found FSM state register spi_neuron_top.u_neuron_memory.state.
|
|
Not marking spi_neuron_top.u_neuron_memory.access_wdata as FSM state register:
|
|
Users of register don't seem to benefit from recoding.
|
|
Found FSM state register spi_neuron_top.u_graph_engine.state.
|
|
Found FSM state register spi_neuron_top.u_layer_sequencer.state.
|
|
Found FSM state register spi_neuron_top.u_neuron_memory.u_mem.state.
|
|
Found FSM state register spi_neuron_top.u_arbiter.owner.
|
|
Found FSM state register spi_neuron_top.u_spi_engine.resp_len.
|
|
Found FSM state register spi_neuron_top.u_spi_engine.state.
|
|
Found FSM state register spi_neuron_top.u_int8_access.state.
|
|
Found FSM state register spi_neuron_top.u_memory_if.state.
|
|
Found FSM state register spi_neuron_top.u_psram_ctrl.state.
|
|
|
|
17.13.2. Executing FSM_EXTRACT pass (extracting FSM from design).
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Extracting FSM `\u_neuron_memory.state' from module `\spi_neuron_top'.
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found $dff cell for state register: $flatten\u_neuron_memory.$procdff$5306
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root of input selection tree: $flatten\u_neuron_memory.$0\state[3:0]
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found reset state: 4'0000 (guessed from mux tree)
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found ctrl input: \graph_rst
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found ctrl input: $flatten\u_neuron_memory.$procmux$1800_CMP
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found ctrl input: $flatten\u_neuron_memory.$procmux$1993_CMP
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found ctrl input: $flatten\u_neuron_memory.$procmux$2192_CMP
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found ctrl input: $flatten\u_neuron_memory.$procmux$1830_CMP
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found ctrl input: $flatten\u_neuron_memory.$procmux$1867_CMP
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found ctrl input: $flatten\u_neuron_memory.$procmux$2020_CMP
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found state code: 4'0000
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found ctrl input: \u_neuron_memory.u_neuron.done
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found ctrl input: $flatten\u_neuron_memory.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:451$1168_Y
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found state code: 4'0010
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found state code: 4'0101
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found ctrl input: \u_neuron_memory.u_mem.ready
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found state code: 4'0100
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found ctrl input: $flatten\u_neuron_memory.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:359$1152_Y
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found state code: 4'0011
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found ctrl input: \mux_nm_start
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found state code: 4'0001
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found ctrl output: $flatten\u_neuron_memory.$procmux$2192_CMP
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found ctrl output: $flatten\u_neuron_memory.$procmux$2020_CMP
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found ctrl output: $flatten\u_neuron_memory.$procmux$1993_CMP
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found ctrl output: $flatten\u_neuron_memory.$procmux$1867_CMP
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found ctrl output: $flatten\u_neuron_memory.$procmux$1830_CMP
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found ctrl output: $flatten\u_neuron_memory.$procmux$1800_CMP
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ctrl inputs: { $flatten\u_neuron_memory.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:359$1152_Y $flatten\u_neuron_memory.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:451$1168_Y \u_neuron_memory.u_mem.ready \u_neuron_memory.u_neuron.done \mux_nm_start \graph_rst }
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ctrl outputs: { $flatten\u_neuron_memory.$0\state[3:0] $flatten\u_neuron_memory.$procmux$1800_CMP $flatten\u_neuron_memory.$procmux$1830_CMP $flatten\u_neuron_memory.$procmux$1867_CMP $flatten\u_neuron_memory.$procmux$1993_CMP $flatten\u_neuron_memory.$procmux$2020_CMP $flatten\u_neuron_memory.$procmux$2192_CMP }
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transition: 4'0000 6'----00 -> 4'0000 10'0000000010
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transition: 4'0000 6'----10 -> 4'0001 10'0001000010
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transition: 4'0000 6'-----1 -> 4'0000 10'0000000010
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transition: 4'0100 6'-----0 -> 4'0101 10'0101000100
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transition: 4'0100 6'-----1 -> 4'0000 10'0000000100
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transition: 4'0010 6'--0--0 -> 4'0010 10'0010010000
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transition: 4'0010 6'0-1--0 -> 4'0010 10'0010010000
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transition: 4'0010 6'1-1--0 -> 4'0011 10'0011010000
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transition: 4'0010 6'-----1 -> 4'0000 10'0000010000
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transition: 4'0001 6'--0--0 -> 4'0001 10'0001001000
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transition: 4'0001 6'0-1--0 -> 4'0001 10'0001001000
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transition: 4'0001 6'1-1--0 -> 4'0010 10'0010001000
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transition: 4'0001 6'-----1 -> 4'0000 10'0000001000
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transition: 4'0101 6'---0-0 -> 4'0101 10'0101100000
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transition: 4'0101 6'-0-1-0 -> 4'0010 10'0010100000
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transition: 4'0101 6'-1-1-0 -> 4'0000 10'0000100000
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transition: 4'0101 6'-----1 -> 4'0000 10'0000100000
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transition: 4'0011 6'--0--0 -> 4'0011 10'0011000001
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transition: 4'0011 6'--1--0 -> 4'0100 10'0100000001
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transition: 4'0011 6'-----1 -> 4'0000 10'0000000001
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Extracting FSM `\u_graph_engine.state' from module `\spi_neuron_top'.
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found $dff cell for state register: $flatten\u_graph_engine.$procdff$5334
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root of input selection tree: $flatten\u_graph_engine.$0\state[3:0]
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found reset state: 4'0000 (guessed from mux tree)
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found ctrl input: \graph_rst
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found ctrl input: $flatten\u_graph_engine.$procmux$2656_CMP
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found ctrl input: $flatten\u_graph_engine.$procmux$2617_CMP
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found ctrl input: $flatten\u_graph_engine.$procmux$2642_CMP
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found ctrl input: $flatten\u_graph_engine.$procmux$2632_CMP
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found ctrl input: $flatten\u_graph_engine.$procmux$2375_CMP
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found ctrl input: $flatten\u_graph_engine.$procmux$2261_CMP
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found ctrl input: $flatten\u_graph_engine.$procmux$2621_CMP
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found ctrl input: $flatten\u_graph_engine.$procmux$2296_CMP
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found ctrl input: $flatten\u_graph_engine.$procmux$2622_CMP
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found ctrl input: $flatten\u_graph_engine.$procmux$2645_CMP
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found ctrl input: $flatten\u_graph_engine.$procmux$2623_CMP
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found ctrl input: $flatten\u_graph_engine.$procmux$2917_CTRL
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found state code: 4'0000
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found ctrl input: \u_arbiter.c_ready
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found ctrl input: $flatten\u_graph_engine.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:527$1041_Y
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found state code: 4'0011
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found state code: 4'1011
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found ctrl input: \u_graph_engine.u_neuron.done
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found ctrl input: \u_graph_engine.is_output_sink
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found state code: 4'1010
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found state code: 4'1001
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found ctrl input: $flatten\u_graph_engine.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:498$1038_Y
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found state code: 4'0101
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found state code: 4'1000
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found ctrl input: $flatten\u_graph_engine.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:449$1030_Y
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found ctrl input: $flatten\u_graph_engine.$logic_or$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:456$1035_Y
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found state code: 4'0111
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found state code: 4'1100
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found ctrl input: $flatten\u_graph_engine.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:420$1026_Y
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found state code: 4'0110
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found ctrl input: $flatten\u_graph_engine.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:389$1021_Y
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found state code: 4'0100
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found ctrl input: $flatten\u_graph_engine.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:346$1018_Y
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found state code: 4'0001
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found state code: 4'0010
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found ctrl input: \graph_run_start
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found ctrl output: $flatten\u_graph_engine.$procmux$2917_CMP [1]
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found ctrl output: $flatten\u_graph_engine.$procmux$2917_CMP [0]
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found ctrl output: $flatten\u_graph_engine.$procmux$2656_CMP
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found ctrl output: $flatten\u_graph_engine.$procmux$2645_CMP
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found ctrl output: $flatten\u_graph_engine.$procmux$2642_CMP
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found ctrl output: $flatten\u_graph_engine.$procmux$2632_CMP
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found ctrl output: $flatten\u_graph_engine.$procmux$2623_CMP
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found ctrl output: $flatten\u_graph_engine.$procmux$2622_CMP
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found ctrl output: $flatten\u_graph_engine.$procmux$2621_CMP
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found ctrl output: $flatten\u_graph_engine.$procmux$2617_CMP
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found ctrl output: $flatten\u_graph_engine.$procmux$2375_CMP
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found ctrl output: $flatten\u_graph_engine.$procmux$2296_CMP
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found ctrl output: $flatten\u_graph_engine.$procmux$2261_CMP
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ctrl inputs: { \u_graph_engine.is_output_sink $flatten\u_graph_engine.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:346$1018_Y $flatten\u_graph_engine.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:389$1021_Y $flatten\u_graph_engine.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:420$1026_Y $flatten\u_graph_engine.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:449$1030_Y $flatten\u_graph_engine.$logic_or$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:456$1035_Y $flatten\u_graph_engine.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:498$1038_Y $flatten\u_graph_engine.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:527$1041_Y $flatten\u_graph_engine.$procmux$2917_CTRL \u_graph_engine.u_neuron.done \u_arbiter.c_ready \graph_rst \graph_run_start }
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ctrl outputs: { $flatten\u_graph_engine.$0\state[3:0] $flatten\u_graph_engine.$procmux$2261_CMP $flatten\u_graph_engine.$procmux$2296_CMP $flatten\u_graph_engine.$procmux$2375_CMP $flatten\u_graph_engine.$procmux$2617_CMP $flatten\u_graph_engine.$procmux$2621_CMP $flatten\u_graph_engine.$procmux$2622_CMP $flatten\u_graph_engine.$procmux$2623_CMP $flatten\u_graph_engine.$procmux$2632_CMP $flatten\u_graph_engine.$procmux$2642_CMP $flatten\u_graph_engine.$procmux$2645_CMP $flatten\u_graph_engine.$procmux$2656_CMP $flatten\u_graph_engine.$procmux$2917_CMP }
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transition: 4'0000 13'-----------00 -> 4'0000 17'00000000000000001
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transition: 4'0000 13'-----------01 -> 4'0001 17'00010000000000001
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transition: 4'0000 13'-----------1- -> 4'0000 17'00000000000000001
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transition: 4'1000 13'-----------0- -> 4'1001 17'10010000000100000
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transition: 4'1000 13'-----------1- -> 4'0000 17'00000000000100000
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transition: 4'0100 13'----------00- -> 4'0100 17'01000100000000000
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transition: 4'0100 13'--0-------10- -> 4'0011 17'00110100000000000
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transition: 4'0100 13'--1-------10- -> 4'0101 17'01010100000000000
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transition: 4'0100 13'-----------1- -> 4'0000 17'00000100000000000
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transition: 4'1100 13'-----------00 -> 4'1100 17'11000000000000010
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transition: 4'1100 13'-----------01 -> 4'0001 17'00010000000000010
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transition: 4'1100 13'-----------1- -> 4'0000 17'00000000000000010
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transition: 4'0010 13'----------00- -> 4'0010 17'00100000000001000
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transition: 4'0010 13'-0--------10- -> 4'0001 17'00010000000001000
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transition: 4'0010 13'-1--------10- -> 4'0011 17'00110000000001000
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transition: 4'0010 13'-----------1- -> 4'0000 17'00000000000001000
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transition: 4'1010 13'-----------0- -> 4'1011 17'10110001000000000
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transition: 4'1010 13'-----------1- -> 4'0000 17'00000001000000000
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transition: 4'0110 13'----------00- -> 4'0110 17'01101000000000000
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transition: 4'0110 13'----0-----10- -> 4'0101 17'01011000000000000
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transition: 4'0110 13'----10----10- -> 4'0111 17'01111000000000000
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transition: 4'0110 13'----11----10- -> 4'1100 17'11001000000000000
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transition: 4'0110 13'-----------1- -> 4'0000 17'00001000000000000
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transition: 4'0001 13'-----------0- -> 4'0010 17'00100000001000000
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transition: 4'0001 13'-----------1- -> 4'0000 17'00000000001000000
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transition: 4'1001 13'---------0-0- -> 4'1001 17'10010000000010000
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transition: 4'1001 13'0------0-1-0- -> 4'0011 17'00110000000010000
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transition: 4'1001 13'0------1-1-0- -> 4'0000 17'00000000000010000
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transition: 4'1001 13'1--------1-0- -> 4'1010 17'10100000000010000
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transition: 4'1001 13'-----------1- -> 4'0000 17'00000000000010000
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transition: 4'0101 13'---0-------0- -> 4'0110 17'01100000100000000
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transition: 4'0101 13'---1-------0- -> 4'1100 17'11000000100000000
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transition: 4'0101 13'-----------1- -> 4'0000 17'00000000100000000
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transition: 4'0011 13'-----------0- -> 4'0100 17'01000000010000000
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transition: 4'0011 13'-----------1- -> 4'0000 17'00000000010000000
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transition: 4'1011 13'----------00- -> 4'1011 17'10110000000000100
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transition: 4'1011 13'-------0--10- -> 4'0011 17'00110000000000100
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transition: 4'1011 13'-------1--10- -> 4'0000 17'00000000000000100
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transition: 4'1011 13'-----------1- -> 4'0000 17'00000000000000100
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transition: 4'0111 13'------0----0- -> 4'0101 17'01010010000000000
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transition: 4'0111 13'------1----0- -> 4'1000 17'10000010000000000
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transition: 4'0111 13'-----------1- -> 4'0000 17'00000010000000000
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Extracting FSM `\u_layer_sequencer.state' from module `\spi_neuron_top'.
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found $dff cell for state register: $flatten\u_layer_sequencer.$procdff$5434
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root of input selection tree: $flatten\u_layer_sequencer.$0\state[3:0]
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found reset state: 4'0000 (guessed from mux tree)
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found ctrl input: \rst
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found ctrl input: $flatten\u_layer_sequencer.$procmux$3305_CMP
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found ctrl input: $flatten\u_layer_sequencer.$procmux$3284_CMP
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found ctrl input: $flatten\u_layer_sequencer.$procmux$3308_CMP
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found ctrl input: $flatten\u_layer_sequencer.$procmux$3294_CMP
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found ctrl input: $flatten\u_layer_sequencer.$procmux$3161_CMP
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found ctrl input: $flatten\u_layer_sequencer.$procmux$3285_CMP
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found ctrl input: $flatten\u_layer_sequencer.$procmux$3325_CMP
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found state code: 4'0000
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found ctrl input: \u_arbiter.c_ready
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found ctrl input: $flatten\u_layer_sequencer.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:301$793_Y
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found state code: 4'0101
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found ctrl input: $flatten\u_layer_sequencer.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:303$795_Y
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found state code: 4'0001
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found state code: 4'0110
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found ctrl input: \u_neuron_memory.done
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found state code: 4'0100
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found ctrl input: $flatten\u_layer_sequencer.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:235$782_Y
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found state code: 4'0011
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found state code: 4'0010
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found ctrl input: \seq_run_start
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found ctrl output: $flatten\u_layer_sequencer.$procmux$3325_CMP
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found ctrl output: $flatten\u_layer_sequencer.$procmux$3308_CMP
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found ctrl output: $flatten\u_layer_sequencer.$procmux$3305_CMP
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found ctrl output: $flatten\u_layer_sequencer.$procmux$3294_CMP
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found ctrl output: $flatten\u_layer_sequencer.$procmux$3285_CMP
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found ctrl output: $flatten\u_layer_sequencer.$procmux$3284_CMP
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found ctrl output: $flatten\u_layer_sequencer.$procmux$3161_CMP
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ctrl inputs: { $flatten\u_layer_sequencer.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:235$782_Y $flatten\u_layer_sequencer.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:301$793_Y $flatten\u_layer_sequencer.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:303$795_Y \u_neuron_memory.done \u_arbiter.c_ready \seq_run_start \rst }
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ctrl outputs: { $flatten\u_layer_sequencer.$0\state[3:0] $flatten\u_layer_sequencer.$procmux$3161_CMP $flatten\u_layer_sequencer.$procmux$3284_CMP $flatten\u_layer_sequencer.$procmux$3285_CMP $flatten\u_layer_sequencer.$procmux$3294_CMP $flatten\u_layer_sequencer.$procmux$3305_CMP $flatten\u_layer_sequencer.$procmux$3308_CMP $flatten\u_layer_sequencer.$procmux$3325_CMP }
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transition: 4'0000 7'-----00 -> 4'0000 11'00000000001
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transition: 4'0000 7'-----10 -> 4'0001 11'00010000001
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transition: 4'0000 7'------1 -> 4'0000 11'00000000001
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transition: 4'0100 7'---0--0 -> 4'0100 11'01000000010
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transition: 4'0100 7'---1--0 -> 4'0101 11'01010000010
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transition: 4'0100 7'------1 -> 4'0000 11'00000000010
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transition: 4'0010 7'----0-0 -> 4'0010 11'00101000000
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transition: 4'0010 7'0---1-0 -> 4'0001 11'00011000000
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transition: 4'0010 7'1---1-0 -> 4'0011 11'00111000000
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transition: 4'0010 7'------1 -> 4'0000 11'00001000000
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transition: 4'0110 7'----0-0 -> 4'0110 11'01100000100
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transition: 4'0110 7'-0--1-0 -> 4'0101 11'01010000100
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transition: 4'0110 7'-10-1-0 -> 4'0001 11'00010000100
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transition: 4'0110 7'-11-1-0 -> 4'0000 11'00000000100
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transition: 4'0110 7'------1 -> 4'0000 11'00000000100
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transition: 4'0001 7'------0 -> 4'0010 11'00100010000
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transition: 4'0001 7'------1 -> 4'0000 11'00000010000
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transition: 4'0101 7'------0 -> 4'0110 11'01100100000
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transition: 4'0101 7'------1 -> 4'0000 11'00000100000
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transition: 4'0011 7'------0 -> 4'0100 11'01000001000
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transition: 4'0011 7'------1 -> 4'0000 11'00000001000
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Extracting FSM `\u_neuron_memory.u_mem.state' from module `\spi_neuron_top'.
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found $dff cell for state register: $flatten\u_neuron_memory.\u_mem.$procdff$5507
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root of input selection tree: $flatten\u_neuron_memory.\u_mem.$0\state[1:0]
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found reset state: 2'00 (guessed from mux tree)
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found ctrl input: \graph_rst
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found ctrl input: $flatten\u_neuron_memory.\u_mem.$procmux$4966_CMP
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found ctrl input: $flatten\u_neuron_memory.\u_mem.$procmux$4958_CMP
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found state code: 2'00
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found ctrl input: \u_arbiter.b_ready
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found ctrl input: \u_neuron_memory.access_req
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found state code: 2'01
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found ctrl output: $flatten\u_neuron_memory.\u_mem.$procmux$4966_CMP
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found ctrl output: $flatten\u_neuron_memory.\u_mem.$procmux$4958_CMP
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ctrl inputs: { \u_neuron_memory.access_req \u_arbiter.b_ready \graph_rst }
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ctrl outputs: { $flatten\u_neuron_memory.\u_mem.$procmux$4966_CMP $flatten\u_neuron_memory.\u_mem.$procmux$4958_CMP $flatten\u_neuron_memory.\u_mem.$0\state[1:0] }
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transition: 2'00 3'0-0 -> 2'00 4'0100
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transition: 2'00 3'1-0 -> 2'01 4'0101
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transition: 2'00 3'--1 -> 2'00 4'0100
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transition: 2'01 3'-00 -> 2'01 4'1001
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transition: 2'01 3'-10 -> 2'00 4'1000
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transition: 2'01 3'--1 -> 2'00 4'1000
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Extracting FSM `\u_arbiter.owner' from module `\spi_neuron_top'.
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found $dff cell for state register: $flatten\u_arbiter.$procdff$5305
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root of input selection tree: $flatten\u_arbiter.$0\owner[1:0]
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found reset state: 2'00 (guessed from mux tree)
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found ctrl input: \rst
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found ctrl input: $flatten\u_arbiter.$procmux$1697_CMP
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found ctrl input: $auto$opt_reduce.cc:137:opt_pmux$5658
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found ctrl input: \u_neuron_memory.u_mem.mem_req
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found ctrl input: \portc_req
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found ctrl input: \u_spi_engine.ram_req
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found state code: 2'01
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found state code: 2'11
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found state code: 2'10
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found ctrl input: \u_int8_access.ready
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found state code: 2'00
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found ctrl output: $flatten\u_arbiter.$procmux$1697_CMP
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found ctrl output: $flatten\u_arbiter.$procmux$1681_CMP
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found ctrl output: $flatten\u_arbiter.$procmux$1672_CMP
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found ctrl output: $flatten\u_arbiter.$procmux$1664_CMP
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ctrl inputs: { \u_spi_engine.ram_req \u_neuron_memory.u_mem.mem_req \u_int8_access.ready \portc_req \rst $auto$opt_reduce.cc:137:opt_pmux$5658 }
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ctrl outputs: { $flatten\u_arbiter.$0\owner[1:0] $flatten\u_arbiter.$procmux$1664_CMP $flatten\u_arbiter.$procmux$1672_CMP $flatten\u_arbiter.$procmux$1681_CMP $flatten\u_arbiter.$procmux$1697_CMP }
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|
transition: 2'00 6'00-00- -> 2'00 6'000001
|
|
transition: 2'00 6'10-00- -> 2'01 6'010001
|
|
transition: 2'00 6'-0-10- -> 2'11 6'110001
|
|
transition: 2'00 6'-1--0- -> 2'10 6'100001
|
|
transition: 2'00 6'----1- -> 2'00 6'000001
|
|
transition: 2'10 6'--0-0- -> 2'10 6'100100
|
|
transition: 2'10 6'--1-0- -> 2'00 6'000100
|
|
transition: 2'10 6'----1- -> 2'00 6'000100
|
|
transition: 2'01 6'--0-0- -> 2'01 6'010010
|
|
transition: 2'01 6'--1-0- -> 2'00 6'000010
|
|
transition: 2'01 6'----1- -> 2'00 6'000010
|
|
transition: 2'11 6'--0-0- -> 2'11 6'111000
|
|
transition: 2'11 6'--1-0- -> 2'00 6'001000
|
|
transition: 2'11 6'----1- -> 2'00 6'001000
|
|
Extracting FSM `\u_spi_engine.resp_len' from module `\spi_neuron_top'.
|
|
found $dff cell for state register: $flatten\u_spi_engine.$procdff$5484
|
|
root of input selection tree: $flatten\u_spi_engine.$0\resp_len[3:0]
|
|
found reset state: 4'0000 (guessed from mux tree)
|
|
found ctrl input: \rst
|
|
found ctrl input: \u_spi_slave.cs_end
|
|
found ctrl input: $flatten\u_spi_engine.$procmux$3716_CMP
|
|
found ctrl input: \u_spi_slave.rx_valid
|
|
found ctrl input: $auto$opt_reduce.cc:137:opt_pmux$5632
|
|
found ctrl input: $flatten\u_spi_engine.$procmux$3881_CMP
|
|
found state code: 4'0001
|
|
found state code: 4'1011
|
|
found state code: 4'0000
|
|
ctrl inputs: { \u_spi_slave.rx_valid \u_spi_slave.cs_end $flatten\u_spi_engine.$procmux$3716_CMP $flatten\u_spi_engine.$procmux$3881_CMP \rst $auto$opt_reduce.cc:137:opt_pmux$5632 }
|
|
ctrl outputs: $flatten\u_spi_engine.$0\resp_len[3:0]
|
|
transition: 4'0000 6'-00-0- -> 4'0000 4'0000
|
|
transition: 4'0000 6'001-0- -> 4'0000 4'0000
|
|
transition: 4'0000 6'101000 -> 4'0000 4'0000
|
|
transition: 4'0000 6'10110- -> 4'1011 4'1011
|
|
transition: 4'0000 6'101-01 -> 4'0001 4'0001
|
|
transition: 4'0000 6'-1--0- -> 4'0000 4'0000
|
|
transition: 4'0000 6'----1- -> 4'0000 4'0000
|
|
transition: 4'0001 6'-00-0- -> 4'0001 4'0001
|
|
transition: 4'0001 6'001-0- -> 4'0001 4'0001
|
|
transition: 4'0001 6'101000 -> 4'0001 4'0001
|
|
transition: 4'0001 6'10110- -> 4'1011 4'1011
|
|
transition: 4'0001 6'101-01 -> 4'0001 4'0001
|
|
transition: 4'0001 6'-1--0- -> 4'0001 4'0001
|
|
transition: 4'0001 6'----1- -> 4'0000 4'0000
|
|
transition: 4'1011 6'-00-0- -> 4'1011 4'1011
|
|
transition: 4'1011 6'001-0- -> 4'1011 4'1011
|
|
transition: 4'1011 6'101000 -> 4'1011 4'1011
|
|
transition: 4'1011 6'10110- -> 4'1011 4'1011
|
|
transition: 4'1011 6'101-01 -> 4'0001 4'0001
|
|
transition: 4'1011 6'-1--0- -> 4'1011 4'1011
|
|
transition: 4'1011 6'----1- -> 4'0000 4'0000
|
|
Extracting FSM `\u_spi_engine.state' from module `\spi_neuron_top'.
|
|
found $dff cell for state register: $flatten\u_spi_engine.$procdff$5473
|
|
root of input selection tree: $flatten\u_spi_engine.$0\state[3:0]
|
|
found reset state: 4'0000 (guessed from mux tree)
|
|
found ctrl input: \rst
|
|
found ctrl input: \u_spi_slave.cs_end
|
|
found ctrl input: $flatten\u_spi_engine.$procmux$3716_CMP
|
|
found ctrl input: $flatten\u_spi_engine.$procmux$3685_CMP
|
|
found ctrl input: $flatten\u_spi_engine.$procmux$3652_CMP
|
|
found ctrl input: $flatten\u_spi_engine.$procmux$3643_CMP
|
|
found ctrl input: $flatten\u_spi_engine.$procmux$3946_CMP
|
|
found ctrl input: $flatten\u_spi_engine.$procmux$3767_CMP
|
|
found ctrl input: $flatten\u_spi_engine.$procmux$3967_CMP
|
|
found ctrl input: $flatten\u_spi_engine.$procmux$3766_CMP
|
|
found ctrl input: $flatten\u_spi_engine.$procmux$3926_CMP
|
|
found ctrl input: $flatten\u_spi_engine.$procmux$3964_CMP
|
|
found ctrl input: $auto$opt_reduce.cc:137:opt_pmux$5650
|
|
found ctrl input: $flatten\u_spi_engine.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:218$749_Y
|
|
found ctrl input: $flatten\u_spi_engine.$procmux$4121_CMP
|
|
found state code: 4'0000
|
|
found ctrl input: \u_spi_slave.rx_valid
|
|
found ctrl input: $flatten\u_spi_engine.$procmux$4052_CTRL
|
|
found ctrl input: $flatten\u_spi_engine.$procmux$4185_CMP
|
|
found ctrl input: $flatten\u_spi_engine.$procmux$4184_CMP
|
|
found ctrl input: $flatten\u_spi_engine.$procmux$4183_CMP
|
|
found ctrl input: $auto$opt_reduce.cc:137:opt_pmux$5634
|
|
found state code: 4'1011
|
|
found state code: 4'0010
|
|
found state code: 4'0001
|
|
found state code: 4'1100
|
|
found state code: 4'1101
|
|
found state code: 4'1010
|
|
found ctrl input: $flatten\u_spi_engine.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:489$762_Y
|
|
found ctrl input: $flatten\u_spi_engine.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:493$763_Y
|
|
found state code: 4'0011
|
|
found ctrl input: $flatten\u_spi_engine.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:540$765_Y
|
|
found ctrl input: $flatten\u_spi_engine.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:545$766_Y
|
|
found ctrl input: $flatten\u_spi_engine.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:549$767_Y
|
|
found state code: 4'0111
|
|
found state code: 4'0100
|
|
found state code: 4'0101
|
|
found state code: 4'0110
|
|
found ctrl input: \u_arbiter.a_ready
|
|
found ctrl input: $flatten\u_spi_engine.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:601$771_Y
|
|
found state code: 4'1000
|
|
found state code: 4'1001
|
|
found ctrl input: $flatten\u_spi_engine.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:707$778_Y
|
|
found ctrl output: $flatten\u_spi_engine.$procmux$3767_CMP
|
|
found ctrl output: $flatten\u_spi_engine.$procmux$3766_CMP
|
|
found ctrl output: $flatten\u_spi_engine.$procmux$4130_CMP
|
|
found ctrl output: $flatten\u_spi_engine.$procmux$4121_CMP
|
|
found ctrl output: $flatten\u_spi_engine.$procmux$3685_CMP
|
|
found ctrl output: $flatten\u_spi_engine.$procmux$3643_CMP
|
|
found ctrl output: $flatten\u_spi_engine.$procmux$3652_CMP
|
|
found ctrl output: $flatten\u_spi_engine.$procmux$3967_CMP
|
|
found ctrl output: $flatten\u_spi_engine.$procmux$3964_CMP
|
|
found ctrl output: $flatten\u_spi_engine.$procmux$3946_CMP
|
|
found ctrl output: $flatten\u_spi_engine.$procmux$3926_CMP
|
|
found ctrl output: $flatten\u_spi_engine.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:218$749_Y
|
|
found ctrl output: $flatten\u_spi_engine.$procmux$3716_CMP
|
|
found ctrl output: $flatten\u_spi_engine.$procmux$3817_CMP
|
|
ctrl inputs: { \u_spi_slave.rx_valid \u_spi_slave.cs_end $flatten\u_spi_engine.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:489$762_Y $flatten\u_spi_engine.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:493$763_Y $flatten\u_spi_engine.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:540$765_Y $flatten\u_spi_engine.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:545$766_Y $flatten\u_spi_engine.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:549$767_Y $flatten\u_spi_engine.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:601$771_Y $flatten\u_spi_engine.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:707$778_Y $flatten\u_spi_engine.$procmux$4052_CTRL $flatten\u_spi_engine.$procmux$4183_CMP $flatten\u_spi_engine.$procmux$4184_CMP $flatten\u_spi_engine.$procmux$4185_CMP \u_arbiter.a_ready \rst $auto$opt_reduce.cc:137:opt_pmux$5634 $auto$opt_reduce.cc:137:opt_pmux$5650 }
|
|
ctrl outputs: { $flatten\u_spi_engine.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:218$749_Y $flatten\u_spi_engine.$0\state[3:0] $flatten\u_spi_engine.$procmux$3643_CMP $flatten\u_spi_engine.$procmux$3652_CMP $flatten\u_spi_engine.$procmux$3685_CMP $flatten\u_spi_engine.$procmux$3716_CMP $flatten\u_spi_engine.$procmux$3766_CMP $flatten\u_spi_engine.$procmux$3767_CMP $flatten\u_spi_engine.$procmux$3817_CMP $flatten\u_spi_engine.$procmux$3926_CMP $flatten\u_spi_engine.$procmux$3946_CMP $flatten\u_spi_engine.$procmux$3964_CMP $flatten\u_spi_engine.$procmux$3967_CMP $flatten\u_spi_engine.$procmux$4121_CMP $flatten\u_spi_engine.$procmux$4130_CMP }
|
|
transition: 4'0000 17'00------------0-- -> 4'0000 18'000000001000000000
|
|
transition: 4'0000 17'10-------0000-00- -> 4'1011 18'010110001000000000
|
|
transition: 4'0000 17'10------------01- -> 4'1010 18'010100001000000000
|
|
transition: 4'0000 17'10--------1---0-- -> 4'1101 18'011010001000000000
|
|
transition: 4'0000 17'10---------1--0-- -> 4'1100 18'011000001000000000
|
|
transition: 4'0000 17'10----------1-0-- -> 4'0001 18'000010001000000000
|
|
transition: 4'0000 17'10-------1----0-- -> 4'0010 18'000100001000000000
|
|
transition: 4'0000 17'-1------------0-- -> 4'0000 18'000000001000000000
|
|
transition: 4'0000 17'--------------1-- -> 4'0000 18'000000001000000000
|
|
transition: 4'1000 17'-0-----------00-- -> 4'1000 18'010000000000100000
|
|
transition: 4'1000 17'-0-----------10-- -> 4'1001 18'010010000000100000
|
|
transition: 4'1000 17'-1------------0-- -> 4'0000 18'000000000000100000
|
|
transition: 4'1000 17'--------------1-- -> 4'0000 18'000000000000100000
|
|
transition: 4'0100 17'00------------0-- -> 4'0100 18'001000000000010000
|
|
transition: 4'0100 17'10------------0-- -> 4'0101 18'001010000000010000
|
|
transition: 4'0100 17'-1------------0-- -> 4'0000 18'000000000000010000
|
|
transition: 4'0100 17'--------------1-- -> 4'0000 18'000000000000010000
|
|
transition: 4'1100 17'00------------0-- -> 4'1100 18'011000000001000000
|
|
transition: 4'1100 17'10------------0-- -> 4'1011 18'010110000001000000
|
|
transition: 4'1100 17'-1------------0-- -> 4'0000 18'000000000001000000
|
|
transition: 4'1100 17'--------------1-- -> 4'0000 18'000000000001000000
|
|
transition: 4'0010 17'00------------0-- -> 4'0010 18'000100100000000000
|
|
transition: 4'0010 17'100-----------0-- -> 4'0010 18'000100100000000000
|
|
transition: 4'0010 17'1010----------0-- -> 4'0011 18'000110100000000000
|
|
transition: 4'0010 17'1011----------0-- -> 4'1011 18'010110100000000000
|
|
transition: 4'0010 17'-1------------0-- -> 4'0000 18'000000100000000000
|
|
transition: 4'0010 17'--------------1-- -> 4'0000 18'000000100000000000
|
|
transition: 4'1010 17'00------------0-- -> 4'1010 18'110100000000000000
|
|
transition: 4'1010 17'10------0-----0-- -> 4'1010 18'110100000000000000
|
|
transition: 4'1010 17'10------1-----0-- -> 4'1011 18'110110000000000000
|
|
transition: 4'1010 17'-1------------0-- -> 4'0000 18'100000000000000000
|
|
transition: 4'1010 17'--------------1-- -> 4'0000 18'100000000000000000
|
|
transition: 4'0110 17'-0-----------00-- -> 4'0110 18'001100000000000100
|
|
transition: 4'0110 17'-0-----0-----10-- -> 4'0100 18'001000000000000100
|
|
transition: 4'0110 17'-0-----1-----10-- -> 4'1011 18'010110000000000100
|
|
transition: 4'0110 17'-1------------0-- -> 4'0000 18'000000000000000100
|
|
transition: 4'0110 17'--------------1-- -> 4'0000 18'000000000000000100
|
|
transition: 4'0001 17'00------------0-- -> 4'0001 18'000010010000000000
|
|
transition: 4'0001 17'10------------0-- -> 4'0010 18'000100010000000000
|
|
transition: 4'0001 17'-1------------0-- -> 4'0000 18'000000010000000000
|
|
transition: 4'0001 17'--------------1-- -> 4'0000 18'000000010000000000
|
|
transition: 4'1001 17'00------------0-- -> 4'1001 18'010010000000001000
|
|
transition: 4'1001 17'10-----0------0-- -> 4'0111 18'001110000000001000
|
|
transition: 4'1001 17'10-----1------0-- -> 4'1011 18'010110000000001000
|
|
transition: 4'1001 17'-1------------0-- -> 4'0000 18'000000000000001000
|
|
transition: 4'1001 17'--------------1-- -> 4'0000 18'000000000000001000
|
|
transition: 4'0101 17'-0------------0-- -> 4'0110 18'001100000010000000
|
|
transition: 4'0101 17'-1------------0-- -> 4'0000 18'000000000010000000
|
|
transition: 4'0101 17'--------------1-- -> 4'0000 18'000000000010000000
|
|
transition: 4'1101 17'00------------0-- -> 4'1101 18'011010000000000001
|
|
transition: 4'1101 17'10------------0-- -> 4'1011 18'010110000000000001
|
|
transition: 4'1101 17'-1------------0-- -> 4'0000 18'000000000000000001
|
|
transition: 4'1101 17'--------------1-- -> 4'0000 18'000000000000000001
|
|
transition: 4'0011 17'00------------0-- -> 4'0011 18'000111000000000000
|
|
transition: 4'0011 17'10--0---------0-- -> 4'0011 18'000111000000000000
|
|
transition: 4'0011 17'10--100-------0-- -> 4'0111 18'001111000000000000
|
|
transition: 4'0011 17'10--101-------0-- -> 4'0100 18'001001000000000000
|
|
transition: 4'0011 17'10--11--------0-- -> 4'1011 18'010111000000000000
|
|
transition: 4'0011 17'-1------------0-- -> 4'0000 18'000001000000000000
|
|
transition: 4'0011 17'--------------1-- -> 4'0000 18'000001000000000000
|
|
transition: 4'1011 17'-0------------0-- -> 4'1011 18'010110000000000010
|
|
transition: 4'1011 17'-1------------0-- -> 4'0000 18'000000000000000010
|
|
transition: 4'1011 17'--------------1-- -> 4'0000 18'000000000000000010
|
|
transition: 4'0111 17'-0------------0-- -> 4'1000 18'010000000100000000
|
|
transition: 4'0111 17'-1------------0-- -> 4'0000 18'000000000100000000
|
|
transition: 4'0111 17'--------------1-- -> 4'0000 18'000000000100000000
|
|
Extracting FSM `\u_int8_access.state' from module `\spi_neuron_top'.
|
|
found $dff cell for state register: $flatten\u_int8_access.$procdff$5507
|
|
root of input selection tree: $flatten\u_int8_access.$0\state[1:0]
|
|
found reset state: 2'00 (guessed from mux tree)
|
|
found ctrl input: \rst
|
|
found ctrl input: $flatten\u_int8_access.$procmux$4966_CMP
|
|
found ctrl input: $flatten\u_int8_access.$procmux$4958_CMP
|
|
found state code: 2'00
|
|
found ctrl input: \u_memory_if.ready
|
|
found ctrl input: \u_arbiter.m_req
|
|
found state code: 2'01
|
|
found ctrl output: $flatten\u_int8_access.$procmux$4966_CMP
|
|
found ctrl output: $flatten\u_int8_access.$procmux$4958_CMP
|
|
ctrl inputs: { \u_arbiter.m_req \u_memory_if.ready \rst }
|
|
ctrl outputs: { $flatten\u_int8_access.$0\state[1:0] $flatten\u_int8_access.$procmux$4958_CMP $flatten\u_int8_access.$procmux$4966_CMP }
|
|
transition: 2'00 3'0-0 -> 2'00 4'0010
|
|
transition: 2'00 3'1-0 -> 2'01 4'0110
|
|
transition: 2'00 3'--1 -> 2'00 4'0010
|
|
transition: 2'01 3'-00 -> 2'01 4'0101
|
|
transition: 2'01 3'-10 -> 2'00 4'0001
|
|
transition: 2'01 3'--1 -> 2'00 4'0001
|
|
Extracting FSM `\u_memory_if.state' from module `\spi_neuron_top'.
|
|
found $dff cell for state register: $flatten\u_memory_if.$procdff$5286
|
|
root of input selection tree: $flatten\u_memory_if.$0\state[1:0]
|
|
found reset state: 2'00 (guessed from mux tree)
|
|
found ctrl input: \rst
|
|
found ctrl input: $flatten\u_memory_if.$procmux$1591_CMP
|
|
found ctrl input: $flatten\u_memory_if.$procmux$1583_CMP
|
|
found state code: 2'00
|
|
found ctrl input: \u_psram_ctrl.mem_ready
|
|
found ctrl input: \u_int8_access.mem_req
|
|
found state code: 2'01
|
|
found ctrl output: $flatten\u_memory_if.$procmux$1591_CMP
|
|
found ctrl output: $flatten\u_memory_if.$procmux$1583_CMP
|
|
ctrl inputs: { \u_int8_access.mem_req \u_psram_ctrl.mem_ready \rst }
|
|
ctrl outputs: { $flatten\u_memory_if.$0\state[1:0] $flatten\u_memory_if.$procmux$1583_CMP $flatten\u_memory_if.$procmux$1591_CMP }
|
|
transition: 2'00 3'0-0 -> 2'00 4'0010
|
|
transition: 2'00 3'1-0 -> 2'01 4'0110
|
|
transition: 2'00 3'--1 -> 2'00 4'0010
|
|
transition: 2'01 3'-00 -> 2'01 4'0101
|
|
transition: 2'01 3'-10 -> 2'00 4'0001
|
|
transition: 2'01 3'--1 -> 2'00 4'0001
|
|
Extracting FSM `\u_psram_ctrl.state' from module `\spi_neuron_top'.
|
|
found $dff cell for state register: $flatten\u_psram_ctrl.$procdff$5489
|
|
root of input selection tree: $flatten\u_psram_ctrl.$0\state[2:0]
|
|
found reset state: 3'000 (guessed from mux tree)
|
|
found ctrl input: \rst
|
|
found ctrl input: $flatten\u_psram_ctrl.$procmux$4807_CMP
|
|
found ctrl input: $flatten\u_psram_ctrl.$procmux$4712_CMP
|
|
found ctrl input: $flatten\u_psram_ctrl.$procmux$4737_CMP
|
|
found ctrl input: $flatten\u_psram_ctrl.$procmux$4718_CMP
|
|
found ctrl input: $flatten\u_psram_ctrl.$procmux$4837_CMP
|
|
found state code: 3'000
|
|
found state code: 3'001
|
|
found ctrl input: $flatten\u_psram_ctrl.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/psram_controller.v:292$1245_Y
|
|
found state code: 3'100
|
|
found ctrl input: \u_memory_if.mem_req
|
|
found ctrl input: \u_memory_if.mem_wr
|
|
found state code: 3'010
|
|
found state code: 3'011
|
|
found ctrl input: $flatten\u_psram_ctrl.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/psram_controller.v:179$1243_Y
|
|
found ctrl output: $flatten\u_psram_ctrl.$procmux$4837_CMP
|
|
found ctrl output: $flatten\u_psram_ctrl.$procmux$4807_CMP
|
|
found ctrl output: $flatten\u_psram_ctrl.$procmux$4737_CMP
|
|
found ctrl output: $flatten\u_psram_ctrl.$procmux$4718_CMP
|
|
found ctrl output: $flatten\u_psram_ctrl.$procmux$4712_CMP
|
|
ctrl inputs: { \u_memory_if.mem_req \u_memory_if.mem_wr $flatten\u_psram_ctrl.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/psram_controller.v:179$1243_Y $flatten\u_psram_ctrl.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/psram_controller.v:292$1245_Y \rst }
|
|
ctrl outputs: { $flatten\u_psram_ctrl.$0\state[2:0] $flatten\u_psram_ctrl.$procmux$4712_CMP $flatten\u_psram_ctrl.$procmux$4718_CMP $flatten\u_psram_ctrl.$procmux$4737_CMP $flatten\u_psram_ctrl.$procmux$4807_CMP $flatten\u_psram_ctrl.$procmux$4837_CMP }
|
|
transition: 3'000 5'--0-0 -> 3'000 8'00000001
|
|
transition: 3'000 5'--1-0 -> 3'001 8'00100001
|
|
transition: 3'000 5'----1 -> 3'000 8'00000001
|
|
transition: 3'100 5'----0 -> 3'001 8'00100010
|
|
transition: 3'100 5'----1 -> 3'000 8'00000010
|
|
transition: 3'010 5'---00 -> 3'010 8'01000100
|
|
transition: 3'010 5'---10 -> 3'001 8'00100100
|
|
transition: 3'010 5'----1 -> 3'000 8'00000100
|
|
transition: 3'001 5'0---0 -> 3'001 8'00101000
|
|
transition: 3'001 5'10--0 -> 3'010 8'01001000
|
|
transition: 3'001 5'11--0 -> 3'011 8'01101000
|
|
transition: 3'001 5'----1 -> 3'000 8'00001000
|
|
transition: 3'011 5'---00 -> 3'011 8'01110000
|
|
transition: 3'011 5'---10 -> 3'100 8'10010000
|
|
transition: 3'011 5'----1 -> 3'000 8'00010000
|
|
|
|
17.13.3. Executing FSM_OPT pass (simple optimizations of FSMs).
|
|
Optimizing FSM `$fsm$\u_psram_ctrl.state$5729' from module `\spi_neuron_top'.
|
|
Optimizing FSM `$fsm$\u_memory_if.state$5725' from module `\spi_neuron_top'.
|
|
Optimizing FSM `$fsm$\u_int8_access.state$5721' from module `\spi_neuron_top'.
|
|
Optimizing FSM `$fsm$\u_spi_engine.state$5705' from module `\spi_neuron_top'.
|
|
Removing unused input signal $auto$opt_reduce.cc:137:opt_pmux$5650.
|
|
Optimizing FSM `$fsm$\u_spi_engine.resp_len$5703' from module `\spi_neuron_top'.
|
|
Optimizing FSM `$fsm$\u_arbiter.owner$5697' from module `\spi_neuron_top'.
|
|
Removing unused input signal $auto$opt_reduce.cc:137:opt_pmux$5658.
|
|
Optimizing FSM `$fsm$\u_neuron_memory.u_mem.state$5693' from module `\spi_neuron_top'.
|
|
Optimizing FSM `$fsm$\u_layer_sequencer.state$5684' from module `\spi_neuron_top'.
|
|
Optimizing FSM `$fsm$\u_graph_engine.state$5669' from module `\spi_neuron_top'.
|
|
Removing unused input signal $flatten\u_graph_engine.$procmux$2917_CTRL.
|
|
Optimizing FSM `$fsm$\u_neuron_memory.state$5661' from module `\spi_neuron_top'.
|
|
|
|
17.13.4. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \spi_neuron_top..
|
|
Removed 153 unused cells and 153 unused wires.
|
|
<suppressed ~154 debug messages>
|
|
|
|
17.13.5. Executing FSM_OPT pass (simple optimizations of FSMs).
|
|
Optimizing FSM `$fsm$\u_memory_if.state$5725' from module `\spi_neuron_top'.
|
|
Removing unused output signal $flatten\u_memory_if.$0\state[1:0] [0].
|
|
Removing unused output signal $flatten\u_memory_if.$0\state[1:0] [1].
|
|
Optimizing FSM `$fsm$\u_psram_ctrl.state$5729' from module `\spi_neuron_top'.
|
|
Removing unused output signal $flatten\u_psram_ctrl.$0\state[2:0] [0].
|
|
Removing unused output signal $flatten\u_psram_ctrl.$0\state[2:0] [1].
|
|
Removing unused output signal $flatten\u_psram_ctrl.$0\state[2:0] [2].
|
|
Optimizing FSM `$fsm$\u_neuron_memory.state$5661' from module `\spi_neuron_top'.
|
|
Removing unused output signal $flatten\u_neuron_memory.$0\state[3:0] [0].
|
|
Removing unused output signal $flatten\u_neuron_memory.$0\state[3:0] [1].
|
|
Removing unused output signal $flatten\u_neuron_memory.$0\state[3:0] [2].
|
|
Removing unused output signal $flatten\u_neuron_memory.$0\state[3:0] [3].
|
|
Optimizing FSM `$fsm$\u_graph_engine.state$5669' from module `\spi_neuron_top'.
|
|
Removing unused output signal $flatten\u_graph_engine.$0\state[3:0] [0].
|
|
Removing unused output signal $flatten\u_graph_engine.$0\state[3:0] [1].
|
|
Removing unused output signal $flatten\u_graph_engine.$0\state[3:0] [2].
|
|
Removing unused output signal $flatten\u_graph_engine.$0\state[3:0] [3].
|
|
Optimizing FSM `$fsm$\u_layer_sequencer.state$5684' from module `\spi_neuron_top'.
|
|
Removing unused output signal $flatten\u_layer_sequencer.$0\state[3:0] [0].
|
|
Removing unused output signal $flatten\u_layer_sequencer.$0\state[3:0] [1].
|
|
Removing unused output signal $flatten\u_layer_sequencer.$0\state[3:0] [2].
|
|
Removing unused output signal $flatten\u_layer_sequencer.$0\state[3:0] [3].
|
|
Optimizing FSM `$fsm$\u_neuron_memory.u_mem.state$5693' from module `\spi_neuron_top'.
|
|
Removing unused output signal $flatten\u_neuron_memory.\u_mem.$0\state[1:0] [0].
|
|
Removing unused output signal $flatten\u_neuron_memory.\u_mem.$0\state[1:0] [1].
|
|
Optimizing FSM `$fsm$\u_arbiter.owner$5697' from module `\spi_neuron_top'.
|
|
Removing unused output signal $flatten\u_arbiter.$0\owner[1:0] [0].
|
|
Removing unused output signal $flatten\u_arbiter.$0\owner[1:0] [1].
|
|
Optimizing FSM `$fsm$\u_spi_engine.resp_len$5703' from module `\spi_neuron_top'.
|
|
Optimizing FSM `$fsm$\u_spi_engine.state$5705' from module `\spi_neuron_top'.
|
|
Removing unused output signal $flatten\u_spi_engine.$procmux$4121_CMP.
|
|
Removing unused output signal $flatten\u_spi_engine.$0\state[3:0] [0].
|
|
Removing unused output signal $flatten\u_spi_engine.$0\state[3:0] [1].
|
|
Removing unused output signal $flatten\u_spi_engine.$0\state[3:0] [2].
|
|
Removing unused output signal $flatten\u_spi_engine.$0\state[3:0] [3].
|
|
Optimizing FSM `$fsm$\u_int8_access.state$5721' from module `\spi_neuron_top'.
|
|
Removing unused output signal $flatten\u_int8_access.$0\state[1:0] [0].
|
|
Removing unused output signal $flatten\u_int8_access.$0\state[1:0] [1].
|
|
|
|
17.13.6. Executing FSM_RECODE pass (re-assigning FSM state encoding).
|
|
Recoding FSM `$fsm$\u_memory_if.state$5725' from module `\spi_neuron_top' using `auto' encoding:
|
|
mapping auto encoding to `one-hot` for this FSM.
|
|
00 -> -1
|
|
01 -> 1-
|
|
Recoding FSM `$fsm$\u_psram_ctrl.state$5729' from module `\spi_neuron_top' using `auto' encoding:
|
|
mapping auto encoding to `one-hot` for this FSM.
|
|
000 -> ----1
|
|
100 -> ---1-
|
|
010 -> --1--
|
|
001 -> -1---
|
|
011 -> 1----
|
|
Recoding FSM `$fsm$\u_neuron_memory.state$5661' from module `\spi_neuron_top' using `auto' encoding:
|
|
mapping auto encoding to `one-hot` for this FSM.
|
|
0000 -> -----1
|
|
0100 -> ----1-
|
|
0010 -> ---1--
|
|
0001 -> --1---
|
|
0101 -> -1----
|
|
0011 -> 1-----
|
|
Recoding FSM `$fsm$\u_graph_engine.state$5669' from module `\spi_neuron_top' using `auto' encoding:
|
|
mapping auto encoding to `one-hot` for this FSM.
|
|
0000 -> ------------1
|
|
1000 -> -----------1-
|
|
0100 -> ----------1--
|
|
1100 -> ---------1---
|
|
0010 -> --------1----
|
|
1010 -> -------1-----
|
|
0110 -> ------1------
|
|
0001 -> -----1-------
|
|
1001 -> ----1--------
|
|
0101 -> ---1---------
|
|
0011 -> --1----------
|
|
1011 -> -1-----------
|
|
0111 -> 1------------
|
|
Recoding FSM `$fsm$\u_layer_sequencer.state$5684' from module `\spi_neuron_top' using `auto' encoding:
|
|
mapping auto encoding to `one-hot` for this FSM.
|
|
0000 -> ------1
|
|
0100 -> -----1-
|
|
0010 -> ----1--
|
|
0110 -> ---1---
|
|
0001 -> --1----
|
|
0101 -> -1-----
|
|
0011 -> 1------
|
|
Recoding FSM `$fsm$\u_neuron_memory.u_mem.state$5693' from module `\spi_neuron_top' using `auto' encoding:
|
|
mapping auto encoding to `one-hot` for this FSM.
|
|
00 -> -1
|
|
01 -> 1-
|
|
Recoding FSM `$fsm$\u_arbiter.owner$5697' from module `\spi_neuron_top' using `auto' encoding:
|
|
mapping auto encoding to `one-hot` for this FSM.
|
|
00 -> ---1
|
|
10 -> --1-
|
|
01 -> -1--
|
|
11 -> 1---
|
|
Recoding FSM `$fsm$\u_spi_engine.resp_len$5703' from module `\spi_neuron_top' using `auto' encoding:
|
|
mapping auto encoding to `one-hot` for this FSM.
|
|
0000 -> --1
|
|
0001 -> -1-
|
|
1011 -> 1--
|
|
Recoding FSM `$fsm$\u_spi_engine.state$5705' from module `\spi_neuron_top' using `auto' encoding:
|
|
mapping auto encoding to `one-hot` for this FSM.
|
|
0000 -> -------------1
|
|
1000 -> ------------1-
|
|
0100 -> -----------1--
|
|
1100 -> ----------1---
|
|
0010 -> ---------1----
|
|
1010 -> --------1-----
|
|
0110 -> -------1------
|
|
0001 -> ------1-------
|
|
1001 -> -----1--------
|
|
0101 -> ----1---------
|
|
1101 -> ---1----------
|
|
0011 -> --1-----------
|
|
1011 -> -1------------
|
|
0111 -> 1-------------
|
|
Recoding FSM `$fsm$\u_int8_access.state$5721' from module `\spi_neuron_top' using `auto' encoding:
|
|
mapping auto encoding to `one-hot` for this FSM.
|
|
00 -> -1
|
|
01 -> 1-
|
|
|
|
17.13.7. Executing FSM_INFO pass (dumping all available information on FSM cells).
|
|
|
|
FSM `$fsm$\u_memory_if.state$5725' from module `spi_neuron_top':
|
|
-------------------------------------
|
|
|
|
Information on FSM $fsm$\u_memory_if.state$5725 (\u_memory_if.state):
|
|
|
|
Number of input signals: 3
|
|
Number of output signals: 2
|
|
Number of state bits: 2
|
|
|
|
Input signals:
|
|
0: \rst
|
|
1: \u_psram_ctrl.mem_ready
|
|
2: \u_int8_access.mem_req
|
|
|
|
Output signals:
|
|
0: $flatten\u_memory_if.$procmux$1591_CMP
|
|
1: $flatten\u_memory_if.$procmux$1583_CMP
|
|
|
|
State encoding:
|
|
0: 2'-1 <RESET STATE>
|
|
1: 2'1-
|
|
|
|
Transition Table (state_in, ctrl_in, state_out, ctrl_out):
|
|
0: 0 3'0-0 -> 0 2'10
|
|
1: 0 3'--1 -> 0 2'10
|
|
2: 0 3'1-0 -> 1 2'10
|
|
3: 1 3'-10 -> 0 2'01
|
|
4: 1 3'--1 -> 0 2'01
|
|
5: 1 3'-00 -> 1 2'01
|
|
|
|
-------------------------------------
|
|
|
|
FSM `$fsm$\u_psram_ctrl.state$5729' from module `spi_neuron_top':
|
|
-------------------------------------
|
|
|
|
Information on FSM $fsm$\u_psram_ctrl.state$5729 (\u_psram_ctrl.state):
|
|
|
|
Number of input signals: 5
|
|
Number of output signals: 5
|
|
Number of state bits: 5
|
|
|
|
Input signals:
|
|
0: \rst
|
|
1: $flatten\u_psram_ctrl.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/psram_controller.v:292$1245_Y
|
|
2: $flatten\u_psram_ctrl.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/psram_controller.v:179$1243_Y
|
|
3: \u_memory_if.mem_wr
|
|
4: \u_memory_if.mem_req
|
|
|
|
Output signals:
|
|
0: $flatten\u_psram_ctrl.$procmux$4837_CMP
|
|
1: $flatten\u_psram_ctrl.$procmux$4807_CMP
|
|
2: $flatten\u_psram_ctrl.$procmux$4737_CMP
|
|
3: $flatten\u_psram_ctrl.$procmux$4718_CMP
|
|
4: $flatten\u_psram_ctrl.$procmux$4712_CMP
|
|
|
|
State encoding:
|
|
0: 5'----1 <RESET STATE>
|
|
1: 5'---1-
|
|
2: 5'--1--
|
|
3: 5'-1---
|
|
4: 5'1----
|
|
|
|
Transition Table (state_in, ctrl_in, state_out, ctrl_out):
|
|
0: 0 5'--0-0 -> 0 5'00001
|
|
1: 0 5'----1 -> 0 5'00001
|
|
2: 0 5'--1-0 -> 3 5'00001
|
|
3: 1 5'----1 -> 0 5'00010
|
|
4: 1 5'----0 -> 3 5'00010
|
|
5: 2 5'----1 -> 0 5'00100
|
|
6: 2 5'---00 -> 2 5'00100
|
|
7: 2 5'---10 -> 3 5'00100
|
|
8: 3 5'----1 -> 0 5'01000
|
|
9: 3 5'10--0 -> 2 5'01000
|
|
10: 3 5'0---0 -> 3 5'01000
|
|
11: 3 5'11--0 -> 4 5'01000
|
|
12: 4 5'----1 -> 0 5'10000
|
|
13: 4 5'---10 -> 1 5'10000
|
|
14: 4 5'---00 -> 4 5'10000
|
|
|
|
-------------------------------------
|
|
|
|
FSM `$fsm$\u_neuron_memory.state$5661' from module `spi_neuron_top':
|
|
-------------------------------------
|
|
|
|
Information on FSM $fsm$\u_neuron_memory.state$5661 (\u_neuron_memory.state):
|
|
|
|
Number of input signals: 6
|
|
Number of output signals: 6
|
|
Number of state bits: 6
|
|
|
|
Input signals:
|
|
0: \graph_rst
|
|
1: \mux_nm_start
|
|
2: \u_neuron_memory.u_neuron.done
|
|
3: \u_neuron_memory.u_mem.ready
|
|
4: $flatten\u_neuron_memory.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:451$1168_Y
|
|
5: $flatten\u_neuron_memory.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:359$1152_Y
|
|
|
|
Output signals:
|
|
0: $flatten\u_neuron_memory.$procmux$2192_CMP
|
|
1: $flatten\u_neuron_memory.$procmux$2020_CMP
|
|
2: $flatten\u_neuron_memory.$procmux$1993_CMP
|
|
3: $flatten\u_neuron_memory.$procmux$1867_CMP
|
|
4: $flatten\u_neuron_memory.$procmux$1830_CMP
|
|
5: $flatten\u_neuron_memory.$procmux$1800_CMP
|
|
|
|
State encoding:
|
|
0: 6'-----1 <RESET STATE>
|
|
1: 6'----1-
|
|
2: 6'---1--
|
|
3: 6'--1---
|
|
4: 6'-1----
|
|
5: 6'1-----
|
|
|
|
Transition Table (state_in, ctrl_in, state_out, ctrl_out):
|
|
0: 0 6'----00 -> 0 6'000010
|
|
1: 0 6'-----1 -> 0 6'000010
|
|
2: 0 6'----10 -> 3 6'000010
|
|
3: 1 6'-----1 -> 0 6'000100
|
|
4: 1 6'-----0 -> 4 6'000100
|
|
5: 2 6'-----1 -> 0 6'010000
|
|
6: 2 6'--0--0 -> 2 6'010000
|
|
7: 2 6'0-1--0 -> 2 6'010000
|
|
8: 2 6'1-1--0 -> 5 6'010000
|
|
9: 3 6'-----1 -> 0 6'001000
|
|
10: 3 6'1-1--0 -> 2 6'001000
|
|
11: 3 6'--0--0 -> 3 6'001000
|
|
12: 3 6'0-1--0 -> 3 6'001000
|
|
13: 4 6'-1-1-0 -> 0 6'100000
|
|
14: 4 6'-----1 -> 0 6'100000
|
|
15: 4 6'-0-1-0 -> 2 6'100000
|
|
16: 4 6'---0-0 -> 4 6'100000
|
|
17: 5 6'-----1 -> 0 6'000001
|
|
18: 5 6'--1--0 -> 1 6'000001
|
|
19: 5 6'--0--0 -> 5 6'000001
|
|
|
|
-------------------------------------
|
|
|
|
FSM `$fsm$\u_graph_engine.state$5669' from module `spi_neuron_top':
|
|
-------------------------------------
|
|
|
|
Information on FSM $fsm$\u_graph_engine.state$5669 (\u_graph_engine.state):
|
|
|
|
Number of input signals: 12
|
|
Number of output signals: 13
|
|
Number of state bits: 13
|
|
|
|
Input signals:
|
|
0: \graph_run_start
|
|
1: \graph_rst
|
|
2: \u_arbiter.c_ready
|
|
3: \u_graph_engine.u_neuron.done
|
|
4: $flatten\u_graph_engine.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:527$1041_Y
|
|
5: $flatten\u_graph_engine.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:498$1038_Y
|
|
6: $flatten\u_graph_engine.$logic_or$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:456$1035_Y
|
|
7: $flatten\u_graph_engine.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:449$1030_Y
|
|
8: $flatten\u_graph_engine.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:420$1026_Y
|
|
9: $flatten\u_graph_engine.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:389$1021_Y
|
|
10: $flatten\u_graph_engine.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:346$1018_Y
|
|
11: \u_graph_engine.is_output_sink
|
|
|
|
Output signals:
|
|
0: $flatten\u_graph_engine.$procmux$2917_CMP [0]
|
|
1: $flatten\u_graph_engine.$procmux$2917_CMP [1]
|
|
2: $flatten\u_graph_engine.$procmux$2656_CMP
|
|
3: $flatten\u_graph_engine.$procmux$2645_CMP
|
|
4: $flatten\u_graph_engine.$procmux$2642_CMP
|
|
5: $flatten\u_graph_engine.$procmux$2632_CMP
|
|
6: $flatten\u_graph_engine.$procmux$2623_CMP
|
|
7: $flatten\u_graph_engine.$procmux$2622_CMP
|
|
8: $flatten\u_graph_engine.$procmux$2621_CMP
|
|
9: $flatten\u_graph_engine.$procmux$2617_CMP
|
|
10: $flatten\u_graph_engine.$procmux$2375_CMP
|
|
11: $flatten\u_graph_engine.$procmux$2296_CMP
|
|
12: $flatten\u_graph_engine.$procmux$2261_CMP
|
|
|
|
State encoding:
|
|
0: 13'------------1 <RESET STATE>
|
|
1: 13'-----------1-
|
|
2: 13'----------1--
|
|
3: 13'---------1---
|
|
4: 13'--------1----
|
|
5: 13'-------1-----
|
|
6: 13'------1------
|
|
7: 13'-----1-------
|
|
8: 13'----1--------
|
|
9: 13'---1---------
|
|
10: 13'--1----------
|
|
11: 13'-1-----------
|
|
12: 13'1------------
|
|
|
|
Transition Table (state_in, ctrl_in, state_out, ctrl_out):
|
|
0: 0 12'----------00 -> 0 13'0000000000001
|
|
1: 0 12'----------1- -> 0 13'0000000000001
|
|
2: 0 12'----------01 -> 7 13'0000000000001
|
|
3: 1 12'----------1- -> 0 13'0000000100000
|
|
4: 1 12'----------0- -> 8 13'0000000100000
|
|
5: 2 12'----------1- -> 0 13'0100000000000
|
|
6: 2 12'---------00- -> 2 13'0100000000000
|
|
7: 2 12'--1------10- -> 9 13'0100000000000
|
|
8: 2 12'--0------10- -> 10 13'0100000000000
|
|
9: 3 12'----------1- -> 0 13'0000000000010
|
|
10: 3 12'----------00 -> 3 13'0000000000010
|
|
11: 3 12'----------01 -> 7 13'0000000000010
|
|
12: 4 12'----------1- -> 0 13'0000000001000
|
|
13: 4 12'---------00- -> 4 13'0000000001000
|
|
14: 4 12'-0-------10- -> 7 13'0000000001000
|
|
15: 4 12'-1-------10- -> 10 13'0000000001000
|
|
16: 5 12'----------1- -> 0 13'0001000000000
|
|
17: 5 12'----------0- -> 11 13'0001000000000
|
|
18: 6 12'----------1- -> 0 13'1000000000000
|
|
19: 6 12'----11---10- -> 3 13'1000000000000
|
|
20: 6 12'---------00- -> 6 13'1000000000000
|
|
21: 6 12'----0----10- -> 9 13'1000000000000
|
|
22: 6 12'----10---10- -> 12 13'1000000000000
|
|
23: 7 12'----------1- -> 0 13'0000001000000
|
|
24: 7 12'----------0- -> 4 13'0000001000000
|
|
25: 8 12'0------11-0- -> 0 13'0000000010000
|
|
26: 8 12'----------1- -> 0 13'0000000010000
|
|
27: 8 12'1-------1-0- -> 5 13'0000000010000
|
|
28: 8 12'--------0-0- -> 8 13'0000000010000
|
|
29: 8 12'0------01-0- -> 10 13'0000000010000
|
|
30: 9 12'----------1- -> 0 13'0000100000000
|
|
31: 9 12'---1------0- -> 3 13'0000100000000
|
|
32: 9 12'---0------0- -> 6 13'0000100000000
|
|
33: 10 12'----------1- -> 0 13'0000010000000
|
|
34: 10 12'----------0- -> 2 13'0000010000000
|
|
35: 11 12'-------1-10- -> 0 13'0000000000100
|
|
36: 11 12'----------1- -> 0 13'0000000000100
|
|
37: 11 12'-------0-10- -> 10 13'0000000000100
|
|
38: 11 12'---------00- -> 11 13'0000000000100
|
|
39: 12 12'----------1- -> 0 13'0010000000000
|
|
40: 12 12'------1---0- -> 1 13'0010000000000
|
|
41: 12 12'------0---0- -> 9 13'0010000000000
|
|
|
|
-------------------------------------
|
|
|
|
FSM `$fsm$\u_layer_sequencer.state$5684' from module `spi_neuron_top':
|
|
-------------------------------------
|
|
|
|
Information on FSM $fsm$\u_layer_sequencer.state$5684 (\u_layer_sequencer.state):
|
|
|
|
Number of input signals: 7
|
|
Number of output signals: 7
|
|
Number of state bits: 7
|
|
|
|
Input signals:
|
|
0: \rst
|
|
1: \seq_run_start
|
|
2: \u_arbiter.c_ready
|
|
3: \u_neuron_memory.done
|
|
4: $flatten\u_layer_sequencer.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:303$795_Y
|
|
5: $flatten\u_layer_sequencer.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:301$793_Y
|
|
6: $flatten\u_layer_sequencer.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:235$782_Y
|
|
|
|
Output signals:
|
|
0: $flatten\u_layer_sequencer.$procmux$3325_CMP
|
|
1: $flatten\u_layer_sequencer.$procmux$3308_CMP
|
|
2: $flatten\u_layer_sequencer.$procmux$3305_CMP
|
|
3: $flatten\u_layer_sequencer.$procmux$3294_CMP
|
|
4: $flatten\u_layer_sequencer.$procmux$3285_CMP
|
|
5: $flatten\u_layer_sequencer.$procmux$3284_CMP
|
|
6: $flatten\u_layer_sequencer.$procmux$3161_CMP
|
|
|
|
State encoding:
|
|
0: 7'------1 <RESET STATE>
|
|
1: 7'-----1-
|
|
2: 7'----1--
|
|
3: 7'---1---
|
|
4: 7'--1----
|
|
5: 7'-1-----
|
|
6: 7'1------
|
|
|
|
Transition Table (state_in, ctrl_in, state_out, ctrl_out):
|
|
0: 0 7'-----00 -> 0 7'0000001
|
|
1: 0 7'------1 -> 0 7'0000001
|
|
2: 0 7'-----10 -> 4 7'0000001
|
|
3: 1 7'------1 -> 0 7'0000010
|
|
4: 1 7'---0--0 -> 1 7'0000010
|
|
5: 1 7'---1--0 -> 5 7'0000010
|
|
6: 2 7'------1 -> 0 7'1000000
|
|
7: 2 7'----0-0 -> 2 7'1000000
|
|
8: 2 7'0---1-0 -> 4 7'1000000
|
|
9: 2 7'1---1-0 -> 6 7'1000000
|
|
10: 3 7'-11-1-0 -> 0 7'0000100
|
|
11: 3 7'------1 -> 0 7'0000100
|
|
12: 3 7'----0-0 -> 3 7'0000100
|
|
13: 3 7'-10-1-0 -> 4 7'0000100
|
|
14: 3 7'-0--1-0 -> 5 7'0000100
|
|
15: 4 7'------1 -> 0 7'0010000
|
|
16: 4 7'------0 -> 2 7'0010000
|
|
17: 5 7'------1 -> 0 7'0100000
|
|
18: 5 7'------0 -> 3 7'0100000
|
|
19: 6 7'------1 -> 0 7'0001000
|
|
20: 6 7'------0 -> 1 7'0001000
|
|
|
|
-------------------------------------
|
|
|
|
FSM `$fsm$\u_neuron_memory.u_mem.state$5693' from module `spi_neuron_top':
|
|
-------------------------------------
|
|
|
|
Information on FSM $fsm$\u_neuron_memory.u_mem.state$5693 (\u_neuron_memory.u_mem.state):
|
|
|
|
Number of input signals: 3
|
|
Number of output signals: 2
|
|
Number of state bits: 2
|
|
|
|
Input signals:
|
|
0: \graph_rst
|
|
1: \u_arbiter.b_ready
|
|
2: \u_neuron_memory.access_req
|
|
|
|
Output signals:
|
|
0: $flatten\u_neuron_memory.\u_mem.$procmux$4958_CMP
|
|
1: $flatten\u_neuron_memory.\u_mem.$procmux$4966_CMP
|
|
|
|
State encoding:
|
|
0: 2'-1 <RESET STATE>
|
|
1: 2'1-
|
|
|
|
Transition Table (state_in, ctrl_in, state_out, ctrl_out):
|
|
0: 0 3'0-0 -> 0 2'01
|
|
1: 0 3'--1 -> 0 2'01
|
|
2: 0 3'1-0 -> 1 2'01
|
|
3: 1 3'-10 -> 0 2'10
|
|
4: 1 3'--1 -> 0 2'10
|
|
5: 1 3'-00 -> 1 2'10
|
|
|
|
-------------------------------------
|
|
|
|
FSM `$fsm$\u_arbiter.owner$5697' from module `spi_neuron_top':
|
|
-------------------------------------
|
|
|
|
Information on FSM $fsm$\u_arbiter.owner$5697 (\u_arbiter.owner):
|
|
|
|
Number of input signals: 5
|
|
Number of output signals: 4
|
|
Number of state bits: 4
|
|
|
|
Input signals:
|
|
0: \rst
|
|
1: \portc_req
|
|
2: \u_int8_access.ready
|
|
3: \u_neuron_memory.u_mem.mem_req
|
|
4: \u_spi_engine.ram_req
|
|
|
|
Output signals:
|
|
0: $flatten\u_arbiter.$procmux$1697_CMP
|
|
1: $flatten\u_arbiter.$procmux$1681_CMP
|
|
2: $flatten\u_arbiter.$procmux$1672_CMP
|
|
3: $flatten\u_arbiter.$procmux$1664_CMP
|
|
|
|
State encoding:
|
|
0: 4'---1 <RESET STATE>
|
|
1: 4'--1-
|
|
2: 4'-1--
|
|
3: 4'1---
|
|
|
|
Transition Table (state_in, ctrl_in, state_out, ctrl_out):
|
|
0: 0 5'00-00 -> 0 4'0001
|
|
1: 0 5'----1 -> 0 4'0001
|
|
2: 0 5'-1--0 -> 1 4'0001
|
|
3: 0 5'10-00 -> 2 4'0001
|
|
4: 0 5'-0-10 -> 3 4'0001
|
|
5: 1 5'--1-0 -> 0 4'0100
|
|
6: 1 5'----1 -> 0 4'0100
|
|
7: 1 5'--0-0 -> 1 4'0100
|
|
8: 2 5'--1-0 -> 0 4'0010
|
|
9: 2 5'----1 -> 0 4'0010
|
|
10: 2 5'--0-0 -> 2 4'0010
|
|
11: 3 5'--1-0 -> 0 4'1000
|
|
12: 3 5'----1 -> 0 4'1000
|
|
13: 3 5'--0-0 -> 3 4'1000
|
|
|
|
-------------------------------------
|
|
|
|
FSM `$fsm$\u_spi_engine.resp_len$5703' from module `spi_neuron_top':
|
|
-------------------------------------
|
|
|
|
Information on FSM $fsm$\u_spi_engine.resp_len$5703 (\u_spi_engine.resp_len):
|
|
|
|
Number of input signals: 6
|
|
Number of output signals: 4
|
|
Number of state bits: 3
|
|
|
|
Input signals:
|
|
0: $auto$opt_reduce.cc:137:opt_pmux$5632
|
|
1: \rst
|
|
2: $flatten\u_spi_engine.$procmux$3881_CMP
|
|
3: $flatten\u_spi_engine.$procmux$3716_CMP
|
|
4: \u_spi_slave.cs_end
|
|
5: \u_spi_slave.rx_valid
|
|
|
|
Output signals:
|
|
0: $flatten\u_spi_engine.$0\resp_len[3:0] [0]
|
|
1: $flatten\u_spi_engine.$0\resp_len[3:0] [1]
|
|
2: $flatten\u_spi_engine.$0\resp_len[3:0] [2]
|
|
3: $flatten\u_spi_engine.$0\resp_len[3:0] [3]
|
|
|
|
State encoding:
|
|
0: 3'--1 <RESET STATE>
|
|
1: 3'-1-
|
|
2: 3'1--
|
|
|
|
Transition Table (state_in, ctrl_in, state_out, ctrl_out):
|
|
0: 0 6'101000 -> 0 4'0000
|
|
1: 0 6'-00-0- -> 0 4'0000
|
|
2: 0 6'001-0- -> 0 4'0000
|
|
3: 0 6'-1--0- -> 0 4'0000
|
|
4: 0 6'----1- -> 0 4'0000
|
|
5: 0 6'101-01 -> 1 4'0001
|
|
6: 0 6'10110- -> 2 4'1011
|
|
7: 1 6'----1- -> 0 4'0000
|
|
8: 1 6'101000 -> 1 4'0001
|
|
9: 1 6'101-01 -> 1 4'0001
|
|
10: 1 6'-00-0- -> 1 4'0001
|
|
11: 1 6'001-0- -> 1 4'0001
|
|
12: 1 6'-1--0- -> 1 4'0001
|
|
13: 1 6'10110- -> 2 4'1011
|
|
14: 2 6'----1- -> 0 4'0000
|
|
15: 2 6'101-01 -> 1 4'0001
|
|
16: 2 6'101000 -> 2 4'1011
|
|
17: 2 6'10110- -> 2 4'1011
|
|
18: 2 6'-00-0- -> 2 4'1011
|
|
19: 2 6'001-0- -> 2 4'1011
|
|
20: 2 6'-1--0- -> 2 4'1011
|
|
|
|
-------------------------------------
|
|
|
|
FSM `$fsm$\u_spi_engine.state$5705' from module `spi_neuron_top':
|
|
-------------------------------------
|
|
|
|
Information on FSM $fsm$\u_spi_engine.state$5705 (\u_spi_engine.state):
|
|
|
|
Number of input signals: 16
|
|
Number of output signals: 13
|
|
Number of state bits: 14
|
|
|
|
Input signals:
|
|
0: $auto$opt_reduce.cc:137:opt_pmux$5634
|
|
1: \rst
|
|
2: \u_arbiter.a_ready
|
|
3: $flatten\u_spi_engine.$procmux$4185_CMP
|
|
4: $flatten\u_spi_engine.$procmux$4184_CMP
|
|
5: $flatten\u_spi_engine.$procmux$4183_CMP
|
|
6: $flatten\u_spi_engine.$procmux$4052_CTRL
|
|
7: $flatten\u_spi_engine.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:707$778_Y
|
|
8: $flatten\u_spi_engine.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:601$771_Y
|
|
9: $flatten\u_spi_engine.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:549$767_Y
|
|
10: $flatten\u_spi_engine.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:545$766_Y
|
|
11: $flatten\u_spi_engine.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:540$765_Y
|
|
12: $flatten\u_spi_engine.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:493$763_Y
|
|
13: $flatten\u_spi_engine.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:489$762_Y
|
|
14: \u_spi_slave.cs_end
|
|
15: \u_spi_slave.rx_valid
|
|
|
|
Output signals:
|
|
0: $flatten\u_spi_engine.$procmux$4130_CMP
|
|
1: $flatten\u_spi_engine.$procmux$3967_CMP
|
|
2: $flatten\u_spi_engine.$procmux$3964_CMP
|
|
3: $flatten\u_spi_engine.$procmux$3946_CMP
|
|
4: $flatten\u_spi_engine.$procmux$3926_CMP
|
|
5: $flatten\u_spi_engine.$procmux$3817_CMP
|
|
6: $flatten\u_spi_engine.$procmux$3767_CMP
|
|
7: $flatten\u_spi_engine.$procmux$3766_CMP
|
|
8: $flatten\u_spi_engine.$procmux$3716_CMP
|
|
9: $flatten\u_spi_engine.$procmux$3685_CMP
|
|
10: $flatten\u_spi_engine.$procmux$3652_CMP
|
|
11: $flatten\u_spi_engine.$procmux$3643_CMP
|
|
12: $flatten\u_spi_engine.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:218$749_Y
|
|
|
|
State encoding:
|
|
0: 14'-------------1 <RESET STATE>
|
|
1: 14'------------1-
|
|
2: 14'-----------1--
|
|
3: 14'----------1---
|
|
4: 14'---------1----
|
|
5: 14'--------1-----
|
|
6: 14'-------1------
|
|
7: 14'------1-------
|
|
8: 14'-----1--------
|
|
9: 14'----1---------
|
|
10: 14'---1----------
|
|
11: 14'--1-----------
|
|
12: 14'-1------------
|
|
13: 14'1-------------
|
|
|
|
Transition Table (state_in, ctrl_in, state_out, ctrl_out):
|
|
0: 0 16'00------------0- -> 0 13'0000100000000
|
|
1: 0 16'-1------------0- -> 0 13'0000100000000
|
|
2: 0 16'--------------1- -> 0 13'0000100000000
|
|
3: 0 16'10---------1--0- -> 3 13'0000100000000
|
|
4: 0 16'10-------1----0- -> 4 13'0000100000000
|
|
5: 0 16'10------------01 -> 5 13'0000100000000
|
|
6: 0 16'10----------1-0- -> 7 13'0000100000000
|
|
7: 0 16'10--------1---0- -> 10 13'0000100000000
|
|
8: 0 16'10-------0000-00 -> 12 13'0000100000000
|
|
9: 1 16'-1------------0- -> 0 13'0000000010000
|
|
10: 1 16'--------------1- -> 0 13'0000000010000
|
|
11: 1 16'-0-----------00- -> 1 13'0000000010000
|
|
12: 1 16'-0-----------10- -> 8 13'0000000010000
|
|
13: 2 16'-1------------0- -> 0 13'0000000001000
|
|
14: 2 16'--------------1- -> 0 13'0000000001000
|
|
15: 2 16'00------------0- -> 2 13'0000000001000
|
|
16: 2 16'10------------0- -> 9 13'0000000001000
|
|
17: 3 16'-1------------0- -> 0 13'0000000100000
|
|
18: 3 16'--------------1- -> 0 13'0000000100000
|
|
19: 3 16'00------------0- -> 3 13'0000000100000
|
|
20: 3 16'10------------0- -> 12 13'0000000100000
|
|
21: 4 16'-1------------0- -> 0 13'0010000000000
|
|
22: 4 16'--------------1- -> 0 13'0010000000000
|
|
23: 4 16'100-----------0- -> 4 13'0010000000000
|
|
24: 4 16'00------------0- -> 4 13'0010000000000
|
|
25: 4 16'1010----------0- -> 11 13'0010000000000
|
|
26: 4 16'1011----------0- -> 12 13'0010000000000
|
|
27: 5 16'-1------------0- -> 0 13'1000000000000
|
|
28: 5 16'--------------1- -> 0 13'1000000000000
|
|
29: 5 16'10------0-----0- -> 5 13'1000000000000
|
|
30: 5 16'00------------0- -> 5 13'1000000000000
|
|
31: 5 16'10------1-----0- -> 12 13'1000000000000
|
|
32: 6 16'-1------------0- -> 0 13'0000000000010
|
|
33: 6 16'--------------1- -> 0 13'0000000000010
|
|
34: 6 16'-0-----0-----10- -> 2 13'0000000000010
|
|
35: 6 16'-0-----------00- -> 6 13'0000000000010
|
|
36: 6 16'-0-----1-----10- -> 12 13'0000000000010
|
|
37: 7 16'-1------------0- -> 0 13'0001000000000
|
|
38: 7 16'--------------1- -> 0 13'0001000000000
|
|
39: 7 16'10------------0- -> 4 13'0001000000000
|
|
40: 7 16'00------------0- -> 7 13'0001000000000
|
|
41: 8 16'-1------------0- -> 0 13'0000000000100
|
|
42: 8 16'--------------1- -> 0 13'0000000000100
|
|
43: 8 16'00------------0- -> 8 13'0000000000100
|
|
44: 8 16'10-----1------0- -> 12 13'0000000000100
|
|
45: 8 16'10-----0------0- -> 13 13'0000000000100
|
|
46: 9 16'-1------------0- -> 0 13'0000001000000
|
|
47: 9 16'--------------1- -> 0 13'0000001000000
|
|
48: 9 16'-0------------0- -> 6 13'0000001000000
|
|
49: 10 16'-1------------0- -> 0 13'0000000000001
|
|
50: 10 16'--------------1- -> 0 13'0000000000001
|
|
51: 10 16'00------------0- -> 10 13'0000000000001
|
|
52: 10 16'10------------0- -> 12 13'0000000000001
|
|
53: 11 16'-1------------0- -> 0 13'0100000000000
|
|
54: 11 16'--------------1- -> 0 13'0100000000000
|
|
55: 11 16'10--101-------0- -> 2 13'0100000000000
|
|
56: 11 16'10--0---------0- -> 11 13'0100000000000
|
|
57: 11 16'00------------0- -> 11 13'0100000000000
|
|
58: 11 16'10--11--------0- -> 12 13'0100000000000
|
|
59: 11 16'10--100-------0- -> 13 13'0100000000000
|
|
60: 12 16'-1------------0- -> 0 13'0000000000000
|
|
61: 12 16'--------------1- -> 0 13'0000000000000
|
|
62: 12 16'-0------------0- -> 12 13'0000000000000
|
|
63: 13 16'-1------------0- -> 0 13'0000010000000
|
|
64: 13 16'--------------1- -> 0 13'0000010000000
|
|
65: 13 16'-0------------0- -> 1 13'0000010000000
|
|
|
|
-------------------------------------
|
|
|
|
FSM `$fsm$\u_int8_access.state$5721' from module `spi_neuron_top':
|
|
-------------------------------------
|
|
|
|
Information on FSM $fsm$\u_int8_access.state$5721 (\u_int8_access.state):
|
|
|
|
Number of input signals: 3
|
|
Number of output signals: 2
|
|
Number of state bits: 2
|
|
|
|
Input signals:
|
|
0: \rst
|
|
1: \u_memory_if.ready
|
|
2: \u_arbiter.m_req
|
|
|
|
Output signals:
|
|
0: $flatten\u_int8_access.$procmux$4966_CMP
|
|
1: $flatten\u_int8_access.$procmux$4958_CMP
|
|
|
|
State encoding:
|
|
0: 2'-1 <RESET STATE>
|
|
1: 2'1-
|
|
|
|
Transition Table (state_in, ctrl_in, state_out, ctrl_out):
|
|
0: 0 3'0-0 -> 0 2'10
|
|
1: 0 3'--1 -> 0 2'10
|
|
2: 0 3'1-0 -> 1 2'10
|
|
3: 1 3'-10 -> 0 2'01
|
|
4: 1 3'--1 -> 0 2'01
|
|
5: 1 3'-00 -> 1 2'01
|
|
|
|
-------------------------------------
|
|
|
|
17.13.8. Executing FSM_MAP pass (mapping FSMs to basic logic).
|
|
Mapping FSM `$fsm$\u_memory_if.state$5725' from module `\spi_neuron_top'.
|
|
Mapping FSM `$fsm$\u_psram_ctrl.state$5729' from module `\spi_neuron_top'.
|
|
Mapping FSM `$fsm$\u_neuron_memory.state$5661' from module `\spi_neuron_top'.
|
|
Mapping FSM `$fsm$\u_graph_engine.state$5669' from module `\spi_neuron_top'.
|
|
Mapping FSM `$fsm$\u_layer_sequencer.state$5684' from module `\spi_neuron_top'.
|
|
Mapping FSM `$fsm$\u_neuron_memory.u_mem.state$5693' from module `\spi_neuron_top'.
|
|
Mapping FSM `$fsm$\u_arbiter.owner$5697' from module `\spi_neuron_top'.
|
|
Mapping FSM `$fsm$\u_spi_engine.resp_len$5703' from module `\spi_neuron_top'.
|
|
Mapping FSM `$fsm$\u_spi_engine.state$5705' from module `\spi_neuron_top'.
|
|
Mapping FSM `$fsm$\u_int8_access.state$5721' from module `\spi_neuron_top'.
|
|
|
|
17.14. Executing OPT pass (performing simple optimizations).
|
|
|
|
17.14.1. Executing OPT_EXPR pass (perform const folding).
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Optimizing module spi_neuron_top.
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<suppressed ~71 debug messages>
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17.14.2. Executing OPT_MERGE pass (detect identical cells).
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Finding identical cells in module `\spi_neuron_top'.
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Computing hashes of 1768 cells of `\spi_neuron_top'.
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Finding duplicate cells in `\spi_neuron_top'.
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Computing hashes of 1706 cells of `\spi_neuron_top'.
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|
Finding duplicate cells in `\spi_neuron_top'.
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|
Computing hashes of 1698 cells of `\spi_neuron_top'.
|
|
Finding duplicate cells in `\spi_neuron_top'.
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|
Computing hashes of 1696 cells of `\spi_neuron_top'.
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Finding duplicate cells in `\spi_neuron_top'.
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<suppressed ~216 debug messages>
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Removed a total of 72 cells.
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17.14.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
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|
Running muxtree optimizer on module \spi_neuron_top..
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Creating internal representation of mux trees.
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|
Evaluating internal representation of mux trees.
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|
Analyzing evaluation results.
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Removed 0 multiplexer ports.
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<suppressed ~1104 debug messages>
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17.14.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
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|
Optimizing cells in module \spi_neuron_top.
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|
Performed a total of 0 changes.
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|
|
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17.14.5. Executing OPT_MERGE pass (detect identical cells).
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|
Finding identical cells in module `\spi_neuron_top'.
|
|
Computing hashes of 1696 cells of `\spi_neuron_top'.
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Finding duplicate cells in `\spi_neuron_top'.
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|
Removed a total of 0 cells.
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|
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17.14.6. Executing OPT_DFF pass (perform DFF optimizations).
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Adding SRST signal on $flatten\u_int8_access.$procdff$5516 ($dff) from module spi_neuron_top (D = $flatten\u_int8_access.$procmux$4974_Y, Q = \u_int8_access.addr_reg, rval = 23'00000000000000000000000).
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Adding EN signal on $auto$ff.cc:337:slice$6466 ($sdff) from module spi_neuron_top (D = \u_arbiter.m_addr, Q = \u_int8_access.addr_reg).
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Adding SRST signal on $flatten\u_spi_engine.$procdff$5479 ($dff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$3978_Y, Q = \u_spi_engine.cur_addr, rval = 23'00000000000000000000000).
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Adding EN signal on $auto$ff.cc:337:slice$6470 ($sdff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$3963_Y, Q = \u_spi_engine.cur_addr).
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Adding SRST signal on $flatten\u_spi_engine.$procdff$5478 ($dff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$4002_Y, Q = \u_spi_engine.len_remaining, rval = 16'0000000000000000).
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Adding EN signal on $auto$ff.cc:337:slice$6488 ($sdff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$3990_Y, Q = \u_spi_engine.len_remaining).
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Adding SRST signal on $flatten\u_spi_engine.$procdff$5477 ($dff) from module spi_neuron_top (D = { $flatten\u_spi_engine.$procmux$3654_Y $flatten\u_spi_engine.$procmux$3687_Y }, Q = \u_spi_engine.len_acc, rval = 16'0000000000000000).
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Adding EN signal on $auto$ff.cc:337:slice$6504 ($sdff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$3672_Y, Q = \u_spi_engine.len_acc [7:0]).
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Adding EN signal on $auto$ff.cc:337:slice$6504 ($sdff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$3642_Y, Q = \u_spi_engine.len_acc [15:8]).
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Adding SRST signal on $flatten\u_spi_engine.$procdff$5476 ($dff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$4057_Y, Q = \u_spi_engine.addr_acc, rval = 24'000000000000000000000000).
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Adding EN signal on $auto$ff.cc:337:slice$6535 ($sdff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$4037_Y, Q = \u_spi_engine.addr_acc).
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Adding SRST signal on $flatten\u_spi_engine.$procdff$5475 ($dff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$4090_Y, Q = \u_spi_engine.byte_pos, rval = 2'00).
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Adding EN signal on $auto$ff.cc:337:slice$6551 ($sdff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$4078_Y, Q = \u_spi_engine.byte_pos).
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Adding SRST signal on $flatten\u_spi_engine.$procdff$5474 ($dff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$4114_Y, Q = \u_spi_engine.opcode, rval = 8'00000000).
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Adding EN signal on $auto$ff.cc:337:slice$6565 ($sdff) from module spi_neuron_top (D = \u_spi_slave.rx_byte, Q = \u_spi_engine.opcode).
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Adding SRST signal on $flatten\u_layer_sequencer.$procdff$5444 ($dff) from module spi_neuron_top (D = $flatten\u_layer_sequencer.$procmux$3444_Y, Q = \u_layer_sequencer.desc_byte_idx, rval = 4'0000).
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Adding EN signal on $auto$ff.cc:337:slice$6571 ($sdff) from module spi_neuron_top (D = $flatten\u_layer_sequencer.$procmux$3444_Y, Q = \u_layer_sequencer.desc_byte_idx).
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Adding SRST signal on $flatten\u_psram_ctrl.$procdff$5506 ($dff) from module spi_neuron_top (D = $flatten\u_psram_ctrl.$procmux$4711_Y, Q = \u_psram_ctrl.dq_oe, rval = 1'0).
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Adding SRST signal on $flatten\u_psram_ctrl.$procdff$5505 ($dff) from module spi_neuron_top (D = $flatten\u_psram_ctrl.$procmux$4824_Y, Q = \u_psram_ctrl.dq_out, rval = 16'0000000000000000).
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Adding EN signal on $auto$ff.cc:337:slice$6588 ($sdff) from module spi_neuron_top (D = \u_memory_if.mem_wdata, Q = \u_psram_ctrl.dq_out).
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Adding SRST signal on $flatten\u_psram_ctrl.$procdff$5504 ($dff) from module spi_neuron_top (D = $flatten\u_psram_ctrl.$procmux$4830_Y, Q = \u_psram_ctrl.ub_reg, rval = 1'1).
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Adding EN signal on $auto$ff.cc:337:slice$6592 ($sdff) from module spi_neuron_top (D = $flatten\u_psram_ctrl.$procmux$4830_Y, Q = \u_psram_ctrl.ub_reg).
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|
Adding SRST signal on $flatten\u_psram_ctrl.$procdff$5503 ($dff) from module spi_neuron_top (D = $flatten\u_psram_ctrl.$procmux$4842_Y, Q = \u_psram_ctrl.lb_reg, rval = 1'1).
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Adding EN signal on $auto$ff.cc:337:slice$6600 ($sdff) from module spi_neuron_top (D = $flatten\u_psram_ctrl.$procmux$4842_Y, Q = \u_psram_ctrl.lb_reg).
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|
Adding SRST signal on $flatten\u_psram_ctrl.$procdff$5499 ($dff) from module spi_neuron_top (D = $flatten\u_psram_ctrl.$procmux$4887_Y, Q = \u_psram_ctrl.counter, rval = 14'00000000000000).
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Adding EN signal on $auto$ff.cc:337:slice$6608 ($sdff) from module spi_neuron_top (D = $flatten\u_psram_ctrl.$procmux$4887_Y, Q = \u_psram_ctrl.counter).
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Adding SRST signal on $flatten\u_psram_ctrl.$procdff$5497 ($dff) from module spi_neuron_top (D = $flatten\u_psram_ctrl.$procmux$4732_Y, Q = \u_psram_ctrl.psram_ub_n, rval = 1'1).
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|
Adding SRST signal on $flatten\u_psram_ctrl.$procdff$5496 ($dff) from module spi_neuron_top (D = $flatten\u_psram_ctrl.$procmux$4746_Y, Q = \u_psram_ctrl.psram_lb_n, rval = 1'1).
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|
Adding SRST signal on $flatten\u_psram_ctrl.$procdff$5495 ($dff) from module spi_neuron_top (D = $flatten\u_psram_ctrl.$procmux$4763_Y, Q = \u_psram_ctrl.psram_we_n, rval = 1'1).
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Adding SRST signal on $flatten\u_psram_ctrl.$procdff$5494 ($dff) from module spi_neuron_top (D = $flatten\u_psram_ctrl.$procmux$4780_Y, Q = \u_psram_ctrl.psram_oe_n, rval = 1'1).
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Adding SRST signal on $flatten\u_psram_ctrl.$procdff$5493 ($dff) from module spi_neuron_top (D = $flatten\u_psram_ctrl.$procmux$4793_Y, Q = \u_psram_ctrl.psram_ce_n, rval = 1'1).
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Adding SRST signal on $flatten\u_psram_ctrl.$procdff$5492 ($dff) from module spi_neuron_top (D = $flatten\u_psram_ctrl.$procmux$4913_Y, Q = \u_psram_ctrl.psram_a, rval = 23'00000000000000000000000).
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Adding EN signal on $auto$ff.cc:337:slice$6621 ($sdff) from module spi_neuron_top (D = \u_memory_if.mem_addr, Q = \u_psram_ctrl.psram_a).
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Adding SRST signal on $flatten\u_psram_ctrl.$procdff$5491 ($dff) from module spi_neuron_top (D = $flatten\u_psram_ctrl.$procmux$4806_Y, Q = \u_psram_ctrl.mem_ready, rval = 1'0).
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Adding SRST signal on $flatten\u_psram_ctrl.$procdff$5490 ($dff) from module spi_neuron_top (D = $flatten\u_psram_ctrl.$procmux$4924_Y, Q = \u_psram_ctrl.mem_rdata, rval = 16'0000000000000000).
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Adding EN signal on $auto$ff.cc:337:slice$6626 ($sdff) from module spi_neuron_top (D = \psram_dq, Q = \u_psram_ctrl.mem_rdata).
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Adding SRST signal on $flatten\u_spi_engine.$procdff$5472 ($dff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$4221_Y, Q = \u_spi_engine.n_out, rval = 16'0000000000000000).
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Adding EN signal on $auto$ff.cc:337:slice$6630 ($sdff) from module spi_neuron_top (D = { \u_spi_engine.addr_acc [7:0] \u_spi_slave.rx_byte }, Q = \u_spi_engine.n_out).
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Adding SRST signal on $flatten\u_spi_engine.$procdff$5471 ($dff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$4252_Y, Q = \u_spi_engine.num_neurons_graph, rval = 16'0000000000000000).
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Adding EN signal on $auto$ff.cc:337:slice$6636 ($sdff) from module spi_neuron_top (D = { \u_spi_engine.addr_acc [7:0] \u_spi_slave.rx_byte }, Q = \u_spi_engine.num_neurons_graph).
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Adding SRST signal on $flatten\u_spi_engine.$procdff$5470 ($dff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$4275_Y, Q = \u_spi_engine.net_type, rval = 8'00000001).
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Adding EN signal on $auto$ff.cc:337:slice$6642 ($sdff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$4262_Y, Q = \u_spi_engine.net_type).
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Adding SRST signal on $flatten\u_spi_engine.$procdff$5469 ($dff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$4291_Y, Q = \u_spi_engine.run_num_layers, rval = 8'00000000).
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Adding EN signal on $auto$ff.cc:337:slice$6656 ($sdff) from module spi_neuron_top (D = \u_spi_slave.rx_byte, Q = \u_spi_engine.run_num_layers).
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Adding SRST signal on $flatten\u_spi_engine.$procdff$5468 ($dff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$3744_Y, Q = \u_spi_engine.run_start, rval = 1'0).
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Adding SRST signal on $flatten\u_spi_engine.$procdff$5467 ($dff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$4326_Y, Q = \u_spi_engine.buf_b_base, rval = 23'00000000000000000000000).
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Adding EN signal on $auto$ff.cc:337:slice$6671 ($sdff) from module spi_neuron_top (D = { \u_spi_engine.addr_acc [14:0] \u_spi_slave.rx_byte }, Q = \u_spi_engine.buf_b_base).
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Adding SRST signal on $flatten\u_spi_engine.$procdff$5466 ($dff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$4362_Y, Q = \u_spi_engine.buf_a_base, rval = 23'00000000000000000000000).
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Adding EN signal on $auto$ff.cc:337:slice$6677 ($sdff) from module spi_neuron_top (D = { \u_spi_engine.addr_acc [14:0] \u_spi_slave.rx_byte }, Q = \u_spi_engine.buf_a_base).
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Adding SRST signal on $flatten\u_spi_engine.$procdff$5465 ($dff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$4399_Y, Q = \u_spi_engine.table_base, rval = 23'00000000000000000000000).
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Adding EN signal on $auto$ff.cc:337:slice$6683 ($sdff) from module spi_neuron_top (D = { \u_spi_engine.addr_acc [14:0] \u_spi_slave.rx_byte }, Q = \u_spi_engine.table_base).
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Adding SRST signal on $flatten\u_spi_engine.$procdff$5464 ($dff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$3711_Y, Q = \u_spi_engine.nm_soft_rst, rval = 1'0).
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Adding SRST signal on $flatten\u_spi_engine.$procdff$5463 ($dff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$3744_Y, Q = \u_spi_engine.nm_start, rval = 1'0).
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Adding SRST signal on $flatten\u_spi_engine.$procdff$5462 ($dff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$4431_Y, Q = \u_spi_engine.n_neurons_real, rval = 16'0000000000000001).
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Adding EN signal on $auto$ff.cc:337:slice$6705 ($sdff) from module spi_neuron_top (D = { \u_spi_engine.addr_acc [7:0] \u_spi_slave.rx_byte }, Q = \u_spi_engine.n_neurons_real).
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Adding SRST signal on $flatten\u_spi_engine.$procdff$5461 ($dff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$4464_Y, Q = \u_spi_engine.n_inputs_real, rval = 16'0000000000100000).
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Adding EN signal on $auto$ff.cc:337:slice$6711 ($sdff) from module spi_neuron_top (D = { \u_spi_engine.addr_acc [7:0] \u_spi_slave.rx_byte }, Q = \u_spi_engine.n_inputs_real).
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Adding SRST signal on $flatten\u_spi_engine.$procdff$5460 ($dff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$4498_Y, Q = \u_spi_engine.activation, rval = 2'01).
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Adding EN signal on $auto$ff.cc:337:slice$6717 ($sdff) from module spi_neuron_top (D = \u_spi_slave.rx_byte [1:0], Q = \u_spi_engine.activation).
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Adding SRST signal on $flatten\u_spi_engine.$procdff$5459 ($dff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$4536_Y, Q = \u_spi_engine.bias_addr, rval = 23'00000000000000000000000).
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Adding EN signal on $auto$ff.cc:337:slice$6723 ($sdff) from module spi_neuron_top (D = { \u_spi_engine.addr_acc [14:0] \u_spi_slave.rx_byte }, Q = \u_spi_engine.bias_addr).
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Adding SRST signal on $flatten\u_spi_engine.$procdff$5458 ($dff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$4575_Y, Q = \u_spi_engine.w_base, rval = 23'00000000000000000000000).
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Adding EN signal on $auto$ff.cc:337:slice$6729 ($sdff) from module spi_neuron_top (D = { \u_spi_engine.addr_acc [14:0] \u_spi_slave.rx_byte }, Q = \u_spi_engine.w_base).
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Adding SRST signal on $flatten\u_spi_engine.$procdff$5457 ($dff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$4615_Y, Q = \u_spi_engine.x_base, rval = 23'00000000000000000000000).
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Adding EN signal on $auto$ff.cc:337:slice$6735 ($sdff) from module spi_neuron_top (D = { \u_spi_engine.addr_acc [14:0] \u_spi_slave.rx_byte }, Q = \u_spi_engine.x_base).
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Adding SRST signal on $flatten\u_spi_engine.$procdff$5456 ($dff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$4632_Y, Q = \u_spi_engine.ram_wdata, rval = 8'00000000).
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Adding EN signal on $auto$ff.cc:337:slice$6741 ($sdff) from module spi_neuron_top (D = \u_spi_engine.pending_wdata, Q = \u_spi_engine.ram_wdata).
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Adding SRST signal on $flatten\u_spi_engine.$procdff$5455 ($dff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$4648_Y, Q = \u_spi_engine.ram_addr, rval = 23'00000000000000000000000).
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Adding EN signal on $auto$ff.cc:337:slice$6747 ($sdff) from module spi_neuron_top (D = \u_spi_engine.cur_addr, Q = \u_spi_engine.ram_addr).
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Adding SRST signal on $flatten\u_spi_engine.$procdff$5454 ($dff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$4664_Y, Q = \u_spi_engine.ram_wr, rval = 1'0).
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Adding EN signal on $auto$ff.cc:337:slice$6753 ($sdff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$4660_Y, Q = \u_spi_engine.ram_wr).
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Adding SRST signal on $flatten\u_spi_engine.$procdff$5453 ($dff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$3765_Y, Q = \u_spi_engine.ram_req, rval = 1'0).
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Adding SRST signal on $flatten\u_memory_if.$procdff$5294 ($dff) from module spi_neuron_top (D = $flatten\u_memory_if.$procmux$1599_Y, Q = \u_memory_if.mem_ub_n, rval = 1'1).
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Adding EN signal on $auto$ff.cc:337:slice$6764 ($sdff) from module spi_neuron_top (D = \u_int8_access.mem_ub_n, Q = \u_memory_if.mem_ub_n).
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Adding SRST signal on $flatten\u_memory_if.$procdff$5293 ($dff) from module spi_neuron_top (D = $flatten\u_memory_if.$procmux$1608_Y, Q = \u_memory_if.mem_lb_n, rval = 1'1).
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Adding EN signal on $auto$ff.cc:337:slice$6768 ($sdff) from module spi_neuron_top (D = \u_int8_access.mem_lb_n, Q = \u_memory_if.mem_lb_n).
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Adding SRST signal on $flatten\u_memory_if.$procdff$5292 ($dff) from module spi_neuron_top (D = $flatten\u_memory_if.$procmux$1588_Y, Q = \u_memory_if.ready, rval = 1'0).
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Adding SRST signal on $flatten\u_memory_if.$procdff$5291 ($dff) from module spi_neuron_top (D = $flatten\u_memory_if.$procmux$1618_Y, Q = \u_memory_if.rdata, rval = 16'0000000000000000).
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Adding EN signal on $auto$ff.cc:337:slice$6777 ($sdff) from module spi_neuron_top (D = \u_psram_ctrl.mem_rdata, Q = \u_memory_if.rdata).
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Adding SRST signal on $flatten\u_memory_if.$procdff$5290 ($dff) from module spi_neuron_top (D = $flatten\u_memory_if.$procmux$1627_Y, Q = \u_memory_if.mem_wdata, rval = 16'0000000000000000).
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Adding EN signal on $auto$ff.cc:337:slice$6783 ($sdff) from module spi_neuron_top (D = \u_int8_access.mem_wdata, Q = \u_memory_if.mem_wdata).
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Adding SRST signal on $flatten\u_memory_if.$procdff$5289 ($dff) from module spi_neuron_top (D = $flatten\u_memory_if.$procmux$1636_Y, Q = \u_memory_if.mem_addr, rval = 23'00000000000000000000000).
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Adding EN signal on $auto$ff.cc:337:slice$6787 ($sdff) from module spi_neuron_top (D = \u_int8_access.mem_addr, Q = \u_memory_if.mem_addr).
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Adding SRST signal on $flatten\u_memory_if.$procdff$5288 ($dff) from module spi_neuron_top (D = $flatten\u_memory_if.$procmux$1645_Y, Q = \u_memory_if.mem_wr, rval = 1'0).
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Adding EN signal on $auto$ff.cc:337:slice$6791 ($sdff) from module spi_neuron_top (D = \u_int8_access.mem_wr, Q = \u_memory_if.mem_wr).
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Adding SRST signal on $flatten\u_memory_if.$procdff$5287 ($dff) from module spi_neuron_top (D = $flatten\u_memory_if.$procmux$1580_Y, Q = \u_memory_if.mem_req, rval = 1'0).
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Adding SRST signal on $flatten\u_int8_access.$procdff$5515 ($dff) from module spi_neuron_top (D = $flatten\u_int8_access.$procmux$4980_Y, Q = \u_int8_access.mem_ub_n, rval = 1'1).
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Adding EN signal on $auto$ff.cc:337:slice$6800 ($sdff) from module spi_neuron_top (D = $flatten\u_int8_access.$procmux$4980_Y, Q = \u_int8_access.mem_ub_n).
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Adding SRST signal on $flatten\u_int8_access.$procdff$5514 ($dff) from module spi_neuron_top (D = $flatten\u_int8_access.$procmux$4992_Y, Q = \u_int8_access.mem_lb_n, rval = 1'1).
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Adding EN signal on $auto$ff.cc:337:slice$6808 ($sdff) from module spi_neuron_top (D = $flatten\u_int8_access.$procmux$4992_Y, Q = \u_int8_access.mem_lb_n).
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Adding SRST signal on $flatten\u_int8_access.$procdff$5513 ($dff) from module spi_neuron_top (D = $flatten\u_int8_access.$procmux$4963_Y, Q = \u_int8_access.ready, rval = 1'0).
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Adding SRST signal on $flatten\u_int8_access.$procdff$5512 ($dff) from module spi_neuron_top (D = $flatten\u_int8_access.$procmux$5009_Y, Q = \u_int8_access.rdata, rval = 8'00000000).
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Adding EN signal on $auto$ff.cc:337:slice$6821 ($sdff) from module spi_neuron_top (D = $flatten\u_int8_access.$procmux$5005_Y, Q = \u_int8_access.rdata).
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Adding SRST signal on $flatten\u_int8_access.$procdff$5511 ($dff) from module spi_neuron_top (D = $flatten\u_int8_access.$procmux$5021_Y, Q = \u_int8_access.mem_wdata, rval = 16'0000000000000000).
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Adding EN signal on $auto$ff.cc:337:slice$6825 ($sdff) from module spi_neuron_top (D = $flatten\u_int8_access.$procmux$5017_Y, Q = \u_int8_access.mem_wdata).
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Adding SRST signal on $flatten\u_int8_access.$procdff$5510 ($dff) from module spi_neuron_top (D = $flatten\u_int8_access.$procmux$5030_Y, Q = \u_int8_access.mem_addr, rval = 23'00000000000000000000000).
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Adding EN signal on $auto$ff.cc:337:slice$6829 ($sdff) from module spi_neuron_top (D = { 1'0 \u_arbiter.m_addr [22:1] }, Q = \u_int8_access.mem_addr).
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Adding SRST signal on $flatten\u_int8_access.$procdff$5509 ($dff) from module spi_neuron_top (D = $flatten\u_int8_access.$procmux$5039_Y, Q = \u_int8_access.mem_wr, rval = 1'0).
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Adding EN signal on $auto$ff.cc:337:slice$6833 ($sdff) from module spi_neuron_top (D = \u_arbiter.m_wr, Q = \u_int8_access.mem_wr).
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|
Adding SRST signal on $flatten\u_int8_access.$procdff$5508 ($dff) from module spi_neuron_top (D = $flatten\u_int8_access.$procmux$4955_Y, Q = \u_int8_access.mem_req, rval = 1'0).
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|
Adding SRST signal on $flatten\u_arbiter.$procdff$5304 ($dff) from module spi_neuron_top (D = $flatten\u_arbiter.$procmux$1734_Y, Q = \u_arbiter.m_wdata, rval = 8'00000000).
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|
Adding EN signal on $auto$ff.cc:337:slice$6842 ($sdff) from module spi_neuron_top (D = $flatten\u_arbiter.$procmux$1732_Y, Q = \u_arbiter.m_wdata).
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Adding SRST signal on $flatten\u_arbiter.$procdff$5303 ($dff) from module spi_neuron_top (D = $flatten\u_arbiter.$procmux$1750_Y, Q = \u_arbiter.m_addr, rval = 23'00000000000000000000000).
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Adding EN signal on $auto$ff.cc:337:slice$6848 ($sdff) from module spi_neuron_top (D = $flatten\u_arbiter.$procmux$1748_Y, Q = \u_arbiter.m_addr).
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Adding SRST signal on $flatten\u_arbiter.$procdff$5302 ($dff) from module spi_neuron_top (D = $flatten\u_arbiter.$procmux$1766_Y, Q = \u_arbiter.m_wr, rval = 1'0).
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Adding EN signal on $auto$ff.cc:337:slice$6854 ($sdff) from module spi_neuron_top (D = $flatten\u_arbiter.$procmux$1764_Y, Q = \u_arbiter.m_wr).
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Adding SRST signal on $flatten\u_arbiter.$procdff$5301 ($dff) from module spi_neuron_top (D = $flatten\u_arbiter.$procmux$1694_Y, Q = \u_arbiter.m_req, rval = 1'0).
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Adding SRST signal on $flatten\u_arbiter.$procdff$5300 ($dff) from module spi_neuron_top (D = $flatten\u_arbiter.$procmux$1661_Y, Q = \u_arbiter.c_ready, rval = 1'0).
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Adding SRST signal on $flatten\u_arbiter.$procdff$5299 ($dff) from module spi_neuron_top (D = $flatten\u_arbiter.$procmux$1773_Y, Q = \u_arbiter.c_rdata, rval = 8'00000000).
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Adding EN signal on $auto$ff.cc:337:slice$6870 ($sdff) from module spi_neuron_top (D = \u_int8_access.rdata, Q = \u_arbiter.c_rdata).
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Adding SRST signal on $flatten\u_arbiter.$procdff$5298 ($dff) from module spi_neuron_top (D = $flatten\u_arbiter.$procmux$1661_Y, Q = \u_arbiter.b_ready, rval = 1'0).
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Adding SRST signal on $flatten\u_arbiter.$procdff$5297 ($dff) from module spi_neuron_top (D = $flatten\u_arbiter.$procmux$1781_Y, Q = \u_arbiter.b_rdata, rval = 8'00000000).
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Adding EN signal on $auto$ff.cc:337:slice$6879 ($sdff) from module spi_neuron_top (D = \u_int8_access.rdata, Q = \u_arbiter.b_rdata).
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Adding SRST signal on $flatten\u_arbiter.$procdff$5296 ($dff) from module spi_neuron_top (D = $flatten\u_arbiter.$procmux$1661_Y, Q = \u_arbiter.a_ready, rval = 1'0).
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Adding SRST signal on $flatten\u_arbiter.$procdff$5295 ($dff) from module spi_neuron_top (D = $flatten\u_arbiter.$procmux$1790_Y, Q = \u_arbiter.a_rdata, rval = 8'00000000).
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Adding EN signal on $auto$ff.cc:337:slice$6888 ($sdff) from module spi_neuron_top (D = \u_int8_access.rdata, Q = \u_arbiter.a_rdata).
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Adding SRST signal on $flatten\u_neuron_memory.\u_neuron.$procdff$5521 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.\u_neuron.$procmux$5129_Y, Q = \u_neuron_memory.u_neuron.y, rval = 8'00000000).
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Adding EN signal on $auto$ff.cc:337:slice$6892 ($sdff) from module spi_neuron_top (D = $flatten\u_neuron_memory.\u_neuron.$procmux$5122_Y, Q = \u_neuron_memory.u_neuron.y).
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Adding SRST signal on $flatten\u_neuron_memory.\u_neuron.$procdff$5522 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.\u_neuron.$procmux$5103_Y, Q = \u_neuron_memory.u_neuron.busy, rval = 1'0).
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Adding SRST signal on $flatten\u_neuron_memory.\u_neuron.$procdff$5523 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.\u_neuron.$procmux$5065_Y, Q = \u_neuron_memory.u_neuron.done, rval = 1'0).
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Adding SRST signal on $flatten\u_neuron_memory.\u_neuron.$procdff$5524 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.\u_neuron.$procmux$5089_Y, Q = \u_neuron_memory.u_neuron.group_index, rval = 4'0000).
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|
Adding EN signal on $auto$ff.cc:337:slice$6904 ($sdff) from module spi_neuron_top (D = $flatten\u_neuron_memory.\u_neuron.$add$/tmp/before_rewrite/neuron_parallel.v:194$1333_Y, Q = \u_neuron_memory.u_neuron.group_index).
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Adding SRST signal on $flatten\u_neuron_memory.\u_neuron.$procdff$5525 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.\u_neuron.$procmux$5078_Y, Q = \u_neuron_memory.u_neuron.acc, rval = 0).
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Adding EN signal on $auto$ff.cc:337:slice$6912 ($sdff) from module spi_neuron_top (D = $flatten\u_neuron_memory.\u_neuron.$procmux$5076_Y, Q = \u_neuron_memory.u_neuron.acc).
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Adding SRST signal on $flatten\u_neuron_memory.\u_mem.$procdff$5508 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.\u_mem.$procmux$4955_Y, Q = \u_neuron_memory.u_mem.mem_req, rval = 1'0).
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Adding SRST signal on $flatten\u_neuron_memory.\u_mem.$procdff$5509 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.\u_mem.$procmux$5039_Y, Q = \u_neuron_memory.u_mem.mem_wr, rval = 1'0).
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Adding EN signal on $auto$ff.cc:337:slice$6921 ($sdff) from module spi_neuron_top (D = \u_neuron_memory.access_wr, Q = \u_neuron_memory.u_mem.mem_wr).
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Adding SRST signal on $flatten\u_neuron_memory.\u_mem.$procdff$5512 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.\u_mem.$procmux$5009_Y, Q = \u_neuron_memory.u_mem.rdata, rval = 8'00000000).
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Adding EN signal on $auto$ff.cc:337:slice$6925 ($sdff) from module spi_neuron_top (D = $flatten\u_neuron_memory.\u_mem.$procmux$5005_Y, Q = \u_neuron_memory.u_mem.rdata).
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Adding SRST signal on $flatten\u_neuron_memory.\u_mem.$procdff$5513 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.\u_mem.$procmux$4963_Y, Q = \u_neuron_memory.u_mem.ready, rval = 1'0).
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Adding SRST signal on $flatten\u_spi_slave.$procdff$5526 ($dff) from module spi_neuron_top (D = $flatten\u_spi_slave.$procmux$5266_Y, Q = \u_spi_slave.miso, rval = 1'0).
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Adding EN signal on $auto$ff.cc:337:slice$6934 ($sdff) from module spi_neuron_top (D = $flatten\u_spi_slave.$procmux$5266_Y, Q = \u_spi_slave.miso).
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Adding SRST signal on $flatten\u_spi_slave.$procdff$5527 ($dff) from module spi_neuron_top (D = $flatten\u_spi_slave.$procmux$5247_Y, Q = \u_spi_slave.rx_byte, rval = 8'00000000).
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Adding EN signal on $auto$ff.cc:337:slice$6946 ($sdff) from module spi_neuron_top (D = { \u_spi_slave.rx_shift [6:0] \u_spi_slave.mosi_sync [2] }, Q = \u_spi_slave.rx_byte).
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Adding SRST signal on $flatten\u_spi_slave.$procdff$5528 ($dff) from module spi_neuron_top (D = $flatten\u_spi_slave.$procmux$5170_Y, Q = \u_spi_slave.rx_valid, rval = 1'0).
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Adding SRST signal on $flatten\u_spi_slave.$procdff$5531 ($dff) from module spi_neuron_top (D = $flatten\u_spi_slave.$procmux$5135_Y, Q = \u_spi_slave.cs_end, rval = 1'0).
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Adding SRST signal on $flatten\u_spi_slave.$procdff$5532 ($dff) from module spi_neuron_top (D = $flatten\u_spi_slave.$procmux$5227_Y, Q = \u_spi_slave.bit_count, rval = 3'000).
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Adding EN signal on $auto$ff.cc:337:slice$6964 ($sdff) from module spi_neuron_top (D = $flatten\u_spi_slave.$procmux$5220_Y, Q = \u_spi_slave.bit_count).
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Adding SRST signal on $flatten\u_spi_slave.$procdff$5533 ($dff) from module spi_neuron_top (D = $flatten\u_spi_slave.$procmux$5213_Y, Q = \u_spi_slave.rx_shift, rval = 8'00000000).
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Adding EN signal on $auto$ff.cc:337:slice$6974 ($sdff) from module spi_neuron_top (D = { \u_spi_slave.rx_shift [6:0] \u_spi_slave.mosi_sync [2] }, Q = \u_spi_slave.rx_shift).
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Adding SRST signal on $flatten\u_spi_slave.$procdff$5534 ($dff) from module spi_neuron_top (D = $flatten\u_spi_slave.$procmux$5199_Y, Q = \u_spi_slave.tx_shift, rval = 8'00000000).
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Adding EN signal on $auto$ff.cc:337:slice$6984 ($sdff) from module spi_neuron_top (D = $flatten\u_spi_slave.$procmux$5199_Y, Q = \u_spi_slave.tx_shift).
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Adding SRST signal on $flatten\u_spi_slave.$procdff$5535 ($dff) from module spi_neuron_top (D = \u_spi_slave.sclk_sync [2], Q = \u_spi_slave.sclk_prev, rval = 1'0).
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Adding SRST signal on $flatten\u_spi_slave.$procdff$5536 ($dff) from module spi_neuron_top (D = \u_spi_slave.cs_n_sync [2], Q = \u_spi_slave.cs_n_prev, rval = 1'1).
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Adding SRST signal on $flatten\u_spi_slave.$procdff$5537 ($dff) from module spi_neuron_top (D = { \u_spi_slave.sclk_sync [1:0] \sclk }, Q = \u_spi_slave.sclk_sync, rval = 3'000).
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Adding SRST signal on $flatten\u_spi_slave.$procdff$5538 ($dff) from module spi_neuron_top (D = { \u_spi_slave.mosi_sync [1:0] \mosi }, Q = \u_spi_slave.mosi_sync, rval = 3'000).
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Adding EN signal on $flatten\u_neuron_memory.$procdff$5318 ($dff) from module spi_neuron_top (D = 8'00000000, Q = \u_neuron_memory.access_wdata).
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Adding SRST signal on $flatten\u_neuron_memory.$procdff$5317 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$procmux$2061_Y, Q = \u_neuron_memory.access_addr, rval = 23'00000000000000000000000).
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Adding EN signal on $auto$ff.cc:337:slice$7001 ($sdff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$procmux$2061_Y, Q = \u_neuron_memory.access_addr).
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Adding SRST signal on $flatten\u_neuron_memory.$procdff$5316 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$procmux$2090_Y, Q = \u_neuron_memory.access_wr, rval = 1'0).
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Adding EN signal on $auto$ff.cc:337:slice$7017 ($sdff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$procmux$2090_Y, Q = \u_neuron_memory.access_wr).
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Adding SRST signal on $flatten\u_neuron_memory.$procdff$5315 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$procmux$2004_Y, Q = \u_neuron_memory.access_req, rval = 1'0).
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Adding SRST signal on $flatten\u_neuron_memory.$procdff$5314 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$procmux$2119_Y, Q = \u_neuron_memory.bias_group_addr, rval = 23'00000000000000000000000).
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Adding EN signal on $auto$ff.cc:337:slice$7034 ($sdff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$procmux$2119_Y, Q = \u_neuron_memory.bias_group_addr).
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Adding SRST signal on $flatten\u_neuron_memory.$procdff$5313 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$procmux$2134_Y, Q = \u_neuron_memory.w_group_base, rval = 23'00000000000000000000000).
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Adding EN signal on $auto$ff.cc:337:slice$7046 ($sdff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$procmux$2134_Y, Q = \u_neuron_memory.w_group_base).
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Adding SRST signal on $flatten\u_neuron_memory.$procdff$5312 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$procmux$2149_Y, Q = \u_neuron_memory.neuron_index, rval = 1'0).
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Adding EN signal on $auto$ff.cc:337:slice$7058 ($sdff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$procmux$2149_Y, Q = \u_neuron_memory.neuron_index).
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Adding SRST signal on $flatten\u_neuron_memory.$procdff$5311 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$procmux$2164_Y, Q = \u_neuron_memory.index, rval = 6'000000).
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Adding EN signal on $auto$ff.cc:337:slice$7070 ($sdff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$procmux$2164_Y, Q = \u_neuron_memory.index).
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Adding SRST signal on $flatten\u_neuron_memory.$procdff$5310 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$procmux$2191_Y, Q = \u_neuron_memory.bias_reg, rval = 8'00000000).
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Adding EN signal on $auto$ff.cc:337:slice$7088 ($sdff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.bias_reg).
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Adding SRST signal on $flatten\u_neuron_memory.$procdff$5309 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$procmux$1992_Y, Q = \u_neuron_memory.neuron_start, rval = 1'0).
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Adding SRST signal on $flatten\u_neuron_memory.$procdff$5308 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$procmux$1975_Y, Q = \u_neuron_memory.done, rval = 1'0).
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Adding SRST signal on $flatten\u_neuron_memory.$procdff$5307 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$procmux$2203_Y, Q = \u_neuron_memory.busy, rval = 1'0).
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Adding EN signal on $auto$ff.cc:337:slice$7100 ($sdff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$procmux$2203_Y, Q = \u_neuron_memory.busy).
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Adding SRST signal on $flatten\u_layer_sequencer.$procdff$5436 ($dff) from module spi_neuron_top (D = $flatten\u_layer_sequencer.$procmux$3546_Y, Q = \u_layer_sequencer.nm_w_base, rval = 23'00000000000000000000000).
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Adding EN signal on $auto$ff.cc:337:slice$7110 ($sdff) from module spi_neuron_top (D = \u_layer_sequencer.w_base_acc [22:0], Q = \u_layer_sequencer.nm_w_base).
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Adding SRST signal on $flatten\u_layer_sequencer.$procdff$5435 ($dff) from module spi_neuron_top (D = $flatten\u_layer_sequencer.$procmux$3555_Y, Q = \u_layer_sequencer.nm_x_base, rval = 23'00000000000000000000000).
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Adding EN signal on $auto$ff.cc:337:slice$7112 ($sdff) from module spi_neuron_top (D = $flatten\u_layer_sequencer.$ternary$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:259$786_Y, Q = \u_layer_sequencer.nm_x_base).
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Adding SRST signal on $flatten\u_spi_slave.$procdff$5539 ($dff) from module spi_neuron_top (D = { \u_spi_slave.cs_n_sync [1:0] \cs_n }, Q = \u_spi_slave.cs_n_sync, rval = 3'111).
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Adding SRST signal on $flatten\u_layer_sequencer.$procdff$5443 ($dff) from module spi_neuron_top (D = $flatten\u_layer_sequencer.$procmux$3467_Y, Q = \u_layer_sequencer.desc_table_addr, rval = 23'00000000000000000000000).
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Adding EN signal on $auto$ff.cc:337:slice$7115 ($sdff) from module spi_neuron_top (D = $flatten\u_layer_sequencer.$procmux$3467_Y, Q = \u_layer_sequencer.desc_table_addr).
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Adding SRST signal on $flatten\u_layer_sequencer.$procdff$5427 ($dff) from module spi_neuron_top (D = $flatten\u_layer_sequencer.$procmux$3283_Y, Q = \u_layer_sequencer.ram_req, rval = 1'0).
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Adding SRST signal on $flatten\u_layer_sequencer.$procdff$5433 ($dff) from module spi_neuron_top (D = $flatten\u_layer_sequencer.$procmux$3424_Y, Q = \u_layer_sequencer.seq_done, rval = 1'0).
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Adding SRST signal on $flatten\u_spi_engine.$procdff$5487 ($dff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$3798_Y, Q = \u_spi_engine.status_snapshot, rval = 8'00000000).
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Adding EN signal on $auto$ff.cc:337:slice$7139 ($sdff) from module spi_neuron_top (D = { 5'00000 \u_graph_engine.err \u_spi_engine.status_done_sticky \u_spi_engine.busy_all }, Q = \u_spi_engine.status_snapshot).
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Adding SRST signal on $flatten\u_neuron_memory.\u_mem.$procdff$5516 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.\u_mem.$procmux$4974_Y, Q = \u_neuron_memory.u_mem.addr_reg, rval = 23'00000000000000000000000).
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Adding EN signal on $auto$ff.cc:337:slice$7145 ($sdff) from module spi_neuron_top (D = \u_neuron_memory.access_addr, Q = \u_neuron_memory.u_mem.addr_reg).
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Adding SRST signal on $flatten\u_graph_engine.\u_neuron.$procdff$5521 ($dff) from module spi_neuron_top (D = $flatten\u_graph_engine.\u_neuron.$procmux$5129_Y, Q = \u_graph_engine.u_neuron.y, rval = 8'00000000).
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Adding EN signal on $auto$ff.cc:337:slice$7149 ($sdff) from module spi_neuron_top (D = $flatten\u_graph_engine.\u_neuron.$procmux$5122_Y, Q = \u_graph_engine.u_neuron.y).
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Adding SRST signal on $flatten\u_graph_engine.\u_neuron.$procdff$5522 ($dff) from module spi_neuron_top (D = $flatten\u_graph_engine.\u_neuron.$procmux$5103_Y, Q = \u_graph_engine.u_neuron.busy, rval = 1'0).
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Adding SRST signal on $flatten\u_graph_engine.\u_neuron.$procdff$5523 ($dff) from module spi_neuron_top (D = $flatten\u_graph_engine.\u_neuron.$procmux$5065_Y, Q = \u_graph_engine.u_neuron.done, rval = 1'0).
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Adding SRST signal on $flatten\u_graph_engine.\u_neuron.$procdff$5524 ($dff) from module spi_neuron_top (D = $flatten\u_graph_engine.\u_neuron.$procmux$5089_Y, Q = \u_graph_engine.u_neuron.group_index, rval = 4'0000).
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Adding EN signal on $auto$ff.cc:337:slice$7161 ($sdff) from module spi_neuron_top (D = $flatten\u_graph_engine.\u_neuron.$add$/tmp/before_rewrite/neuron_parallel.v:194$1333_Y, Q = \u_graph_engine.u_neuron.group_index).
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Adding SRST signal on $flatten\u_graph_engine.\u_neuron.$procdff$5525 ($dff) from module spi_neuron_top (D = $flatten\u_graph_engine.\u_neuron.$procmux$5078_Y, Q = \u_graph_engine.u_neuron.acc, rval = 0).
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Adding EN signal on $auto$ff.cc:337:slice$7169 ($sdff) from module spi_neuron_top (D = $flatten\u_graph_engine.\u_neuron.$procmux$5076_Y, Q = \u_graph_engine.u_neuron.acc).
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Adding SRST signal on $flatten\u_graph_engine.$procdff$5355 ($dff) from module spi_neuron_top (D = $flatten\u_graph_engine.$procmux$2700_Y, Q = \u_graph_engine.n_conn_padded_reg, rval = 16'0000000000000000).
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Adding EN signal on $auto$ff.cc:337:slice$7173 ($sdff) from module spi_neuron_top (D = { $flatten\u_graph_engine.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:394$1022_Y [15:1] 1'0 }, Q = \u_graph_engine.n_conn_padded_reg).
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Adding SRST signal on $flatten\u_graph_engine.$procdff$5354 ($dff) from module spi_neuron_top (D = $flatten\u_graph_engine.$procmux$2718_Y, Q = \u_graph_engine.activation_reg, rval = 2'01).
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Adding EN signal on $auto$ff.cc:337:slice$7177 ($sdff) from module spi_neuron_top (D = \u_arbiter.c_rdata [1:0], Q = \u_graph_engine.activation_reg).
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Adding SRST signal on $flatten\u_graph_engine.$procdff$5353 ($dff) from module spi_neuron_top (D = $flatten\u_graph_engine.$procmux$2735_Y, Q = \u_graph_engine.bias_reg, rval = 8'00000000).
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Adding EN signal on $auto$ff.cc:337:slice$7181 ($sdff) from module spi_neuron_top (D = \u_arbiter.c_rdata, Q = \u_graph_engine.bias_reg).
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Adding SRST signal on $flatten\u_graph_engine.$procdff$5352 ($dff) from module spi_neuron_top (D = $flatten\u_graph_engine.$procmux$2631_Y, Q = \u_graph_engine.neuron_start, rval = 1'0).
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Adding SRST signal on $flatten\u_graph_engine.$procdff$5351 ($dff) from module spi_neuron_top (D = $flatten\u_graph_engine.$procmux$2745_Y, Q = \u_graph_engine.act_wr_data, rval = 8'00000000).
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Adding EN signal on $auto$ff.cc:337:slice$7186 ($sdff) from module spi_neuron_top (D = $flatten\u_graph_engine.$procmux$2745_Y, Q = \u_graph_engine.act_wr_data).
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Adding SRST signal on $flatten\u_graph_engine.$procdff$5350 ($dff) from module spi_neuron_top (D = $flatten\u_graph_engine.$procmux$2758_Y, Q = \u_graph_engine.act_wr_addr, rval = 12'000000000000).
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Adding EN signal on $auto$ff.cc:337:slice$7196 ($sdff) from module spi_neuron_top (D = $flatten\u_graph_engine.$procmux$2758_Y, Q = \u_graph_engine.act_wr_addr).
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Adding SRST signal on $flatten\u_graph_engine.$procdff$5349 ($dff) from module spi_neuron_top (D = $flatten\u_graph_engine.$procmux$2641_Y, Q = \u_graph_engine.act_wr_en, rval = 1'0).
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Adding SRST signal on $flatten\u_graph_engine.$procdff$5348 ($dff) from module spi_neuron_top (D = $flatten\u_graph_engine.$procmux$2776_Y, Q = \u_graph_engine.weight_acc, rval = 8'00000000).
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Adding EN signal on $auto$ff.cc:337:slice$7207 ($sdff) from module spi_neuron_top (D = \u_arbiter.c_rdata, Q = \u_graph_engine.weight_acc).
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Adding SRST signal on $flatten\u_graph_engine.$procdff$5347 ($dff) from module spi_neuron_top (D = { $flatten\u_graph_engine.$procmux$2260_Y $flatten\u_graph_engine.$procmux$2276_Y }, Q = \u_graph_engine.src_id_acc, rval = 16'0000000000000000).
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Adding EN signal on $auto$ff.cc:337:slice$7211 ($sdff) from module spi_neuron_top (D = \u_arbiter.c_rdata, Q = \u_graph_engine.src_id_acc [7:0]).
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Adding EN signal on $auto$ff.cc:337:slice$7211 ($sdff) from module spi_neuron_top (D = \u_arbiter.c_rdata, Q = \u_graph_engine.src_id_acc [15:8]).
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Adding SRST signal on $flatten\u_graph_engine.$procdff$5346 ($dff) from module spi_neuron_top (D = $flatten\u_graph_engine.$procmux$2812_Y, Q = \u_graph_engine.edge_byte_idx, rval = 2'00).
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Adding EN signal on $auto$ff.cc:337:slice$7218 ($sdff) from module spi_neuron_top (D = $flatten\u_graph_engine.$procmux$2812_Y, Q = \u_graph_engine.edge_byte_idx).
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Adding SRST signal on $flatten\u_graph_engine.$procdff$5345 ($dff) from module spi_neuron_top (D = $flatten\u_graph_engine.$procmux$2831_Y, Q = \u_graph_engine.conn_i, rval = 6'000000).
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Adding EN signal on $auto$ff.cc:337:slice$7230 ($sdff) from module spi_neuron_top (D = $flatten\u_graph_engine.$procmux$2831_Y, Q = \u_graph_engine.conn_i).
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Adding SRST signal on $flatten\u_graph_engine.$procdff$5344 ($dff) from module spi_neuron_top (D = { $flatten\u_graph_engine.$procmux$2796_Y $flatten\u_graph_engine.$procmux$2295_Y }, Q = \u_graph_engine.out_id_acc, rval = 16'0000000000000000).
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Adding EN signal on $auto$ff.cc:337:slice$7240 ($sdff) from module spi_neuron_top (D = \u_arbiter.c_rdata, Q = \u_graph_engine.out_id_acc [15:8]).
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Adding EN signal on $auto$ff.cc:337:slice$7240 ($sdff) from module spi_neuron_top (D = \u_arbiter.c_rdata, Q = \u_graph_engine.out_id_acc [7:0]).
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Adding SRST signal on $flatten\u_graph_engine.$procdff$5343 ($dff) from module spi_neuron_top (D = { $flatten\u_graph_engine.$procmux$2859_Y $flatten\u_graph_engine.$procmux$2316_Y }, Q = \u_graph_engine.n_conn_acc, rval = 16'0000000000000000).
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|
Adding EN signal on $auto$ff.cc:337:slice$7247 ($sdff) from module spi_neuron_top (D = \u_arbiter.c_rdata, Q = \u_graph_engine.n_conn_acc [15:8]).
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Adding EN signal on $auto$ff.cc:337:slice$7247 ($sdff) from module spi_neuron_top (D = \u_arbiter.c_rdata, Q = \u_graph_engine.n_conn_acc [7:0]).
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Adding SRST signal on $flatten\u_graph_engine.$procdff$5342 ($dff) from module spi_neuron_top (D = { $flatten\u_graph_engine.$procmux$2364_Y $flatten\u_graph_engine.$procmux$2883_Y $flatten\u_graph_engine.$procmux$2339_Y }, Q = \u_graph_engine.conn_ptr_acc, rval = 24'000000000000000000000000).
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Adding EN signal on $auto$ff.cc:337:slice$7254 ($sdff) from module spi_neuron_top (D = \u_arbiter.c_rdata, Q = \u_graph_engine.conn_ptr_acc [15:8]).
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Adding EN signal on $auto$ff.cc:337:slice$7254 ($sdff) from module spi_neuron_top (D = \u_arbiter.c_rdata, Q = \u_graph_engine.conn_ptr_acc [23:16]).
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Adding EN signal on $auto$ff.cc:337:slice$7254 ($sdff) from module spi_neuron_top (D = \u_arbiter.c_rdata, Q = \u_graph_engine.conn_ptr_acc [7:0]).
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Adding SRST signal on $flatten\u_graph_engine.$procdff$5341 ($dff) from module spi_neuron_top (D = $flatten\u_graph_engine.$procmux$2904_Y, Q = \u_graph_engine.desc_addr, rval = 23'00000000000000000000000).
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Adding EN signal on $auto$ff.cc:337:slice$7264 ($sdff) from module spi_neuron_top (D = $flatten\u_graph_engine.$procmux$2904_Y, Q = \u_graph_engine.desc_addr).
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Adding SRST signal on $flatten\u_graph_engine.$procdff$5340 ($dff) from module spi_neuron_top (D = $flatten\u_graph_engine.$procmux$2927_Y, Q = \u_graph_engine.neuron_idx, rval = 16'0000000000000000).
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Adding EN signal on $auto$ff.cc:337:slice$7278 ($sdff) from module spi_neuron_top (D = $flatten\u_graph_engine.$procmux$2927_Y, Q = \u_graph_engine.neuron_idx).
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Adding SRST signal on $flatten\u_graph_engine.$procdff$5339 ($dff) from module spi_neuron_top (D = $flatten\u_graph_engine.$procmux$2959_Y, Q = \u_graph_engine.in_idx, rval = 16'0000000000000000).
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Adding EN signal on $auto$ff.cc:337:slice$7292 ($sdff) from module spi_neuron_top (D = $flatten\u_graph_engine.$procmux$2959_Y, Q = \u_graph_engine.in_idx).
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Adding SRST signal on $flatten\u_graph_engine.$procdff$5338 ($dff) from module spi_neuron_top (D = $flatten\u_graph_engine.$procmux$2981_Y, Q = \u_graph_engine.err, rval = 1'0).
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Adding EN signal on $auto$ff.cc:337:slice$7304 ($sdff) from module spi_neuron_top (D = $flatten\u_graph_engine.$procmux$2981_Y, Q = \u_graph_engine.err).
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Adding SRST signal on $flatten\u_graph_engine.$procdff$5337 ($dff) from module spi_neuron_top (D = $flatten\u_graph_engine.$procmux$2655_Y, Q = \u_graph_engine.done, rval = 1'0).
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|
Adding SRST signal on $flatten\u_graph_engine.$procdff$5336 ($dff) from module spi_neuron_top (D = $flatten\u_graph_engine.$procmux$2999_Y, Q = \u_graph_engine.busy, rval = 1'0).
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Adding EN signal on $auto$ff.cc:337:slice$7321 ($sdff) from module spi_neuron_top (D = $flatten\u_graph_engine.$procmux$2999_Y, Q = \u_graph_engine.busy).
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Adding SRST signal on $flatten\u_graph_engine.$procdff$5335 ($dff) from module spi_neuron_top (D = $flatten\u_graph_engine.$procmux$3035_Y, Q = \u_graph_engine.desc_byte_idx, rval = 4'0000).
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Adding EN signal on $auto$ff.cc:337:slice$7343 ($sdff) from module spi_neuron_top (D = $flatten\u_graph_engine.$procmux$3035_Y, Q = \u_graph_engine.desc_byte_idx).
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Adding SRST signal on $flatten\u_graph_engine.$procdff$5333 ($dff) from module spi_neuron_top (D = $flatten\u_graph_engine.$procmux$3119_Y, Q = \u_graph_engine.ram_wdata, rval = 8'00000000).
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Adding EN signal on $auto$ff.cc:337:slice$7363 ($sdff) from module spi_neuron_top (D = \u_graph_engine.u_neuron.y, Q = \u_graph_engine.ram_wdata).
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Adding SRST signal on $flatten\u_graph_engine.$procdff$5332 ($dff) from module spi_neuron_top (D = $flatten\u_graph_engine.$procmux$3126_Y, Q = \u_graph_engine.ram_addr, rval = 23'00000000000000000000000).
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Adding EN signal on $auto$ff.cc:337:slice$7365 ($sdff) from module spi_neuron_top (D = $flatten\u_graph_engine.$procmux$3126_Y, Q = \u_graph_engine.ram_addr).
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Adding SRST signal on $flatten\u_graph_engine.$procdff$5331 ($dff) from module spi_neuron_top (D = $flatten\u_graph_engine.$procmux$3139_Y, Q = \u_graph_engine.ram_wr, rval = 1'0).
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Adding EN signal on $auto$ff.cc:337:slice$7373 ($sdff) from module spi_neuron_top (D = $flatten\u_graph_engine.$procmux$3139_Y, Q = \u_graph_engine.ram_wr).
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Adding SRST signal on $flatten\u_graph_engine.$procdff$5330 ($dff) from module spi_neuron_top (D = $flatten\u_graph_engine.$procmux$2616_Y, Q = \u_graph_engine.ram_req, rval = 1'0).
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Adding SRST signal on $flatten\u_layer_sequencer.$procdff$5432 ($dff) from module spi_neuron_top (D = $flatten\u_layer_sequencer.$procmux$3598_Y, Q = \u_layer_sequencer.seq_busy, rval = 1'0).
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Adding EN signal on $auto$ff.cc:337:slice$7382 ($sdff) from module spi_neuron_top (D = $flatten\u_layer_sequencer.$procmux$3598_Y, Q = \u_layer_sequencer.seq_busy).
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Adding SRST signal on $flatten\u_spi_engine.$procdff$5486 ($dff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$3829_Y, Q = \u_spi_engine.graph_mode, rval = 1'0).
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Adding SRST signal on $flatten\u_layer_sequencer.$procdff$5431 ($dff) from module spi_neuron_top (D = $flatten\u_layer_sequencer.$procmux$3293_Y, Q = \u_layer_sequencer.nm_start, rval = 1'0).
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Adding SRST signal on $flatten\u_layer_sequencer.$procdff$5430 ($dff) from module spi_neuron_top (D = $flatten\u_layer_sequencer.$procmux$3608_Y, Q = \u_layer_sequencer.ram_wdata, rval = 8'00000000).
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Adding EN signal on $auto$ff.cc:337:slice$7398 ($sdff) from module spi_neuron_top (D = $flatten\u_layer_sequencer.$shiftx$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:291$791_Y, Q = \u_layer_sequencer.ram_wdata).
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Adding SRST signal on $flatten\u_layer_sequencer.$procdff$5429 ($dff) from module spi_neuron_top (D = $flatten\u_layer_sequencer.$procmux$3615_Y, Q = \u_layer_sequencer.ram_addr, rval = 23'00000000000000000000000).
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Adding EN signal on $auto$ff.cc:337:slice$7400 ($sdff) from module spi_neuron_top (D = $flatten\u_layer_sequencer.$procmux$3615_Y, Q = \u_layer_sequencer.ram_addr).
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Adding SRST signal on $flatten\u_layer_sequencer.$procdff$5428 ($dff) from module spi_neuron_top (D = $flatten\u_layer_sequencer.$procmux$3623_Y, Q = \u_layer_sequencer.ram_wr, rval = 1'0).
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Adding EN signal on $auto$ff.cc:337:slice$7404 ($sdff) from module spi_neuron_top (D = $flatten\u_layer_sequencer.$procmux$3623_Y, Q = \u_layer_sequencer.ram_wr).
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Adding SRST signal on $flatten\u_layer_sequencer.$procdff$5445 ($dff) from module spi_neuron_top (D = { $flatten\u_layer_sequencer.$procmux$3276_Y $flatten\u_layer_sequencer.$procmux$3416_Y $flatten\u_layer_sequencer.$procmux$3252_Y }, Q = \u_layer_sequencer.w_base_acc, rval = 24'000000000000000000000000).
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Adding EN signal on $auto$ff.cc:337:slice$7408 ($sdff) from module spi_neuron_top (D = \u_arbiter.c_rdata, Q = \u_layer_sequencer.w_base_acc [15:8]).
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Adding EN signal on $auto$ff.cc:337:slice$7408 ($sdff) from module spi_neuron_top (D = \u_arbiter.c_rdata, Q = \u_layer_sequencer.w_base_acc [23:16]).
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Adding EN signal on $auto$ff.cc:337:slice$7408 ($sdff) from module spi_neuron_top (D = \u_arbiter.c_rdata, Q = \u_layer_sequencer.w_base_acc [7:0]).
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Adding SRST signal on $flatten\u_layer_sequencer.$procdff$5446 ($dff) from module spi_neuron_top (D = { $flatten\u_layer_sequencer.$procmux$3230_Y $flatten\u_layer_sequencer.$procmux$3375_Y $flatten\u_layer_sequencer.$procmux$3209_Y }, Q = \u_layer_sequencer.bias_addr_acc, rval = 24'000000000000000000000000).
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Adding EN signal on $auto$ff.cc:337:slice$7418 ($sdff) from module spi_neuron_top (D = \u_arbiter.c_rdata, Q = \u_layer_sequencer.bias_addr_acc [15:8]).
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Adding EN signal on $auto$ff.cc:337:slice$7418 ($sdff) from module spi_neuron_top (D = \u_arbiter.c_rdata, Q = \u_layer_sequencer.bias_addr_acc [23:16]).
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Adding EN signal on $auto$ff.cc:337:slice$7418 ($sdff) from module spi_neuron_top (D = \u_arbiter.c_rdata, Q = \u_layer_sequencer.bias_addr_acc [7:0]).
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Adding SRST signal on $flatten\u_spi_engine.$procdff$5485 ($dff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$3860_Y, Q = \u_spi_engine.net_mode, rval = 1'0).
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Adding SRST signal on $flatten\u_layer_sequencer.$procdff$5447 ($dff) from module spi_neuron_top (D = $flatten\u_layer_sequencer.$procmux$3393_Y, Q = \u_layer_sequencer.activation_acc, rval = 8'00000000).
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Adding EN signal on $auto$ff.cc:337:slice$7429 ($sdff) from module spi_neuron_top (D = \u_arbiter.c_rdata, Q = \u_layer_sequencer.activation_acc).
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Adding SRST signal on $flatten\u_spi_engine.$procdff$5483 ($dff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$3912_Y, Q = \u_spi_engine.resp_index, rval = 4'0000).
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Adding EN signal on $auto$ff.cc:337:slice$7433 ($sdff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$3901_Y, Q = \u_spi_engine.resp_index).
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Adding SRST signal on $flatten\u_spi_engine.$procdff$5482 ($dff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$3928_Y, Q = \u_spi_engine.cur_read_byte, rval = 8'00000000).
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Adding EN signal on $auto$ff.cc:337:slice$7449 ($sdff) from module spi_neuron_top (D = \u_arbiter.a_rdata, Q = \u_spi_engine.cur_read_byte).
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Adding SRST signal on $flatten\u_layer_sequencer.$procdff$5448 ($dff) from module spi_neuron_top (D = { $flatten\u_layer_sequencer.$procmux$3355_Y $flatten\u_layer_sequencer.$procmux$3190_Y }, Q = \u_layer_sequencer.n_inputs_acc, rval = 16'0000000000000000).
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Adding EN signal on $auto$ff.cc:337:slice$7455 ($sdff) from module spi_neuron_top (D = \u_arbiter.c_rdata, Q = \u_layer_sequencer.n_inputs_acc [15:8]).
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Adding EN signal on $auto$ff.cc:337:slice$7455 ($sdff) from module spi_neuron_top (D = \u_arbiter.c_rdata, Q = \u_layer_sequencer.n_inputs_acc [7:0]).
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Adding SRST signal on $flatten\u_spi_engine.$procdff$5481 ($dff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$3948_Y, Q = \u_spi_engine.pending_wdata, rval = 8'00000000).
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Adding EN signal on $auto$ff.cc:337:slice$7462 ($sdff) from module spi_neuron_top (D = \u_spi_slave.rx_byte, Q = \u_spi_engine.pending_wdata).
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Adding SRST signal on $flatten\u_layer_sequencer.$procdff$5449 ($dff) from module spi_neuron_top (D = { $flatten\u_layer_sequencer.$procmux$3160_Y $flatten\u_layer_sequencer.$procmux$3174_Y }, Q = \u_layer_sequencer.n_neurons_acc, rval = 16'0000000000000000).
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Adding EN signal on $auto$ff.cc:337:slice$7468 ($sdff) from module spi_neuron_top (D = \u_arbiter.c_rdata, Q = \u_layer_sequencer.n_neurons_acc [15:8]).
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Adding EN signal on $auto$ff.cc:337:slice$7468 ($sdff) from module spi_neuron_top (D = \u_arbiter.c_rdata, Q = \u_layer_sequencer.n_neurons_acc [7:0]).
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Adding SRST signal on $flatten\u_layer_sequencer.$procdff$5450 ($dff) from module spi_neuron_top (D = $flatten\u_layer_sequencer.$procmux$3338_Y, Q = \u_layer_sequencer.cur_sel, rval = 1'0).
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Adding EN signal on $auto$ff.cc:337:slice$7475 ($sdff) from module spi_neuron_top (D = \u_layer_sequencer.write_sel, Q = \u_layer_sequencer.cur_sel).
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Adding SRST signal on $flatten\u_layer_sequencer.$procdff$5451 ($dff) from module spi_neuron_top (D = $flatten\u_layer_sequencer.$procmux$3321_Y, Q = \u_layer_sequencer.write_sel, rval = 1'0).
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Adding EN signal on $auto$ff.cc:337:slice$7481 ($sdff) from module spi_neuron_top (D = $flatten\u_layer_sequencer.$procmux$3321_Y, Q = \u_layer_sequencer.write_sel).
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Adding SRST signal on $flatten\u_layer_sequencer.$procdff$5452 ($dff) from module spi_neuron_top (D = $flatten\u_layer_sequencer.$procmux$3304_Y, Q = \u_layer_sequencer.copy_idx, rval = 1'0).
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Adding EN signal on $auto$ff.cc:337:slice$7495 ($sdff) from module spi_neuron_top (D = $flatten\u_layer_sequencer.$procmux$3304_Y, Q = \u_layer_sequencer.copy_idx).
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Adding SRST signal on $flatten\u_layer_sequencer.$procdff$5437 ($dff) from module spi_neuron_top (D = $flatten\u_layer_sequencer.$procmux$3537_Y, Q = \u_layer_sequencer.nm_bias_addr, rval = 23'00000000000000000000000).
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Adding EN signal on $auto$ff.cc:337:slice$7507 ($sdff) from module spi_neuron_top (D = \u_layer_sequencer.bias_addr_acc [22:0], Q = \u_layer_sequencer.nm_bias_addr).
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Adding SRST signal on $flatten\u_layer_sequencer.$procdff$5438 ($dff) from module spi_neuron_top (D = $flatten\u_layer_sequencer.$procmux$3528_Y, Q = \u_layer_sequencer.nm_activation, rval = 2'01).
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Adding EN signal on $auto$ff.cc:337:slice$7509 ($sdff) from module spi_neuron_top (D = \u_layer_sequencer.activation_acc [1:0], Q = \u_layer_sequencer.nm_activation).
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Adding SRST signal on $flatten\u_layer_sequencer.$procdff$5439 ($dff) from module spi_neuron_top (D = $flatten\u_layer_sequencer.$procmux$3519_Y, Q = \u_layer_sequencer.nm_n_inputs, rval = 16'0000000000000000).
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Adding EN signal on $auto$ff.cc:337:slice$7511 ($sdff) from module spi_neuron_top (D = \u_layer_sequencer.n_inputs_acc, Q = \u_layer_sequencer.nm_n_inputs).
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Adding SRST signal on $flatten\u_layer_sequencer.$procdff$5440 ($dff) from module spi_neuron_top (D = $flatten\u_layer_sequencer.$procmux$3510_Y, Q = \u_layer_sequencer.nm_n_neurons, rval = 16'0000000000000000).
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Adding EN signal on $auto$ff.cc:337:slice$7513 ($sdff) from module spi_neuron_top (D = \u_layer_sequencer.n_neurons_acc, Q = \u_layer_sequencer.nm_n_neurons).
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Adding SRST signal on $flatten\u_layer_sequencer.$procdff$5441 ($dff) from module spi_neuron_top (D = $flatten\u_layer_sequencer.$procmux$3498_Y, Q = \u_layer_sequencer.layer_idx, rval = 8'00000000).
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Adding EN signal on $auto$ff.cc:337:slice$7515 ($sdff) from module spi_neuron_top (D = $flatten\u_layer_sequencer.$procmux$3498_Y, Q = \u_layer_sequencer.layer_idx).
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Adding SRST signal on $flatten\u_layer_sequencer.$procdff$5442 ($dff) from module spi_neuron_top (D = $flatten\u_layer_sequencer.$procmux$3484_Y, Q = \u_layer_sequencer.num_layers_reg, rval = 8'00000000).
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Adding EN signal on $auto$ff.cc:337:slice$7529 ($sdff) from module spi_neuron_top (D = \u_spi_engine.run_num_layers, Q = \u_layer_sequencer.num_layers_reg).
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Adding SRST signal on $flatten\u_spi_engine.$procdff$5488 ($dff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$4701_Y, Q = \u_spi_engine.status_done_sticky, rval = 1'0).
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Adding EN signal on $auto$ff.cc:337:slice$7533 ($sdff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$4701_Y, Q = \u_spi_engine.status_done_sticky).
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Setting constant 0-bit at position 0 on $auto$ff.cc:337:slice$7174 ($sdffe) from module spi_neuron_top.
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Setting constant 0-bit at position 3 on $auto$ff.cc:337:slice$7140 ($sdffe) from module spi_neuron_top.
|
|
Setting constant 0-bit at position 4 on $auto$ff.cc:337:slice$7140 ($sdffe) from module spi_neuron_top.
|
|
Setting constant 0-bit at position 5 on $auto$ff.cc:337:slice$7140 ($sdffe) from module spi_neuron_top.
|
|
Setting constant 0-bit at position 6 on $auto$ff.cc:337:slice$7140 ($sdffe) from module spi_neuron_top.
|
|
Setting constant 0-bit at position 7 on $auto$ff.cc:337:slice$7140 ($sdffe) from module spi_neuron_top.
|
|
Setting constant 0-bit at position 0 on $auto$ff.cc:337:slice$7000 ($dffe) from module spi_neuron_top.
|
|
Setting constant 0-bit at position 1 on $auto$ff.cc:337:slice$7000 ($dffe) from module spi_neuron_top.
|
|
Setting constant 0-bit at position 2 on $auto$ff.cc:337:slice$7000 ($dffe) from module spi_neuron_top.
|
|
Setting constant 0-bit at position 3 on $auto$ff.cc:337:slice$7000 ($dffe) from module spi_neuron_top.
|
|
Setting constant 0-bit at position 4 on $auto$ff.cc:337:slice$7000 ($dffe) from module spi_neuron_top.
|
|
Setting constant 0-bit at position 5 on $auto$ff.cc:337:slice$7000 ($dffe) from module spi_neuron_top.
|
|
Setting constant 0-bit at position 6 on $auto$ff.cc:337:slice$7000 ($dffe) from module spi_neuron_top.
|
|
Setting constant 0-bit at position 7 on $auto$ff.cc:337:slice$7000 ($dffe) from module spi_neuron_top.
|
|
Setting constant 0-bit at position 22 on $auto$ff.cc:337:slice$6830 ($sdffe) from module spi_neuron_top.
|
|
|
|
17.14.7. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \spi_neuron_top..
|
|
Removed 481 unused cells and 631 unused wires.
|
|
<suppressed ~482 debug messages>
|
|
|
|
17.14.8. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module spi_neuron_top.
|
|
<suppressed ~46 debug messages>
|
|
|
|
17.14.9. Rerunning OPT passes. (Maybe there is more to do..)
|
|
|
|
17.14.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \spi_neuron_top..
|
|
Creating internal representation of mux trees.
|
|
Evaluating internal representation of mux trees.
|
|
Analyzing evaluation results.
|
|
Removed 0 multiplexer ports.
|
|
<suppressed ~541 debug messages>
|
|
|
|
17.14.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \spi_neuron_top.
|
|
Performed a total of 0 changes.
|
|
|
|
17.14.12. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\spi_neuron_top'.
|
|
Computing hashes of 1617 cells of `\spi_neuron_top'.
|
|
Finding duplicate cells in `\spi_neuron_top'.
|
|
Computing hashes of 1475 cells of `\spi_neuron_top'.
|
|
Finding duplicate cells in `\spi_neuron_top'.
|
|
Computing hashes of 1463 cells of `\spi_neuron_top'.
|
|
Finding duplicate cells in `\spi_neuron_top'.
|
|
<suppressed ~462 debug messages>
|
|
Removed a total of 154 cells.
|
|
|
|
17.14.13. Executing OPT_DFF pass (perform DFF optimizations).
|
|
Setting constant 0-bit at position 2 on $flatten\u_spi_engine.$procdff$5484 ($dff) from module spi_neuron_top.
|
|
Setting constant 0-bit at position 22 on $auto$ff.cc:337:slice$6788 ($sdffe) from module spi_neuron_top.
|
|
|
|
17.14.14. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \spi_neuron_top..
|
|
Removed 0 unused cells and 154 unused wires.
|
|
<suppressed ~1 debug messages>
|
|
|
|
17.14.15. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module spi_neuron_top.
|
|
|
|
17.14.16. Rerunning OPT passes. (Maybe there is more to do..)
|
|
|
|
17.14.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \spi_neuron_top..
|
|
Creating internal representation of mux trees.
|
|
Evaluating internal representation of mux trees.
|
|
Analyzing evaluation results.
|
|
Removed 0 multiplexer ports.
|
|
<suppressed ~550 debug messages>
|
|
|
|
17.14.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \spi_neuron_top.
|
|
Performed a total of 0 changes.
|
|
|
|
17.14.19. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\spi_neuron_top'.
|
|
Computing hashes of 1463 cells of `\spi_neuron_top'.
|
|
Finding duplicate cells in `\spi_neuron_top'.
|
|
Removed a total of 0 cells.
|
|
|
|
17.14.20. Executing OPT_DFF pass (perform DFF optimizations).
|
|
Setting constant 0-bit at position 22 on $auto$ff.cc:337:slice$6622 ($sdffe) from module spi_neuron_top.
|
|
|
|
17.14.21. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \spi_neuron_top..
|
|
|
|
17.14.22. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module spi_neuron_top.
|
|
|
|
17.14.23. Rerunning OPT passes. (Maybe there is more to do..)
|
|
|
|
17.14.24. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \spi_neuron_top..
|
|
Creating internal representation of mux trees.
|
|
Evaluating internal representation of mux trees.
|
|
Analyzing evaluation results.
|
|
Removed 0 multiplexer ports.
|
|
<suppressed ~550 debug messages>
|
|
|
|
17.14.25. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \spi_neuron_top.
|
|
Performed a total of 0 changes.
|
|
|
|
17.14.26. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\spi_neuron_top'.
|
|
Computing hashes of 1463 cells of `\spi_neuron_top'.
|
|
Finding duplicate cells in `\spi_neuron_top'.
|
|
Removed a total of 0 cells.
|
|
|
|
17.14.27. Executing OPT_DFF pass (perform DFF optimizations).
|
|
|
|
17.14.28. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \spi_neuron_top..
|
|
|
|
17.14.29. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module spi_neuron_top.
|
|
|
|
17.14.30. Finished fast OPT passes. (There is nothing left to do.)
|
|
|
|
17.15. Executing WREDUCE pass (reducing word size of cells).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:214$1049 (u_graph_engine.x_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:215$1050 (u_graph_engine.w_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:214$1051 (u_graph_engine.x_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:215$1052 (u_graph_engine.w_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:214$1053 (u_graph_engine.x_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:215$1054 (u_graph_engine.w_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:214$1055 (u_graph_engine.x_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:215$1056 (u_graph_engine.w_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:214$1057 (u_graph_engine.x_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:215$1058 (u_graph_engine.w_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:214$1059 (u_graph_engine.x_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:215$1060 (u_graph_engine.w_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:214$1061 (u_graph_engine.x_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:215$1062 (u_graph_engine.w_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:214$1063 (u_graph_engine.x_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:215$1064 (u_graph_engine.w_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:214$1065 (u_graph_engine.x_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:215$1066 (u_graph_engine.w_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:214$1067 (u_graph_engine.x_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:215$1068 (u_graph_engine.w_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:214$1069 (u_graph_engine.x_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:215$1070 (u_graph_engine.w_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:214$1071 (u_graph_engine.x_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:215$1072 (u_graph_engine.w_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:214$1073 (u_graph_engine.x_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:215$1074 (u_graph_engine.w_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:214$1075 (u_graph_engine.x_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:215$1076 (u_graph_engine.w_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:214$1077 (u_graph_engine.x_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:215$1078 (u_graph_engine.w_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:214$1079 (u_graph_engine.x_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:215$1080 (u_graph_engine.w_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:214$1081 (u_graph_engine.x_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:215$1082 (u_graph_engine.w_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:214$1083 (u_graph_engine.x_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:215$1084 (u_graph_engine.w_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:214$1085 (u_graph_engine.x_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:215$1086 (u_graph_engine.w_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:214$1087 (u_graph_engine.x_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:215$1088 (u_graph_engine.w_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:214$1089 (u_graph_engine.x_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:215$1090 (u_graph_engine.w_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:214$1091 (u_graph_engine.x_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:215$1092 (u_graph_engine.w_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:214$1093 (u_graph_engine.x_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:215$1094 (u_graph_engine.w_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:214$1095 (u_graph_engine.x_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:215$1096 (u_graph_engine.w_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:214$1097 (u_graph_engine.x_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:215$1098 (u_graph_engine.w_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:214$1099 (u_graph_engine.x_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:215$1100 (u_graph_engine.w_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:214$1101 (u_graph_engine.x_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:215$1102 (u_graph_engine.w_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:214$1103 (u_graph_engine.x_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:215$1104 (u_graph_engine.w_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:214$1105 (u_graph_engine.x_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:215$1106 (u_graph_engine.w_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:214$1107 (u_graph_engine.x_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:215$1108 (u_graph_engine.w_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:214$1109 (u_graph_engine.x_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:215$1110 (u_graph_engine.w_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:214$1111 (u_graph_engine.x_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:215$1112 (u_graph_engine.w_mem).
|
|
Removed top 1 address bits (of 6) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$5608 (u_graph_engine.x_mem).
|
|
Removed top 1 address bits (of 6) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$5609 (u_graph_engine.w_mem).
|
|
Removed top 28 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_spi_engine.$auto$mem.cc:351:emit$1577 ($flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1575).
|
|
Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$5544 (u_graph_engine.x_mem).
|
|
Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$5545 (u_graph_engine.w_mem).
|
|
Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$5546 (u_graph_engine.x_mem).
|
|
Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$5547 (u_graph_engine.w_mem).
|
|
Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$5548 (u_graph_engine.x_mem).
|
|
Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$5549 (u_graph_engine.w_mem).
|
|
Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$5550 (u_graph_engine.x_mem).
|
|
Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$5551 (u_graph_engine.w_mem).
|
|
Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$5552 (u_graph_engine.x_mem).
|
|
Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$5553 (u_graph_engine.w_mem).
|
|
Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$5554 (u_graph_engine.x_mem).
|
|
Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$5555 (u_graph_engine.w_mem).
|
|
Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$5556 (u_graph_engine.x_mem).
|
|
Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$5557 (u_graph_engine.w_mem).
|
|
Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$5558 (u_graph_engine.x_mem).
|
|
Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$5559 (u_graph_engine.w_mem).
|
|
Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$5560 (u_graph_engine.x_mem).
|
|
Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$5561 (u_graph_engine.w_mem).
|
|
Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$5562 (u_graph_engine.x_mem).
|
|
Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$5563 (u_graph_engine.w_mem).
|
|
Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$5564 (u_graph_engine.x_mem).
|
|
Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$5565 (u_graph_engine.w_mem).
|
|
Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$5566 (u_graph_engine.x_mem).
|
|
Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$5567 (u_graph_engine.w_mem).
|
|
Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$5568 (u_graph_engine.x_mem).
|
|
Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$5569 (u_graph_engine.w_mem).
|
|
Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$5570 (u_graph_engine.x_mem).
|
|
Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$5571 (u_graph_engine.w_mem).
|
|
Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$5572 (u_graph_engine.x_mem).
|
|
Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$5573 (u_graph_engine.w_mem).
|
|
Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$5574 (u_graph_engine.x_mem).
|
|
Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$5575 (u_graph_engine.w_mem).
|
|
Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$5576 (u_graph_engine.x_mem).
|
|
Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$5577 (u_graph_engine.w_mem).
|
|
Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$5578 (u_graph_engine.x_mem).
|
|
Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$5579 (u_graph_engine.w_mem).
|
|
Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$5580 (u_graph_engine.x_mem).
|
|
Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$5581 (u_graph_engine.w_mem).
|
|
Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$5582 (u_graph_engine.x_mem).
|
|
Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$5583 (u_graph_engine.w_mem).
|
|
Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$5584 (u_graph_engine.x_mem).
|
|
Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$5585 (u_graph_engine.w_mem).
|
|
Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$5586 (u_graph_engine.x_mem).
|
|
Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$5587 (u_graph_engine.w_mem).
|
|
Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$5588 (u_graph_engine.x_mem).
|
|
Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$5589 (u_graph_engine.w_mem).
|
|
Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$5590 (u_graph_engine.x_mem).
|
|
Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$5591 (u_graph_engine.w_mem).
|
|
Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$5592 (u_graph_engine.x_mem).
|
|
Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$5593 (u_graph_engine.w_mem).
|
|
Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$5594 (u_graph_engine.x_mem).
|
|
Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$5595 (u_graph_engine.w_mem).
|
|
Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$5596 (u_graph_engine.x_mem).
|
|
Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$5597 (u_graph_engine.w_mem).
|
|
Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$5598 (u_graph_engine.x_mem).
|
|
Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$5599 (u_graph_engine.w_mem).
|
|
Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$5600 (u_graph_engine.x_mem).
|
|
Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$5601 (u_graph_engine.w_mem).
|
|
Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$5602 (u_graph_engine.x_mem).
|
|
Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$5603 (u_graph_engine.w_mem).
|
|
Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$5604 (u_graph_engine.x_mem).
|
|
Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$5605 (u_graph_engine.w_mem).
|
|
Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$5606 (u_graph_engine.x_mem).
|
|
Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$5607 (u_graph_engine.w_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:129$1173 (u_neuron_memory.x_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:130$1174 (u_neuron_memory.w_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:129$1175 (u_neuron_memory.x_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:130$1176 (u_neuron_memory.w_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:129$1177 (u_neuron_memory.x_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:130$1178 (u_neuron_memory.w_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:129$1179 (u_neuron_memory.x_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:130$1180 (u_neuron_memory.w_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:129$1181 (u_neuron_memory.x_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:130$1182 (u_neuron_memory.w_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:129$1183 (u_neuron_memory.x_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:130$1184 (u_neuron_memory.w_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:129$1185 (u_neuron_memory.x_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:130$1186 (u_neuron_memory.w_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:129$1187 (u_neuron_memory.x_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:130$1188 (u_neuron_memory.w_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:129$1189 (u_neuron_memory.x_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:130$1190 (u_neuron_memory.w_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:129$1191 (u_neuron_memory.x_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:130$1192 (u_neuron_memory.w_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:129$1193 (u_neuron_memory.x_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:130$1194 (u_neuron_memory.w_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:129$1195 (u_neuron_memory.x_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:130$1196 (u_neuron_memory.w_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:129$1197 (u_neuron_memory.x_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:130$1198 (u_neuron_memory.w_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:129$1199 (u_neuron_memory.x_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:130$1200 (u_neuron_memory.w_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:129$1201 (u_neuron_memory.x_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:130$1202 (u_neuron_memory.w_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:129$1203 (u_neuron_memory.x_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:130$1204 (u_neuron_memory.w_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:129$1205 (u_neuron_memory.x_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:130$1206 (u_neuron_memory.w_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:129$1207 (u_neuron_memory.x_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:130$1208 (u_neuron_memory.w_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:129$1209 (u_neuron_memory.x_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:130$1210 (u_neuron_memory.w_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:129$1211 (u_neuron_memory.x_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:130$1212 (u_neuron_memory.w_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:129$1213 (u_neuron_memory.x_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:130$1214 (u_neuron_memory.w_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:129$1215 (u_neuron_memory.x_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:130$1216 (u_neuron_memory.w_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:129$1217 (u_neuron_memory.x_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:130$1218 (u_neuron_memory.w_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:129$1219 (u_neuron_memory.x_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:130$1220 (u_neuron_memory.w_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:129$1221 (u_neuron_memory.x_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:130$1222 (u_neuron_memory.w_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:129$1223 (u_neuron_memory.x_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:130$1224 (u_neuron_memory.w_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:129$1225 (u_neuron_memory.x_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:130$1226 (u_neuron_memory.w_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:129$1227 (u_neuron_memory.x_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:130$1228 (u_neuron_memory.w_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:129$1229 (u_neuron_memory.x_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:130$1230 (u_neuron_memory.w_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:129$1231 (u_neuron_memory.x_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:130$1232 (u_neuron_memory.w_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:129$1233 (u_neuron_memory.x_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:130$1234 (u_neuron_memory.w_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:129$1235 (u_neuron_memory.x_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:130$1236 (u_neuron_memory.w_mem).
|
|
Removed top 32 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\y_reg$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:140$1237 (u_neuron_memory.y_reg).
|
|
Removed top 32 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_neuron_memory.$auto$proc_memwr.cc:45:proc_memwr$5540 (u_neuron_memory.y_reg).
|
|
Removed top 1 address bits (of 6) from memory init port spi_neuron_top.$flatten\u_neuron_memory.$auto$proc_memwr.cc:45:proc_memwr$5541 (u_neuron_memory.x_mem).
|
|
Removed top 1 address bits (of 6) from memory init port spi_neuron_top.$flatten\u_neuron_memory.$auto$proc_memwr.cc:45:proc_memwr$5542 (u_neuron_memory.w_mem).
|
|
Removed top 1 address bits (of 1) from memory init port spi_neuron_top.$flatten\u_neuron_memory.$auto$proc_memwr.cc:45:proc_memwr$5543 (u_neuron_memory.y_reg).
|
|
Removed top 1 bits (of 3) from FF cell spi_neuron_top.$auto$ff.cc:337:slice$7542 ($dff).
|
|
Removed top 1 bits (of 2) from port B of cell spi_neuron_top.$auto$opt_dff.cc:320:make_patterns_logic$7444 ($ne).
|
|
Removed top 6 bits (of 8) from FF cell spi_neuron_top.$auto$ff.cc:337:slice$7430 ($sdffe).
|
|
Removed top 1 bits (of 8) from FF cell spi_neuron_top.$auto$ff.cc:337:slice$7422 ($sdffe).
|
|
Removed top 1 bits (of 8) from FF cell spi_neuron_top.$auto$ff.cc:337:slice$7412 ($sdffe).
|
|
Removed top 1 bits (of 2) from port B of cell spi_neuron_top.$auto$opt_dff.cc:320:make_patterns_logic$7269 ($ne).
|
|
Removed top 1 bits (of 8) from FF cell spi_neuron_top.$auto$ff.cc:337:slice$7258 ($sdffe).
|
|
Removed top 22 bits (of 23) from FF cell spi_neuron_top.$auto$ff.cc:337:slice$7146 ($sdffe).
|
|
Removed top 1 bits (of 2) from port B of cell spi_neuron_top.$auto$opt_dff.cc:320:make_patterns_logic$7024 ($ne).
|
|
Removed top 1 bits (of 2) from port B of cell spi_neuron_top.$auto$opt_dff.cc:320:make_patterns_logic$7022 ($ne).
|
|
Removed top 1 bits (of 2) from port B of cell spi_neuron_top.$auto$opt_dff.cc:320:make_patterns_logic$6987 ($ne).
|
|
Removed top 1 bits (of 8) from FF cell spi_neuron_top.$auto$ff.cc:337:slice$6985 ($sdffe).
|
|
Removed top 1 bits (of 8) from FF cell spi_neuron_top.$auto$ff.cc:337:slice$6975 ($sdffe).
|
|
Removed top 1 bits (of 2) from port B of cell spi_neuron_top.$auto$opt_dff.cc:320:make_patterns_logic$6803 ($ne).
|
|
Removed top 1 bits (of 2) from port B of cell spi_neuron_top.$auto$opt_dff.cc:320:make_patterns_logic$6651 ($ne).
|
|
Removed top 1 bits (of 2) from port B of cell spi_neuron_top.$auto$opt_dff.cc:320:make_patterns_logic$6597 ($ne).
|
|
Removed top 1 bits (of 2) from port B of cell spi_neuron_top.$auto$opt_dff.cc:320:make_patterns_logic$6546 ($ne).
|
|
Removed top 1 bits (of 2) from port B of cell spi_neuron_top.$auto$opt_dff.cc:320:make_patterns_logic$6542 ($ne).
|
|
Removed top 8 bits (of 24) from FF cell spi_neuron_top.$auto$ff.cc:337:slice$6536 ($sdffe).
|
|
Removed top 1 bits (of 2) from port B of cell spi_neuron_top.$auto$opt_dff.cc:320:make_patterns_logic$6509 ($ne).
|
|
Removed top 1 bits (of 2) from port B of cell spi_neuron_top.$auto$opt_dff.cc:320:make_patterns_logic$6499 ($ne).
|
|
Removed top 1 bits (of 2) from port B of cell spi_neuron_top.$auto$opt_dff.cc:320:make_patterns_logic$6483 ($ne).
|
|
Removed top 1 bits (of 2) from port B of cell spi_neuron_top.$auto$opt_dff.cc:320:make_patterns_logic$6481 ($ne).
|
|
Removed top 22 bits (of 23) from FF cell spi_neuron_top.$auto$ff.cc:337:slice$6467 ($sdffe).
|
|
Removed top 1 bits (of 4) from port B of cell spi_neuron_top.$auto$fsm_map.cc:77:implement_pattern_cache$6403 ($eq).
|
|
Removed top 1 bits (of 3) from port B of cell spi_neuron_top.$auto$fsm_map.cc:77:implement_pattern_cache$6364 ($eq).
|
|
Removed top 2 bits (of 4) from port B of cell spi_neuron_top.$auto$fsm_map.cc:77:implement_pattern_cache$6294 ($eq).
|
|
Removed top 2 bits (of 4) from port B of cell spi_neuron_top.$auto$fsm_map.cc:77:implement_pattern_cache$6263 ($eq).
|
|
Removed top 1 bits (of 3) from port B of cell spi_neuron_top.$auto$fsm_map.cc:77:implement_pattern_cache$6135 ($eq).
|
|
Removed top 1 bits (of 3) from port B of cell spi_neuron_top.$auto$fsm_map.cc:77:implement_pattern_cache$6063 ($eq).
|
|
Removed top 1 bits (of 3) from port B of cell spi_neuron_top.$auto$fsm_map.cc:77:implement_pattern_cache$6058 ($eq).
|
|
Removed top 2 bits (of 4) from port B of cell spi_neuron_top.$auto$fsm_map.cc:77:implement_pattern_cache$5990 ($eq).
|
|
Removed top 1 bits (of 3) from port B of cell spi_neuron_top.$auto$fsm_map.cc:77:implement_pattern_cache$5982 ($eq).
|
|
Removed top 1 bits (of 3) from port B of cell spi_neuron_top.$auto$fsm_map.cc:77:implement_pattern_cache$5978 ($eq).
|
|
Removed top 1 bits (of 3) from port B of cell spi_neuron_top.$auto$fsm_map.cc:77:implement_pattern_cache$5965 ($eq).
|
|
Removed top 1 bits (of 3) from port B of cell spi_neuron_top.$auto$fsm_map.cc:77:implement_pattern_cache$5951 ($eq).
|
|
Removed top 1 bits (of 2) from port B of cell spi_neuron_top.$auto$fsm_map.cc:77:implement_pattern_cache$5945 ($eq).
|
|
Removed top 1 bits (of 4) from port B of cell spi_neuron_top.$auto$fsm_map.cc:77:implement_pattern_cache$5890 ($eq).
|
|
Removed top 1 bits (of 3) from port B of cell spi_neuron_top.$auto$fsm_map.cc:77:implement_pattern_cache$5855 ($eq).
|
|
Removed top 1 bits (of 3) from port B of cell spi_neuron_top.$auto$fsm_map.cc:77:implement_pattern_cache$5830 ($eq).
|
|
Removed top 15 bits (of 16) from mux cell spi_neuron_top.$ternary$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_neuron_top.v:289$620 ($mux).
|
|
Removed top 11 bits (of 14) from port B of cell spi_neuron_top.$flatten\u_psram_ctrl.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/psram_controller.v:292$1245 ($eq).
|
|
Removed top 23 bits (of 32) from port B of cell spi_neuron_top.$flatten\u_neuron_memory.\u_neuron.$shiftx$/tmp/before_rewrite/neuron_parallel.v:101$1318 ($shiftx).
|
|
Removed top 23 bits (of 32) from port B of cell spi_neuron_top.$flatten\u_neuron_memory.\u_neuron.$shiftx$/tmp/before_rewrite/neuron_parallel.v:107$1322 ($shiftx).
|
|
Removed top 24 bits (of 32) from port B of cell spi_neuron_top.$flatten\u_neuron_memory.\u_neuron.$add$/tmp/before_rewrite/neuron_parallel.v:128$1323 ($add).
|
|
Removed top 24 bits (of 32) from port B of cell spi_neuron_top.$flatten\u_neuron_memory.\u_neuron.$lt$/tmp/before_rewrite/neuron_parallel.v:165$1330 ($lt).
|
|
Removed top 31 bits (of 32) from port B of cell spi_neuron_top.$flatten\u_neuron_memory.\u_neuron.$le$/tmp/before_rewrite/neuron_parallel.v:176$1331 ($le).
|
|
Removed top 24 bits (of 32) from port B of cell spi_neuron_top.$flatten\u_neuron_memory.\u_neuron.$gt$/tmp/before_rewrite/neuron_parallel.v:178$1332 ($gt).
|
|
Converting cell spi_neuron_top.$flatten\u_neuron_memory.\u_neuron.\u_mac8.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101$1348 ($add) from unsigned to signed.
|
|
Removed top 16 bits (of 32) from port A of cell spi_neuron_top.$flatten\u_neuron_memory.\u_neuron.\u_mac8.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101$1348 ($add).
|
|
Removed top 16 bits (of 32) from port B of cell spi_neuron_top.$flatten\u_neuron_memory.\u_neuron.\u_mac8.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101$1348 ($add).
|
|
Removed top 15 bits (of 32) from port Y of cell spi_neuron_top.$flatten\u_neuron_memory.\u_neuron.\u_mac8.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101$1348 ($add).
|
|
Removed top 1 bits (of 6) from mux cell spi_neuron_top.$flatten\u_neuron_memory.$procmux$2049 ($mux).
|
|
Removed top 1 bits (of 6) from mux cell spi_neuron_top.$flatten\u_neuron_memory.$procmux$2040 ($mux).
|
|
Removed cell spi_neuron_top.$flatten\u_neuron_memory.$procmux$2031 ($mux).
|
|
Removed top 1 bits (of 6) from mux cell spi_neuron_top.$flatten\u_neuron_memory.$procmux$1967 ($mux).
|
|
Removed top 1 bits (of 6) from mux cell spi_neuron_top.$flatten\u_neuron_memory.$procmux$1937 ($mux).
|
|
Removed cell spi_neuron_top.$flatten\u_neuron_memory.$procmux$1910 ($mux).
|
|
Removed top 1 bits (of 6) from mux cell spi_neuron_top.$flatten\u_neuron_memory.$procmux$1851 ($mux).
|
|
Removed cell spi_neuron_top.$flatten\u_neuron_memory.$procmux$1815 ($mux).
|
|
Removed top 23 bits (of 32) from port B of cell spi_neuron_top.$flatten\u_graph_engine.\u_neuron.$shiftx$/tmp/before_rewrite/neuron_parallel.v:101$1318 ($shiftx).
|
|
Removed top 23 bits (of 32) from port B of cell spi_neuron_top.$flatten\u_graph_engine.\u_neuron.$shiftx$/tmp/before_rewrite/neuron_parallel.v:107$1322 ($shiftx).
|
|
Removed top 24 bits (of 32) from port B of cell spi_neuron_top.$flatten\u_graph_engine.\u_neuron.$add$/tmp/before_rewrite/neuron_parallel.v:128$1323 ($add).
|
|
Removed top 24 bits (of 32) from port B of cell spi_neuron_top.$flatten\u_graph_engine.\u_neuron.$lt$/tmp/before_rewrite/neuron_parallel.v:165$1330 ($lt).
|
|
Removed top 31 bits (of 32) from port B of cell spi_neuron_top.$flatten\u_graph_engine.\u_neuron.$le$/tmp/before_rewrite/neuron_parallel.v:176$1331 ($le).
|
|
Removed top 24 bits (of 32) from port B of cell spi_neuron_top.$flatten\u_graph_engine.\u_neuron.$gt$/tmp/before_rewrite/neuron_parallel.v:178$1332 ($gt).
|
|
Converting cell spi_neuron_top.$flatten\u_graph_engine.\u_neuron.\u_mac8.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101$1348 ($add) from unsigned to signed.
|
|
Removed top 16 bits (of 32) from port A of cell spi_neuron_top.$flatten\u_graph_engine.\u_neuron.\u_mac8.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101$1348 ($add).
|
|
Removed top 16 bits (of 32) from port B of cell spi_neuron_top.$flatten\u_graph_engine.\u_neuron.\u_mac8.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101$1348 ($add).
|
|
Removed top 15 bits (of 32) from port Y of cell spi_neuron_top.$flatten\u_graph_engine.\u_neuron.\u_mac8.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101$1348 ($add).
|
|
Removed top 3 bits (of 4) from port B of cell spi_neuron_top.$flatten\u_graph_engine.$procmux$2880_CMP0 ($eq).
|
|
Removed top 2 bits (of 4) from port B of cell spi_neuron_top.$flatten\u_graph_engine.$procmux$2856_CMP0 ($eq).
|
|
Removed top 1 bits (of 4) from port B of cell spi_neuron_top.$flatten\u_graph_engine.$procmux$2793_CMP0 ($eq).
|
|
Removed top 1 bits (of 4) from port B of cell spi_neuron_top.$flatten\u_graph_engine.$procmux$2715_CMP0 ($eq).
|
|
Removed top 1 bits (of 6) from mux cell spi_neuron_top.$flatten\u_graph_engine.$procmux$2676 ($mux).
|
|
Removed top 1 bits (of 6) from mux cell spi_neuron_top.$flatten\u_graph_engine.$procmux$2384 ($mux).
|
|
Removed top 2 bits (of 4) from port B of cell spi_neuron_top.$flatten\u_graph_engine.$procmux$2336_CMP0 ($eq).
|
|
Removed top 1 bits (of 4) from port B of cell spi_neuron_top.$flatten\u_graph_engine.$procmux$2313_CMP0 ($eq).
|
|
Removed top 1 bits (of 4) from port B of cell spi_neuron_top.$flatten\u_graph_engine.$procmux$2292_CMP0 ($eq).
|
|
Removed top 1 bits (of 2) from port B of cell spi_neuron_top.$flatten\u_graph_engine.$procmux$2273_CMP0 ($eq).
|
|
Removed top 28 bits (of 32) from port B of cell spi_neuron_top.$flatten\u_graph_engine.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:533$1043 ($add).
|
|
Removed top 9 bits (of 32) from port Y of cell spi_neuron_top.$flatten\u_graph_engine.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:533$1043 ($add).
|
|
Removed top 15 bits (of 16) from port B of cell spi_neuron_top.$flatten\u_graph_engine.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:532$1042 ($add).
|
|
Removed top 15 bits (of 16) from port B of cell spi_neuron_top.$flatten\u_graph_engine.$sub$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:527$1040 ($sub).
|
|
Removed top 1 bits (of 2) from port B of cell spi_neuron_top.$flatten\u_graph_engine.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:478$1036 ($add).
|
|
Removed top 3 bits (of 16) from port B of cell spi_neuron_top.$flatten\u_graph_engine.$ge$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:458$1034 ($ge).
|
|
Removed top 3 bits (of 16) from port B of cell spi_neuron_top.$flatten\u_graph_engine.$ge$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:457$1032 ($ge).
|
|
Removed top 9 bits (of 32) from port Y of cell spi_neuron_top.$flatten\u_graph_engine.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:430$1029 ($add).
|
|
Removed top 9 bits (of 32) from port A of cell spi_neuron_top.$flatten\u_graph_engine.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:430$1029 ($add).
|
|
Removed top 24 bits (of 32) from port B of cell spi_neuron_top.$flatten\u_graph_engine.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:430$1028 ($add).
|
|
Removed top 9 bits (of 32) from port Y of cell spi_neuron_top.$flatten\u_graph_engine.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:430$1028 ($add).
|
|
Removed top 3 bits (of 4) from port B of cell spi_neuron_top.$flatten\u_graph_engine.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:401$1025 ($add).
|
|
Removed top 31 bits (of 32) from port B of cell spi_neuron_top.$flatten\u_graph_engine.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:394$1022 ($add).
|
|
Removed top 16 bits (of 32) from port Y of cell spi_neuron_top.$flatten\u_graph_engine.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:394$1022 ($add).
|
|
Removed top 15 bits (of 16) from port B of cell spi_neuron_top.$flatten\u_graph_engine.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:350$1019 ($add).
|
|
Removed top 15 bits (of 16) from port B of cell spi_neuron_top.$flatten\u_graph_engine.$sub$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:346$1017 ($sub).
|
|
Removed top 3 bits (of 4) from port B of cell spi_neuron_top.$flatten\u_layer_sequencer.$procmux$3413_CMP0 ($eq).
|
|
Removed top 1 bits (of 4) from port B of cell spi_neuron_top.$flatten\u_layer_sequencer.$procmux$3390_CMP0 ($eq).
|
|
Removed top 1 bits (of 4) from port B of cell spi_neuron_top.$flatten\u_layer_sequencer.$procmux$3372_CMP0 ($eq).
|
|
Removed top 1 bits (of 4) from port B of cell spi_neuron_top.$flatten\u_layer_sequencer.$procmux$3352_CMP0 ($eq).
|
|
Removed top 2 bits (of 4) from port B of cell spi_neuron_top.$flatten\u_layer_sequencer.$procmux$3249_CMP0 ($eq).
|
|
Removed top 2 bits (of 4) from port B of cell spi_neuron_top.$flatten\u_layer_sequencer.$procmux$3227_CMP0 ($eq).
|
|
Removed top 1 bits (of 4) from port B of cell spi_neuron_top.$flatten\u_layer_sequencer.$procmux$3206_CMP0 ($eq).
|
|
Removed top 28 bits (of 32) from port B of cell spi_neuron_top.$flatten\u_layer_sequencer.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:317$798 ($add).
|
|
Removed top 9 bits (of 32) from port Y of cell spi_neuron_top.$flatten\u_layer_sequencer.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:317$798 ($add).
|
|
Removed top 7 bits (of 8) from port B of cell spi_neuron_top.$flatten\u_layer_sequencer.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:316$797 ($add).
|
|
Removed top 7 bits (of 8) from port B of cell spi_neuron_top.$flatten\u_layer_sequencer.$sub$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:303$794 ($sub).
|
|
Removed top 27 bits (of 32) from port B of cell spi_neuron_top.$flatten\u_layer_sequencer.$shiftx$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:291$791 ($shiftx).
|
|
Removed top 3 bits (of 4) from port B of cell spi_neuron_top.$flatten\u_layer_sequencer.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:239$783 ($add).
|
|
Removed top 2 bits (of 8) from port B of cell spi_neuron_top.$flatten\u_spi_engine.$procmux$4691_CMP0 ($eq).
|
|
Removed top 2 bits (of 8) from port B of cell spi_neuron_top.$flatten\u_spi_engine.$procmux$4683_CMP0 ($eq).
|
|
Removed top 2 bits (of 8) from port B of cell spi_neuron_top.$flatten\u_spi_engine.$procmux$4673_CMP0 ($eq).
|
|
Removed top 7 bits (of 8) from port B of cell spi_neuron_top.$flatten\u_spi_engine.$procmux$4565_CMP0 ($eq).
|
|
Removed top 6 bits (of 8) from port B of cell spi_neuron_top.$flatten\u_spi_engine.$procmux$4526_CMP0 ($eq).
|
|
Removed top 5 bits (of 8) from port B of cell spi_neuron_top.$flatten\u_spi_engine.$procmux$4488_CMP0 ($eq).
|
|
Removed top 5 bits (of 8) from port B of cell spi_neuron_top.$flatten\u_spi_engine.$procmux$4454_CMP0 ($eq).
|
|
Removed top 4 bits (of 8) from port B of cell spi_neuron_top.$flatten\u_spi_engine.$procmux$4421_CMP0 ($eq).
|
|
Removed top 6 bits (of 8) from port B of cell spi_neuron_top.$flatten\u_spi_engine.$procmux$4389_CMP0 ($eq).
|
|
Removed top 5 bits (of 8) from port B of cell spi_neuron_top.$flatten\u_spi_engine.$procmux$4352_CMP0 ($eq).
|
|
Removed top 5 bits (of 8) from port B of cell spi_neuron_top.$flatten\u_spi_engine.$procmux$4316_CMP0 ($eq).
|
|
Removed top 4 bits (of 8) from port B of cell spi_neuron_top.$flatten\u_spi_engine.$procmux$4242_CMP0 ($eq).
|
|
Removed top 4 bits (of 8) from port B of cell spi_neuron_top.$flatten\u_spi_engine.$procmux$4211_CMP0 ($eq).
|
|
Removed top 3 bits (of 8) from port B of cell spi_neuron_top.$flatten\u_spi_engine.$procmux$4185_CMP0 ($eq).
|
|
Removed top 2 bits (of 8) from port B of cell spi_neuron_top.$flatten\u_spi_engine.$procmux$4184_CMP0 ($eq).
|
|
Removed top 3 bits (of 8) from port B of cell spi_neuron_top.$flatten\u_spi_engine.$procmux$4183_CMP0 ($eq).
|
|
Removed top 6 bits (of 8) from port B of cell spi_neuron_top.$flatten\u_spi_engine.$procmux$4052_CMP1 ($eq).
|
|
Removed top 7 bits (of 8) from port B of cell spi_neuron_top.$flatten\u_spi_engine.$procmux$4052_CMP0 ($eq).
|
|
Removed top 8 bits (of 24) from mux cell spi_neuron_top.$flatten\u_spi_engine.$procmux$4037 ($pmux).
|
|
Removed top 8 bits (of 24) from mux cell spi_neuron_top.$flatten\u_spi_engine.$procmux$4035 ($mux).
|
|
Removed top 2 bits (of 8) from port B of cell spi_neuron_top.$flatten\u_spi_engine.$procmux$3883_CMP0 ($eq).
|
|
Removed top 2 bits (of 8) from port B of cell spi_neuron_top.$flatten\u_spi_engine.$procmux$3882_CMP0 ($eq).
|
|
Removed top 2 bits (of 8) from port B of cell spi_neuron_top.$flatten\u_spi_engine.$procmux$3881_CMP0 ($eq).
|
|
Removed top 4 bits (of 8) from port B of cell spi_neuron_top.$flatten\u_spi_engine.$procmux$3855_CMP0 ($eq).
|
|
Removed top 2 bits (of 8) from port B of cell spi_neuron_top.$flatten\u_spi_engine.$procmux$3747_CMP0 ($eq).
|
|
Removed top 3 bits (of 4) from port B of cell spi_neuron_top.$flatten\u_spi_engine.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:710$779 ($add).
|
|
Removed top 3 bits (of 4) from port B of cell spi_neuron_top.$flatten\u_spi_engine.$sub$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:707$777 ($sub).
|
|
Removed top 6 bits (of 8) from port B of cell spi_neuron_top.$flatten\u_spi_engine.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:674$776 ($eq).
|
|
Removed top 15 bits (of 16) from port B of cell spi_neuron_top.$flatten\u_spi_engine.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:644$774 ($eq).
|
|
Removed top 15 bits (of 16) from port B of cell spi_neuron_top.$flatten\u_spi_engine.$sub$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:642$773 ($sub).
|
|
Removed top 1 bits (of 2) from port B of cell spi_neuron_top.$flatten\u_spi_engine.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:561$768 ($add).
|
|
Removed top 7 bits (of 8) from port B of cell spi_neuron_top.$flatten\u_spi_engine.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:549$767 ($eq).
|
|
Removed top 1 bits (of 2) from port B of cell spi_neuron_top.$flatten\u_spi_engine.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:540$765 ($eq).
|
|
Removed top 3 bits (of 8) from port B of cell spi_neuron_top.$flatten\u_spi_engine.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:493$763 ($eq).
|
|
Removed top 24 bits (of 32) from port B of cell spi_neuron_top.$flatten\u_spi_engine.$shiftx$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:277$759 ($shiftx).
|
|
Removed top 31 bits (of 32) from port B of cell spi_neuron_top.$flatten\u_spi_engine.$lt$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:276$756 ($lt).
|
|
Removed top 1 bits (of 8) from mux cell spi_neuron_top.$flatten\u_spi_slave.$procmux$5199 ($mux).
|
|
Removed top 1 bits (of 8) from mux cell spi_neuron_top.$flatten\u_spi_slave.$procmux$5196 ($mux).
|
|
Removed top 1 bits (of 8) from mux cell spi_neuron_top.$flatten\u_spi_slave.$procmux$5193 ($mux).
|
|
Removed top 1 bits (of 8) from mux cell spi_neuron_top.$flatten\u_spi_slave.$procmux$5191 ($mux).
|
|
Removed top 1 bits (of 8) from mux cell spi_neuron_top.$flatten\u_spi_slave.$procmux$5188 ($mux).
|
|
Removed top 1 bits (of 8) from mux cell spi_neuron_top.$flatten\u_spi_slave.$procmux$5186 ($mux).
|
|
Removed top 2 bits (of 3) from port B of cell spi_neuron_top.$flatten\u_spi_slave.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_slave.v:173$14 ($add).
|
|
Removed top 15 bits (of 16) from FF cell spi_neuron_top.$auto$ff.cc:337:slice$7514 ($sdffe).
|
|
Removed top 7 bits (of 8) from FF cell spi_neuron_top.$auto$ff.cc:337:slice$7472 ($sdffe).
|
|
Removed cell spi_neuron_top.$auto$ff.cc:337:slice$7469 ($sdffe).
|
|
Removed top 15 bits (of 16) from FF cell spi_neuron_top.$auto$ff.cc:337:slice$6706 ($sdffe).
|
|
Removed top 1 bits (of 16) from FF cell spi_neuron_top.$auto$ff.cc:337:slice$6536 ($sdffe).
|
|
Removed top 8 bits (of 24) from mux cell spi_neuron_top.$flatten\u_spi_engine.$procmux$4053 ($mux).
|
|
Removed top 8 bits (of 24) from mux cell spi_neuron_top.$flatten\u_spi_engine.$procmux$4039 ($mux).
|
|
Removed top 1 bits (of 16) from mux cell spi_neuron_top.$flatten\u_spi_engine.$procmux$4037 ($pmux).
|
|
Removed top 1 bits (of 16) from mux cell spi_neuron_top.$flatten\u_spi_engine.$procmux$4035 ($mux).
|
|
Removed top 1 bits (of 16) from mux cell spi_neuron_top.$flatten\u_spi_engine.$procmux$4053 ($mux).
|
|
Removed top 9 bits (of 24) from mux cell spi_neuron_top.$flatten\u_spi_engine.$procmux$4051 ($mux).
|
|
Removed top 1 bits (of 16) from mux cell spi_neuron_top.$flatten\u_spi_engine.$procmux$4039 ($mux).
|
|
Removed top 1 bits (of 6) from wire spi_neuron_top.$flatten\u_neuron_memory.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:357$1114_ADDR[5:0]$1120.
|
|
Removed top 1 bits (of 6) from wire spi_neuron_top.$flatten\u_neuron_memory.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:390$1115_ADDR[5:0]$1123.
|
|
Removed top 1 bits (of 6) from wire spi_neuron_top.$flatten\u_neuron_memory.$2$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:357$1114_ADDR[5:0]$1139.
|
|
Removed top 1 bits (of 6) from wire spi_neuron_top.$flatten\u_neuron_memory.$2$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:390$1115_ADDR[5:0]$1142.
|
|
Removed top 1 bits (of 6) from wire spi_neuron_top.$flatten\u_neuron_memory.$3$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:390$1115_ADDR[5:0]$1156.
|
|
Removed top 1 bits (of 6) from wire spi_neuron_top.$flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:496$865_ADDR[5:0]$937.
|
|
Removed top 9 bits (of 24) from wire spi_neuron_top.$flatten\u_spi_engine.$procmux$4053_Y.
|
|
Removed top 9 bits (of 24) from wire spi_neuron_top.$flatten\u_spi_engine.$procmux$4051_Y.
|
|
Removed top 9 bits (of 24) from wire spi_neuron_top.$flatten\u_spi_engine.$procmux$4039_Y.
|
|
Removed top 9 bits (of 24) from wire spi_neuron_top.$flatten\u_spi_engine.$procmux$4037_Y.
|
|
Removed top 9 bits (of 24) from wire spi_neuron_top.$flatten\u_spi_engine.$procmux$4035_Y.
|
|
Removed top 1 bits (of 6) from wire spi_neuron_top.$flatten\u_graph_engine.$2$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:496$865_ADDR[5:0]$1013.
|
|
Removed top 16 bits (of 32) from wire spi_neuron_top.$flatten\u_graph_engine.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:394$1022_Y.
|
|
Removed top 9 bits (of 32) from wire spi_neuron_top.$flatten\u_graph_engine.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:430$1028_Y.
|
|
Removed top 9 bits (of 32) from wire spi_neuron_top.$flatten\u_graph_engine.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:430$1029_Y.
|
|
Removed top 9 bits (of 32) from wire spi_neuron_top.$flatten\u_graph_engine.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:533$1043_Y.
|
|
Removed top 9 bits (of 32) from wire spi_neuron_top.$flatten\u_layer_sequencer.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:317$798_Y.
|
|
Removed top 1 bits (of 8) from wire spi_neuron_top.$flatten\u_spi_slave.$procmux$5199_Y.
|
|
Removed top 1 bits (of 8) from wire spi_neuron_top.$flatten\u_spi_slave.$procmux$5196_Y.
|
|
Removed top 1 bits (of 8) from wire spi_neuron_top.$flatten\u_spi_slave.$procmux$5193_Y.
|
|
Removed top 1 bits (of 8) from wire spi_neuron_top.$flatten\u_spi_slave.$procmux$5191_Y.
|
|
Removed top 1 bits (of 8) from wire spi_neuron_top.$flatten\u_spi_slave.$procmux$5188_Y.
|
|
Removed top 1 bits (of 8) from wire spi_neuron_top.$flatten\u_spi_slave.$procmux$5186_Y.
|
|
Removed top 15 bits (of 16) from wire spi_neuron_top.n_neurons_real.
|
|
Removed top 15 bits (of 16) from wire spi_neuron_top.seq_nm_n_neurons.
|
|
Removed top 15 bits (of 16) from wire spi_neuron_top.mux_nm_n_neurons.
|
|
Removed top 1 bits (of 23) from wire spi_neuron_top.i8_mem_addr.
|
|
Removed top 1 bits (of 23) from wire spi_neuron_top.psram_mem_addr.
|
|
|
|
17.16. Executing PEEPOPT pass (run peephole optimizers).
|
|
shiftpow2 pattern in spi_neuron_top: shift=$flatten\u_graph_engine.\u_neuron.$shiftx$/tmp/before_rewrite/neuron_parallel.v:107$1322, index=\u_graph_engine.u_neuron.group_index, stride=16, width=16, ways=16
|
|
shiftpow2 pattern in spi_neuron_top: shift=$flatten\u_graph_engine.\u_neuron.$shiftx$/tmp/before_rewrite/neuron_parallel.v:101$1318, index=\u_graph_engine.u_neuron.group_index, stride=16, width=16, ways=16
|
|
shiftpow2 pattern in spi_neuron_top: shift=$flatten\u_layer_sequencer.$shiftx$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:291$791, index=\u_layer_sequencer.copy_idx, stride=8, width=8, ways=2
|
|
shiftpow2 pattern in spi_neuron_top: shift=$flatten\u_neuron_memory.\u_neuron.$shiftx$/tmp/before_rewrite/neuron_parallel.v:107$1322, index=\u_neuron_memory.u_neuron.group_index, stride=16, width=16, ways=16
|
|
shiftpow2 pattern in spi_neuron_top: shift=$flatten\u_neuron_memory.\u_neuron.$shiftx$/tmp/before_rewrite/neuron_parallel.v:101$1318, index=\u_neuron_memory.u_neuron.group_index, stride=16, width=16, ways=16
|
|
|
|
17.17. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \spi_neuron_top..
|
|
Removed 2 unused cells and 33 unused wires.
|
|
<suppressed ~3 debug messages>
|
|
|
|
17.18. Executing SHARE pass (SAT-based resource sharing).
|
|
Found 5 cells in module spi_neuron_top that may be considered for resource sharing.
|
|
Analyzing resource sharing options for $flatten\u_neuron_memory.\u_neuron.\u_mac8.\GEN_MAC[1].u_mac.$mul$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:16$1249 ($mul):
|
|
Cell is always active. Therefore no sharing is possible.
|
|
Analyzing resource sharing options for $flatten\u_neuron_memory.\u_neuron.\u_mac8.\GEN_MAC[0].u_mac.$mul$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:16$1249 ($mul):
|
|
Cell is always active. Therefore no sharing is possible.
|
|
Analyzing resource sharing options for $flatten\u_graph_engine.\u_neuron.\u_mac8.\GEN_MAC[1].u_mac.$mul$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:16$1249 ($mul):
|
|
Cell is always active. Therefore no sharing is possible.
|
|
Analyzing resource sharing options for $flatten\u_graph_engine.\u_neuron.\u_mac8.\GEN_MAC[0].u_mac.$mul$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:16$1249 ($mul):
|
|
Cell is always active. Therefore no sharing is possible.
|
|
Analyzing resource sharing options for $flatten\u_spi_engine.$auto$mem.cc:305:emit$1576 ($memrd_v2):
|
|
Found 2 activation_patterns using ctrl signal { \u_spi_slave.cs_n_sync [2] \u_spi_slave.sclk_rise \u_spi_slave.sclk_fall \u_spi_slave.cs_fell \u_spi_slave.cs_rose $flatten\u_spi_slave.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_slave.v:182$15_Y \u_spi_engine.state [5] $flatten\u_spi_engine.$procmux$4673_CMP }.
|
|
No candidates found.
|
|
|
|
17.19. Executing TECHMAP pass (map to technology primitives).
|
|
|
|
17.19.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/cmp2lut.v
|
|
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/cmp2lut.v' to AST representation.
|
|
Generating RTLIL representation for module `\_90_lut_cmp_'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
17.19.2. Continuing TECHMAP pass.
|
|
Using template $paramod$e284bc47c88f6e32a7d40296f7bdff7bac057394\_90_lut_cmp_ for cells of type $lt.
|
|
No more expansions possible.
|
|
<suppressed ~166 debug messages>
|
|
|
|
17.20. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module spi_neuron_top.
|
|
|
|
17.21. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \spi_neuron_top..
|
|
Removed 0 unused cells and 3 unused wires.
|
|
<suppressed ~1 debug messages>
|
|
|
|
17.22. Executing TECHMAP pass (map to technology primitives).
|
|
|
|
17.22.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/mul2dsp.v
|
|
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/mul2dsp.v' to AST representation.
|
|
Generating RTLIL representation for module `\_80_mul'.
|
|
Generating RTLIL representation for module `\_90_soft_mul'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
17.22.2. Continuing TECHMAP pass.
|
|
Using template $paramod$cc733e0dbb038034434917c1e0de96998ec4103f\_80_mul for cells of type $mul.
|
|
No more expansions possible.
|
|
<suppressed ~88 debug messages>
|
|
|
|
17.23. Executing TECHMAP pass (map to technology primitives).
|
|
|
|
17.23.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/dsp_map_18x18.v
|
|
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/dsp_map_18x18.v' to AST representation.
|
|
Generating RTLIL representation for module `$__MUL18X18'.
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Successfully finished Verilog frontend.
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17.23.2. Continuing TECHMAP pass.
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Using template $paramod$ea686d7c43b0ae12a4f0d39aec4e01bcc4449b23$__MUL18X18 for cells of type $__MUL18X18.
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No more expansions possible.
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<suppressed ~26 debug messages>
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17.24. Executing ALUMACC pass (create $alu and $macc cells).
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Extracting $alu and $macc cells in module spi_neuron_top:
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creating $macc model for $flatten\u_graph_engine.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:550$1044 ($add).
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creating $macc model for $flatten\u_graph_engine.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:430$1028 ($add).
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creating $macc model for $flatten\u_spi_slave.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_slave.v:173$14 ($add).
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creating $macc model for $flatten\u_graph_engine.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:401$1025 ($add).
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creating $macc model for $flatten\u_layer_sequencer.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:239$783 ($add).
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creating $macc model for $flatten\u_graph_engine.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:533$1043 ($add).
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creating $macc model for $flatten\u_graph_engine.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:394$1022 ($add).
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creating $macc model for $flatten\u_graph_engine.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:366$1020 ($add).
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creating $macc model for $flatten\u_graph_engine.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:350$1019 ($add).
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creating $macc model for $flatten\u_graph_engine.$sub$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:346$1017 ($sub).
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creating $macc model for $flatten\u_graph_engine.$sub$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:527$1040 ($sub).
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creating $macc model for $flatten\u_graph_engine.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:332$1016 ($add).
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creating $macc model for $flatten\u_graph_engine.$sub$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:177$868 ($sub).
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creating $macc model for $flatten\u_graph_engine.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:502$1039 ($add).
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creating $macc model for $flatten\u_graph_engine.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:532$1042 ($add).
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|
creating $macc model for $flatten\u_graph_engine.$sub$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:498$1037 ($sub).
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creating $macc model for $flatten\u_graph_engine.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:478$1036 ($add).
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|
creating $macc model for $flatten\u_spi_engine.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:710$779 ($add).
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creating $macc model for $flatten\u_spi_engine.$sub$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:707$777 ($sub).
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|
creating $macc model for $flatten\u_spi_engine.$sub$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:642$773 ($sub).
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creating $macc model for $flatten\u_spi_engine.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:641$772 ($add).
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creating $macc model for $flatten\u_spi_engine.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:561$768 ($add).
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creating $macc model for $flatten\u_graph_engine.\u_neuron.\u_mac8.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101$1348 ($add).
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creating $macc model for $flatten\u_graph_engine.\u_neuron.$add$/tmp/before_rewrite/neuron_parallel.v:194$1333 ($add).
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creating $macc model for $flatten\u_graph_engine.\u_neuron.$sub$/tmp/before_rewrite/neuron_parallel.v:152$1327 ($sub).
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creating $macc model for $flatten\u_graph_engine.\u_neuron.$add$/tmp/before_rewrite/neuron_parallel.v:128$1323 ($add).
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creating $macc model for $flatten\u_graph_engine.\u_neuron.\u_mac8.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:115$1342 ($add).
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creating $macc model for $flatten\u_neuron_memory.$sub$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:359$1151 ($sub).
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creating $macc model for $flatten\u_neuron_memory.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:371$1153 ($add).
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creating $macc model for $flatten\u_neuron_memory.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:373$1154 ($add).
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creating $macc model for $flatten\u_neuron_memory.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:373$1155 ($add).
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creating $macc model for $flatten\u_neuron_memory.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:404$1162 ($add).
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creating $macc model for $flatten\u_neuron_memory.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:404$1163 ($add).
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creating $macc model for $flatten\u_neuron_memory.$sub$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:451$1167 ($sub).
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creating $macc model for $flatten\u_neuron_memory.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:464$1169 ($add).
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creating $macc model for $flatten\u_neuron_memory.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:465$1170 ($add).
|
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creating $macc model for $flatten\u_neuron_memory.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:466$1171 ($add).
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creating $macc model for $flatten\u_layer_sequencer.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:290$788 ($add).
|
|
creating $macc model for $flatten\u_layer_sequencer.$sub$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:301$792 ($sub).
|
|
creating $macc model for $flatten\u_layer_sequencer.$sub$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:303$794 ($sub).
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creating $macc model for $flatten\u_layer_sequencer.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:316$797 ($add).
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creating $macc model for $flatten\u_layer_sequencer.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:317$798 ($add).
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creating $macc model for $flatten\u_layer_sequencer.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:326$799 ($add).
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|
creating $macc model for $flatten\u_neuron_memory.\u_neuron.\u_mac8.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101$1348 ($add).
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|
creating $macc model for $flatten\u_neuron_memory.\u_neuron.$add$/tmp/before_rewrite/neuron_parallel.v:194$1333 ($add).
|
|
creating $macc model for $flatten\u_neuron_memory.\u_neuron.$sub$/tmp/before_rewrite/neuron_parallel.v:152$1327 ($sub).
|
|
creating $macc model for $flatten\u_neuron_memory.\u_neuron.$add$/tmp/before_rewrite/neuron_parallel.v:128$1323 ($add).
|
|
creating $macc model for $flatten\u_neuron_memory.\u_neuron.\u_mac8.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:115$1342 ($add).
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creating $macc model for $flatten\u_graph_engine.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:430$1029 ($add).
|
|
creating $macc model for $flatten\u_psram_ctrl.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/psram_controller.v:186$1244 ($add).
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|
creating $macc model for $flatten\u_layer_sequencer.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:211$781 ($add).
|
|
creating $macc model for $flatten\u_graph_engine.$sub$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:175$866 ($sub).
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merging $macc model for $flatten\u_graph_engine.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:430$1028 into $flatten\u_graph_engine.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:430$1029.
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merging $macc model for $flatten\u_neuron_memory.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:404$1162 into $flatten\u_neuron_memory.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:404$1163.
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merging $macc model for $flatten\u_neuron_memory.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:373$1154 into $flatten\u_neuron_memory.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:373$1155.
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creating $alu model for $macc $flatten\u_neuron_memory.\u_neuron.\u_mac8.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:115$1342.
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|
creating $alu model for $macc $flatten\u_neuron_memory.\u_neuron.$add$/tmp/before_rewrite/neuron_parallel.v:128$1323.
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|
creating $alu model for $macc $flatten\u_neuron_memory.\u_neuron.$sub$/tmp/before_rewrite/neuron_parallel.v:152$1327.
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|
creating $alu model for $macc $flatten\u_neuron_memory.\u_neuron.$add$/tmp/before_rewrite/neuron_parallel.v:194$1333.
|
|
creating $alu model for $macc $flatten\u_neuron_memory.\u_neuron.\u_mac8.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101$1348.
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creating $alu model for $macc $flatten\u_layer_sequencer.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:326$799.
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|
creating $alu model for $macc $flatten\u_layer_sequencer.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:317$798.
|
|
creating $alu model for $macc $flatten\u_layer_sequencer.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:316$797.
|
|
creating $alu model for $macc $flatten\u_layer_sequencer.$sub$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:303$794.
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|
creating $alu model for $macc $flatten\u_layer_sequencer.$sub$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:301$792.
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|
creating $alu model for $macc $flatten\u_layer_sequencer.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:290$788.
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|
creating $alu model for $macc $flatten\u_neuron_memory.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:466$1171.
|
|
creating $alu model for $macc $flatten\u_neuron_memory.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:465$1170.
|
|
creating $alu model for $macc $flatten\u_neuron_memory.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:464$1169.
|
|
creating $alu model for $macc $flatten\u_neuron_memory.$sub$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:451$1167.
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|
creating $alu model for $macc $flatten\u_neuron_memory.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:404$1163.
|
|
creating $alu model for $macc $flatten\u_layer_sequencer.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:211$781.
|
|
creating $alu model for $macc $flatten\u_neuron_memory.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:373$1155.
|
|
creating $alu model for $macc $flatten\u_graph_engine.$sub$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:175$866.
|
|
creating $alu model for $macc $flatten\u_neuron_memory.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:371$1153.
|
|
creating $alu model for $macc $flatten\u_neuron_memory.$sub$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:359$1151.
|
|
creating $alu model for $macc $flatten\u_graph_engine.\u_neuron.\u_mac8.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:115$1342.
|
|
creating $alu model for $macc $flatten\u_graph_engine.\u_neuron.$add$/tmp/before_rewrite/neuron_parallel.v:128$1323.
|
|
creating $alu model for $macc $flatten\u_graph_engine.\u_neuron.$sub$/tmp/before_rewrite/neuron_parallel.v:152$1327.
|
|
creating $alu model for $macc $flatten\u_graph_engine.\u_neuron.$add$/tmp/before_rewrite/neuron_parallel.v:194$1333.
|
|
creating $alu model for $macc $flatten\u_graph_engine.\u_neuron.\u_mac8.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101$1348.
|
|
creating $alu model for $macc $flatten\u_spi_engine.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:561$768.
|
|
creating $alu model for $macc $flatten\u_spi_engine.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:641$772.
|
|
creating $alu model for $macc $flatten\u_spi_engine.$sub$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:642$773.
|
|
creating $alu model for $macc $flatten\u_spi_engine.$sub$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:707$777.
|
|
creating $alu model for $macc $flatten\u_spi_engine.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:710$779.
|
|
creating $alu model for $macc $flatten\u_graph_engine.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:478$1036.
|
|
creating $alu model for $macc $flatten\u_graph_engine.$sub$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:498$1037.
|
|
creating $alu model for $macc $flatten\u_graph_engine.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:532$1042.
|
|
creating $alu model for $macc $flatten\u_graph_engine.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:502$1039.
|
|
creating $alu model for $macc $flatten\u_graph_engine.$sub$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:177$868.
|
|
creating $alu model for $macc $flatten\u_graph_engine.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:332$1016.
|
|
creating $alu model for $macc $flatten\u_graph_engine.$sub$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:527$1040.
|
|
creating $alu model for $macc $flatten\u_graph_engine.$sub$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:346$1017.
|
|
creating $alu model for $macc $flatten\u_graph_engine.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:350$1019.
|
|
creating $alu model for $macc $flatten\u_graph_engine.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:366$1020.
|
|
creating $alu model for $macc $flatten\u_graph_engine.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:394$1022.
|
|
creating $alu model for $macc $flatten\u_graph_engine.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:533$1043.
|
|
creating $alu model for $macc $flatten\u_layer_sequencer.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:239$783.
|
|
creating $alu model for $macc $flatten\u_graph_engine.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:401$1025.
|
|
creating $alu model for $macc $flatten\u_spi_slave.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_slave.v:173$14.
|
|
creating $alu model for $macc $flatten\u_psram_ctrl.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/psram_controller.v:186$1244.
|
|
creating $alu model for $macc $flatten\u_graph_engine.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:550$1044.
|
|
creating $macc cell for $flatten\u_graph_engine.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:430$1029: $auto$alumacc.cc:399:replace_macc$7589
|
|
creating $alu model for $flatten\u_graph_engine.$ge$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:176$867 ($ge): merged with $flatten\u_graph_engine.$sub$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:177$868.
|
|
creating $alu model for $flatten\u_graph_engine.\u_neuron.$gt$/tmp/before_rewrite/neuron_parallel.v:178$1332 ($gt): new $alu
|
|
creating $alu model for $flatten\u_graph_engine.\u_neuron.$le$/tmp/before_rewrite/neuron_parallel.v:176$1331 ($le): new $alu
|
|
creating $alu model for $flatten\u_graph_engine.\u_neuron.$lt$/tmp/before_rewrite/neuron_parallel.v:165$1330 ($lt): new $alu
|
|
creating $alu model for $flatten\u_graph_engine.$ge$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:458$1034 ($ge): new $alu
|
|
creating $alu model for $flatten\u_neuron_memory.\u_neuron.$gt$/tmp/before_rewrite/neuron_parallel.v:178$1332 ($gt): new $alu
|
|
creating $alu model for $flatten\u_neuron_memory.\u_neuron.$le$/tmp/before_rewrite/neuron_parallel.v:176$1331 ($le): new $alu
|
|
creating $alu model for $flatten\u_neuron_memory.\u_neuron.$lt$/tmp/before_rewrite/neuron_parallel.v:165$1330 ($lt): new $alu
|
|
creating $alu model for $flatten\u_graph_engine.$ge$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:457$1032 ($ge): new $alu
|
|
creating $alu model for $flatten\u_graph_engine.$ge$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:456$1031 ($ge): new $alu
|
|
creating $alu model for $flatten\u_spi_engine.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:644$774 ($eq): merged with $flatten\u_spi_engine.$sub$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:642$773.
|
|
creating $alu cell for $flatten\u_graph_engine.$ge$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:456$1031: $auto$alumacc.cc:548:replace_alu$7599
|
|
creating $alu cell for $flatten\u_graph_engine.$ge$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:457$1032: $auto$alumacc.cc:548:replace_alu$7612
|
|
creating $alu cell for $flatten\u_neuron_memory.\u_neuron.$lt$/tmp/before_rewrite/neuron_parallel.v:165$1330: $auto$alumacc.cc:548:replace_alu$7625
|
|
creating $alu cell for $flatten\u_neuron_memory.\u_neuron.$le$/tmp/before_rewrite/neuron_parallel.v:176$1331: $auto$alumacc.cc:548:replace_alu$7632
|
|
creating $alu cell for $flatten\u_neuron_memory.\u_neuron.$gt$/tmp/before_rewrite/neuron_parallel.v:178$1332: $auto$alumacc.cc:548:replace_alu$7643
|
|
creating $alu cell for $flatten\u_graph_engine.$ge$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:458$1034: $auto$alumacc.cc:548:replace_alu$7656
|
|
creating $alu cell for $flatten\u_graph_engine.\u_neuron.$lt$/tmp/before_rewrite/neuron_parallel.v:165$1330: $auto$alumacc.cc:548:replace_alu$7669
|
|
creating $alu cell for $flatten\u_graph_engine.\u_neuron.$le$/tmp/before_rewrite/neuron_parallel.v:176$1331: $auto$alumacc.cc:548:replace_alu$7676
|
|
creating $alu cell for $flatten\u_graph_engine.\u_neuron.$gt$/tmp/before_rewrite/neuron_parallel.v:178$1332: $auto$alumacc.cc:548:replace_alu$7687
|
|
creating $alu cell for $flatten\u_graph_engine.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:550$1044: $auto$alumacc.cc:548:replace_alu$7700
|
|
creating $alu cell for $flatten\u_psram_ctrl.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/psram_controller.v:186$1244: $auto$alumacc.cc:548:replace_alu$7703
|
|
creating $alu cell for $flatten\u_spi_slave.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_slave.v:173$14: $auto$alumacc.cc:548:replace_alu$7706
|
|
creating $alu cell for $flatten\u_graph_engine.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:401$1025: $auto$alumacc.cc:548:replace_alu$7709
|
|
creating $alu cell for $flatten\u_layer_sequencer.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:239$783: $auto$alumacc.cc:548:replace_alu$7712
|
|
creating $alu cell for $flatten\u_graph_engine.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:533$1043: $auto$alumacc.cc:548:replace_alu$7715
|
|
creating $alu cell for $flatten\u_graph_engine.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:394$1022: $auto$alumacc.cc:548:replace_alu$7718
|
|
creating $alu cell for $flatten\u_graph_engine.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:366$1020: $auto$alumacc.cc:548:replace_alu$7721
|
|
creating $alu cell for $flatten\u_graph_engine.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:350$1019: $auto$alumacc.cc:548:replace_alu$7724
|
|
creating $alu cell for $flatten\u_graph_engine.$sub$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:346$1017: $auto$alumacc.cc:548:replace_alu$7727
|
|
creating $alu cell for $flatten\u_graph_engine.$sub$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:527$1040: $auto$alumacc.cc:548:replace_alu$7730
|
|
creating $alu cell for $flatten\u_graph_engine.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:332$1016: $auto$alumacc.cc:548:replace_alu$7733
|
|
creating $alu cell for $flatten\u_graph_engine.$sub$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:177$868, $flatten\u_graph_engine.$ge$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:176$867: $auto$alumacc.cc:548:replace_alu$7736
|
|
creating $alu cell for $flatten\u_graph_engine.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:502$1039: $auto$alumacc.cc:548:replace_alu$7749
|
|
creating $alu cell for $flatten\u_graph_engine.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:532$1042: $auto$alumacc.cc:548:replace_alu$7752
|
|
creating $alu cell for $flatten\u_graph_engine.$sub$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:498$1037: $auto$alumacc.cc:548:replace_alu$7755
|
|
creating $alu cell for $flatten\u_graph_engine.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:478$1036: $auto$alumacc.cc:548:replace_alu$7758
|
|
creating $alu cell for $flatten\u_spi_engine.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:710$779: $auto$alumacc.cc:548:replace_alu$7761
|
|
creating $alu cell for $flatten\u_spi_engine.$sub$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:707$777: $auto$alumacc.cc:548:replace_alu$7764
|
|
creating $alu cell for $flatten\u_spi_engine.$sub$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:642$773, $flatten\u_spi_engine.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:644$774: $auto$alumacc.cc:548:replace_alu$7767
|
|
creating $alu cell for $flatten\u_spi_engine.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:641$772: $auto$alumacc.cc:548:replace_alu$7772
|
|
creating $alu cell for $flatten\u_spi_engine.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:561$768: $auto$alumacc.cc:548:replace_alu$7775
|
|
creating $alu cell for $flatten\u_graph_engine.\u_neuron.\u_mac8.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101$1348: $auto$alumacc.cc:548:replace_alu$7778
|
|
creating $alu cell for $flatten\u_graph_engine.\u_neuron.$add$/tmp/before_rewrite/neuron_parallel.v:194$1333: $auto$alumacc.cc:548:replace_alu$7781
|
|
creating $alu cell for $flatten\u_graph_engine.\u_neuron.$sub$/tmp/before_rewrite/neuron_parallel.v:152$1327: $auto$alumacc.cc:548:replace_alu$7784
|
|
creating $alu cell for $flatten\u_graph_engine.\u_neuron.$add$/tmp/before_rewrite/neuron_parallel.v:128$1323: $auto$alumacc.cc:548:replace_alu$7787
|
|
creating $alu cell for $flatten\u_graph_engine.\u_neuron.\u_mac8.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:115$1342: $auto$alumacc.cc:548:replace_alu$7790
|
|
creating $alu cell for $flatten\u_neuron_memory.$sub$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:359$1151: $auto$alumacc.cc:548:replace_alu$7793
|
|
creating $alu cell for $flatten\u_neuron_memory.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:371$1153: $auto$alumacc.cc:548:replace_alu$7796
|
|
creating $alu cell for $flatten\u_graph_engine.$sub$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:175$866: $auto$alumacc.cc:548:replace_alu$7799
|
|
creating $alu cell for $flatten\u_neuron_memory.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:373$1155: $auto$alumacc.cc:548:replace_alu$7802
|
|
creating $alu cell for $flatten\u_layer_sequencer.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:211$781: $auto$alumacc.cc:548:replace_alu$7805
|
|
creating $alu cell for $flatten\u_neuron_memory.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:404$1163: $auto$alumacc.cc:548:replace_alu$7808
|
|
creating $alu cell for $flatten\u_neuron_memory.$sub$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:451$1167: $auto$alumacc.cc:548:replace_alu$7811
|
|
creating $alu cell for $flatten\u_neuron_memory.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:464$1169: $auto$alumacc.cc:548:replace_alu$7814
|
|
creating $alu cell for $flatten\u_neuron_memory.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:465$1170: $auto$alumacc.cc:548:replace_alu$7817
|
|
creating $alu cell for $flatten\u_neuron_memory.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:466$1171: $auto$alumacc.cc:548:replace_alu$7820
|
|
creating $alu cell for $flatten\u_layer_sequencer.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:290$788: $auto$alumacc.cc:548:replace_alu$7823
|
|
creating $alu cell for $flatten\u_layer_sequencer.$sub$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:301$792: $auto$alumacc.cc:548:replace_alu$7826
|
|
creating $alu cell for $flatten\u_layer_sequencer.$sub$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:303$794: $auto$alumacc.cc:548:replace_alu$7829
|
|
creating $alu cell for $flatten\u_layer_sequencer.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:316$797: $auto$alumacc.cc:548:replace_alu$7832
|
|
creating $alu cell for $flatten\u_layer_sequencer.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:317$798: $auto$alumacc.cc:548:replace_alu$7835
|
|
creating $alu cell for $flatten\u_layer_sequencer.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:326$799: $auto$alumacc.cc:548:replace_alu$7838
|
|
creating $alu cell for $flatten\u_neuron_memory.\u_neuron.\u_mac8.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101$1348: $auto$alumacc.cc:548:replace_alu$7841
|
|
creating $alu cell for $flatten\u_neuron_memory.\u_neuron.$add$/tmp/before_rewrite/neuron_parallel.v:194$1333: $auto$alumacc.cc:548:replace_alu$7844
|
|
creating $alu cell for $flatten\u_neuron_memory.\u_neuron.$sub$/tmp/before_rewrite/neuron_parallel.v:152$1327: $auto$alumacc.cc:548:replace_alu$7847
|
|
creating $alu cell for $flatten\u_neuron_memory.\u_neuron.$add$/tmp/before_rewrite/neuron_parallel.v:128$1323: $auto$alumacc.cc:548:replace_alu$7850
|
|
creating $alu cell for $flatten\u_neuron_memory.\u_neuron.\u_mac8.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:115$1342: $auto$alumacc.cc:548:replace_alu$7853
|
|
created 57 $alu and 1 $macc cells.
|
|
|
|
17.25. Executing OPT pass (performing simple optimizations).
|
|
|
|
17.25.1. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module spi_neuron_top.
|
|
<suppressed ~10 debug messages>
|
|
|
|
17.25.2. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\spi_neuron_top'.
|
|
Computing hashes of 1496 cells of `\spi_neuron_top'.
|
|
Finding duplicate cells in `\spi_neuron_top'.
|
|
Removed a total of 0 cells.
|
|
|
|
17.25.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \spi_neuron_top..
|
|
Creating internal representation of mux trees.
|
|
Evaluating internal representation of mux trees.
|
|
Analyzing evaluation results.
|
|
Removed 0 multiplexer ports.
|
|
<suppressed ~546 debug messages>
|
|
|
|
17.25.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \spi_neuron_top.
|
|
Optimizing cells in module \spi_neuron_top.
|
|
Performed a total of 1 changes.
|
|
|
|
17.25.5. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\spi_neuron_top'.
|
|
Computing hashes of 1496 cells of `\spi_neuron_top'.
|
|
Finding duplicate cells in `\spi_neuron_top'.
|
|
Removed a total of 0 cells.
|
|
|
|
17.25.6. Executing OPT_DFF pass (perform DFF optimizations).
|
|
|
|
17.25.7. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \spi_neuron_top..
|
|
Removed 5 unused cells and 58 unused wires.
|
|
<suppressed ~8 debug messages>
|
|
|
|
17.25.8. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module spi_neuron_top.
|
|
|
|
17.25.9. Rerunning OPT passes. (Maybe there is more to do..)
|
|
|
|
17.25.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \spi_neuron_top..
|
|
Creating internal representation of mux trees.
|
|
Evaluating internal representation of mux trees.
|
|
Analyzing evaluation results.
|
|
Removed 0 multiplexer ports.
|
|
<suppressed ~548 debug messages>
|
|
|
|
17.25.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \spi_neuron_top.
|
|
Performed a total of 0 changes.
|
|
|
|
17.25.12. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\spi_neuron_top'.
|
|
Computing hashes of 1489 cells of `\spi_neuron_top'.
|
|
Finding duplicate cells in `\spi_neuron_top'.
|
|
Removed a total of 0 cells.
|
|
|
|
17.25.13. Executing OPT_DFF pass (perform DFF optimizations).
|
|
|
|
17.25.14. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \spi_neuron_top..
|
|
|
|
17.25.15. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module spi_neuron_top.
|
|
|
|
17.25.16. Finished fast OPT passes. (There is nothing left to do.)
|
|
|
|
17.26. Executing MEMORY pass.
|
|
|
|
17.26.1. Executing OPT_MEM pass (optimize memories).
|
|
spi_neuron_top.$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1575: removing const-0 lane 6
|
|
spi_neuron_top.$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1575: removing const-0 lane 7
|
|
Performed a total of 1 transformations.
|
|
|
|
17.26.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations).
|
|
Performed a total of 992 transformations.
|
|
|
|
17.26.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths).
|
|
Analyzing spi_neuron_top.u_graph_engine.x_mem write port 0.
|
|
Analyzing spi_neuron_top.u_graph_engine.x_mem write port 1.
|
|
Analyzing spi_neuron_top.u_graph_engine.x_mem write port 2.
|
|
Analyzing spi_neuron_top.u_graph_engine.x_mem write port 3.
|
|
Analyzing spi_neuron_top.u_graph_engine.x_mem write port 4.
|
|
Analyzing spi_neuron_top.u_graph_engine.x_mem write port 5.
|
|
Analyzing spi_neuron_top.u_graph_engine.x_mem write port 6.
|
|
Analyzing spi_neuron_top.u_graph_engine.x_mem write port 7.
|
|
Analyzing spi_neuron_top.u_graph_engine.x_mem write port 8.
|
|
Analyzing spi_neuron_top.u_graph_engine.x_mem write port 9.
|
|
Analyzing spi_neuron_top.u_graph_engine.x_mem write port 10.
|
|
Analyzing spi_neuron_top.u_graph_engine.x_mem write port 11.
|
|
Analyzing spi_neuron_top.u_graph_engine.x_mem write port 12.
|
|
Analyzing spi_neuron_top.u_graph_engine.x_mem write port 13.
|
|
Analyzing spi_neuron_top.u_graph_engine.x_mem write port 14.
|
|
Analyzing spi_neuron_top.u_graph_engine.x_mem write port 15.
|
|
Analyzing spi_neuron_top.u_graph_engine.x_mem write port 16.
|
|
Analyzing spi_neuron_top.u_graph_engine.x_mem write port 17.
|
|
Analyzing spi_neuron_top.u_graph_engine.x_mem write port 18.
|
|
Analyzing spi_neuron_top.u_graph_engine.x_mem write port 19.
|
|
Analyzing spi_neuron_top.u_graph_engine.x_mem write port 20.
|
|
Analyzing spi_neuron_top.u_graph_engine.x_mem write port 21.
|
|
Analyzing spi_neuron_top.u_graph_engine.x_mem write port 22.
|
|
Analyzing spi_neuron_top.u_graph_engine.x_mem write port 23.
|
|
Analyzing spi_neuron_top.u_graph_engine.x_mem write port 24.
|
|
Analyzing spi_neuron_top.u_graph_engine.x_mem write port 25.
|
|
Analyzing spi_neuron_top.u_graph_engine.x_mem write port 26.
|
|
Analyzing spi_neuron_top.u_graph_engine.x_mem write port 27.
|
|
Analyzing spi_neuron_top.u_graph_engine.x_mem write port 28.
|
|
Analyzing spi_neuron_top.u_graph_engine.x_mem write port 29.
|
|
Analyzing spi_neuron_top.u_graph_engine.x_mem write port 30.
|
|
Analyzing spi_neuron_top.u_graph_engine.x_mem write port 31.
|
|
Analyzing spi_neuron_top.u_graph_engine.x_mem write port 32.
|
|
Analyzing spi_neuron_top.u_graph_engine.w_mem write port 0.
|
|
Analyzing spi_neuron_top.u_graph_engine.w_mem write port 1.
|
|
Analyzing spi_neuron_top.u_graph_engine.w_mem write port 2.
|
|
Analyzing spi_neuron_top.u_graph_engine.w_mem write port 3.
|
|
Analyzing spi_neuron_top.u_graph_engine.w_mem write port 4.
|
|
Analyzing spi_neuron_top.u_graph_engine.w_mem write port 5.
|
|
Analyzing spi_neuron_top.u_graph_engine.w_mem write port 6.
|
|
Analyzing spi_neuron_top.u_graph_engine.w_mem write port 7.
|
|
Analyzing spi_neuron_top.u_graph_engine.w_mem write port 8.
|
|
Analyzing spi_neuron_top.u_graph_engine.w_mem write port 9.
|
|
Analyzing spi_neuron_top.u_graph_engine.w_mem write port 10.
|
|
Analyzing spi_neuron_top.u_graph_engine.w_mem write port 11.
|
|
Analyzing spi_neuron_top.u_graph_engine.w_mem write port 12.
|
|
Analyzing spi_neuron_top.u_graph_engine.w_mem write port 13.
|
|
Analyzing spi_neuron_top.u_graph_engine.w_mem write port 14.
|
|
Analyzing spi_neuron_top.u_graph_engine.w_mem write port 15.
|
|
Analyzing spi_neuron_top.u_graph_engine.w_mem write port 16.
|
|
Analyzing spi_neuron_top.u_graph_engine.w_mem write port 17.
|
|
Analyzing spi_neuron_top.u_graph_engine.w_mem write port 18.
|
|
Analyzing spi_neuron_top.u_graph_engine.w_mem write port 19.
|
|
Analyzing spi_neuron_top.u_graph_engine.w_mem write port 20.
|
|
Analyzing spi_neuron_top.u_graph_engine.w_mem write port 21.
|
|
Analyzing spi_neuron_top.u_graph_engine.w_mem write port 22.
|
|
Analyzing spi_neuron_top.u_graph_engine.w_mem write port 23.
|
|
Analyzing spi_neuron_top.u_graph_engine.w_mem write port 24.
|
|
Analyzing spi_neuron_top.u_graph_engine.w_mem write port 25.
|
|
Analyzing spi_neuron_top.u_graph_engine.w_mem write port 26.
|
|
Analyzing spi_neuron_top.u_graph_engine.w_mem write port 27.
|
|
Analyzing spi_neuron_top.u_graph_engine.w_mem write port 28.
|
|
Analyzing spi_neuron_top.u_graph_engine.w_mem write port 29.
|
|
Analyzing spi_neuron_top.u_graph_engine.w_mem write port 30.
|
|
Analyzing spi_neuron_top.u_graph_engine.w_mem write port 31.
|
|
Analyzing spi_neuron_top.u_graph_engine.w_mem write port 32.
|
|
Analyzing spi_neuron_top.u_graph_engine.u_act_buffer.mem write port 0.
|
|
Analyzing spi_neuron_top.u_neuron_memory.y_reg write port 0.
|
|
Analyzing spi_neuron_top.u_neuron_memory.y_reg write port 1.
|
|
Analyzing spi_neuron_top.u_neuron_memory.x_mem write port 0.
|
|
Analyzing spi_neuron_top.u_neuron_memory.w_mem write port 0.
|
|
|
|
17.26.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs).
|
|
|
|
17.26.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd).
|
|
Checking read port `$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1575'[0] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_graph_engine.x_mem'[0] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_graph_engine.x_mem'[1] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_graph_engine.x_mem'[2] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_graph_engine.x_mem'[3] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_graph_engine.x_mem'[4] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_graph_engine.x_mem'[5] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_graph_engine.x_mem'[6] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_graph_engine.x_mem'[7] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_graph_engine.x_mem'[8] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_graph_engine.x_mem'[9] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_graph_engine.x_mem'[10] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_graph_engine.x_mem'[11] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_graph_engine.x_mem'[12] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_graph_engine.x_mem'[13] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_graph_engine.x_mem'[14] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_graph_engine.x_mem'[15] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_graph_engine.x_mem'[16] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_graph_engine.x_mem'[17] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_graph_engine.x_mem'[18] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_graph_engine.x_mem'[19] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_graph_engine.x_mem'[20] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_graph_engine.x_mem'[21] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_graph_engine.x_mem'[22] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_graph_engine.x_mem'[23] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_graph_engine.x_mem'[24] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_graph_engine.x_mem'[25] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_graph_engine.x_mem'[26] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_graph_engine.x_mem'[27] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_graph_engine.x_mem'[28] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_graph_engine.x_mem'[29] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_graph_engine.x_mem'[30] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_graph_engine.x_mem'[31] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_graph_engine.w_mem'[0] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_graph_engine.w_mem'[1] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_graph_engine.w_mem'[2] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_graph_engine.w_mem'[3] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_graph_engine.w_mem'[4] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_graph_engine.w_mem'[5] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_graph_engine.w_mem'[6] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_graph_engine.w_mem'[7] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_graph_engine.w_mem'[8] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_graph_engine.w_mem'[9] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_graph_engine.w_mem'[10] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_graph_engine.w_mem'[11] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_graph_engine.w_mem'[12] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_graph_engine.w_mem'[13] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_graph_engine.w_mem'[14] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_graph_engine.w_mem'[15] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_graph_engine.w_mem'[16] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_graph_engine.w_mem'[17] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_graph_engine.w_mem'[18] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_graph_engine.w_mem'[19] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_graph_engine.w_mem'[20] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_graph_engine.w_mem'[21] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_graph_engine.w_mem'[22] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_graph_engine.w_mem'[23] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_graph_engine.w_mem'[24] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_graph_engine.w_mem'[25] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_graph_engine.w_mem'[26] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_graph_engine.w_mem'[27] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_graph_engine.w_mem'[28] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_graph_engine.w_mem'[29] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_graph_engine.w_mem'[30] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_graph_engine.w_mem'[31] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_graph_engine.u_act_buffer.mem'[0] in module `\spi_neuron_top': merging output FF to cell.
|
|
Write port 0: non-transparent.
|
|
Checking read port `\u_neuron_memory.y_reg'[0] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_neuron_memory.x_mem'[0] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_neuron_memory.x_mem'[1] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_neuron_memory.x_mem'[2] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_neuron_memory.x_mem'[3] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_neuron_memory.x_mem'[4] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_neuron_memory.x_mem'[5] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_neuron_memory.x_mem'[6] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_neuron_memory.x_mem'[7] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_neuron_memory.x_mem'[8] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_neuron_memory.x_mem'[9] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_neuron_memory.x_mem'[10] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_neuron_memory.x_mem'[11] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_neuron_memory.x_mem'[12] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_neuron_memory.x_mem'[13] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_neuron_memory.x_mem'[14] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_neuron_memory.x_mem'[15] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_neuron_memory.x_mem'[16] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_neuron_memory.x_mem'[17] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_neuron_memory.x_mem'[18] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_neuron_memory.x_mem'[19] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_neuron_memory.x_mem'[20] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_neuron_memory.x_mem'[21] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_neuron_memory.x_mem'[22] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_neuron_memory.x_mem'[23] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_neuron_memory.x_mem'[24] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_neuron_memory.x_mem'[25] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_neuron_memory.x_mem'[26] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_neuron_memory.x_mem'[27] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_neuron_memory.x_mem'[28] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_neuron_memory.x_mem'[29] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_neuron_memory.x_mem'[30] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_neuron_memory.x_mem'[31] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_neuron_memory.w_mem'[0] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_neuron_memory.w_mem'[1] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_neuron_memory.w_mem'[2] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_neuron_memory.w_mem'[3] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_neuron_memory.w_mem'[4] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_neuron_memory.w_mem'[5] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_neuron_memory.w_mem'[6] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_neuron_memory.w_mem'[7] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_neuron_memory.w_mem'[8] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_neuron_memory.w_mem'[9] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_neuron_memory.w_mem'[10] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_neuron_memory.w_mem'[11] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_neuron_memory.w_mem'[12] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_neuron_memory.w_mem'[13] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_neuron_memory.w_mem'[14] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_neuron_memory.w_mem'[15] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_neuron_memory.w_mem'[16] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_neuron_memory.w_mem'[17] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_neuron_memory.w_mem'[18] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_neuron_memory.w_mem'[19] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_neuron_memory.w_mem'[20] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_neuron_memory.w_mem'[21] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_neuron_memory.w_mem'[22] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_neuron_memory.w_mem'[23] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_neuron_memory.w_mem'[24] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_neuron_memory.w_mem'[25] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_neuron_memory.w_mem'[26] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_neuron_memory.w_mem'[27] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_neuron_memory.w_mem'[28] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_neuron_memory.w_mem'[29] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_neuron_memory.w_mem'[30] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_neuron_memory.w_mem'[31] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port address `$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1575'[0] in module `\spi_neuron_top': merged address FF to cell.
|
|
Checking read port address `\u_graph_engine.x_mem'[0] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_graph_engine.x_mem'[1] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_graph_engine.x_mem'[2] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_graph_engine.x_mem'[3] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_graph_engine.x_mem'[4] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_graph_engine.x_mem'[5] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_graph_engine.x_mem'[6] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_graph_engine.x_mem'[7] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_graph_engine.x_mem'[8] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_graph_engine.x_mem'[9] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_graph_engine.x_mem'[10] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_graph_engine.x_mem'[11] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_graph_engine.x_mem'[12] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_graph_engine.x_mem'[13] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_graph_engine.x_mem'[14] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_graph_engine.x_mem'[15] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_graph_engine.x_mem'[16] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_graph_engine.x_mem'[17] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_graph_engine.x_mem'[18] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_graph_engine.x_mem'[19] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_graph_engine.x_mem'[20] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_graph_engine.x_mem'[21] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_graph_engine.x_mem'[22] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_graph_engine.x_mem'[23] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_graph_engine.x_mem'[24] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_graph_engine.x_mem'[25] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_graph_engine.x_mem'[26] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_graph_engine.x_mem'[27] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_graph_engine.x_mem'[28] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_graph_engine.x_mem'[29] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_graph_engine.x_mem'[30] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_graph_engine.x_mem'[31] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_graph_engine.w_mem'[0] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_graph_engine.w_mem'[1] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_graph_engine.w_mem'[2] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_graph_engine.w_mem'[3] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_graph_engine.w_mem'[4] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_graph_engine.w_mem'[5] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_graph_engine.w_mem'[6] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_graph_engine.w_mem'[7] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_graph_engine.w_mem'[8] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_graph_engine.w_mem'[9] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_graph_engine.w_mem'[10] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_graph_engine.w_mem'[11] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_graph_engine.w_mem'[12] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_graph_engine.w_mem'[13] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_graph_engine.w_mem'[14] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_graph_engine.w_mem'[15] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_graph_engine.w_mem'[16] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_graph_engine.w_mem'[17] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_graph_engine.w_mem'[18] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_graph_engine.w_mem'[19] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_graph_engine.w_mem'[20] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_graph_engine.w_mem'[21] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_graph_engine.w_mem'[22] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_graph_engine.w_mem'[23] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_graph_engine.w_mem'[24] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_graph_engine.w_mem'[25] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_graph_engine.w_mem'[26] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_graph_engine.w_mem'[27] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_graph_engine.w_mem'[28] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_graph_engine.w_mem'[29] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_graph_engine.w_mem'[30] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_graph_engine.w_mem'[31] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_neuron_memory.y_reg'[0] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_neuron_memory.x_mem'[0] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_neuron_memory.x_mem'[1] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_neuron_memory.x_mem'[2] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_neuron_memory.x_mem'[3] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_neuron_memory.x_mem'[4] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_neuron_memory.x_mem'[5] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_neuron_memory.x_mem'[6] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_neuron_memory.x_mem'[7] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_neuron_memory.x_mem'[8] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_neuron_memory.x_mem'[9] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_neuron_memory.x_mem'[10] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_neuron_memory.x_mem'[11] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_neuron_memory.x_mem'[12] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_neuron_memory.x_mem'[13] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_neuron_memory.x_mem'[14] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_neuron_memory.x_mem'[15] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_neuron_memory.x_mem'[16] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_neuron_memory.x_mem'[17] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_neuron_memory.x_mem'[18] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_neuron_memory.x_mem'[19] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_neuron_memory.x_mem'[20] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_neuron_memory.x_mem'[21] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_neuron_memory.x_mem'[22] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_neuron_memory.x_mem'[23] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_neuron_memory.x_mem'[24] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_neuron_memory.x_mem'[25] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_neuron_memory.x_mem'[26] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_neuron_memory.x_mem'[27] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_neuron_memory.x_mem'[28] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_neuron_memory.x_mem'[29] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_neuron_memory.x_mem'[30] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_neuron_memory.x_mem'[31] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_neuron_memory.w_mem'[0] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_neuron_memory.w_mem'[1] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_neuron_memory.w_mem'[2] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_neuron_memory.w_mem'[3] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_neuron_memory.w_mem'[4] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_neuron_memory.w_mem'[5] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_neuron_memory.w_mem'[6] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_neuron_memory.w_mem'[7] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_neuron_memory.w_mem'[8] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_neuron_memory.w_mem'[9] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_neuron_memory.w_mem'[10] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_neuron_memory.w_mem'[11] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_neuron_memory.w_mem'[12] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_neuron_memory.w_mem'[13] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_neuron_memory.w_mem'[14] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_neuron_memory.w_mem'[15] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_neuron_memory.w_mem'[16] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_neuron_memory.w_mem'[17] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_neuron_memory.w_mem'[18] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_neuron_memory.w_mem'[19] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_neuron_memory.w_mem'[20] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_neuron_memory.w_mem'[21] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_neuron_memory.w_mem'[22] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_neuron_memory.w_mem'[23] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_neuron_memory.w_mem'[24] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_neuron_memory.w_mem'[25] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_neuron_memory.w_mem'[26] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_neuron_memory.w_mem'[27] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_neuron_memory.w_mem'[28] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_neuron_memory.w_mem'[29] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_neuron_memory.w_mem'[30] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_neuron_memory.w_mem'[31] in module `\spi_neuron_top': no address FF found.
|
|
|
|
17.26.6. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \spi_neuron_top..
|
|
Removed 1 unused cells and 9 unused wires.
|
|
<suppressed ~2 debug messages>
|
|
|
|
17.26.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells).
|
|
Consolidating read ports of memory spi_neuron_top.u_graph_engine.x_mem by address:
|
|
Merging ports 0, 1 (address 5'11111).
|
|
Merging ports 0, 2 (address 5'11110).
|
|
Merging ports 0, 3 (address 5'11100).
|
|
Merging ports 0, 4 (address 5'11100).
|
|
Merging ports 0, 5 (address 5'11000).
|
|
Merging ports 0, 6 (address 5'11000).
|
|
Merging ports 0, 7 (address 5'11000).
|
|
Merging ports 0, 8 (address 5'11000).
|
|
Merging ports 0, 9 (address 5'10000).
|
|
Merging ports 0, 10 (address 5'10000).
|
|
Merging ports 0, 11 (address 5'10000).
|
|
Merging ports 0, 12 (address 5'10000).
|
|
Merging ports 0, 13 (address 5'10000).
|
|
Merging ports 0, 14 (address 5'10000).
|
|
Merging ports 0, 15 (address 5'10000).
|
|
Merging ports 0, 16 (address 5'10000).
|
|
Merging ports 18, 19 (address 5'01101).
|
|
Merging ports 20, 21 (address 5'01011).
|
|
Merging ports 20, 22 (address 5'01010).
|
|
Merging ports 20, 23 (address 5'01000).
|
|
Merging ports 24, 25 (address 5'00111).
|
|
Merging ports 24, 26 (address 5'00110).
|
|
Merging ports 24, 27 (address 5'00100).
|
|
Merging ports 24, 28 (address 5'00100).
|
|
Merging ports 24, 29 (address 5'00000).
|
|
Merging ports 24, 30 (address 5'00000).
|
|
Merging ports 24, 31 (address 5'00000).
|
|
Consolidating read ports of memory spi_neuron_top.u_graph_engine.x_mem by address:
|
|
Merging ports 1, 2 (address 5'01110).
|
|
Merging ports 1, 3 (address 5'01100).
|
|
Merging ports 1, 4 (address 5'01000).
|
|
Consolidating read ports of memory spi_neuron_top.u_graph_engine.x_mem by address:
|
|
Consolidating write ports of memory spi_neuron_top.u_graph_engine.x_mem by address:
|
|
Merging ports 0, 1 (address 5'00000).
|
|
Merging ports 0, 2 (address 5'00000).
|
|
Merging ports 0, 3 (address 5'00000).
|
|
Merging ports 0, 4 (address 5'00000).
|
|
Merging ports 0, 5 (address 5'00000).
|
|
Merging ports 0, 6 (address 5'00000).
|
|
Merging ports 0, 7 (address 5'00000).
|
|
Merging ports 0, 8 (address 5'00000).
|
|
Merging ports 0, 9 (address 5'00000).
|
|
Merging ports 0, 10 (address 5'00000).
|
|
Merging ports 0, 11 (address 5'00000).
|
|
Merging ports 0, 12 (address 5'00000).
|
|
Merging ports 0, 13 (address 5'00000).
|
|
Merging ports 0, 14 (address 5'00000).
|
|
Merging ports 0, 15 (address 5'00000).
|
|
Merging ports 0, 16 (address 5'00000).
|
|
Merging ports 18, 19 (address 5'10010).
|
|
Merging ports 20, 21 (address 5'10100).
|
|
Merging ports 20, 22 (address 5'10100).
|
|
Merging ports 20, 23 (address 5'10100).
|
|
Merging ports 24, 25 (address 5'11000).
|
|
Merging ports 24, 26 (address 5'11000).
|
|
Merging ports 24, 27 (address 5'11000).
|
|
Merging ports 24, 28 (address 5'11000).
|
|
Merging ports 24, 29 (address 5'11000).
|
|
Merging ports 24, 30 (address 5'11000).
|
|
Merging ports 24, 31 (address 5'11000).
|
|
Consolidating write ports of memory spi_neuron_top.u_graph_engine.x_mem by address:
|
|
Merging ports 1, 2 (address 5'10001).
|
|
Merging ports 1, 3 (address 5'10000).
|
|
Merging ports 1, 4 (address 5'10000).
|
|
Consolidating write ports of memory spi_neuron_top.u_graph_engine.x_mem by address:
|
|
Consolidating read ports of memory spi_neuron_top.u_graph_engine.w_mem by address:
|
|
Merging ports 0, 1 (address 5'11111).
|
|
Merging ports 0, 2 (address 5'11110).
|
|
Merging ports 0, 3 (address 5'11100).
|
|
Merging ports 0, 4 (address 5'11100).
|
|
Merging ports 0, 5 (address 5'11000).
|
|
Merging ports 0, 6 (address 5'11000).
|
|
Merging ports 0, 7 (address 5'11000).
|
|
Merging ports 0, 8 (address 5'11000).
|
|
Merging ports 0, 9 (address 5'10000).
|
|
Merging ports 0, 10 (address 5'10000).
|
|
Merging ports 0, 11 (address 5'10000).
|
|
Merging ports 0, 12 (address 5'10000).
|
|
Merging ports 0, 13 (address 5'10000).
|
|
Merging ports 0, 14 (address 5'10000).
|
|
Merging ports 0, 15 (address 5'10000).
|
|
Merging ports 0, 16 (address 5'10000).
|
|
Merging ports 18, 19 (address 5'01101).
|
|
Merging ports 20, 21 (address 5'01011).
|
|
Merging ports 20, 22 (address 5'01010).
|
|
Merging ports 20, 23 (address 5'01000).
|
|
Merging ports 24, 25 (address 5'00111).
|
|
Merging ports 24, 26 (address 5'00110).
|
|
Merging ports 24, 27 (address 5'00100).
|
|
Merging ports 24, 28 (address 5'00100).
|
|
Merging ports 24, 29 (address 5'00000).
|
|
Merging ports 24, 30 (address 5'00000).
|
|
Merging ports 24, 31 (address 5'00000).
|
|
Consolidating read ports of memory spi_neuron_top.u_graph_engine.w_mem by address:
|
|
Merging ports 1, 2 (address 5'01110).
|
|
Merging ports 1, 3 (address 5'01100).
|
|
Merging ports 1, 4 (address 5'01000).
|
|
Consolidating read ports of memory spi_neuron_top.u_graph_engine.w_mem by address:
|
|
Consolidating write ports of memory spi_neuron_top.u_graph_engine.w_mem by address:
|
|
Merging ports 0, 1 (address 5'00000).
|
|
Merging ports 0, 2 (address 5'00000).
|
|
Merging ports 0, 3 (address 5'00000).
|
|
Merging ports 0, 4 (address 5'00000).
|
|
Merging ports 0, 5 (address 5'00000).
|
|
Merging ports 0, 6 (address 5'00000).
|
|
Merging ports 0, 7 (address 5'00000).
|
|
Merging ports 0, 8 (address 5'00000).
|
|
Merging ports 0, 9 (address 5'00000).
|
|
Merging ports 0, 10 (address 5'00000).
|
|
Merging ports 0, 11 (address 5'00000).
|
|
Merging ports 0, 12 (address 5'00000).
|
|
Merging ports 0, 13 (address 5'00000).
|
|
Merging ports 0, 14 (address 5'00000).
|
|
Merging ports 0, 15 (address 5'00000).
|
|
Merging ports 0, 16 (address 5'00000).
|
|
Merging ports 18, 19 (address 5'10010).
|
|
Merging ports 20, 21 (address 5'10100).
|
|
Merging ports 20, 22 (address 5'10100).
|
|
Merging ports 20, 23 (address 5'10100).
|
|
Merging ports 24, 25 (address 5'11000).
|
|
Merging ports 24, 26 (address 5'11000).
|
|
Merging ports 24, 27 (address 5'11000).
|
|
Merging ports 24, 28 (address 5'11000).
|
|
Merging ports 24, 29 (address 5'11000).
|
|
Merging ports 24, 30 (address 5'11000).
|
|
Merging ports 24, 31 (address 5'11000).
|
|
Consolidating write ports of memory spi_neuron_top.u_graph_engine.w_mem by address:
|
|
Merging ports 1, 2 (address 5'10001).
|
|
Merging ports 1, 3 (address 5'10000).
|
|
Merging ports 1, 4 (address 5'10000).
|
|
Consolidating write ports of memory spi_neuron_top.u_graph_engine.w_mem by address:
|
|
Consolidating write ports of memory spi_neuron_top.u_neuron_memory.y_reg by address:
|
|
Consolidating read ports of memory spi_neuron_top.u_neuron_memory.x_mem by address:
|
|
Merging ports 0, 1 (address 5'11111).
|
|
Merging ports 0, 2 (address 5'11110).
|
|
Merging ports 0, 3 (address 5'11100).
|
|
Merging ports 0, 4 (address 5'11100).
|
|
Merging ports 0, 5 (address 5'11000).
|
|
Merging ports 0, 6 (address 5'11000).
|
|
Merging ports 0, 7 (address 5'11000).
|
|
Merging ports 0, 8 (address 5'11000).
|
|
Merging ports 0, 9 (address 5'10000).
|
|
Merging ports 0, 10 (address 5'10000).
|
|
Merging ports 0, 11 (address 5'10000).
|
|
Merging ports 0, 12 (address 5'10000).
|
|
Merging ports 0, 13 (address 5'10000).
|
|
Merging ports 0, 14 (address 5'10000).
|
|
Merging ports 0, 15 (address 5'10000).
|
|
Merging ports 0, 16 (address 5'10000).
|
|
Merging ports 18, 19 (address 5'01101).
|
|
Merging ports 20, 21 (address 5'01011).
|
|
Merging ports 20, 22 (address 5'01010).
|
|
Merging ports 20, 23 (address 5'01000).
|
|
Merging ports 24, 25 (address 5'00111).
|
|
Merging ports 24, 26 (address 5'00110).
|
|
Merging ports 24, 27 (address 5'00100).
|
|
Merging ports 24, 28 (address 5'00100).
|
|
Merging ports 24, 29 (address 5'00000).
|
|
Merging ports 24, 30 (address 5'00000).
|
|
Merging ports 24, 31 (address 5'00000).
|
|
Consolidating read ports of memory spi_neuron_top.u_neuron_memory.x_mem by address:
|
|
Merging ports 1, 2 (address 5'01110).
|
|
Merging ports 1, 3 (address 5'01100).
|
|
Merging ports 1, 4 (address 5'01000).
|
|
Consolidating read ports of memory spi_neuron_top.u_neuron_memory.x_mem by address:
|
|
Consolidating read ports of memory spi_neuron_top.u_neuron_memory.w_mem by address:
|
|
Merging ports 0, 1 (address 5'11111).
|
|
Merging ports 0, 2 (address 5'11110).
|
|
Merging ports 0, 3 (address 5'11100).
|
|
Merging ports 0, 4 (address 5'11100).
|
|
Merging ports 0, 5 (address 5'11000).
|
|
Merging ports 0, 6 (address 5'11000).
|
|
Merging ports 0, 7 (address 5'11000).
|
|
Merging ports 0, 8 (address 5'11000).
|
|
Merging ports 0, 9 (address 5'10000).
|
|
Merging ports 0, 10 (address 5'10000).
|
|
Merging ports 0, 11 (address 5'10000).
|
|
Merging ports 0, 12 (address 5'10000).
|
|
Merging ports 0, 13 (address 5'10000).
|
|
Merging ports 0, 14 (address 5'10000).
|
|
Merging ports 0, 15 (address 5'10000).
|
|
Merging ports 0, 16 (address 5'10000).
|
|
Merging ports 18, 19 (address 5'01101).
|
|
Merging ports 20, 21 (address 5'01011).
|
|
Merging ports 20, 22 (address 5'01010).
|
|
Merging ports 20, 23 (address 5'01000).
|
|
Merging ports 24, 25 (address 5'00111).
|
|
Merging ports 24, 26 (address 5'00110).
|
|
Merging ports 24, 27 (address 5'00100).
|
|
Merging ports 24, 28 (address 5'00100).
|
|
Merging ports 24, 29 (address 5'00000).
|
|
Merging ports 24, 30 (address 5'00000).
|
|
Merging ports 24, 31 (address 5'00000).
|
|
Consolidating read ports of memory spi_neuron_top.u_neuron_memory.w_mem by address:
|
|
Merging ports 1, 2 (address 5'01110).
|
|
Merging ports 1, 3 (address 5'01100).
|
|
Merging ports 1, 4 (address 5'01000).
|
|
Consolidating read ports of memory spi_neuron_top.u_neuron_memory.w_mem by address:
|
|
Consolidating write ports of memory spi_neuron_top.u_graph_engine.x_mem using sat-based resource sharing:
|
|
Consolidating write ports of memory spi_neuron_top.u_graph_engine.w_mem using sat-based resource sharing:
|
|
Consolidating write ports of memory spi_neuron_top.u_neuron_memory.y_reg using sat-based resource sharing:
|
|
Checking group clocked with posedge \clk, width 8: ports 0, 1.
|
|
Common input cone for all EN signals: 5 cells.
|
|
Size of unconstrained SAT problem: 42 variables, 115 clauses
|
|
Merging port 1 into port 0.
|
|
|
|
17.26.8. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide).
|
|
Performed a total of 0 transformations.
|
|
|
|
17.26.9. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \spi_neuron_top..
|
|
Removed 1 unused cells and 113 unused wires.
|
|
<suppressed ~2 debug messages>
|
|
|
|
17.26.10. Executing MEMORY_COLLECT pass (generating $mem cells).
|
|
|
|
17.27. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \spi_neuron_top..
|
|
|
|
17.28. Executing MEMORY_LIBMAP pass (mapping memories to cells).
|
|
mapping memory spi_neuron_top.u_graph_engine.u_act_buffer.mem via $__DP16KD_
|
|
using FF mapping for memory spi_neuron_top.$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1575
|
|
using FF mapping for memory spi_neuron_top.u_graph_engine.w_mem
|
|
using FF mapping for memory spi_neuron_top.u_graph_engine.x_mem
|
|
using FF mapping for memory spi_neuron_top.u_neuron_memory.x_mem
|
|
using FF mapping for memory spi_neuron_top.u_neuron_memory.w_mem
|
|
using FF mapping for memory spi_neuron_top.u_neuron_memory.y_reg
|
|
<suppressed ~910 debug messages>
|
|
|
|
17.29. Executing TECHMAP pass (map to technology primitives).
|
|
|
|
17.29.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/lutrams_map_trellis.v
|
|
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/lutrams_map_trellis.v' to AST representation.
|
|
Generating RTLIL representation for module `$__TRELLIS_DPR16X4_'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
17.29.2. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/brams_map_16kd.v
|
|
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/brams_map_16kd.v' to AST representation.
|
|
Generating RTLIL representation for module `$__DP16KD_'.
|
|
Generating RTLIL representation for module `$__PDPW16KD_'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
17.29.3. Continuing TECHMAP pass.
|
|
Using template $paramod$c4aea9a221b3d95ca47d9df3d018cdac65e6baac$__DP16KD_ for cells of type $__DP16KD_.
|
|
No more expansions possible.
|
|
<suppressed ~36 debug messages>
|
|
|
|
17.30. Executing OPT pass (performing simple optimizations).
|
|
|
|
17.30.1. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module spi_neuron_top.
|
|
<suppressed ~342 debug messages>
|
|
|
|
17.30.2. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\spi_neuron_top'.
|
|
Computing hashes of 1157 cells of `\spi_neuron_top'.
|
|
Finding duplicate cells in `\spi_neuron_top'.
|
|
Removed a total of 0 cells.
|
|
|
|
17.30.3. Executing OPT_DFF pass (perform DFF optimizations).
|
|
Removing always-active EN on $auto$mem.cc:1169:emulate_transparency$8268 ($dffe) from module spi_neuron_top.
|
|
|
|
17.30.4. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \spi_neuron_top..
|
|
Removed 14 unused cells and 274 unused wires.
|
|
<suppressed ~15 debug messages>
|
|
|
|
17.30.5. Rerunning OPT passes. (Removed registers in this run.)
|
|
|
|
17.30.6. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module spi_neuron_top.
|
|
<suppressed ~1 debug messages>
|
|
|
|
17.30.7. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\spi_neuron_top'.
|
|
Computing hashes of 1142 cells of `\spi_neuron_top'.
|
|
Finding duplicate cells in `\spi_neuron_top'.
|
|
Removed a total of 0 cells.
|
|
|
|
17.30.8. Executing OPT_DFF pass (perform DFF optimizations).
|
|
|
|
17.30.9. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \spi_neuron_top..
|
|
Removed 0 unused cells and 1 unused wires.
|
|
<suppressed ~1 debug messages>
|
|
|
|
17.30.10. Finished fast OPT passes.
|
|
|
|
17.31. Executing MEMORY_MAP pass (converting memories to logic and flip-flops).
|
|
Mapping memory $flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1575 in module \spi_neuron_top:
|
|
created 16 $dff cells and 0 static cells of width 6.
|
|
Extracted data FF from read port 0 of spi_neuron_top.$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1575: $$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1575$rdreg[0]
|
|
read interface: 1 $dff and 15 $mux cells.
|
|
write interface: 0 write mux blocks.
|
|
Mapping memory \u_graph_engine.w_mem in module \spi_neuron_top:
|
|
created 32 $dff cells and 0 static cells of width 8.
|
|
read interface: 0 $dff and 1 $mux cells.
|
|
write interface: 96 write mux blocks.
|
|
Mapping memory \u_graph_engine.x_mem in module \spi_neuron_top:
|
|
created 32 $dff cells and 0 static cells of width 8.
|
|
read interface: 0 $dff and 1 $mux cells.
|
|
write interface: 96 write mux blocks.
|
|
Mapping memory \u_neuron_memory.x_mem in module \spi_neuron_top:
|
|
created 32 $dff cells and 0 static cells of width 8.
|
|
read interface: 0 $dff and 1 $mux cells.
|
|
write interface: 32 write mux blocks.
|
|
Mapping memory \u_neuron_memory.w_mem in module \spi_neuron_top:
|
|
created 32 $dff cells and 0 static cells of width 8.
|
|
read interface: 0 $dff and 1 $mux cells.
|
|
write interface: 32 write mux blocks.
|
|
Mapping memory \u_neuron_memory.y_reg in module \spi_neuron_top:
|
|
created 1 $dff cells and 0 static cells of width 8.
|
|
read interface: 0 $dff and 0 $mux cells.
|
|
write interface: 1 write mux blocks.
|
|
|
|
17.32. Executing OPT pass (performing simple optimizations).
|
|
|
|
17.32.1. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module spi_neuron_top.
|
|
<suppressed ~223 debug messages>
|
|
|
|
17.32.2. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\spi_neuron_top'.
|
|
Computing hashes of 1705 cells of `\spi_neuron_top'.
|
|
Finding duplicate cells in `\spi_neuron_top'.
|
|
Computing hashes of 1673 cells of `\spi_neuron_top'.
|
|
Finding duplicate cells in `\spi_neuron_top'.
|
|
<suppressed ~96 debug messages>
|
|
Removed a total of 32 cells.
|
|
|
|
17.32.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \spi_neuron_top..
|
|
Creating internal representation of mux trees.
|
|
Evaluating internal representation of mux trees.
|
|
Replacing known input bits on port B of cell $auto$memory_share.cc:454:consolidate_wr_using_sat$8260: $auto$rtlil.cc:3271:ReduceOr$8254 -> 1'1
|
|
Analyzing evaluation results.
|
|
Removed 0 multiplexer ports.
|
|
<suppressed ~663 debug messages>
|
|
|
|
17.32.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \spi_neuron_top.
|
|
Consolidated identical input bits for $mux cell $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1575$rdmux[0][3][5]$8598:
|
|
Old ports: A=6'000001, B=6'000000, Y=$memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1575$rdmux[0][2][2]$b$8579
|
|
New ports: A=1'1, B=1'0, Y=$memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1575$rdmux[0][2][2]$b$8579 [0]
|
|
New connections: $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1575$rdmux[0][2][2]$b$8579 [5:1] = 5'00000
|
|
Consolidated identical input bits for $mux cell $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1575$rdmux[0][3][4]$8595:
|
|
Old ports: A=6'010000, B=6'000000, Y=$memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1575$rdmux[0][2][2]$a$8578
|
|
New ports: A=1'1, B=1'0, Y=$memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1575$rdmux[0][2][2]$a$8578 [4]
|
|
New connections: { $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1575$rdmux[0][2][2]$a$8578 [5] $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1575$rdmux[0][2][2]$a$8578 [3:0] } = 5'00000
|
|
Consolidated identical input bits for $mux cell $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1575$rdmux[0][3][3]$8592:
|
|
Old ports: A=6'000000, B=6'000001, Y=$memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1575$rdmux[0][2][1]$b$8576
|
|
New ports: A=1'0, B=1'1, Y=$memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1575$rdmux[0][2][1]$b$8576 [0]
|
|
New connections: $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1575$rdmux[0][2][1]$b$8576 [5:1] = 5'00000
|
|
Consolidated identical input bits for $mux cell $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1575$rdmux[0][3][2]$8589:
|
|
Old ports: A=6'000010, B=6'001000, Y=$memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1575$rdmux[0][2][1]$a$8575
|
|
New ports: A=2'01, B=2'10, Y={ $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1575$rdmux[0][2][1]$a$8575 [3] $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1575$rdmux[0][2][1]$a$8575 [1] }
|
|
New connections: { $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1575$rdmux[0][2][1]$a$8575 [5:4] $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1575$rdmux[0][2][1]$a$8575 [2] $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1575$rdmux[0][2][1]$a$8575 [0] } = 4'0000
|
|
Consolidated identical input bits for $mux cell $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1575$rdmux[0][3][1]$8586:
|
|
Old ports: A=6'100000, B=6'000001, Y=$memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1575$rdmux[0][2][0]$b$8573
|
|
New ports: A=2'10, B=2'01, Y={ $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1575$rdmux[0][2][0]$b$8573 [5] $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1575$rdmux[0][2][0]$b$8573 [0] }
|
|
New connections: $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1575$rdmux[0][2][0]$b$8573 [4:1] = 4'0000
|
|
Consolidated identical input bits for $mux cell $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1575$rdmux[0][3][0]$8583:
|
|
Old ports: A=6'010111, B=6'000000, Y=$memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1575$rdmux[0][2][0]$a$8572
|
|
New ports: A=1'1, B=1'0, Y=$memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1575$rdmux[0][2][0]$a$8572 [0]
|
|
New connections: $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1575$rdmux[0][2][0]$a$8572 [5:1] = { 1'0 $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1575$rdmux[0][2][0]$a$8572 [0] 1'0 $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1575$rdmux[0][2][0]$a$8572 [0] $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1575$rdmux[0][2][0]$a$8572 [0] }
|
|
New ctrl vector for $pmux cell $flatten\u_graph_engine.$procmux$2904: $auto$opt_reduce.cc:137:opt_pmux$10144
|
|
New ctrl vector for $pmux cell $flatten\u_graph_engine.$procmux$2927: $auto$opt_reduce.cc:137:opt_pmux$10146
|
|
New ctrl vector for $pmux cell $flatten\u_graph_engine.$procmux$2981: $auto$opt_reduce.cc:137:opt_pmux$10148
|
|
New ctrl vector for $pmux cell $flatten\u_graph_engine.$procmux$2999: { $auto$opt_reduce.cc:137:opt_pmux$10152 $auto$opt_reduce.cc:137:opt_pmux$10150 }
|
|
New ctrl vector for $pmux cell $flatten\u_graph_engine.$procmux$3035: { $auto$opt_reduce.cc:137:opt_pmux$10154 \u_graph_engine.state [2] }
|
|
New ctrl vector for $pmux cell $flatten\u_spi_engine.$procmux$3990: $auto$opt_reduce.cc:137:opt_pmux$10156
|
|
New ctrl vector for $pmux cell $flatten\u_graph_engine.$procmux$3139: $auto$opt_reduce.cc:137:opt_pmux$10158
|
|
Consolidated identical input bits for $pmux cell $flatten\u_neuron_memory.$procmux$2090:
|
|
Old ports: A=1'0, B=2'00, Y=$flatten\u_neuron_memory.$procmux$2090_Y
|
|
New connections: $flatten\u_neuron_memory.$procmux$2090_Y = 1'0
|
|
New ctrl vector for $pmux cell $flatten\u_neuron_memory.$procmux$2164: { \u_neuron_memory.state [2] \u_neuron_memory.state [3] }
|
|
New ctrl vector for $pmux cell $flatten\u_neuron_memory.$procmux$2203: \u_neuron_memory.state [0]
|
|
New ctrl vector for $pmux cell $flatten\u_spi_engine.$procmux$4037: \u_spi_engine.state [4]
|
|
New ctrl vector for $pmux cell $flatten\u_spi_engine.$procmux$3963: $auto$opt_reduce.cc:137:opt_pmux$10160
|
|
New ctrl vector for $pmux cell $flatten\u_psram_ctrl.$procmux$4887: { \u_psram_ctrl.state [0] $auto$opt_reduce.cc:137:opt_pmux$5660 }
|
|
New ctrl vector for $pmux cell $flatten\u_layer_sequencer.$procmux$3444: \u_layer_sequencer.state [2]
|
|
New input vector for $reduce_or cell $auto$opt_reduce.cc:131:opt_pmux$10157: { \u_graph_engine.state [10:9] \u_graph_engine.state [7] }
|
|
Optimizing cells in module \spi_neuron_top.
|
|
Consolidated identical input bits for $mux cell $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1575$rdmux[0][2][2]$8577:
|
|
Old ports: A=$memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1575$rdmux[0][2][2]$a$8578, B=$memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1575$rdmux[0][2][2]$b$8579, Y=$memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1575$rdmux[0][1][1]$a$8569
|
|
New ports: A={ $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1575$rdmux[0][2][2]$a$8578 [4] 1'0 }, B={ 1'0 $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1575$rdmux[0][2][2]$b$8579 [0] }, Y={ $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1575$rdmux[0][1][1]$a$8569 [4] $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1575$rdmux[0][1][1]$a$8569 [0] }
|
|
New connections: { $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1575$rdmux[0][1][1]$a$8569 [5] $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1575$rdmux[0][1][1]$a$8569 [3:1] } = 4'0000
|
|
Consolidated identical input bits for $mux cell $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1575$rdmux[0][2][1]$8574:
|
|
Old ports: A=$memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1575$rdmux[0][2][1]$a$8575, B=$memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1575$rdmux[0][2][1]$b$8576, Y=$memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1575$rdmux[0][1][0]$b$8567
|
|
New ports: A={ $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1575$rdmux[0][2][1]$a$8575 [3] $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1575$rdmux[0][2][1]$a$8575 [1] 1'0 }, B={ 2'00 $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1575$rdmux[0][2][1]$b$8576 [0] }, Y={ $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1575$rdmux[0][1][0]$b$8567 [3] $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1575$rdmux[0][1][0]$b$8567 [1:0] }
|
|
New connections: { $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1575$rdmux[0][1][0]$b$8567 [5:4] $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1575$rdmux[0][1][0]$b$8567 [2] } = 3'000
|
|
Consolidated identical input bits for $mux cell $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1575$rdmux[0][2][0]$8571:
|
|
Old ports: A=$memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1575$rdmux[0][2][0]$a$8572, B=$memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1575$rdmux[0][2][0]$b$8573, Y=$memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1575$rdmux[0][1][0]$a$8566
|
|
New ports: A={ 1'0 $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1575$rdmux[0][2][0]$a$8572 [0] $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1575$rdmux[0][2][0]$a$8572 [0] }, B={ $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1575$rdmux[0][2][0]$b$8573 [5] 1'0 $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1575$rdmux[0][2][0]$b$8573 [0] }, Y={ $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1575$rdmux[0][1][0]$a$8566 [5] $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1575$rdmux[0][1][0]$a$8566 [1:0] }
|
|
New connections: $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1575$rdmux[0][1][0]$a$8566 [4:2] = { $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1575$rdmux[0][1][0]$a$8566 [1] 1'0 $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1575$rdmux[0][1][0]$a$8566 [1] }
|
|
Optimizing cells in module \spi_neuron_top.
|
|
Consolidated identical input bits for $mux cell $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1575$rdmux[0][1][1]$8568:
|
|
Old ports: A=$memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1575$rdmux[0][1][1]$a$8569, B=6'000000, Y=$memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1575$rdmux[0][0][0]$b$8564
|
|
New ports: A={ $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1575$rdmux[0][1][1]$a$8569 [4] $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1575$rdmux[0][1][1]$a$8569 [0] }, B=2'00, Y={ $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1575$rdmux[0][0][0]$b$8564 [4] $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1575$rdmux[0][0][0]$b$8564 [0] }
|
|
New connections: { $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1575$rdmux[0][0][0]$b$8564 [5] $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1575$rdmux[0][0][0]$b$8564 [3:1] } = 4'0000
|
|
Consolidated identical input bits for $mux cell $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1575$rdmux[0][1][0]$8565:
|
|
Old ports: A=$memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1575$rdmux[0][1][0]$a$8566, B=$memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1575$rdmux[0][1][0]$b$8567, Y=$memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1575$rdmux[0][0][0]$a$8563
|
|
New ports: A={ $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1575$rdmux[0][1][0]$a$8566 [5] 1'0 $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1575$rdmux[0][1][0]$a$8566 [1] $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1575$rdmux[0][1][0]$a$8566 [1:0] }, B={ 1'0 $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1575$rdmux[0][1][0]$b$8567 [3] 1'0 $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1575$rdmux[0][1][0]$b$8567 [1:0] }, Y={ $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1575$rdmux[0][0][0]$a$8563 [5] $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1575$rdmux[0][0][0]$a$8563 [3:0] }
|
|
New connections: $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1575$rdmux[0][0][0]$a$8563 [4] = $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1575$rdmux[0][0][0]$a$8563 [2]
|
|
Optimizing cells in module \spi_neuron_top.
|
|
Performed a total of 26 changes.
|
|
|
|
17.32.5. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\spi_neuron_top'.
|
|
Computing hashes of 1681 cells of `\spi_neuron_top'.
|
|
Finding duplicate cells in `\spi_neuron_top'.
|
|
Computing hashes of 1674 cells of `\spi_neuron_top'.
|
|
Finding duplicate cells in `\spi_neuron_top'.
|
|
<suppressed ~21 debug messages>
|
|
Removed a total of 7 cells.
|
|
|
|
17.32.6. Executing OPT_DFF pass (perform DFF optimizations).
|
|
Adding EN signal on $auto$ff.cc:337:slice$7265 ($sdffe) from module spi_neuron_top (D = $flatten\u_graph_engine.$procmux$2904_Y, Q = \u_graph_engine.desc_addr).
|
|
Adding EN signal on $auto$ff.cc:337:slice$7279 ($sdffe) from module spi_neuron_top (D = $flatten\u_graph_engine.$procmux$2927_Y, Q = \u_graph_engine.neuron_idx).
|
|
Adding EN signal on $auto$ff.cc:337:slice$7322 ($sdffe) from module spi_neuron_top (D = $flatten\u_graph_engine.$procmux$2999_Y, Q = \u_graph_engine.busy).
|
|
Adding EN signal on $auto$ff.cc:337:slice$7344 ($sdffe) from module spi_neuron_top (D = $flatten\u_graph_engine.$procmux$3035_Y, Q = \u_graph_engine.desc_byte_idx).
|
|
|
|
17.32.7. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \spi_neuron_top..
|
|
Removed 0 unused cells and 410 unused wires.
|
|
<suppressed ~1 debug messages>
|
|
|
|
17.32.8. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module spi_neuron_top.
|
|
<suppressed ~6 debug messages>
|
|
|
|
17.32.9. Rerunning OPT passes. (Maybe there is more to do..)
|
|
|
|
17.32.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \spi_neuron_top..
|
|
Creating internal representation of mux trees.
|
|
Evaluating internal representation of mux trees.
|
|
Analyzing evaluation results.
|
|
Removed 0 multiplexer ports.
|
|
<suppressed ~644 debug messages>
|
|
|
|
17.32.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \spi_neuron_top.
|
|
New input vector for $reduce_and cell $auto$opt_dff.cc:337:make_patterns_logic$10180: { $auto$opt_dff.cc:319:make_patterns_logic$7188 $auto$opt_dff.cc:319:make_patterns_logic$7190 $auto$opt_dff.cc:319:make_patterns_logic$7220 $auto$opt_dff.cc:319:make_patterns_logic$7270 $auto$opt_dff.cc:319:make_patterns_logic$7274 $auto$opt_dff.cc:319:make_patterns_logic$7353 $auto$opt_dff.cc:319:make_patterns_logic$7355 $auto$opt_dff.cc:319:make_patterns_logic$7359 $auto$opt_dff.cc:319:make_patterns_logic$10177 }
|
|
New input vector for $reduce_and cell $auto$opt_dff.cc:337:make_patterns_logic$10175: { $auto$opt_dff.cc:319:make_patterns_logic$7190 $auto$opt_dff.cc:319:make_patterns_logic$7222 $auto$opt_dff.cc:319:make_patterns_logic$7268 $auto$opt_dff.cc:319:make_patterns_logic$7270 $auto$opt_dff.cc:319:make_patterns_logic$7274 $auto$opt_dff.cc:319:make_patterns_logic$7312 $auto$opt_dff.cc:319:make_patterns_logic$7314 $auto$opt_dff.cc:319:make_patterns_logic$7316 $auto$opt_dff.cc:319:make_patterns_logic$7323 $auto$opt_dff.cc:319:make_patterns_logic$10172 }
|
|
New input vector for $reduce_and cell $auto$opt_dff.cc:337:make_patterns_logic$10170: { $auto$opt_dff.cc:319:make_patterns_logic$7190 $auto$opt_dff.cc:319:make_patterns_logic$7266 $auto$opt_dff.cc:319:make_patterns_logic$7268 $auto$opt_dff.cc:319:make_patterns_logic$7270 $auto$opt_dff.cc:319:make_patterns_logic$7274 $auto$opt_dff.cc:319:make_patterns_logic$10167 }
|
|
New input vector for $reduce_and cell $auto$opt_dff.cc:337:make_patterns_logic$10165: { $auto$opt_dff.cc:319:make_patterns_logic$7190 $auto$opt_dff.cc:319:make_patterns_logic$7266 $auto$opt_dff.cc:319:make_patterns_logic$7268 $auto$opt_dff.cc:319:make_patterns_logic$7270 $auto$opt_dff.cc:319:make_patterns_logic$7274 $auto$opt_dff.cc:319:make_patterns_logic$10162 }
|
|
New ctrl vector for $pmux cell $flatten\u_graph_engine.$procmux$2999: $auto$opt_reduce.cc:137:opt_pmux$10182
|
|
New ctrl vector for $pmux cell $flatten\u_graph_engine.$procmux$3035: \u_graph_engine.state [2]
|
|
New input vector for $reduce_or cell $auto$opt_reduce.cc:131:opt_pmux$10181: { \u_graph_engine.state [11] \u_graph_engine.state [9:8] \u_graph_engine.state [6] }
|
|
Optimizing cells in module \spi_neuron_top.
|
|
Performed a total of 7 changes.
|
|
|
|
17.32.12. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\spi_neuron_top'.
|
|
Computing hashes of 1677 cells of `\spi_neuron_top'.
|
|
Finding duplicate cells in `\spi_neuron_top'.
|
|
Computing hashes of 1675 cells of `\spi_neuron_top'.
|
|
Finding duplicate cells in `\spi_neuron_top'.
|
|
Computing hashes of 1674 cells of `\spi_neuron_top'.
|
|
Finding duplicate cells in `\spi_neuron_top'.
|
|
<suppressed ~9 debug messages>
|
|
Removed a total of 3 cells.
|
|
|
|
17.32.13. Executing OPT_DFF pass (perform DFF optimizations).
|
|
Adding SRST signal on $$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1575$rdreg[0] ($dff) from module spi_neuron_top (D = $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1575$rdmux[0][2][0]$b$8573 [5], Q = $flatten\u_spi_engine.$4\tx_byte_comb[7:0] [5], rval = 1'0).
|
|
Adding SRST signal on $$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1575$rdreg[0] ($dff) from module spi_neuron_top (D = $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1575$rdmux[0][2][1]$a$8575 [3], Q = $flatten\u_spi_engine.$4\tx_byte_comb[7:0] [3], rval = 1'0).
|
|
Adding SRST signal on $$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1575$rdreg[0] ($dff) from module spi_neuron_top (D = $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1575$rdmux[0][0][0]$a$8563 [2:1], Q = $flatten\u_spi_engine.$4\tx_byte_comb[7:0] [2:1], rval = 2'00).
|
|
Adding EN signal on $memory\u_graph_engine.w_mem[0]$8607 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.w_mem$wrmux[0][2][0]$y$8707, Q = \u_graph_engine.w_mem[0]).
|
|
Adding EN signal on $memory\u_graph_engine.w_mem[1]$8609 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.w_mem$wrmux[1][2][0]$y$8725, Q = \u_graph_engine.w_mem[1]).
|
|
Adding EN signal on $memory\u_graph_engine.w_mem[2]$8611 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.w_mem$wrmux[2][2][0]$y$8743, Q = \u_graph_engine.w_mem[2]).
|
|
Adding EN signal on $memory\u_graph_engine.w_mem[3]$8613 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.w_mem$wrmux[3][2][0]$y$8759, Q = \u_graph_engine.w_mem[3]).
|
|
Adding EN signal on $memory\u_graph_engine.w_mem[4]$8615 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.w_mem$wrmux[4][2][0]$y$8777, Q = \u_graph_engine.w_mem[4]).
|
|
Adding EN signal on $memory\u_graph_engine.w_mem[5]$8617 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.w_mem$wrmux[5][2][0]$y$8791, Q = \u_graph_engine.w_mem[5]).
|
|
Adding EN signal on $memory\u_graph_engine.w_mem[6]$8619 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.w_mem$wrmux[6][2][0]$y$8805, Q = \u_graph_engine.w_mem[6]).
|
|
Adding EN signal on $memory\u_graph_engine.w_mem[7]$8621 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.w_mem$wrmux[7][2][0]$y$8819, Q = \u_graph_engine.w_mem[7]).
|
|
Adding EN signal on $memory\u_graph_engine.w_mem[8]$8623 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.w_mem$wrmux[8][2][0]$y$8839, Q = \u_graph_engine.w_mem[8]).
|
|
Adding EN signal on $memory\u_graph_engine.w_mem[9]$8625 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.w_mem$wrmux[9][2][0]$y$8853, Q = \u_graph_engine.w_mem[9]).
|
|
Adding EN signal on $memory\u_graph_engine.w_mem[10]$8627 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.w_mem$wrmux[10][2][0]$y$8867, Q = \u_graph_engine.w_mem[10]).
|
|
Adding EN signal on $memory\u_graph_engine.w_mem[11]$8629 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.w_mem$wrmux[11][2][0]$y$8881, Q = \u_graph_engine.w_mem[11]).
|
|
Adding EN signal on $memory\u_graph_engine.w_mem[12]$8631 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.w_mem$wrmux[12][2][0]$y$8897, Q = \u_graph_engine.w_mem[12]).
|
|
Adding EN signal on $memory\u_graph_engine.w_mem[13]$8633 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.w_mem$wrmux[13][2][0]$y$8911, Q = \u_graph_engine.w_mem[13]).
|
|
Adding EN signal on $memory\u_graph_engine.w_mem[14]$8635 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.w_mem$wrmux[14][2][0]$y$8925, Q = \u_graph_engine.w_mem[14]).
|
|
Adding EN signal on $memory\u_graph_engine.w_mem[15]$8637 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.w_mem$wrmux[15][2][0]$y$8939, Q = \u_graph_engine.w_mem[15]).
|
|
Adding EN signal on $memory\u_graph_engine.w_mem[16]$8639 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.w_mem$wrmux[16][2][0]$y$8961, Q = \u_graph_engine.w_mem[16]).
|
|
Adding EN signal on $memory\u_graph_engine.w_mem[17]$8641 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.w_mem$wrmux[17][2][0]$y$8975, Q = \u_graph_engine.w_mem[17]).
|
|
Adding EN signal on $memory\u_graph_engine.w_mem[18]$8643 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.w_mem$wrmux[18][2][0]$y$8989, Q = \u_graph_engine.w_mem[18]).
|
|
Adding EN signal on $memory\u_graph_engine.w_mem[19]$8645 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.w_mem$wrmux[19][2][0]$y$9003, Q = \u_graph_engine.w_mem[19]).
|
|
Adding EN signal on $memory\u_graph_engine.w_mem[20]$8647 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.w_mem$wrmux[20][2][0]$y$9019, Q = \u_graph_engine.w_mem[20]).
|
|
Adding EN signal on $memory\u_graph_engine.w_mem[21]$8649 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.w_mem$wrmux[21][2][0]$y$9033, Q = \u_graph_engine.w_mem[21]).
|
|
Adding EN signal on $memory\u_graph_engine.w_mem[22]$8651 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.w_mem$wrmux[22][2][0]$y$9047, Q = \u_graph_engine.w_mem[22]).
|
|
Adding EN signal on $memory\u_graph_engine.w_mem[23]$8653 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.w_mem$wrmux[23][2][0]$y$9061, Q = \u_graph_engine.w_mem[23]).
|
|
Adding EN signal on $memory\u_graph_engine.w_mem[24]$8655 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.w_mem$wrmux[24][2][0]$y$9079, Q = \u_graph_engine.w_mem[24]).
|
|
Adding EN signal on $memory\u_graph_engine.w_mem[25]$8657 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.w_mem$wrmux[25][2][0]$y$9093, Q = \u_graph_engine.w_mem[25]).
|
|
Adding EN signal on $memory\u_graph_engine.w_mem[26]$8659 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.w_mem$wrmux[26][2][0]$y$9107, Q = \u_graph_engine.w_mem[26]).
|
|
Adding EN signal on $memory\u_graph_engine.w_mem[27]$8661 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.w_mem$wrmux[27][2][0]$y$9121, Q = \u_graph_engine.w_mem[27]).
|
|
Adding EN signal on $memory\u_graph_engine.w_mem[28]$8663 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.w_mem$wrmux[28][2][0]$y$9137, Q = \u_graph_engine.w_mem[28]).
|
|
Adding EN signal on $memory\u_graph_engine.w_mem[29]$8665 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.w_mem$wrmux[29][2][0]$y$9151, Q = \u_graph_engine.w_mem[29]).
|
|
Adding EN signal on $memory\u_graph_engine.w_mem[30]$8667 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.w_mem$wrmux[30][2][0]$y$9165, Q = \u_graph_engine.w_mem[30]).
|
|
Adding EN signal on $memory\u_graph_engine.w_mem[31]$8669 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.w_mem$wrmux[31][2][0]$y$9179, Q = \u_graph_engine.w_mem[31]).
|
|
Adding EN signal on $memory\u_neuron_memory.x_mem[7]$9645 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.x_mem[7]).
|
|
Adding EN signal on $memory\u_neuron_memory.x_mem[8]$9647 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.x_mem[8]).
|
|
Adding EN signal on $memory\u_neuron_memory.x_mem[9]$9649 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.x_mem[9]).
|
|
Adding EN signal on $memory\u_neuron_memory.x_mem[10]$9651 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.x_mem[10]).
|
|
Adding EN signal on $memory\u_neuron_memory.x_mem[11]$9653 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.x_mem[11]).
|
|
Adding EN signal on $memory\u_neuron_memory.x_mem[12]$9655 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.x_mem[12]).
|
|
Adding EN signal on $memory\u_neuron_memory.x_mem[13]$9657 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.x_mem[13]).
|
|
Adding EN signal on $memory\u_neuron_memory.x_mem[14]$9659 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.x_mem[14]).
|
|
Adding EN signal on $memory\u_neuron_memory.x_mem[15]$9661 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.x_mem[15]).
|
|
Adding EN signal on $memory\u_neuron_memory.x_mem[16]$9663 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.x_mem[16]).
|
|
Adding EN signal on $memory\u_neuron_memory.x_mem[17]$9665 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.x_mem[17]).
|
|
Adding EN signal on $memory\u_neuron_memory.x_mem[18]$9667 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.x_mem[18]).
|
|
Adding EN signal on $memory\u_neuron_memory.x_mem[19]$9669 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.x_mem[19]).
|
|
Adding EN signal on $memory\u_neuron_memory.x_mem[20]$9671 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.x_mem[20]).
|
|
Adding EN signal on $memory\u_neuron_memory.x_mem[21]$9673 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.x_mem[21]).
|
|
Adding EN signal on $memory\u_neuron_memory.w_mem[31]$10004 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.w_mem[31]).
|
|
Adding EN signal on $memory\u_neuron_memory.w_mem[30]$10002 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.w_mem[30]).
|
|
Adding EN signal on $memory\u_neuron_memory.x_mem[22]$9675 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.x_mem[22]).
|
|
Adding EN signal on $memory\u_neuron_memory.w_mem[29]$10000 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.w_mem[29]).
|
|
Adding EN signal on $memory\u_neuron_memory.w_mem[28]$9998 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.w_mem[28]).
|
|
Adding EN signal on $memory\u_neuron_memory.w_mem[27]$9996 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.w_mem[27]).
|
|
Adding EN signal on $memory\u_neuron_memory.x_mem[23]$9677 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.x_mem[23]).
|
|
Adding EN signal on $memory\u_neuron_memory.w_mem[26]$9994 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.w_mem[26]).
|
|
Adding EN signal on $memory\u_neuron_memory.w_mem[25]$9992 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.w_mem[25]).
|
|
Adding EN signal on $memory\u_neuron_memory.w_mem[24]$9990 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.w_mem[24]).
|
|
Adding EN signal on $memory\u_neuron_memory.x_mem[24]$9679 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.x_mem[24]).
|
|
Adding EN signal on $memory\u_neuron_memory.w_mem[23]$9988 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.w_mem[23]).
|
|
Adding EN signal on $memory\u_neuron_memory.w_mem[22]$9986 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.w_mem[22]).
|
|
Adding EN signal on $memory\u_neuron_memory.w_mem[21]$9984 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.w_mem[21]).
|
|
Adding EN signal on $memory\u_neuron_memory.x_mem[25]$9681 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.x_mem[25]).
|
|
Adding EN signal on $memory\u_neuron_memory.w_mem[20]$9982 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.w_mem[20]).
|
|
Adding EN signal on $memory\u_neuron_memory.w_mem[19]$9980 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.w_mem[19]).
|
|
Adding EN signal on $memory\u_neuron_memory.w_mem[18]$9978 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.w_mem[18]).
|
|
Adding EN signal on $memory\u_neuron_memory.x_mem[26]$9683 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.x_mem[26]).
|
|
Adding EN signal on $memory\u_neuron_memory.w_mem[17]$9976 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.w_mem[17]).
|
|
Adding EN signal on $memory\u_neuron_memory.w_mem[16]$9974 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.w_mem[16]).
|
|
Adding EN signal on $memory\u_neuron_memory.w_mem[15]$9972 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.w_mem[15]).
|
|
Adding EN signal on $memory\u_neuron_memory.x_mem[27]$9685 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.x_mem[27]).
|
|
Adding EN signal on $memory\u_neuron_memory.w_mem[14]$9970 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.w_mem[14]).
|
|
Adding EN signal on $memory\u_neuron_memory.w_mem[13]$9968 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.w_mem[13]).
|
|
Adding EN signal on $memory\u_neuron_memory.w_mem[12]$9966 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.w_mem[12]).
|
|
Adding EN signal on $memory\u_neuron_memory.x_mem[28]$9687 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.x_mem[28]).
|
|
Adding EN signal on $memory\u_neuron_memory.w_mem[11]$9964 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.w_mem[11]).
|
|
Adding EN signal on $memory\u_neuron_memory.w_mem[10]$9962 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.w_mem[10]).
|
|
Adding EN signal on $memory\u_neuron_memory.w_mem[9]$9960 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.w_mem[9]).
|
|
Adding EN signal on $memory\u_neuron_memory.x_mem[29]$9689 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.x_mem[29]).
|
|
Adding EN signal on $memory\u_neuron_memory.w_mem[8]$9958 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.w_mem[8]).
|
|
Adding EN signal on $memory\u_neuron_memory.w_mem[7]$9956 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.w_mem[7]).
|
|
Adding EN signal on $memory\u_neuron_memory.w_mem[6]$9954 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.w_mem[6]).
|
|
Adding EN signal on $memory\u_neuron_memory.x_mem[30]$9691 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.x_mem[30]).
|
|
Adding EN signal on $memory\u_neuron_memory.w_mem[5]$9952 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.w_mem[5]).
|
|
Adding EN signal on $memory\u_neuron_memory.w_mem[4]$9950 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.w_mem[4]).
|
|
Adding EN signal on $memory\u_neuron_memory.w_mem[3]$9948 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.w_mem[3]).
|
|
Adding EN signal on $memory\u_neuron_memory.x_mem[31]$9693 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.x_mem[31]).
|
|
Adding EN signal on $memory\u_neuron_memory.w_mem[2]$9946 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.w_mem[2]).
|
|
Adding EN signal on $memory\u_neuron_memory.w_mem[1]$9944 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.w_mem[1]).
|
|
Adding EN signal on $memory\u_neuron_memory.w_mem[0]$9942 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.w_mem[0]).
|
|
Adding EN signal on $memory\u_graph_engine.x_mem[0]$9180 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.x_mem$wrmux[0][2][0]$y$9258, Q = \u_graph_engine.x_mem[0]).
|
|
Adding EN signal on $memory\u_graph_engine.x_mem[1]$9182 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.x_mem$wrmux[1][2][0]$y$9270, Q = \u_graph_engine.x_mem[1]).
|
|
Adding EN signal on $memory\u_graph_engine.x_mem[2]$9184 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.x_mem$wrmux[2][2][0]$y$9282, Q = \u_graph_engine.x_mem[2]).
|
|
Adding EN signal on $memory\u_graph_engine.x_mem[3]$9186 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.x_mem$wrmux[3][2][0]$y$9294, Q = \u_graph_engine.x_mem[3]).
|
|
Adding EN signal on $memory\u_graph_engine.x_mem[4]$9188 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.x_mem$wrmux[4][2][0]$y$9306, Q = \u_graph_engine.x_mem[4]).
|
|
Adding EN signal on $memory\u_graph_engine.x_mem[5]$9190 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.x_mem$wrmux[5][2][0]$y$9318, Q = \u_graph_engine.x_mem[5]).
|
|
Adding EN signal on $memory\u_graph_engine.x_mem[6]$9192 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.x_mem$wrmux[6][2][0]$y$9330, Q = \u_graph_engine.x_mem[6]).
|
|
Adding EN signal on $memory\u_graph_engine.x_mem[7]$9194 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.x_mem$wrmux[7][2][0]$y$9342, Q = \u_graph_engine.x_mem[7]).
|
|
Adding EN signal on $memory\u_graph_engine.x_mem[8]$9196 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.x_mem$wrmux[8][2][0]$y$9354, Q = \u_graph_engine.x_mem[8]).
|
|
Adding EN signal on $memory\u_graph_engine.x_mem[9]$9198 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.x_mem$wrmux[9][2][0]$y$9366, Q = \u_graph_engine.x_mem[9]).
|
|
Adding EN signal on $memory\u_graph_engine.x_mem[10]$9200 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.x_mem$wrmux[10][2][0]$y$9378, Q = \u_graph_engine.x_mem[10]).
|
|
Adding EN signal on $memory\u_graph_engine.x_mem[11]$9202 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.x_mem$wrmux[11][2][0]$y$9390, Q = \u_graph_engine.x_mem[11]).
|
|
Adding EN signal on $memory\u_graph_engine.x_mem[12]$9204 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.x_mem$wrmux[12][2][0]$y$9402, Q = \u_graph_engine.x_mem[12]).
|
|
Adding EN signal on $memory\u_graph_engine.x_mem[13]$9206 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.x_mem$wrmux[13][2][0]$y$9414, Q = \u_graph_engine.x_mem[13]).
|
|
Adding EN signal on $memory\u_graph_engine.x_mem[14]$9208 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.x_mem$wrmux[14][2][0]$y$9426, Q = \u_graph_engine.x_mem[14]).
|
|
Adding EN signal on $memory\u_graph_engine.x_mem[15]$9210 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.x_mem$wrmux[15][2][0]$y$9438, Q = \u_graph_engine.x_mem[15]).
|
|
Adding EN signal on $memory\u_graph_engine.x_mem[16]$9212 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.x_mem$wrmux[16][2][0]$y$9450, Q = \u_graph_engine.x_mem[16]).
|
|
Adding EN signal on $memory\u_graph_engine.x_mem[17]$9214 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.x_mem$wrmux[17][2][0]$y$9462, Q = \u_graph_engine.x_mem[17]).
|
|
Adding EN signal on $memory\u_graph_engine.x_mem[18]$9216 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.x_mem$wrmux[18][2][0]$y$9474, Q = \u_graph_engine.x_mem[18]).
|
|
Adding EN signal on $memory\u_graph_engine.x_mem[19]$9218 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.x_mem$wrmux[19][2][0]$y$9486, Q = \u_graph_engine.x_mem[19]).
|
|
Adding EN signal on $memory\u_graph_engine.x_mem[20]$9220 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.x_mem$wrmux[20][2][0]$y$9498, Q = \u_graph_engine.x_mem[20]).
|
|
Adding EN signal on $memory\u_graph_engine.x_mem[21]$9222 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.x_mem$wrmux[21][2][0]$y$9510, Q = \u_graph_engine.x_mem[21]).
|
|
Adding EN signal on $memory\u_graph_engine.x_mem[22]$9224 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.x_mem$wrmux[22][2][0]$y$9522, Q = \u_graph_engine.x_mem[22]).
|
|
Adding EN signal on $memory\u_graph_engine.x_mem[23]$9226 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.x_mem$wrmux[23][2][0]$y$9534, Q = \u_graph_engine.x_mem[23]).
|
|
Adding EN signal on $memory\u_graph_engine.x_mem[24]$9228 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.x_mem$wrmux[24][2][0]$y$9546, Q = \u_graph_engine.x_mem[24]).
|
|
Adding EN signal on $memory\u_graph_engine.x_mem[25]$9230 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.x_mem$wrmux[25][2][0]$y$9558, Q = \u_graph_engine.x_mem[25]).
|
|
Adding EN signal on $memory\u_graph_engine.x_mem[26]$9232 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.x_mem$wrmux[26][2][0]$y$9570, Q = \u_graph_engine.x_mem[26]).
|
|
Adding EN signal on $memory\u_graph_engine.x_mem[27]$9234 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.x_mem$wrmux[27][2][0]$y$9582, Q = \u_graph_engine.x_mem[27]).
|
|
Adding EN signal on $memory\u_graph_engine.x_mem[28]$9236 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.x_mem$wrmux[28][2][0]$y$9594, Q = \u_graph_engine.x_mem[28]).
|
|
Adding EN signal on $memory\u_graph_engine.x_mem[29]$9238 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.x_mem$wrmux[29][2][0]$y$9606, Q = \u_graph_engine.x_mem[29]).
|
|
Adding EN signal on $memory\u_graph_engine.x_mem[30]$9240 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.x_mem$wrmux[30][2][0]$y$9618, Q = \u_graph_engine.x_mem[30]).
|
|
Adding EN signal on $memory\u_graph_engine.x_mem[31]$9242 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.x_mem$wrmux[31][2][0]$y$9630, Q = \u_graph_engine.x_mem[31]).
|
|
Adding EN signal on $memory\u_neuron_memory.y_reg[0]$10137 ($dff) from module spi_neuron_top (D = $auto$rtlil.cc:3402:Mux$8258, Q = \u_neuron_memory.y_reg[0]).
|
|
Adding SRST signal on $auto$ff.cc:337:slice$10444 ($dffe) from module spi_neuron_top (D = \u_neuron_memory.u_neuron.y, Q = \u_neuron_memory.y_reg[0], rval = 8'00000000).
|
|
Adding EN signal on $memory\u_neuron_memory.x_mem[0]$9631 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.x_mem[0]).
|
|
Adding EN signal on $memory\u_neuron_memory.x_mem[1]$9633 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.x_mem[1]).
|
|
Adding EN signal on $memory\u_neuron_memory.x_mem[2]$9635 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.x_mem[2]).
|
|
Adding EN signal on $memory\u_neuron_memory.x_mem[3]$9637 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.x_mem[3]).
|
|
Adding EN signal on $memory\u_neuron_memory.x_mem[4]$9639 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.x_mem[4]).
|
|
Adding EN signal on $memory\u_neuron_memory.x_mem[5]$9641 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.x_mem[5]).
|
|
Adding EN signal on $memory\u_neuron_memory.x_mem[6]$9643 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.x_mem[6]).
|
|
Setting constant 0-bit at position 0 on $auto$ff.cc:337:slice$7018 ($sdffe) from module spi_neuron_top.
|
|
|
|
17.32.14. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \spi_neuron_top..
|
|
Removed 73 unused cells and 82 unused wires.
|
|
<suppressed ~74 debug messages>
|
|
|
|
17.32.15. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module spi_neuron_top.
|
|
<suppressed ~128 debug messages>
|
|
|
|
17.32.16. Rerunning OPT passes. (Maybe there is more to do..)
|
|
|
|
17.32.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \spi_neuron_top..
|
|
Creating internal representation of mux trees.
|
|
Evaluating internal representation of mux trees.
|
|
Analyzing evaluation results.
|
|
Removed 0 multiplexer ports.
|
|
<suppressed ~452 debug messages>
|
|
|
|
17.32.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \spi_neuron_top.
|
|
Performed a total of 0 changes.
|
|
|
|
17.32.19. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\spi_neuron_top'.
|
|
Computing hashes of 1607 cells of `\spi_neuron_top'.
|
|
Finding duplicate cells in `\spi_neuron_top'.
|
|
Computing hashes of 1575 cells of `\spi_neuron_top'.
|
|
Finding duplicate cells in `\spi_neuron_top'.
|
|
<suppressed ~96 debug messages>
|
|
Removed a total of 32 cells.
|
|
|
|
17.32.20. Executing OPT_DFF pass (perform DFF optimizations).
|
|
Adding SRST signal on $auto$ff.cc:337:slice$10195 ($dffe) from module spi_neuron_top (D = \u_graph_engine.weight_acc, Q = \u_graph_engine.w_mem[0], rval = 8'00000000).
|
|
Adding SRST signal on $auto$ff.cc:337:slice$10198 ($dffe) from module spi_neuron_top (D = \u_graph_engine.weight_acc, Q = \u_graph_engine.w_mem[1], rval = 8'00000000).
|
|
Adding SRST signal on $auto$ff.cc:337:slice$10201 ($dffe) from module spi_neuron_top (D = \u_graph_engine.weight_acc, Q = \u_graph_engine.w_mem[2], rval = 8'00000000).
|
|
Adding SRST signal on $auto$ff.cc:337:slice$10204 ($dffe) from module spi_neuron_top (D = \u_graph_engine.weight_acc, Q = \u_graph_engine.w_mem[3], rval = 8'00000000).
|
|
Adding SRST signal on $auto$ff.cc:337:slice$10207 ($dffe) from module spi_neuron_top (D = \u_graph_engine.weight_acc, Q = \u_graph_engine.w_mem[4], rval = 8'00000000).
|
|
Adding SRST signal on $auto$ff.cc:337:slice$10210 ($dffe) from module spi_neuron_top (D = \u_graph_engine.weight_acc, Q = \u_graph_engine.w_mem[5], rval = 8'00000000).
|
|
Adding SRST signal on $auto$ff.cc:337:slice$10213 ($dffe) from module spi_neuron_top (D = \u_graph_engine.weight_acc, Q = \u_graph_engine.w_mem[6], rval = 8'00000000).
|
|
Adding SRST signal on $auto$ff.cc:337:slice$10216 ($dffe) from module spi_neuron_top (D = \u_graph_engine.weight_acc, Q = \u_graph_engine.w_mem[7], rval = 8'00000000).
|
|
Adding SRST signal on $auto$ff.cc:337:slice$10219 ($dffe) from module spi_neuron_top (D = \u_graph_engine.weight_acc, Q = \u_graph_engine.w_mem[8], rval = 8'00000000).
|
|
Adding SRST signal on $auto$ff.cc:337:slice$10222 ($dffe) from module spi_neuron_top (D = \u_graph_engine.weight_acc, Q = \u_graph_engine.w_mem[9], rval = 8'00000000).
|
|
Adding SRST signal on $auto$ff.cc:337:slice$10225 ($dffe) from module spi_neuron_top (D = \u_graph_engine.weight_acc, Q = \u_graph_engine.w_mem[10], rval = 8'00000000).
|
|
Adding SRST signal on $auto$ff.cc:337:slice$10228 ($dffe) from module spi_neuron_top (D = \u_graph_engine.weight_acc, Q = \u_graph_engine.w_mem[11], rval = 8'00000000).
|
|
Adding SRST signal on $auto$ff.cc:337:slice$10231 ($dffe) from module spi_neuron_top (D = \u_graph_engine.weight_acc, Q = \u_graph_engine.w_mem[12], rval = 8'00000000).
|
|
Adding SRST signal on $auto$ff.cc:337:slice$10234 ($dffe) from module spi_neuron_top (D = \u_graph_engine.weight_acc, Q = \u_graph_engine.w_mem[13], rval = 8'00000000).
|
|
Adding SRST signal on $auto$ff.cc:337:slice$10237 ($dffe) from module spi_neuron_top (D = \u_graph_engine.weight_acc, Q = \u_graph_engine.w_mem[14], rval = 8'00000000).
|
|
Adding SRST signal on $auto$ff.cc:337:slice$10240 ($dffe) from module spi_neuron_top (D = \u_graph_engine.weight_acc, Q = \u_graph_engine.w_mem[15], rval = 8'00000000).
|
|
Adding SRST signal on $auto$ff.cc:337:slice$10243 ($dffe) from module spi_neuron_top (D = \u_graph_engine.weight_acc, Q = \u_graph_engine.w_mem[16], rval = 8'00000000).
|
|
Adding SRST signal on $auto$ff.cc:337:slice$10246 ($dffe) from module spi_neuron_top (D = \u_graph_engine.weight_acc, Q = \u_graph_engine.w_mem[17], rval = 8'00000000).
|
|
Adding SRST signal on $auto$ff.cc:337:slice$10249 ($dffe) from module spi_neuron_top (D = \u_graph_engine.weight_acc, Q = \u_graph_engine.w_mem[18], rval = 8'00000000).
|
|
Adding SRST signal on $auto$ff.cc:337:slice$10252 ($dffe) from module spi_neuron_top (D = \u_graph_engine.weight_acc, Q = \u_graph_engine.w_mem[19], rval = 8'00000000).
|
|
Adding SRST signal on $auto$ff.cc:337:slice$10255 ($dffe) from module spi_neuron_top (D = \u_graph_engine.weight_acc, Q = \u_graph_engine.w_mem[20], rval = 8'00000000).
|
|
Adding SRST signal on $auto$ff.cc:337:slice$10258 ($dffe) from module spi_neuron_top (D = \u_graph_engine.weight_acc, Q = \u_graph_engine.w_mem[21], rval = 8'00000000).
|
|
Adding SRST signal on $auto$ff.cc:337:slice$10261 ($dffe) from module spi_neuron_top (D = \u_graph_engine.weight_acc, Q = \u_graph_engine.w_mem[22], rval = 8'00000000).
|
|
Adding SRST signal on $auto$ff.cc:337:slice$10264 ($dffe) from module spi_neuron_top (D = \u_graph_engine.weight_acc, Q = \u_graph_engine.w_mem[23], rval = 8'00000000).
|
|
Adding SRST signal on $auto$ff.cc:337:slice$10267 ($dffe) from module spi_neuron_top (D = \u_graph_engine.weight_acc, Q = \u_graph_engine.w_mem[24], rval = 8'00000000).
|
|
Adding SRST signal on $auto$ff.cc:337:slice$10270 ($dffe) from module spi_neuron_top (D = \u_graph_engine.weight_acc, Q = \u_graph_engine.w_mem[25], rval = 8'00000000).
|
|
Adding SRST signal on $auto$ff.cc:337:slice$10273 ($dffe) from module spi_neuron_top (D = \u_graph_engine.weight_acc, Q = \u_graph_engine.w_mem[26], rval = 8'00000000).
|
|
Adding SRST signal on $auto$ff.cc:337:slice$10276 ($dffe) from module spi_neuron_top (D = \u_graph_engine.weight_acc, Q = \u_graph_engine.w_mem[27], rval = 8'00000000).
|
|
Adding SRST signal on $auto$ff.cc:337:slice$10279 ($dffe) from module spi_neuron_top (D = \u_graph_engine.weight_acc, Q = \u_graph_engine.w_mem[28], rval = 8'00000000).
|
|
Adding SRST signal on $auto$ff.cc:337:slice$10282 ($dffe) from module spi_neuron_top (D = \u_graph_engine.weight_acc, Q = \u_graph_engine.w_mem[29], rval = 8'00000000).
|
|
Adding SRST signal on $auto$ff.cc:337:slice$10285 ($dffe) from module spi_neuron_top (D = \u_graph_engine.weight_acc, Q = \u_graph_engine.w_mem[30], rval = 8'00000000).
|
|
Adding SRST signal on $auto$ff.cc:337:slice$10288 ($dffe) from module spi_neuron_top (D = \u_graph_engine.weight_acc, Q = \u_graph_engine.w_mem[31], rval = 8'00000000).
|
|
Adding SRST signal on $auto$ff.cc:337:slice$10348 ($dffe) from module spi_neuron_top (D = \u_graph_engine.u_act_buffer.rd_data, Q = \u_graph_engine.x_mem[0], rval = 8'00000000).
|
|
Adding SRST signal on $auto$ff.cc:337:slice$10351 ($dffe) from module spi_neuron_top (D = \u_graph_engine.u_act_buffer.rd_data, Q = \u_graph_engine.x_mem[1], rval = 8'00000000).
|
|
Adding SRST signal on $auto$ff.cc:337:slice$10354 ($dffe) from module spi_neuron_top (D = \u_graph_engine.u_act_buffer.rd_data, Q = \u_graph_engine.x_mem[2], rval = 8'00000000).
|
|
Adding SRST signal on $auto$ff.cc:337:slice$10357 ($dffe) from module spi_neuron_top (D = \u_graph_engine.u_act_buffer.rd_data, Q = \u_graph_engine.x_mem[3], rval = 8'00000000).
|
|
Adding SRST signal on $auto$ff.cc:337:slice$10360 ($dffe) from module spi_neuron_top (D = \u_graph_engine.u_act_buffer.rd_data, Q = \u_graph_engine.x_mem[4], rval = 8'00000000).
|
|
Adding SRST signal on $auto$ff.cc:337:slice$10363 ($dffe) from module spi_neuron_top (D = \u_graph_engine.u_act_buffer.rd_data, Q = \u_graph_engine.x_mem[5], rval = 8'00000000).
|
|
Adding SRST signal on $auto$ff.cc:337:slice$10366 ($dffe) from module spi_neuron_top (D = \u_graph_engine.u_act_buffer.rd_data, Q = \u_graph_engine.x_mem[6], rval = 8'00000000).
|
|
Adding SRST signal on $auto$ff.cc:337:slice$10369 ($dffe) from module spi_neuron_top (D = \u_graph_engine.u_act_buffer.rd_data, Q = \u_graph_engine.x_mem[7], rval = 8'00000000).
|
|
Adding SRST signal on $auto$ff.cc:337:slice$10372 ($dffe) from module spi_neuron_top (D = \u_graph_engine.u_act_buffer.rd_data, Q = \u_graph_engine.x_mem[8], rval = 8'00000000).
|
|
Adding SRST signal on $auto$ff.cc:337:slice$10375 ($dffe) from module spi_neuron_top (D = \u_graph_engine.u_act_buffer.rd_data, Q = \u_graph_engine.x_mem[9], rval = 8'00000000).
|
|
Adding SRST signal on $auto$ff.cc:337:slice$10378 ($dffe) from module spi_neuron_top (D = \u_graph_engine.u_act_buffer.rd_data, Q = \u_graph_engine.x_mem[10], rval = 8'00000000).
|
|
Adding SRST signal on $auto$ff.cc:337:slice$10381 ($dffe) from module spi_neuron_top (D = \u_graph_engine.u_act_buffer.rd_data, Q = \u_graph_engine.x_mem[11], rval = 8'00000000).
|
|
Adding SRST signal on $auto$ff.cc:337:slice$10384 ($dffe) from module spi_neuron_top (D = \u_graph_engine.u_act_buffer.rd_data, Q = \u_graph_engine.x_mem[12], rval = 8'00000000).
|
|
Adding SRST signal on $auto$ff.cc:337:slice$10387 ($dffe) from module spi_neuron_top (D = \u_graph_engine.u_act_buffer.rd_data, Q = \u_graph_engine.x_mem[13], rval = 8'00000000).
|
|
Adding SRST signal on $auto$ff.cc:337:slice$10390 ($dffe) from module spi_neuron_top (D = \u_graph_engine.u_act_buffer.rd_data, Q = \u_graph_engine.x_mem[14], rval = 8'00000000).
|
|
Adding SRST signal on $auto$ff.cc:337:slice$10393 ($dffe) from module spi_neuron_top (D = \u_graph_engine.u_act_buffer.rd_data, Q = \u_graph_engine.x_mem[15], rval = 8'00000000).
|
|
Adding SRST signal on $auto$ff.cc:337:slice$10396 ($dffe) from module spi_neuron_top (D = \u_graph_engine.u_act_buffer.rd_data, Q = \u_graph_engine.x_mem[16], rval = 8'00000000).
|
|
Adding SRST signal on $auto$ff.cc:337:slice$10399 ($dffe) from module spi_neuron_top (D = \u_graph_engine.u_act_buffer.rd_data, Q = \u_graph_engine.x_mem[17], rval = 8'00000000).
|
|
Adding SRST signal on $auto$ff.cc:337:slice$10402 ($dffe) from module spi_neuron_top (D = \u_graph_engine.u_act_buffer.rd_data, Q = \u_graph_engine.x_mem[18], rval = 8'00000000).
|
|
Adding SRST signal on $auto$ff.cc:337:slice$10405 ($dffe) from module spi_neuron_top (D = \u_graph_engine.u_act_buffer.rd_data, Q = \u_graph_engine.x_mem[19], rval = 8'00000000).
|
|
Adding SRST signal on $auto$ff.cc:337:slice$10408 ($dffe) from module spi_neuron_top (D = \u_graph_engine.u_act_buffer.rd_data, Q = \u_graph_engine.x_mem[20], rval = 8'00000000).
|
|
Adding SRST signal on $auto$ff.cc:337:slice$10411 ($dffe) from module spi_neuron_top (D = \u_graph_engine.u_act_buffer.rd_data, Q = \u_graph_engine.x_mem[21], rval = 8'00000000).
|
|
Adding SRST signal on $auto$ff.cc:337:slice$10414 ($dffe) from module spi_neuron_top (D = \u_graph_engine.u_act_buffer.rd_data, Q = \u_graph_engine.x_mem[22], rval = 8'00000000).
|
|
Adding SRST signal on $auto$ff.cc:337:slice$10417 ($dffe) from module spi_neuron_top (D = \u_graph_engine.u_act_buffer.rd_data, Q = \u_graph_engine.x_mem[23], rval = 8'00000000).
|
|
Adding SRST signal on $auto$ff.cc:337:slice$10420 ($dffe) from module spi_neuron_top (D = \u_graph_engine.u_act_buffer.rd_data, Q = \u_graph_engine.x_mem[24], rval = 8'00000000).
|
|
Adding SRST signal on $auto$ff.cc:337:slice$10423 ($dffe) from module spi_neuron_top (D = \u_graph_engine.u_act_buffer.rd_data, Q = \u_graph_engine.x_mem[25], rval = 8'00000000).
|
|
Adding SRST signal on $auto$ff.cc:337:slice$10426 ($dffe) from module spi_neuron_top (D = \u_graph_engine.u_act_buffer.rd_data, Q = \u_graph_engine.x_mem[26], rval = 8'00000000).
|
|
Adding SRST signal on $auto$ff.cc:337:slice$10429 ($dffe) from module spi_neuron_top (D = \u_graph_engine.u_act_buffer.rd_data, Q = \u_graph_engine.x_mem[27], rval = 8'00000000).
|
|
Adding SRST signal on $auto$ff.cc:337:slice$10432 ($dffe) from module spi_neuron_top (D = \u_graph_engine.u_act_buffer.rd_data, Q = \u_graph_engine.x_mem[28], rval = 8'00000000).
|
|
Adding SRST signal on $auto$ff.cc:337:slice$10435 ($dffe) from module spi_neuron_top (D = \u_graph_engine.u_act_buffer.rd_data, Q = \u_graph_engine.x_mem[29], rval = 8'00000000).
|
|
Adding SRST signal on $auto$ff.cc:337:slice$10438 ($dffe) from module spi_neuron_top (D = \u_graph_engine.u_act_buffer.rd_data, Q = \u_graph_engine.x_mem[30], rval = 8'00000000).
|
|
Adding SRST signal on $auto$ff.cc:337:slice$10441 ($dffe) from module spi_neuron_top (D = \u_graph_engine.u_act_buffer.rd_data, Q = \u_graph_engine.x_mem[31], rval = 8'00000000).
|
|
Setting constant 0-bit at position 0 on $auto$ff.cc:337:slice$6922 ($sdffe) from module spi_neuron_top.
|
|
|
|
17.32.21. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \spi_neuron_top..
|
|
Removed 64 unused cells and 160 unused wires.
|
|
<suppressed ~65 debug messages>
|
|
|
|
17.32.22. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module spi_neuron_top.
|
|
|
|
17.32.23. Rerunning OPT passes. (Maybe there is more to do..)
|
|
|
|
17.32.24. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \spi_neuron_top..
|
|
Creating internal representation of mux trees.
|
|
Evaluating internal representation of mux trees.
|
|
Analyzing evaluation results.
|
|
Removed 0 multiplexer ports.
|
|
<suppressed ~292 debug messages>
|
|
|
|
17.32.25. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \spi_neuron_top.
|
|
Performed a total of 0 changes.
|
|
|
|
17.32.26. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\spi_neuron_top'.
|
|
Computing hashes of 1510 cells of `\spi_neuron_top'.
|
|
Finding duplicate cells in `\spi_neuron_top'.
|
|
Removed a total of 0 cells.
|
|
|
|
17.32.27. Executing OPT_DFF pass (perform DFF optimizations).
|
|
|
|
17.32.28. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \spi_neuron_top..
|
|
|
|
17.32.29. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module spi_neuron_top.
|
|
|
|
17.32.30. Finished fast OPT passes. (There is nothing left to do.)
|
|
|
|
17.33. Executing TECHMAP pass (map to technology primitives).
|
|
|
|
17.33.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/techmap.v
|
|
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/techmap.v' to AST representation.
|
|
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
|
|
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
|
|
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
|
|
Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
|
|
Generating RTLIL representation for module `\_90_simplemap_various'.
|
|
Generating RTLIL representation for module `\_90_simplemap_registers'.
|
|
Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
|
|
Generating RTLIL representation for module `\_90_shift_shiftx'.
|
|
Generating RTLIL representation for module `\_90_fa'.
|
|
Generating RTLIL representation for module `\_90_lcu_brent_kung'.
|
|
Generating RTLIL representation for module `\_90_alu'.
|
|
Generating RTLIL representation for module `\_90_macc'.
|
|
Generating RTLIL representation for module `\_90_alumacc'.
|
|
Generating RTLIL representation for module `$__div_mod_u'.
|
|
Generating RTLIL representation for module `$__div_mod_trunc'.
|
|
Generating RTLIL representation for module `\_90_div'.
|
|
Generating RTLIL representation for module `\_90_mod'.
|
|
Generating RTLIL representation for module `$__div_mod_floor'.
|
|
Generating RTLIL representation for module `\_90_divfloor'.
|
|
Generating RTLIL representation for module `\_90_modfloor'.
|
|
Generating RTLIL representation for module `\_90_pow'.
|
|
Generating RTLIL representation for module `\_90_demux'.
|
|
Generating RTLIL representation for module `\_90_lut'.
|
|
Generating RTLIL representation for module `$connect'.
|
|
Generating RTLIL representation for module `$input_port'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
17.33.2. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v
|
|
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v' to AST representation.
|
|
Generating RTLIL representation for module `\_80_ccu2c_alu'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
17.33.3. Continuing TECHMAP pass.
|
|
Using extmapper simplemap for cells of type $sdffce.
|
|
Using extmapper simplemap for cells of type $dffe.
|
|
Using extmapper simplemap for cells of type $reduce_bool.
|
|
Using extmapper simplemap for cells of type $dff.
|
|
Using extmapper simplemap for cells of type $sdff.
|
|
Using extmapper simplemap for cells of type $reduce_or.
|
|
Using extmapper simplemap for cells of type $not.
|
|
Using extmapper simplemap for cells of type $reduce_and.
|
|
Using extmapper simplemap for cells of type $sdffe.
|
|
Using extmapper simplemap for cells of type $ne.
|
|
Using extmapper simplemap for cells of type $and.
|
|
Using template $paramod$b18e16801adf491a64caa0542270798e5d4ac6b6\_80_ccu2c_alu for cells of type $alu.
|
|
Using template $paramod$fc972a7a46956c1788f3cb5257b53c8f1df2d0cc\_90_alu for cells of type $alu.
|
|
Using extmapper simplemap for cells of type $mux.
|
|
Using extmapper simplemap for cells of type $eq.
|
|
Using template $paramod$2470b7ea32c975a55c3ab8b283381b72d09e16d3\_80_ccu2c_alu for cells of type $alu.
|
|
Using template $paramod$2653f68ddb8eab7b1907b4a20767b72a824a7a36\_80_ccu2c_alu for cells of type $alu.
|
|
Using template $paramod$8fdcfe020be5e507ba05385ffd706e02b549d39d\_80_ccu2c_alu for cells of type $alu.
|
|
Using template $paramod$8742280fdebca84e1c87f2a86ed84f62d558f4cc\_90_alu for cells of type $alu.
|
|
Using template $paramod$32a7b7b86c07519b7537abc18e96f0331f97914d\_90_alu for cells of type $alu.
|
|
Using template $paramod$7945baf943a7eaf2bd95deee6e66976c53d43b8d\_80_ccu2c_alu for cells of type $alu.
|
|
Using template $paramod$c3cd1564c35d873179656addd6052d7ea8b6d991\_80_ccu2c_alu for cells of type $alu.
|
|
Using template $paramod$403a3c2fa431a154c52a6a5429d7a6260b5d144f\_80_ccu2c_alu for cells of type $alu.
|
|
Using template $paramod$36fdbc18fab0758c8553dda57bd33e3f8f3e8765\_80_ccu2c_alu for cells of type $alu.
|
|
Using template $paramod$7bdc7d89ea9376c9c454fd05d9b64ca6288b61c9\_80_ccu2c_alu for cells of type $alu.
|
|
Using template $paramod$bb2d74554e7f3344a65c51a9d0fb34626611aac9\_80_ccu2c_alu for cells of type $alu.
|
|
Using template $paramod$6df0329addda9228fcc2546de2aaf14ad26c98e1\_80_ccu2c_alu for cells of type $alu.
|
|
Using template $paramod$32efbfac1c4dc57230cf86180788fdfd12e3b511\_80_ccu2c_alu for cells of type $alu.
|
|
Using template $paramod$a04dd9d4d8b430140c4ff94b50470fb380fda2a0\_80_ccu2c_alu for cells of type $alu.
|
|
Using template $paramod$175e67c02b86e96b1288b9dc100122520d7240d8\_90_alu for cells of type $alu.
|
|
Using template $paramod$a1665ef28c749ebcdbe9aecd466e644647b56463\_80_ccu2c_alu for cells of type $alu.
|
|
Using template $paramod$2af30114e9bd4ccb04dad757b3f0a8f6bf0615b0\_80_ccu2c_alu for cells of type $alu.
|
|
Using extmapper simplemap for cells of type $or.
|
|
Using template $paramod$3ef7d3dd227da7627a99c5e5a6a4deb817573e39\_90_alu for cells of type $alu.
|
|
Using template $paramod$713617589782cfade849bb573b5c36106c4b708f\_80_ccu2c_alu for cells of type $alu.
|
|
Using extmapper simplemap for cells of type $xor.
|
|
Using template $paramod$5d0bb5be5579f553e9e7790fdead1e778acc7812\_80_ccu2c_alu for cells of type $alu.
|
|
Using template $paramod$6694d39cad831bc5688fe7ffaed39b79bdf33392\_80_ccu2c_alu for cells of type $alu.
|
|
Using extmapper maccmap for cells of type $macc_v2.
|
|
add \u_graph_engine.conn_ptr_acc [22:0] (23 bits, unsigned)
|
|
add \u_graph_engine.edge_byte_idx (2 bits, unsigned)
|
|
add { \u_graph_engine.conn_i 2'00 } (8 bits, unsigned)
|
|
Using extmapper simplemap for cells of type $bmux.
|
|
Using extmapper simplemap for cells of type $logic_not.
|
|
Using extmapper simplemap for cells of type $pmux.
|
|
Using extmapper simplemap for cells of type $tribuf.
|
|
Using extmapper simplemap for cells of type $logic_and.
|
|
Using extmapper simplemap for cells of type $logic_or.
|
|
Using template $paramod$constmap:1c62fa0501c71c523e718f52047352464d16f12e$paramod$a50ae57e8afac966c737391c51ad88342606b747\_90_shift_shiftx for cells of type $shiftx.
|
|
Using extmapper simplemap for cells of type $lut.
|
|
Using template $paramod$448756c9a9dfaa49080ce4b90c6cc182883e181f\_80_ccu2c_alu for cells of type $alu.
|
|
Using extmapper simplemap for cells of type $pos.
|
|
Using template $paramod\_90_fa\WIDTH=32'00000000000000000000000000000001 for cells of type $fa.
|
|
Using template $paramod\_90_lcu_brent_kung\WIDTH=32'00000000000000000000000000000001 for cells of type $lcu.
|
|
Using template $paramod\_90_fa\WIDTH=32'00000000000000000000000000000100 for cells of type $fa.
|
|
Using template $paramod\_90_lcu_brent_kung\WIDTH=32'00000000000000000000000000000100 for cells of type $lcu.
|
|
Using template $paramod\_90_fa\WIDTH=32'00000000000000000000000000000010 for cells of type $fa.
|
|
Using template $paramod\_90_lcu_brent_kung\WIDTH=32'00000000000000000000000000000010 for cells of type $lcu.
|
|
Using template $paramod\_90_fa\WIDTH=32'00000000000000000000000000000011 for cells of type $fa.
|
|
Using template $paramod\_90_lcu_brent_kung\WIDTH=32'00000000000000000000000000000011 for cells of type $lcu.
|
|
No more expansions possible.
|
|
<suppressed ~4926 debug messages>
|
|
|
|
17.34. Executing OPT pass (performing simple optimizations).
|
|
|
|
17.34.1. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module spi_neuron_top.
|
|
<suppressed ~3754 debug messages>
|
|
|
|
17.34.2. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\spi_neuron_top'.
|
|
Computing hashes of 9548 cells of `\spi_neuron_top'.
|
|
Finding duplicate cells in `\spi_neuron_top'.
|
|
Computing hashes of 9027 cells of `\spi_neuron_top'.
|
|
Finding duplicate cells in `\spi_neuron_top'.
|
|
Computing hashes of 8906 cells of `\spi_neuron_top'.
|
|
Finding duplicate cells in `\spi_neuron_top'.
|
|
Computing hashes of 8883 cells of `\spi_neuron_top'.
|
|
Finding duplicate cells in `\spi_neuron_top'.
|
|
Computing hashes of 8877 cells of `\spi_neuron_top'.
|
|
Finding duplicate cells in `\spi_neuron_top'.
|
|
Computing hashes of 8875 cells of `\spi_neuron_top'.
|
|
Finding duplicate cells in `\spi_neuron_top'.
|
|
<suppressed ~2019 debug messages>
|
|
Removed a total of 673 cells.
|
|
|
|
17.34.3. Executing OPT_DFF pass (perform DFF optimizations).
|
|
Adding SRST signal on $auto$ff.cc:337:slice$16140 ($_SDFF_PP0_) from module spi_neuron_top (D = $auto$simplemap.cc:189:logic_reduce$18153, Q = \u_psram_ctrl.dq_oe, rval = 1'0).
|
|
Adding SRST signal on $auto$ff.cc:337:slice$16090 ($_SDFF_PP1_) from module spi_neuron_top (D = $auto$simplemap.cc:189:logic_reduce$18143, Q = \u_psram_ctrl.psram_ub_n, rval = 1'1).
|
|
Adding SRST signal on $auto$ff.cc:337:slice$16089 ($_SDFF_PP1_) from module spi_neuron_top (D = $auto$simplemap.cc:189:logic_reduce$18126, Q = \u_psram_ctrl.psram_lb_n, rval = 1'1).
|
|
Adding SRST signal on $auto$ff.cc:337:slice$16088 ($_SDFF_PP1_) from module spi_neuron_top (D = $auto$simplemap.cc:189:logic_reduce$18109, Q = \u_psram_ctrl.psram_we_n, rval = 1'1).
|
|
Adding SRST signal on $auto$ff.cc:337:slice$16087 ($_SDFF_PP1_) from module spi_neuron_top (D = $auto$simplemap.cc:189:logic_reduce$18098, Q = \u_psram_ctrl.psram_oe_n, rval = 1'1).
|
|
Adding SRST signal on $auto$ff.cc:337:slice$16086 ($_SDFF_PP1_) from module spi_neuron_top (D = $auto$simplemap.cc:189:logic_reduce$18088, Q = \u_psram_ctrl.psram_ce_n, rval = 1'1).
|
|
Adding SRST signal on $auto$ff.cc:337:slice$16083 ($_SDFF_PP0_) from module spi_neuron_top (D = $auto$simplemap.cc:189:logic_reduce$18072, Q = \u_psram_ctrl.mem_ready, rval = 1'0).
|
|
Adding SRST signal on $auto$ff.cc:337:slice$15251 ($_SDFF_PP0_) from module spi_neuron_top (D = $auto$simplemap.cc:189:logic_reduce$18858, Q = \u_neuron_memory.access_req, rval = 1'0).
|
|
Adding SRST signal on $auto$ff.cc:337:slice$14892 ($_SDFF_PP0_) from module spi_neuron_top (D = $auto$simplemap.cc:189:logic_reduce$19462, Q = \u_graph_engine.act_wr_en, rval = 1'0).
|
|
Adding SRST signal on $auto$ff.cc:337:slice$14641 ($_SDFF_PP0_) from module spi_neuron_top (D = $auto$simplemap.cc:189:logic_reduce$19452, Q = \u_graph_engine.done, rval = 1'0).
|
|
Adding SRST signal on $auto$ff.cc:337:slice$14562 ($_SDFF_PP0_) from module spi_neuron_top (D = $auto$simplemap.cc:189:logic_reduce$19472, Q = \u_graph_engine.ram_req, rval = 1'0).
|
|
|
|
17.34.4. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \spi_neuron_top..
|
|
Removed 1635 unused cells and 4265 unused wires.
|
|
<suppressed ~1636 debug messages>
|
|
|
|
17.34.5. Rerunning OPT passes. (Removed registers in this run.)
|
|
|
|
17.34.6. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module spi_neuron_top.
|
|
<suppressed ~2 debug messages>
|
|
|
|
17.34.7. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\spi_neuron_top'.
|
|
Computing hashes of 7260 cells of `\spi_neuron_top'.
|
|
Finding duplicate cells in `\spi_neuron_top'.
|
|
Computing hashes of 7256 cells of `\spi_neuron_top'.
|
|
Finding duplicate cells in `\spi_neuron_top'.
|
|
Computing hashes of 7253 cells of `\spi_neuron_top'.
|
|
Finding duplicate cells in `\spi_neuron_top'.
|
|
<suppressed ~21 debug messages>
|
|
Removed a total of 7 cells.
|
|
|
|
17.34.8. Executing OPT_DFF pass (perform DFF optimizations).
|
|
|
|
17.34.9. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \spi_neuron_top..
|
|
Removed 0 unused cells and 7 unused wires.
|
|
<suppressed ~1 debug messages>
|
|
|
|
17.34.10. Finished fast OPT passes.
|
|
|
|
17.35. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \spi_neuron_top..
|
|
|
|
17.36. Executing DFFLEGALIZE pass (convert FFs to types supported by the target).
|
|
|
|
17.37. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\spi_neuron_top'.
|
|
Computing hashes of 8293 cells of `\spi_neuron_top'.
|
|
Finding duplicate cells in `\spi_neuron_top'.
|
|
Computing hashes of 7806 cells of `\spi_neuron_top'.
|
|
Finding duplicate cells in `\spi_neuron_top'.
|
|
Computing hashes of 7319 cells of `\spi_neuron_top'.
|
|
Finding duplicate cells in `\spi_neuron_top'.
|
|
<suppressed ~2922 debug messages>
|
|
Removed a total of 974 cells.
|
|
|
|
17.38. Executing TECHMAP pass (map to technology primitives).
|
|
|
|
17.38.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v
|
|
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v' to AST representation.
|
|
Generating RTLIL representation for module `$_DFF_N_'.
|
|
Generating RTLIL representation for module `$_DFF_P_'.
|
|
Generating RTLIL representation for module `$_DFFE_NN_'.
|
|
Generating RTLIL representation for module `$_DFFE_PN_'.
|
|
Generating RTLIL representation for module `$_DFFE_NP_'.
|
|
Generating RTLIL representation for module `$_DFFE_PP_'.
|
|
Generating RTLIL representation for module `$_DFF_NP0_'.
|
|
Generating RTLIL representation for module `$_DFF_NP1_'.
|
|
Generating RTLIL representation for module `$_DFF_PP0_'.
|
|
Generating RTLIL representation for module `$_DFF_PP1_'.
|
|
Generating RTLIL representation for module `$_SDFF_NP0_'.
|
|
Generating RTLIL representation for module `$_SDFF_NP1_'.
|
|
Generating RTLIL representation for module `$_SDFF_PP0_'.
|
|
Generating RTLIL representation for module `$_SDFF_PP1_'.
|
|
Generating RTLIL representation for module `$_DFFE_NP0P_'.
|
|
Generating RTLIL representation for module `$_DFFE_NP1P_'.
|
|
Generating RTLIL representation for module `$_DFFE_PP0P_'.
|
|
Generating RTLIL representation for module `$_DFFE_PP1P_'.
|
|
Generating RTLIL representation for module `$_DFFE_NP0N_'.
|
|
Generating RTLIL representation for module `$_DFFE_NP1N_'.
|
|
Generating RTLIL representation for module `$_DFFE_PP0N_'.
|
|
Generating RTLIL representation for module `$_DFFE_PP1N_'.
|
|
Generating RTLIL representation for module `$_SDFFE_NP0P_'.
|
|
Generating RTLIL representation for module `$_SDFFE_NP1P_'.
|
|
Generating RTLIL representation for module `$_SDFFE_PP0P_'.
|
|
Generating RTLIL representation for module `$_SDFFE_PP1P_'.
|
|
Generating RTLIL representation for module `$_SDFFE_NP0N_'.
|
|
Generating RTLIL representation for module `$_SDFFE_NP1N_'.
|
|
Generating RTLIL representation for module `$_SDFFE_PP0N_'.
|
|
Generating RTLIL representation for module `$_SDFFE_PP1N_'.
|
|
Generating RTLIL representation for module `$_ALDFF_NP_'.
|
|
Generating RTLIL representation for module `$_ALDFF_PP_'.
|
|
Generating RTLIL representation for module `$_ALDFFE_NPN_'.
|
|
Generating RTLIL representation for module `$_ALDFFE_NPP_'.
|
|
Generating RTLIL representation for module `$_ALDFFE_PPN_'.
|
|
Generating RTLIL representation for module `$_ALDFFE_PPP_'.
|
|
Generating RTLIL representation for module `\FD1P3AX'.
|
|
Generating RTLIL representation for module `\FD1P3AY'.
|
|
Generating RTLIL representation for module `\FD1P3BX'.
|
|
Generating RTLIL representation for module `\FD1P3DX'.
|
|
Generating RTLIL representation for module `\FD1P3IX'.
|
|
Generating RTLIL representation for module `\FD1P3JX'.
|
|
Generating RTLIL representation for module `\FD1S3AX'.
|
|
Generating RTLIL representation for module `\FD1S3AY'.
|
|
Generating RTLIL representation for module `\FD1S3BX'.
|
|
Generating RTLIL representation for module `\FD1S3DX'.
|
|
Generating RTLIL representation for module `\FD1S3IX'.
|
|
Generating RTLIL representation for module `\FD1S3JX'.
|
|
Generating RTLIL representation for module `\IFS1P3BX'.
|
|
Generating RTLIL representation for module `\IFS1P3DX'.
|
|
Generating RTLIL representation for module `\IFS1P3IX'.
|
|
Generating RTLIL representation for module `\IFS1P3JX'.
|
|
Generating RTLIL representation for module `\OFS1P3BX'.
|
|
Generating RTLIL representation for module `\OFS1P3DX'.
|
|
Generating RTLIL representation for module `\OFS1P3IX'.
|
|
Generating RTLIL representation for module `\OFS1P3JX'.
|
|
Generating RTLIL representation for module `\IB'.
|
|
Generating RTLIL representation for module `\IBPU'.
|
|
Generating RTLIL representation for module `\IBPD'.
|
|
Generating RTLIL representation for module `\OB'.
|
|
Generating RTLIL representation for module `\OBZ'.
|
|
Generating RTLIL representation for module `\OBZPU'.
|
|
Generating RTLIL representation for module `\OBZPD'.
|
|
Generating RTLIL representation for module `\OBCO'.
|
|
Generating RTLIL representation for module `\BB'.
|
|
Generating RTLIL representation for module `\BBPU'.
|
|
Generating RTLIL representation for module `\BBPD'.
|
|
Generating RTLIL representation for module `\ILVDS'.
|
|
Generating RTLIL representation for module `\OLVDS'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
17.38.2. Continuing TECHMAP pass.
|
|
Using template $_SDFF_PP0_ for cells of type $_SDFF_PP0_.
|
|
Using template $_SDFF_PP1_ for cells of type $_SDFF_PP1_.
|
|
Using template $paramod$_DFF_P_\_TECHMAP_WIREINIT_Q_=1'x for cells of type $_DFF_P_.
|
|
Using template $_SDFFE_PP0P_ for cells of type $_SDFFE_PP0P_.
|
|
Using template $_SDFFE_PP1P_ for cells of type $_SDFFE_PP1P_.
|
|
Using template $paramod$_DFFE_PP_\_TECHMAP_WIREINIT_Q_=1'x for cells of type $_DFFE_PP_.
|
|
No more expansions possible.
|
|
<suppressed ~2499 debug messages>
|
|
|
|
17.39. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module spi_neuron_top.
|
|
<suppressed ~18 debug messages>
|
|
|
|
17.40. Executing SIMPLEMAP pass (map simple cells to gate primitives).
|
|
|
|
17.41. Executing LATTICE_GSR pass (implement FF init values).
|
|
Handling GSR in spi_neuron_top.
|
|
|
|
17.42. Executing ATTRMVCP pass (move or copy attributes).
|
|
|
|
17.43. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \spi_neuron_top..
|
|
Removed 0 unused cells and 14668 unused wires.
|
|
<suppressed ~1 debug messages>
|
|
|
|
17.44. Executing CHECK pass (checking for obvious problems).
|
|
Checking module spi_neuron_top...
|
|
Found and reported 0 problems.
|
|
|
|
17.45. Executing TECHMAP pass (map to technology primitives).
|
|
|
|
17.45.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/latches_map.v
|
|
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/latches_map.v' to AST representation.
|
|
Generating RTLIL representation for module `$_DLATCH_N_'.
|
|
Generating RTLIL representation for module `$_DLATCH_P_'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
17.45.2. Continuing TECHMAP pass.
|
|
No more expansions possible.
|
|
<suppressed ~4 debug messages>
|
|
|
|
17.46. Executing ABC9 pass.
|
|
|
|
17.46.1. Executing ABC9_OPS pass (helper functions for ABC9).
|
|
|
|
17.46.2. Executing ABC9_OPS pass (helper functions for ABC9).
|
|
|
|
17.46.3. Executing SCC pass (detecting logic loops).
|
|
Found 0 SCCs in module spi_neuron_top.
|
|
Found 0 SCCs.
|
|
|
|
17.46.4. Executing ABC9_OPS pass (helper functions for ABC9).
|
|
|
|
17.46.5. Executing TECHMAP pass (map to technology primitives).
|
|
|
|
17.46.5.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/techmap.v
|
|
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/techmap.v' to AST representation.
|
|
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
|
|
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
|
|
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
|
|
Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
|
|
Generating RTLIL representation for module `\_90_simplemap_various'.
|
|
Generating RTLIL representation for module `\_90_simplemap_registers'.
|
|
Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
|
|
Generating RTLIL representation for module `\_90_shift_shiftx'.
|
|
Generating RTLIL representation for module `\_90_fa'.
|
|
Generating RTLIL representation for module `\_90_lcu_brent_kung'.
|
|
Generating RTLIL representation for module `\_90_alu'.
|
|
Generating RTLIL representation for module `\_90_macc'.
|
|
Generating RTLIL representation for module `\_90_alumacc'.
|
|
Generating RTLIL representation for module `$__div_mod_u'.
|
|
Generating RTLIL representation for module `$__div_mod_trunc'.
|
|
Generating RTLIL representation for module `\_90_div'.
|
|
Generating RTLIL representation for module `\_90_mod'.
|
|
Generating RTLIL representation for module `$__div_mod_floor'.
|
|
Generating RTLIL representation for module `\_90_divfloor'.
|
|
Generating RTLIL representation for module `\_90_modfloor'.
|
|
Generating RTLIL representation for module `\_90_pow'.
|
|
Generating RTLIL representation for module `\_90_demux'.
|
|
Generating RTLIL representation for module `\_90_lut'.
|
|
Generating RTLIL representation for module `$connect'.
|
|
Generating RTLIL representation for module `$input_port'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
17.46.5.2. Continuing TECHMAP pass.
|
|
No more expansions possible.
|
|
<suppressed ~166 debug messages>
|
|
|
|
17.46.6. Executing OPT pass (performing simple optimizations).
|
|
|
|
17.46.6.1. Executing OPT_EXPR pass (perform const folding).
|
|
|
|
17.46.6.2. Executing OPT_MERGE pass (detect identical cells).
|
|
Removed a total of 0 cells.
|
|
|
|
17.46.6.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Removed 0 multiplexer ports.
|
|
|
|
17.46.6.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Performed a total of 0 changes.
|
|
|
|
17.46.6.5. Executing OPT_MERGE pass (detect identical cells).
|
|
Removed a total of 0 cells.
|
|
|
|
17.46.6.6. Executing OPT_DFF pass (perform DFF optimizations).
|
|
|
|
17.46.6.7. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
|
|
17.46.6.8. Executing OPT_EXPR pass (perform const folding).
|
|
|
|
17.46.6.9. Finished fast OPT passes. (There is nothing left to do.)
|
|
|
|
17.46.7. Executing TECHMAP pass (map to technology primitives).
|
|
|
|
17.46.7.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/abc9_map.v
|
|
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/abc9_map.v' to AST representation.
|
|
Successfully finished Verilog frontend.
|
|
|
|
17.46.7.2. Continuing TECHMAP pass.
|
|
No more expansions possible.
|
|
<suppressed ~2 debug messages>
|
|
|
|
17.46.8. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/abc9_model.v
|
|
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/abc9_model.v' to AST representation.
|
|
Generating RTLIL representation for module `$__ABC9_DELAY'.
|
|
Generating RTLIL representation for module `$__ABC9_SCC_BREAKER'.
|
|
Generating RTLIL representation for module `$__DFF_N__$abc9_flop'.
|
|
Generating RTLIL representation for module `$__DFF_P__$abc9_flop'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
17.46.9. Executing ABC9_OPS pass (helper functions for ABC9).
|
|
<suppressed ~2 debug messages>
|
|
|
|
17.46.10. Executing ABC9_OPS pass (helper functions for ABC9).
|
|
|
|
17.46.11. Executing ABC9_OPS pass (helper functions for ABC9).
|
|
<suppressed ~2 debug messages>
|
|
|
|
17.46.12. Executing TECHMAP pass (map to technology primitives).
|
|
|
|
17.46.12.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/techmap.v
|
|
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/techmap.v' to AST representation.
|
|
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
|
|
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
|
|
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
|
|
Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
|
|
Generating RTLIL representation for module `\_90_simplemap_various'.
|
|
Generating RTLIL representation for module `\_90_simplemap_registers'.
|
|
Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
|
|
Generating RTLIL representation for module `\_90_shift_shiftx'.
|
|
Generating RTLIL representation for module `\_90_fa'.
|
|
Generating RTLIL representation for module `\_90_lcu_brent_kung'.
|
|
Generating RTLIL representation for module `\_90_alu'.
|
|
Generating RTLIL representation for module `\_90_macc'.
|
|
Generating RTLIL representation for module `\_90_alumacc'.
|
|
Generating RTLIL representation for module `$__div_mod_u'.
|
|
Generating RTLIL representation for module `$__div_mod_trunc'.
|
|
Generating RTLIL representation for module `\_90_div'.
|
|
Generating RTLIL representation for module `\_90_mod'.
|
|
Generating RTLIL representation for module `$__div_mod_floor'.
|
|
Generating RTLIL representation for module `\_90_divfloor'.
|
|
Generating RTLIL representation for module `\_90_modfloor'.
|
|
Generating RTLIL representation for module `\_90_pow'.
|
|
Generating RTLIL representation for module `\_90_demux'.
|
|
Generating RTLIL representation for module `\_90_lut'.
|
|
Generating RTLIL representation for module `$connect'.
|
|
Generating RTLIL representation for module `$input_port'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
17.46.12.2. Continuing TECHMAP pass.
|
|
Using template $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C for cells of type $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C.
|
|
Using extmapper simplemap for cells of type $or.
|
|
Using extmapper simplemap for cells of type $and.
|
|
Using extmapper simplemap for cells of type $not.
|
|
Using extmapper simplemap for cells of type $xor.
|
|
Using template $paramod\LUT2\INIT=4'1010 for cells of type LUT2.
|
|
Using template $paramod\LUT4\INIT=16'1001011010101010 for cells of type LUT4.
|
|
Using extmapper simplemap for cells of type $mux.
|
|
No more expansions possible.
|
|
<suppressed ~205 debug messages>
|
|
|
|
17.46.13. Executing OPT pass (performing simple optimizations).
|
|
|
|
17.46.13.1. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module spi_neuron_top.
|
|
<suppressed ~18 debug messages>
|
|
|
|
17.46.13.2. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\spi_neuron_top'.
|
|
Computing hashes of 59 cells of `\spi_neuron_top'.
|
|
Finding duplicate cells in `\spi_neuron_top'.
|
|
Computing hashes of 57 cells of `\spi_neuron_top'.
|
|
Finding duplicate cells in `\spi_neuron_top'.
|
|
<suppressed ~6 debug messages>
|
|
Removed a total of 2 cells.
|
|
|
|
17.46.13.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \spi_neuron_top..
|
|
Creating internal representation of mux trees.
|
|
No muxes found in this module.
|
|
Removed 0 multiplexer ports.
|
|
|
|
17.46.13.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \spi_neuron_top.
|
|
Performed a total of 0 changes.
|
|
|
|
17.46.13.5. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\spi_neuron_top'.
|
|
Computing hashes of 57 cells of `\spi_neuron_top'.
|
|
Finding duplicate cells in `\spi_neuron_top'.
|
|
Removed a total of 0 cells.
|
|
|
|
17.46.13.6. Executing OPT_DFF pass (perform DFF optimizations).
|
|
|
|
17.46.13.7. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \spi_neuron_top..
|
|
Removed 0 unused cells and 55 unused wires.
|
|
<suppressed ~1 debug messages>
|
|
|
|
17.46.13.8. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module spi_neuron_top.
|
|
|
|
17.46.13.9. Rerunning OPT passes. (Maybe there is more to do..)
|
|
|
|
17.46.13.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \spi_neuron_top..
|
|
Creating internal representation of mux trees.
|
|
No muxes found in this module.
|
|
Removed 0 multiplexer ports.
|
|
|
|
17.46.13.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \spi_neuron_top.
|
|
Performed a total of 0 changes.
|
|
|
|
17.46.13.12. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\spi_neuron_top'.
|
|
Computing hashes of 57 cells of `\spi_neuron_top'.
|
|
Finding duplicate cells in `\spi_neuron_top'.
|
|
Removed a total of 0 cells.
|
|
|
|
17.46.13.13. Executing OPT_DFF pass (perform DFF optimizations).
|
|
|
|
17.46.13.14. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \spi_neuron_top..
|
|
|
|
17.46.13.15. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module spi_neuron_top.
|
|
|
|
17.46.13.16. Finished fast OPT passes. (There is nothing left to do.)
|
|
|
|
17.46.14. Executing AIGMAP pass (map logic to AIG).
|
|
Module spi_neuron_top: replaced 18 cells with 120 new cells, skipped 39 cells.
|
|
replaced 3 cell types:
|
|
14 $_MUX_
|
|
2 $_OR_
|
|
2 $_XOR_
|
|
not replaced 3 cell types:
|
|
4 $_AND_
|
|
4 $_NOT_
|
|
31 $specify2
|
|
|
|
17.46.15. Executing AIGMAP pass (map logic to AIG).
|
|
Module spi_neuron_top: replaced 2998 cells with 18268 new cells, skipped 4305 cells.
|
|
replaced 4 cell types:
|
|
1959 $_MUX_
|
|
33 $_ORNOT_
|
|
862 $_OR_
|
|
144 $_XOR_
|
|
not replaced 8 cell types:
|
|
978 $_AND_
|
|
485 $_NOT_
|
|
16 $_TBUF_
|
|
19 $scopeinfo
|
|
2406 TRELLIS_FF
|
|
2 DP16KD
|
|
4 MULT18X18D
|
|
395 $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C
|
|
|
|
17.46.15.1. Executing ABC9_OPS pass (helper functions for ABC9).
|
|
|
|
17.46.15.2. Executing ABC9_OPS pass (helper functions for ABC9).
|
|
|
|
17.46.15.3. Executing XAIGER backend.
|
|
<suppressed ~11 debug messages>
|
|
Extracted 8182 AND gates and 24631 wires from module `spi_neuron_top' to a netlist network with 2499 inputs and 1429 outputs.
|
|
|
|
17.46.15.4. Executing ABC9_EXE pass (technology mapping using ABC9).
|
|
|
|
17.46.15.5. Executing ABC9.
|
|
Running ABC command: "<yosys-exe-dir>/yosys-abc" -s -f <abc-temp-dir>/abc.script 2>&1
|
|
ABC: ======== ABC command line "source <abc-temp-dir>/abc.script"
|
|
ABC: + read_lut <abc-temp-dir>/input.lut
|
|
ABC: + read_box <abc-temp-dir>/input.box
|
|
ABC: + &read <abc-temp-dir>/input.xaig
|
|
ABC: + &ps
|
|
ABC: <abc-temp-dir>/input : i/o = 2499/ 1429 and = 7458 lev = 21 (1.09) mem = 0.22 MB box = 395 bb = 0
|
|
ABC: Warning: AIG with boxes has internal fanout in 0 complex flops and 4 carries.
|
|
ABC: + &scorr
|
|
ABC: Warning: The network is combinational.
|
|
ABC: + &sweep
|
|
ABC: + &dc2
|
|
ABC: + &dch -f -r
|
|
ABC: + &ps
|
|
ABC: <abc-temp-dir>/input : i/o = 2499/ 1429 and = 10608 lev = 36 (0.91) mem = 0.25 MB ch = 1538 box = 395 bb = 0
|
|
ABC: cst = 0 cls = 1267 lit = 1538 unused = 11487 proof = 0
|
|
ABC: Warning: AIG with boxes has internal fanout in 0 complex flops and 4 carries.
|
|
ABC: + &if -W 300 -v
|
|
ABC: K = 7. Memory (bytes): Truth = 0. Cut = 76. Obj = 156. Set = 780. CutMin = no
|
|
ABC: Node = 10608. Ch = 1267. Total mem = 3.16 MB. Peak cut mem = 0.19 MB.
|
|
ABC: P: Del = 4978.00. Ar = 6386.0. Edge = 8683. Cut = 99719. T = 0.01 sec
|
|
ABC: P: Del = 4978.00. Ar = 6300.0. Edge = 8723. Cut = 99512. T = 0.01 sec
|
|
ABC: P: Del = 4978.00. Ar = 3081.0. Edge = 9770. Cut = 154941. T = 0.02 sec
|
|
ABC: F: Del = 4971.00. Ar = 2614.0. Edge = 8525. Cut = 159575. T = 0.02 sec
|
|
ABC: A: Del = 4971.00. Ar = 2459.0. Edge = 7613. Cut = 156619. T = 0.03 sec
|
|
ABC: A: Del = 4971.00. Ar = 2456.0. Edge = 7614. Cut = 157407. T = 0.03 sec
|
|
ABC: Total time = 0.11 sec
|
|
ABC: + &write -n <abc-temp-dir>/output.aig
|
|
ABC: + &mfs
|
|
ABC: + &ps -l
|
|
ABC: <abc-temp-dir>/input : i/o = 2499/ 1429 and = 6828 lev = 21 (0.97) mem = 0.21 MB box = 391 bb = 0
|
|
ABC: Mapping (K=5) : lut = 2004 edge = 7418 lev = 8 (0.50) levB = 21 mem = 0.10 MB
|
|
ABC: LUT = 2004 : 2=225 11.2 % 3=504 25.1 % 4=919 45.9 % 5=356 17.8 % Ave = 3.70
|
|
ABC: + &write -n <abc-temp-dir>/output.aig
|
|
ABC: + &verify
|
|
ABC: Networks are equivalent. Time = 0.10 sec
|
|
ABC: + time
|
|
ABC: elapse: 0.73 seconds, total: 0.73 seconds
|
|
|
|
17.46.15.6. Executing AIGER frontend.
|
|
<suppressed ~10 debug messages>
|
|
Removed 10780 unused cells and 18907 unused wires.
|
|
|
|
17.46.15.7. Executing ABC_OPS_REINTEGRATE pass (reintegrate ABC mapped design into module).
|
|
ABC RESULTS: $lut cells: 2011
|
|
ABC RESULTS: $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C cells: 391
|
|
ABC RESULTS: input signals: 161
|
|
ABC RESULTS: output signals: 439
|
|
<suppressed ~7860 debug messages>
|
|
Removing temp directory.
|
|
|
|
17.46.16. Executing TECHMAP pass (map to technology primitives).
|
|
|
|
17.46.16.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/abc9_unmap.v
|
|
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/abc9_unmap.v' to AST representation.
|
|
Generating RTLIL representation for module `$__DFF_x__$abc9_flop'.
|
|
Generating RTLIL representation for module `$__ABC9_SCC_BREAKER'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
17.46.16.2. Continuing TECHMAP pass.
|
|
Using template $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C for cells of type $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C.
|
|
No more expansions possible.
|
|
<suppressed ~397 debug messages>
|
|
Removed 327 unused cells and 29297 unused wires.
|
|
|
|
17.47. Executing TECHMAP pass (map to technology primitives).
|
|
|
|
17.47.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v
|
|
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v' to AST representation.
|
|
Generating RTLIL representation for module `$_DFF_N_'.
|
|
Generating RTLIL representation for module `$_DFF_P_'.
|
|
Generating RTLIL representation for module `$_DFFE_NN_'.
|
|
Generating RTLIL representation for module `$_DFFE_PN_'.
|
|
Generating RTLIL representation for module `$_DFFE_NP_'.
|
|
Generating RTLIL representation for module `$_DFFE_PP_'.
|
|
Generating RTLIL representation for module `$_DFF_NP0_'.
|
|
Generating RTLIL representation for module `$_DFF_NP1_'.
|
|
Generating RTLIL representation for module `$_DFF_PP0_'.
|
|
Generating RTLIL representation for module `$_DFF_PP1_'.
|
|
Generating RTLIL representation for module `$_SDFF_NP0_'.
|
|
Generating RTLIL representation for module `$_SDFF_NP1_'.
|
|
Generating RTLIL representation for module `$_SDFF_PP0_'.
|
|
Generating RTLIL representation for module `$_SDFF_PP1_'.
|
|
Generating RTLIL representation for module `$_DFFE_NP0P_'.
|
|
Generating RTLIL representation for module `$_DFFE_NP1P_'.
|
|
Generating RTLIL representation for module `$_DFFE_PP0P_'.
|
|
Generating RTLIL representation for module `$_DFFE_PP1P_'.
|
|
Generating RTLIL representation for module `$_DFFE_NP0N_'.
|
|
Generating RTLIL representation for module `$_DFFE_NP1N_'.
|
|
Generating RTLIL representation for module `$_DFFE_PP0N_'.
|
|
Generating RTLIL representation for module `$_DFFE_PP1N_'.
|
|
Generating RTLIL representation for module `$_SDFFE_NP0P_'.
|
|
Generating RTLIL representation for module `$_SDFFE_NP1P_'.
|
|
Generating RTLIL representation for module `$_SDFFE_PP0P_'.
|
|
Generating RTLIL representation for module `$_SDFFE_PP1P_'.
|
|
Generating RTLIL representation for module `$_SDFFE_NP0N_'.
|
|
Generating RTLIL representation for module `$_SDFFE_NP1N_'.
|
|
Generating RTLIL representation for module `$_SDFFE_PP0N_'.
|
|
Generating RTLIL representation for module `$_SDFFE_PP1N_'.
|
|
Generating RTLIL representation for module `$_ALDFF_NP_'.
|
|
Generating RTLIL representation for module `$_ALDFF_PP_'.
|
|
Generating RTLIL representation for module `$_ALDFFE_NPN_'.
|
|
Generating RTLIL representation for module `$_ALDFFE_NPP_'.
|
|
Generating RTLIL representation for module `$_ALDFFE_PPN_'.
|
|
Generating RTLIL representation for module `$_ALDFFE_PPP_'.
|
|
Generating RTLIL representation for module `\FD1P3AX'.
|
|
Generating RTLIL representation for module `\FD1P3AY'.
|
|
Generating RTLIL representation for module `\FD1P3BX'.
|
|
Generating RTLIL representation for module `\FD1P3DX'.
|
|
Generating RTLIL representation for module `\FD1P3IX'.
|
|
Generating RTLIL representation for module `\FD1P3JX'.
|
|
Generating RTLIL representation for module `\FD1S3AX'.
|
|
Generating RTLIL representation for module `\FD1S3AY'.
|
|
Generating RTLIL representation for module `\FD1S3BX'.
|
|
Generating RTLIL representation for module `\FD1S3DX'.
|
|
Generating RTLIL representation for module `\FD1S3IX'.
|
|
Generating RTLIL representation for module `\FD1S3JX'.
|
|
Generating RTLIL representation for module `\IFS1P3BX'.
|
|
Generating RTLIL representation for module `\IFS1P3DX'.
|
|
Generating RTLIL representation for module `\IFS1P3IX'.
|
|
Generating RTLIL representation for module `\IFS1P3JX'.
|
|
Generating RTLIL representation for module `\OFS1P3BX'.
|
|
Generating RTLIL representation for module `\OFS1P3DX'.
|
|
Generating RTLIL representation for module `\OFS1P3IX'.
|
|
Generating RTLIL representation for module `\OFS1P3JX'.
|
|
Generating RTLIL representation for module `\IB'.
|
|
Generating RTLIL representation for module `\IBPU'.
|
|
Generating RTLIL representation for module `\IBPD'.
|
|
Generating RTLIL representation for module `\OB'.
|
|
Generating RTLIL representation for module `\OBZ'.
|
|
Generating RTLIL representation for module `\OBZPU'.
|
|
Generating RTLIL representation for module `\OBZPD'.
|
|
Generating RTLIL representation for module `\OBCO'.
|
|
Generating RTLIL representation for module `\BB'.
|
|
Generating RTLIL representation for module `\BBPU'.
|
|
Generating RTLIL representation for module `\BBPD'.
|
|
Generating RTLIL representation for module `\ILVDS'.
|
|
Generating RTLIL representation for module `\OLVDS'.
|
|
Generating RTLIL representation for module `$lut'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
17.47.2. Continuing TECHMAP pass.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10101100 for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0001 for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0100 for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1000 for cells of type $lut.
|
|
Using template $paramod$8512f4fb47fa9596f76cdbe5b407a5b54df368e7$lut for cells of type $lut.
|
|
Using template $paramod$df196ed0a1da5c4a58c5e08a1dac304fd3fccaab$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10111000 for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01100000 for cells of type $lut.
|
|
Using template $paramod$c962292e904af64537e3818de80ba8dbc5e0c017$lut for cells of type $lut.
|
|
Using template $paramod$23b135911b7c14b5b19b5329e5903bcf58b44188$lut for cells of type $lut.
|
|
Using template $paramod$53ce561f80f32d4298a3beadc88b6c5c78293221$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000001 for cells of type $lut.
|
|
Using template $paramod$873c285bdccf0ac2b60d2304ea5cd14bf211d2a6$lut for cells of type $lut.
|
|
Using template $paramod$fbeae4d13c6561566bb87c819d405873ec370e64$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11001010 for cells of type $lut.
|
|
Using template $paramod$2014354416722209de7d48370ab008bc2278a034$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01101010 for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1001 for cells of type $lut.
|
|
Using template $paramod$69cd07689187c617289e4eda75b267345c09f795$lut for cells of type $lut.
|
|
Using template $paramod$2c6f13368cb0449ec939549bc6cfaba2c2c9c11f$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11100100 for cells of type $lut.
|
|
Using template $paramod$cf52221ef2d451442dd7d72d5c8ad598e89310e9$lut for cells of type $lut.
|
|
Using template $paramod$a47d3f6fd9a7aebdb1b556bc977da3380a17c8cf$lut for cells of type $lut.
|
|
Using template $paramod$a59854b679c443f21a6748ea460109b8241cb007$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11100010 for cells of type $lut.
|
|
Using template $paramod$fa45f28daf300aaa781ee4b9baa5ce968b1d8c66$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1110 for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0010 for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11101010 for cells of type $lut.
|
|
Using template $paramod$6e238df02989b317f10820a22773676e71120644$lut for cells of type $lut.
|
|
Using template $paramod$658b9ed803f0d3d335616d3858b53e0a2522f1e8$lut for cells of type $lut.
|
|
Using template $paramod$eba7de026ff587370e320127e266317dae097a89$lut for cells of type $lut.
|
|
Using template $paramod$6d6beead1425af15cf78b27fd9b11b41b5d4bce8$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11110010 for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11100000 for cells of type $lut.
|
|
Using template $paramod$722bfd9af0ae56ca9d1d12a221cb5ede16461f26$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1101 for cells of type $lut.
|
|
Using template $paramod$a76326805bbb30a33bf46239f93b537676c24ad2$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10101011 for cells of type $lut.
|
|
Using template $paramod$fee012b92df74541b277e340e6596737f818902d$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0111 for cells of type $lut.
|
|
Using template $paramod$101238f3d8d49ab12a9b49a2f01cd503b26e9c61$lut for cells of type $lut.
|
|
Using template $paramod$85b779ce5ab505dbf25e5e046fb43ca2b76b878b$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00010000 for cells of type $lut.
|
|
Using template $paramod$9bdc414229f06e785dc8fd97a243faa9336e164a$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01010001 for cells of type $lut.
|
|
Using template $paramod$b89c522b7f70adaee1a35d80e932f38159b6a445$lut for cells of type $lut.
|
|
Using template $paramod$f3b603d1450c2c61ce732232fcb5fe1f2884aa83$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11011100 for cells of type $lut.
|
|
Using template $paramod$f58e0d90afc57a738914697b6a4a7319b30d7e7e$lut for cells of type $lut.
|
|
Using template $paramod$80bc945f6d438f16387422ec284dc12b4bb4e68f$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00001000 for cells of type $lut.
|
|
Using template $paramod$965f8f2fa1a796a6c51222eabb50fbd26e97d98b$lut for cells of type $lut.
|
|
Using template $paramod$d74f27ecdfbf562ce0161f824cec9778b19ee549$lut for cells of type $lut.
|
|
Using template $paramod$6036593eb6f7d1618fdaa514fe11339bec63f433$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000100 for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10000000 for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00100000 for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1011 for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11111110 for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10111010 for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000010 for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11110001 for cells of type $lut.
|
|
Using template $paramod$0d3ac82cf5b8a192d5ff4c23e3143360366ae882$lut for cells of type $lut.
|
|
Using template $paramod$f8f63b209b7230e81958663ff24fef1613156af7$lut for cells of type $lut.
|
|
Using template $paramod$ffc80aea4aa44f0166b2d4713ba5912f56e92991$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11111101 for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11110111 for cells of type $lut.
|
|
Using template $paramod$62fb31b1a783eac472264027492b859f55ad08ed$lut for cells of type $lut.
|
|
Using template $paramod$86d1a43c2f1d620ff2cef866448dd1258c868fad$lut for cells of type $lut.
|
|
Using template $paramod$59f2a3e232df3029c8bc36978b9bbe72a71dfb5a$lut for cells of type $lut.
|
|
Using template $paramod$32ccf65669c41e1e3bce1f16051f6d60ad96a2a0$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10010000 for cells of type $lut.
|
|
Using template $paramod$571404c0889eaf57f492cb5e37f8acb5df5852f9$lut for cells of type $lut.
|
|
Using template $paramod$1bf62ab10e48d71d6497bccacf5c70420c470fe9$lut for cells of type $lut.
|
|
Using template $paramod$1a36cdd01c31a8831aa99b9e16c9846e7b0b4244$lut for cells of type $lut.
|
|
Using template $paramod$4d9437f28ee827cf4006287c53ecaa1266100fca$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11110100 for cells of type $lut.
|
|
Using template $paramod$1d37fad81d5c3a064596f39fb11fa0c240200089$lut for cells of type $lut.
|
|
Using template $paramod$64977556c846e4e7f9ced3a7b7fe9d317e7a6b98$lut for cells of type $lut.
|
|
Using template $paramod$66e741791413519a466d4f44240bc83d3a191818$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00101000 for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10111111 for cells of type $lut.
|
|
Using template $paramod$364c9ffbffac467d60dfec81bba4e18476c15602$lut for cells of type $lut.
|
|
Using template $paramod$7e9df0afb32b76fe5fce0691b8752aca650057fa$lut for cells of type $lut.
|
|
Using template $paramod$f9813472aa48e533b3838c6f2316dc2e78c66111$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11111000 for cells of type $lut.
|
|
Using template $paramod$ad823946862e656cf7f96d606b18b8f972dc6d6c$lut for cells of type $lut.
|
|
Using template $paramod$359fe4e746656bf9c72aecaff84fc7bdea9f55a5$lut for cells of type $lut.
|
|
Using template $paramod$126c776b0f5e5eef0fff11eb6abcf95b4d1189d2$lut for cells of type $lut.
|
|
Using template $paramod$251994398653c4cf8de320f1e306e535d5d2d624$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01000000 for cells of type $lut.
|
|
Using template $paramod$335de092ac977e67dfc6a726b48f2c00b6134ff7$lut for cells of type $lut.
|
|
Using template $paramod$9d2fef5c87ddb9887606fe6f9041bc36b5295b4d$lut for cells of type $lut.
|
|
Using template $paramod$904721edce36ee1a1c3db700015f0abf1d413695$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11000100 for cells of type $lut.
|
|
Using template $paramod$3c64762f56d2dfc9226156923515f492b69b41a9$lut for cells of type $lut.
|
|
Using template $paramod$106b4d877d926f41bd5171be21de0765aec0f89c$lut for cells of type $lut.
|
|
Using template $paramod$b4d86bc56178c155fcd3a08e5c9b9265b7ef420a$lut for cells of type $lut.
|
|
Using template $paramod$ba018320c09b6ecbdc95fc97480f4fe931c8f33f$lut for cells of type $lut.
|
|
Using template $paramod$e3a75b2081c6a7009d08311bf36359c39658675e$lut for cells of type $lut.
|
|
Using template $paramod$7e3d8ac009723e554811ad53385162c0e6a41625$lut for cells of type $lut.
|
|
Using template $paramod$11426815751623871d46bc9f1667ef33eaf7eced$lut for cells of type $lut.
|
|
Using template $paramod$5ce0414f30742591cfbc3ba73903b522793ddcd1$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11111011 for cells of type $lut.
|
|
Using template $paramod$a4bbe892a28ec0471eac4c548ab7ee6abbaf1e36$lut for cells of type $lut.
|
|
Using template $paramod$af4df82eb2070dd4a82d4d6555d1dcbbe415b68a$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11101111 for cells of type $lut.
|
|
Using template $paramod$f4e3e92a4c91ccc38cbcadd03ed0b5769fbf8483$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0110 for cells of type $lut.
|
|
Using template $paramod$1b4942fad7257f60532954b1eb94a6b84f2e5ae3$lut for cells of type $lut.
|
|
Using template $paramod$25f748a39f13f638a0dd44b265e145242e43bbc5$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000111 for cells of type $lut.
|
|
Using template $paramod$fda6887b37f599177ed9cb69271d882b63df7e66$lut for cells of type $lut.
|
|
Using template $paramod$223d1ec0b6718782528b6753a31b303111f0a5a3$lut for cells of type $lut.
|
|
Using template $paramod$c804510587673ea9effea3633f70afe50850f176$lut for cells of type $lut.
|
|
Using template $paramod$b7944410d6d04b6d6c1e394a2577bba154fa7c93$lut for cells of type $lut.
|
|
Using template $paramod$8e44661def013b6bf9fe6f8b049ef2c838d749f9$lut for cells of type $lut.
|
|
Using template $paramod$81df3b5b0c68f16cd64a76012a4213a1b5a86efa$lut for cells of type $lut.
|
|
Using template $paramod$272652f6c6fbe9a75eff76e45cc7e2788835518b$lut for cells of type $lut.
|
|
Using template $paramod$e51a8a571bee774247b38f52d6e85fd62ae52cea$lut for cells of type $lut.
|
|
Using template $paramod$d6ca727e39f31d51d29072e0f33aa09c65e37336$lut for cells of type $lut.
|
|
Using template $paramod$b384dc73c0775b5f6f92a9b94aaf5890a74d4097$lut for cells of type $lut.
|
|
Using template $paramod$1cabbe2f17ea824b0f9f091fd1dc13fff0b3a362$lut for cells of type $lut.
|
|
Using template $paramod$bf60f6ec407ee294958b6566514fc3125ec42258$lut for cells of type $lut.
|
|
Using template $paramod$a5516fc31d1e552de2435200bb732b4d4ad63a9c$lut for cells of type $lut.
|
|
Using template $paramod$9d1915f40715c7f715525567f7dfd63744c26c4a$lut for cells of type $lut.
|
|
Using template $paramod$619b7c9a4d44585e10b42f7fb79b16304cca97c5$lut for cells of type $lut.
|
|
Using template $paramod$237d4069bbce32a2e7cf939c60ef41d72d5dba1d$lut for cells of type $lut.
|
|
Using template $paramod$373d637619c29cb9150902df9528107e5f3b8288$lut for cells of type $lut.
|
|
Using template $paramod$ae847b3caa0d009b4b5d7e5047ef425662ce7a78$lut for cells of type $lut.
|
|
Using template $paramod$517625bf4a7b846fd553901d881a35fcc8afe4c4$lut for cells of type $lut.
|
|
Using template $paramod$e85b6eba0dacefc5f73f8748159b8b9599212afc$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00101111 for cells of type $lut.
|
|
Using template $paramod$5d33cfa6a45c55d19e75fa773f09299628aedc6c$lut for cells of type $lut.
|
|
Using template $paramod$8e7b1ec7df4c8852d827365421a6d41e55bd7752$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11001101 for cells of type $lut.
|
|
Using template $paramod$47a8214374025465e226fa66bee690ff33268a25$lut for cells of type $lut.
|
|
Using template $paramod$edc5a73130589b9210f4bdf92e14bdcacac8945d$lut for cells of type $lut.
|
|
Using template $paramod$e3e4230bb990723642112b292aa705ee0cbad0d4$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11101100 for cells of type $lut.
|
|
Using template $paramod$3718b46f9fc8e7db62b1202aeaec21c3331ed565$lut for cells of type $lut.
|
|
Using template $paramod$cad45b6c9da81941161a13849773fe2ed4bc1c6f$lut for cells of type $lut.
|
|
Using template $paramod$863f41f551a5816159b16156be2ce40a67f3ea1f$lut for cells of type $lut.
|
|
Using template $paramod$f1d91fb944a09c116c3c99b59cca8cee904c96de$lut for cells of type $lut.
|
|
Using template $paramod$72043e0aa7fa64cb454e3c2ca3dbe1636171896a$lut for cells of type $lut.
|
|
Using template $paramod$8c6086e5ec3e9c40cf78aa00b56d8032c461f06e$lut for cells of type $lut.
|
|
Using template $paramod$e5e9da8fed769f971686eed8c5eea50e61f73aaa$lut for cells of type $lut.
|
|
Using template $paramod$19f568890ed784cb1efc3ce1b67eed20a6c54d9a$lut for cells of type $lut.
|
|
Using template $paramod$cdc5bba2585477f1744fd1f869bebc8beb23d707$lut for cells of type $lut.
|
|
Using template $paramod$bb7be8bae5c143932e2a0774e60657333fd7fa30$lut for cells of type $lut.
|
|
Using template $paramod$41326ad8644342a66dfb051d050f2b6fbf15015b$lut for cells of type $lut.
|
|
Using template $paramod$a197ef6f3b51d411ae3e5b42b5d77a606c4fb11a$lut for cells of type $lut.
|
|
Using template $paramod$3b56205e0e57b3ea26d80fc7983017f83663129e$lut for cells of type $lut.
|
|
Using template $paramod$c95600c22d16130655f2a86bbcbf5f6580781063$lut for cells of type $lut.
|
|
Using template $paramod$9a6965d4f53d69e345bd8d48283856520a30225e$lut for cells of type $lut.
|
|
Using template $paramod$e6a488add0b5a2d742e2ae29f62ce7616e04271d$lut for cells of type $lut.
|
|
Using template $paramod$beae4210b922fc9ba2fcc4008a7474b475e38c50$lut for cells of type $lut.
|
|
Using template $paramod$01f38dafe767eff3b774c3e1f729826d7239b804$lut for cells of type $lut.
|
|
Using template $paramod$8a2b1b54a4376a3fb67849a0d1e5a43b738db53a$lut for cells of type $lut.
|
|
Using template $paramod$daac9b1e7bb2ac018f7132a3fbe0026ddd7b1a71$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10001011 for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10000010 for cells of type $lut.
|
|
Using template $paramod$4133fe00eb18442862a284ccc67a95f8194d041c$lut for cells of type $lut.
|
|
Using template $paramod$c9994e2a733aa21e4bfe57075af37a9c5257c791$lut for cells of type $lut.
|
|
Using template $paramod$63adfd7f010aebf4643ba93b2dbe21144284e1e6$lut for cells of type $lut.
|
|
Using template $paramod$66caeb00a39d236782a97659e3bd99621b74681b$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00010011 for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01010100 for cells of type $lut.
|
|
Using template $paramod$e404e4e0a49bc1f265c6a481282b448f97ae52b0$lut for cells of type $lut.
|
|
Using template $paramod$3a75385b1beb239786b9fcdc898b53110e63595f$lut for cells of type $lut.
|
|
Using template $paramod$8702d826849a5d8af6dd5fde2d287a6443f7d076$lut for cells of type $lut.
|
|
Using template $paramod$94ac66a11090dca84889e55fcf03297912a5b7ec$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01001100 for cells of type $lut.
|
|
Using template $paramod$856d39e7e3d7f684f4fddef2de69af230893be00$lut for cells of type $lut.
|
|
Using template $paramod$9d12c15405e25608417ce779d7fe1b86619365f9$lut for cells of type $lut.
|
|
Using template $paramod$c68110307ed3a83d1f1d050a34218c458bce2221$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00001110 for cells of type $lut.
|
|
Using template $paramod$45d35c067ded9854bad436d064758afc38659286$lut for cells of type $lut.
|
|
Using template $paramod$b1c1fcc81573437ec158d7c629938862148f7151$lut for cells of type $lut.
|
|
Using template $paramod$d2b5e7b5429639878c0a614cf001753581eebd9c$lut for cells of type $lut.
|
|
Using template $paramod$992bdc10cff2c6edd722994f0e1044bc863f79f7$lut for cells of type $lut.
|
|
Using template $paramod$b86b68a00733dbecb31d58a14a13683475a2002a$lut for cells of type $lut.
|
|
Using template $paramod$43779580bfffd5d5a9f321249a174febf1dac288$lut for cells of type $lut.
|
|
Using template $paramod$eced46750b43aa9efabd63e9db30cd976a863157$lut for cells of type $lut.
|
|
Using template $paramod$b4410865e8124402796f9dfbf73ef8d279fdbd08$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11011000 for cells of type $lut.
|
|
Using template $paramod$a9fc6e1212e2c97f661279eebf7fa89d410eb14a$lut for cells of type $lut.
|
|
Using template $paramod$94d2f1f461ef911482e15efdba185521de732c99$lut for cells of type $lut.
|
|
Using template $paramod$153c6cdaaddbc43e6ef3facd06aa851de33910ae$lut for cells of type $lut.
|
|
Using template $paramod$29442795ef2e10dd90e3826e90a6d7a832893bba$lut for cells of type $lut.
|
|
Using template $paramod$478e33feeac3aa53ff57d491aada044b8aedceae$lut for cells of type $lut.
|
|
Using template $paramod$446d5374f1a9a50c11eb107999155fc0219be593$lut for cells of type $lut.
|
|
Using template $paramod$01efcb95fbb77a39361bfe0d84053cbb9d694b4d$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11000101 for cells of type $lut.
|
|
Using template $paramod$0a4d85497e20c50068555dd5ad9ad3a7952cab73$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00001011 for cells of type $lut.
|
|
Using template $paramod$001d9634602f00137f774620efde4c651c7a59ca$lut for cells of type $lut.
|
|
Using template $paramod$b13d7f338373f4c4f4ec6906c2249b9fcaf9e733$lut for cells of type $lut.
|
|
Using template $paramod$3830fbfbec2ed4d6e3e957e17e4fca97b7adef1f$lut for cells of type $lut.
|
|
Using template $paramod$af763bca85949884aefa417266a961f9c91132de$lut for cells of type $lut.
|
|
Using template $paramod$e3232e0a90c8340ac10328f8e4e3ccd56fa7779b$lut for cells of type $lut.
|
|
Using template $paramod$d21d214a5aa271f2d9da3f90f22432c0ecee130f$lut for cells of type $lut.
|
|
Using template $paramod$d575d3554e876f643193272ee6813447059f103f$lut for cells of type $lut.
|
|
Using template $paramod$23764ef6208c0eba4ffe4afe904943e1ed80e8a4$lut for cells of type $lut.
|
|
Using template $paramod$053427f7f5ea07d59a8194fc808f0dbdb8dee48b$lut for cells of type $lut.
|
|
Using template $paramod$f09f8b6cd4e5ceeddd06811b7669f05eb21b8588$lut for cells of type $lut.
|
|
Using template $paramod$ab8bb87959c5d7cfa27886cee1355b38e054a61a$lut for cells of type $lut.
|
|
Using template $paramod$bab3258ad21cb83a958fbc51f2a3a88704f4353a$lut for cells of type $lut.
|
|
Using template $paramod$a03ef989f8f4e1878ce2f5c4e0e3d2dfb54307ef$lut for cells of type $lut.
|
|
Using template $paramod$4d7f17f71543a1e7fc1835bd79c4827a43f2e844$lut for cells of type $lut.
|
|
Using template $paramod$636489ee6fd9daecee952e374b74ebd4427c62b5$lut for cells of type $lut.
|
|
Using template $paramod$d4540f9e5df3797fdf6eef46613f626a85f23f59$lut for cells of type $lut.
|
|
Using template $paramod$6d5ed6b0f166a223a987cdae0f9a10556ce66e78$lut for cells of type $lut.
|
|
Using template $paramod$e484b1e0bd351ba5af34f5fd66a8e850cc5b8335$lut for cells of type $lut.
|
|
Using template $paramod$9085b12d8ba976889f5f19665d793e2ee93c26a6$lut for cells of type $lut.
|
|
Using template $paramod$8a77a4b825e7cd0e2a0cbe1bb8ec99794d7f5906$lut for cells of type $lut.
|
|
Using template $paramod$52adc4306ced619ca2f6304c7a7bbf71ea42dfec$lut for cells of type $lut.
|
|
Using template $paramod$0fa351d24d2713ce0a93e46f5deedd65d95d22b8$lut for cells of type $lut.
|
|
Using template $paramod$477da4277c03c2ef33b36398805e65ce04b52e70$lut for cells of type $lut.
|
|
Using template $paramod$4658fedcd7ebe2858c93f54b88221dcf68c6bb6c$lut for cells of type $lut.
|
|
Using template $paramod$0cfa02b8e619bfc1aba4a45bcc0909421d0ed179$lut for cells of type $lut.
|
|
Using template $paramod$6e1e2bf7f29cfe416c0ceb4dc5c676edd2a3b996$lut for cells of type $lut.
|
|
Using template $paramod$3fd3cd243a8b2f71b0ffe04bdaebf6ad83bcc78e$lut for cells of type $lut.
|
|
Using template $paramod$085ac6daadd555b0f8cf8f603c7849f876be6cbc$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01001110 for cells of type $lut.
|
|
Using template $paramod$c28a8b7ce0535d090c4cfb52e9c74affd52b110c$lut for cells of type $lut.
|
|
Using template $paramod$ec81262755b5faeae9efcdd7371cb9491a86822d$lut for cells of type $lut.
|
|
Using template $paramod$a4404e742e43b8bf8bde71df8b64cbe0c6ba02bd$lut for cells of type $lut.
|
|
Using template $paramod$7aa8140c7d6de3160b21e7ff84e0f93f69f7fcc6$lut for cells of type $lut.
|
|
Using template $paramod$b93d1ea7a612a32c185108f67a153d44ffb9aac2$lut for cells of type $lut.
|
|
Using template $paramod$4be3a821fb2284ae092558dd891a9ab902259ece$lut for cells of type $lut.
|
|
Using template $paramod$afceeb21a88aad210a7a4582fbc4377c30be6ab4$lut for cells of type $lut.
|
|
Using template $paramod$64c98a93c00f2932cdb01ce29e3a216b58ad51fe$lut for cells of type $lut.
|
|
Using template $paramod$085cb83d0db09780ae5aa544a0f286ba9445143f$lut for cells of type $lut.
|
|
Using template $paramod$fdbc1565cc0339618c56447407c383a651685ec1$lut for cells of type $lut.
|
|
Using template $paramod$7694df82e9546b70eb54723c5a4cb0e31fa58da9$lut for cells of type $lut.
|
|
Using template $paramod$5e9374f44a27c3f8a1c38af244ec43ceb4fb8d4f$lut for cells of type $lut.
|
|
Using template $paramod$8adf7fbd410d2cc654c288d5be5f7508ee8809b0$lut for cells of type $lut.
|
|
Using template $paramod$e5477ee47846ce208224b9029657ffd8771566cb$lut for cells of type $lut.
|
|
Using template $paramod$7570309fe7168df91480992af97b4a58b43668e2$lut for cells of type $lut.
|
|
Using template $paramod$210534b73e432a1d89abd2ae048c31c7f92e6092$lut for cells of type $lut.
|
|
Using template $paramod$88a379586ab99d22384fb6ffdcafb4a7aae8da78$lut for cells of type $lut.
|
|
Using template $paramod$25778dc227058ce4d08c7139853cde1896fb97bd$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00110001 for cells of type $lut.
|
|
Using template $paramod$ce02e2afa3256c1c2c45460d429171d794707fae$lut for cells of type $lut.
|
|
Using template $paramod$0498819220bb36cfd5ba6facabe8eab892920bd6$lut for cells of type $lut.
|
|
Using template $paramod$709de57d2785ba42cbf79b5b78414e5a87816ad9$lut for cells of type $lut.
|
|
Using template $paramod$f969aefcb5fdd29444244ce17e4806b1ebc6f568$lut for cells of type $lut.
|
|
Using template $paramod$691e5d89fa42ac31086ffa9583f01739cd14cecd$lut for cells of type $lut.
|
|
Using template $paramod$9c20013182155af3d3efdd49fa8397638e437d7d$lut for cells of type $lut.
|
|
Using template $paramod$d7c634c964a868577f926c0690c937ab5b147f6e$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10110000 for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000001\LUT=2'01 for cells of type $lut.
|
|
No more expansions possible.
|
|
<suppressed ~5385 debug messages>
|
|
|
|
17.48. Executing OPT_LUT_INS pass (discard unused LUT inputs).
|
|
Optimizing LUTs in spi_neuron_top.
|
|
Optimizing lut $abc$68353$lut$aiger$o4214.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
|
|
Optimizing lut $abc$68353$lut$aiger$o4874.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
|
|
Optimizing lut $abc$68353$lut$aiger68352$6325.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
|
|
Optimizing lut $abc$68353$lut$aiger68352$10340.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$68353$lut$aiger68352$8409.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$68353$lut$aiger68352$10269.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$68353$lut$aiger68352$8050.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$68353$lut$aiger68352$5931.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$68353$lut$aiger68352$9043.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
|
|
Optimizing lut $abc$68353$lut$aiger68352$8670.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
|
|
Optimizing lut $abc$68353$lut$aiger68352$8190.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
|
|
Optimizing lut $abc$68353$lut$aiger68352$8649.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$68353$lut$aiger68352$6432.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
|
|
Optimizing lut $abc$68353$lut$aiger68352$6003.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
|
|
Optimizing lut $abc$68353$lut$aiger68352$7656.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
|
|
Optimizing lut $abc$68353$lut$aiger68352$8980.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
|
|
Optimizing lut $abc$68353$lut$aiger68352$4468.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$68353$lut$aiger68352$9424.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
|
|
Optimizing lut $abc$68353$lut$aiger68352$8920.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
|
|
Optimizing lut $abc$68353$lut$aiger68352$7006.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$68353$lut$aiger68352$5538.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$68353$lut$aiger68352$4614.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
|
|
Optimizing lut $abc$68353$lut$aiger68352$8135.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$68353$lut$aiger68352$8003.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
|
|
Optimizing lut $abc$68353$lut$aiger68352$8555.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$68353$lut$aiger68352$9338.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
|
|
Optimizing lut $abc$68353$lut$aiger68352$8881.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
|
|
Optimizing lut $abc$68353$lut$aiger68352$7999.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$68353$lut$aiger68352$7511.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
|
|
Optimizing lut $abc$68353$lut$aiger$o4451.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
|
|
Optimizing lut $abc$68353$lut$aiger68352$8125.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$68353$lut$aiger68352$8871.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
|
|
Optimizing lut $abc$68353$lut$aiger68352$9901.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$68353$lut$aiger68352$9307.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$68353$lut$aiger68352$6171.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
|
|
Optimizing lut $abc$68353$lut$aiger68352$8283.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$68353$lut$aiger68352$9825.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
|
|
Optimizing lut $abc$68353$lut$aiger68352$7310.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$68353$lut$aiger68352$8273.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$68353$lut$aiger68352$7979.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$68353$lut$aiger$o4620.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
|
|
Optimizing lut $abc$68353$lut$aiger68352$6857.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$68353$lut$aiger68352$8071.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$68353$lut$aiger68352$9775.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
|
|
Optimizing lut $abc$68353$lut$aiger68352$6231.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
|
|
Optimizing lut $abc$68353$lut$aiger68352$7697.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$68353$lut$aiger$o4664.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
|
|
Optimizing lut $abc$68353$lut$aiger68352$7074.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$68353$lut$aiger68352$7940.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$68353$lut$aiger68352$7877.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
|
|
Optimizing lut $abc$68353$lut$aiger68352$6631.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
|
|
Optimizing lut $abc$68353$lut$aiger68352$4834.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$68555.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$68395.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $abc$68353$lut$aiger68352$3952.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$68353$lut$aiger68352$9694.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$68353$lut$aiger68352$6315.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$68353$lut$aiger$o4214.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$68400.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $abc$68353$lut$aiger$o4182.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
|
|
Optimizing lut $abc$68353$lut$aiger68352$5843.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$68353$lut$aiger$o4326.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
|
|
Optimizing lut $abc$68353$lut$aiger68352$7697.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
|
|
Optimizing lut $abc$68353$lut$aiger$o4326.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$68353$lut$aiger68352$5843.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
|
|
Optimizing lut $abc$68353$lut$aiger68352$6315.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
|
|
Optimizing lut $abc$68353$lut$aiger68352$8231.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$68353$lut$aiger68352$8071.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$68411.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $abc$68353$lut$aiger68352$6325.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$68423.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $abc$68353$lut$aiger68352$5854.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
|
|
Optimizing lut $abc$68353$lut$aiger68352$8231.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$68433.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $abc$68353$lut$aiger68352$9660.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$68353$lut$aiger68352$9660.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$68440.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $abc$68353$lut$aiger68352$5854.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$68353$lut$aiger68352$7458.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$68353$lut$aiger$o4654.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
|
|
Optimizing lut $abc$68353$lut$aiger68352$7436.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$68353$lut$aiger$o4654.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$68353$lut$aiger68352$10429.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$68353$lut$aiger68352$10429.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
|
|
Optimizing lut $abc$68353$lut$aiger68352$5864.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$68451.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $abc$68353$lut$aiger$o3615.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
|
|
Optimizing lut $abc$68353$lut$aiger68352$5864.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
|
|
Optimizing lut $abc$68353$lut$aiger68352$9650.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$68455.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $abc$68353$lut$aiger68352$9650.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
|
|
Optimizing lut $abc$68353$lut$aiger68352$5847.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
|
|
Optimizing lut $abc$68353$lut$aiger$o4874.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$68353$lut$aiger68352$8435.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
|
|
Optimizing lut $abc$68353$lut$aiger68352$4041.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
|
|
Optimizing lut $abc$68353$lut$aiger$o3617.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
|
|
Optimizing lut $abc$68353$lut$aiger68352$8435.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$68353$lut$aiger68352$10404.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$68353$lut$aiger68352$9119.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$68353$lut$aiger68352$9119.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
|
|
Optimizing lut $abc$68353$lut$aiger68352$10404.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$68353$lut$aiger$o4232.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
|
|
Optimizing lut $abc$68353$lut$aiger$o4153.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
|
|
Optimizing lut $abc$68353$lut$aiger68352$9638.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
|
|
Optimizing lut $abc$68353$lut$aiger68352$9638.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$68462.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $abc$68353$lut$aiger68352$8425.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
|
|
Optimizing lut $abc$68353$lut$aiger$o4846.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
|
|
Optimizing lut $abc$68353$lut$aiger68352$7436.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$68353$lut$aiger68352$7374.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$68535.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
|
|
Optimizing lut $abc$68353$lut$aiger$o4528.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
|
|
Optimizing lut $abc$68353$lut$aiger$o4528.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$68353$lut$aiger$o3621.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$68486.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$68470.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$68473.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $abc$68353$lut$aiger68352$8425.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$68353$lut$aiger68352$8709.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
|
|
Optimizing lut $abc$68353$lut$aiger68352$7755.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$68353$lut$aiger68352$8709.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$68353$lut$aiger68352$9606.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$68353$lut$aiger68352$4127.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
|
|
Optimizing lut $abc$68353$lut$aiger68352$4131.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$68353$lut$aiger68352$10340.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
|
|
Optimizing lut $abc$68353$lut$aiger68352$9606.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$68353$lut$aiger$o4282.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$68487.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $abc$68353$lut$aiger$o4331.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
|
|
Optimizing lut $abc$68353$lut$aiger$o4331.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$68353$lut$aiger68352$7642.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
|
|
Optimizing lut $abc$68353$lut$aiger68352$10327.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$68353$lut$aiger68352$10327.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$68492.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$68353$lut$aiger$o4462.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
|
|
Optimizing lut $abc$68353$lut$aiger$o4854.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
|
|
Optimizing lut $abc$68353$lut$aiger$o4854.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$68353$lut$aiger68352$8699.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$68353$lut$aiger68352$5921.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
|
|
Optimizing lut $abc$68353$lut$aiger68352$9076.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$68498.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
|
|
Optimizing lut $abc$68353$lut$aiger$o4168.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$68353$lut$aiger68352$6729.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$68353$lut$aiger$o4846.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$68353$lut$aiger68352$5921.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$68353$lut$aiger68352$9076.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$68353$lut$aiger68352$7944.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
|
|
Optimizing lut $abc$68353$lut$aiger$o3919.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $abc$68353$lut$aiger68352$5931.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
|
|
Optimizing lut $abc$68353$lut$aiger68352$5295.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$68353$lut$aiger68352$10281.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$68353$lut$aiger68352$8689.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$68505.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $abc$68353$lut$aiger68352$8689.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
|
|
Optimizing lut $abc$68353$lut$aiger68352$8409.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
|
|
Optimizing lut $abc$68353$lut$aiger68352$9576.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$68353$lut$aiger68352$9576.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
|
|
Optimizing lut $abc$68353$lut$aiger68352$10281.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$68353$lut$aiger68352$6396.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
|
|
Optimizing lut $abc$68353$lut$aiger68352$10269.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
|
|
Optimizing lut $abc$68353$lut$aiger68352$5942.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
|
|
Optimizing lut $abc$68353$lut$aiger68352$6396.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$68353$lut$aiger68352$8050.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
|
|
Optimizing lut $abc$68353$lut$aiger68352$6729.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
|
|
Optimizing lut $abc$68353$lut$aiger68352$7588.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
|
|
Optimizing lut $abc$68353$lut$aiger68352$5942.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$68353$lut$aiger68352$5952.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$68353$lut$aiger68352$5334.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $abc$68353$lut$aiger68352$5952.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
|
|
Optimizing lut $abc$68353$lut$aiger68352$7374.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$68353$lut$aiger68352$7159.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$68353$lut$aiger68352$9546.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
|
|
Optimizing lut $abc$68353$lut$aiger68352$5935.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
|
|
Optimizing lut $abc$68353$lut$aiger68352$7940.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
|
|
Optimizing lut $abc$68353$lut$aiger68352$9542.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$68353$lut$aiger68352$9542.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
|
|
Optimizing lut $abc$68353$lut$aiger68352$8670.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$68353$lut$aiger68352$9039.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$68353$lut$aiger68352$9039.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
|
|
Optimizing lut $abc$68353$lut$aiger$o3942.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
|
|
Optimizing lut $abc$68353$lut$aiger$o3942.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$68353$lut$aiger68352$6422.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$68353$lut$aiger68352$10216.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$68353$lut$aiger68352$10216.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
|
|
Optimizing lut $abc$68353$lut$aiger68352$9532.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$68353$lut$aiger68352$9532.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
|
|
Optimizing lut $abc$68353$lut$aiger68352$8186.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$68353$lut$aiger68352$8186.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
|
|
Optimizing lut $abc$68353$lut$aiger68352$8660.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$68353$lut$aiger68352$8660.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
|
|
Optimizing lut $abc$68353$lut$aiger68352$6422.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
|
|
Optimizing lut $abc$68353$lut$aiger$o4707.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
|
|
Optimizing lut $abc$68353$lut$aiger$o4707.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$68353$lut$aiger68352$8653.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
|
|
Optimizing lut $abc$68353$lut$aiger68352$4300.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $abc$68353$lut$aiger68352$5387.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
|
|
Optimizing lut $abc$68353$lut$aiger68352$5387.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$68353$lut$aiger68352$10194.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$68353$lut$aiger68352$6432.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$68353$lut$aiger$o3662.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
|
|
Optimizing lut $abc$68353$lut$aiger$o3662.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$68353$lut$aiger68352$10194.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$68353$lut$aiger68352$5993.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$68353$lut$aiger$o3671.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $abc$68353$lut$aiger68352$6733.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
|
|
Optimizing lut $abc$68353$lut$aiger68352$4342.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$68558.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$68537.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
|
|
Optimizing lut $abc$68353$lut$aiger68352$7159.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
|
|
Optimizing lut $abc$68353$lut$aiger68352$7501.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$68353$lut$aiger68352$8649.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$68538.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $abc$68353$lut$aiger$o4815.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
|
|
Optimizing lut $abc$68353$lut$aiger$o4815.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$68353$lut$aiger68352$5993.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
|
|
Optimizing lut $abc$68353$lut$aiger68352$6003.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$68353$lut$aiger68352$5427.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$68353$lut$aiger68352$8376.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
|
|
Optimizing lut $abc$68353$lut$aiger68352$8176.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$68353$lut$aiger68352$7841.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$68353$lut$aiger68352$8176.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
|
|
Optimizing lut $abc$68353$lut$aiger68352$8372.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$68353$lut$aiger68352$9785.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
|
|
Optimizing lut $abc$68353$lut$aiger68352$8372.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
|
|
Optimizing lut $abc$68353$lut$aiger68352$10151.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$68353$lut$aiger68352$5427.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
|
|
Optimizing lut $abc$68353$lut$aiger68352$6996.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
|
|
Optimizing lut $abc$68353$lut$aiger68352$10151.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
|
|
Optimizing lut $abc$68353$lut$aiger68352$6015.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
|
|
Optimizing lut $abc$68353$lut$aiger68352$4403.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $abc$68353$lut$aiger68352$8639.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$68353$lut$aiger68352$8639.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
|
|
Optimizing lut $abc$68353$lut$aiger68352$6015.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$68353$lut$aiger$o4802.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
|
|
Optimizing lut $abc$68353$lut$aiger$o4802.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$68353$lut$aiger68352$9477.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
|
|
Optimizing lut $abc$68353$lut$aiger68352$6025.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
|
|
Optimizing lut $abc$68353$lut$aiger68352$9477.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$68353$lut$aiger$o3716.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $abc$68353$lut$aiger68352$6776.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
|
|
Optimizing lut $abc$68353$lut$aiger68352$6025.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$68353$lut$aiger68352$6996.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$68353$lut$aiger68352$6776.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$68353$lut$aiger68352$9467.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
|
|
Optimizing lut $abc$68353$lut$aiger68352$9467.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$68353$lut$aiger68352$5431.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
|
|
Optimizing lut $abc$68353$lut$aiger68352$4457.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
|
|
Optimizing lut $abc$68353$lut$aiger68352$10109.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$68353$lut$aiger$o4097.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
|
|
Optimizing lut $abc$68353$lut$aiger$o4097.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$68353$lut$aiger68352$8980.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$68353$lut$aiger68352$5472.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
|
|
Optimizing lut $abc$68353$lut$aiger68352$7006.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
|
|
Optimizing lut $abc$68353$lut$aiger68352$10109.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$68353$lut$aiger68352$4457.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$68353$lut$aiger68352$7300.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
|
|
Optimizing lut $abc$68353$lut$aiger68352$4468.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
|
|
Optimizing lut $abc$68353$lut$aiger68352$7458.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$68353$lut$aiger68352$5472.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$68353$lut$aiger68352$8970.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
|
|
Optimizing lut $abc$68353$lut$aiger68352$4479.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
|
|
Optimizing lut $abc$68353$lut$aiger68352$8970.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$68353$lut$aiger68352$7841.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$68353$lut$aiger68352$6063.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$68353$lut$aiger68352$4479.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$68353$lut$aiger68352$4489.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$68353$lut$aiger68352$7241.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
|
|
Optimizing lut $abc$68353$lut$aiger68352$9420.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$68353$lut$aiger68352$4489.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
|
|
Optimizing lut $abc$68353$lut$aiger68352$4472.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
|
|
Optimizing lut $abc$68353$lut$aiger68352$6499.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$68353$lut$aiger68352$6063.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
|
|
Optimizing lut $abc$68353$lut$aiger68352$10068.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$68353$lut$aiger68352$10068.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
|
|
Optimizing lut $abc$68353$lut$aiger68352$7501.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
|
|
Optimizing lut $abc$68353$lut$aiger68352$8601.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$68353$lut$aiger68352$3902.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
|
|
Optimizing lut $abc$68353$lut$aiger68352$7017.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
|
|
Optimizing lut $abc$68353$lut$aiger68352$4539.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$68353$lut$aiger68352$7163.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
|
|
Optimizing lut $abc$68353$lut$aiger68352$9420.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
|
|
Optimizing lut $abc$68353$lut$aiger68352$8601.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$68353$lut$aiger68352$6499.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
|
|
Optimizing lut $abc$68353$lut$aiger68352$4539.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
|
|
Optimizing lut $abc$68353$lut$aiger68352$7584.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
|
|
Optimizing lut $abc$68353$lut$aiger$o4784.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
|
|
Optimizing lut $abc$68353$lut$aiger68352$7300.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$68353$lut$aiger$o4784.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$68353$lut$aiger68352$4550.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
|
|
Optimizing lut $abc$68353$lut$aiger68352$5528.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
|
|
Optimizing lut $abc$68353$lut$aiger68352$4550.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$68353$lut$aiger68352$7017.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$68353$lut$aiger68352$4560.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$68353$lut$aiger68352$6067.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
|
|
Optimizing lut $abc$68353$lut$aiger68352$5528.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$68353$lut$aiger68352$4560.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
|
|
Optimizing lut $abc$68353$lut$aiger68352$4543.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
|
|
Optimizing lut $abc$68353$lut$aiger68352$10020.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$68353$lut$aiger68352$9394.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
|
|
Optimizing lut $abc$68353$lut$aiger68352$9394.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$68353$lut$aiger68352$10020.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$68353$lut$aiger68352$5538.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
|
|
Optimizing lut $abc$68353$lut$aiger68352$8930.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
|
|
Optimizing lut $abc$68353$lut$aiger68352$8930.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$68353$lut$aiger68352$7027.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$68353$lut$aiger68352$7310.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$68591.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
|
|
Optimizing lut $abc$68353$lut$aiger68352$9384.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$68353$lut$aiger68352$8324.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$68353$lut$aiger68352$9384.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
|
|
Optimizing lut $abc$68353$lut$aiger68352$9997.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$68353$lut$aiger68352$9377.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
|
|
Optimizing lut $abc$68353$lut$aiger68352$7511.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$68353$lut$aiger68352$7027.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
|
|
Optimizing lut $abc$68353$lut$aiger68352$9997.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$68353$lut$aiger68352$8920.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$68353$lut$aiger68352$7010.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
|
|
Optimizing lut $abc$68353$lut$aiger68352$7196.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
|
|
Optimizing lut $abc$68353$lut$aiger68352$9373.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$68353$lut$aiger68352$9373.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
|
|
Optimizing lut $abc$68353$lut$aiger68352$4614.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$68353$lut$aiger68352$6503.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
|
|
Optimizing lut $abc$68353$lut$aiger68352$5542.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
|
|
Optimizing lut $abc$68353$lut$aiger68352$8324.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$68353$lut$aiger68352$8139.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
|
|
Optimizing lut $abc$68353$lut$aiger68352$9363.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$68353$lut$aiger68352$9363.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
|
|
Optimizing lut $abc$68353$lut$aiger68352$6826.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$68606.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$68353$lut$aiger$o4769.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
|
|
Optimizing lut $abc$68353$lut$aiger$o4769.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$68353$lut$aiger68352$6826.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$68353$lut$aiger$o4119.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
|
|
Optimizing lut $abc$68353$lut$aiger$o4119.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$68353$lut$aiger68352$8135.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
|
|
Optimizing lut $abc$68353$lut$aiger68352$7642.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$68353$lut$aiger68352$4670.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$68353$lut$aiger68352$8559.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
|
|
Optimizing lut $abc$68353$lut$aiger68352$9947.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$68353$lut$aiger68352$9947.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
|
|
Optimizing lut $abc$68353$lut$aiger68352$4670.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
|
|
Optimizing lut $abc$68353$lut$aiger68352$8555.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
|
|
Optimizing lut $abc$68353$lut$aiger68352$9338.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$68353$lut$aiger68352$9328.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$68353$lut$aiger68352$9328.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
|
|
Optimizing lut $abc$68353$lut$aiger68352$6161.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$68353$lut$aiger68352$8881.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$68353$lut$aiger68352$6567.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$68353$lut$aiger68352$9321.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
|
|
Optimizing lut $abc$68353$lut$aiger68352$7999.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
|
|
Optimizing lut $abc$68353$lut$aiger68352$7321.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
|
|
Optimizing lut $abc$68353$lut$aiger68352$9922.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
|
|
Optimizing lut $abc$68353$lut$aiger68352$9922.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$68353$lut$aiger68352$8545.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$68353$lut$aiger68352$7220.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$68353$lut$aiger68352$8545.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
|
|
Optimizing lut $abc$68353$lut$aiger$o4451.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$68353$lut$aiger68352$6161.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
|
|
Optimizing lut $abc$68353$lut$aiger68352$9317.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$68353$lut$aiger68352$9317.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
|
|
Optimizing lut $abc$68353$lut$aiger68352$6847.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
|
|
Optimizing lut $abc$68353$lut$aiger68352$6171.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$68353$lut$aiger68352$9912.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$68353$lut$aiger68352$9912.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
|
|
Optimizing lut $abc$68353$lut$aiger68352$8125.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
|
|
Optimizing lut $abc$68353$lut$aiger68352$8871.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$68353$lut$aiger68352$9905.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
|
|
Optimizing lut $abc$68353$lut$aiger$o4540.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$68353$lut$aiger68352$6567.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
|
|
Optimizing lut $abc$68353$lut$aiger68352$9901.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
|
|
Optimizing lut $abc$68353$lut$aiger68352$9307.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
|
|
Optimizing lut $abc$68353$lut$aiger68352$6847.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$68353$lut$aiger68352$9891.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$68353$lut$aiger68352$9891.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
|
|
Optimizing lut $abc$68353$lut$aiger68352$7064.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
|
|
Optimizing lut $abc$68353$lut$aiger68352$7321.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$68353$lut$aiger$o4567.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
|
|
Optimizing lut $abc$68353$lut$aiger68352$6857.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
|
|
Optimizing lut $abc$68353$lut$aiger68352$7474.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
|
|
Optimizing lut $abc$68353$lut$aiger$o4567.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$68353$lut$aiger68352$7331.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$68353$lut$aiger$o4747.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
|
|
Optimizing lut $abc$68353$lut$aiger$o4747.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$68353$lut$aiger68352$7415.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
|
|
Optimizing lut $abc$68353$lut$aiger68352$4755.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $abc$68353$lut$aiger68352$5686.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$68353$lut$aiger68352$7220.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
|
|
Optimizing lut $abc$68353$lut$aiger68352$7064.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$68353$lut$aiger68352$5686.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
|
|
Optimizing lut $abc$68353$lut$aiger$o3752.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
|
|
Optimizing lut $abc$68353$lut$aiger68352$6571.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
|
|
Optimizing lut $abc$68353$lut$aiger68352$6868.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
|
|
Optimizing lut $abc$68353$lut$aiger68352$7474.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$68353$lut$aiger68352$9267.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
|
|
Optimizing lut $abc$68353$lut$aiger68352$8283.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
|
|
Optimizing lut $abc$68353$lut$aiger68352$7415.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$68353$lut$aiger68352$9263.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$68639.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $abc$68353$lut$aiger68352$9263.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
|
|
Optimizing lut $abc$68353$lut$aiger68352$5697.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
|
|
Optimizing lut $abc$68353$lut$aiger68352$7331.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
|
|
Optimizing lut $abc$68353$lut$aiger68352$7074.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
|
|
Optimizing lut $abc$68353$lut$aiger68352$6221.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$68353$lut$aiger68352$9835.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
|
|
Optimizing lut $abc$68353$lut$aiger68352$9835.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$68353$lut$aiger68352$8828.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
|
|
Optimizing lut $abc$68353$lut$aiger68352$8828.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$68353$lut$aiger68352$5697.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$68353$lut$aiger68352$7584.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$68353$lut$aiger68352$5707.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$68353$lut$aiger68352$6868.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$68644.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $abc$68353$lut$aiger68352$7765.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
|
|
Optimizing lut $abc$68353$lut$aiger68352$7765.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$68353$lut$aiger68352$5707.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
|
|
Optimizing lut $abc$68353$lut$aiger68352$6221.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
|
|
Optimizing lut $abc$68353$lut$aiger68352$9825.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$68353$lut$aiger68352$7887.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
|
|
Optimizing lut $abc$68353$lut$aiger68352$7887.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$68353$lut$aiger68352$6878.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$68353$lut$aiger68352$5690.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
|
|
Optimizing lut $abc$68353$lut$aiger68352$6231.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$68353$lut$aiger68352$7314.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
|
|
Optimizing lut $abc$68353$lut$aiger68352$8818.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
|
|
Optimizing lut $abc$68353$lut$aiger68352$8818.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$68353$lut$aiger68352$8273.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
|
|
Optimizing lut $abc$68353$lut$aiger$o4470.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
|
|
Optimizing lut $abc$68353$lut$aiger$o4470.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$68353$lut$aiger68352$7979.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
|
|
Optimizing lut $abc$68353$lut$aiger68352$7231.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
|
|
Optimizing lut $abc$68353$lut$aiger$o4620.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$68353$lut$aiger68352$6878.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
|
|
Optimizing lut $abc$68353$lut$aiger68352$6861.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
|
|
Optimizing lut $abc$68353$lut$aiger68352$9233.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$68353$lut$aiger68352$9233.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$68353$lut$aiger68352$8075.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
|
|
Optimizing lut $abc$68353$lut$aiger68352$6621.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$68653.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $abc$68353$lut$aiger68352$4856.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
|
|
Optimizing lut $abc$68353$lut$aiger68352$9785.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$68353$lut$aiger68352$8485.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
|
|
Optimizing lut $abc$68353$lut$aiger68352$6621.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
|
|
Optimizing lut $abc$68353$lut$aiger68352$8481.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$68353$lut$aiger68352$8481.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
|
|
Optimizing lut $abc$68353$lut$aiger68352$9775.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$68353$lut$aiger68352$7755.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
|
|
Optimizing lut $abc$68353$lut$aiger68352$6631.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$68353$lut$aiger68352$8261.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
|
|
Optimizing lut $abc$68353$lut$aiger68352$8261.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$68353$lut$aiger68352$9209.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$68353$lut$aiger68352$9209.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
|
|
Optimizing lut $abc$68353$lut$aiger68352$9762.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$68353$lut$aiger68352$9762.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
|
|
Optimizing lut $abc$68353$lut$aiger68352$7231.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$68353$lut$aiger68352$5773.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$68662.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $abc$68353$lut$aiger68352$5773.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$68353$lut$aiger68352$7701.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
|
|
Optimizing lut $abc$68353$lut$aiger68352$7241.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$68353$lut$aiger$o4664.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$68353$lut$aiger68352$6912.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
|
|
Optimizing lut $abc$68353$lut$aiger68352$7078.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
|
|
Optimizing lut $abc$68353$lut$aiger$o3784.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$68671.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $abc$68353$lut$aiger68352$5833.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$68353$lut$aiger68352$9718.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
|
|
Optimizing lut $abc$68353$lut$aiger68352$9718.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$68673.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $abc$68353$lut$aiger68352$7224.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
|
|
Optimizing lut $abc$68353$lut$aiger68352$6912.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$68353$lut$aiger$o3604.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
|
|
Optimizing lut $abc$68353$lut$aiger68352$8762.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
|
|
Optimizing lut $abc$68353$lut$aiger68352$8762.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$68353$lut$aiger68352$7877.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$68353$lut$aiger68352$7652.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$68353$lut$aiger68352$9708.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
|
|
Optimizing lut $abc$68353$lut$aiger68352$9708.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$68353$lut$aiger68352$9165.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
|
|
Optimizing lut $abc$68353$lut$aiger68352$9161.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$68353$lut$aiger68352$9161.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
|
|
Optimizing lut $abc$68353$lut$aiger68352$7652.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$68680.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $abc$68353$lut$aiger68352$5833.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
|
|
Optimizing lut $abc$68353$lut$aiger68352$8752.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
|
|
Optimizing lut $abc$68353$lut$aiger68352$8752.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$68382.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$68353$lut$aiger68352$3941.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$68353$lut$aiger68352$3941.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$68379.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $abc$68353$lut$aiger68352$3757.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $abc$68353$lut$aiger68352$8699.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
|
|
Optimizing lut $abc$68353$lut$aiger68352$9694.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$68353$lut$aiger$o3574.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $abc$68353$lut$aiger68352$3910.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$68378.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $abc$68353$lut$aiger68352$3708.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$68368.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $abc$68353$lut$aiger$o3553.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
|
|
Optimizing lut $abc$68353$lut$aiger$o3705.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $abc$68353$lut$aiger$o3547.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Removed 0 unused cells and 4694 unused wires.
|
|
|
|
17.49. Executing AUTONAME pass.
|
|
Renamed 8193 objects in module spi_neuron_top.
|
|
<suppressed ~8193 debug messages>
|
|
|
|
17.50. Executing HIERARCHY pass (managing design hierarchy).
|
|
Attribute `top' found on module `spi_neuron_top'. Setting top module to spi_neuron_top.
|
|
|
|
17.50.1. Analyzing design hierarchy..
|
|
Top module: \spi_neuron_top
|
|
|
|
17.50.2. Analyzing design hierarchy..
|
|
Top module: \spi_neuron_top
|
|
Removed 0 unused modules.
|
|
|
|
17.51. Printing statistics.
|
|
|
|
=== spi_neuron_top ===
|
|
|
|
+----------Local Count, excluding submodules.
|
|
|
|
|
3241 wires
|
|
13292 wire bits
|
|
3241 public wires
|
|
13292 public wire bits
|
|
14 ports
|
|
51 port bits
|
|
41 cells
|
|
16 $_TBUF_
|
|
19 $scopeinfo
|
|
2 DP16KD
|
|
4 MULT18X18D
|
|
5520 submodules
|
|
391 CCU2C
|
|
2367 LUT4
|
|
356 PFUMX
|
|
2406 TRELLIS_FF
|
|
|
|
=== design hierarchy ===
|
|
|
|
+----------Count including submodules.
|
|
|
|
|
41 spi_neuron_top
|
|
|
|
+----------Count including submodules.
|
|
|
|
|
3241 wires
|
|
13292 wire bits
|
|
3241 public wires
|
|
13292 public wire bits
|
|
14 ports
|
|
51 port bits
|
|
- memories
|
|
- memory bits
|
|
- processes
|
|
41 cells
|
|
16 $_TBUF_
|
|
19 $scopeinfo
|
|
2 DP16KD
|
|
4 MULT18X18D
|
|
5520 submodules
|
|
391 CCU2C
|
|
2367 LUT4
|
|
356 PFUMX
|
|
2406 TRELLIS_FF
|
|
|
|
17.52. Executing CHECK pass (checking for obvious problems).
|
|
Checking module spi_neuron_top...
|
|
Found and reported 0 problems.
|
|
|
|
17.53. Executing JSON backend.
|
|
|
|
18. Printing statistics.
|
|
|
|
=== spi_neuron_top ===
|
|
|
|
+----------Local Count, excluding submodules.
|
|
|
|
|
3241 wires
|
|
13292 wire bits
|
|
3241 public wires
|
|
13292 public wire bits
|
|
14 ports
|
|
51 port bits
|
|
5561 cells
|
|
16 $_TBUF_
|
|
19 $scopeinfo
|
|
391 CCU2C
|
|
2 DP16KD
|
|
2367 LUT4
|
|
4 MULT18X18D
|
|
356 PFUMX
|
|
2406 TRELLIS_FF
|
|
|
|
Warnings: 1 unique messages, 1 total
|
|
End of script. Logfile hash: 64857ad720, time: 2.41s, user: 1.74s, system: 0.06s, MEM: 160.31 MB peak
|
|
Yosys 0.68+post (git sha1 c12172fbae8af5e20f6fb52e3d4e92d56ed587b6, Release, AppleClang clang++ 21.0.0.21000101)
|
|
Time spent: 29% 1x abc9_exe (0 sec), 12% 12x techmap (0 sec), ...
|