michele
1ddaa9adfd
Yosys + nextpnr-ecp5 synthesis of the extended spi_neuron_top.v (layer_sequencer + mux + arbiter Port C wired in), speed grade -8, N_INPUTS=32/N_NEURONS=1: PARALLEL=8 -> 40.57 MHz FAIL, PARALLEL=2 -> 42.54 MHz FAIL. Both worse than Phase 4 alone (~52.58/~55.85 MHz for the identical configs) -- the Phase 5 wiring cost real timing headroom. Critical path also shifted from Phase 4's saturation- comparator finding to neuron_memory's x_mem/w_mem LUT-RAM read-mux tree feeding the accumulator. Full analysis and candidate next steps (block RAM for x_mem/w_mem, pipelining, a seed sweep to separate placement noise from a structural bottleneck) recorded under Phase 7 in docs/FPGA-NeuralNetwork-Engine.md.
28 lines
1.1 KiB
Plaintext
28 lines
1.1 KiB
Plaintext
read_verilog -sv \
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/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_slave.v \
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/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v \
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/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v \
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/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mem_arbiter.v \
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/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v \
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/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/int8_memory_access.v \
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/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/memory_interface.v \
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/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/psram_controller.v \
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/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v \
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/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v \
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/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v \
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/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_neuron_top.v
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hierarchy -top spi_neuron_top
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proc
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flatten
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opt
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memory
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opt
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techmap
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opt
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abc -g simple
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clean
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synth_ecp5 -top spi_neuron_top -json /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/synth/ecp5/spi_neuron_top_p8/top.json
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