micheleandClaude Sonnet 5
dc0b331d3e
Begins the V2 Neural Multiprocessor / Dataflow architecture per docs/v2-description.md, per explicit user request to freeze V1 and start V2 development, copying from V1 what's needed. Scaffold: - hardware/v1/: byte-exact, read-only copy of the current V1 codebase (rtl, testbenches, tools, constraints, a representative subset of synthesis results, and reference docs) -- verified identical via diff/cmp against the live top-level tree before being made filesystem-read-only. The live top-level tree is untouched and remains the project's "production" V1 (see hardware/v1/README.md and hardware/v2/logs/decisions.log DEC-0001 for why copy-not-move). - hardware/v2/: mandatory structure (rtl/sim/constraints/synthesis/ reports/scripts/logs/docs) plus the full logging system required by the spec (development/architecture/simulation/synthesis/timing/ benchmark/decisions/experiments/errors.log). M1 -- Neural Processor (hardware/v2/rtl/neural_processor.v): - 8-stage pipelined perceptron unit (P_IN=8): input align, 8 multipliers, 3-level adder tree, accumulator, bias+activation, INT8 saturation. Genuine 1-tile/cycle throughput, not just a wider combinational datapath. - 7-state FSM (NP_IDLE..NP_ERROR per docs/v2-description.md §6, with 4 baseline states merged into NP_WAIT_OPERANDS -- see decisions.log DEC-0002); valid/ready/data/last stream interfaces per §7. - Bit-exact vs the frozen hardware/v1/rtl/neuron_parallel.v + mac8.v + mac_unit.v: 7/7 tests pass (hardware/v2/sim/tb_neural_processor.v), covering regular/mixed-sign/extreme-INT8 vectors, both activations, a zero-idle-gap back-to-back-tiles throughput check, and an 8-tile job -- verified with Verilator (see below for why). - Real synthesis + place&route (Yosys + nextpnr-ecp5): 0 CHECK problems, Fmax 183.12 MHz at ACC_WIDTH=32 (PASS at 80MHz, ~3x V1's isolated PARALLEL=8 Fmax of 61.71 MHz) and 176.21 MHz at ACC_WIDTH=24 (a user-requested comparison experiment, also bit-exact-verified; see experiments.log EXP-0001/EXP-0002 and benchmark.log). Three real bugs found and resolved during M1 development (full diagnostic record in errors.log): - Two independent, reproducible Icarus Verilog v13.0 scheduling defects (ERR-0001, ERR-0002) that silently produced wrong simulation results for standard sequential Verilog -- confirmed via Verilator 5.050 giving correct results on the same minimal repros. Verilator is now the trusted simulator for hardware/v2/ (decisions.log DEC-0004); Icarus's affected protocol-violation check was removed from the RTL and deferred architecturally to the Neural Director (DEC-0003) rather than chased further. - One real RTL bug (ERR-0003): last0 wasn't gated like valid0, letting a "last tile" tag leak into the pipeline ahead of its actual valid tile on back-to-back jobs. Fixed and verified. Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
18194 lines
396 KiB
Plaintext
18194 lines
396 KiB
Plaintext
.device LFE5U-45F
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.comment Part: LFE5U-45F-8CABGA381
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.tile CIB_R10C24:CIB_EBR
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arc: N3_V06N0303 S3_V06N0303
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.tile CIB_R10C3:PVT_COUNT2
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unknown: F2B0
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unknown: F3B0
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unknown: F5B0
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unknown: F11B0
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unknown: F13B0
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.tile CIB_R11C1:CIB_LR
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arc: E3_H06E0303 JQ5
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.tile CIB_R14C1:CIB_LR
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arc: E3_H06E0303 JQ5
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.tile CIB_R14C89:CIB_LR
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arc: S1_V02S0501 H06E0303
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arc: W3_H06W0303 JF5
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.tile CIB_R16C1:CIB_LR
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arc: E3_H06E0303 JQ5
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arc: S3_V06S0303 JF5
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.tile CIB_R16C89:CIB_LR
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arc: JA0 N1_V02S0501
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arc: W3_H06W0303 JQ5
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enum: CIB.JB0MUX 0
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.tile CIB_R17C1:CIB_LR
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arc: E3_H06E0303 JQ5
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arc: S3_V06S0303 JF5
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.tile CIB_R17C89:CIB_LR
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arc: S3_V06S0303 JF5
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arc: W3_H06W0303 JQ5
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.tile CIB_R19C1:CIB_LR
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arc: E3_H06E0303 JQ5
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arc: S1_V02S0501 JF5
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.tile CIB_R19C89:CIB_LR
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arc: H01W0100 JQ5
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arc: W3_H06W0303 JF5
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.tile CIB_R1C10:CIB
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arc: W1_H02W0501 S1_V02N0501
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.tile CIB_R1C11:CIB
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arc: JA0 S1_V02N0701
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enum: CIB.JB0MUX 0
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.tile CIB_R1C12:CIB
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arc: E3_H06E0003 JQ0
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.tile CIB_R1C13:CIB
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arc: E1_H02E0501 S1_V02N0501
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arc: E3_H06E0003 JQ0
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.tile CIB_R1C14:CIB
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arc: JA0 H02E0501
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enum: CIB.JB0MUX 0
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.tile CIB_R1C15:CIB
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arc: JA0 S1_V02N0701
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enum: CIB.JB0MUX 0
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.tile CIB_R1C16:CIB
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arc: E3_H06E0003 JQ0
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.tile CIB_R1C18:CIB
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arc: E3_H06E0103 W3_H06E0003
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arc: JA0 S1_V02N0501
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arc: S3_V06S0303 E1_H01W0100
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enum: CIB.JB0MUX 0
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.tile CIB_R1C19:CIB
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arc: E1_H02E0501 V06N0303
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arc: E3_H06E0103 W3_H06E0003
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arc: H01W0100 JQ0
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.tile CIB_R1C20:CIB
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arc: JA0 H02E0501
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enum: CIB.JB0MUX 0
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.tile CIB_R1C21:CIB
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arc: E3_H06E0003 JQ0
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arc: S3_V06S0103 H06E0103
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.tile CIB_R1C22:CIB
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arc: E3_H06E0103 W3_H06E0003
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arc: JA0 E1_H02W0501
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arc: S3_V06S0003 H06W0003
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arc: S3_V06S0103 H06E0103
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arc: S3_V06S0303 E3_H06W0303
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enum: CIB.JB0MUX 0
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.tile CIB_R1C23:CIB
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arc: E3_H06E0003 JQ0
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arc: S3_V06S0303 E3_H06W0303
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.tile CIB_R1C24:CIB
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arc: E1_H01E0001 JQ0
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arc: S3_V06S0003 H06E0003
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arc: W1_H02W0501 V06N0303
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.tile CIB_R1C25:CIB
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arc: E3_H06E0203 H01E0001
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arc: S3_V06S0003 JQ0
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arc: W3_H06W0003 E3_H06W0003
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.tile CIB_R1C26:CIB
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arc: S3_V06S0003 E3_H06W0003
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.tile CIB_R1C27:CIB
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arc: S1_V02S0001 JQ0
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arc: S3_V06S0003 E1_H01W0000
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arc: S3_V06S0203 E3_H06W0203
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arc: S3_V06S0303 E3_H06W0303
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.tile CIB_R1C28:CIB
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arc: H01W0000 JQ0
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arc: S3_V06S0003 E3_H06W0003
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arc: S3_V06S0103 W3_H06E0103
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arc: S3_V06S0203 H06E0203
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arc: S3_V06S0303 H06W0303
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arc: W3_H06W0303 E3_H06W0203
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.tile CIB_R1C29:CIB
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arc: E1_H01E0101 JQ0
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arc: S3_V06S0003 W3_H06E0003
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arc: W3_H06W0303 E3_H06W0303
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.tile CIB_R1C30:CIB
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arc: S3_V06S0003 JQ0
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arc: S3_V06S0303 H01E0101
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.tile CIB_R1C31:CIB
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arc: S3_V06S0003 JQ0
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arc: S3_V06S0203 E1_H01W0000
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arc: W3_H06W0003 E3_H06W0003
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arc: W3_H06W0303 E3_H06W0303
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.tile CIB_R1C32:CIB
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arc: H01W0000 JQ0
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arc: S3_V06S0003 E1_H01W0000
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arc: W3_H06W0003 E3_H06W0003
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.tile CIB_R1C33:CIB
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arc: H01W0000 JQ0
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arc: W3_H06W0203 E3_H06W0203
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arc: W3_H06W0303 E3_H06W0303
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.tile CIB_R1C34:CIB
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arc: S3_V06S0003 JQ0
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arc: W3_H06W0003 E3_H06W0003
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arc: W3_H06W0203 E3_H06W0203
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.tile CIB_R1C35:CIB
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arc: S3_V06S0003 E1_H01W0000
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arc: S3_V06S0103 H06W0103
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arc: S3_V06S0203 H06W0203
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arc: W3_H06W0303 E3_H06W0303
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.tile CIB_R1C36:CIB
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arc: H01W0000 JQ0
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arc: S3_V06S0003 H06W0003
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arc: S3_V06S0103 H06W0103
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arc: S3_V06S0203 E3_H06W0203
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arc: S3_V06S0303 E1_H01W0100
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.tile CIB_R1C37:CIB
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arc: E3_H06E0203 S3_V06N0203
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arc: H01W0100 JQ0
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arc: S3_V06S0103 E3_H06W0103
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arc: S3_V06S0203 E3_H06W0203
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arc: W3_H06W0003 E3_H06W0003
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arc: W3_H06W0303 E3_H06W0303
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.tile CIB_R1C38:CIB
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arc: E3_H06E0003 JQ0
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arc: W3_H06W0003 E3_H06W0003
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arc: W3_H06W0103 E1_H01W0100
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arc: W3_H06W0203 E3_H06W0103
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.tile CIB_R1C39:CIB
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arc: H01W0100 JQ0
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arc: W3_H06W0003 E3_H06W0003
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arc: W3_H06W0103 E3_H06W0103
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arc: W3_H06W0203 E3_H06W0203
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arc: W3_H06W0303 E3_H06W0303
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.tile CIB_R1C40:CIB
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arc: W3_H06W0003 E3_H06W0003
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arc: W3_H06W0203 E3_H06W0103
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.tile CIB_R1C41:CIB
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arc: S3_V06S0003 H06E0003
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arc: W3_H06W0303 E3_H06W0203
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.tile CIB_R1C42:CIB
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arc: S3_V06S0003 JQ0
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arc: S3_V06S0303 E3_H06W0303
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arc: W3_H06W0203 E3_H06W0103
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.tile CIB_R1C43:CIB
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arc: E3_H06E0303 W3_H06E0203
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arc: S3_V06S0203 H06W0203
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arc: W3_H06W0003 JQ0
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arc: W3_H06W0103 E3_H06W0003
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arc: W3_H06W0203 E3_H06W0103
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arc: W3_H06W0303 E3_H06W0303
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.tile CIB_R1C44:CIB
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arc: S3_V06S0003 H06W0003
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arc: S3_V06S0103 E3_H06W0103
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arc: S3_V06S0303 H06W0303
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arc: W3_H06W0003 JQ0
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arc: W3_H06W0103 E3_H06W0003
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.tile CIB_R1C45:CIB
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arc: S3_V06S0003 E3_H06W0003
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arc: W3_H06W0003 JQ0
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arc: W3_H06W0103 E3_H06W0103
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arc: W3_H06W0203 E1_H01W0000
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arc: W3_H06W0303 E3_H06W0203
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.tile CIB_R1C46:CIB
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arc: H01W0000 E3_H06W0103
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arc: W3_H06W0003 E3_H06W0303
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arc: W3_H06W0103 E3_H06W0003
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arc: W3_H06W0203 E1_H01W0000
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.tile CIB_R1C47:CIB
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arc: H01W0000 JQ0
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arc: W3_H06W0003 E3_H06W0003
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arc: W3_H06W0203 E3_H06W0203
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arc: W3_H06W0303 E1_H01W0100
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.tile CIB_R1C48:CIB
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arc: H01W0100 JQ0
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arc: JD7 E1_H01W0100
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arc: W3_H06W0103 E3_H06W0003
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arc: W3_H06W0303 E3_H06W0203
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.tile CIB_R1C49:CIB
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arc: H01W0100 W3_H06E0303
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arc: W3_H06W0003 JQ0
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arc: W3_H06W0103 E3_H06W0103
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arc: W3_H06W0303 E3_H06W0303
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.tile CIB_R1C50:CIB
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arc: W3_H06W0003 JQ0
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arc: W3_H06W0103 E3_H06W0003
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.tile CIB_R1C51:CIB
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arc: W3_H06W0003 JQ0
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arc: W3_H06W0103 E3_H06W0003
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arc: W3_H06W0203 E3_H06W0103
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.tile CIB_R1C52:CIB
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arc: W3_H06W0003 JQ0
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arc: W3_H06W0103 E3_H06W0003
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arc: W3_H06W0303 E3_H06W0203
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.tile CIB_R1C53:CIB
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arc: JA0 V02N0501
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arc: W3_H06W0003 E3_H06W0003
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arc: W3_H06W0203 E3_H06W0103
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enum: CIB.JB0MUX 0
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.tile CIB_R1C54:CIB
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arc: W3_H06W0003 JQ0
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arc: W3_H06W0203 E3_H06W0203
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.tile CIB_R1C55:CIB
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arc: W3_H06W0103 E3_H06W0003
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arc: W3_H06W0303 E3_H06W0303
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.tile CIB_R1C56:CIB
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arc: JA0 H02W0701
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arc: W3_H06W0003 E3_H06W0003
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enum: CIB.JB0MUX 0
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.tile CIB_R1C57:CIB
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arc: W1_H02W0701 S1_V02N0701
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arc: W3_H06W0003 JQ0
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arc: W3_H06W0103 E3_H06W0103
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.tile CIB_R1C58:CIB
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arc: W3_H06W0003 JQ0
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arc: W3_H06W0203 E3_H06W0103
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.tile CIB_R1C59:CIB
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arc: W3_H06W0003 JQ0
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arc: W3_H06W0103 E3_H06W0003
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.tile CIB_R1C60:CIB
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arc: E1_H02E0501 S3_V06N0303
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arc: JA0 S1_V02N0501
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arc: W3_H06W0203 E3_H06W0103
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enum: CIB.JB0MUX 0
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.tile CIB_R1C61:CIB
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arc: E1_H02E0501 S3_V06N0303
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arc: JA0 H02E0501
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arc: W3_H06W0003 E3_H06W0003
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arc: W3_H06W0303 E1_H01W0100
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enum: CIB.JB0MUX 0
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.tile CIB_R1C62:CIB
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arc: H01W0100 JQ0
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arc: W3_H06W0003 E3_H06W0003
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.tile CIB_R1C63:CIB
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arc: JA0 W1_H02E0501
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arc: W3_H06W0103 E3_H06W0003
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enum: CIB.JB0MUX 0
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.tile CIB_R1C64:CIB
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arc: E1_H02E0501 S1_V02N0501
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arc: W3_H06W0103 E3_H06W0003
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.tile CIB_R1C65:CIB
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arc: W3_H06W0003 JQ0
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.tile CIB_R1C66:CIB
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arc: JA0 W1_H02E0501
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arc: W3_H06W0103 E3_H06W0003
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enum: CIB.JB0MUX 0
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.tile CIB_R1C67:CIB
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arc: W3_H06W0003 JQ0
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.tile CIB_R1C68:CIB
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arc: W3_H06W0003 JQ0
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.tile CIB_R1C69:CIB
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arc: W3_H06W0003 JQ0
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.tile CIB_R1C70:CIB
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arc: E1_H02E0701 V06N0203
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arc: W3_H06W0003 JQ0
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.tile CIB_R1C71:CIB
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arc: JA0 H02E0701
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enum: CIB.JB0MUX 0
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.tile CIB_R1C72:CIB
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arc: W3_H06W0003 JQ0
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.tile CIB_R1C9:CIB
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arc: JA0 H02W0501
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enum: CIB.JB0MUX 0
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.tile CIB_R20C1:CIB_LR
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arc: E1_H01E0001 JQ5
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arc: E3_H06E0303 V06S0303
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arc: S1_V02S0701 JF5
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.tile CIB_R20C89:CIB_LR
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arc: W1_H02W0501 V06S0303
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arc: W1_H02W0701 JF5
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arc: W3_H06W0303 JQ5
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.tile CIB_R21C1:CIB_LR
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arc: E1_H02E0501 N1_V02S0501
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arc: E1_H02E0701 V02S0701
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arc: E3_H06E0003 V01N0001
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arc: E3_H06E0103 V01N0101
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.tile CIB_R22C13:CIB_DSP
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arc: E3_H06E0003 W3_H06E0303
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.tile CIB_R22C19:CIB_DSP
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arc: E3_H06E0003 W3_H06E0003
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.tile CIB_R22C1:CIB_LR_S
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arc: E3_H06E0303 N3_V06S0303
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arc: N1_V01N0001 JQ5
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arc: N1_V01N0101 JF5
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arc: V01S0100 S3_V06N0303
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.tile CIB_R22C21:CIB_DSP
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arc: E1_H02E0001 N1_V01S0000
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arc: E1_H02E0301 N1_V01S0100
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arc: S1_V02S0301 E1_H02W0301
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arc: S1_V02S0401 E1_H01W0000
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.tile CIB_R22C22:CIB_DSP
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arc: E1_H01E0001 JF2
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arc: E1_H02E0001 V02N0001
|
|
arc: E1_H02E0101 N1_V01S0100
|
|
arc: E1_H02E0301 V01N0101
|
|
arc: E1_H02E0501 N1_V01S0100
|
|
arc: E1_H02E0701 N1_V01S0100
|
|
arc: H00L0100 N1_V02S0101
|
|
arc: H00R0000 V02S0601
|
|
arc: H00R0100 V02N0701
|
|
arc: H01W0000 JF4
|
|
arc: JB0 V01N0001
|
|
arc: JB1 H02E0301
|
|
arc: JB2 V02N0101
|
|
arc: JB3 V02S0101
|
|
arc: JB4 H00R0000
|
|
arc: JB5 H02W0101
|
|
arc: JB6 V00B0100
|
|
arc: JB7 V00B0000
|
|
arc: JCE0 H00R0100
|
|
arc: JD0 N1_V01S0000
|
|
arc: JD1 V00T0100
|
|
arc: JD2 H02W0001
|
|
arc: JD3 H02W0201
|
|
arc: JD4 N1_V02S0601
|
|
arc: JD5 V02N0401
|
|
arc: JD6 H00L0100
|
|
arc: JD7 H02E0001
|
|
arc: JLSR0 E1_H02W0501
|
|
arc: JLSR1 E1_H02W0501
|
|
arc: N1_V02N0001 JF0
|
|
arc: N1_V02N0301 JF1
|
|
arc: N1_V02N0401 N3_V06S0203
|
|
arc: N1_V02N0701 JF5
|
|
arc: S1_V02S0101 E1_H01W0100
|
|
arc: S1_V02S0201 S3_V06N0103
|
|
arc: S1_V02S0301 JF3
|
|
arc: S1_V02S0401 JF6
|
|
arc: S1_V02S0601 E1_H01W0000
|
|
arc: S1_V02S0701 JF7
|
|
arc: V00B0000 V02N0001
|
|
arc: V00B0100 V02S0301
|
|
arc: V00T0100 S1_V02N0501
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JC2MUX 0
|
|
enum: CIB.JA1MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
enum: CIB.JC6MUX 0
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
|
|
.tile CIB_R22C23:CIB_DSP
|
|
arc: E1_H01E0001 JF6
|
|
arc: H00R0100 H02E0701
|
|
arc: H01W0000 JF4
|
|
arc: H01W0100 JF2
|
|
arc: JB0 H02E0101
|
|
arc: JB1 H02E0301
|
|
arc: JB2 H02E0101
|
|
arc: JB3 H02E0301
|
|
arc: JB4 H02E0101
|
|
arc: JB5 H02E0301
|
|
arc: JB6 H02E0101
|
|
arc: JB7 H02E0301
|
|
arc: JD0 V02N0201
|
|
arc: JD1 V00B0100
|
|
arc: JD2 V02N0201
|
|
arc: JD3 V00B0100
|
|
arc: JD4 V02N0601
|
|
arc: JD5 H00R0100
|
|
arc: JD6 V02N0601
|
|
arc: JD7 H00R0100
|
|
arc: JLSR1 V00T0100
|
|
arc: N1_V01N0001 JF1
|
|
arc: N1_V02N0201 JF0
|
|
arc: S1_V02S0401 H01E0001
|
|
arc: S1_V02S0501 JF7
|
|
arc: S1_V02S0601 S3_V06N0303
|
|
arc: S1_V02S0701 JF5
|
|
arc: V00B0100 H02E0701
|
|
arc: V00T0100 V02N0701
|
|
arc: W1_H02W0001 N1_V01S0000
|
|
arc: W1_H02W0101 V02N0101
|
|
arc: W1_H02W0201 V01N0001
|
|
arc: W1_H02W0301 JF3
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JC2MUX 0
|
|
enum: CIB.JA1MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
enum: CIB.JC6MUX 0
|
|
|
|
.tile CIB_R22C24:CIB_DSP
|
|
arc: JB0 W1_H02E0101
|
|
arc: JB1 W1_H02E0301
|
|
arc: JD0 W1_H02E0001
|
|
arc: JD1 V00B0100
|
|
arc: S1_V02S0201 H01E0001
|
|
arc: S3_V06S0003 N3_V06S0303
|
|
arc: V00B0100 W1_H02E0501
|
|
arc: W1_H02W0501 N3_V06S0303
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
|
|
.tile CIB_R22C25:CIB_DSP
|
|
arc: E1_H02E0101 N1_V01S0100
|
|
arc: E1_H02E0201 V01N0001
|
|
arc: E1_H02E0301 V01N0101
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: S1_V02S0201 E1_H01W0000
|
|
arc: S1_V02S0301 S3_V06N0003
|
|
arc: S1_V02S0501 H02W0501
|
|
arc: V01S0100 S3_V06N0303
|
|
|
|
.tile CIB_R22C26:CIB_DSP
|
|
arc: E1_H01E0001 JF4
|
|
arc: E1_H02E0001 V01N0001
|
|
arc: E1_H02E0101 V02N0101
|
|
arc: E1_H02E0201 V02N0201
|
|
arc: E1_H02E0301 V01N0101
|
|
arc: E1_H02E0401 V01N0001
|
|
arc: E1_H02E0501 JQ7
|
|
arc: E1_H02E0601 V01N0001
|
|
arc: H00R0000 E1_H02W0401
|
|
arc: H01W0000 JQ5
|
|
arc: JB4 H02E0301
|
|
arc: JB5 S1_V02N0701
|
|
arc: JB6 V02N0701
|
|
arc: JB7 H02E0101
|
|
arc: JCE2 H00R0000
|
|
arc: JCE3 H00R0000
|
|
arc: JD4 V02N0401
|
|
arc: JD5 V00B0000
|
|
arc: JD6 V02S0401
|
|
arc: JD7 H02E0201
|
|
arc: N1_V02N0401 JQ6
|
|
arc: S1_V02S0201 E1_H01W0000
|
|
arc: S1_V02S0401 JQ4
|
|
arc: S1_V02S0501 E1_H01W0100
|
|
arc: S1_V02S0601 JF6
|
|
arc: S1_V02S0701 JF7
|
|
arc: S3_V06S0003 N1_V01S0000
|
|
arc: S3_V06S0103 N1_V01S0100
|
|
arc: V00B0000 H02W0601
|
|
arc: W1_H02W0501 JF5
|
|
|
|
.tile CIB_R22C27:CIB_DSP
|
|
arc: E1_H01E0001 JF1
|
|
arc: E1_H01E0101 JF3
|
|
arc: E1_H02E0001 N1_V02S0001
|
|
arc: E1_H02E0101 V02S0101
|
|
arc: E1_H02E0201 V01N0001
|
|
arc: E1_H02E0301 V01N0101
|
|
arc: E1_H02E0501 N1_V01S0100
|
|
arc: H00R0000 H02E0401
|
|
arc: H01W0000 JF6
|
|
arc: H01W0100 JF7
|
|
arc: JB0 V00T0000
|
|
arc: JB1 V02N0101
|
|
arc: JB2 H02E0101
|
|
arc: JB3 H02E0301
|
|
arc: JB4 H00R0000
|
|
arc: JB5 H02E0301
|
|
arc: JB6 V02N0701
|
|
arc: JB7 H02E0301
|
|
arc: JD0 V02N0201
|
|
arc: JD1 V00B0100
|
|
arc: JD2 V02N0001
|
|
arc: JD3 S1_V02N0201
|
|
arc: JD4 H02E0201
|
|
arc: JD5 H02E0001
|
|
arc: JD6 H02E0201
|
|
arc: JD7 H02E0001
|
|
arc: N1_V01N0001 JF0
|
|
arc: N1_V01N0101 JQ6
|
|
arc: N1_V02N0001 JQ2
|
|
arc: N1_V02N0101 JQ1
|
|
arc: N1_V02N0201 JF2
|
|
arc: N1_V02N0301 H02W0301
|
|
arc: N1_V02N0401 N1_V01S0000
|
|
arc: N1_V02N0501 E1_H01W0100
|
|
arc: N1_V02N0601 JF4
|
|
arc: S1_V02S0001 H01E0001
|
|
arc: S1_V02S0101 JQ3
|
|
arc: S1_V02S0201 JQ0
|
|
arc: S1_V02S0401 JQ4
|
|
arc: S1_V02S0501 JQ5
|
|
arc: S1_V02S0601 E1_H01W0000
|
|
arc: S1_V02S0701 JQ7
|
|
arc: V00B0100 V02N0301
|
|
arc: V00T0000 S1_V02N0601
|
|
arc: V01S0000 JF5
|
|
arc: W1_H02W0601 N1_V02S0601
|
|
enum: CIB.JC1MUX 0
|
|
enum: CIB.JA6MUX 0
|
|
enum: CIB.JC7MUX 0
|
|
enum: CIB.JA4MUX 0
|
|
enum: CIB.JC5MUX 0
|
|
enum: CIB.JA2MUX 0
|
|
enum: CIB.JC3MUX 0
|
|
enum: CIB.JA0MUX 0
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JC2MUX 0
|
|
enum: CIB.JA1MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
enum: CIB.JC6MUX 0
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
|
|
.tile CIB_R22C28:CIB_DSP
|
|
arc: E1_H02E0001 N1_V01S0000
|
|
arc: E1_H02E0101 V02N0101
|
|
arc: E1_H02E0201 S1_V02N0201
|
|
arc: H00R0000 W1_H02E0601
|
|
arc: H01W0000 JQ2
|
|
arc: H01W0100 JQ3
|
|
arc: JB0 V02N0301
|
|
arc: JB1 W1_H02E0301
|
|
arc: JB2 V02N0301
|
|
arc: JB3 W1_H02E0301
|
|
arc: JB4 H00R0000
|
|
arc: JB5 W1_H02E0301
|
|
arc: JB6 V02N0701
|
|
arc: JB7 V00B0000
|
|
arc: JD0 W1_H02E0201
|
|
arc: JD1 W1_H02E0001
|
|
arc: JD2 W1_H02E0201
|
|
arc: JD3 W1_H02E0001
|
|
arc: JD4 W1_H02E0201
|
|
arc: JD5 W1_H02E0001
|
|
arc: JD6 V02S0601
|
|
arc: JD7 V02N0601
|
|
arc: JLSR0 E1_H02W0501
|
|
arc: JLSR1 E1_H02W0501
|
|
arc: N1_V01N0001 JF2
|
|
arc: N1_V02N0001 JF0
|
|
arc: N1_V02N0101 JF3
|
|
arc: N1_V02N0201 S1_V02N0701
|
|
arc: N1_V02N0301 JF1
|
|
arc: N1_V02N0601 H01E0001
|
|
arc: N1_V02N0701 H01E0101
|
|
arc: S1_V02S0001 JQ0
|
|
arc: S1_V02S0101 JQ1
|
|
arc: S1_V02S0401 S3_V06N0203
|
|
arc: S1_V02S0501 W1_H02E0501
|
|
arc: V00B0000 V02S0201
|
|
arc: W1_H02W0301 V06N0003
|
|
arc: W1_H02W0401 V02N0401
|
|
enum: CIB.JC1MUX 0
|
|
enum: CIB.JA6MUX 0
|
|
enum: CIB.JC7MUX 0
|
|
enum: CIB.JA4MUX 0
|
|
enum: CIB.JC5MUX 0
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JC2MUX 0
|
|
enum: CIB.JA1MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
enum: CIB.JC6MUX 0
|
|
|
|
.tile CIB_R22C29:CIB_DSP
|
|
arc: E1_H02E0201 W1_H02E0201
|
|
arc: E1_H02E0301 V02N0301
|
|
arc: H00R0100 W1_H02E0501
|
|
arc: JB0 W1_H02E0101
|
|
arc: JB1 V02N0101
|
|
arc: JB2 N1_V02S0101
|
|
arc: JB3 W1_H02E0301
|
|
arc: JB4 V02S0501
|
|
arc: JB5 V02N0701
|
|
arc: JB6 V02S0501
|
|
arc: JB7 V02N0701
|
|
arc: JD0 N1_V01S0000
|
|
arc: JD1 H02E0001
|
|
arc: JD2 W1_H02E0001
|
|
arc: JD3 V02S0001
|
|
arc: JD4 V00B0000
|
|
arc: JD5 H02E0201
|
|
arc: JD6 W1_H02E0201
|
|
arc: JD7 H00R0100
|
|
arc: JLSR1 V00B0100
|
|
arc: V00B0000 V02N0201
|
|
arc: V00B0100 V02N0301
|
|
arc: V01S0000 S3_V06N0103
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
|
|
.tile CIB_R22C30:CIB_DSP
|
|
arc: E1_H02E0501 N3_V06S0303
|
|
arc: H00L0100 H02E0301
|
|
arc: H00R0000 V02S0401
|
|
arc: H00R0100 V02S0701
|
|
arc: JB0 H00R0100
|
|
arc: JB1 V00T0000
|
|
arc: JB2 H00R0100
|
|
arc: JB3 W1_H02E0101
|
|
arc: JB4 V02S0701
|
|
arc: JB5 V02N0501
|
|
arc: JB6 V02S0701
|
|
arc: JB7 V02N0501
|
|
arc: JCE3 H00L0100
|
|
arc: JD0 H02E0201
|
|
arc: JD1 H00R0000
|
|
arc: JD2 V02N0201
|
|
arc: JD3 H00R0000
|
|
arc: JD4 V02N0601
|
|
arc: JD5 V02S0401
|
|
arc: JD6 V02N0601
|
|
arc: JD7 V02S0401
|
|
arc: JLSR0 V00B0100
|
|
arc: JLSR1 V00B0100
|
|
arc: S1_V02S0601 E1_H01W0000
|
|
arc: S1_V02S0701 E1_H01W0100
|
|
arc: S3_V06S0303 N3_V06S0303
|
|
arc: V00B0100 V02N0101
|
|
arc: V00T0000 V02N0601
|
|
arc: V01S0100 N3_V06S0303
|
|
arc: W1_H02W0501 N3_V06S0303
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JC2MUX 0
|
|
enum: CIB.JA1MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
|
|
.tile CIB_R22C31:CIB_DSP
|
|
arc: E1_H01E0001 JQ7
|
|
arc: E1_H01E0101 JQ6
|
|
arc: E1_H02E0001 V01N0001
|
|
arc: E1_H02E0101 N1_V01S0100
|
|
arc: E1_H02E0201 N1_V01S0000
|
|
arc: E1_H02E0301 JQ3
|
|
arc: E1_H02E0501 JQ5
|
|
arc: H01W0000 JQ0
|
|
arc: H01W0100 JQ4
|
|
arc: N1_V01N0001 JQ1
|
|
arc: N1_V02N0101 V01N0101
|
|
arc: N1_V02N0301 W3_H06E0003
|
|
arc: S1_V02S0101 V01N0101
|
|
arc: S1_V02S0601 E1_H01W0000
|
|
arc: V01S0000 JQ2
|
|
enum: CIB.JC1MUX 0
|
|
enum: CIB.JA6MUX 0
|
|
enum: CIB.JC7MUX 0
|
|
enum: CIB.JA4MUX 0
|
|
enum: CIB.JC5MUX 0
|
|
enum: CIB.JA2MUX 0
|
|
enum: CIB.JC3MUX 0
|
|
enum: CIB.JA0MUX 0
|
|
|
|
.tile CIB_R22C32:CIB_DSP
|
|
arc: E1_H02E0001 S1_V02N0001
|
|
arc: E1_H02E0101 V02S0101
|
|
arc: E1_H02E0201 N1_V01S0000
|
|
arc: E1_H02E0301 N1_V01S0100
|
|
arc: E1_H02E0501 W1_H02E0501
|
|
arc: E1_H02E0701 V02S0701
|
|
arc: H01W0000 JQ1
|
|
arc: N1_V01N0001 JQ4
|
|
arc: N1_V02N0101 H01E0101
|
|
arc: N1_V02N0701 JQ7
|
|
arc: S1_V02S0001 JQ2
|
|
arc: S1_V02S0101 JQ3
|
|
arc: S1_V02S0201 JQ0
|
|
arc: S1_V02S0301 H02E0301
|
|
arc: S1_V02S0401 JQ6
|
|
arc: S1_V02S0501 H02E0501
|
|
arc: S1_V02S0601 H01E0001
|
|
arc: S1_V02S0701 JQ5
|
|
enum: CIB.JC1MUX 0
|
|
enum: CIB.JA6MUX 0
|
|
enum: CIB.JC7MUX 0
|
|
enum: CIB.JA4MUX 0
|
|
enum: CIB.JC5MUX 0
|
|
|
|
.tile CIB_R22C33:CIB_DSP
|
|
arc: E1_H02E0001 V02S0001
|
|
arc: E1_H02E0301 V02S0301
|
|
arc: H00R0000 V02N0401
|
|
arc: H00R0100 H02E0701
|
|
arc: JB2 H00R0100
|
|
arc: JB3 H00R0000
|
|
arc: JB4 V02N0501
|
|
arc: JB5 N1_V02S0701
|
|
arc: JB6 W1_H02E0101
|
|
arc: JB7 S1_V02N0701
|
|
arc: JD2 W1_H02E0201
|
|
arc: JD3 N1_V01S0000
|
|
arc: JD4 S1_V02N0601
|
|
arc: JD5 V01N0001
|
|
arc: JD6 W1_H02E0001
|
|
arc: JD7 H02E0001
|
|
arc: JLSR0 H02E0501
|
|
arc: JLSR1 H02E0501
|
|
|
|
.tile CIB_R22C34:CIB_DSP
|
|
arc: E1_H02E0001 V01N0001
|
|
arc: E1_H02E0101 V01N0101
|
|
arc: E1_H02E0201 N1_V01S0000
|
|
arc: E1_H02E0301 N1_V01S0100
|
|
arc: E1_H02E0601 S3_V06N0303
|
|
arc: E3_H06E0303 V01N0101
|
|
arc: JB0 W1_H02E0301
|
|
arc: JB1 W1_H02E0101
|
|
arc: JB2 W1_H02E0301
|
|
arc: JB3 V02S0301
|
|
arc: JB4 W1_H02E0301
|
|
arc: JB5 W1_H02E0101
|
|
arc: JB6 W1_H02E0301
|
|
arc: JB7 W1_H02E0101
|
|
arc: JD0 V02S0201
|
|
arc: JD1 H02E0001
|
|
arc: JD2 N1_V02S0001
|
|
arc: JD3 W1_H02E0201
|
|
arc: JD4 N1_V02S0601
|
|
arc: JD5 W1_H02E0201
|
|
arc: JD6 N1_V02S0601
|
|
arc: JD7 W1_H02E0201
|
|
arc: S1_V02S0101 E1_H02W0101
|
|
arc: S1_V02S0301 E1_H01W0100
|
|
arc: S1_V02S0601 E1_H01W0000
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JC2MUX 0
|
|
enum: CIB.JA1MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
|
|
.tile CIB_R22C35:CIB_DSP
|
|
arc: E1_H01E0001 JQ4
|
|
arc: E1_H01E0101 JQ6
|
|
arc: E1_H02E0001 N1_V01S0000
|
|
arc: E1_H02E0101 N1_V01S0100
|
|
arc: E1_H02E0201 V02S0201
|
|
arc: E1_H02E0501 N1_V01S0100
|
|
arc: E1_H02E0701 N1_V01S0100
|
|
arc: H00L0000 V02N0001
|
|
arc: H00L0100 V02S0301
|
|
arc: H00R0000 V02S0601
|
|
arc: H00R0100 V02S0501
|
|
arc: H01W0000 JQ5
|
|
arc: H01W0100 JF7
|
|
arc: JB0 H00R0100
|
|
arc: JB1 W1_H02E0301
|
|
arc: JB2 H00R0000
|
|
arc: JB3 W1_H02E0301
|
|
arc: JB4 S1_V02N0501
|
|
arc: JB5 H00L0000
|
|
arc: JB6 N1_V02S0501
|
|
arc: JB7 V00T0000
|
|
arc: JCE0 H02E0101
|
|
arc: JCE1 H02E0101
|
|
arc: JCE2 H02E0101
|
|
arc: JCE3 H02E0101
|
|
arc: JD0 V02S0001
|
|
arc: JD1 H00R0000
|
|
arc: JD2 V02S0001
|
|
arc: JD3 H00R0000
|
|
arc: JD4 N1_V02S0601
|
|
arc: JD5 H00L0100
|
|
arc: JD6 V01N0001
|
|
arc: JD7 V02N0601
|
|
arc: N1_V02N0601 H02E0601
|
|
arc: S1_V02S0001 S3_V06N0003
|
|
arc: S1_V02S0101 E1_H02W0101
|
|
arc: S1_V02S0201 E1_H01W0000
|
|
arc: S1_V02S0301 E1_H01W0100
|
|
arc: S1_V02S0401 JF4
|
|
arc: S1_V02S0501 H02W0501
|
|
arc: S1_V02S0601 JF6
|
|
arc: S1_V02S0701 JF5
|
|
arc: S3_V06S0203 JQ7
|
|
arc: V00T0000 V02S0401
|
|
arc: V01S0000 S3_V06N0103
|
|
|
|
.tile CIB_R22C36:CIB_DSP
|
|
arc: E1_H01E0001 JF6
|
|
arc: E1_H01E0101 JQ7
|
|
arc: E1_H02E0001 V02N0001
|
|
arc: E1_H02E0101 N1_V01S0100
|
|
arc: E1_H02E0201 V01N0001
|
|
arc: E1_H02E0301 V02N0301
|
|
arc: E1_H02E0401 V02S0401
|
|
arc: E1_H02E0501 N3_V06S0303
|
|
arc: E1_H02E0601 S1_V02N0601
|
|
arc: E1_H02E0701 V01N0101
|
|
arc: H00R0100 H02E0501
|
|
arc: H01W0000 JF4
|
|
arc: H01W0100 JF1
|
|
arc: JB0 W1_H02E0301
|
|
arc: JB1 S1_V02N0101
|
|
arc: JB2 V02S0301
|
|
arc: JB3 H02E0101
|
|
arc: JB4 V02S0701
|
|
arc: JB5 H02E0101
|
|
arc: JB6 V02S0701
|
|
arc: JB7 H02E0101
|
|
arc: JD0 W1_H02E0201
|
|
arc: JD1 W1_H02E0001
|
|
arc: JD2 N1_V01S0000
|
|
arc: JD3 H02E0001
|
|
arc: JD4 H00R0100
|
|
arc: JD5 H02E0201
|
|
arc: JD6 H00R0100
|
|
arc: JD7 H02E0201
|
|
arc: N1_V01N0001 JF2
|
|
arc: N1_V01N0101 JF5
|
|
arc: N1_V02N0001 JQ2
|
|
arc: N1_V02N0101 E1_H01W0100
|
|
arc: N1_V02N0201 JQ0
|
|
arc: N1_V02N0301 JQ1
|
|
arc: N1_V02N0401 JQ6
|
|
arc: N1_V02N0601 H01E0001
|
|
arc: S1_V02S0001 E1_H01W0000
|
|
arc: S1_V02S0101 JQ3
|
|
arc: S1_V02S0501 H01E0101
|
|
arc: S1_V02S0601 JQ4
|
|
arc: S1_V02S0701 JQ5
|
|
arc: S3_V06S0003 JF0
|
|
arc: S3_V06S0303 N3_V06S0303
|
|
arc: V01S0100 S3_V06N0303
|
|
arc: W1_H02W0101 JF3
|
|
arc: W1_H02W0501 JF7
|
|
enum: CIB.JC1MUX 0
|
|
enum: CIB.JA6MUX 0
|
|
enum: CIB.JC7MUX 0
|
|
enum: CIB.JA4MUX 0
|
|
enum: CIB.JC5MUX 0
|
|
enum: CIB.JA2MUX 0
|
|
enum: CIB.JC3MUX 0
|
|
enum: CIB.JA0MUX 0
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JC2MUX 0
|
|
enum: CIB.JA1MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
enum: CIB.JC6MUX 0
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
|
|
.tile CIB_R22C37:CIB_DSP
|
|
arc: E1_H02E0001 V02N0001
|
|
arc: E1_H02E0101 V02N0101
|
|
arc: E1_H02E0301 S1_V02N0301
|
|
arc: H00L0000 V02S0001
|
|
arc: H00R0100 W1_H02E0501
|
|
arc: H01W0000 JQ0
|
|
arc: H01W0100 JQ3
|
|
arc: JB0 V00B0000
|
|
arc: JB1 W1_H02E0101
|
|
arc: JB2 H00L0000
|
|
arc: JB3 W1_H02E0101
|
|
arc: JB4 H00L0000
|
|
arc: JB5 W1_H02E0101
|
|
arc: JB6 S1_V02N0501
|
|
arc: JB7 V02N0501
|
|
arc: JD0 V00B0100
|
|
arc: JD1 V02S0201
|
|
arc: JD2 V00B0100
|
|
arc: JD3 V02S0201
|
|
arc: JD4 H00R0100
|
|
arc: JD5 V00B0000
|
|
arc: JD6 N1_V02S0601
|
|
arc: JD7 H02W0001
|
|
arc: JLSR0 H02E0501
|
|
arc: JLSR1 H02E0501
|
|
arc: N1_V01N0001 JQ1
|
|
arc: N1_V02N0101 H01E0101
|
|
arc: N1_V02N0201 JF0
|
|
arc: N1_V02N0301 JF1
|
|
arc: N1_V02N0401 H01E0001
|
|
arc: S1_V02S0001 JF2
|
|
arc: S1_V02S0201 JQ2
|
|
arc: V00B0000 V02S0201
|
|
arc: V00B0100 W1_H02E0701
|
|
arc: V01S0100 S3_V06N0303
|
|
arc: W1_H02W0101 JF3
|
|
enum: CIB.JC1MUX 0
|
|
enum: CIB.JA6MUX 0
|
|
enum: CIB.JC7MUX 0
|
|
enum: CIB.JA4MUX 0
|
|
enum: CIB.JC5MUX 0
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JC2MUX 0
|
|
enum: CIB.JA1MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
enum: CIB.JC6MUX 0
|
|
|
|
.tile CIB_R22C38:CIB_DSP
|
|
arc: E1_H02E0501 W1_H02E0501
|
|
arc: E3_H06E0303 W1_H02E0501
|
|
arc: H00R0000 W1_H02E0401
|
|
arc: H00R0100 W1_H02E0701
|
|
arc: JB0 V00B0000
|
|
arc: JB1 W1_H02E0101
|
|
arc: JB2 H00R0100
|
|
arc: JB3 H02E0301
|
|
arc: JB4 H00R0000
|
|
arc: JB5 W1_H02E0301
|
|
arc: JB6 V00T0000
|
|
arc: JB7 W1_H02E0301
|
|
arc: JD0 V02N0201
|
|
arc: JD1 V02N0001
|
|
arc: JD2 N1_V02S0201
|
|
arc: JD3 V00T0100
|
|
arc: JD4 N1_V02S0601
|
|
arc: JD5 W1_H02E0001
|
|
arc: JD6 W1_H02E0201
|
|
arc: JD7 V02S0601
|
|
arc: JLSR1 E1_H02W0501
|
|
arc: N1_V02N0201 S1_V02N0201
|
|
arc: N1_V02N0401 V01N0001
|
|
arc: N1_V02N0601 V01N0001
|
|
arc: V00B0000 W1_H02E0601
|
|
arc: V00T0000 V02S0601
|
|
arc: V00T0100 V02N0701
|
|
arc: W1_H02W0001 N1_V01S0000
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
|
|
.tile CIB_R22C39:CIB_DSP
|
|
arc: H00R0000 V02S0401
|
|
arc: H00R0100 V02S0701
|
|
arc: JB0 H00R0100
|
|
arc: JB1 W1_H02E0101
|
|
arc: JB2 H00R0000
|
|
arc: JB3 W1_H02E0101
|
|
arc: JB4 V02S0701
|
|
arc: JB5 W1_H02E0101
|
|
arc: JB6 V02S0701
|
|
arc: JB7 W1_H02E0101
|
|
arc: JCE3 E1_H02W0101
|
|
arc: JD0 W1_H02E0001
|
|
arc: JD1 H00R0000
|
|
arc: JD2 W1_H02E0001
|
|
arc: JD3 H00R0000
|
|
arc: JD4 W1_H02E0001
|
|
arc: JD5 V02S0401
|
|
arc: JD6 W1_H02E0001
|
|
arc: JD7 V02S0401
|
|
arc: JLSR0 H02E0501
|
|
arc: JLSR1 H02E0501
|
|
arc: N1_V02N0701 S1_V02N0701
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JC2MUX 0
|
|
enum: CIB.JA1MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
|
|
.tile CIB_R22C40:CIB_DSP
|
|
arc: S1_V02S0701 S3_V06N0203
|
|
arc: W1_H02W0501 W3_H06E0303
|
|
|
|
.tile CIB_R22C41:CIB_DSP
|
|
arc: E1_H02E0101 N1_V01S0100
|
|
arc: E1_H02E0301 V02N0301
|
|
arc: N1_V01N0101 N3_V06S0203
|
|
arc: S1_V02S0101 E1_H02W0101
|
|
arc: S1_V02S0201 E1_H02W0201
|
|
arc: S1_V02S0401 E1_H01W0000
|
|
arc: S1_V02S0501 E1_H02W0501
|
|
arc: S1_V02S0701 E1_H01W0100
|
|
arc: S3_V06S0203 N1_V01S0000
|
|
arc: W1_H02W0101 V02N0101
|
|
|
|
.tile CIB_R22C42:CIB_DSP
|
|
arc: E1_H01E0001 JF0
|
|
arc: E1_H01E0101 JQ0
|
|
arc: E1_H02E0001 V02S0001
|
|
arc: E1_H02E0101 N1_V01S0100
|
|
arc: E1_H02E0201 V01N0001
|
|
arc: E1_H02E0301 V01N0101
|
|
arc: E1_H02E0401 V02S0401
|
|
arc: E1_H02E0501 N1_V01S0100
|
|
arc: E1_H02E0601 JQ4
|
|
arc: E1_H02E0701 JQ5
|
|
arc: E3_H06E0103 JQ1
|
|
arc: H00L0100 H02E0301
|
|
arc: H00R0000 V02S0601
|
|
arc: H00R0100 V02N0501
|
|
arc: H01W0000 JF7
|
|
arc: H01W0100 JF1
|
|
arc: JB0 V02S0301
|
|
arc: JB1 H02E0101
|
|
arc: JB2 S1_V02N0301
|
|
arc: JB3 H00R0000
|
|
arc: JB4 S1_V02N0701
|
|
arc: JB5 S1_V02N0501
|
|
arc: JB6 V00T0000
|
|
arc: JB7 V02N0701
|
|
arc: JCE0 H00L0100
|
|
arc: JD0 V00T0100
|
|
arc: JD1 S1_V02N0001
|
|
arc: JD2 N1_V01S0000
|
|
arc: JD3 V00B0100
|
|
arc: JD4 N1_V02S0401
|
|
arc: JD5 V00B0000
|
|
arc: JD6 H00R0100
|
|
arc: JD7 V02N0401
|
|
arc: JLSR0 E1_H02W0501
|
|
arc: JLSR1 E1_H02W0501
|
|
arc: N1_V01N0001 JQ3
|
|
arc: N1_V02N0201 H06W0103
|
|
arc: N1_V02N0601 JF4
|
|
arc: N1_V02N0701 JQ7
|
|
arc: S1_V02S0001 JF2
|
|
arc: S1_V02S0101 JF3
|
|
arc: S1_V02S0201 JQ2
|
|
arc: S1_V02S0401 JQ6
|
|
arc: S1_V02S0501 JF5
|
|
arc: S1_V02S0601 JF6
|
|
arc: S1_V02S0701 E1_H01W0100
|
|
arc: S3_V06S0003 E1_H01W0000
|
|
arc: V00B0000 V02N0201
|
|
arc: V00B0100 V02N0301
|
|
arc: V00T0000 V02S0401
|
|
arc: V00T0100 N1_V02S0501
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JC2MUX 0
|
|
enum: CIB.JA1MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
enum: CIB.JC6MUX 0
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
enum: CIB.JC1MUX 0
|
|
enum: CIB.JA6MUX 0
|
|
enum: CIB.JC7MUX 0
|
|
enum: CIB.JA4MUX 0
|
|
enum: CIB.JC5MUX 0
|
|
enum: CIB.JA2MUX 0
|
|
enum: CIB.JC3MUX 0
|
|
enum: CIB.JA0MUX 0
|
|
|
|
.tile CIB_R22C43:CIB_DSP
|
|
arc: E1_H01E0001 JF4
|
|
arc: E1_H01E0101 JQ3
|
|
arc: E1_H02E0001 N1_V01S0000
|
|
arc: E1_H02E0101 V01N0101
|
|
arc: E1_H02E0201 V01N0001
|
|
arc: E1_H02E0301 N1_V01S0100
|
|
arc: E1_H02E0501 E1_H01W0100
|
|
arc: H00R0000 H02E0401
|
|
arc: H00R0100 H02E0501
|
|
arc: H01W0000 JQ4
|
|
arc: H01W0100 JF7
|
|
arc: JB0 H02E0101
|
|
arc: JB1 H02E0301
|
|
arc: JB2 H02E0101
|
|
arc: JB3 H02E0301
|
|
arc: JB4 H02E0101
|
|
arc: JB5 H02E0301
|
|
arc: JB6 H02E0101
|
|
arc: JB7 H02E0301
|
|
arc: JD0 V02N0001
|
|
arc: JD1 H00R0000
|
|
arc: JD2 H02E0201
|
|
arc: JD3 H00R0000
|
|
arc: JD4 H02E0201
|
|
arc: JD5 H00R0100
|
|
arc: JD6 H02E0201
|
|
arc: JD7 H00R0100
|
|
arc: JLSR1 V00T0100
|
|
arc: N1_V01N0001 JF3
|
|
arc: N1_V02N0001 JF2
|
|
arc: N1_V02N0201 JQ0
|
|
arc: N1_V02N0401 H06W0203
|
|
arc: N1_V02N0501 JQ7
|
|
arc: S1_V02S0001 JQ2
|
|
arc: S1_V02S0101 H01E0101
|
|
arc: S1_V02S0201 H01E0001
|
|
arc: S1_V02S0301 JQ1
|
|
arc: S1_V02S0401 JQ6
|
|
arc: S1_V02S0501 JQ5
|
|
arc: S1_V02S0601 JF6
|
|
arc: S1_V02S0701 H02E0701
|
|
arc: V00T0100 V02N0701
|
|
arc: V01S0100 S3_V06N0303
|
|
arc: W1_H02W0101 JF1
|
|
arc: W1_H02W0201 JF0
|
|
arc: W1_H02W0501 JF5
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JC2MUX 0
|
|
enum: CIB.JA1MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
enum: CIB.JC6MUX 0
|
|
enum: CIB.JC1MUX 0
|
|
enum: CIB.JA6MUX 0
|
|
enum: CIB.JC7MUX 0
|
|
enum: CIB.JA4MUX 0
|
|
enum: CIB.JC5MUX 0
|
|
|
|
.tile CIB_R22C44:CIB_DSP
|
|
arc: E1_H02E0201 V02N0201
|
|
arc: H00R0000 V02N0401
|
|
arc: H00R0100 V02S0501
|
|
arc: H01W0100 W3_H06E0303
|
|
arc: JB0 W1_H02E0101
|
|
arc: JB1 W1_H02E0301
|
|
arc: JB2 V02N0101
|
|
arc: JB3 H00R0000
|
|
arc: JB4 H02E0301
|
|
arc: JB5 V02N0701
|
|
arc: JB6 N1_V01S0000
|
|
arc: JB7 V02S0701
|
|
arc: JD0 W1_H02E0201
|
|
arc: JD1 V00B0100
|
|
arc: JD2 W1_H02E0001
|
|
arc: JD3 S1_V02N0201
|
|
arc: JD4 S1_V02N0601
|
|
arc: JD5 H02E0001
|
|
arc: JD6 N1_V02S0401
|
|
arc: JD7 H00R0100
|
|
arc: JLSR0 H02E0501
|
|
arc: JLSR1 H02E0501
|
|
arc: N1_V02N0401 H01E0001
|
|
arc: S1_V02S0001 S3_V06N0003
|
|
arc: S1_V02S0601 W1_H02E0601
|
|
arc: S1_V02S0701 H01E0101
|
|
arc: V00B0100 W1_H02E0501
|
|
arc: W1_H02W0501 W3_H06E0303
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
|
|
.tile CIB_R22C45:CIB_DSP
|
|
arc: H00R0100 V02N0501
|
|
arc: JB0 W1_H02E0101
|
|
arc: JB1 H00R0100
|
|
arc: JB2 W1_H02E0101
|
|
arc: JB3 H00R0100
|
|
arc: JB4 W1_H02E0101
|
|
arc: JB5 V02N0501
|
|
arc: JB6 W1_H02E0101
|
|
arc: JB7 V02N0501
|
|
arc: JD0 V02S0201
|
|
arc: JD1 V00B0100
|
|
arc: JD2 H02E0201
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arc: JD3 W1_H02E0201
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arc: JD4 H02E0201
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arc: JD5 W1_H02E0201
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arc: JD6 H02E0201
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arc: JD7 W1_H02E0201
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arc: S1_V02S0201 H06E0103
|
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arc: V00B0100 N1_V02S0101
|
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arc: W3_H06W0103 E3_H06W0103
|
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enum: CIB.JA3MUX 0
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enum: CIB.JC2MUX 0
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enum: CIB.JA1MUX 0
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enum: CIB.JC0MUX 0
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enum: CIB.JA7MUX 0
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.tile CIB_R22C46:CIB_DSP
|
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arc: H00R0000 V02N0401
|
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arc: H00R0100 V02N0701
|
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arc: JB0 V02N0101
|
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arc: JB1 H00R0100
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arc: JB2 V02N0101
|
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arc: JB3 H00R0100
|
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arc: JCE0 H00R0000
|
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arc: JCE1 H00R0000
|
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arc: JD0 W1_H02E0201
|
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arc: JD1 V02N0201
|
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arc: JD2 W1_H02E0201
|
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arc: JD3 V02N0201
|
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arc: W3_H06W0203 E1_H01W0000
|
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.tile CIB_R22C47:CIB_DSP
|
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arc: H01W0000 E3_H06W0103
|
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|
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.tile CIB_R22C51:CIB_DSP
|
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arc: W3_H06W0103 E3_H06W0103
|
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|
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.tile CIB_R22C53:CIB_DSP
|
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arc: W3_H06W0103 E3_H06W0003
|
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|
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.tile CIB_R22C57:CIB_DSP
|
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arc: W3_H06W0103 E3_H06W0103
|
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|
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.tile CIB_R22C59:CIB_DSP
|
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arc: W3_H06W0003 E3_H06W0003
|
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|
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.tile CIB_R22C63:CIB_DSP
|
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arc: W3_H06W0103 E3_H06W0103
|
|
|
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.tile CIB_R22C65:CIB_DSP
|
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arc: W3_H06W0003 E3_H06W0003
|
|
|
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.tile CIB_R22C69:CIB_DSP
|
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arc: W3_H06W0103 E3_H06W0003
|
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|
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.tile CIB_R22C71:CIB_DSP
|
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arc: W3_H06W0003 E3_H06W0003
|
|
|
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.tile CIB_R22C75:CIB_DSP
|
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arc: W3_H06W0003 E3_H06W0003
|
|
|
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.tile CIB_R22C77:CIB_DSP
|
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arc: W3_H06W0003 E3_H06W0003
|
|
|
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.tile CIB_R22C7:CIB_DSP
|
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arc: E3_H06E0303 W3_H06E0303
|
|
|
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.tile CIB_R22C81:CIB_DSP
|
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arc: W3_H06W0003 E3_H06W0303
|
|
|
|
.tile CIB_R22C83:CIB_DSP
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
|
|
.tile CIB_R22C87:CIB_DSP
|
|
arc: S3_V06S0303 N3_V06S0203
|
|
arc: W3_H06W0303 E1_H02W0501
|
|
|
|
.tile CIB_R22C89:CIB_LR_S
|
|
arc: W1_H02W0501 JF5
|
|
arc: W3_H06W0303 JQ5
|
|
|
|
.tile CIB_R23C1:CIB_LR
|
|
arc: E1_H02E0501 JF5
|
|
arc: E1_H02E0701 S1_V02N0701
|
|
arc: E3_H06E0003 S3_V06N0003
|
|
arc: E3_H06E0103 N1_V01S0100
|
|
arc: E3_H06E0303 JQ5
|
|
arc: V01S0100 S3_V06N0303
|
|
|
|
.tile CIB_R23C89:CIB_LR
|
|
arc: V01S0100 S3_V06N0303
|
|
arc: W1_H02W0701 JF5
|
|
arc: W3_H06W0003 S3_V06N0003
|
|
arc: W3_H06W0303 JQ5
|
|
|
|
.tile CIB_R24C1:CIB_LR
|
|
arc: E1_H02E0501 S1_V02N0501
|
|
arc: E3_H06E0103 N1_V01S0100
|
|
arc: E3_H06E0203 S3_V06N0203
|
|
arc: S3_V06S0003 H06W0003
|
|
arc: S3_V06S0103 E3_H06W0103
|
|
|
|
.tile CIB_R24C89:CIB_LR
|
|
arc: W3_H06W0303 N1_V01S0100
|
|
|
|
.tile CIB_R25C1:CIB_LR
|
|
arc: E3_H06E0003 S3_V06N0003
|
|
arc: E3_H06E0203 V01N0001
|
|
arc: E3_H06E0303 JF5
|
|
arc: N1_V02N0701 JQ5
|
|
|
|
.tile CIB_R25C89:CIB_LR
|
|
arc: H01W0000 JQ5
|
|
arc: W1_H02W0501 V06N0303
|
|
arc: W1_H02W0701 JF5
|
|
arc: W3_H06W0303 S3_V06N0303
|
|
|
|
.tile CIB_R26C1:CIB_LR
|
|
arc: E3_H06E0203 S3_V06N0203
|
|
arc: E3_H06E0303 S3_V06N0303
|
|
arc: N1_V01N0001 JF5
|
|
arc: N1_V02N0501 JQ5
|
|
arc: S1_V02S0501 E1_H02W0501
|
|
|
|
.tile CIB_R26C89:CIB_LR
|
|
arc: H01W0000 JQ5
|
|
arc: S1_V02S0701 H06E0203
|
|
arc: V01S0100 S3_V06N0303
|
|
arc: W3_H06W0003 S3_V06N0003
|
|
arc: W3_H06W0303 JF5
|
|
|
|
.tile CIB_R27C89:CIB_LR
|
|
arc: W3_H06W0103 N1_V01S0100
|
|
arc: W3_H06W0303 S3_V06N0303
|
|
|
|
.tile CIB_R28C1:CIB_LR
|
|
arc: E3_H06E0003 S3_V06N0003
|
|
arc: JA3 N1_V02S0501
|
|
arc: N3_V06N0303 JF5
|
|
enum: CIB.JB3MUX 0
|
|
|
|
.tile CIB_R28C89:CIB_LR
|
|
arc: JA3 N1_V02S0701
|
|
arc: N3_V06N0303 JF5
|
|
arc: W3_H06W0303 S3_V06N0303
|
|
enum: CIB.JB3MUX 0
|
|
|
|
.tile CIB_R29C1:CIB_LR
|
|
arc: E3_H06E0203 S3_V06N0203
|
|
arc: E3_H06E0303 JF5
|
|
arc: N3_V06N0003 S3_V06N0303
|
|
arc: N3_V06N0303 JQ5
|
|
arc: S1_V02S0701 H02W0701
|
|
|
|
.tile CIB_R29C89:CIB_LR
|
|
arc: N3_V06N0003 S3_V06N0303
|
|
arc: N3_V06N0303 JF5
|
|
arc: W3_H06W0303 JQ5
|
|
|
|
.tile CIB_R30C1:CIB_LR
|
|
arc: N3_V06N0203 S1_V02N0701
|
|
arc: S3_V06S0003 N3_V06S0003
|
|
arc: S3_V06S0103 H06W0103
|
|
arc: S3_V06S0203 N3_V06S0103
|
|
|
|
.tile CIB_R30C89:CIB_LR
|
|
arc: S1_V02S0401 H06E0203
|
|
|
|
.tile CIB_R31C1:CIB_LR
|
|
arc: JA0 N1_V02S0701
|
|
arc: JA3 E1_H02W0701
|
|
arc: N3_V06N0003 S3_V06N0303
|
|
enum: CIB.JB0MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
|
|
.tile CIB_R31C89:CIB_LR
|
|
arc: JA0 W1_H02E0701
|
|
arc: N3_V06N0303 JQ5
|
|
arc: W3_H06W0303 S3_V06N0303
|
|
enum: CIB.JB0MUX 0
|
|
|
|
.tile CIB_R32C1:CIB_LR
|
|
arc: E3_H06E0303 S3_V06N0303
|
|
arc: N1_V02N0701 JQ5
|
|
arc: N3_V06N0203 S3_V06N0203
|
|
arc: N3_V06N0303 JF5
|
|
arc: S3_V06S0203 H06W0203
|
|
|
|
.tile CIB_R32C89:CIB_LR
|
|
arc: N3_V06N0003 S3_V06N0303
|
|
arc: N3_V06N0303 JF5
|
|
arc: S1_V02S0501 N1_V02S0401
|
|
arc: W3_H06W0303 JQ5
|
|
|
|
.tile CIB_R33C89:CIB_LR
|
|
arc: N3_V06N0303 S1_V02N0601
|
|
|
|
.tile CIB_R34C13:CIB_EBR
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
|
|
.tile CIB_R34C16:CIB_EBR
|
|
arc: N1_V02N0201 S3_V06N0103
|
|
|
|
.tile CIB_R34C18:CIB_EBR
|
|
arc: N3_V06N0303 S3_V06N0303
|
|
|
|
.tile CIB_R34C19:CIB_EBR
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
|
|
.tile CIB_R34C1:CIB_LR_S
|
|
arc: E3_H06E0303 JQ5
|
|
arc: JA0 E1_H02W0501
|
|
arc: N3_V06N0003 S3_V06N0303
|
|
enum: CIB.JB0MUX 0
|
|
|
|
.tile CIB_R34C22:CIB_EBR
|
|
arc: N3_V06N0103 S3_V06N0003
|
|
|
|
.tile CIB_R34C23:CIB_EBR
|
|
arc: N3_V06N0303 S3_V06N0203
|
|
|
|
.tile CIB_R34C25:CIB_EBR
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
arc: N3_V06N0003 S3_V06N0303
|
|
arc: N3_V06N0303 S3_V06N0203
|
|
|
|
.tile CIB_R34C28:CIB_EBR
|
|
arc: N3_V06N0103 S3_V06N0003
|
|
arc: N3_V06N0303 S3_V06N0303
|
|
|
|
.tile CIB_R34C29:CIB_EBR
|
|
arc: N1_V02N0101 E3_H06W0103
|
|
arc: N3_V06N0103 S3_V06N0003
|
|
|
|
.tile CIB_R34C31:CIB_EBR
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
|
|
.tile CIB_R34C34:CIB_EBR
|
|
arc: N1_V02N0701 S3_V06N0203
|
|
arc: N3_V06N0003 S3_V06N0003
|
|
arc: N3_V06N0203 S3_V06N0103
|
|
|
|
.tile CIB_R34C35:CIB_EBR
|
|
arc: N1_V02N0001 S3_V06N0003
|
|
arc: N3_V06N0003 S3_V06N0303
|
|
arc: N3_V06N0103 S3_V06N0103
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
|
|
.tile CIB_R34C36:CIB_EBR
|
|
arc: N3_V06N0103 S3_V06N0103
|
|
arc: N3_V06N0303 S3_V06N0203
|
|
|
|
.tile CIB_R34C37:CIB_EBR
|
|
arc: N3_V06N0303 W3_H06E0303
|
|
|
|
.tile CIB_R34C3:CIB_EBR
|
|
arc: W1_H02W0501 N1_V01S0100
|
|
|
|
.tile CIB_R34C41:CIB_EBR
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
|
|
.tile CIB_R34C42:CIB_EBR
|
|
arc: N1_V02N0201 S3_V06N0103
|
|
arc: N3_V06N0003 S3_V06N0003
|
|
|
|
.tile CIB_R34C43:CIB_EBR
|
|
arc: N1_V02N0201 S3_V06N0103
|
|
arc: N3_V06N0203 S3_V06N0203
|
|
|
|
.tile CIB_R34C44:CIB_EBR
|
|
arc: N3_V06N0303 S3_V06N0203
|
|
|
|
.tile CIB_R34C47:CIB_EBR
|
|
arc: N3_V06N0303 S3_V06N0203
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
|
|
.tile CIB_R34C53:CIB_EBR
|
|
arc: W3_H06W0303 E3_H06W0203
|
|
|
|
.tile CIB_R34C59:CIB_EBR
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
|
|
.tile CIB_R34C65:CIB_EBR
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
|
|
.tile CIB_R34C71:CIB_EBR
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
|
|
.tile CIB_R34C77:CIB_EBR
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
|
|
.tile CIB_R34C7:CIB_EBR
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
|
|
.tile CIB_R34C83:CIB_EBR
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
|
|
.tile CIB_R34C87:CIB_EBR
|
|
arc: S3_V06S0303 N3_V06S0303
|
|
|
|
.tile CIB_R34C89:CIB_LR_S
|
|
arc: JA0 N1_V02S0501
|
|
arc: N3_V06N0303 JQ5
|
|
arc: W3_H06W0303 S3_V06N0303
|
|
enum: CIB.JB0MUX 0
|
|
|
|
.tile CIB_R35C1:CIB_LR
|
|
arc: E3_H06E0003 S3_V06N0003
|
|
arc: E3_H06E0303 JQ5
|
|
arc: JA0 E1_H02W0701
|
|
arc: N3_V06N0203 S1_V02N0701
|
|
arc: N3_V06N0303 S3_V06N0303
|
|
enum: CIB.JB0MUX 0
|
|
|
|
.tile CIB_R35C89:CIB_LR
|
|
arc: N1_V02N0601 S3_V06N0303
|
|
arc: N3_V06N0303 JF5
|
|
arc: W3_H06W0303 JQ5
|
|
|
|
.tile CIB_R36C1:CIB_LR
|
|
arc: E3_H06E0303 S3_V06N0303
|
|
arc: S3_V06S0003 N3_V06S0003
|
|
arc: S3_V06S0103 N3_V06S0103
|
|
arc: S3_V06S0303 N3_V06S0203
|
|
|
|
.tile CIB_R37C1:CIB_LR
|
|
arc: E3_H06E0303 S3_V06N0303
|
|
arc: N1_V02N0701 JQ5
|
|
arc: N3_V06N0303 JF5
|
|
|
|
.tile CIB_R37C89:CIB_LR
|
|
arc: H01W0100 JQ5
|
|
arc: N3_V06N0303 JF5
|
|
arc: W3_H06W0303 S3_V06N0303
|
|
|
|
.tile CIB_R38C1:CIB_LR
|
|
arc: E3_H06E0303 JQ5
|
|
arc: JA0 H02W0501
|
|
arc: N3_V06N0203 S1_V02N0701
|
|
arc: N3_V06N0303 S3_V06N0303
|
|
arc: S3_V06S0203 N3_V06S0203
|
|
enum: CIB.JB0MUX 0
|
|
|
|
.tile CIB_R38C89:CIB_LR
|
|
arc: N3_V06N0303 JQ5
|
|
arc: W1_H02W0701 JF5
|
|
arc: W3_H06W0303 S3_V06N0303
|
|
|
|
.tile CIB_R40C1:CIB_LR
|
|
arc: E3_H06E0003 S3_V06N0003
|
|
arc: E3_H06E0303 S3_V06N0303
|
|
arc: N1_V02N0701 JQ5
|
|
arc: N3_V06N0303 JF5
|
|
|
|
.tile CIB_R40C89:CIB_LR
|
|
arc: H01W0100 JQ5
|
|
arc: N3_V06N0303 JF5
|
|
arc: W3_H06W0003 S3_V06N0003
|
|
arc: W3_H06W0303 S3_V06N0303
|
|
|
|
.tile CIB_R41C1:CIB_LR
|
|
arc: E3_H06E0003 S3_V06N0003
|
|
arc: E3_H06E0203 S3_V06N0203
|
|
arc: E3_H06E0303 JQ5
|
|
arc: N3_V06N0003 S3_V06N0303
|
|
arc: N3_V06N0303 JF5
|
|
|
|
.tile CIB_R41C89:CIB_LR
|
|
arc: N3_V06N0303 S3_V06N0303
|
|
arc: W1_H02W0701 JF5
|
|
arc: W3_H06W0303 JQ5
|
|
|
|
.tile CIB_R42C1:CIB_LR
|
|
arc: N3_V06N0303 S1_V02N0501
|
|
arc: S3_V06S0003 N3_V06S0303
|
|
arc: S3_V06S0103 N3_V06S0003
|
|
arc: S3_V06S0203 N3_V06S0103
|
|
|
|
.tile CIB_R43C1:CIB_LR
|
|
arc: E3_H06E0303 JQ5
|
|
arc: JA0 V02N0701
|
|
arc: N3_V06N0303 S3_V06N0303
|
|
enum: CIB.JB0MUX 0
|
|
|
|
.tile CIB_R43C89:CIB_LR
|
|
arc: N3_V06N0303 JQ5
|
|
arc: W3_H06W0303 JF5
|
|
|
|
.tile CIB_R44C1:CIB_LR
|
|
arc: E3_H06E0303 S3_V06N0303
|
|
arc: N1_V02N0501 JQ5
|
|
arc: N1_V02N0701 N3_V06S0203
|
|
arc: N3_V06N0303 JF5
|
|
|
|
.tile CIB_R44C89:CIB_LR
|
|
arc: H01W0100 JQ5
|
|
arc: N3_V06N0303 JF5
|
|
arc: W3_H06W0303 S3_V06N0303
|
|
|
|
.tile CIB_R46C13:CIB_DSP
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
|
|
.tile CIB_R46C16:CIB_DSP
|
|
arc: N3_V06N0103 S3_V06N0103
|
|
|
|
.tile CIB_R46C18:CIB_DSP
|
|
arc: N3_V06N0303 S3_V06N0203
|
|
|
|
.tile CIB_R46C19:CIB_DSP
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
|
|
.tile CIB_R46C1:CIB_LR_S
|
|
arc: E3_H06E0303 JQ5
|
|
arc: N3_V06N0003 S3_V06N0303
|
|
arc: N3_V06N0303 JF5
|
|
|
|
.tile CIB_R46C22:CIB_DSP
|
|
arc: N3_V06N0303 S3_V06N0303
|
|
|
|
.tile CIB_R46C23:CIB_DSP
|
|
arc: N3_V06N0103 S3_V06N0103
|
|
|
|
.tile CIB_R46C25:CIB_DSP
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: N3_V06N0103 S3_V06N0103
|
|
arc: N3_V06N0303 S3_V06N0303
|
|
|
|
.tile CIB_R46C29:CIB_DSP
|
|
arc: N3_V06N0003 E3_H06W0003
|
|
|
|
.tile CIB_R46C31:CIB_DSP
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
|
|
.tile CIB_R46C34:CIB_DSP
|
|
arc: N3_V06N0103 H06E0103
|
|
arc: N3_V06N0203 S3_V06N0203
|
|
|
|
.tile CIB_R46C35:CIB_DSP
|
|
arc: N3_V06N0103 S3_V06N0003
|
|
arc: N3_V06N0303 S3_V06N0303
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
|
|
.tile CIB_R46C36:CIB_DSP
|
|
arc: N3_V06N0003 S3_V06N0303
|
|
arc: N3_V06N0103 S3_V06N0003
|
|
|
|
.tile CIB_R46C41:CIB_DSP
|
|
arc: W3_H06W0303 E3_H06W0203
|
|
|
|
.tile CIB_R46C42:CIB_DSP
|
|
arc: N3_V06N0103 S3_V06N0003
|
|
arc: N3_V06N0303 S3_V06N0203
|
|
|
|
.tile CIB_R46C43:CIB_DSP
|
|
arc: N3_V06N0103 H06W0103
|
|
arc: N3_V06N0203 S3_V06N0103
|
|
|
|
.tile CIB_R46C46:CIB_DSP
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
|
|
.tile CIB_R46C47:CIB_DSP
|
|
arc: N3_V06N0203 S3_V06N0203
|
|
arc: W3_H06W0203 E3_H06W0203
|
|
|
|
.tile CIB_R46C52:CIB_DSP
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
|
|
.tile CIB_R46C53:CIB_DSP
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
|
|
.tile CIB_R46C58:CIB_DSP
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
|
|
.tile CIB_R46C59:CIB_DSP
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
|
|
.tile CIB_R46C64:CIB_DSP
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
|
|
.tile CIB_R46C65:CIB_DSP
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
|
|
.tile CIB_R46C70:CIB_DSP
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
|
|
.tile CIB_R46C71:CIB_DSP
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
|
|
.tile CIB_R46C76:CIB_DSP
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
|
|
.tile CIB_R46C77:CIB_DSP
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
|
|
.tile CIB_R46C7:CIB_DSP
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
|
|
.tile CIB_R46C82:CIB_DSP
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
|
|
.tile CIB_R46C83:CIB_DSP
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
|
|
.tile CIB_R46C87:CIB_DSP
|
|
arc: S3_V06S0303 N3_V06S0303
|
|
|
|
.tile CIB_R46C88:CIB_DSP
|
|
arc: W3_H06W0003 E1_H01W0000
|
|
|
|
.tile CIB_R46C89:CIB_LR_S
|
|
arc: H01W0000 JQ5
|
|
arc: N3_V06N0003 S3_V06N0303
|
|
arc: N3_V06N0303 JF5
|
|
arc: W3_H06W0303 V06N0303
|
|
|
|
.tile CIB_R47C1:CIB_LR
|
|
arc: E3_H06E0303 JQ5
|
|
arc: N3_V06N0003 S3_V06N0303
|
|
arc: N3_V06N0203 S1_V02N0701
|
|
arc: N3_V06N0303 JF5
|
|
|
|
.tile CIB_R47C89:CIB_LR
|
|
arc: H01W0000 JQ5
|
|
arc: N3_V06N0303 JF5
|
|
arc: W3_H06W0303 S3_V06N0303
|
|
|
|
.tile CIB_R48C1:CIB_LR
|
|
arc: S3_V06S0003 N3_V06S0003
|
|
arc: S3_V06S0103 N3_V06S0103
|
|
arc: S3_V06S0203 N3_V06S0203
|
|
|
|
.tile CIB_R48C89:CIB_LR
|
|
arc: S1_V02S0501 H02E0501
|
|
|
|
.tile CIB_R49C1:CIB_LR
|
|
arc: E3_H06E0303 S3_V06N0303
|
|
arc: N1_V02N0701 JQ5
|
|
arc: N3_V06N0303 JF5
|
|
|
|
.tile CIB_R49C89:CIB_LR
|
|
arc: N3_V06N0303 JQ5
|
|
arc: W1_H02W0701 JF5
|
|
arc: W3_H06W0303 S3_V06N0303
|
|
|
|
.tile CIB_R50C1:CIB_LR
|
|
arc: E1_H02E0701 JF5
|
|
arc: E3_H06E0303 S3_V06N0303
|
|
arc: N3_V06N0303 JQ5
|
|
|
|
.tile CIB_R50C89:CIB_LR
|
|
arc: JA3 N1_V02S0501
|
|
arc: N3_V06N0303 JF5
|
|
arc: W3_H06W0303 S3_V06N0303
|
|
enum: CIB.JB3MUX 0
|
|
|
|
.tile CIB_R52C1:CIB_LR
|
|
arc: E3_H06E0303 S3_V06N0303
|
|
arc: JA0 E1_H02W0701
|
|
arc: N3_V06N0303 JQ5
|
|
enum: CIB.JB0MUX 0
|
|
|
|
.tile CIB_R52C89:CIB_LR
|
|
arc: JA0 W1_H02E0501
|
|
arc: N3_V06N0303 JQ5
|
|
arc: W3_H06W0303 S3_V06N0303
|
|
enum: CIB.JB0MUX 0
|
|
|
|
.tile CIB_R53C1:CIB_LR
|
|
arc: E3_H06E0303 S3_V06N0303
|
|
arc: H00L0000 V02N0001
|
|
arc: JA0 H00L0000
|
|
arc: N3_V06N0303 JQ5
|
|
enum: CIB.JB0MUX 0
|
|
|
|
.tile CIB_R53C89:CIB_LR
|
|
arc: N3_V06N0303 JF5
|
|
arc: W3_H06W0303 JQ5
|
|
|
|
.tile CIB_R54C1:CIB_LR
|
|
arc: N1_V02N0001 N3_V06S0003
|
|
arc: S1_V02S0101 N3_V06S0103
|
|
arc: S1_V02S0701 N3_V06S0203
|
|
|
|
.tile CIB_R55C1:CIB_LR
|
|
arc: E3_H06E0303 S3_V06N0303
|
|
arc: JA3 E1_H02W0701
|
|
arc: N3_V06N0303 JF5
|
|
enum: CIB.JB3MUX 0
|
|
|
|
.tile CIB_R55C89:CIB_LR
|
|
arc: H01W0100 JQ5
|
|
arc: N3_V06N0303 JF5
|
|
arc: W3_H06W0303 S3_V06N0303
|
|
|
|
.tile CIB_R56C1:CIB_LR
|
|
arc: H00L0100 N1_V02S0101
|
|
arc: JA3 H00L0100
|
|
arc: N3_V06N0303 JF5
|
|
arc: S1_V02S0701 N1_V02S0701
|
|
enum: CIB.JB3MUX 0
|
|
|
|
.tile CIB_R56C89:CIB_LR
|
|
arc: N3_V06N0303 JF5
|
|
arc: W3_H06W0303 JQ5
|
|
|
|
.tile CIB_R58C16:CIB_EBR
|
|
arc: N3_V06N0103 S3_V06N0003
|
|
|
|
.tile CIB_R58C18:CIB_EBR
|
|
arc: N3_V06N0203 S3_V06N0103
|
|
|
|
.tile CIB_R58C1:CIB_LR_S
|
|
arc: JA3 N1_V02S0701
|
|
arc: N3_V06N0303 JF5
|
|
enum: CIB.JB3MUX 0
|
|
|
|
.tile CIB_R58C22:CIB_EBR
|
|
arc: N3_V06N0303 S3_V06N0203
|
|
|
|
.tile CIB_R58C23:CIB_EBR
|
|
arc: N3_V06N0103 S3_V06N0003
|
|
|
|
.tile CIB_R58C25:CIB_EBR
|
|
arc: N3_V06N0203 S3_V06N0103
|
|
|
|
.tile CIB_R58C34:CIB_EBR
|
|
arc: N3_V06N0103 S3_V06N0103
|
|
|
|
.tile CIB_R58C35:CIB_EBR
|
|
arc: N1_V02N0401 S3_V06N0203
|
|
arc: N3_V06N0203 S3_V06N0103
|
|
arc: N3_V06N0303 E3_H06W0303
|
|
|
|
.tile CIB_R58C36:CIB_EBR
|
|
arc: N3_V06N0003 S3_V06N0303
|
|
arc: N3_V06N0303 S3_V06N0203
|
|
|
|
.tile CIB_R58C41:CIB_EBR
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
|
|
.tile CIB_R58C42:CIB_EBR
|
|
arc: N3_V06N0103 S3_V06N0103
|
|
arc: N3_V06N0303 S3_V06N0203
|
|
|
|
.tile CIB_R58C43:CIB_EBR
|
|
arc: N3_V06N0003 S3_V06N0003
|
|
|
|
.tile CIB_R58C47:CIB_EBR
|
|
arc: W3_H06W0303 E3_H06W0203
|
|
|
|
.tile CIB_R58C53:CIB_EBR
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
|
|
.tile CIB_R58C59:CIB_EBR
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
|
|
.tile CIB_R58C65:CIB_EBR
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
|
|
.tile CIB_R58C71:CIB_EBR
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
|
|
.tile CIB_R58C77:CIB_EBR
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
|
|
.tile CIB_R58C83:CIB_EBR
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
|
|
.tile CIB_R58C89:CIB_LR_S
|
|
arc: N3_V06N0303 JF5
|
|
arc: W3_H06W0303 JQ5
|
|
|
|
.tile CIB_R59C1:CIB_LR
|
|
arc: E3_H06E0303 JQ5
|
|
arc: N3_V06N0303 JF5
|
|
|
|
.tile CIB_R5C1:CIB_PLL1
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
|
|
.tile CIB_R5C89:CIB_PLL1
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
|
|
.tile CIB_R61C1:CIB_LR
|
|
arc: N3_V06N0303 JF5
|
|
|
|
.tile CIB_R61C89:CIB_LR
|
|
arc: N3_V06N0303 JQ5
|
|
arc: W3_H06W0303 JF5
|
|
|
|
.tile CIB_R70C10:CIB
|
|
arc: E3_H06E0003 JQ0
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
|
|
.tile CIB_R70C11:CIB
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: N3_V06N0003 JQ0
|
|
|
|
.tile CIB_R70C12:CIB
|
|
arc: E3_H06E0003 JQ0
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
|
|
.tile CIB_R70C13:CIB
|
|
arc: E3_H06E0003 JQ0
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
|
|
.tile CIB_R70C14:CIB
|
|
arc: E3_H06E0003 JQ0
|
|
|
|
.tile CIB_R70C15:CIB
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: N3_V06N0003 JQ0
|
|
|
|
.tile CIB_R70C16:CIB
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: N3_V06N0003 JQ0
|
|
|
|
.tile CIB_R70C17:CIB
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
|
|
.tile CIB_R70C18:CIB
|
|
arc: E3_H06E0003 JQ0
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: N3_V06N0003 H06E0003
|
|
|
|
.tile CIB_R70C19:CIB
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
|
|
.tile CIB_R70C20:CIB
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
|
|
.tile CIB_R70C22:CIB
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: N3_V06N0203 H06E0203
|
|
|
|
.tile CIB_R70C23:CIB
|
|
arc: N3_V06N0003 W3_H06E0003
|
|
|
|
.tile CIB_R70C24:CIB
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
|
|
.tile CIB_R70C25:CIB
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: N3_V06N0003 H06E0003
|
|
|
|
.tile CIB_R70C26:CIB
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
|
|
.tile CIB_R70C28:CIB
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
|
|
.tile CIB_R70C30:CIB
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
|
|
.tile CIB_R70C31:CIB
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
|
|
.tile CIB_R70C32:CIB
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
|
|
.tile CIB_R70C34:CIB
|
|
arc: N3_V06N0103 W3_H06E0103
|
|
|
|
.tile CIB_R70C35:CIB
|
|
arc: N3_V06N0103 H06E0103
|
|
|
|
.tile CIB_R70C36:CIB
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
arc: N3_V06N0103 W3_H06E0103
|
|
arc: N3_V06N0303 W3_H06E0303
|
|
|
|
.tile CIB_R70C37:CIB
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
|
|
.tile CIB_R70C3:CIB_PLL3
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
|
|
.tile CIB_R70C42:VCIB_DCU0
|
|
arc: N3_V06N0203 W3_H06E0203
|
|
enum: CIB.JA1MUX 0
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JC2MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
enum: CIB.JC6MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C43:VCIB_DCUA
|
|
arc: N3_V06N0003 W3_H06E0003
|
|
enum: CIB.JA1MUX 0
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JC2MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
enum: CIB.JC6MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C44:VCIB_DCUB
|
|
enum: CIB.JA1MUX 0
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JC2MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
enum: CIB.JC6MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C45:VCIB_DCUC
|
|
enum: CIB.JA1MUX 0
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JC2MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
enum: CIB.JC6MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C46:VCIB_DCUD
|
|
enum: CIB.JA1MUX 0
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JC2MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
enum: CIB.JC6MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C47:VCIB_DCUF
|
|
enum: CIB.JA1MUX 0
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JC2MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
enum: CIB.JC6MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C48:VCIB_DCU3
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
enum: CIB.JC6MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C49:VCIB_DCU2
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C4:CIB
|
|
arc: E3_H06E0003 JQ0
|
|
|
|
.tile CIB_R70C50:VCIB_DCUG
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C51:VCIB_DCUH
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C52:VCIB_DCUI
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C53:VCIB_DCU1
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
|
|
.tile CIB_R70C5:CIB
|
|
arc: E3_H06E0003 JQ0
|
|
|
|
.tile CIB_R70C69:VCIB_DCU0
|
|
enum: CIB.JA1MUX 0
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JC2MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
enum: CIB.JC6MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C6:CIB_EFB0
|
|
arc: E3_H06E0003 JQ0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JC6MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C70:VCIB_DCUA
|
|
enum: CIB.JA1MUX 0
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JC2MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
enum: CIB.JC6MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C71:VCIB_DCUB
|
|
enum: CIB.JA1MUX 0
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JC2MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
enum: CIB.JC6MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C72:VCIB_DCUC
|
|
enum: CIB.JA1MUX 0
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JC2MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
enum: CIB.JC6MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C73:VCIB_DCUD
|
|
enum: CIB.JA1MUX 0
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JC2MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
enum: CIB.JC6MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C74:VCIB_DCUF
|
|
enum: CIB.JA1MUX 0
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JC2MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
enum: CIB.JC6MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C75:VCIB_DCU3
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
enum: CIB.JC6MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C76:VCIB_DCU2
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C77:VCIB_DCUG
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C78:VCIB_DCUH
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C79:VCIB_DCUI
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C7:CIB_EFB1
|
|
arc: E3_H06E0003 JQ0
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JA4MUX 0
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JA6MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB4MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB6MUX 0
|
|
enum: CIB.JC3MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
enum: CIB.JC5MUX 0
|
|
enum: CIB.JD3MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD5MUX 0
|
|
|
|
.tile CIB_R70C80:VCIB_DCU1
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
|
|
.tile CIB_R70C87:CIB_PLL3
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
|
|
.tile CIB_R70C9:CIB
|
|
arc: E3_H06E0003 JQ0
|
|
|
|
.tile MIB_R0C11:PIOT0
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R0C12:PIOT1
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOB.HYSTERESIS ON
|
|
|
|
.tile MIB_R0C13:PIOT0
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOA.HYSTERESIS ON
|
|
|
|
.tile MIB_R0C14:PIOT1
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R0C15:PIOT0
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R0C16:PIOT1
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOB.HYSTERESIS ON
|
|
|
|
.tile MIB_R0C18:PIOT0
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R0C19:PIOT1
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOB.HYSTERESIS ON
|
|
|
|
.tile MIB_R0C20:PIOT0
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R0C21:PIOT1
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOB.HYSTERESIS ON
|
|
|
|
.tile MIB_R0C22:PIOT0
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R0C23:PIOT1
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOB.HYSTERESIS ON
|
|
|
|
.tile MIB_R0C24:PIOT0
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOA.HYSTERESIS ON
|
|
|
|
.tile MIB_R0C25:PIOT1
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOB.HYSTERESIS ON
|
|
|
|
.tile MIB_R0C27:PIOT0
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOA.HYSTERESIS ON
|
|
|
|
.tile MIB_R0C28:PIOT1
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOB.HYSTERESIS ON
|
|
|
|
.tile MIB_R0C29:PIOT0
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOA.HYSTERESIS ON
|
|
|
|
.tile MIB_R0C30:PIOT1
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOB.HYSTERESIS ON
|
|
|
|
.tile MIB_R0C31:PIOT0
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOA.HYSTERESIS ON
|
|
|
|
.tile MIB_R0C32:PIOT1
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOB.HYSTERESIS ON
|
|
|
|
.tile MIB_R0C33:PIOT0
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOA.HYSTERESIS ON
|
|
|
|
.tile MIB_R0C34:PIOT1
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOB.HYSTERESIS ON
|
|
|
|
.tile MIB_R0C36:PIOT0
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOA.HYSTERESIS ON
|
|
|
|
.tile MIB_R0C37:PIOT1
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOB.HYSTERESIS ON
|
|
|
|
.tile MIB_R0C38:PIOT0
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOA.HYSTERESIS ON
|
|
|
|
.tile MIB_R0C39:PIOT1
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOB.HYSTERESIS ON
|
|
|
|
.tile MIB_R0C3:BANKREF0
|
|
enum: BANK.VCCIO 3V3
|
|
|
|
.tile MIB_R0C40:TMID_0
|
|
arc: G_TDCC0CLKI G_JTRQPCLKCIB1
|
|
|
|
.tile MIB_R0C42:PIOT0
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOA.HYSTERESIS ON
|
|
|
|
.tile MIB_R0C43:PIOT1
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOB.HYSTERESIS ON
|
|
|
|
.tile MIB_R0C44:PIOT0
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOA.HYSTERESIS ON
|
|
|
|
.tile MIB_R0C45:PIOT1
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOB.HYSTERESIS ON
|
|
|
|
.tile MIB_R0C47:PIOT0
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOA.HYSTERESIS ON
|
|
|
|
.tile MIB_R0C48:PIOT1
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOB.HYSTERESIS ON
|
|
|
|
.tile MIB_R0C49:PIOT0
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOA.HYSTERESIS ON
|
|
|
|
.tile MIB_R0C50:PIOT1
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOB.HYSTERESIS ON
|
|
|
|
.tile MIB_R0C51:PIOT0
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOA.HYSTERESIS ON
|
|
|
|
.tile MIB_R0C52:PIOT1
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOB.HYSTERESIS ON
|
|
|
|
.tile MIB_R0C53:PIOT0
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R0C54:PIOT1
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOB.HYSTERESIS ON
|
|
|
|
.tile MIB_R0C56:PIOT0
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R0C57:PIOT1
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOB.HYSTERESIS ON
|
|
|
|
.tile MIB_R0C58:PIOT0
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOA.HYSTERESIS ON
|
|
|
|
.tile MIB_R0C59:PIOT1
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOB.HYSTERESIS ON
|
|
|
|
.tile MIB_R0C60:PIOT0
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R0C61:PIOT1
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R0C62:PIOT0
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOA.HYSTERESIS ON
|
|
|
|
.tile MIB_R0C63:PIOT1
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R0C65:PIOT0
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOA.HYSTERESIS ON
|
|
|
|
.tile MIB_R0C66:PIOT1
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R0C67:PIOT0
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOA.HYSTERESIS ON
|
|
|
|
.tile MIB_R0C68:PIOT1
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOB.HYSTERESIS ON
|
|
|
|
.tile MIB_R0C69:PIOT0
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOA.HYSTERESIS ON
|
|
|
|
.tile MIB_R0C70:PIOT1
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOB.HYSTERESIS ON
|
|
|
|
.tile MIB_R0C71:PIOT0
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R0C72:PIOT1
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOB.HYSTERESIS ON
|
|
|
|
.tile MIB_R0C87:BANKREF1
|
|
enum: BANK.VCCIO 3V3
|
|
|
|
.tile MIB_R0C9:PIOT0
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R10C0:BANKREF7
|
|
enum: BANK.VCCIO 3V3
|
|
|
|
.tile MIB_R10C12:EBR_SPINE_UL1
|
|
arc: G_VPTX0000 G_HPRX0000
|
|
|
|
.tile MIB_R10C30:EBR_SPINE_UL0
|
|
arc: G_VPTX0000 G_HPRX0000
|
|
|
|
.tile MIB_R10C40:CMUX_UL_0
|
|
arc: G_DCS0CLK0 G_VPFN0000
|
|
arc: G_ULPCLK0 G_VPFS0000
|
|
|
|
.tile MIB_R10C41:CMUX_UR_0
|
|
arc: G_DCS0CLK1 G_VPFN0000
|
|
arc: G_URPCLK0 G_VPFS0000
|
|
|
|
.tile MIB_R10C50:EBR_SPINE_UR0
|
|
arc: G_VPTX0000 G_HPRX0000
|
|
|
|
.tile MIB_R10C90:BANKREF2
|
|
enum: BANK.VCCIO 3V3
|
|
|
|
.tile MIB_R11C0:PICL0
|
|
arc: JDIB JPADDIB_PIO
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R12C0:PICL1
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOB.HYSTERESIS ON
|
|
|
|
.tile MIB_R14C0:PICL0
|
|
arc: JDIB JPADDIB_PIO
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R14C90:PICR0
|
|
arc: JDIA JPADDIA_PIO
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R15C0:PICL1_DQS0
|
|
enum: PIOD.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOD.HYSTERESIS ON
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOB.HYSTERESIS ON
|
|
enum: PIOC.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOC.HYSTERESIS ON
|
|
|
|
.tile MIB_R15C90:PICR1_DQS0
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOA.HYSTERESIS ON
|
|
enum: PIOD.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOD.HYSTERESIS ON
|
|
enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R16C0:PICL2_DQS1
|
|
enum: PIOD.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOC.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R16C90:PICR2_DQS1
|
|
enum: PIOD.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R17C0:PICL0_DQS2
|
|
arc: JDIA JPADDIA_PIO
|
|
arc: JDIB JPADDIB_PIO
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R17C90:PICR0_DQS2
|
|
arc: JDIA JPADDIA_PIO
|
|
arc: JDIB JPADDIB_PIO
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R18C0:PICL1_DQS3
|
|
enum: PIOD.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOD.HYSTERESIS ON
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOA.HYSTERESIS ON
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOB.HYSTERESIS ON
|
|
enum: PIOC.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOC.HYSTERESIS ON
|
|
|
|
.tile MIB_R18C90:PICR1_DQS3
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOB.HYSTERESIS ON
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOA.HYSTERESIS ON
|
|
enum: PIOC.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOC.HYSTERESIS ON
|
|
enum: PIOD.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOD.HYSTERESIS ON
|
|
|
|
.tile MIB_R19C0:PICL2
|
|
enum: PIOD.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOC.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R19C90:PICR2
|
|
enum: PIOC.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOD.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C11:PICT0
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C12:PICT1
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C13:PICT0
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C14:PICT1
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C15:PICT0
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C16:PICT1
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C18:PICT0
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C19:PICT1
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C20:PICT0
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C21:PICT1
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C22:PICT0
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C23:PICT1
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C24:PICT0
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C25:PICT1
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C27:PICT0
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C28:PICT1
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C29:PICT0
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C30:PICT1
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C31:PICT0
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C32:PICT1
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C33:PICT0
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C34:PICT1
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C36:PICT0
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C37:PICT1
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C38:PICT0
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C39:PICT1
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C42:PICT0
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C43:PICT1
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C44:PICT0
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C45:PICT1
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C47:PICT0
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C48:PICT1
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C49:PICT0
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C50:PICT1
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C51:PICT0
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C52:PICT1
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C53:PICT0
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C54:PICT1
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C56:PICT0
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C57:PICT1
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C58:PICT0
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C59:PICT1
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C60:PICT0
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C61:PICT1
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C62:PICT0
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C63:PICT1
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C65:PICT0
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C66:PICT1
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C67:PICT0
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C68:PICT1
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C69:PICT0
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C70:PICT1
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C71:PICT0
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C72:PICT1
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C9:PICT0
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R20C0:PICL0
|
|
arc: JDIA JPADDIA_PIO
|
|
arc: JDIB JPADDIB_PIO
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R20C90:PICR0
|
|
arc: JDIA JPADDIA_PIO
|
|
arc: JDIB JPADDIB_PIO
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R21C0:PICL1
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOA.HYSTERESIS ON
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOB.HYSTERESIS ON
|
|
enum: PIOC.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOC.HYSTERESIS ON
|
|
enum: PIOD.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOD.HYSTERESIS ON
|
|
|
|
.tile MIB_R21C90:PICR1
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOA.HYSTERESIS ON
|
|
enum: PIOC.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOC.HYSTERESIS ON
|
|
enum: PIOD.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOD.HYSTERESIS ON
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOB.HYSTERESIS ON
|
|
|
|
.tile MIB_R22C0:MIB_CIB_LR
|
|
enum: PIOC.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOD.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R22C22:MIB_DSP0
|
|
arc: JMULTA0 JMUIA0
|
|
arc: JMULTA1 JMUIA1
|
|
arc: JMULTA10 JMUIA10
|
|
arc: JMULTA11 JMUIA11
|
|
arc: JMULTA12 JMUIA12
|
|
arc: JMULTA13 JMUIA13
|
|
arc: JMULTA14 JMUIA14
|
|
arc: JMULTA15 JMUIA15
|
|
arc: JMULTA16 JMUIA16
|
|
arc: JMULTA17 JMUIA17
|
|
arc: JMULTA2 JMUIA2
|
|
arc: JMULTA3 JMUIA3
|
|
arc: JMULTA4 JMUIA4
|
|
arc: JMULTA5 JMUIA5
|
|
arc: JMULTA6 JMUIA6
|
|
arc: JMULTA7 JMUIA7
|
|
arc: JMULTA8 JMUIA8
|
|
arc: JMULTA9 JMUIA9
|
|
|
|
.tile MIB_R22C42:MIB_DSP0
|
|
arc: JMULTA0 JMUIA0
|
|
arc: JMULTA1 JMUIA1
|
|
arc: JMULTA10 JMUIA10
|
|
arc: JMULTA11 JMUIA11
|
|
arc: JMULTA12 JMUIA12
|
|
arc: JMULTA13 JMUIA13
|
|
arc: JMULTA14 JMUIA14
|
|
arc: JMULTA15 JMUIA15
|
|
arc: JMULTA16 JMUIA16
|
|
arc: JMULTA17 JMUIA17
|
|
arc: JMULTA2 JMUIA2
|
|
arc: JMULTA3 JMUIA3
|
|
arc: JMULTA4 JMUIA4
|
|
arc: JMULTA5 JMUIA5
|
|
arc: JMULTA6 JMUIA6
|
|
arc: JMULTA7 JMUIA7
|
|
arc: JMULTA8 JMUIA8
|
|
arc: JMULTA9 JMUIA9
|
|
|
|
.tile MIB_R22C90:MIB_CIB_LR_A
|
|
enum: PIOC.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOD.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R23C0:PICL0
|
|
arc: JDIA JPADDIA_PIO
|
|
arc: JDIB JPADDIB_PIO
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R23C90:PICR0
|
|
arc: JDIA JPADDIA_PIO
|
|
arc: JDIB JPADDIB_PIO
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R24C0:PICL1
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOB.HYSTERESIS ON
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOA.HYSTERESIS ON
|
|
enum: PIOD.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOD.HYSTERESIS ON
|
|
enum: PIOC.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOC.HYSTERESIS ON
|
|
|
|
.tile MIB_R24C90:PICR1
|
|
enum: PIOD.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOD.HYSTERESIS ON
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOB.HYSTERESIS ON
|
|
enum: PIOC.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOC.HYSTERESIS ON
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOA.HYSTERESIS ON
|
|
|
|
.tile MIB_R25C0:PICL2
|
|
enum: PIOD.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOC.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R25C90:PICR2
|
|
enum: PIOD.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOC.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R26C0:PICL0
|
|
arc: JDIA JPADDIA_PIO
|
|
arc: JDIB JPADDIB_PIO
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R26C90:PICR0
|
|
arc: JDIA JPADDIA_PIO
|
|
arc: JDIB JPADDIB_PIO
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R27C0:PICL1_DQS0
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOB.HYSTERESIS ON
|
|
enum: PIOD.BASE_TYPE OUTPUT_LVCMOS33
|
|
enum: PIOC.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOC.HYSTERESIS ON
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOA.HYSTERESIS ON
|
|
|
|
.tile MIB_R27C90:PICR1_DQS0
|
|
enum: PIOC.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOC.HYSTERESIS ON
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOA.HYSTERESIS ON
|
|
enum: PIOD.BASE_TYPE OUTPUT_LVCMOS33
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOB.HYSTERESIS ON
|
|
|
|
.tile MIB_R28C0:PICL2_DQS1
|
|
enum: PIOD.BASE_TYPE OUTPUT_LVCMOS33
|
|
enum: PIOC.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R28C90:PICR2_DQS1
|
|
enum: PIOC.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOD.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R29C0:PICL0_DQS2
|
|
arc: JDIA JPADDIA_PIO
|
|
arc: JDIB JPADDIB_PIO
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R29C90:PICR0_DQS2
|
|
arc: JDIA JPADDIA_PIO
|
|
arc: JDIB JPADDIB_PIO
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R30C0:PICL1_DQS3
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOA.HYSTERESIS ON
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOB.HYSTERESIS ON
|
|
enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33
|
|
enum: PIOD.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R30C90:PICR1_DQS3
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOA.HYSTERESIS ON
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOB.HYSTERESIS ON
|
|
enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33
|
|
enum: PIOD.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOD.HYSTERESIS ON
|
|
|
|
.tile MIB_R31C0:PICL2
|
|
enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33
|
|
enum: PIOD.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R31C90:PICR2
|
|
enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33
|
|
enum: PIOD.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R32C0:PICL0
|
|
arc: JDIA JPADDIA_PIO
|
|
arc: JDIB JPADDIB_PIO
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R32C90:PICR0
|
|
arc: JDIA JPADDIA_PIO
|
|
arc: JDIB JPADDIB_PIO
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R33C0:PICL1
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOB.HYSTERESIS ON
|
|
enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOA.HYSTERESIS ON
|
|
enum: PIOD.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOD.HYSTERESIS ON
|
|
|
|
.tile MIB_R33C90:PICR1
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOA.HYSTERESIS ON
|
|
enum: PIOD.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOD.HYSTERESIS ON
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOB.HYSTERESIS ON
|
|
enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R34C0:MIB_CIB_LR
|
|
enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33
|
|
enum: PIOD.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R34C90:MIB_CIB_LR_A
|
|
enum: PIOD.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R35C0:PICL0
|
|
arc: JDIB JPADDIB_PIO
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R35C90:PICR0
|
|
arc: JDIA JPADDIA_PIO
|
|
arc: JDIB JPADDIB_PIO
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R36C0:PICL1
|
|
enum: PIOC.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOC.HYSTERESIS ON
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
enum: PIOD.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOD.HYSTERESIS ON
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOB.HYSTERESIS ON
|
|
|
|
.tile MIB_R36C90:PICR1
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOA.HYSTERESIS ON
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOB.HYSTERESIS ON
|
|
enum: PIOD.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOD.HYSTERESIS ON
|
|
enum: PIOC.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOC.HYSTERESIS ON
|
|
|
|
.tile MIB_R37C0:PICL2
|
|
enum: PIOC.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOD.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R37C90:PICR2
|
|
enum: PIOD.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOC.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R38C0:PICL0
|
|
arc: JDIB JPADDIB_PIO
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R38C90:PICR0
|
|
arc: JDIA JPADDIA_PIO
|
|
arc: JDIB JPADDIB_PIO
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R39C0:PICL1_DQS0
|
|
enum: PIOD.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOD.HYSTERESIS ON
|
|
enum: PIOC.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOC.HYSTERESIS ON
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOB.HYSTERESIS ON
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R39C90:PICR1_DQS0
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOB.HYSTERESIS ON
|
|
enum: PIOD.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOD.HYSTERESIS ON
|
|
enum: PIOC.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOC.HYSTERESIS ON
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOA.HYSTERESIS ON
|
|
|
|
.tile MIB_R40C0:PICL2_DQS1
|
|
enum: PIOD.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOC.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R40C90:PICR2_DQS1
|
|
enum: PIOD.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOC.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R41C0:PICL0_DQS2
|
|
arc: JDIA JPADDIA_PIO
|
|
arc: JDIB JPADDIB_PIO
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R41C90:PICR0_DQS2
|
|
arc: JDIA JPADDIA_PIO
|
|
arc: JDIB JPADDIB_PIO
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R42C0:PICL1_DQS3
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOB.HYSTERESIS ON
|
|
enum: PIOD.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOD.HYSTERESIS ON
|
|
enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOA.HYSTERESIS ON
|
|
|
|
.tile MIB_R42C90:PICR1_DQS3
|
|
enum: PIOD.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOD.HYSTERESIS ON
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOB.HYSTERESIS ON
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOA.HYSTERESIS ON
|
|
enum: PIOC.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOC.HYSTERESIS ON
|
|
|
|
.tile MIB_R43C0:PICL2
|
|
enum: PIOD.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R43C90:PICR2
|
|
enum: PIOD.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOC.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R44C0:PICL0
|
|
arc: JDIA JPADDIA_PIO
|
|
arc: JDIB JPADDIB_PIO
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R44C90:PICR0
|
|
arc: JDIA JPADDIA_PIO
|
|
arc: JDIB JPADDIB_PIO
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R45C0:PICL1
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOB.HYSTERESIS ON
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOA.HYSTERESIS ON
|
|
enum: PIOC.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOC.HYSTERESIS ON
|
|
enum: PIOD.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOD.HYSTERESIS ON
|
|
|
|
.tile MIB_R45C90:PICR1
|
|
enum: PIOC.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOC.HYSTERESIS ON
|
|
enum: PIOD.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOD.HYSTERESIS ON
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOB.HYSTERESIS ON
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOA.HYSTERESIS ON
|
|
|
|
.tile MIB_R46C0:MIB_CIB_LR
|
|
enum: PIOC.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOD.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R46C90:MIB_CIB_LR_A
|
|
enum: PIOC.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOD.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R47C0:PICL0
|
|
arc: JDIA JPADDIA_PIO
|
|
arc: JDIB JPADDIB_PIO
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R47C90:PICR0
|
|
arc: JDIA JPADDIA_PIO
|
|
arc: JDIB JPADDIB_PIO
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R48C0:PICL1
|
|
enum: PIOD.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOD.HYSTERESIS ON
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOA.HYSTERESIS ON
|
|
enum: PIOC.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOC.HYSTERESIS ON
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOB.HYSTERESIS ON
|
|
|
|
.tile MIB_R48C90:PICR1
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOB.HYSTERESIS ON
|
|
enum: PIOD.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOD.HYSTERESIS ON
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOA.HYSTERESIS ON
|
|
enum: PIOC.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOC.HYSTERESIS ON
|
|
|
|
.tile MIB_R49C0:PICL2
|
|
enum: PIOD.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOC.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R49C90:PICR2
|
|
enum: PIOD.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOC.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R50C0:PICL0
|
|
arc: JDIA JPADDIA_PIO
|
|
arc: JDIB JPADDIB_PIO
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R50C90:PICR0
|
|
arc: JDIA JPADDIA_PIO
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R51C0:PICL1_DQS0
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOA.HYSTERESIS ON
|
|
enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33
|
|
enum: PIOD.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOD.HYSTERESIS ON
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOB.HYSTERESIS ON
|
|
|
|
.tile MIB_R51C90:PICR1_DQS0
|
|
enum: PIOD.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOD.HYSTERESIS ON
|
|
enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOA.HYSTERESIS ON
|
|
|
|
.tile MIB_R52C0:PICL2_DQS1
|
|
enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33
|
|
enum: PIOD.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R52C90:PICR2_DQS1
|
|
enum: PIOD.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R53C0:PICL0_DQS2
|
|
arc: JDIB JPADDIB_PIO
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R53C90:PICR0_DQS2
|
|
arc: JDIA JPADDIA_PIO
|
|
arc: JDIB JPADDIB_PIO
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R54C0:PICL1_DQS3
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOB.HYSTERESIS ON
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
enum: PIOD.BASE_TYPE OUTPUT_LVCMOS33
|
|
enum: PIOC.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOC.HYSTERESIS ON
|
|
|
|
.tile MIB_R54C90:PICR1_DQS3
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOA.HYSTERESIS ON
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOB.HYSTERESIS ON
|
|
enum: PIOC.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOC.HYSTERESIS ON
|
|
enum: PIOD.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOD.HYSTERESIS ON
|
|
|
|
.tile MIB_R55C0:PICL2
|
|
enum: PIOD.BASE_TYPE OUTPUT_LVCMOS33
|
|
enum: PIOC.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R55C90:PICR2
|
|
enum: PIOC.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOD.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R56C0:PICL0
|
|
arc: JDIA JPADDIA_PIO
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R56C90:PICR0
|
|
arc: JDIA JPADDIA_PIO
|
|
arc: JDIB JPADDIB_PIO
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R57C0:PICL1
|
|
enum: PIOC.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOC.HYSTERESIS ON
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
enum: PIOD.BASE_TYPE OUTPUT_LVCMOS33
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOA.HYSTERESIS ON
|
|
|
|
.tile MIB_R57C90:PICR1
|
|
enum: PIOD.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOD.HYSTERESIS ON
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOB.HYSTERESIS ON
|
|
enum: PIOC.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOC.HYSTERESIS ON
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOA.HYSTERESIS ON
|
|
|
|
.tile MIB_R58C0:MIB_CIB_LR
|
|
enum: PIOC.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOD.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R58C40:CMUX_LL_0
|
|
arc: G_DCS1CLK0 G_VPFN0000
|
|
arc: G_LLPCLK0 G_VPFS0000
|
|
|
|
.tile MIB_R58C41:CMUX_LR_0
|
|
arc: G_DCS1CLK1 G_VPFN0000
|
|
arc: G_LRPCLK0 G_VPFS0000
|
|
|
|
.tile MIB_R58C90:MIB_CIB_LR_A
|
|
enum: PIOD.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOC.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R59C0:PICL0
|
|
arc: JDIA JPADDIA_PIO
|
|
arc: JDIB JPADDIB_PIO
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R60C0:PICL1
|
|
enum: PIOC.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOC.HYSTERESIS ON
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOA.HYSTERESIS ON
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOB.HYSTERESIS ON
|
|
|
|
.tile MIB_R60C90:PICR1
|
|
enum: PIOC.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOC.HYSTERESIS ON
|
|
enum: PIOD.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOD.HYSTERESIS ON
|
|
|
|
.tile MIB_R61C0:PICL2
|
|
enum: PIOC.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R61C90:PICR2
|
|
enum: PIOC.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOD.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R71C10:PICB1
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
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enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
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enum: PIOB.HYSTERESIS ON
|
|
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.tile MIB_R71C11:PICB0
|
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arc: JDIA JPADDIA_PIO
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
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enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOA.HYSTERESIS ON
|
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.tile MIB_R71C12:PICB1
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
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enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOB.HYSTERESIS ON
|
|
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.tile MIB_R71C13:PICB0
|
|
arc: JDIA JPADDIA_PIO
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOA.HYSTERESIS ON
|
|
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.tile MIB_R71C14:PICB1
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
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enum: PIOB.HYSTERESIS ON
|
|
|
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.tile MIB_R71C15:PICB0
|
|
arc: JDIA JPADDIA_PIO
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOA.HYSTERESIS ON
|
|
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.tile MIB_R71C16:PICB1
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOB.HYSTERESIS ON
|
|
|
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.tile MIB_R71C18:SPICB0
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOA.HYSTERESIS ON
|
|
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.tile MIB_R71C1:BANKREF6
|
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enum: BANK.VCCIO 3V3
|
|
|
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.tile MIB_R71C4:EFB0_PICB0
|
|
arc: JDIA JPADDIA_PIO
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOA.HYSTERESIS ON
|
|
unknown: F54B1
|
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unknown: F56B1
|
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unknown: F82B1
|
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unknown: F94B1
|
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.tile MIB_R71C5:EFB1_PICB1
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOB.HYSTERESIS ON
|
|
|
|
.tile MIB_R71C6:EFB2_PICB0
|
|
arc: JDIA JPADDIA_PIO
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOA.HYSTERESIS ON
|
|
|
|
.tile MIB_R71C7:EFB3_PICB1
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOB.HYSTERESIS ON
|
|
|
|
.tile MIB_R71C89:BANKREF3
|
|
enum: BANK.VCCIO 3V3
|
|
|
|
.tile MIB_R71C9:PICB0
|
|
arc: JDIA JPADDIA_PIO
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOA.HYSTERESIS ON
|
|
|
|
.tile R11C13:PLC2
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: N3_V06N0203 S3_V06N0103
|
|
|
|
.tile R11C14:PLC2
|
|
arc: N1_V02N0401 S3_V06N0203
|
|
|
|
.tile R11C18:PLC2
|
|
arc: N1_V02N0601 S3_V06N0303
|
|
arc: N3_V06N0203 S3_V06N0103
|
|
|
|
.tile R11C19:PLC2
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
|
|
.tile R11C25:PLC2
|
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arc: E3_H06E0103 W3_H06E0103
|
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|
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.tile R11C31:PLC2
|
|
arc: E3_H06E0103 W3_H06E0103
|
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.tile R11C37:PLC2
|
|
arc: N1_V02N0101 W3_H06E0103
|
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.tile R11C57:PLC2
|
|
arc: N1_V02N0701 S3_V06N0203
|
|
|
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.tile R11C60:PLC2
|
|
arc: N1_V02N0301 S3_V06N0003
|
|
arc: N1_V02N0501 S3_V06N0303
|
|
|
|
.tile R11C61:PLC2
|
|
arc: N1_V02N0301 S3_V06N0003
|
|
|
|
.tile R11C64:PLC2
|
|
arc: N3_V06N0203 S3_V06N0103
|
|
|
|
.tile R11C7:PLC2
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
|
|
.tile R12C19:PLC2
|
|
arc: N3_V06N0303 S3_V06N0203
|
|
|
|
.tile R12C70:PLC2
|
|
arc: N3_V06N0203 S3_V06N0103
|
|
|
|
.tile R13C18:PLC2
|
|
arc: S3_V06S0103 N3_V06S0003
|
|
|
|
.tile R13C21:PLC2
|
|
arc: S3_V06S0103 N3_V06S0103
|
|
|
|
.tile R13C22:PLC2
|
|
arc: S3_V06S0003 N3_V06S0003
|
|
arc: S3_V06S0203 N3_V06S0103
|
|
arc: S3_V06S0303 N3_V06S0303
|
|
|
|
.tile R13C23:PLC2
|
|
arc: S3_V06S0303 N3_V06S0303
|
|
|
|
.tile R13C24:PLC2
|
|
arc: S3_V06S0203 N3_V06S0103
|
|
|
|
.tile R13C25:PLC2
|
|
arc: S3_V06S0203 N3_V06S0103
|
|
|
|
.tile R13C26:PLC2
|
|
arc: S3_V06S0103 N3_V06S0103
|
|
|
|
.tile R13C27:PLC2
|
|
arc: S3_V06S0003 N3_V06S0303
|
|
arc: S3_V06S0203 N3_V06S0103
|
|
arc: S3_V06S0303 N3_V06S0203
|
|
|
|
.tile R13C28:PLC2
|
|
arc: S3_V06S0003 N3_V06S0303
|
|
arc: S3_V06S0103 N3_V06S0103
|
|
arc: S3_V06S0303 N3_V06S0203
|
|
|
|
.tile R13C29:PLC2
|
|
arc: S3_V06S0203 N3_V06S0103
|
|
|
|
.tile R13C30:PLC2
|
|
arc: S3_V06S0003 N3_V06S0303
|
|
arc: S3_V06S0103 N3_V06S0003
|
|
|
|
.tile R13C31:PLC2
|
|
arc: S3_V06S0203 N3_V06S0103
|
|
arc: S3_V06S0303 N3_V06S0303
|
|
|
|
.tile R13C32:PLC2
|
|
arc: S3_V06S0003 N3_V06S0003
|
|
|
|
.tile R13C34:PLC2
|
|
arc: S3_V06S0003 N3_V06S0003
|
|
|
|
.tile R13C35:PLC2
|
|
arc: S3_V06S0103 N3_V06S0003
|
|
arc: S3_V06S0203 N3_V06S0203
|
|
arc: S3_V06S0303 N3_V06S0303
|
|
|
|
.tile R13C36:PLC2
|
|
arc: S1_V02S0001 N3_V06S0003
|
|
arc: S3_V06S0003 N3_V06S0303
|
|
arc: S3_V06S0103 N3_V06S0103
|
|
arc: S3_V06S0203 N3_V06S0203
|
|
|
|
.tile R13C37:PLC2
|
|
arc: S3_V06S0103 N3_V06S0103
|
|
arc: S3_V06S0303 N3_V06S0203
|
|
|
|
.tile R13C41:PLC2
|
|
arc: S3_V06S0103 N3_V06S0103
|
|
|
|
.tile R13C42:PLC2
|
|
arc: S3_V06S0103 N3_V06S0003
|
|
arc: S3_V06S0203 N3_V06S0103
|
|
|
|
.tile R13C43:PLC2
|
|
arc: S3_V06S0203 N3_V06S0203
|
|
|
|
.tile R13C44:PLC2
|
|
arc: S3_V06S0003 N3_V06S0003
|
|
arc: S3_V06S0203 N3_V06S0103
|
|
arc: S3_V06S0303 N3_V06S0303
|
|
|
|
.tile R13C45:PLC2
|
|
arc: S3_V06S0103 N3_V06S0003
|
|
|
|
.tile R14C13:PLC2
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
|
|
.tile R14C19:PLC2
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
|
|
.tile R14C25:PLC2
|
|
arc: S3_V06S0303 W3_H06E0303
|
|
|
|
.tile R14C38:PLC2
|
|
arc: E3_H06E0303 S3_V06N0303
|
|
arc: S3_V06S0103 H06W0103
|
|
|
|
.tile R14C41:PLC2
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
|
|
.tile R14C44:PLC2
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
|
|
.tile R14C47:PLC2
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
|
|
.tile R14C50:PLC2
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
|
|
.tile R14C53:PLC2
|
|
arc: N3_V06N0203 S3_V06N0203
|
|
arc: W3_H06W0303 E3_H06W0203
|
|
|
|
.tile R14C56:PLC2
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
|
|
.tile R14C59:PLC2
|
|
arc: W3_H06W0203 E3_H06W0203
|
|
|
|
.tile R14C62:PLC2
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
|
|
.tile R14C65:PLC2
|
|
arc: W3_H06W0203 E3_H06W0203
|
|
|
|
.tile R14C68:PLC2
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
|
|
.tile R14C71:PLC2
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
|
|
.tile R14C74:PLC2
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
|
|
.tile R14C77:PLC2
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
|
|
.tile R14C7:PLC2
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
|
|
.tile R14C80:PLC2
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
|
|
.tile R14C83:PLC2
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
|
|
.tile R14C86:PLC2
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
|
|
.tile R15C10:PLC2
|
|
arc: N3_V06N0303 S3_V06N0303
|
|
|
|
.tile R15C27:PLC2
|
|
arc: S3_V06S0103 N3_V06S0103
|
|
|
|
.tile R15C28:PLC2
|
|
arc: S3_V06S0203 N3_V06S0203
|
|
|
|
.tile R15C36:PLC2
|
|
arc: S3_V06S0003 N1_V02S0001
|
|
|
|
.tile R16C13:PLC2
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
|
|
.tile R16C19:PLC2
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
|
|
.tile R16C22:PLC2
|
|
arc: S3_V06S0203 H06E0203
|
|
|
|
.tile R16C24:PLC2
|
|
arc: N3_V06N0303 E3_H06W0303
|
|
arc: S3_V06S0303 E3_H06W0303
|
|
|
|
.tile R16C30:PLC2
|
|
arc: E3_H06E0303 F6
|
|
arc: F6 F6_SLICE
|
|
arc: S3_V06S0303 F6
|
|
arc: W3_H06W0303 F6
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
|
|
.tile R16C36:PLC2
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
arc: S3_V06S0303 W3_H06E0303
|
|
|
|
.tile R16C41:PLC2
|
|
arc: S3_V06S0203 E3_H06W0203
|
|
|
|
.tile R16C42:PLC2
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
|
|
.tile R16C47:PLC2
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
|
|
.tile R16C48:PLC2
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
|
|
.tile R16C53:PLC2
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
|
|
.tile R16C54:PLC2
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
|
|
.tile R16C59:PLC2
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
|
|
.tile R16C60:PLC2
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
|
|
.tile R16C65:PLC2
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
|
|
.tile R16C66:PLC2
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
|
|
.tile R16C71:PLC2
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
|
|
.tile R16C72:PLC2
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
|
|
.tile R16C77:PLC2
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
|
|
.tile R16C78:PLC2
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
|
|
.tile R16C7:PLC2
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
|
|
.tile R16C83:PLC2
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
|
|
.tile R16C84:PLC2
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
|
|
.tile R16C87:PLC2
|
|
arc: S3_V06S0203 H06E0203
|
|
|
|
.tile R17C13:PLC2
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: N3_V06N0103 S3_V06N0003
|
|
|
|
.tile R17C14:PLC2
|
|
arc: N3_V06N0203 S3_V06N0203
|
|
|
|
.tile R17C18:PLC2
|
|
arc: N3_V06N0103 S3_V06N0103
|
|
arc: N3_V06N0303 S3_V06N0303
|
|
|
|
.tile R17C19:PLC2
|
|
arc: S3_V06S0003 W3_H06E0003
|
|
|
|
.tile R17C29:PLC2
|
|
arc: S1_V02S0401 E3_H06W0203
|
|
|
|
.tile R17C35:PLC2
|
|
arc: W3_H06W0203 E3_H06W0203
|
|
|
|
.tile R17C41:PLC2
|
|
arc: W3_H06W0203 E3_H06W0203
|
|
|
|
.tile R17C46:PLC2
|
|
arc: E3_H06E0003 S3_V06N0003
|
|
|
|
.tile R17C47:PLC2
|
|
arc: W3_H06W0203 E3_H06W0203
|
|
|
|
.tile R17C52:PLC2
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
|
|
.tile R17C53:PLC2
|
|
arc: W3_H06W0203 E3_H06W0203
|
|
|
|
.tile R17C57:PLC2
|
|
arc: N3_V06N0203 S3_V06N0103
|
|
|
|
.tile R17C58:PLC2
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
|
|
.tile R17C59:PLC2
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
|
|
.tile R17C60:PLC2
|
|
arc: N3_V06N0003 S3_V06N0003
|
|
arc: N3_V06N0303 S3_V06N0303
|
|
|
|
.tile R17C61:PLC2
|
|
arc: N3_V06N0003 H06E0003
|
|
|
|
.tile R17C64:PLC2
|
|
arc: N3_V06N0103 S3_V06N0103
|
|
|
|
.tile R17C65:PLC2
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
|
|
.tile R17C71:PLC2
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
|
|
.tile R17C77:PLC2
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
|
|
.tile R17C7:PLC2
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
|
|
.tile R17C83:PLC2
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
|
|
.tile R18C19:PLC2
|
|
arc: N3_V06N0203 S3_V06N0203
|
|
|
|
.tile R18C40:PLC2
|
|
arc: E3_H06E0303 S3_V06N0303
|
|
|
|
.tile R18C46:PLC2
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
|
|
.tile R18C52:PLC2
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
|
|
.tile R18C58:PLC2
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
|
|
.tile R18C64:PLC2
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
|
|
.tile R18C70:PLC2
|
|
arc: N3_V06N0103 W3_H06E0103
|
|
|
|
.tile R19C13:PLC2
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
|
|
.tile R19C18:PLC2
|
|
arc: S3_V06S0203 N3_V06S0103
|
|
|
|
.tile R19C19:PLC2
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
|
|
.tile R19C21:PLC2
|
|
arc: S1_V02S0201 N3_V06S0103
|
|
|
|
.tile R19C22:PLC2
|
|
arc: S1_V02S0001 N3_V06S0003
|
|
arc: S1_V02S0401 N3_V06S0203
|
|
arc: S1_V02S0601 N3_V06S0303
|
|
|
|
.tile R19C23:PLC2
|
|
arc: S1_V02S0501 N3_V06S0303
|
|
|
|
.tile R19C24:PLC2
|
|
arc: S1_V02S0401 N3_V06S0203
|
|
|
|
.tile R19C25:PLC2
|
|
arc: E1_H02E0701 N3_V06S0203
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
arc: S1_V02S0501 E1_H02W0501
|
|
|
|
.tile R19C26:PLC2
|
|
arc: S1_V02S0201 N3_V06S0103
|
|
|
|
.tile R19C27:PLC2
|
|
arc: S1_V02S0001 H02W0001
|
|
arc: S1_V02S0401 N3_V06S0203
|
|
arc: S1_V02S0701 W1_H02E0701
|
|
arc: S3_V06S0003 N3_V06S0003
|
|
arc: W1_H02W0501 N3_V06S0303
|
|
|
|
.tile R19C28:PLC2
|
|
arc: S1_V02S0301 S3_V06N0003
|
|
arc: S3_V06S0303 N3_V06S0303
|
|
arc: V01S0000 N3_V06S0103
|
|
arc: W1_H02W0001 N3_V06S0003
|
|
|
|
.tile R19C29:PLC2
|
|
arc: S1_V02S0501 N1_V02S0401
|
|
arc: S1_V02S0701 N3_V06S0203
|
|
|
|
.tile R19C30:PLC2
|
|
arc: S1_V02S0201 N3_V06S0103
|
|
arc: S1_V02S0301 N3_V06S0003
|
|
|
|
.tile R19C31:PLC2
|
|
arc: E1_H01E0101 W3_H06E0203
|
|
arc: E1_H02E0401 N3_V06S0203
|
|
arc: S1_V02S0601 N3_V06S0303
|
|
|
|
.tile R19C32:PLC2
|
|
arc: E3_H06E0103 H01E0101
|
|
arc: S1_V02S0001 N3_V06S0003
|
|
arc: S1_V02S0401 H02E0401
|
|
|
|
.tile R19C33:PLC2
|
|
arc: S1_V02S0401 E1_H02W0401
|
|
|
|
.tile R19C34:PLC2
|
|
arc: S1_V02S0301 N3_V06S0003
|
|
|
|
.tile R19C35:PLC2
|
|
arc: S1_V02S0101 H06E0103
|
|
arc: S1_V02S0201 H02W0201
|
|
arc: S1_V02S0401 N3_V06S0203
|
|
arc: S1_V02S0601 N3_V06S0303
|
|
arc: S3_V06S0203 N3_V06S0103
|
|
arc: W1_H02W0401 E3_H06W0203
|
|
|
|
.tile R19C36:PLC2
|
|
arc: S1_V02S0201 H02W0201
|
|
arc: S1_V02S0301 N3_V06S0003
|
|
arc: S1_V02S0401 N3_V06S0203
|
|
arc: S1_V02S0501 H06W0303
|
|
arc: S1_V02S0601 H02W0601
|
|
arc: W1_H02W0201 N3_V06S0103
|
|
|
|
.tile R19C37:PLC2
|
|
arc: W1_H02W0201 N3_V06S0103
|
|
arc: W1_H02W0601 N3_V06S0303
|
|
|
|
.tile R19C39:PLC2
|
|
arc: W3_H06W0303 E1_H01W0100
|
|
|
|
.tile R19C40:PLC2
|
|
arc: H01W0100 E3_H06W0303
|
|
|
|
.tile R19C41:PLC2
|
|
arc: V01S0000 N3_V06S0103
|
|
arc: W3_H06W0203 E3_H06W0203
|
|
|
|
.tile R19C42:PLC2
|
|
arc: S1_V02S0401 N3_V06S0203
|
|
arc: V01S0000 N3_V06S0103
|
|
|
|
.tile R19C43:PLC2
|
|
arc: S1_V02S0401 N3_V06S0203
|
|
|
|
.tile R19C44:PLC2
|
|
arc: S1_V02S0001 N3_V06S0003
|
|
arc: S1_V02S0401 N3_V06S0203
|
|
arc: S1_V02S0601 N3_V06S0303
|
|
|
|
.tile R19C45:PLC2
|
|
arc: V01S0000 N3_V06S0103
|
|
|
|
.tile R19C46:PLC2
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
|
|
.tile R19C47:PLC2
|
|
arc: W3_H06W0203 E3_H06W0203
|
|
|
|
.tile R19C52:PLC2
|
|
arc: W3_H06W0303 E3_H06W0203
|
|
|
|
.tile R19C53:PLC2
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
|
|
.tile R19C58:PLC2
|
|
arc: W3_H06W0203 E3_H06W0203
|
|
|
|
.tile R19C59:PLC2
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
|
|
.tile R19C64:PLC2
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
|
|
.tile R19C65:PLC2
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
|
|
.tile R19C70:PLC2
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
|
|
.tile R19C71:PLC2
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
|
|
.tile R19C76:PLC2
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
|
|
.tile R19C77:PLC2
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
|
|
.tile R19C7:PLC2
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
|
|
.tile R19C82:PLC2
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
|
|
.tile R19C83:PLC2
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
|
|
.tile R19C88:PLC2
|
|
arc: W3_H06W0303 E1_H01W0100
|
|
|
|
.tile R20C13:PLC2
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
|
|
.tile R20C14:PLC2
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
|
|
.tile R20C19:PLC2
|
|
arc: E1_H02E0001 V06S0003
|
|
arc: E1_H02E0601 W3_H06E0303
|
|
|
|
.tile R20C20:PLC2
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
|
|
.tile R20C21:PLC2
|
|
arc: S1_V02S0001 W1_H02E0001
|
|
arc: S1_V02S0601 W1_H02E0601
|
|
|
|
.tile R20C22:PLC2
|
|
arc: H00R0000 S1_V02N0401
|
|
arc: S1_V02S0601 V01N0001
|
|
arc: CE0 V02N0201
|
|
arc: CLK0 G_HPBX0000
|
|
arc: M1 H00R0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: S1_V02S0101 Q1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R20C25:PLC2
|
|
arc: E1_H02E0601 N3_V06S0303
|
|
|
|
.tile R20C26:PLC2
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
|
|
.tile R20C27:PLC2
|
|
arc: H00R0100 V02S0701
|
|
arc: CE0 V02N0201
|
|
arc: CE1 V02N0201
|
|
arc: CE3 V02N0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H02E0101 Q1
|
|
arc: M1 H00R0100
|
|
arc: M2 W1_H02E0601
|
|
arc: M6 H02W0401
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: S1_V02S0001 Q2
|
|
arc: S1_V02S0601 Q6
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R20C28:PLC2
|
|
arc: V00B0100 V02S0301
|
|
arc: V00T0100 V02N0701
|
|
arc: W1_H02W0401 N1_V01S0000
|
|
arc: CE1 S1_V02N0201
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E3_H06E0103 Q2
|
|
arc: LSR1 V00B0100
|
|
arc: M2 V00T0100
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXLSR1 LSR1
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R20C29:PLC2
|
|
arc: S1_V02S0101 W1_H02E0101
|
|
arc: S1_V02S0201 H06W0103
|
|
|
|
.tile R20C2:PLC2
|
|
arc: E3_H06E0003 H01E0001
|
|
|
|
.tile R20C32:PLC2
|
|
arc: E1_H02E0001 V01N0001
|
|
arc: E1_H02E0601 V01N0001
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
arc: H00L0000 V02S0001
|
|
arc: W3_H06W0103 E1_H01W0100
|
|
arc: CE0 V02N0201
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0101 Q1
|
|
arc: M1 H00L0000
|
|
arc: MUXCLK0 CLK0
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R20C33:PLC2
|
|
arc: H01W0100 E3_H06W0303
|
|
arc: S1_V02S0201 E3_H06W0103
|
|
arc: S1_V02S0701 H01E0101
|
|
|
|
.tile R20C34:PLC2
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: S1_V02S0001 W1_H02E0001
|
|
arc: S1_V02S0601 W1_H02E0601
|
|
|
|
.tile R20C35:PLC2
|
|
arc: H00L0000 V02N0201
|
|
arc: H00R0000 V02S0601
|
|
arc: S1_V02S0001 S3_V06N0003
|
|
arc: S1_V02S0601 V01N0001
|
|
arc: V00T0100 E1_H02W0301
|
|
arc: V01S0000 S3_V06N0103
|
|
arc: CE1 V02N0201
|
|
arc: CE2 V02N0601
|
|
arc: CE3 H00L0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: M3 E1_H02W0201
|
|
arc: M5 H00R0000
|
|
arc: M6 V00T0100
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: S1_V02S0501 Q5
|
|
arc: S3_V06S0003 Q3
|
|
arc: S3_V06S0303 Q6
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R20C36:PLC2
|
|
arc: E1_H02E0601 V01N0001
|
|
arc: H00L0000 V02N0001
|
|
arc: H00R0000 S1_V02N0601
|
|
arc: V00T0000 V02S0401
|
|
arc: CE0 V02N0201
|
|
arc: CE1 V02N0201
|
|
arc: CE3 V02N0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0001 Q3
|
|
arc: E1_H02E0201 Q0
|
|
arc: M0 V00T0000
|
|
arc: M3 H00L0000
|
|
arc: M7 H00R0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: S3_V06S0203 Q7
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R20C37:PLC2
|
|
arc: E1_H02E0301 V02N0301
|
|
arc: E1_H02E0501 V02N0501
|
|
arc: S1_V02S0601 H01E0001
|
|
arc: W1_H02W0201 S1_V02N0201
|
|
arc: W1_H02W0301 S1_V02N0301
|
|
|
|
.tile R20C38:PLC2
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: H00L0000 V02N0201
|
|
arc: H00R0000 S1_V02N0401
|
|
arc: S1_V02S0201 W1_H02E0201
|
|
arc: S1_V02S0401 H06W0203
|
|
arc: S1_V02S0601 W1_H02E0601
|
|
arc: V01S0000 N3_V06S0103
|
|
arc: CE0 H00R0000
|
|
arc: CE3 S1_V02N0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E3_H06E0103 Q1
|
|
arc: LSR0 H02E0301
|
|
arc: LSR1 H02E0501
|
|
arc: M1 H00L0000
|
|
arc: M6 E1_H02W0401
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR3 LSR0
|
|
arc: N3_V06N0303 Q6
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R20C39:PLC2
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
arc: W3_H06W0303 E3_H06W0203
|
|
|
|
.tile R20C40:PLC2
|
|
arc: W1_H02W0401 W3_H06E0203
|
|
|
|
.tile R20C41:PLC2
|
|
arc: E1_H02E0001 N1_V01S0000
|
|
arc: S1_V02S0301 H06E0003
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
|
|
.tile R20C42:PLC2
|
|
arc: E1_H02E0101 V02N0101
|
|
arc: H00L0000 V02N0001
|
|
arc: H00L0100 V02N0101
|
|
arc: H00R0000 V02S0401
|
|
arc: S1_V02S0401 V01N0001
|
|
arc: S1_V02S0601 N1_V01S0000
|
|
arc: CE2 H00L0000
|
|
arc: CE3 H00L0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: M4 E1_H02W0401
|
|
arc: M7 H00R0000
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: S1_V02S0501 Q7
|
|
arc: S3_V06S0203 Q4
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R20C43:PLC2
|
|
arc: V00T0000 V02S0401
|
|
arc: CE0 V02N0201
|
|
arc: CE2 H02E0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H02E0101 Q1
|
|
arc: E1_H02E0401 Q4
|
|
arc: M1 W1_H02E0001
|
|
arc: M4 V00T0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R20C44:PLC2
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: S1_V02S0401 H02E0401
|
|
arc: W1_H02W0401 S1_V02N0401
|
|
|
|
.tile R20C45:PLC2
|
|
arc: S1_V02S0101 W1_H02E0101
|
|
arc: S3_V06S0003 N1_V01S0000
|
|
arc: V01S0000 S3_V06N0103
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
arc: W3_H06W0203 E3_H06W0203
|
|
|
|
.tile R20C47:PLC2
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
|
|
.tile R20C50:PLC2
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
|
|
.tile R20C51:PLC2
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
|
|
.tile R20C53:PLC2
|
|
arc: N3_V06N0203 H06E0203
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
|
|
.tile R20C57:PLC2
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
|
|
.tile R20C59:PLC2
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
|
|
.tile R20C63:PLC2
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
|
|
.tile R20C65:PLC2
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
|
|
.tile R20C69:PLC2
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
|
|
.tile R20C71:PLC2
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
|
|
.tile R20C75:PLC2
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
|
|
.tile R20C77:PLC2
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
|
|
.tile R20C7:PLC2
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
|
|
.tile R20C81:PLC2
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
arc: W3_H06W0303 E3_H06W0203
|
|
|
|
.tile R20C83:PLC2
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
|
|
.tile R20C87:PLC2
|
|
arc: W3_H06W0203 E1_H02W0701
|
|
arc: W3_H06W0303 E1_H02W0501
|
|
|
|
.tile R20C8:PLC2
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
|
|
.tile R21C10:PLC2
|
|
arc: N3_V06N0303 E3_H06W0303
|
|
|
|
.tile R21C13:PLC2
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
|
|
.tile R21C15:PLC2
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
|
|
.tile R21C16:PLC2
|
|
arc: V00B0100 S1_V02N0301
|
|
arc: CE2 S1_V02N0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: LSR1 V00B0100
|
|
arc: M5 E1_H02W0001
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR2 LSR1
|
|
arc: W3_H06W0303 Q5
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R21C18:PLC2
|
|
arc: W1_H02W0001 S1_V02N0001
|
|
|
|
.tile R21C19:PLC2
|
|
arc: E1_H01E0001 W3_H06E0003
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
|
|
.tile R21C20:PLC2
|
|
arc: E1_H02E0201 H01E0001
|
|
|
|
.tile R21C21:PLC2
|
|
arc: E1_H02E0601 W3_H06E0303
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: H00L0000 N1_V02S0201
|
|
arc: H00R0000 V02S0601
|
|
arc: V00B0000 V02S0001
|
|
arc: CE2 H02W0101
|
|
arc: CE3 H02W0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0101 Q5
|
|
arc: M4 V00B0000
|
|
arc: M5 H00L0000
|
|
arc: M7 H00R0000
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: V01S0000 Q4
|
|
arc: V01S0100 Q7
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R21C22:PLC2
|
|
arc: E1_H02E0201 S1_V02N0201
|
|
arc: E1_H02E0601 N1_V02S0601
|
|
arc: H00L0000 V02N0001
|
|
arc: H00R0000 N1_V02S0401
|
|
arc: H00R0100 V02N0701
|
|
arc: N1_V02N0201 E1_H02W0201
|
|
arc: S1_V02S0101 H01E0101
|
|
arc: S1_V02S0201 E1_H02W0201
|
|
arc: V00B0000 N1_V02S0001
|
|
arc: V00B0100 V02N0301
|
|
arc: W1_H02W0101 E1_H02W0101
|
|
arc: CE0 S1_V02N0201
|
|
arc: CE1 E1_H02W0101
|
|
arc: CE2 E1_H02W0101
|
|
arc: CE3 S1_V02N0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: M0 V00B0100
|
|
arc: M1 H00L0000
|
|
arc: M2 H02E0601
|
|
arc: M3 W1_H02E0201
|
|
arc: M4 V00B0000
|
|
arc: M5 H00R0000
|
|
arc: M6 H02W0401
|
|
arc: M7 H00R0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q2
|
|
arc: S1_V02S0301 Q3
|
|
arc: S1_V02S0601 Q4
|
|
arc: S3_V06S0003 Q0
|
|
arc: S3_V06S0103 Q1
|
|
arc: S3_V06S0203 Q7
|
|
arc: S3_V06S0303 Q6
|
|
arc: V01S0000 Q5
|
|
arc: V01S0100 Q3
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R21C23:PLC2
|
|
arc: H00L0000 H02E0201
|
|
arc: H00R0000 H02E0601
|
|
arc: S1_V02S0001 N1_V02S0501
|
|
arc: V00B0000 V02N0201
|
|
arc: W1_H02W0401 V01N0001
|
|
arc: CE1 H02W0101
|
|
arc: CE2 H00L0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: M3 H00R0000
|
|
arc: M4 V00B0000
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: S3_V06S0203 Q4
|
|
arc: V01S0000 Q3
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R21C24:PLC2
|
|
arc: E1_H02E0101 E3_H06W0103
|
|
arc: S1_V02S0101 E3_H06W0103
|
|
arc: S1_V02S0401 N1_V02S0401
|
|
arc: S3_V06S0103 E3_H06W0103
|
|
arc: W1_H02W0101 E3_H06W0103
|
|
arc: W1_H02W0201 E3_H06W0103
|
|
|
|
.tile R21C25:PLC2
|
|
arc: E1_H02E0401 S1_V02N0401
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: H00R0000 S1_V02N0401
|
|
arc: H00R0100 N1_V02S0501
|
|
arc: S1_V02S0201 E1_H01W0000
|
|
arc: CE0 H00R0000
|
|
arc: CE2 H02E0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: M1 E1_H02W0001
|
|
arc: M5 H00R0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: S1_V02S0101 Q1
|
|
arc: V01S0100 Q5
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R21C26:PLC2
|
|
arc: E1_H02E0201 N1_V02S0201
|
|
arc: E1_H02E0401 V02N0401
|
|
arc: H00L0100 E1_H02W0101
|
|
arc: H00R0000 H02E0401
|
|
arc: S1_V02S0401 E1_H01W0000
|
|
arc: S1_V02S0501 H06W0303
|
|
arc: V00B0100 E1_H02W0701
|
|
arc: V00T0100 E1_H02W0301
|
|
arc: CE0 H00R0000
|
|
arc: CE1 H00R0000
|
|
arc: CE2 H00R0000
|
|
arc: CE3 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: H01W0000 Q2
|
|
arc: M0 H02W0601
|
|
arc: M1 E1_H02W0001
|
|
arc: M2 E1_H02W0601
|
|
arc: M3 H02W0201
|
|
arc: M4 V00T0100
|
|
arc: M5 H00L0100
|
|
arc: M6 V00B0100
|
|
arc: M7 E1_H02W0201
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: S1_V02S0101 Q3
|
|
arc: S1_V02S0301 Q1
|
|
arc: S1_V02S0601 Q6
|
|
arc: S3_V06S0003 Q0
|
|
arc: S3_V06S0203 Q4
|
|
arc: V01S0000 Q7
|
|
arc: V01S0100 Q5
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R21C27:PLC2
|
|
arc: E1_H01E0101 W3_H06E0203
|
|
arc: H00L0000 V02N0001
|
|
arc: H00L0100 V02N0301
|
|
arc: H00R0000 V02N0401
|
|
arc: H00R0100 V02N0501
|
|
arc: N1_V02N0201 H06W0103
|
|
arc: N1_V02N0601 E1_H02W0601
|
|
arc: S1_V02S0201 H06W0103
|
|
arc: S1_V02S0401 N1_V02S0401
|
|
arc: S1_V02S0701 V01N0101
|
|
arc: V00B0000 N1_V02S0001
|
|
arc: V00B0100 V02N0101
|
|
arc: V00T0000 E1_H02W0001
|
|
arc: V01S0000 N3_V06S0103
|
|
arc: W1_H02W0001 V01N0001
|
|
arc: W1_H02W0201 V02N0201
|
|
arc: W1_H02W0601 V02N0601
|
|
arc: CE0 H00L0100
|
|
arc: CE1 E1_H02W0101
|
|
arc: CE2 H00L0100
|
|
arc: CE3 E1_H02W0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H02E0001 Q2
|
|
arc: E1_H02E0501 Q7
|
|
arc: E3_H06E0003 Q0
|
|
arc: E3_H06E0103 Q1
|
|
arc: E3_H06E0203 Q7
|
|
arc: E3_H06E0303 Q5
|
|
arc: H01W0000 Q6
|
|
arc: M0 V00B0100
|
|
arc: M1 H00R0100
|
|
arc: M2 V00T0000
|
|
arc: M3 H00R0000
|
|
arc: M4 H02E0401
|
|
arc: M5 H00L0000
|
|
arc: M6 V00B0000
|
|
arc: M7 H02E0201
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: S1_V02S0101 Q3
|
|
arc: S3_V06S0203 Q4
|
|
arc: V01S0100 Q7
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R21C28:PLC2
|
|
arc: E3_H06E0103 H01E0101
|
|
arc: H00R0100 H02W0701
|
|
arc: N1_V02N0701 N3_V06S0203
|
|
arc: V00B0100 H02W0501
|
|
arc: W1_H02W0001 V02N0001
|
|
arc: W1_H02W0101 V02N0101
|
|
arc: W1_H02W0201 V01N0001
|
|
arc: W1_H02W0301 V02N0301
|
|
arc: W1_H02W0601 V02N0601
|
|
arc: W1_H02W0701 V02N0701
|
|
arc: CE0 E1_H02W0101
|
|
arc: CE2 E1_H02W0101
|
|
arc: CE3 E1_H02W0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: M0 V00B0100
|
|
arc: M5 H00R0100
|
|
arc: M6 H02W0401
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: S1_V02S0201 Q0
|
|
arc: S1_V02S0601 Q6
|
|
arc: V01S0000 Q5
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R21C29:PLC2
|
|
arc: S1_V02S0001 W1_H02E0001
|
|
arc: S1_V02S0501 W1_H02E0501
|
|
arc: S3_V06S0103 E1_H01W0100
|
|
arc: V00B0000 V02S0201
|
|
arc: W1_H02W0001 S1_V02N0001
|
|
arc: W1_H02W0101 E1_H01W0100
|
|
arc: W1_H02W0401 S1_V02N0401
|
|
arc: W1_H02W0501 N1_V02S0501
|
|
arc: W1_H02W0601 E1_H01W0000
|
|
arc: W1_H02W0701 N1_V02S0701
|
|
arc: W3_H06W0303 E1_H01W0100
|
|
arc: CE2 H02W0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: M4 V00B0000
|
|
arc: MUXCLK2 CLK0
|
|
arc: V01S0000 Q4
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R21C30:PLC2
|
|
arc: E1_H02E0201 N1_V02S0201
|
|
arc: E1_H02E0401 E1_H01W0000
|
|
arc: H00L0100 N1_V02S0301
|
|
arc: H00R0100 S1_V02N0701
|
|
arc: S1_V02S0401 H06E0203
|
|
arc: S1_V02S0701 H06E0203
|
|
arc: V00B0000 H02W0401
|
|
arc: C1 H02W0401
|
|
arc: CE3 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D1 E1_H02W0001
|
|
arc: E1_H01E0001 F1
|
|
arc: E1_H02E0101 F1
|
|
arc: E3_H06E0103 F1
|
|
arc: E3_H06E0203 Q7
|
|
arc: F1 F1_SLICE
|
|
arc: H01W0000 F1
|
|
arc: H01W0100 F1
|
|
arc: LSR1 V00B0000
|
|
arc: M7 H00L0100
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR3 LSR1
|
|
arc: S1_V02S0101 F1
|
|
arc: S3_V06S0103 F1
|
|
arc: W1_H02W0101 F1
|
|
arc: W3_H06W0103 F1
|
|
word: SLICEA.K1.INIT 0000111100000000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R21C31:PLC2
|
|
arc: E1_H02E0101 V02N0101
|
|
arc: E1_H02E0201 H01E0001
|
|
arc: E1_H02E0301 V02N0301
|
|
arc: E1_H02E0401 V01N0001
|
|
arc: E1_H02E0601 H01E0001
|
|
arc: E3_H06E0203 H01E0001
|
|
arc: H00L0000 H02E0201
|
|
arc: H01W0000 W3_H06E0103
|
|
arc: V00T0000 N1_V02S0601
|
|
arc: W1_H02W0401 S1_V02N0401
|
|
arc: CE0 H02E0101
|
|
arc: CE2 H02E0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: M1 H00L0000
|
|
arc: M4 V00T0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: V01S0000 Q1
|
|
arc: V01S0100 Q4
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R21C32:PLC2
|
|
arc: H00R0000 N1_V02S0401
|
|
arc: H00R0100 V02N0701
|
|
arc: N1_V02N0201 H02E0201
|
|
arc: S1_V02S0201 V01N0001
|
|
arc: V00B0100 V02N0101
|
|
arc: V00T0100 H02E0301
|
|
arc: W1_H02W0001 S1_V02N0001
|
|
arc: CE0 H02E0101
|
|
arc: CE1 W1_H02E0101
|
|
arc: CE2 H02E0101
|
|
arc: CE3 W1_H02E0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H02E0201 Q2
|
|
arc: E1_H02E0301 Q3
|
|
arc: E3_H06E0003 Q3
|
|
arc: E3_H06E0303 Q6
|
|
arc: M0 V00B0100
|
|
arc: M2 V00T0100
|
|
arc: M3 H02W0201
|
|
arc: M4 H02E0401
|
|
arc: M5 H00R0100
|
|
arc: M6 W1_H02E0401
|
|
arc: M7 H00R0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q3
|
|
arc: S1_V02S0101 Q3
|
|
arc: S1_V02S0701 Q7
|
|
arc: S3_V06S0003 Q0
|
|
arc: S3_V06S0203 Q4
|
|
arc: S3_V06S0303 Q5
|
|
arc: V01S0000 Q6
|
|
arc: V01S0100 Q6
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R21C33:PLC2
|
|
arc: H00R0000 W1_H02E0601
|
|
arc: H00R0100 E1_H02W0701
|
|
arc: S1_V02S0101 H06E0103
|
|
arc: S1_V02S0301 H02E0301
|
|
arc: S3_V06S0003 W3_H06E0003
|
|
arc: S3_V06S0103 W3_H06E0103
|
|
arc: S3_V06S0303 W3_H06E0303
|
|
arc: V00T0000 N1_V02S0401
|
|
arc: W1_H02W0201 V02S0201
|
|
arc: CE0 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: M0 V00T0000
|
|
arc: M1 H00R0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: S1_V02S0001 Q0
|
|
arc: V01S0000 Q1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R21C34:PLC2
|
|
arc: E1_H02E0101 S1_V02N0101
|
|
arc: E1_H02E0201 S1_V02N0201
|
|
arc: E1_H02E0601 S1_V02N0601
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: H00R0100 S1_V02N0701
|
|
arc: S1_V02S0201 W1_H02E0201
|
|
arc: S1_V02S0301 W1_H02E0301
|
|
arc: S1_V02S0701 H06E0203
|
|
arc: V00B0100 N1_V02S0301
|
|
arc: CE0 E1_H02W0101
|
|
arc: CE1 E1_H02W0101
|
|
arc: CE2 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: M0 V00B0100
|
|
arc: M2 H02W0601
|
|
arc: M5 E1_H02W0001
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: S3_V06S0303 Q5
|
|
arc: V01S0000 Q0
|
|
arc: V01S0100 Q2
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R21C35:PLC2
|
|
arc: E1_H02E0601 E1_H01W0000
|
|
arc: H00L0000 V02S0001
|
|
arc: H00L0100 N1_V02S0101
|
|
arc: H00R0000 V02N0601
|
|
arc: H00R0100 H02W0501
|
|
arc: N1_V02N0201 H02E0201
|
|
arc: N1_V02N0601 E1_H01W0000
|
|
arc: S1_V02S0001 H06E0003
|
|
arc: S1_V02S0501 H06E0303
|
|
arc: S1_V02S0601 H06E0303
|
|
arc: S3_V06S0303 E1_H01W0100
|
|
arc: V00B0000 N1_V02S0201
|
|
arc: V00T0000 N1_V02S0401
|
|
arc: V00T0100 H02W0301
|
|
arc: W1_H02W0601 N1_V01S0000
|
|
arc: W1_H02W0701 S1_V02N0701
|
|
arc: CE0 H02W0101
|
|
arc: CE1 H02W0101
|
|
arc: CE2 H02E0101
|
|
arc: CE3 H02W0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0101 Q2
|
|
arc: E1_H02E0001 Q2
|
|
arc: E1_H02E0201 Q2
|
|
arc: M0 V00T0100
|
|
arc: M1 H00L0000
|
|
arc: M2 V00T0000
|
|
arc: M3 H00R0000
|
|
arc: M4 E1_H02W0401
|
|
arc: M5 H00R0100
|
|
arc: M6 V00B0000
|
|
arc: M7 H00L0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q0
|
|
arc: S1_V02S0201 Q2
|
|
arc: S1_V02S0301 Q1
|
|
arc: S1_V02S0401 Q6
|
|
arc: S1_V02S0701 Q5
|
|
arc: S3_V06S0203 Q4
|
|
arc: V01S0000 Q3
|
|
arc: V01S0100 Q7
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R21C36:PLC2
|
|
arc: E1_H02E0101 W3_H06E0103
|
|
arc: E1_H02E0201 V02N0201
|
|
arc: E1_H02E0401 V02N0401
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: H00L0000 N1_V02S0201
|
|
arc: H00L0100 V02N0301
|
|
arc: H00R0000 H02E0601
|
|
arc: H00R0100 H02W0701
|
|
arc: H01W0000 W3_H06E0103
|
|
arc: N1_V02N0001 N3_V06S0003
|
|
arc: N1_V02N0201 W3_H06E0103
|
|
arc: N1_V02N0601 W1_H02E0601
|
|
arc: S1_V02S0101 W3_H06E0103
|
|
arc: S1_V02S0201 W3_H06E0103
|
|
arc: S1_V02S0301 H01E0101
|
|
arc: S1_V02S0701 H01E0101
|
|
arc: S3_V06S0103 W3_H06E0103
|
|
arc: S3_V06S0203 W3_H06E0203
|
|
arc: V00B0000 V02N0001
|
|
arc: V00B0100 V02N0101
|
|
arc: V00T0000 N1_V02S0601
|
|
arc: V00T0100 N1_V02S0501
|
|
arc: W1_H02W0001 V01N0001
|
|
arc: W1_H02W0101 W3_H06E0103
|
|
arc: W1_H02W0301 N1_V02S0301
|
|
arc: W1_H02W0501 V01N0101
|
|
arc: CE0 H00R0100
|
|
arc: CE1 H00R0100
|
|
arc: CE2 H00R0000
|
|
arc: CE3 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0101 Q0
|
|
arc: E1_H02E0601 Q4
|
|
arc: E3_H06E0203 Q4
|
|
arc: H01W0100 Q1
|
|
arc: M0 V00B0100
|
|
arc: M1 H00L0100
|
|
arc: M2 V00B0000
|
|
arc: M3 H02W0201
|
|
arc: M4 V00T0100
|
|
arc: M5 E1_H02W0001
|
|
arc: M6 V00T0000
|
|
arc: M7 H00L0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q5
|
|
arc: S1_V02S0001 Q2
|
|
arc: S1_V02S0401 Q4
|
|
arc: S3_V06S0003 Q3
|
|
arc: V01S0000 Q6
|
|
arc: V01S0100 Q7
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R21C37:PLC2
|
|
arc: E1_H02E0601 S1_V02N0601
|
|
arc: E1_H02E0701 S1_V02N0701
|
|
arc: H00L0000 S1_V02N0201
|
|
arc: H00R0100 S1_V02N0701
|
|
arc: N1_V02N0301 S1_V02N0201
|
|
arc: N1_V02N0501 S1_V02N0401
|
|
arc: S1_V02S0001 W1_H02E0001
|
|
arc: S1_V02S0201 W1_H02E0201
|
|
arc: S3_V06S0303 H01E0101
|
|
arc: V00B0100 V02N0101
|
|
arc: W1_H02W0201 V01N0001
|
|
arc: W1_H02W0401 V02N0401
|
|
arc: W1_H02W0701 S1_V02N0701
|
|
arc: CE1 H00R0100
|
|
arc: CE2 H00L0000
|
|
arc: CE3 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: M2 V00B0100
|
|
arc: M4 H02E0401
|
|
arc: M7 H02E0201
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: S1_V02S0401 Q4
|
|
arc: S3_V06S0103 Q2
|
|
arc: S3_V06S0203 Q7
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R21C38:PLC2
|
|
arc: H00R0000 V02S0401
|
|
arc: H00R0100 H02E0701
|
|
arc: S1_V02S0401 E1_H01W0000
|
|
arc: S1_V02S0601 W1_H02E0601
|
|
arc: W1_H02W0001 N1_V01S0000
|
|
arc: C0 H02E0601
|
|
arc: CE0 H00R0100
|
|
arc: CE3 W1_H02E0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02N0201
|
|
arc: F0 F0_SLICE
|
|
arc: M7 H00R0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V02N0201 Q0
|
|
arc: V01S0000 Q7
|
|
word: SLICEA.K0.INIT 1111000000000000
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
|
|
.tile R21C39:PLC2
|
|
arc: H00R0000 S1_V02N0401
|
|
arc: S1_V02S0401 H06E0203
|
|
arc: S1_V02S0701 H06E0203
|
|
arc: V00T0100 V02N0701
|
|
arc: CLK0 G_HPBX0000
|
|
arc: H00L0100 Q3
|
|
arc: H01W0000 Q2
|
|
arc: LSR1 V00T0100
|
|
arc: M2 V00B0000
|
|
arc: M3 H00R0000
|
|
arc: M6 V00B0100
|
|
arc: M7 H00L0100
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR3 LSR1
|
|
arc: V00B0000 Q6
|
|
arc: V00B0100 Q7
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R21C3:PLC2
|
|
arc: E3_H06E0203 W1_H02E0701
|
|
arc: E3_H06E0303 W1_H02E0501
|
|
|
|
.tile R21C40:PLC2
|
|
arc: E1_H02E0101 S1_V02N0101
|
|
arc: E1_H02E0201 W3_H06E0103
|
|
|
|
.tile R21C41:PLC2
|
|
arc: E1_H02E0201 S1_V02N0201
|
|
arc: E1_H02E0401 E1_H01W0000
|
|
arc: E1_H02E0501 V01N0101
|
|
arc: S3_V06S0103 E1_H01W0100
|
|
arc: V00B0100 V02S0301
|
|
arc: CE1 H02E0101
|
|
arc: CE3 H02W0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: M2 E1_H02W0601
|
|
arc: M6 V00B0100
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: V01S0000 Q2
|
|
arc: V01S0100 Q6
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R21C42:PLC2
|
|
arc: E1_H02E0001 V01N0001
|
|
arc: E1_H02E0101 W3_H06E0103
|
|
arc: E1_H02E0201 W3_H06E0103
|
|
arc: E1_H02E0601 V02S0601
|
|
arc: E1_H02E0701 V02N0701
|
|
arc: H00L0000 S1_V02N0001
|
|
arc: H00R0000 H02E0401
|
|
arc: H00R0100 H02E0501
|
|
arc: H01W0000 W3_H06E0103
|
|
arc: N1_V02N0001 S1_V02N0001
|
|
arc: N1_V02N0101 W3_H06E0103
|
|
arc: S1_V02S0101 W3_H06E0103
|
|
arc: S1_V02S0201 W3_H06E0103
|
|
arc: S3_V06S0103 W3_H06E0103
|
|
arc: S3_V06S0203 E1_H01W0000
|
|
arc: S3_V06S0303 E1_H01W0100
|
|
arc: V00B0000 V02N0201
|
|
arc: V00B0100 H02W0501
|
|
arc: V00T0000 V02N0601
|
|
arc: W1_H02W0101 W3_H06E0103
|
|
arc: CE0 H00L0000
|
|
arc: CE1 H00R0000
|
|
arc: CE2 H00R0000
|
|
arc: CE3 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: H01W0100 Q1
|
|
arc: M0 V00T0000
|
|
arc: M1 H02W0001
|
|
arc: M2 V00B0100
|
|
arc: M3 W1_H02E0201
|
|
arc: M4 E1_H02W0401
|
|
arc: M5 H00R0100
|
|
arc: M6 V00B0000
|
|
arc: M7 H02E0201
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q5
|
|
arc: S1_V02S0001 Q2
|
|
arc: S1_V02S0301 Q3
|
|
arc: S1_V02S0401 Q6
|
|
arc: S1_V02S0601 Q4
|
|
arc: S3_V06S0003 Q0
|
|
arc: V01S0000 Q7
|
|
arc: V01S0100 Q6
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R21C43:PLC2
|
|
arc: H00L0100 S1_V02N0301
|
|
arc: H00R0000 V02N0401
|
|
arc: H00R0100 V02N0501
|
|
arc: N1_V02N0201 H02E0201
|
|
arc: V00B0000 V02N0201
|
|
arc: V00B0100 H02E0701
|
|
arc: V00T0100 H02W0301
|
|
arc: W1_H02W0001 V02N0001
|
|
arc: W1_H02W0501 S1_V02N0501
|
|
arc: W1_H02W0601 V01N0001
|
|
arc: CE0 H02E0101
|
|
arc: CE1 H02E0101
|
|
arc: CE2 H00L0100
|
|
arc: CE3 H00L0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0101 Q0
|
|
arc: E1_H02E0201 Q2
|
|
arc: H01W0000 Q7
|
|
arc: H01W0100 Q6
|
|
arc: M0 V00T0100
|
|
arc: M1 H02W0001
|
|
arc: M2 H02E0601
|
|
arc: M3 H00R0000
|
|
arc: M4 V00B0000
|
|
arc: M5 H02E0001
|
|
arc: M6 V00B0100
|
|
arc: M7 H00R0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: S3_V06S0203 Q4
|
|
arc: S3_V06S0303 Q5
|
|
arc: V01S0000 Q3
|
|
arc: V01S0100 Q1
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R21C44:PLC2
|
|
arc: H00R0000 N1_V02S0601
|
|
arc: S1_V02S0201 W1_H02E0201
|
|
arc: S1_V02S0701 H01E0101
|
|
arc: W1_H02W0001 N1_V02S0001
|
|
arc: W1_H02W0301 S1_V02N0301
|
|
arc: W1_H02W0401 N1_V02S0401
|
|
arc: CE2 W1_H02E0101
|
|
arc: CE3 W1_H02E0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: M5 H02W0001
|
|
arc: M7 H00R0000
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: S1_V02S0501 Q7
|
|
arc: V01S0000 Q5
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R21C45:PLC2
|
|
arc: S1_V02S0201 W1_H02E0201
|
|
arc: W1_H02W0001 N1_V01S0000
|
|
|
|
.tile R21C7:PLC2
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
|
|
.tile R21C9:PLC2
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
|
|
.tile R23C13:PLC2
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
arc: N3_V06N0003 E3_H06W0003
|
|
|
|
.tile R23C14:PLC2
|
|
arc: N3_V06N0203 E3_H06W0203
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
|
|
.tile R23C15:PLC2
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
|
|
.tile R23C16:PLC2
|
|
arc: N1_V02N0301 S3_V06N0003
|
|
arc: N1_V02N0601 H06W0303
|
|
arc: S1_V02S0001 S3_V06N0003
|
|
arc: S1_V02S0601 H06W0303
|
|
|
|
.tile R23C18:PLC2
|
|
arc: N1_V02N0001 V01N0001
|
|
arc: N3_V06N0103 E3_H06W0103
|
|
arc: CE3 E1_H02W0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: LSR0 H02W0301
|
|
arc: M6 H02W0401
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR3 LSR0
|
|
arc: N3_V06N0303 Q6
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R23C19:PLC2
|
|
arc: E1_H01E0101 W3_H06E0203
|
|
arc: E1_H02E0101 E1_H01W0100
|
|
arc: E1_H02E0301 S3_V06N0003
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
arc: H00R0100 H02W0501
|
|
arc: S1_V02S0001 S3_V06N0003
|
|
arc: S1_V02S0301 S3_V06N0003
|
|
arc: S1_V02S0601 S3_V06N0303
|
|
arc: W1_H02W0301 S3_V06N0003
|
|
arc: W1_H02W0401 V01N0001
|
|
arc: W3_H06W0303 E1_H01W0100
|
|
arc: CE1 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: LSR0 E1_H02W0301
|
|
arc: M3 H02W0201
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXLSR1 LSR0
|
|
arc: W3_H06W0003 Q3
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R23C20:PLC2
|
|
arc: E3_H06E0103 H01E0101
|
|
arc: H00R0000 V02N0401
|
|
arc: H01W0100 E3_H06W0303
|
|
arc: W1_H02W0101 E3_H06W0103
|
|
arc: W1_H02W0201 V01N0001
|
|
arc: W1_H02W0501 E3_H06W0303
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
arc: CE3 H02E0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: LSR1 H02E0301
|
|
arc: M7 H00R0000
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR3 LSR1
|
|
arc: W3_H06W0203 Q7
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R23C21:PLC2
|
|
arc: E1_H01E0101 W3_H06E0203
|
|
arc: E1_H02E0401 V02S0401
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: H00L0100 V02S0301
|
|
arc: W1_H02W0301 V02N0301
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
arc: W3_H06W0303 E3_H06W0203
|
|
arc: CE1 H02W0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E3_H06E0003 Q3
|
|
arc: M3 H00L0100
|
|
arc: MUXCLK1 CLK0
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R23C22:PLC2
|
|
arc: E1_H02E0001 S3_V06N0003
|
|
arc: E1_H02E0101 S3_V06N0103
|
|
arc: E1_H02E0701 E3_H06W0203
|
|
arc: E3_H06E0103 H01E0101
|
|
arc: H00L0100 V02S0301
|
|
arc: H00R0000 V02N0401
|
|
arc: N1_V02N0201 S3_V06N0103
|
|
arc: N1_V02N0401 E1_H01W0000
|
|
arc: N1_V02N0601 S1_V02N0601
|
|
arc: N1_V02N0701 E3_H06W0203
|
|
arc: S1_V02S0201 S3_V06N0103
|
|
arc: S1_V02S0501 S3_V06N0303
|
|
arc: V00B0000 V02S0201
|
|
arc: V00T0100 V02S0701
|
|
arc: W1_H02W0101 S3_V06N0103
|
|
arc: CE0 N1_V02S0201
|
|
arc: CE1 N1_V02S0201
|
|
arc: CE2 S1_V02N0601
|
|
arc: CE3 S1_V02N0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0001 Q0
|
|
arc: E1_H01E0101 Q1
|
|
arc: E3_H06E0203 Q7
|
|
arc: E3_H06E0303 Q6
|
|
arc: M0 V00B0000
|
|
arc: M1 H02W0001
|
|
arc: M2 H02W0601
|
|
arc: M3 H00R0000
|
|
arc: M4 H02E0401
|
|
arc: M5 H00L0100
|
|
arc: M6 V00T0100
|
|
arc: M7 E1_H02W0201
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q2
|
|
arc: N1_V01N0101 Q0
|
|
arc: N1_V02N0001 Q0
|
|
arc: N1_V02N0101 Q3
|
|
arc: V01S0000 Q5
|
|
arc: V01S0100 Q4
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R23C23:PLC2
|
|
arc: H00R0000 V02S0401
|
|
arc: H00R0100 V02S0501
|
|
arc: N1_V02N0101 H01E0101
|
|
arc: N1_V02N0201 H01E0001
|
|
arc: N1_V02N0601 H01E0001
|
|
arc: N1_V02N0701 H02E0701
|
|
arc: V00T0100 V02S0701
|
|
arc: W1_H02W0001 N1_V02S0001
|
|
arc: W1_H02W0601 V02S0601
|
|
arc: CE0 H02W0101
|
|
arc: CE2 H02E0101
|
|
arc: CE3 H02E0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H02E0701 Q5
|
|
arc: E3_H06E0203 Q7
|
|
arc: H01W0000 Q0
|
|
arc: M0 E1_H02W0601
|
|
arc: M1 H02E0001
|
|
arc: M4 V00T0100
|
|
arc: M5 H00R0000
|
|
arc: M7 H00R0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q1
|
|
arc: V01S0100 Q4
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R23C24:PLC2
|
|
arc: E1_H02E0101 N1_V02S0101
|
|
arc: E1_H02E0401 N1_V02S0401
|
|
arc: E1_H02E0601 V02N0601
|
|
arc: H00R0000 E1_H02W0401
|
|
arc: S1_V02S0201 E1_H02W0201
|
|
arc: S1_V02S0701 H02W0701
|
|
arc: V00B0000 V02N0001
|
|
arc: V00B0100 H02W0701
|
|
arc: V00T0000 H02W0201
|
|
arc: W1_H02W0101 N1_V02S0101
|
|
arc: W1_H02W0201 V02S0201
|
|
arc: CE0 H00R0000
|
|
arc: CE1 H00R0000
|
|
arc: CE3 E1_H02W0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E3_H06E0103 Q1
|
|
arc: LSR0 V00B0100
|
|
arc: LSR1 V00B0100
|
|
arc: M1 V01S0100
|
|
arc: M2 V00B0000
|
|
arc: M6 V00T0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR3 LSR1
|
|
arc: V01S0100 Q6
|
|
arc: W3_H06W0103 Q2
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R23C25:PLC2
|
|
arc: E1_H02E0001 S1_V02N0001
|
|
arc: E1_H02E0201 V02S0201
|
|
arc: E1_H02E0401 S3_V06N0203
|
|
arc: E1_H02E0601 V02N0601
|
|
arc: E1_H02E0701 N1_V01S0100
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: E3_H06E0203 S3_V06N0203
|
|
arc: H00L0000 V02N0001
|
|
arc: H00L0100 V02S0301
|
|
arc: H00R0000 H02E0401
|
|
arc: H00R0100 V02S0501
|
|
arc: N1_V02N0401 S3_V06N0203
|
|
arc: S1_V02S0101 E1_H01W0100
|
|
arc: S1_V02S0301 N1_V02S0201
|
|
arc: S1_V02S0401 N1_V02S0101
|
|
arc: S1_V02S0501 H06E0303
|
|
arc: S1_V02S0601 E1_H01W0000
|
|
arc: S1_V02S0701 W1_H02E0701
|
|
arc: V00B0000 V02N0201
|
|
arc: V00T0100 S1_V02N0701
|
|
arc: W1_H02W0201 S3_V06N0103
|
|
arc: W1_H02W0601 E1_H02W0601
|
|
arc: W1_H02W0701 S3_V06N0203
|
|
arc: CE0 H02E0101
|
|
arc: CE1 S1_V02N0201
|
|
arc: CE2 H02E0101
|
|
arc: CE3 H02E0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0001 Q4
|
|
arc: E1_H01E0101 Q0
|
|
arc: E1_H02E0301 Q1
|
|
arc: M0 V00B0000
|
|
arc: M1 H00R0000
|
|
arc: M3 H00R0100
|
|
arc: M4 V00T0100
|
|
arc: M5 H00L0100
|
|
arc: M7 H00L0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q5
|
|
arc: N1_V01N0101 Q7
|
|
arc: V01S0000 Q3
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R23C26:PLC2
|
|
arc: E1_H02E0401 V02S0401
|
|
arc: E1_H02E0601 S1_V02N0601
|
|
arc: H00R0000 H02E0401
|
|
arc: H00R0100 N1_V02S0501
|
|
arc: H01W0000 E3_H06W0103
|
|
arc: N1_V02N0401 H01E0001
|
|
arc: N1_V02N0701 H01E0101
|
|
arc: S1_V02S0101 V01N0101
|
|
arc: S1_V02S0201 W3_H06E0103
|
|
arc: S1_V02S0301 N1_V02S0301
|
|
arc: S1_V02S0401 N1_V02S0101
|
|
arc: S1_V02S0601 N1_V02S0601
|
|
arc: S1_V02S0701 H06E0203
|
|
arc: S3_V06S0103 E3_H06W0103
|
|
arc: V00B0100 H02E0701
|
|
arc: V00T0100 V02S0701
|
|
arc: W1_H02W0101 E1_H02W0101
|
|
arc: W1_H02W0201 E3_H06W0103
|
|
arc: W1_H02W0401 E3_H06W0203
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
arc: W3_H06W0303 E3_H06W0203
|
|
arc: CE0 H00R0100
|
|
arc: CE1 H00R0100
|
|
arc: CE2 H00R0100
|
|
arc: CE3 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0001 Q5
|
|
arc: E1_H01E0101 Q3
|
|
arc: E1_H02E0101 Q1
|
|
arc: E1_H02E0201 Q0
|
|
arc: E1_H02E0301 Q3
|
|
arc: H01W0100 Q6
|
|
arc: M0 W1_H02E0601
|
|
arc: M1 E1_H02W0001
|
|
arc: M2 V00B0100
|
|
arc: M3 E1_H02W0201
|
|
arc: M5 H02W0001
|
|
arc: M6 V00T0100
|
|
arc: M7 H02W0201
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q3
|
|
arc: N1_V01N0101 Q2
|
|
arc: N1_V02N0101 Q3
|
|
arc: N1_V02N0201 Q2
|
|
arc: S1_V02S0501 Q7
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R23C27:PLC2
|
|
arc: E1_H02E0101 W3_H06E0103
|
|
arc: E1_H02E0401 V02S0401
|
|
arc: E1_H02E0501 W1_H02E0401
|
|
arc: H00L0000 N1_V02S0201
|
|
arc: H00L0100 H02W0301
|
|
arc: H00R0000 N1_V02S0401
|
|
arc: H00R0100 N1_V02S0701
|
|
arc: N1_V02N0001 H01E0001
|
|
arc: N1_V02N0101 H02E0101
|
|
arc: N1_V02N0201 H02E0201
|
|
arc: N1_V02N0301 W1_H02E0301
|
|
arc: N1_V02N0701 H01E0101
|
|
arc: S1_V02S0301 W3_H06E0003
|
|
arc: S1_V02S0401 W1_H02E0401
|
|
arc: V00B0000 V02S0201
|
|
arc: W1_H02W0001 V06N0003
|
|
arc: W1_H02W0201 N1_V01S0000
|
|
arc: W1_H02W0601 E3_H06W0303
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
arc: CE0 N1_V02S0201
|
|
arc: CE1 H00L0100
|
|
arc: CE2 H00L0000
|
|
arc: CE3 H00L0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0001 Q1
|
|
arc: E1_H01E0101 Q5
|
|
arc: E1_H02E0201 Q0
|
|
arc: E1_H02E0601 Q6
|
|
arc: E1_H02E0701 Q5
|
|
arc: E3_H06E0003 Q3
|
|
arc: E3_H06E0103 Q2
|
|
arc: E3_H06E0203 Q7
|
|
arc: E3_H06E0303 Q5
|
|
arc: M0 W1_H02E0601
|
|
arc: M1 W1_H02E0001
|
|
arc: M2 V00B0000
|
|
arc: M3 W1_H02E0201
|
|
arc: M4 E1_H02W0401
|
|
arc: M5 H00R0000
|
|
arc: M6 H02E0401
|
|
arc: M7 H00R0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q5
|
|
arc: N1_V01N0101 Q4
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R23C28:PLC2
|
|
arc: E1_H01E0101 E3_H06W0203
|
|
arc: E1_H02E0701 V01N0101
|
|
arc: E3_H06E0303 W1_H02E0601
|
|
arc: H00L0100 V02S0101
|
|
arc: H00R0000 V02S0401
|
|
arc: H00R0100 H02E0501
|
|
arc: N1_V02N0101 H01E0101
|
|
arc: N1_V02N0301 W1_H02E0301
|
|
arc: N1_V02N0401 E3_H06W0203
|
|
arc: N1_V02N0601 H01E0001
|
|
arc: S1_V02S0401 E1_H02W0401
|
|
arc: S1_V02S0701 W3_H06E0203
|
|
arc: V00T0100 V02S0501
|
|
arc: W1_H02W0001 S1_V02N0001
|
|
arc: W1_H02W0101 V01N0101
|
|
arc: W1_H02W0201 W3_H06E0103
|
|
arc: W1_H02W0301 S1_V02N0301
|
|
arc: W3_H06W0203 E3_H06W0203
|
|
arc: CE0 H00R0100
|
|
arc: CE1 S1_V02N0201
|
|
arc: CE2 V02N0601
|
|
arc: CE3 E1_H02W0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H02E0201 Q0
|
|
arc: E3_H06E0003 Q3
|
|
arc: E3_H06E0203 Q4
|
|
arc: M0 V00T0100
|
|
arc: M3 H00L0100
|
|
arc: M4 H02E0401
|
|
arc: M7 H00R0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V02N0701 Q7
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R23C29:PLC2
|
|
arc: E1_H02E0201 W1_H02E0701
|
|
arc: E3_H06E0103 W1_H02E0101
|
|
arc: E3_H06E0303 W1_H02E0601
|
|
arc: N1_V02N0001 S1_V02N0001
|
|
arc: N1_V02N0201 W1_H02E0201
|
|
arc: N1_V02N0301 H01E0101
|
|
arc: N1_V02N0401 E3_H06W0203
|
|
arc: N1_V02N0701 W1_H02E0701
|
|
arc: S3_V06S0203 H06W0203
|
|
arc: W1_H02W0401 N1_V01S0000
|
|
arc: CE0 H02W0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: M1 E1_H02W0001
|
|
arc: MUXCLK0 CLK0
|
|
arc: N1_V02N0101 Q1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R23C2:PLC2
|
|
arc: S3_V06S0203 E3_H06W0203
|
|
|
|
.tile R23C30:PLC2
|
|
arc: E1_H02E0101 N1_V02S0101
|
|
arc: E1_H02E0301 W1_H02E0201
|
|
arc: E1_H02E0601 V02S0601
|
|
arc: E1_H02E0701 V02S0701
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: N1_V02N0101 N1_V01S0100
|
|
arc: N1_V02N0201 H02E0201
|
|
arc: N1_V02N0501 H06E0303
|
|
arc: N1_V02N0601 H06E0303
|
|
arc: N1_V02N0701 W1_H02E0701
|
|
arc: S1_V02S0101 H06E0103
|
|
arc: W1_H02W0101 N1_V02S0101
|
|
arc: W1_H02W0401 E1_H02W0401
|
|
|
|
.tile R23C31:PLC2
|
|
arc: E1_H01E0101 W3_H06E0203
|
|
arc: E1_H02E0101 V02S0101
|
|
arc: E1_H02E0201 W3_H06E0103
|
|
arc: E1_H02E0401 N1_V01S0000
|
|
arc: E1_H02E0601 V02S0601
|
|
arc: E3_H06E0203 S3_V06N0203
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
arc: H00R0000 V02N0401
|
|
arc: H00R0100 S1_V02N0701
|
|
arc: N1_V01N0101 S3_V06N0203
|
|
arc: N1_V02N0401 S3_V06N0203
|
|
arc: S1_V02S0401 W3_H06E0203
|
|
arc: S1_V02S0601 E1_H01W0000
|
|
arc: S1_V02S0701 E1_H01W0100
|
|
arc: W1_H02W0001 W3_H06E0003
|
|
arc: CE2 H02E0101
|
|
arc: CE3 H02E0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H02E0501 Q7
|
|
arc: M5 H00R0000
|
|
arc: M7 H00R0100
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q5
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R23C32:PLC2
|
|
arc: E1_H02E0001 V02S0001
|
|
arc: E1_H02E0201 V02S0201
|
|
arc: E3_H06E0103 H01E0101
|
|
arc: H00L0000 N1_V02S0201
|
|
arc: H00L0100 V02S0101
|
|
arc: H00R0000 V02S0601
|
|
arc: H00R0100 V02S0701
|
|
arc: H01W0000 E3_H06W0103
|
|
arc: N1_V02N0001 E3_H06W0003
|
|
arc: S1_V02S0001 S3_V06N0003
|
|
arc: S1_V02S0301 W1_H02E0301
|
|
arc: S1_V02S0501 H06E0303
|
|
arc: S1_V02S0701 V01N0101
|
|
arc: V00B0100 W1_H02E0701
|
|
arc: V00T0100 V02S0501
|
|
arc: W1_H02W0401 E3_H06W0203
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
arc: W3_H06W0303 E3_H06W0203
|
|
arc: CE0 H02E0101
|
|
arc: CE1 H02E0101
|
|
arc: CE2 H02E0101
|
|
arc: CE3 H02E0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0001 Q1
|
|
arc: E1_H02E0501 Q5
|
|
arc: H01W0100 Q3
|
|
arc: M0 V00B0100
|
|
arc: M1 H00R0100
|
|
arc: M2 W1_H02E0601
|
|
arc: M3 H00L0000
|
|
arc: M4 H02E0401
|
|
arc: M5 H00R0000
|
|
arc: M6 V00T0100
|
|
arc: M7 H00L0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: S1_V02S0201 Q2
|
|
arc: S1_V02S0401 Q4
|
|
arc: S3_V06S0303 Q6
|
|
arc: V01S0000 Q0
|
|
arc: V01S0100 Q7
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R23C33:PLC2
|
|
arc: E1_H02E0201 W1_H02E0201
|
|
arc: H00L0100 N1_V02S0101
|
|
arc: N1_V02N0501 W1_H02E0501
|
|
arc: S1_V02S0301 W3_H06E0003
|
|
arc: S1_V02S0501 H02E0501
|
|
arc: S1_V02S0601 H01E0001
|
|
arc: S1_V02S0701 W3_H06E0203
|
|
arc: V00B0100 S1_V02N0101
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
arc: CE0 H02W0101
|
|
arc: CE1 H02W0101
|
|
arc: CE2 H00L0100
|
|
arc: CE3 H00L0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: M1 H02E0001
|
|
arc: M2 W1_H02E0601
|
|
arc: M3 H02E0201
|
|
arc: M5 E1_H02W0001
|
|
arc: M6 V00B0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q5
|
|
arc: N1_V02N0401 Q6
|
|
arc: S1_V02S0101 Q3
|
|
arc: S1_V02S0201 Q2
|
|
arc: V01S0000 Q1
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R23C34:PLC2
|
|
arc: E1_H02E0101 S3_V06N0103
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
arc: H00L0000 S1_V02N0001
|
|
arc: H00L0100 V02S0301
|
|
arc: H00R0000 V02S0601
|
|
arc: H00R0100 N1_V02S0701
|
|
arc: N1_V02N0101 S3_V06N0103
|
|
arc: N1_V02N0201 S3_V06N0103
|
|
arc: N1_V02N0601 H06E0303
|
|
arc: N1_V02N0701 H06E0203
|
|
arc: S1_V02S0101 S3_V06N0103
|
|
arc: S1_V02S0301 W3_H06E0003
|
|
arc: S1_V02S0401 S3_V06N0203
|
|
arc: S1_V02S0701 W3_H06E0203
|
|
arc: V00B0100 V02S0101
|
|
arc: W1_H02W0101 S3_V06N0103
|
|
arc: CE0 S1_V02N0201
|
|
arc: CE1 H00R0100
|
|
arc: CE2 S1_V02N0601
|
|
arc: CE3 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0001 Q3
|
|
arc: E3_H06E0203 F7
|
|
arc: F7 F7_SLICE
|
|
arc: M0 H02W0601
|
|
arc: M1 H00L0100
|
|
arc: M3 H00L0000
|
|
arc: M4 V00B0100
|
|
arc: M5 H00R0000
|
|
arc: M7 E1_H02W0201
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q7
|
|
arc: N1_V01N0101 F7
|
|
arc: S3_V06S0003 Q0
|
|
arc: S3_V06S0103 Q1
|
|
arc: S3_V06S0203 Q4
|
|
arc: S3_V06S0303 Q5
|
|
arc: W3_H06W0203 F7
|
|
word: SLICED.K1.INIT 1111111111111111
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
|
|
.tile R23C35:PLC2
|
|
arc: E1_H02E0001 V02N0001
|
|
arc: E1_H02E0201 N1_V01S0000
|
|
arc: E1_H02E0601 S3_V06N0303
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: H00L0000 V02S0001
|
|
arc: H00R0000 V02S0401
|
|
arc: H00R0100 H02W0701
|
|
arc: N1_V02N0601 H01E0001
|
|
arc: N1_V02N0701 S1_V02N0601
|
|
arc: S1_V02S0201 H06E0103
|
|
arc: S1_V02S0401 E1_H02W0401
|
|
arc: S3_V06S0203 N1_V02S0701
|
|
arc: V00B0000 V02N0201
|
|
arc: V00B0100 V02S0301
|
|
arc: V00T0000 S1_V02N0401
|
|
arc: V00T0100 V02N0701
|
|
arc: W1_H02W0001 S3_V06N0003
|
|
arc: W1_H02W0601 V02S0601
|
|
arc: W3_H06W0203 E3_H06W0203
|
|
arc: CE0 H02W0101
|
|
arc: CE1 H02W0101
|
|
arc: CE2 H02E0101
|
|
arc: CE3 H02W0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0001 Q1
|
|
arc: E3_H06E0003 Q3
|
|
arc: E3_H06E0203 Q7
|
|
arc: M0 V00T0100
|
|
arc: M1 H00R0100
|
|
arc: M2 V00B0000
|
|
arc: M3 H00L0000
|
|
arc: M4 V00B0100
|
|
arc: M5 H00R0000
|
|
arc: M6 V00T0000
|
|
arc: M7 W1_H02E0201
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q0
|
|
arc: N1_V02N0001 Q2
|
|
arc: S1_V02S0601 Q4
|
|
arc: S1_V02S0701 Q5
|
|
arc: V01S0100 Q6
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R23C36:PLC2
|
|
arc: E1_H02E0001 E1_H01W0000
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
arc: H00L0100 N1_V02S0101
|
|
arc: H00R0000 V02S0601
|
|
arc: H00R0100 H02W0501
|
|
arc: N1_V02N0001 H01E0001
|
|
arc: S1_V02S0101 N1_V02S0001
|
|
arc: S1_V02S0401 N1_V02S0101
|
|
arc: V00B0000 V02S0001
|
|
arc: V00B0100 H02W0701
|
|
arc: W1_H02W0101 N1_V02S0101
|
|
arc: W1_H02W0201 V02N0201
|
|
arc: W1_H02W0701 N1_V01S0100
|
|
arc: CE0 N1_V02S0201
|
|
arc: CE1 H00R0100
|
|
arc: CE2 H00R0100
|
|
arc: CE3 H00L0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0001 Q1
|
|
arc: E1_H01E0101 Q1
|
|
arc: E1_H02E0201 Q0
|
|
arc: E1_H02E0501 Q7
|
|
arc: M0 H02E0601
|
|
arc: M1 H02E0001
|
|
arc: M2 V00B0000
|
|
arc: M3 H02W0201
|
|
arc: M5 H00R0000
|
|
arc: M6 V00B0100
|
|
arc: M7 H02E0201
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q1
|
|
arc: N1_V01N0101 Q6
|
|
arc: N1_V02N0301 Q1
|
|
arc: S1_V02S0201 Q2
|
|
arc: S1_V02S0501 Q5
|
|
arc: S3_V06S0003 Q3
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R23C37:PLC2
|
|
arc: E1_H02E0401 W3_H06E0203
|
|
arc: E1_H02E0501 W3_H06E0303
|
|
arc: E1_H02E0701 S3_V06N0203
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
arc: N1_V02N0001 H01E0001
|
|
arc: N1_V02N0101 H01E0101
|
|
arc: N1_V02N0201 S3_V06N0103
|
|
arc: N1_V02N0401 S3_V06N0203
|
|
arc: N1_V02N0501 H02E0501
|
|
arc: N1_V02N0601 S1_V02N0601
|
|
arc: N1_V02N0701 S3_V06N0203
|
|
arc: S1_V02S0501 S3_V06N0303
|
|
arc: S1_V02S0601 W3_H06E0303
|
|
arc: S3_V06S0203 N1_V02S0401
|
|
arc: V00T0000 H02W0201
|
|
arc: V00T0100 V02N0701
|
|
arc: V01S0100 S3_V06N0303
|
|
arc: W1_H02W0201 V02S0201
|
|
arc: W1_H02W0401 W3_H06E0203
|
|
arc: W1_H02W0501 S3_V06N0303
|
|
arc: W1_H02W0701 N1_V01S0100
|
|
arc: A2 V00B0000
|
|
arc: B2 H00R0100
|
|
arc: B4 E1_H02W0101
|
|
arc: C2 H00L0000
|
|
arc: C4 H02W0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D2 Q2
|
|
arc: D4 E1_H02W0201
|
|
arc: E1_H01E0101 F4
|
|
arc: E1_H02E0001 F2
|
|
arc: E1_H02E0301 Q3
|
|
arc: E1_H02E0601 F4
|
|
arc: E3_H06E0103 Q2
|
|
arc: F2 F2_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: H00L0000 Q0
|
|
arc: H00R0100 Q5
|
|
arc: H01W0000 Q3
|
|
arc: H01W0100 Q2
|
|
arc: LSR0 V00T0100
|
|
arc: LSR1 V00T0100
|
|
arc: M0 V00T0000
|
|
arc: M2 V00B0000
|
|
arc: M3 H01W0100
|
|
arc: M5 H00L0000
|
|
arc: M6 V00B0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR0
|
|
arc: S3_V06S0103 Q2
|
|
arc: V00B0000 Q6
|
|
arc: V00B0100 Q5
|
|
word: SLICEC.K0.INIT 0000000000001100
|
|
word: SLICEB.K0.INIT 0000000000000001
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R23C38:PLC2
|
|
arc: E1_H02E0301 E1_H01W0100
|
|
arc: E3_H06E0303 H01E0101
|
|
arc: H00L0000 H02W0001
|
|
arc: H00L0100 V02N0101
|
|
arc: H00R0000 N1_V02S0401
|
|
arc: N1_V02N0001 H06E0003
|
|
arc: N1_V02N0201 W1_H02E0201
|
|
arc: N1_V02N0701 H06E0203
|
|
arc: V00B0100 H02E0701
|
|
arc: W1_H02W0601 E1_H01W0000
|
|
arc: A1 E1_H02W0701
|
|
arc: A3 F5
|
|
arc: A4 F7
|
|
arc: A6 H00L0000
|
|
arc: A7 Q7
|
|
arc: B1 H02W0301
|
|
arc: B5 H02W0301
|
|
arc: B6 H02W0101
|
|
arc: B7 H02E0301
|
|
arc: C0 H02W0601
|
|
arc: C1 H00R0100
|
|
arc: C4 E1_H01E0101
|
|
arc: C6 V00B0100
|
|
arc: C7 V00T0000
|
|
arc: CE2 V02N0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H01E0101
|
|
arc: D1 H02W0001
|
|
arc: D3 H02W0001
|
|
arc: D4 H02E0001
|
|
arc: D5 E1_H01W0100
|
|
arc: D6 H02W0201
|
|
arc: D7 H01W0000
|
|
arc: E1_H01E0001 Q6
|
|
arc: E1_H01E0101 F3
|
|
arc: E1_H02E0501 Q7
|
|
arc: E1_H02E0701 F5
|
|
arc: E3_H06E0103 F1
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00R0100 Q7
|
|
arc: H01W0000 Q1
|
|
arc: LSR0 H02E0501
|
|
arc: LSR1 V00B0100
|
|
arc: M1 W1_H02E0001
|
|
arc: M3 H00L0100
|
|
arc: M4 E1_H02W0401
|
|
arc: M6 V00T0100
|
|
arc: M7 H00R0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR1
|
|
arc: N1_V01N0001 F1
|
|
arc: S3_V06S0103 F1
|
|
arc: S3_V06S0303 F6
|
|
arc: V00T0000 Q0
|
|
arc: V00T0100 Q3
|
|
arc: V01S0000 Q4
|
|
arc: V01S0100 F1
|
|
arc: W1_H02W0201 Q0
|
|
arc: W3_H06W0003 F0
|
|
arc: W3_H06W0103 F1
|
|
arc: W3_H06W0203 F4
|
|
word: SLICEA.K0.INIT 1111000000000000
|
|
word: SLICEC.K1.INIT 0000000000110011
|
|
word: SLICED.K0.INIT 1111000111110000
|
|
word: SLICEC.K0.INIT 1010000000000000
|
|
word: SLICEA.K1.INIT 0000000010000000
|
|
word: SLICEB.K1.INIT 0000000010101010
|
|
word: SLICED.K1.INIT 0000000000000001
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET SET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R23C39:PLC2
|
|
arc: E1_H02E0401 W1_H02E0401
|
|
arc: E1_H02E0501 W1_H02E0501
|
|
arc: N1_V02N0401 H01E0001
|
|
arc: S1_V02S0101 H02W0101
|
|
arc: V00B0100 H02E0501
|
|
arc: V00T0100 H02W0101
|
|
arc: W1_H02W0601 E1_H02W0601
|
|
arc: W3_H06W0303 E3_H06W0203
|
|
arc: A2 H02E0701
|
|
arc: A3 V00T0000
|
|
arc: A5 E1_H01W0000
|
|
arc: B0 V00T0000
|
|
arc: B1 V00T0000
|
|
arc: B3 H01W0100
|
|
arc: B5 H01E0101
|
|
arc: C0 H00L0100
|
|
arc: C1 H00L0100
|
|
arc: C2 W1_H02E0601
|
|
arc: C3 H00L0100
|
|
arc: C5 V02N0001
|
|
arc: CE0 H00R0100
|
|
arc: CE1 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V01S0100
|
|
arc: D1 V01S0100
|
|
arc: D3 V00B0100
|
|
arc: D5 E1_H01W0100
|
|
arc: E1_H01E0101 Q2
|
|
arc: E1_H02E0001 Q2
|
|
arc: E1_H02E0101 Q1
|
|
arc: E1_H02E0201 Q0
|
|
arc: E1_H02E0301 F3
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: H00L0100 Q1
|
|
arc: H00R0100 F5
|
|
arc: H01W0000 Q0
|
|
arc: H01W0100 Q2
|
|
arc: LSR1 V00T0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR1
|
|
arc: V00T0000 Q0
|
|
arc: V01S0100 Q2
|
|
arc: W1_H02W0001 Q0
|
|
arc: W1_H02W0101 Q1
|
|
arc: W1_H02W0201 Q2
|
|
arc: W1_H02W0301 Q1
|
|
arc: W3_H06W0003 Q0
|
|
arc: W3_H06W0103 Q1
|
|
word: SLICEA.K0.INIT 1111000011001100
|
|
word: SLICEA.K1.INIT 1100001111110000
|
|
word: SLICEB.K0.INIT 1111101011111010
|
|
word: SLICEC.K1.INIT 0101000100000000
|
|
word: SLICEB.K1.INIT 0000000001000000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R23C3:PLC2
|
|
arc: E3_H06E0203 W1_H02E0701
|
|
arc: E3_H06E0303 W1_H02E0501
|
|
arc: S3_V06S0203 E3_H06W0203
|
|
arc: S3_V06S0303 E3_H06W0303
|
|
|
|
.tile R23C40:PLC2
|
|
arc: E1_H01E0101 W3_H06E0203
|
|
arc: E1_H02E0101 S3_V06N0103
|
|
arc: E1_H02E0601 W3_H06E0303
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
arc: H00L0000 H02E0001
|
|
arc: N1_V02N0101 S3_V06N0103
|
|
arc: S1_V02S0101 S3_V06N0103
|
|
arc: S1_V02S0601 H06E0303
|
|
arc: S3_V06S0103 H06E0103
|
|
arc: V00B0000 V02N0001
|
|
arc: V00T0100 W1_H02E0301
|
|
arc: W1_H02W0101 S3_V06N0103
|
|
arc: W1_H02W0401 V02N0401
|
|
arc: W1_H02W0701 H01E0101
|
|
arc: A0 W1_H02E0701
|
|
arc: A3 V00B0000
|
|
arc: A5 V00T0000
|
|
arc: A6 F5
|
|
arc: B2 H02E0101
|
|
arc: B3 H02E0101
|
|
arc: B5 H02E0301
|
|
arc: B6 H02E0101
|
|
arc: C3 H00L0000
|
|
arc: C5 S1_V02N0001
|
|
arc: C6 V00T0100
|
|
arc: CE0 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H02E0201
|
|
arc: D2 H02E0001
|
|
arc: D3 H02E0201
|
|
arc: D5 F0
|
|
arc: D6 H02E0201
|
|
arc: E3_H06E0003 Q0
|
|
arc: F0 F0_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: H00R0000 F6
|
|
arc: H01W0000 F2
|
|
arc: H01W0100 F5
|
|
arc: LSR0 H02E0501
|
|
arc: M2 H02W0601
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: V00T0000 Q0
|
|
word: SLICEB.K0.INIT 0000000011001100
|
|
word: SLICEC.K1.INIT 0011001100100000
|
|
word: SLICEB.K1.INIT 0000110000000100
|
|
word: SLICED.K0.INIT 0000001010000000
|
|
word: SLICEA.K0.INIT 0101010111111111
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
|
|
.tile R23C41:PLC2
|
|
arc: E1_H02E0001 S1_V02N0001
|
|
arc: E1_H02E0101 W3_H06E0103
|
|
arc: E1_H02E0501 W1_H02E0401
|
|
arc: H00L0000 E1_H02W0001
|
|
arc: H00R0000 V02S0401
|
|
arc: H00R0100 V02S0501
|
|
arc: N1_V02N0101 H01E0101
|
|
arc: N1_V02N0201 S1_V02N0201
|
|
arc: N1_V02N0301 H01E0101
|
|
arc: S1_V02S0001 E1_H02W0001
|
|
arc: S1_V02S0701 E1_H02W0701
|
|
arc: V00B0100 V02S0101
|
|
arc: V00T0100 V02S0701
|
|
arc: V01S0000 S3_V06N0103
|
|
arc: W1_H02W0601 S1_V02N0601
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
arc: CE0 H02E0101
|
|
arc: CE2 H02E0101
|
|
arc: CE3 H00L0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: M0 V00T0100
|
|
arc: M1 H00R0100
|
|
arc: M5 H00R0000
|
|
arc: M6 V00B0100
|
|
arc: M7 E1_H02W0201
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: S1_V02S0101 Q1
|
|
arc: S1_V02S0601 Q6
|
|
arc: S3_V06S0003 Q0
|
|
arc: S3_V06S0203 Q7
|
|
arc: V01S0100 Q5
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R23C42:PLC2
|
|
arc: E1_H02E0101 N1_V02S0101
|
|
arc: E1_H02E0201 V02S0201
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
arc: H00L0000 H02W0001
|
|
arc: H00L0100 N1_V02S0101
|
|
arc: H00R0000 V02S0601
|
|
arc: H00R0100 H02W0501
|
|
arc: N1_V02N0001 H02W0001
|
|
arc: S1_V02S0001 H06W0003
|
|
arc: S1_V02S0301 H02W0301
|
|
arc: S3_V06S0203 E1_H01W0000
|
|
arc: S3_V06S0303 E1_H01W0100
|
|
arc: V00B0000 W1_H02E0601
|
|
arc: V00B0100 V02S0101
|
|
arc: V00T0000 V02N0401
|
|
arc: V00T0100 H02E0101
|
|
arc: CE0 N1_V02S0201
|
|
arc: CE1 H00L0000
|
|
arc: CE2 H00L0100
|
|
arc: CE3 H00L0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0001 Q7
|
|
arc: M0 V00T0000
|
|
arc: M1 H02E0001
|
|
arc: M2 V00B0100
|
|
arc: M3 H00R0000
|
|
arc: M4 V00T0100
|
|
arc: M5 H00R0100
|
|
arc: M6 V00B0000
|
|
arc: M7 E1_H02W0201
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q7
|
|
arc: N1_V01N0101 Q7
|
|
arc: N1_V02N0201 Q0
|
|
arc: N1_V02N0301 Q1
|
|
arc: N1_V02N0401 Q6
|
|
arc: N1_V02N0501 Q5
|
|
arc: N1_V02N0701 Q7
|
|
arc: S3_V06S0003 Q3
|
|
arc: S3_V06S0103 Q2
|
|
arc: V01S0100 Q4
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R23C43:PLC2
|
|
arc: E1_H02E0201 S3_V06N0103
|
|
arc: E1_H02E0301 S3_V06N0003
|
|
arc: H00L0100 V02S0301
|
|
arc: H00R0000 V02N0601
|
|
arc: H00R0100 W1_H02E0501
|
|
arc: N1_V02N0001 H01E0001
|
|
arc: N1_V02N0301 S3_V06N0003
|
|
arc: N1_V02N0501 S3_V06N0303
|
|
arc: N1_V02N0701 H06E0203
|
|
arc: S1_V02S0301 S3_V06N0003
|
|
arc: S1_V02S0501 W3_H06E0303
|
|
arc: S3_V06S0303 E1_H01W0100
|
|
arc: V00B0000 E1_H02W0601
|
|
arc: V00B0100 V02S0101
|
|
arc: V00T0000 H02W0001
|
|
arc: V00T0100 V02S0501
|
|
arc: W1_H02W0001 S3_V06N0003
|
|
arc: W1_H02W0201 V02S0201
|
|
arc: W1_H02W0301 S3_V06N0003
|
|
arc: W1_H02W0501 N1_V01S0100
|
|
arc: CE0 H02E0101
|
|
arc: CE1 S1_V02N0201
|
|
arc: CE2 H00R0100
|
|
arc: CE3 H02E0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0001 Q7
|
|
arc: E1_H01E0101 Q0
|
|
arc: E1_H02E0401 Q6
|
|
arc: E1_H02E0501 Q7
|
|
arc: E3_H06E0103 Q1
|
|
arc: E3_H06E0203 Q7
|
|
arc: H01W0000 Q3
|
|
arc: H01W0100 Q4
|
|
arc: M0 V00T0000
|
|
arc: M1 E1_H02W0001
|
|
arc: M2 V00T0100
|
|
arc: M3 E1_H02W0201
|
|
arc: M4 V00B0100
|
|
arc: M5 H00L0100
|
|
arc: M6 V00B0000
|
|
arc: M7 H00R0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q1
|
|
arc: N1_V01N0101 Q1
|
|
arc: S3_V06S0103 Q2
|
|
arc: W1_H02W0701 Q5
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R23C44:PLC2
|
|
arc: E1_H02E0101 W3_H06E0103
|
|
arc: E1_H02E0201 V01N0001
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
arc: H00L0100 H02E0301
|
|
arc: H00R0000 V02S0601
|
|
arc: H00R0100 V02S0701
|
|
arc: N1_V02N0101 S1_V02N0101
|
|
arc: N1_V02N0201 H01E0001
|
|
arc: N1_V02N0301 S3_V06N0003
|
|
arc: N1_V02N0401 H02E0401
|
|
arc: N1_V02N0701 H01E0101
|
|
arc: V00T0000 W1_H02E0201
|
|
arc: W1_H02W0001 V02S0001
|
|
arc: W1_H02W0201 S1_V02N0201
|
|
arc: CE0 H00L0100
|
|
arc: CE1 N1_V02S0201
|
|
arc: CE2 H00L0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: H01W0100 Q5
|
|
arc: M0 V00T0000
|
|
arc: M1 H00R0000
|
|
arc: M3 H02E0201
|
|
arc: M5 H00R0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: S3_V06S0003 Q0
|
|
arc: S3_V06S0103 Q1
|
|
arc: V01S0000 Q3
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R23C45:PLC2
|
|
arc: E1_H02E0301 W1_H02E0301
|
|
arc: N1_V02N0501 W1_H02E0501
|
|
arc: S1_V02S0301 W1_H02E0301
|
|
arc: V00B0100 V02N0301
|
|
arc: W1_H02W0001 V06S0003
|
|
arc: W1_H02W0201 V02S0201
|
|
arc: W1_H02W0601 E1_H02W0301
|
|
arc: W3_H06W0003 S3_V06N0003
|
|
arc: W3_H06W0203 E3_H06W0203
|
|
arc: CE0 H02E0101
|
|
arc: CE3 H02E0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E3_H06E0003 Q0
|
|
arc: E3_H06E0203 Q7
|
|
arc: LSR0 W1_H02E0301
|
|
arc: M0 V00B0100
|
|
arc: M7 H02E0201
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR3 LSR0
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R23C46:PLC2
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: N1_V02N0101 H06E0103
|
|
arc: N1_V02N0201 H06E0103
|
|
arc: N1_V02N0401 W3_H06E0203
|
|
arc: N1_V02N0701 H06E0203
|
|
arc: V00B0100 V02N0301
|
|
arc: CE0 W1_H02E0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: LSR1 H02E0301
|
|
arc: M0 V00B0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: N3_V06N0003 Q0
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R23C47:PLC2
|
|
arc: V01S0000 S3_V06N0103
|
|
arc: W1_H02W0301 E3_H06W0003
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
|
|
.tile R23C48:PLC2
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
|
|
.tile R23C50:PLC2
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
|
|
.tile R23C51:PLC2
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
arc: W3_H06W0203 E3_H06W0203
|
|
|
|
.tile R23C52:PLC2
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
|
|
.tile R23C53:PLC2
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
|
|
.tile R23C54:PLC2
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
|
|
.tile R23C56:PLC2
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
|
|
.tile R23C57:PLC2
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
arc: N3_V06N0103 W3_H06E0103
|
|
arc: W3_H06W0203 E3_H06W0203
|
|
|
|
.tile R23C58:PLC2
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
|
|
.tile R23C59:PLC2
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
|
|
.tile R23C60:PLC2
|
|
arc: N3_V06N0003 W3_H06E0003
|
|
arc: N3_V06N0303 H06E0303
|
|
|
|
.tile R23C62:PLC2
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
|
|
.tile R23C63:PLC2
|
|
arc: W3_H06W0203 E3_H06W0203
|
|
|
|
.tile R23C64:PLC2
|
|
arc: N3_V06N0103 W3_H06E0103
|
|
|
|
.tile R23C65:PLC2
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
|
|
.tile R23C68:PLC2
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
|
|
.tile R23C69:PLC2
|
|
arc: W3_H06W0203 E3_H06W0203
|
|
|
|
.tile R23C71:PLC2
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
arc: W3_H06W0303 E3_H06W0203
|
|
|
|
.tile R23C74:PLC2
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
|
|
.tile R23C75:PLC2
|
|
arc: W3_H06W0203 E3_H06W0203
|
|
|
|
.tile R23C77:PLC2
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
|
|
.tile R23C7:PLC2
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
|
|
.tile R23C80:PLC2
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
|
|
.tile R23C81:PLC2
|
|
arc: W3_H06W0203 E3_H06W0203
|
|
|
|
.tile R23C83:PLC2
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
|
|
.tile R23C86:PLC2
|
|
arc: S3_V06S0203 W3_H06E0203
|
|
|
|
.tile R23C87:PLC2
|
|
arc: W3_H06W0203 E1_H02W0701
|
|
|
|
.tile R23C8:PLC2
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
|
|
.tile R23C9:PLC2
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
arc: W3_H06W0203 E3_H06W0203
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
|
|
.tile R24C10:PLC2
|
|
arc: W3_H06W0303 E3_H06W0203
|
|
|
|
.tile R24C12:PLC2
|
|
arc: W3_H06W0303 E3_H06W0203
|
|
|
|
.tile R24C13:PLC2
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
|
|
.tile R24C15:PLC2
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
|
|
.tile R24C16:PLC2
|
|
arc: E1_H02E0001 S3_V06N0003
|
|
arc: V00B0000 V02S0001
|
|
arc: V00B0100 E1_H02W0501
|
|
arc: CE2 V02S0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: LSR0 V00B0000
|
|
arc: M4 V00B0100
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR2 LSR0
|
|
arc: W3_H06W0203 Q4
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R24C18:PLC2
|
|
arc: E1_H02E0001 S1_V02N0001
|
|
arc: H00R0000 V02N0401
|
|
arc: H00R0100 E1_H02W0501
|
|
arc: V00T0000 H02W0001
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
arc: CE0 H00R0100
|
|
arc: CE3 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: LSR0 V00T0000
|
|
arc: M1 W1_H02E0001
|
|
arc: M7 H00R0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR3 LSR0
|
|
arc: N1_V01N0001 Q1
|
|
arc: W1_H02W0501 Q7
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R24C19:PLC2
|
|
arc: E1_H02E0301 V02S0301
|
|
arc: E1_H02E0401 W3_H06E0203
|
|
arc: E1_H02E0601 V02S0601
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
arc: N3_V06N0203 E3_H06W0203
|
|
arc: V00B0000 V02S0001
|
|
arc: W1_H02W0001 V02S0001
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
arc: CE2 E1_H02W0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: LSR1 V00B0000
|
|
arc: M5 H02E0001
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR2 LSR1
|
|
arc: N1_V01N0001 Q5
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R24C20:PLC2
|
|
arc: H00R0000 H02E0601
|
|
arc: H00R0100 E1_H02W0501
|
|
arc: W1_H02W0501 E1_H02W0501
|
|
arc: CE2 H00R0100
|
|
arc: CE3 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: LSR1 H02E0301
|
|
arc: M5 H00R0000
|
|
arc: M6 H02E0401
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR1
|
|
arc: N1_V01N0001 Q5
|
|
arc: N1_V02N0401 Q6
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R24C21:PLC2
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
arc: N1_V02N0301 W1_H02E0301
|
|
arc: W1_H02W0101 E1_H01W0100
|
|
|
|
.tile R24C22:PLC2
|
|
arc: E1_H02E0601 V06S0303
|
|
arc: E3_H06E0103 N1_V01S0100
|
|
arc: E3_H06E0203 N1_V01S0000
|
|
arc: H00R0000 N1_V02S0601
|
|
arc: H00R0100 V02S0501
|
|
arc: H01W0100 E3_H06W0303
|
|
arc: N1_V02N0401 S1_V02N0101
|
|
arc: V00B0100 N1_V02S0101
|
|
arc: V00T0000 N1_V02S0401
|
|
arc: W1_H02W0501 E3_H06W0303
|
|
arc: CE0 V02S0201
|
|
arc: CE1 V02S0201
|
|
arc: CE3 E1_H02W0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H02E0301 Q1
|
|
arc: M0 V00T0000
|
|
arc: M1 H00R0000
|
|
arc: M2 V00B0100
|
|
arc: M7 H00R0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V02N0501 Q7
|
|
arc: V01S0000 Q2
|
|
arc: V01S0100 Q0
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R24C23:PLC2
|
|
arc: E3_H06E0303 N1_V01S0100
|
|
|
|
.tile R24C24:PLC2
|
|
arc: E1_H02E0101 V06S0103
|
|
arc: E1_H02E0201 E1_H01W0000
|
|
arc: E1_H02E0301 W1_H02E0301
|
|
arc: E1_H02E0701 W1_H02E0601
|
|
arc: N1_V02N0001 H06W0003
|
|
arc: N1_V02N0601 H06E0303
|
|
arc: V00T0000 E1_H02W0201
|
|
arc: V00T0100 V02S0701
|
|
arc: W1_H02W0101 V06S0103
|
|
arc: CE1 V02S0201
|
|
arc: CLK0 G_HPBX0000
|
|
arc: LSR0 V00T0100
|
|
arc: M2 V00T0000
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXLSR1 LSR0
|
|
arc: W3_H06W0103 Q2
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R24C25:PLC2
|
|
arc: E1_H02E0401 S1_V02N0401
|
|
arc: H01W0000 E3_H06W0103
|
|
arc: N1_V02N0001 S1_V02N0001
|
|
arc: N1_V02N0201 S1_V02N0201
|
|
arc: N1_V02N0601 W3_H06E0303
|
|
arc: S1_V02S0001 N1_V01S0000
|
|
arc: S1_V02S0101 H06E0103
|
|
arc: S1_V02S0501 E1_H01W0100
|
|
arc: S1_V02S0701 H06E0203
|
|
arc: V00B0100 V02N0301
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
arc: CE3 V02S0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: LSR0 V00B0100
|
|
arc: M7 H02E0201
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR3 LSR0
|
|
arc: W3_H06W0203 Q7
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R24C26:PLC2
|
|
arc: E1_H02E0201 V02S0201
|
|
arc: H00L0000 V02N0201
|
|
arc: H00L0100 S1_V02N0101
|
|
arc: H00R0000 S1_V02N0401
|
|
arc: H00R0100 N1_V02S0501
|
|
arc: S1_V02S0301 W1_H02E0301
|
|
arc: S1_V02S0501 H06E0303
|
|
arc: S1_V02S0701 W1_H02E0701
|
|
arc: V00B0000 N1_V02S0201
|
|
arc: V00T0000 N1_V02S0601
|
|
arc: W1_H02W0201 E1_H02W0201
|
|
arc: CE0 H00R0000
|
|
arc: CE1 W1_H02E0101
|
|
arc: CE2 W1_H02E0101
|
|
arc: CE3 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0001 Q3
|
|
arc: H01W0100 Q1
|
|
arc: M0 V00B0000
|
|
arc: M1 H02W0001
|
|
arc: M3 H00L0000
|
|
arc: M5 H00L0100
|
|
arc: M6 V00T0000
|
|
arc: M7 H00R0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0101 Q7
|
|
arc: N1_V02N0701 Q5
|
|
arc: S1_V02S0201 Q0
|
|
arc: V01S0100 Q6
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R24C27:PLC2
|
|
arc: E1_H02E0401 W1_H02E0401
|
|
arc: E1_H02E0601 V01N0001
|
|
arc: E3_H06E0203 V06S0203
|
|
arc: H00L0100 H02W0301
|
|
arc: H00R0000 V02S0401
|
|
arc: H00R0100 N1_V02S0501
|
|
arc: N1_V02N0201 H01E0001
|
|
arc: S1_V02S0301 H02W0301
|
|
arc: V00B0100 N1_V02S0101
|
|
arc: V00T0000 N1_V02S0601
|
|
arc: V00T0100 N1_V02S0701
|
|
arc: W1_H02W0001 N1_V02S0001
|
|
arc: W3_H06W0003 E1_H01W0000
|
|
arc: CE0 H00L0100
|
|
arc: CE1 V02N0201
|
|
arc: CE2 H00R0000
|
|
arc: CE3 E1_H02W0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0001 Q7
|
|
arc: E1_H01E0101 Q0
|
|
arc: E3_H06E0003 Q3
|
|
arc: E3_H06E0103 Q2
|
|
arc: E3_H06E0303 Q5
|
|
arc: M0 V00T0100
|
|
arc: M2 V00T0000
|
|
arc: M3 H00R0100
|
|
arc: M4 V00B0100
|
|
arc: M5 H02W0001
|
|
arc: M6 E1_H02W0401
|
|
arc: M7 H02E0201
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V02N0601 Q6
|
|
arc: V01S0100 Q4
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R24C28:PLC2
|
|
arc: E1_H02E0201 S3_V06N0103
|
|
arc: E1_H02E0301 V02N0301
|
|
arc: E3_H06E0103 H01E0101
|
|
arc: N1_V02N0201 H01E0001
|
|
arc: N1_V02N0601 V01N0001
|
|
arc: V00B0100 V02N0301
|
|
arc: V00T0100 V02N0501
|
|
arc: W1_H02W0001 N1_V02S0001
|
|
arc: W1_H02W0301 V02N0301
|
|
arc: C5 S1_V02N0001
|
|
arc: CE0 H00R0100
|
|
arc: CE1 H00R0100
|
|
arc: CE3 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D5 V02S0401
|
|
arc: E1_H02E0501 F5
|
|
arc: E1_H02E0701 F5
|
|
arc: E3_H06E0303 F5
|
|
arc: F5 F5_SLICE
|
|
arc: H00R0100 F5
|
|
arc: H01W0000 Q0
|
|
arc: LSR0 V00B0100
|
|
arc: LSR1 V00B0100
|
|
arc: M0 H02W0601
|
|
arc: M2 H02E0601
|
|
arc: M6 V00T0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR3 LSR0
|
|
arc: N1_V01N0101 F5
|
|
arc: N1_V02N0701 F5
|
|
arc: S1_V02S0701 F5
|
|
arc: S3_V06S0303 F5
|
|
arc: V01S0000 Q6
|
|
arc: W1_H02W0201 Q2
|
|
arc: W3_H06W0303 F5
|
|
word: SLICEC.K1.INIT 1111000000000000
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R24C29:PLC2
|
|
arc: E1_H02E0401 W1_H02E0401
|
|
arc: H00R0100 H02E0501
|
|
arc: W1_H02W0101 V06S0103
|
|
arc: W1_H02W0401 V02N0401
|
|
arc: W1_H02W0601 S1_V02N0601
|
|
arc: CE3 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E3_H06E0203 Q7
|
|
arc: LSR1 H02E0301
|
|
arc: M7 H02E0201
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR3 LSR1
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R24C30:PLC2
|
|
arc: E1_H02E0101 V06S0103
|
|
arc: E1_H02E0701 W1_H02E0701
|
|
|
|
.tile R24C31:PLC2
|
|
arc: E1_H02E0101 N1_V02S0101
|
|
arc: H00R0100 H02E0701
|
|
arc: N1_V02N0401 W1_H02E0401
|
|
arc: V00B0000 E1_H02W0601
|
|
arc: V00B0100 N1_V02S0101
|
|
arc: V00T0000 V02S0401
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
arc: CE0 H00R0100
|
|
arc: CE3 V02S0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E3_H06E0103 Q1
|
|
arc: LSR0 V00B0100
|
|
arc: LSR1 V00T0000
|
|
arc: M1 H02W0001
|
|
arc: M6 V00B0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR3 LSR0
|
|
arc: W3_H06W0303 Q6
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R24C32:PLC2
|
|
arc: E1_H02E0101 W1_H02E0101
|
|
arc: E1_H02E0501 V06S0303
|
|
arc: H00R0000 N1_V02S0401
|
|
arc: S1_V02S0101 N1_V01S0100
|
|
arc: S1_V02S0301 H02W0301
|
|
arc: S1_V02S0401 N1_V01S0000
|
|
arc: S1_V02S0501 V01N0101
|
|
arc: S1_V02S0601 V01N0001
|
|
arc: S1_V02S0701 H02W0701
|
|
arc: V00B0000 V02N0201
|
|
arc: V00B0100 N1_V02S0301
|
|
arc: W1_H02W0001 V02S0001
|
|
arc: CE0 H02E0101
|
|
arc: CE1 W1_H02E0101
|
|
arc: CE2 H02E0101
|
|
arc: CE3 W1_H02E0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0001 Q6
|
|
arc: M1 H00R0000
|
|
arc: M2 V00B0000
|
|
arc: M4 V00B0100
|
|
arc: M6 H02W0401
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0101 Q4
|
|
arc: N1_V02N0001 Q2
|
|
arc: V01S0000 Q1
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R24C33:PLC2
|
|
arc: E1_H02E0101 W3_H06E0103
|
|
arc: N1_V02N0601 H01E0001
|
|
arc: S1_V02S0101 H02W0101
|
|
arc: S1_V02S0301 W3_H06E0003
|
|
arc: S1_V02S0401 V01N0001
|
|
arc: S1_V02S0501 W3_H06E0303
|
|
arc: S1_V02S0601 N1_V01S0000
|
|
arc: S1_V02S0701 V01N0101
|
|
arc: W1_H02W0301 V06S0003
|
|
arc: W1_H02W0401 V02N0401
|
|
arc: W1_H02W0601 E1_H02W0301
|
|
arc: W1_H02W0701 W3_H06E0203
|
|
arc: CE2 H02E0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: M5 H02W0001
|
|
arc: MUXCLK2 CLK0
|
|
arc: N1_V02N0701 Q5
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R24C34:PLC2
|
|
arc: E1_H02E0101 V02S0101
|
|
arc: E1_H02E0201 S3_V06N0103
|
|
arc: E1_H02E0401 V02S0401
|
|
arc: E1_H02E0601 W3_H06E0303
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
arc: S1_V02S0101 H02E0101
|
|
arc: S1_V02S0501 W1_H02E0501
|
|
arc: W1_H02W0001 S1_V02N0001
|
|
arc: W1_H02W0101 W3_H06E0103
|
|
|
|
.tile R24C35:PLC2
|
|
arc: E1_H02E0201 S1_V02N0201
|
|
arc: E1_H02E0701 W3_H06E0203
|
|
arc: H00L0000 N1_V02S0201
|
|
arc: H00R0000 V02S0401
|
|
arc: H00R0100 N1_V02S0501
|
|
arc: N1_V02N0001 S3_V06N0003
|
|
arc: N1_V02N0201 S3_V06N0103
|
|
arc: N1_V02N0501 N1_V01S0100
|
|
arc: N1_V02N0701 S3_V06N0203
|
|
arc: S1_V02S0301 E1_H01W0100
|
|
arc: V00B0100 N1_V02S0101
|
|
arc: V00T0100 N1_V02S0701
|
|
arc: W1_H02W0301 E3_H06W0003
|
|
arc: CE0 H00R0000
|
|
arc: CE1 V02S0201
|
|
arc: CE2 H02W0101
|
|
arc: CE3 H02E0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0101 Q4
|
|
arc: E1_H02E0101 Q3
|
|
arc: E1_H02E0501 Q7
|
|
arc: M0 V00T0100
|
|
arc: M1 E1_H02W0001
|
|
arc: M3 H00L0000
|
|
arc: M4 H02E0401
|
|
arc: M6 V00B0100
|
|
arc: M7 H00R0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: S1_V02S0001 Q0
|
|
arc: S1_V02S0101 Q1
|
|
arc: S1_V02S0601 Q6
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R24C36:PLC2
|
|
arc: E1_H02E0201 V06S0103
|
|
arc: E1_H02E0401 V06S0203
|
|
arc: E1_H02E0601 W1_H02E0601
|
|
arc: H00L0000 V02N0001
|
|
arc: H00L0100 N1_V02S0101
|
|
arc: H00R0000 V02S0401
|
|
arc: H00R0100 N1_V02S0501
|
|
arc: N1_V02N0101 H01E0101
|
|
arc: N1_V02N0201 W1_H02E0201
|
|
arc: S1_V02S0101 H02E0101
|
|
arc: S1_V02S0401 E1_H01W0000
|
|
arc: S1_V02S0501 H02E0501
|
|
arc: V00T0100 N1_V02S0701
|
|
arc: W1_H02W0101 V06S0103
|
|
arc: A0 H02W0701
|
|
arc: B0 E1_H01W0100
|
|
arc: C0 H02W0601
|
|
arc: CE0 H02W0101
|
|
arc: CE1 H02W0101
|
|
arc: CE2 H00R0000
|
|
arc: CE3 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 S1_V02N0201
|
|
arc: E1_H01E0101 Q7
|
|
arc: E1_H02E0501 Q5
|
|
arc: F0 F0_SLICE
|
|
arc: H01W0100 Q3
|
|
arc: M1 H00L0100
|
|
arc: M2 V00T0100
|
|
arc: M3 H00R0100
|
|
arc: M5 H00L0000
|
|
arc: M6 H02W0401
|
|
arc: M7 H02E0201
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V02N0601 Q6
|
|
arc: S1_V02S0201 Q2
|
|
arc: S1_V02S0301 Q1
|
|
arc: S3_V06S0003 Q0
|
|
word: SLICEA.K0.INIT 0000111110001010
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
|
|
.tile R24C37:PLC2
|
|
arc: E1_H02E0001 S1_V02N0001
|
|
arc: E1_H02E0301 N1_V01S0100
|
|
arc: E1_H02E0701 N1_V01S0100
|
|
arc: H00R0100 V02S0501
|
|
arc: N1_V02N0301 H01E0101
|
|
arc: N1_V02N0501 H02E0501
|
|
arc: N1_V02N0701 N1_V01S0100
|
|
arc: S1_V02S0101 W3_H06E0103
|
|
arc: S1_V02S0201 E1_H01W0000
|
|
arc: S1_V02S0301 E1_H02W0301
|
|
arc: S1_V02S0401 E3_H06W0203
|
|
arc: S1_V02S0601 E1_H02W0601
|
|
arc: S1_V02S0701 W1_H02E0701
|
|
arc: W1_H02W0001 N1_V02S0001
|
|
arc: W1_H02W0101 N1_V01S0100
|
|
arc: W1_H02W0401 S1_V02N0401
|
|
arc: W1_H02W0601 V02N0601
|
|
arc: W1_H02W0701 V01N0101
|
|
arc: A0 V02N0501
|
|
arc: B0 F1
|
|
arc: C0 V02N0401
|
|
arc: C1 H02E0401
|
|
arc: CE0 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02N0201
|
|
arc: D1 H02W0201
|
|
arc: D4 H02E0201
|
|
arc: E1_H01E0001 F1
|
|
arc: E1_H02E0601 F4
|
|
arc: E3_H06E0103 F1
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: H01W0000 F1
|
|
arc: H01W0100 F1
|
|
arc: MUXCLK0 CLK0
|
|
arc: S3_V06S0103 F1
|
|
arc: W3_H06W0003 Q0
|
|
word: SLICEC.K0.INIT 0000000011111111
|
|
word: SLICEA.K0.INIT 0101010111010000
|
|
word: SLICEA.K1.INIT 0000000000001111
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
|
|
.tile R24C38:PLC2
|
|
arc: E1_H02E0101 N1_V01S0100
|
|
arc: N1_V02N0201 H01E0001
|
|
arc: N1_V02N0601 W1_H02E0601
|
|
arc: S1_V02S0101 E1_H01W0100
|
|
arc: S1_V02S0401 E1_H02W0401
|
|
arc: S1_V02S0501 H02W0501
|
|
arc: S1_V02S0601 H01E0001
|
|
arc: V00B0000 H02E0601
|
|
arc: V00B0100 H02W0701
|
|
arc: W1_H02W0201 N1_V01S0000
|
|
arc: A1 V02N0501
|
|
arc: A2 V01N0101
|
|
arc: A3 V01N0101
|
|
arc: A7 V02N0101
|
|
arc: B1 V02N0301
|
|
arc: B2 V01N0001
|
|
arc: B3 V02N0301
|
|
arc: C1 H00R0100
|
|
arc: C2 V02N0401
|
|
arc: C3 V02N0601
|
|
arc: C7 V02N0201
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D1 S1_V02N0001
|
|
arc: D2 V02N0001
|
|
arc: D3 V02N0001
|
|
arc: E1_H01E0001 F3
|
|
arc: F0 F5A_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00R0100 F7
|
|
arc: H01W0000 F0
|
|
arc: LSR1 V00B0000
|
|
arc: M0 V00B0100
|
|
arc: M1 H02E0001
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: N1_V02N0101 Q1
|
|
arc: S1_V02S0001 F2
|
|
word: SLICED.K1.INIT 0000010100000101
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000010000
|
|
word: SLICEB.K1.INIT 1000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000001
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
|
|
.tile R24C39:PLC2
|
|
arc: E1_H02E0001 W1_H02E0001
|
|
arc: E1_H02E0201 S1_V02N0201
|
|
arc: E3_H06E0103 N1_V01S0100
|
|
arc: H00L0000 H02W0001
|
|
arc: N1_V02N0001 H02W0001
|
|
arc: N1_V02N0701 W1_H02E0701
|
|
arc: S1_V02S0401 H01E0001
|
|
arc: S1_V02S0501 E3_H06W0303
|
|
arc: S1_V02S0701 W1_H02E0701
|
|
arc: V00B0000 V02N0201
|
|
arc: V00B0100 H02W0501
|
|
arc: W1_H02W0301 E3_H06W0003
|
|
arc: W1_H02W0501 E3_H06W0303
|
|
arc: A1 V02N0501
|
|
arc: A5 V02N0101
|
|
arc: A6 S1_V02N0101
|
|
arc: A7 V02N0301
|
|
arc: B1 E1_H02W0301
|
|
arc: B5 S1_V02N0701
|
|
arc: B6 V02N0701
|
|
arc: B7 V00B0000
|
|
arc: C1 V02N0601
|
|
arc: C5 V01N0101
|
|
arc: C6 S1_V02N0001
|
|
arc: C7 V02N0001
|
|
arc: CE3 H00L0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D1 E1_H02W0001
|
|
arc: D5 V02N0401
|
|
arc: D6 H02W0201
|
|
arc: D7 V01N0001
|
|
arc: F0 F5A_SLICE
|
|
arc: F4 F5C_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0100 Q7
|
|
arc: LSR1 W1_H02E0301
|
|
arc: M0 H02W0601
|
|
arc: M4 V00B0100
|
|
arc: M7 E1_H02W0201
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR3 LSR1
|
|
arc: S1_V02S0201 F0
|
|
arc: S1_V02S0601 F4
|
|
arc: W1_H02W0601 F6
|
|
arc: W1_H02W0701 F7
|
|
word: SLICED.K1.INIT 0000000000000001
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 1000000000000000
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 1000000000000000
|
|
word: SLICED.K0.INIT 0000000000000001
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
|
|
.tile R24C3:PLC2
|
|
arc: E3_H06E0303 W1_H02E0501
|
|
arc: S3_V06S0003 H06W0003
|
|
|
|
.tile R24C40:PLC2
|
|
arc: E1_H02E0101 V02S0101
|
|
arc: E1_H02E0601 S1_V02N0601
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
arc: H00L0100 V02N0101
|
|
arc: N1_V02N0001 H02E0001
|
|
arc: N1_V02N0401 H02W0401
|
|
arc: S1_V02S0201 H06W0103
|
|
arc: S1_V02S0301 E1_H02W0301
|
|
arc: S1_V02S0701 N1_V02S0701
|
|
arc: V00B0000 V02N0201
|
|
arc: V00B0100 V02S0101
|
|
arc: V00T0000 H02E0201
|
|
arc: V00T0100 V02N0701
|
|
arc: W1_H02W0001 W3_H06E0003
|
|
arc: W1_H02W0201 V02N0201
|
|
arc: W1_H02W0601 V01N0001
|
|
arc: A1 V01N0101
|
|
arc: A4 H02W0701
|
|
arc: A5 V02N0301
|
|
arc: B1 V02N0301
|
|
arc: B4 V02N0701
|
|
arc: B7 V02N0501
|
|
arc: C1 V02N0401
|
|
arc: C4 V01N0101
|
|
arc: CE3 W1_H02E0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D1 V00T0100
|
|
arc: D4 H02W0001
|
|
arc: D5 V02N0401
|
|
arc: D7 V02N0601
|
|
arc: F0 F5A_SLICE
|
|
arc: F1 FXA_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: LSR1 V00B0100
|
|
arc: M0 V00B0000
|
|
arc: M1 H00L0100
|
|
arc: M2 V00B0000
|
|
arc: M6 V00T0000
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR3 LSR1
|
|
arc: N3_V06N0303 Q6
|
|
arc: S1_V02S0101 F1
|
|
arc: S1_V02S0501 F5
|
|
arc: W1_H02W0401 F4
|
|
arc: W1_H02W0501 F7
|
|
word: SLICED.K1.INIT 1100110000000000
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 1000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 0000000000000001
|
|
word: SLICEC.K1.INIT 0000000001010101
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
|
|
.tile R24C41:PLC2
|
|
arc: H00L0000 V02S0001
|
|
arc: S1_V02S0101 N1_V01S0100
|
|
arc: S1_V02S0301 E1_H02W0301
|
|
arc: S1_V02S0701 E1_H02W0701
|
|
arc: V00B0000 N1_V02S0201
|
|
arc: W1_H02W0001 V01N0001
|
|
arc: W1_H02W0201 N1_V01S0000
|
|
arc: W1_H02W0301 V01N0101
|
|
arc: W1_H02W0401 V06N0203
|
|
arc: W1_H02W0701 V01N0101
|
|
arc: A0 V02N0701
|
|
arc: B0 V01N0001
|
|
arc: C0 H02E0601
|
|
arc: CE0 H00L0000
|
|
arc: CE3 H02E0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 E1_H02W0201
|
|
arc: F0 F0_SLICE
|
|
arc: M6 V00B0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: V01S0100 Q6
|
|
arc: W3_H06W0003 Q0
|
|
word: SLICEA.K0.INIT 0011101000110010
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
|
|
.tile R24C42:PLC2
|
|
arc: E1_H02E0101 V06S0103
|
|
arc: E1_H02E0401 N1_V02S0401
|
|
arc: H00L0000 N1_V02S0001
|
|
arc: H00L0100 V02S0301
|
|
arc: H00R0100 N1_V02S0701
|
|
arc: N1_V02N0401 S1_V02N0101
|
|
arc: N1_V02N0501 N1_V01S0100
|
|
arc: N1_V02N0701 V01N0101
|
|
arc: S1_V02S0101 E1_H01W0100
|
|
arc: S1_V02S0501 N1_V02S0501
|
|
arc: V00B0000 V02S0001
|
|
arc: CE0 V02N0201
|
|
arc: CE1 H00L0100
|
|
arc: CE3 H00L0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: M0 V00B0000
|
|
arc: M1 H02W0001
|
|
arc: M2 H02W0601
|
|
arc: M3 H00L0000
|
|
arc: M7 H00R0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V02N0001 Q0
|
|
arc: N1_V02N0301 Q1
|
|
arc: S1_V02S0001 Q2
|
|
arc: S1_V02S0701 Q7
|
|
arc: W1_H02W0301 Q3
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R24C43:PLC2
|
|
arc: E1_H02E0201 V02N0201
|
|
arc: E1_H02E0301 V02S0301
|
|
arc: H00L0000 N1_V02S0001
|
|
arc: H00L0100 V02S0301
|
|
arc: H00R0000 H02E0401
|
|
arc: H00R0100 V02S0501
|
|
arc: N1_V02N0601 S1_V02N0601
|
|
arc: V00B0100 V02N0301
|
|
arc: V00T0000 N1_V02S0401
|
|
arc: V00T0100 N1_V02S0701
|
|
arc: W1_H02W0001 S3_V06N0003
|
|
arc: W1_H02W0201 W3_H06E0103
|
|
arc: W1_H02W0601 N1_V02S0601
|
|
arc: W3_H06W0203 E1_H01W0000
|
|
arc: CE0 V02N0201
|
|
arc: CE1 H00R0100
|
|
arc: CE2 H00L0100
|
|
arc: CE3 H02E0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0001 Q6
|
|
arc: H01W0100 Q0
|
|
arc: M0 V00T0000
|
|
arc: M2 V00T0100
|
|
arc: M3 H00R0000
|
|
arc: M5 H00L0000
|
|
arc: M6 V00B0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: W1_H02W0301 Q3
|
|
arc: W1_H02W0701 Q5
|
|
arc: W3_H06W0103 Q2
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R24C44:PLC2
|
|
arc: H00R0000 E1_H02W0601
|
|
arc: H00R0100 S1_V02N0501
|
|
arc: N1_V02N0201 N1_V01S0000
|
|
arc: N1_V02N0601 H01E0001
|
|
arc: CE0 H00R0000
|
|
arc: CE2 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0101 Q1
|
|
arc: H01W0000 Q0
|
|
arc: LSR1 H02E0301
|
|
arc: M0 H02W0601
|
|
arc: M1 H00R0100
|
|
arc: M5 E1_H02W0001
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR2 LSR1
|
|
arc: N1_V01N0001 Q5
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R24C45:PLC2
|
|
arc: E1_H02E0101 E1_H01W0100
|
|
arc: E1_H02E0301 V02S0301
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: H00R0000 H02W0601
|
|
arc: N1_V02N0301 H01E0101
|
|
arc: V00T0000 W1_H02E0201
|
|
arc: W1_H02W0601 E1_H02W0301
|
|
arc: CE0 H00R0000
|
|
arc: CE2 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: LSR0 V00T0000
|
|
arc: M0 E1_H02W0601
|
|
arc: M5 E1_H02W0001
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR2 LSR0
|
|
arc: W3_H06W0003 Q0
|
|
arc: W3_H06W0303 Q5
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R24C46:PLC2
|
|
arc: H00R0100 V02N0501
|
|
arc: H01W0100 W3_H06E0303
|
|
arc: W1_H02W0001 S1_V02N0001
|
|
arc: W1_H02W0601 W3_H06E0303
|
|
arc: CE0 H02E0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: LSR1 H02E0301
|
|
arc: M1 H00R0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: N1_V02N0301 Q1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R24C47:PLC2
|
|
arc: W1_H02W0001 N1_V01S0000
|
|
arc: W1_H02W0301 E3_H06W0003
|
|
arc: W1_H02W0601 S1_V02N0601
|
|
|
|
.tile R24C4:PLC2
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
|
|
.tile R24C51:PLC2
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
|
|
.tile R24C53:PLC2
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
|
|
.tile R24C57:PLC2
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
|
|
.tile R24C59:PLC2
|
|
arc: W3_H06W0303 E3_H06W0203
|
|
|
|
.tile R24C63:PLC2
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
|
|
.tile R24C65:PLC2
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
|
|
.tile R24C69:PLC2
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
|
|
.tile R24C6:PLC2
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
|
|
.tile R24C71:PLC2
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
|
|
.tile R24C75:PLC2
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
|
|
.tile R24C77:PLC2
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
|
|
.tile R24C7:PLC2
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
|
|
.tile R24C81:PLC2
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
|
|
.tile R24C83:PLC2
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
|
|
.tile R24C87:PLC2
|
|
arc: S3_V06S0303 W3_H06E0303
|
|
|
|
.tile R24C9:PLC2
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
|
|
.tile R25C13:PLC2
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
|
|
.tile R25C18:PLC2
|
|
arc: N1_V02N0401 N3_V06S0203
|
|
|
|
.tile R25C19:PLC2
|
|
arc: E1_H02E0601 W3_H06E0303
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
|
|
.tile R25C21:PLC2
|
|
arc: E3_H06E0303 W1_H02E0601
|
|
|
|
.tile R25C22:PLC2
|
|
arc: E3_H06E0003 N1_V01S0000
|
|
arc: E3_H06E0103 N1_V01S0100
|
|
arc: N1_V02N0601 S1_V02N0301
|
|
|
|
.tile R25C24:PLC2
|
|
arc: E1_H02E0301 V06S0003
|
|
|
|
.tile R25C25:PLC2
|
|
arc: E1_H01E0001 W3_H06E0003
|
|
arc: E1_H02E0501 N1_V02S0501
|
|
arc: N1_V02N0001 S3_V06N0003
|
|
arc: N1_V02N0201 S1_V02N0201
|
|
arc: N1_V02N0301 S1_V02N0201
|
|
arc: N1_V02N0701 W3_H06E0203
|
|
arc: V00B0000 V02S0001
|
|
arc: V00T0000 N1_V02S0401
|
|
arc: A2 V02S0501
|
|
arc: A3 V00B0000
|
|
arc: A4 H02W0701
|
|
arc: A5 N1_V02S0101
|
|
arc: A6 V02S0101
|
|
arc: A7 N1_V02S0301
|
|
arc: B0 H02E0301
|
|
arc: B2 S1_V02N0101
|
|
arc: B3 S1_V02N0301
|
|
arc: B4 N1_V02S0701
|
|
arc: B5 V02S0701
|
|
arc: B6 V00T0000
|
|
arc: B7 S1_V02N0701
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E3_H06E0003 Q3
|
|
arc: E3_H06E0103 Q2
|
|
arc: E3_H06E0203 Q4
|
|
arc: E3_H06E0303 Q5
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: V01S0000 Q6
|
|
arc: V01S0100 Q7
|
|
word: SLICED.K1.INIT 0110011001101100
|
|
word: SLICED.K0.INIT 0110011001101010
|
|
word: SLICEC.K1.INIT 0110011001101100
|
|
word: SLICEC.K0.INIT 0110011001101100
|
|
word: SLICEB.K1.INIT 0110011001101100
|
|
word: SLICEB.K0.INIT 0110011001101100
|
|
word: SLICEA.K1.INIT 1111111111111111
|
|
word: SLICEA.K0.INIT 0000000000001100
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 YES
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R25C26:PLC2
|
|
arc: E1_H02E0101 V06S0103
|
|
arc: E1_H02E0301 V06S0003
|
|
arc: E1_H02E0701 N1_V02S0701
|
|
arc: H00R0000 N1_V02S0401
|
|
arc: H00R0100 N1_V02S0501
|
|
arc: N1_V02N0201 H06W0103
|
|
arc: N1_V02N0601 H01E0001
|
|
arc: V00B0000 V02S0201
|
|
arc: V00B0100 N1_V02S0301
|
|
arc: V00T0000 N1_V02S0601
|
|
arc: W1_H02W0701 N1_V01S0100
|
|
arc: A0 H00R0000
|
|
arc: A1 H02E0501
|
|
arc: A2 S1_V02N0701
|
|
arc: A3 V02S0701
|
|
arc: A4 V00B0000
|
|
arc: A5 N1_V02S0101
|
|
arc: A6 V02S0301
|
|
arc: A7 V02N0301
|
|
arc: B0 E1_H02W0101
|
|
arc: B1 V00T0000
|
|
arc: B2 S1_V02N0301
|
|
arc: B3 H00R0100
|
|
arc: B4 E1_H02W0301
|
|
arc: B5 H02W0301
|
|
arc: B6 V00B0100
|
|
arc: B7 V02S0501
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0001 Q7
|
|
arc: E1_H01E0101 Q6
|
|
arc: E3_H06E0003 Q0
|
|
arc: E3_H06E0103 Q1
|
|
arc: E3_H06E0203 Q4
|
|
arc: E3_H06E0303 Q5
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: V01S0000 Q2
|
|
arc: V01S0100 Q3
|
|
word: SLICED.K1.INIT 0110011001101100
|
|
word: SLICED.K0.INIT 0110011001101010
|
|
word: SLICEC.K1.INIT 0110011001101100
|
|
word: SLICEC.K0.INIT 0110011001101100
|
|
word: SLICEB.K1.INIT 0110011001101010
|
|
word: SLICEB.K0.INIT 0110011001101010
|
|
word: SLICEA.K1.INIT 0110011001101010
|
|
word: SLICEA.K0.INIT 0110011001101100
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R25C27:PLC2
|
|
arc: E1_H02E0301 V02S0301
|
|
arc: E1_H02E0501 W3_H06E0303
|
|
arc: E3_H06E0003 H01E0001
|
|
arc: E3_H06E0103 H01E0101
|
|
arc: E3_H06E0303 N1_V01S0100
|
|
arc: N1_V01N0001 N3_V06S0003
|
|
arc: N1_V02N0201 H02W0201
|
|
arc: W1_H02W0301 N1_V02S0301
|
|
arc: A0 H02W0701
|
|
arc: A1 H02E0701
|
|
arc: A2 H02E0701
|
|
arc: B0 H02E0301
|
|
arc: B1 H02E0101
|
|
arc: B2 H02E0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0101 Q2
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: V01S0000 Q1
|
|
arc: V01S0100 Q0
|
|
word: SLICEC.K1.INIT 0000000000001110
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0110011001101010
|
|
word: SLICEA.K1.INIT 0110011001101010
|
|
word: SLICEA.K0.INIT 0110011001101010
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R25C28:PLC2
|
|
arc: E3_H06E0203 N1_V01S0000
|
|
arc: E3_H06E0303 H01E0101
|
|
arc: H00R0100 V02S0701
|
|
arc: N1_V01N0001 S3_V06N0003
|
|
arc: N1_V02N0001 E3_H06W0003
|
|
arc: N1_V02N0201 S3_V06N0103
|
|
arc: N1_V02N0301 S3_V06N0003
|
|
arc: N1_V02N0501 N3_V06S0303
|
|
arc: N3_V06N0003 S3_V06N0003
|
|
arc: V00B0000 V02N0201
|
|
arc: W1_H02W0101 W3_H06E0103
|
|
arc: W1_H02W0201 S3_V06N0103
|
|
arc: W1_H02W0301 W3_H06E0003
|
|
arc: W1_H02W0701 N1_V02S0701
|
|
arc: CE0 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E3_H06E0003 Q0
|
|
arc: LSR1 H02E0301
|
|
arc: M0 V00B0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R25C29:PLC2
|
|
arc: E1_H02E0001 W1_H02E0501
|
|
arc: N1_V02N0001 S3_V06N0003
|
|
arc: N1_V02N0401 S1_V02N0101
|
|
arc: W3_H06W0103 S3_V06N0103
|
|
|
|
.tile R25C30:PLC2
|
|
arc: E1_H02E0101 N1_V02S0101
|
|
arc: E1_H02E0501 V06S0303
|
|
|
|
.tile R25C31:PLC2
|
|
arc: E1_H02E0201 S3_V06N0103
|
|
arc: E1_H02E0701 N1_V02S0701
|
|
arc: E3_H06E0003 W1_H02E0001
|
|
arc: N1_V02N0701 S1_V02N0601
|
|
arc: S1_V02S0101 W3_H06E0103
|
|
arc: S1_V02S0301 W3_H06E0003
|
|
arc: S1_V02S0501 W3_H06E0303
|
|
arc: S1_V02S0701 W3_H06E0203
|
|
|
|
.tile R25C32:PLC2
|
|
arc: E1_H02E0101 V02S0101
|
|
arc: E1_H02E0301 S1_V02N0301
|
|
arc: E1_H02E0501 W3_H06E0303
|
|
arc: E1_H02E0601 N1_V01S0000
|
|
arc: H00L0000 N1_V02S0201
|
|
arc: H00R0000 V02S0401
|
|
arc: N1_V02N0201 H02E0201
|
|
arc: S1_V02S0301 W3_H06E0003
|
|
arc: S1_V02S0401 W3_H06E0203
|
|
arc: S1_V02S0501 W1_H02E0501
|
|
arc: S3_V06S0103 W3_H06E0103
|
|
arc: V00T0000 N1_V02S0401
|
|
arc: A0 W1_H02E0501
|
|
arc: A2 N1_V02S0501
|
|
arc: A3 S1_V02N0701
|
|
arc: A4 V00T0000
|
|
arc: A5 N1_V02S0301
|
|
arc: A6 H00R0000
|
|
arc: A7 V02S0301
|
|
arc: B2 H00L0000
|
|
arc: B3 H02W0301
|
|
arc: B4 V02S0701
|
|
arc: B5 N1_V02S0701
|
|
arc: B6 W1_H02E0101
|
|
arc: B7 S1_V02N0501
|
|
arc: CLK0 G_HPBX0000
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q2
|
|
arc: N1_V01N0101 Q3
|
|
arc: S1_V02S0601 Q4
|
|
arc: S1_V02S0701 Q7
|
|
arc: V01S0000 Q5
|
|
arc: V01S0100 Q6
|
|
word: SLICED.K1.INIT 0110011001101010
|
|
word: SLICED.K0.INIT 0110011001101100
|
|
word: SLICEC.K1.INIT 0110011001101010
|
|
word: SLICEC.K0.INIT 0110011001101100
|
|
word: SLICEB.K1.INIT 0110011001101100
|
|
word: SLICEB.K0.INIT 0110011001101010
|
|
word: SLICEA.K1.INIT 1111111111111111
|
|
word: SLICEA.K0.INIT 0000000000001010
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 YES
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R25C33:PLC2
|
|
arc: E1_H02E0101 S1_V02N0101
|
|
arc: H00R0000 N1_V02S0601
|
|
arc: H01W0100 W3_H06E0303
|
|
arc: N1_V02N0101 E3_H06W0103
|
|
arc: N1_V02N0401 E3_H06W0203
|
|
arc: S1_V02S0101 W3_H06E0103
|
|
arc: S1_V02S0301 W3_H06E0003
|
|
arc: S1_V02S0501 H02E0501
|
|
arc: V00B0000 N1_V02S0201
|
|
arc: V00T0000 V02S0601
|
|
arc: W1_H02W0301 N1_V02S0301
|
|
arc: A0 S1_V02N0501
|
|
arc: A1 N1_V02S0501
|
|
arc: A2 H02W0701
|
|
arc: A3 V00B0000
|
|
arc: A4 V00T0000
|
|
arc: A5 V02S0101
|
|
arc: A6 W1_H02E0701
|
|
arc: A7 H00R0000
|
|
arc: B0 H02E0301
|
|
arc: B1 H01W0100
|
|
arc: B2 N1_V02S0101
|
|
arc: B3 V02S0301
|
|
arc: B4 N1_V02S0701
|
|
arc: B5 H02E0101
|
|
arc: B6 V02S0501
|
|
arc: B7 H02W0301
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0101 Q2
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q3
|
|
arc: N1_V01N0101 Q1
|
|
arc: S1_V02S0001 Q0
|
|
arc: S1_V02S0401 Q4
|
|
arc: S1_V02S0701 Q7
|
|
arc: V01S0000 Q6
|
|
arc: V01S0100 Q5
|
|
word: SLICED.K1.INIT 0110011001101100
|
|
word: SLICED.K0.INIT 0110011001101100
|
|
word: SLICEC.K1.INIT 0110011001101010
|
|
word: SLICEC.K0.INIT 0110011001101100
|
|
word: SLICEB.K1.INIT 0110011001101100
|
|
word: SLICEB.K0.INIT 0110011001101010
|
|
word: SLICEA.K1.INIT 0110011001101100
|
|
word: SLICEA.K0.INIT 0110011001101010
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R25C34:PLC2
|
|
arc: E1_H02E0101 E3_H06W0103
|
|
arc: E1_H02E0201 S1_V02N0201
|
|
arc: E1_H02E0301 W3_H06E0003
|
|
arc: E1_H02E0701 W3_H06E0203
|
|
arc: H00R0000 W1_H02E0601
|
|
arc: N1_V02N0001 H06E0003
|
|
arc: N1_V02N0201 S1_V02N0201
|
|
arc: N1_V02N0601 S1_V02N0301
|
|
arc: S1_V02S0301 H01E0101
|
|
arc: S1_V02S0501 W3_H06E0303
|
|
arc: W1_H02W0301 N1_V02S0301
|
|
arc: W1_H02W0701 N1_V02S0701
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
arc: A0 H00R0000
|
|
arc: A1 V02S0501
|
|
arc: A2 V02S0501
|
|
arc: B0 V02S0101
|
|
arc: B1 H02E0101
|
|
arc: B2 H02E0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: S1_V02S0001 Q0
|
|
arc: S1_V02S0101 Q1
|
|
arc: S1_V02S0201 Q2
|
|
word: SLICEC.K1.INIT 0000000000001110
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0110011001101100
|
|
word: SLICEA.K1.INIT 0110011001101100
|
|
word: SLICEA.K0.INIT 0110011001101100
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R25C35:PLC2
|
|
arc: E1_H02E0401 V06S0203
|
|
arc: H00L0000 H02E0201
|
|
arc: N1_V02N0401 N3_V06S0203
|
|
arc: N1_V02N0601 S3_V06N0303
|
|
arc: S1_V02S0101 E1_H01W0100
|
|
arc: S1_V02S0501 H02W0501
|
|
arc: S1_V02S0601 N1_V02S0601
|
|
arc: S1_V02S0701 N1_V02S0701
|
|
arc: CE2 H00L0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: M5 H02W0001
|
|
arc: MUXCLK2 CLK0
|
|
arc: V01S0100 Q5
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R25C36:PLC2
|
|
arc: E1_H02E0301 W1_H02E0301
|
|
arc: E1_H02E0501 V06S0303
|
|
arc: E1_H02E0701 W1_H02E0701
|
|
arc: H00R0000 H02E0401
|
|
arc: H00R0100 V02N0501
|
|
arc: N1_V02N0001 H02W0001
|
|
arc: S1_V02S0101 N1_V02S0101
|
|
arc: S1_V02S0301 N1_V02S0201
|
|
arc: S1_V02S0501 N1_V02S0501
|
|
arc: S1_V02S0701 E1_H01W0100
|
|
arc: W1_H02W0001 V06S0003
|
|
arc: W1_H02W0501 V06S0303
|
|
arc: A0 H02W0501
|
|
arc: B0 W1_H02E0101
|
|
arc: C0 V02S0401
|
|
arc: CE0 H00R0100
|
|
arc: CE1 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02N0201
|
|
arc: F0 F0_SLICE
|
|
arc: H01W0100 Q3
|
|
arc: M3 H00R0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: S3_V06S0003 Q0
|
|
word: SLICEA.K0.INIT 0011001110100010
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R25C37:PLC2
|
|
arc: E1_H02E0201 S1_V02N0201
|
|
arc: E1_H02E0501 N1_V02S0501
|
|
arc: H00L0000 S1_V02N0201
|
|
arc: H00R0000 V02S0401
|
|
arc: N1_V02N0201 V01N0001
|
|
arc: N1_V02N0501 H06W0303
|
|
arc: N1_V02N0601 H06W0303
|
|
arc: S1_V02S0101 H06W0103
|
|
arc: S1_V02S0601 H06W0303
|
|
arc: S3_V06S0103 H06W0103
|
|
arc: S3_V06S0203 E1_H01W0000
|
|
arc: V00B0000 V02N0201
|
|
arc: V00T0000 S1_V02N0401
|
|
arc: V00T0100 V02N0501
|
|
arc: W1_H02W0001 S3_V06N0003
|
|
arc: A0 H02E0501
|
|
arc: A2 H02E0701
|
|
arc: A3 S1_V02N0701
|
|
arc: A4 V00T0100
|
|
arc: A5 V00T0000
|
|
arc: A6 V02S0101
|
|
arc: A7 V02S0301
|
|
arc: B2 V02N0301
|
|
arc: B3 H00R0000
|
|
arc: B4 V02S0701
|
|
arc: B5 H02E0301
|
|
arc: B6 V02N0701
|
|
arc: B7 V00B0000
|
|
arc: CE1 S1_V02N0201
|
|
arc: CE2 H00L0000
|
|
arc: CE3 N1_V02S0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E3_H06E0203 Q7
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0100 Q4
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0101 Q2
|
|
arc: N1_V02N0401 Q6
|
|
arc: V01S0100 Q3
|
|
arc: W1_H02W0501 Q5
|
|
word: SLICED.K1.INIT 0110011001101010
|
|
word: SLICED.K0.INIT 0110011001101010
|
|
word: SLICEC.K1.INIT 0110011001101100
|
|
word: SLICEC.K0.INIT 0110011001101100
|
|
word: SLICEB.K1.INIT 0110011001101100
|
|
word: SLICEB.K0.INIT 0110011001101010
|
|
word: SLICEA.K1.INIT 1111111111111111
|
|
word: SLICEA.K0.INIT 0000000000001010
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 YES
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R25C38:PLC2
|
|
arc: E1_H02E0001 W1_H02E0501
|
|
arc: H00L0000 H02E0201
|
|
arc: H00R0000 S1_V02N0401
|
|
arc: H00R0100 H02E0501
|
|
arc: N1_V02N0101 E1_H02W0101
|
|
arc: N1_V02N0201 E1_H02W0201
|
|
arc: N1_V02N0401 E1_H01W0000
|
|
arc: S1_V02S0201 H02E0201
|
|
arc: S1_V02S0701 E1_H01W0100
|
|
arc: V00B0000 V02N0201
|
|
arc: V00T0100 V02N0701
|
|
arc: A0 S1_V02N0701
|
|
arc: A1 V02S0501
|
|
arc: A2 V02S0501
|
|
arc: A3 V02S0501
|
|
arc: A4 V00T0100
|
|
arc: A5 V00B0000
|
|
arc: A6 S1_V02N0101
|
|
arc: A7 S1_V02N0301
|
|
arc: B0 V02S0101
|
|
arc: B1 V02N0101
|
|
arc: B2 V02N0301
|
|
arc: B3 H00R0000
|
|
arc: B4 V02S0501
|
|
arc: B5 V02S0501
|
|
arc: B6 V02S0501
|
|
arc: B7 V02S0501
|
|
arc: CE0 H00L0000
|
|
arc: CE1 H00L0000
|
|
arc: CE2 V02N0601
|
|
arc: CE3 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H02E0501 Q7
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 Q0
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q6
|
|
arc: N1_V01N0101 Q3
|
|
arc: N1_V02N0001 Q2
|
|
arc: N1_V02N0301 Q1
|
|
arc: N1_V02N0501 Q5
|
|
arc: N1_V02N0601 Q6
|
|
arc: S1_V02S0501 Q7
|
|
arc: V01S0000 Q4
|
|
arc: V01S0100 Q5
|
|
word: SLICED.K1.INIT 0110011001101100
|
|
word: SLICED.K0.INIT 0110011001101100
|
|
word: SLICEC.K1.INIT 0110011001101100
|
|
word: SLICEC.K0.INIT 0110011001101100
|
|
word: SLICEB.K1.INIT 0110011001101010
|
|
word: SLICEB.K0.INIT 0110011001101010
|
|
word: SLICEA.K1.INIT 0110011001101010
|
|
word: SLICEA.K0.INIT 0110011001101100
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R25C39:PLC2
|
|
arc: E1_H02E0501 V02S0501
|
|
arc: H00L0000 S1_V02N0201
|
|
arc: H00L0100 N1_V02S0101
|
|
arc: H00R0000 V02N0401
|
|
arc: H00R0100 V02S0701
|
|
arc: N1_V02N0501 E1_H01W0100
|
|
arc: N1_V02N0601 E1_H01W0000
|
|
arc: N1_V02N0701 E1_H01W0100
|
|
arc: V00T0000 V02N0601
|
|
arc: V00T0100 V02N0501
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
arc: A0 V02S0501
|
|
arc: A1 V02S0501
|
|
arc: A2 V02S0501
|
|
arc: A3 V02S0501
|
|
arc: A4 V00T0000
|
|
arc: A5 V00T0100
|
|
arc: A6 H00R0000
|
|
arc: A7 H02W0701
|
|
arc: B0 V02N0301
|
|
arc: B1 S1_V02N0101
|
|
arc: B2 S1_V02N0301
|
|
arc: B3 H00L0000
|
|
arc: B4 V02S0501
|
|
arc: B5 V02S0501
|
|
arc: B6 V02S0501
|
|
arc: B7 V02S0501
|
|
arc: CE0 H00R0100
|
|
arc: CE1 H00L0100
|
|
arc: CE2 H00L0100
|
|
arc: CE3 H00L0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0001 Q2
|
|
arc: E1_H01E0101 Q7
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 Q5
|
|
arc: H01W0100 Q4
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q3
|
|
arc: N1_V01N0101 Q5
|
|
arc: N1_V02N0001 Q2
|
|
arc: N1_V02N0101 Q3
|
|
arc: N1_V02N0201 Q0
|
|
arc: N1_V02N0301 Q1
|
|
arc: N1_V02N0401 Q4
|
|
arc: S1_V02S0201 Q0
|
|
arc: S1_V02S0301 Q1
|
|
arc: V01S0000 Q7
|
|
arc: V01S0100 Q6
|
|
word: SLICED.K1.INIT 0110011001101100
|
|
word: SLICED.K0.INIT 0110011001101100
|
|
word: SLICEC.K1.INIT 0110011001101100
|
|
word: SLICEC.K0.INIT 0110011001101100
|
|
word: SLICEB.K1.INIT 0110011001101010
|
|
word: SLICEB.K0.INIT 0110011001101010
|
|
word: SLICEA.K1.INIT 0110011001101010
|
|
word: SLICEA.K0.INIT 0110011001101010
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R25C40:PLC2
|
|
arc: H00L0000 V02N0001
|
|
arc: H00L0100 N1_V02S0101
|
|
arc: H00R0000 V02N0401
|
|
arc: H00R0100 S1_V02N0701
|
|
arc: N1_V02N0001 S3_V06N0003
|
|
arc: N1_V02N0101 H01E0101
|
|
arc: N1_V02N0501 W1_H02E0501
|
|
arc: N1_V02N0601 H01E0001
|
|
arc: S1_V02S0001 W1_H02E0001
|
|
arc: S1_V02S0501 E1_H02W0501
|
|
arc: S1_V02S0701 V01N0101
|
|
arc: V00B0000 S1_V02N0001
|
|
arc: W1_H02W0701 V02N0701
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
arc: W3_H06W0103 E1_H01W0100
|
|
arc: W3_H06W0303 E1_H01W0100
|
|
arc: A0 H02E0501
|
|
arc: A1 H02E0501
|
|
arc: A2 H02E0501
|
|
arc: A3 H02E0501
|
|
arc: A4 H02E0501
|
|
arc: A5 H02E0501
|
|
arc: A6 H02E0501
|
|
arc: A7 H02E0501
|
|
arc: B0 V02N0301
|
|
arc: B1 V02N0101
|
|
arc: B2 H00L0000
|
|
arc: B3 H00R0100
|
|
arc: B4 H00R0000
|
|
arc: B5 V02N0501
|
|
arc: B6 V00B0000
|
|
arc: B7 V02S0701
|
|
arc: CE0 H00L0100
|
|
arc: CE1 H00L0100
|
|
arc: CE2 N1_V02S0601
|
|
arc: CE3 H00L0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 Q1
|
|
arc: H01W0100 Q7
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q0
|
|
arc: N1_V01N0101 Q4
|
|
arc: N1_V02N0201 Q2
|
|
arc: N1_V02N0301 Q3
|
|
arc: N1_V02N0401 Q6
|
|
arc: N1_V02N0701 Q5
|
|
arc: W1_H02W0101 Q1
|
|
arc: W1_H02W0201 Q0
|
|
word: SLICEB.K0.INIT 0110011001101010
|
|
word: SLICEA.K1.INIT 0110011001101010
|
|
word: SLICEA.K0.INIT 0110011001101010
|
|
word: SLICEC.K0.INIT 0110011001101010
|
|
word: SLICEC.K1.INIT 0110011001101010
|
|
word: SLICED.K0.INIT 0110011001101010
|
|
word: SLICED.K1.INIT 0110011001101010
|
|
word: SLICEB.K1.INIT 0110011001101010
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
|
|
.tile R25C41:PLC2
|
|
arc: N1_V02N0001 S3_V06N0003
|
|
arc: N1_V02N0201 S3_V06N0103
|
|
arc: N1_V02N0601 E3_H06W0303
|
|
arc: N1_V02N0701 E1_H02W0701
|
|
arc: S1_V02S0101 N1_V02S0101
|
|
arc: S1_V02S0301 N1_V01S0100
|
|
arc: S1_V02S0501 V01N0101
|
|
arc: S1_V02S0601 N1_V02S0601
|
|
arc: S1_V02S0701 N1_V02S0701
|
|
arc: A0 W1_H02E0501
|
|
arc: A1 W1_H02E0501
|
|
arc: B0 V02N0301
|
|
arc: B1 V02N0101
|
|
arc: CE0 V02N0201
|
|
arc: CLK0 G_HPBX0000
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: H01W0100 Q1
|
|
arc: MUXCLK0 CLK0
|
|
arc: N1_V01N0001 Q1
|
|
arc: N1_V01N0101 Q0
|
|
word: SLICEA.K0.INIT 0110011001101010
|
|
word: SLICEA.K1.INIT 0110011001101010
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000001110
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
|
|
.tile R25C42:PLC2
|
|
arc: E1_H02E0001 V06S0003
|
|
arc: E1_H02E0101 S1_V02N0101
|
|
arc: E1_H02E0201 V06N0103
|
|
arc: H00R0100 V02S0501
|
|
arc: N1_V02N0201 S1_V02N0201
|
|
arc: S1_V02S0501 V01N0101
|
|
arc: CE1 S1_V02N0201
|
|
arc: CE3 V02N0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: M2 H02W0601
|
|
arc: M7 H00R0100
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0101 Q2
|
|
arc: W1_H02W0501 Q7
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R25C43:PLC2
|
|
arc: H00R0100 S1_V02N0501
|
|
arc: N1_V02N0201 S1_V02N0701
|
|
arc: N1_V02N0301 S3_V06N0003
|
|
arc: W1_H02W0601 E1_H02W0301
|
|
arc: W1_H02W0701 W3_H06E0203
|
|
arc: CE0 H02E0101
|
|
arc: CE2 S1_V02N0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0101 Q1
|
|
arc: M1 H00R0100
|
|
arc: M5 H02E0001
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: V01S0100 Q5
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R25C44:PLC2
|
|
arc: N1_V02N0101 H01E0101
|
|
arc: N1_V02N0201 W1_H02E0201
|
|
|
|
.tile R25C45:PLC2
|
|
arc: W1_H02W0301 S3_V06N0003
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
|
|
.tile R25C46:PLC2
|
|
arc: N1_V02N0501 S3_V06N0303
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
|
|
.tile R25C47:PLC2
|
|
arc: W3_H06W0303 E3_H06W0203
|
|
|
|
.tile R25C51:PLC2
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
|
|
.tile R25C52:PLC2
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
|
|
.tile R25C53:PLC2
|
|
arc: W3_H06W0203 E3_H06W0203
|
|
|
|
.tile R25C57:PLC2
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
|
|
.tile R25C58:PLC2
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
|
|
.tile R25C59:PLC2
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
|
|
.tile R25C63:PLC2
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
|
|
.tile R25C64:PLC2
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
|
|
.tile R25C65:PLC2
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
|
|
.tile R25C69:PLC2
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
arc: W3_H06W0303 E3_H06W0203
|
|
|
|
.tile R25C70:PLC2
|
|
arc: W3_H06W0303 E3_H06W0203
|
|
|
|
.tile R25C71:PLC2
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
|
|
.tile R25C75:PLC2
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
arc: W3_H06W0203 E3_H06W0203
|
|
|
|
.tile R25C76:PLC2
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
|
|
.tile R25C77:PLC2
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
|
|
.tile R25C7:PLC2
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
|
|
.tile R25C81:PLC2
|
|
arc: W3_H06W0203 E3_H06W0203
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
|
|
.tile R25C82:PLC2
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
|
|
.tile R25C83:PLC2
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
|
|
.tile R25C87:PLC2
|
|
arc: W3_H06W0203 E1_H02W0701
|
|
arc: W3_H06W0303 E1_H02W0501
|
|
|
|
.tile R25C88:PLC2
|
|
arc: W3_H06W0003 E1_H01W0000
|
|
|
|
.tile R26C13:PLC2
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
|
|
.tile R26C18:PLC2
|
|
arc: N1_V02N0001 S1_V02N0501
|
|
|
|
.tile R26C19:PLC2
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
|
|
.tile R26C22:PLC2
|
|
arc: N1_V02N0101 S3_V06N0103
|
|
|
|
.tile R26C25:PLC2
|
|
arc: E1_H02E0001 V06N0003
|
|
arc: E1_H02E0401 V06N0203
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: E3_H06E0203 N1_V01S0000
|
|
arc: E3_H06E0303 N1_V01S0100
|
|
arc: N1_V02N0001 S3_V06N0003
|
|
arc: N1_V02N0201 H06W0103
|
|
arc: N1_V02N0401 W3_H06E0203
|
|
|
|
.tile R26C26:PLC2
|
|
arc: E3_H06E0103 N1_V01S0100
|
|
arc: E3_H06E0203 N1_V01S0000
|
|
arc: H00L0000 H02E0001
|
|
arc: H00R0100 E1_H02W0701
|
|
arc: N1_V02N0101 H06W0103
|
|
arc: N1_V02N0301 V01N0101
|
|
arc: N1_V02N0401 H02E0401
|
|
arc: V00B0000 H02E0401
|
|
arc: CE1 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: LSR1 V00B0000
|
|
arc: M3 H00L0000
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXLSR1 LSR1
|
|
arc: V01S0000 Q3
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R26C27:PLC2
|
|
arc: E3_H06E0003 N1_V01S0000
|
|
arc: E3_H06E0303 N1_V01S0100
|
|
arc: N3_V06N0003 S3_V06N0003
|
|
|
|
.tile R26C28:PLC2
|
|
arc: N1_V02N0001 S1_V02N0501
|
|
arc: N1_V02N0201 S1_V02N0701
|
|
arc: W1_H02W0701 N1_V02S0701
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
|
|
.tile R26C29:PLC2
|
|
arc: N1_V02N0601 S3_V06N0303
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
|
|
.tile R26C31:PLC2
|
|
arc: E1_H01E0101 W3_H06E0203
|
|
arc: E1_H02E0101 V02S0101
|
|
arc: E1_H02E0301 V02S0301
|
|
arc: E1_H02E0501 V02S0501
|
|
arc: E1_H02E0601 W3_H06E0303
|
|
arc: E1_H02E0701 V02S0701
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
|
|
.tile R26C32:PLC2
|
|
arc: E1_H02E0101 W3_H06E0103
|
|
arc: E1_H02E0301 V02S0301
|
|
arc: E1_H02E0401 V02S0401
|
|
arc: E1_H02E0701 W3_H06E0203
|
|
arc: H00R0000 V02S0601
|
|
arc: V00B0000 H02E0601
|
|
arc: V00T0000 N1_V02S0601
|
|
arc: V00T0100 V02S0701
|
|
arc: A0 V02S0501
|
|
arc: A2 V00T0000
|
|
arc: A3 N1_V02S0501
|
|
arc: A4 H02E0701
|
|
arc: A5 H02E0501
|
|
arc: A6 N1_V01S0100
|
|
arc: A7 V00T0100
|
|
arc: B2 H02E0101
|
|
arc: B3 H02E0301
|
|
arc: B4 H00R0000
|
|
arc: B5 N1_V01S0000
|
|
arc: B6 H01E0101
|
|
arc: B7 V00B0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0101 Q6
|
|
arc: E1_H02E0501 Q7
|
|
arc: E3_H06E0203 Q4
|
|
arc: E3_H06E0303 Q5
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: V01S0000 Q3
|
|
arc: V01S0100 Q2
|
|
word: SLICED.K1.INIT 0110011001101100
|
|
word: SLICED.K0.INIT 0110011001101100
|
|
word: SLICEC.K1.INIT 0110011001101010
|
|
word: SLICEC.K0.INIT 0110011001101010
|
|
word: SLICEB.K1.INIT 0110011001101100
|
|
word: SLICEB.K0.INIT 0110011001101100
|
|
word: SLICEA.K1.INIT 1111111111111111
|
|
word: SLICEA.K0.INIT 0000000000001010
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 YES
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R26C33:PLC2
|
|
arc: E1_H02E0301 W3_H06E0003
|
|
arc: E1_H02E0501 W3_H06E0303
|
|
arc: E3_H06E0103 H01E0101
|
|
arc: H00L0000 V02S0001
|
|
arc: H00R0000 V02S0401
|
|
arc: V00B0000 H02E0401
|
|
arc: V00T0000 N1_V02S0401
|
|
arc: A0 H00L0000
|
|
arc: A1 N1_V02S0701
|
|
arc: A2 H02E0701
|
|
arc: A3 V00T0000
|
|
arc: A4 V00B0000
|
|
arc: A5 N1_V01S0100
|
|
arc: A6 V02S0101
|
|
arc: A7 V02S0301
|
|
arc: B0 H02E0301
|
|
arc: B1 S1_V02N0101
|
|
arc: B2 H02W0301
|
|
arc: B3 H02E0101
|
|
arc: B4 H00R0000
|
|
arc: B5 V02S0501
|
|
arc: B6 N1_V01S0000
|
|
arc: B7 V02S0701
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0101 Q7
|
|
arc: E1_H02E0201 Q2
|
|
arc: E1_H02E0401 Q6
|
|
arc: E3_H06E0003 Q3
|
|
arc: E3_H06E0203 Q4
|
|
arc: E3_H06E0303 Q5
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: V01S0000 Q0
|
|
arc: V01S0100 Q1
|
|
word: SLICED.K1.INIT 0110011001101010
|
|
word: SLICED.K0.INIT 0110011001101010
|
|
word: SLICEC.K1.INIT 0110011001101100
|
|
word: SLICEC.K0.INIT 0110011001101010
|
|
word: SLICEB.K1.INIT 0110011001101100
|
|
word: SLICEB.K0.INIT 0110011001101010
|
|
word: SLICEA.K1.INIT 0110011001101100
|
|
word: SLICEA.K0.INIT 0110011001101100
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R26C34:PLC2
|
|
arc: E1_H02E0101 V06S0103
|
|
arc: E1_H02E0301 V06S0003
|
|
arc: E1_H02E0501 V06S0303
|
|
arc: E1_H02E0701 V06S0203
|
|
arc: E3_H06E0103 H01E0101
|
|
arc: E3_H06E0303 W1_H02E0501
|
|
arc: H00L0000 V02S0201
|
|
arc: H00L0100 V02S0101
|
|
arc: N1_V02N0001 S1_V02N0001
|
|
arc: V00B0000 V02S0001
|
|
arc: W1_H02W0301 V02S0301
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
arc: A0 H02E0501
|
|
arc: A1 H00L0100
|
|
arc: A2 V02S0501
|
|
arc: A3 V02S0501
|
|
arc: B0 V00B0000
|
|
arc: B1 H02E0301
|
|
arc: B2 H00L0000
|
|
arc: B3 H00L0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H02E0001 Q2
|
|
arc: E3_H06E0003 Q3
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: V01S0000 Q0
|
|
arc: V01S0100 Q1
|
|
word: SLICEC.K1.INIT 0000000000001110
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0110011001101010
|
|
word: SLICEB.K0.INIT 0110011001101010
|
|
word: SLICEA.K1.INIT 0110011001101100
|
|
word: SLICEA.K0.INIT 0110011001101010
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R26C35:PLC2
|
|
arc: E1_H02E0101 N1_V02S0101
|
|
arc: E1_H02E0301 N3_V06S0003
|
|
arc: E1_H02E0501 N3_V06S0303
|
|
arc: E1_H02E0601 N1_V02S0601
|
|
arc: E1_H02E0701 V06S0203
|
|
arc: E3_H06E0103 W1_H02E0201
|
|
arc: E3_H06E0203 W1_H02E0401
|
|
arc: H00L0000 N1_V02S0001
|
|
arc: H00R0000 V02S0601
|
|
arc: H00R0100 V02S0701
|
|
arc: N1_V02N0201 H02W0201
|
|
arc: N3_V06N0003 S3_V06N0303
|
|
arc: N3_V06N0103 S3_V06N0003
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
arc: A0 V02S0501
|
|
arc: A2 H02W0701
|
|
arc: A3 H02E0501
|
|
arc: A4 N1_V02S0301
|
|
arc: A5 V02S0101
|
|
arc: A6 N1_V01S0100
|
|
arc: A7 H00R0000
|
|
arc: B2 H00R0100
|
|
arc: B3 H00L0000
|
|
arc: B4 H02E0301
|
|
arc: B5 H02E0101
|
|
arc: B6 V02N0701
|
|
arc: B7 V02N0501
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0001 Q6
|
|
arc: E1_H01E0101 Q7
|
|
arc: E1_H02E0401 Q4
|
|
arc: E3_H06E0303 Q5
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: V01S0000 Q3
|
|
arc: V01S0100 Q2
|
|
word: SLICED.K1.INIT 0110011001101100
|
|
word: SLICED.K0.INIT 0110011001101100
|
|
word: SLICEC.K1.INIT 0110011001101010
|
|
word: SLICEC.K0.INIT 0110011001101010
|
|
word: SLICEB.K1.INIT 0110011001101010
|
|
word: SLICEB.K0.INIT 0110011001101010
|
|
word: SLICEA.K1.INIT 1111111111111111
|
|
word: SLICEA.K0.INIT 0000000000001010
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 YES
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R26C36:PLC2
|
|
arc: E1_H02E0301 V06S0003
|
|
arc: E3_H06E0003 W1_H02E0001
|
|
arc: E3_H06E0103 H01E0101
|
|
arc: E3_H06E0203 H01E0001
|
|
arc: H00L0000 N1_V02S0201
|
|
arc: N1_V02N0201 E1_H01W0000
|
|
arc: N1_V02N0501 H02W0501
|
|
arc: S1_V02S0101 H06E0103
|
|
arc: S1_V02S0201 E1_H01W0000
|
|
arc: V00B0000 V02N0001
|
|
arc: V00T0100 N1_V02S0501
|
|
arc: W1_H02W0201 S1_V02N0201
|
|
arc: W1_H02W0701 N3_V06S0203
|
|
arc: A0 V02N0501
|
|
arc: A1 W1_H02E0701
|
|
arc: A2 V02S0501
|
|
arc: A3 H02E0701
|
|
arc: A4 H02W0701
|
|
arc: A5 V00T0100
|
|
arc: A6 V02S0301
|
|
arc: A7 H02E0501
|
|
arc: B0 V02S0101
|
|
arc: B1 N1_V02S0301
|
|
arc: B2 N1_V02S0101
|
|
arc: B3 H00L0000
|
|
arc: B4 V02N0701
|
|
arc: B5 H02W0101
|
|
arc: B6 H02E0301
|
|
arc: B7 V00B0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0001 Q4
|
|
arc: E1_H02E0201 Q2
|
|
arc: E1_H02E0401 Q6
|
|
arc: E1_H02E0501 Q7
|
|
arc: E3_H06E0303 Q5
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: S1_V02S0301 Q3
|
|
arc: V01S0000 Q0
|
|
arc: V01S0100 Q1
|
|
word: SLICED.K1.INIT 0110011001101100
|
|
word: SLICED.K0.INIT 0110011001101010
|
|
word: SLICEC.K1.INIT 0110011001101100
|
|
word: SLICEC.K0.INIT 0110011001101010
|
|
word: SLICEB.K1.INIT 0110011001101100
|
|
word: SLICEB.K0.INIT 0110011001101010
|
|
word: SLICEA.K1.INIT 0110011001101100
|
|
word: SLICEA.K0.INIT 0110011001101100
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R26C37:PLC2
|
|
arc: E1_H02E0101 V02S0101
|
|
arc: E1_H02E0601 V06N0303
|
|
arc: E1_H02E0701 N1_V01S0100
|
|
arc: E3_H06E0003 H01E0001
|
|
arc: E3_H06E0203 W1_H02E0401
|
|
arc: H00L0100 W1_H02E0101
|
|
arc: H00R0000 W1_H02E0601
|
|
arc: N1_V02N0001 W3_H06E0003
|
|
arc: N1_V02N0201 S1_V02N0701
|
|
arc: N1_V02N0301 S1_V02N0201
|
|
arc: N1_V02N0401 S3_V06N0203
|
|
arc: N1_V02N0501 S1_V02N0401
|
|
arc: N1_V02N0701 S1_V02N0601
|
|
arc: S1_V02S0101 H06E0103
|
|
arc: S1_V02S0501 E1_H01W0100
|
|
arc: S1_V02S0601 H06E0303
|
|
arc: S1_V02S0701 H02W0701
|
|
arc: V00B0000 W1_H02E0601
|
|
arc: V00T0000 E1_H02W0201
|
|
arc: W1_H02W0101 V02N0101
|
|
arc: W1_H02W0501 V06N0303
|
|
arc: W1_H02W0701 V06S0203
|
|
arc: A0 H00L0100
|
|
arc: A1 V02N0501
|
|
arc: A2 V02N0501
|
|
arc: A6 H02W0501
|
|
arc: B0 H02E0301
|
|
arc: B1 V00B0000
|
|
arc: B2 H00R0000
|
|
arc: B6 H02W0101
|
|
arc: C6 N1_V02S0201
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D6 N1_V02S0601
|
|
arc: E1_H01E0101 F6
|
|
arc: E3_H06E0103 Q2
|
|
arc: E3_H06E0303 F6
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F6 F5D_SLICE
|
|
arc: H01W0000 F6
|
|
arc: M6 V00T0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: N1_V01N0001 F6
|
|
arc: S1_V02S0401 F6
|
|
arc: V01S0000 Q1
|
|
arc: V01S0100 Q0
|
|
word: SLICEC.K1.INIT 0000000000001110
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0110011001101010
|
|
word: SLICEA.K1.INIT 0110011001101010
|
|
word: SLICEA.K0.INIT 0110011001101100
|
|
word: SLICED.K0.INIT 0111111111111111
|
|
word: SLICED.K1.INIT 0000000000000000
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
|
|
.tile R26C38:PLC2
|
|
arc: E1_H02E0001 N1_V01S0000
|
|
arc: E1_H02E0101 N1_V01S0100
|
|
arc: E1_H02E0501 W1_H02E0501
|
|
arc: E3_H06E0103 W1_H02E0201
|
|
arc: E3_H06E0203 W1_H02E0401
|
|
arc: H00R0100 V02S0501
|
|
arc: H01W0100 W3_H06E0303
|
|
arc: N1_V02N0001 N1_V01S0000
|
|
arc: N1_V02N0101 S1_V02N0101
|
|
arc: N1_V02N0201 S1_V02N0701
|
|
arc: N1_V02N0301 S1_V02N0201
|
|
arc: N1_V02N0601 H02E0601
|
|
arc: N1_V02N0701 S1_V02N0601
|
|
arc: S1_V02S0101 H06E0103
|
|
arc: S1_V02S0301 H02W0301
|
|
arc: S1_V02S0401 H06E0203
|
|
arc: S1_V02S0501 E1_H01W0100
|
|
arc: S1_V02S0701 H02W0701
|
|
arc: W1_H02W0501 E1_H02W0501
|
|
arc: W1_H02W0701 W3_H06E0203
|
|
arc: A0 H02E0701
|
|
arc: A1 V02S0701
|
|
arc: B0 H02E0101
|
|
arc: B1 H00R0100
|
|
arc: C0 N1_V02S0601
|
|
arc: C1 N1_V02S0401
|
|
arc: CE0 V02S0201
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H01E0101
|
|
arc: D1 N1_V02S0001
|
|
arc: E1_H01E0001 Q0
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: MUXCLK0 CLK0
|
|
arc: W1_H02W0101 F1
|
|
word: SLICEA.K0.INIT 0011001110100010
|
|
word: SLICEA.K1.INIT 0001000000000000
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R26C39:PLC2
|
|
arc: H01W0100 W3_H06E0303
|
|
arc: N1_V02N0001 N1_V01S0000
|
|
arc: N1_V02N0101 N1_V01S0100
|
|
arc: N1_V02N0201 H01E0001
|
|
arc: N1_V02N0301 S1_V02N0201
|
|
arc: N1_V02N0401 S1_V02N0401
|
|
arc: N1_V02N0501 S1_V02N0501
|
|
arc: N1_V02N0601 S1_V02N0601
|
|
arc: N1_V02N0701 N1_V01S0100
|
|
arc: S1_V02S0101 H06E0103
|
|
arc: S1_V02S0301 H06E0003
|
|
arc: S1_V02S0501 H06E0303
|
|
arc: S1_V02S0601 V01N0001
|
|
arc: S1_V02S0701 H06E0203
|
|
arc: V00T0000 N1_V02S0601
|
|
arc: W1_H02W0301 W3_H06E0003
|
|
arc: W1_H02W0701 W3_H06E0203
|
|
arc: A1 F5
|
|
arc: A5 V02S0301
|
|
arc: B1 H02W0101
|
|
arc: B5 H02E0101
|
|
arc: C1 N1_V02S0401
|
|
arc: C5 V02S0201
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D1 N1_V02S0201
|
|
arc: D5 H02E0001
|
|
arc: F0 F5A_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: M0 V00T0000
|
|
arc: M2 H02W0601
|
|
arc: M6 H02W0401
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: S1_V02S0201 Q2
|
|
arc: V01S0100 Q6
|
|
arc: W1_H02W0201 F0
|
|
word: SLICEC.K1.INIT 1000000000000000
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 1000000000000000
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R26C3:PLC2
|
|
arc: W1_H02W0501 V06S0303
|
|
|
|
.tile R26C40:PLC2
|
|
arc: E1_H02E0201 V06N0103
|
|
arc: H00L0000 V02S0001
|
|
arc: H00R0000 V02N0401
|
|
arc: H00R0100 H02W0701
|
|
arc: N1_V02N0001 S1_V02N0001
|
|
arc: N1_V02N0101 S1_V02N0101
|
|
arc: N1_V02N0301 S1_V02N0201
|
|
arc: N1_V02N0401 S1_V02N0401
|
|
arc: N1_V02N0501 S1_V02N0501
|
|
arc: N1_V02N0601 H06E0303
|
|
arc: N1_V02N0701 S1_V02N0601
|
|
arc: S1_V02S0101 E1_H01W0100
|
|
arc: S1_V02S0301 W3_H06E0003
|
|
arc: S1_V02S0401 H06E0203
|
|
arc: S1_V02S0501 W1_H02E0501
|
|
arc: V00B0000 N1_V02S0201
|
|
arc: V00B0100 V02N0101
|
|
arc: V00T0000 E1_H02W0201
|
|
arc: V00T0100 V02S0501
|
|
arc: W1_H02W0101 N1_V02S0101
|
|
arc: W1_H02W0401 V02N0401
|
|
arc: W1_H02W0501 N1_V02S0501
|
|
arc: W1_H02W0601 V02N0601
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
arc: A0 H00L0000
|
|
arc: A2 E1_H02W0501
|
|
arc: A3 E1_H02W0701
|
|
arc: A4 N1_V02S0301
|
|
arc: A5 V00T0000
|
|
arc: A6 V02N0301
|
|
arc: A7 V00T0100
|
|
arc: B2 H00R0100
|
|
arc: B3 H02W0301
|
|
arc: B4 E1_H02W0301
|
|
arc: B5 V02N0501
|
|
arc: B6 E1_H02W0101
|
|
arc: B7 V00B0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0001 Q1
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: M0 V00B0100
|
|
arc: M1 H00R0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0101 Q3
|
|
arc: S1_V02S0001 Q2
|
|
arc: S1_V02S0201 Q0
|
|
arc: S1_V02S0601 Q4
|
|
arc: S1_V02S0701 Q5
|
|
arc: V01S0000 Q6
|
|
arc: V01S0100 Q7
|
|
word: SLICED.K1.INIT 0110011001101010
|
|
word: SLICED.K0.INIT 0110011001101010
|
|
word: SLICEC.K1.INIT 0110011001101010
|
|
word: SLICEC.K0.INIT 0110011001101010
|
|
word: SLICEB.K1.INIT 0110011001101100
|
|
word: SLICEB.K0.INIT 0110011001101100
|
|
word: SLICEA.K1.INIT 1111111111111111
|
|
word: SLICEA.K0.INIT 0000000000001010
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 YES
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R26C41:PLC2
|
|
arc: H00L0000 H02W0001
|
|
arc: H00R0000 V02S0601
|
|
arc: H01W0100 W3_H06E0303
|
|
arc: N1_V02N0101 S1_V02N0101
|
|
arc: N1_V02N0201 H02E0201
|
|
arc: N1_V02N0301 S1_V02N0201
|
|
arc: S1_V02S0101 H06E0103
|
|
arc: S1_V02S0401 H06E0203
|
|
arc: S1_V02S0601 H01E0001
|
|
arc: V00B0000 H02W0401
|
|
arc: V00T0000 E1_H02W0201
|
|
arc: W1_H02W0301 V06S0003
|
|
arc: W1_H02W0701 V06S0203
|
|
arc: W3_H06W0303 E3_H06W0203
|
|
arc: A0 H00L0000
|
|
arc: A1 V02N0501
|
|
arc: A2 V02N0701
|
|
arc: A3 V02S0701
|
|
arc: A4 V02N0101
|
|
arc: A5 E1_H02W0501
|
|
arc: A6 E1_H02W0701
|
|
arc: A7 V02S0101
|
|
arc: B0 N1_V02S0301
|
|
arc: B1 N1_V02S0101
|
|
arc: B2 V02S0301
|
|
arc: B3 H00R0000
|
|
arc: B4 N1_V02S0701
|
|
arc: B5 S1_V02N0701
|
|
arc: B6 V00B0000
|
|
arc: B7 V00T0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0101 Q1
|
|
arc: S1_V02S0001 Q0
|
|
arc: S1_V02S0201 Q2
|
|
arc: S1_V02S0301 Q3
|
|
arc: S1_V02S0501 Q7
|
|
arc: S1_V02S0701 Q5
|
|
arc: V01S0000 Q4
|
|
arc: V01S0100 Q6
|
|
word: SLICED.K1.INIT 0110011001101010
|
|
word: SLICED.K0.INIT 0110011001101100
|
|
word: SLICEC.K1.INIT 0110011001101100
|
|
word: SLICEC.K0.INIT 0110011001101010
|
|
word: SLICEB.K1.INIT 0110011001101100
|
|
word: SLICEB.K0.INIT 0110011001101100
|
|
word: SLICEA.K1.INIT 0110011001101100
|
|
word: SLICEA.K0.INIT 0110011001101010
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R26C42:PLC2
|
|
arc: H00L0000 N1_V02S0001
|
|
arc: H00R0100 N1_V02S0701
|
|
arc: N1_V02N0101 S3_V06N0103
|
|
arc: N1_V02N0601 H02W0601
|
|
arc: S1_V02S0101 H02W0101
|
|
arc: W1_H02W0001 V06S0003
|
|
arc: W1_H02W0101 E1_H02W0101
|
|
arc: W1_H02W0201 V06S0103
|
|
arc: W1_H02W0301 E1_H02W0301
|
|
arc: W1_H02W0401 N3_V06S0203
|
|
arc: W1_H02W0501 V06S0303
|
|
arc: W1_H02W0701 V06S0203
|
|
arc: A0 H00L0000
|
|
arc: A1 V02N0701
|
|
arc: A2 V01N0101
|
|
arc: B0 N1_V02S0101
|
|
arc: B1 H00R0100
|
|
arc: B2 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: N1_V01N0101 Q2
|
|
arc: S1_V02S0201 Q0
|
|
arc: S1_V02S0301 Q1
|
|
word: SLICEC.K1.INIT 0000000000001110
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0110011001101100
|
|
word: SLICEA.K1.INIT 0110011001101100
|
|
word: SLICEA.K0.INIT 0110011001101010
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R26C43:PLC2
|
|
arc: N1_V02N0601 S3_V06N0303
|
|
arc: S1_V02S0301 W3_H06E0003
|
|
arc: W1_H02W0101 W3_H06E0103
|
|
arc: W1_H02W0201 V06S0103
|
|
arc: W1_H02W0501 V06S0303
|
|
arc: W1_H02W0601 V02N0601
|
|
arc: W1_H02W0701 N1_V01S0100
|
|
|
|
.tile R26C44:PLC2
|
|
arc: N1_V02N0501 H06W0303
|
|
arc: W1_H02W0101 V06S0103
|
|
arc: W1_H02W0301 V06S0003
|
|
|
|
.tile R26C45:PLC2
|
|
arc: N3_V06N0103 S3_V06N0103
|
|
|
|
.tile R26C46:PLC2
|
|
arc: N1_V02N0001 S1_V02N0501
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
|
|
.tile R26C47:PLC2
|
|
arc: N1_V02N0601 S1_V02N0601
|
|
arc: W3_H06W0203 E3_H06W0203
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
|
|
.tile R26C52:PLC2
|
|
arc: W3_H06W0303 E3_H06W0203
|
|
|
|
.tile R26C53:PLC2
|
|
arc: W3_H06W0203 E3_H06W0203
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
|
|
.tile R26C58:PLC2
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
|
|
.tile R26C59:PLC2
|
|
arc: W3_H06W0203 E3_H06W0203
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
|
|
.tile R26C64:PLC2
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
|
|
.tile R26C65:PLC2
|
|
arc: W3_H06W0203 E3_H06W0203
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
|
|
.tile R26C70:PLC2
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
|
|
.tile R26C71:PLC2
|
|
arc: W3_H06W0203 E3_H06W0203
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
|
|
.tile R26C76:PLC2
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
|
|
.tile R26C77:PLC2
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
|
|
.tile R26C7:PLC2
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
|
|
.tile R26C82:PLC2
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
|
|
.tile R26C83:PLC2
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
|
|
.tile R26C86:PLC2
|
|
arc: E3_H06E0203 V06S0203
|
|
|
|
.tile R26C88:PLC2
|
|
arc: W3_H06W0003 E1_H01W0000
|
|
|
|
.tile R27C12:PLC2
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
|
|
.tile R27C18:PLC2
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
|
|
.tile R27C22:PLC2
|
|
arc: E3_H06E0003 N3_V06S0003
|
|
arc: E3_H06E0103 N3_V06S0103
|
|
arc: E3_H06E0203 N3_V06S0203
|
|
arc: N1_V02N0301 S1_V02N0201
|
|
|
|
.tile R27C23:PLC2
|
|
arc: E3_H06E0203 N3_V06S0203
|
|
|
|
.tile R27C24:PLC2
|
|
arc: V00B0100 H02W0701
|
|
arc: CE2 E1_H02W0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: LSR1 V00B0100
|
|
arc: M5 E1_H02W0001
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR2 LSR1
|
|
arc: W3_H06W0303 Q5
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R27C25:PLC2
|
|
arc: N1_V02N0101 H06E0103
|
|
arc: N1_V02N0201 S1_V02N0701
|
|
arc: N1_V02N0301 H06E0003
|
|
arc: N1_V02N0701 H06E0203
|
|
arc: W1_H02W0701 S1_V02N0701
|
|
|
|
.tile R27C26:PLC2
|
|
arc: N1_V01N0101 N3_V06S0203
|
|
arc: N1_V02N0301 N3_V06S0003
|
|
arc: N1_V02N0701 H06E0203
|
|
arc: W1_H02W0001 N1_V01S0000
|
|
arc: W1_H02W0101 S1_V02N0101
|
|
|
|
.tile R27C29:PLC2
|
|
arc: N1_V02N0101 E3_H06W0103
|
|
|
|
.tile R27C31:PLC2
|
|
arc: N1_V02N0601 S1_V02N0601
|
|
|
|
.tile R27C32:PLC2
|
|
arc: E3_H06E0203 N1_V01S0000
|
|
arc: E3_H06E0303 N1_V01S0100
|
|
arc: N1_V02N0301 N3_V06S0003
|
|
arc: N1_V02N0501 S1_V02N0501
|
|
arc: N1_V02N0701 N3_V06S0203
|
|
|
|
.tile R27C33:PLC2
|
|
arc: E1_H02E0601 N1_V01S0000
|
|
arc: E3_H06E0103 N1_V01S0100
|
|
arc: N1_V02N0101 N3_V06S0103
|
|
arc: N1_V02N0501 N3_V06S0303
|
|
|
|
.tile R27C34:PLC2
|
|
arc: E1_H02E0401 E3_H06W0203
|
|
arc: E1_H02E0501 N3_V06S0303
|
|
arc: E3_H06E0203 N1_V01S0000
|
|
arc: E3_H06E0303 N1_V01S0100
|
|
arc: N1_V02N0201 S1_V02N0201
|
|
arc: N1_V02N0301 S1_V02N0201
|
|
|
|
.tile R27C35:PLC2
|
|
arc: E1_H02E0501 E3_H06W0303
|
|
arc: E1_H02E0601 W1_H02E0601
|
|
arc: E1_H02E0701 N3_V06S0203
|
|
arc: E3_H06E0003 N1_V01S0000
|
|
arc: E3_H06E0303 N1_V01S0100
|
|
arc: N1_V02N0501 N3_V06S0303
|
|
arc: N1_V02N0701 E1_H02W0701
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
|
|
.tile R27C36:PLC2
|
|
arc: E1_H02E0101 V02S0101
|
|
arc: E1_H02E0301 V02S0301
|
|
arc: E1_H02E0501 W1_H02E0401
|
|
arc: E3_H06E0103 N1_V01S0100
|
|
arc: E3_H06E0203 N1_V01S0000
|
|
arc: H00R0000 H02W0401
|
|
arc: N1_V02N0001 N3_V06S0003
|
|
arc: N1_V02N0501 W1_H02E0501
|
|
arc: N1_V02N0701 H02E0701
|
|
arc: A0 N1_V02S0701
|
|
arc: B0 H02W0101
|
|
arc: C0 H02W0601
|
|
arc: CE0 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02S0201
|
|
arc: F0 F0_SLICE
|
|
arc: MUXCLK0 CLK0
|
|
arc: S3_V06S0003 Q0
|
|
word: SLICEA.K0.INIT 0000111110001010
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
|
|
.tile R27C37:PLC2
|
|
arc: E1_H02E0101 V02S0101
|
|
arc: E1_H02E0501 W1_H02E0501
|
|
arc: E1_H02E0701 W1_H02E0601
|
|
arc: E3_H06E0003 N1_V01S0000
|
|
arc: E3_H06E0303 N1_V01S0100
|
|
arc: H00R0000 H02W0401
|
|
arc: N1_V02N0101 N3_V06S0103
|
|
arc: N1_V02N0201 S1_V02N0701
|
|
arc: N1_V02N0401 V01N0001
|
|
arc: N1_V02N0501 N3_V06S0303
|
|
arc: N1_V02N0701 V01N0101
|
|
arc: S1_V02S0701 E1_H01W0100
|
|
arc: V00B0000 E1_H02W0601
|
|
arc: V00T0000 V02S0601
|
|
arc: W1_H02W0101 V06S0103
|
|
arc: W1_H02W0401 S1_V02N0401
|
|
arc: W1_H02W0601 N1_V02S0601
|
|
arc: W1_H02W0701 N3_V06S0203
|
|
arc: A0 V02N0501
|
|
arc: A2 H02W0501
|
|
arc: A3 H02W0701
|
|
arc: A4 V00B0000
|
|
arc: A5 E1_H02W0701
|
|
arc: A6 H00R0000
|
|
arc: A7 H02E0501
|
|
arc: B2 H02W0301
|
|
arc: B3 H02W0101
|
|
arc: B4 V02S0701
|
|
arc: B5 V02S0501
|
|
arc: B6 H02E0101
|
|
arc: B7 V00T0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: S1_V02S0001 Q2
|
|
arc: S1_V02S0101 Q3
|
|
arc: S1_V02S0501 Q7
|
|
arc: S1_V02S0601 Q6
|
|
arc: V01S0000 Q5
|
|
arc: V01S0100 Q4
|
|
word: SLICED.K1.INIT 0110011001101010
|
|
word: SLICED.K0.INIT 0110011001101010
|
|
word: SLICEC.K1.INIT 0110011001101010
|
|
word: SLICEC.K0.INIT 0110011001101010
|
|
word: SLICEB.K1.INIT 0110011001101100
|
|
word: SLICEB.K0.INIT 0110011001101100
|
|
word: SLICEA.K1.INIT 1111111111111111
|
|
word: SLICEA.K0.INIT 0000000000001010
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 YES
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R27C38:PLC2
|
|
arc: E1_H02E0601 W1_H02E0301
|
|
arc: H00L0000 H02W0001
|
|
arc: H00R0000 E1_H02W0601
|
|
arc: N1_V02N0101 S1_V02N0001
|
|
arc: N1_V02N0301 S1_V02N0301
|
|
arc: N1_V02N0401 V01N0001
|
|
arc: N1_V02N0701 V01N0101
|
|
arc: S1_V02S0701 E1_H01W0100
|
|
arc: V00B0000 H02W0401
|
|
arc: V00T0000 V02S0401
|
|
arc: W1_H02W0101 E1_H02W0101
|
|
arc: W1_H02W0301 E1_H02W0201
|
|
arc: W1_H02W0401 E1_H02W0401
|
|
arc: W1_H02W0501 W3_H06E0303
|
|
arc: W1_H02W0701 W3_H06E0203
|
|
arc: A0 H02E0701
|
|
arc: A1 H00R0000
|
|
arc: A2 V02N0501
|
|
arc: A3 V00B0000
|
|
arc: A4 V02N0301
|
|
arc: A5 H02E0501
|
|
arc: A6 H02W0501
|
|
arc: A7 H00L0000
|
|
arc: B0 H02W0301
|
|
arc: B1 H02W0101
|
|
arc: B2 V02S0101
|
|
arc: B3 V02S0301
|
|
arc: B4 V02S0701
|
|
arc: B5 V02S0501
|
|
arc: B6 V00T0000
|
|
arc: B7 H02E0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0100 Q3
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: S1_V02S0001 Q0
|
|
arc: S1_V02S0201 Q2
|
|
arc: S1_V02S0301 Q1
|
|
arc: S1_V02S0501 Q7
|
|
arc: S1_V02S0601 Q6
|
|
arc: V01S0000 Q5
|
|
arc: V01S0100 Q4
|
|
word: SLICED.K1.INIT 0110011001101010
|
|
word: SLICED.K0.INIT 0110011001101010
|
|
word: SLICEC.K1.INIT 0110011001101010
|
|
word: SLICEC.K0.INIT 0110011001101010
|
|
word: SLICEB.K1.INIT 0110011001101010
|
|
word: SLICEB.K0.INIT 0110011001101010
|
|
word: SLICEA.K1.INIT 0110011001101010
|
|
word: SLICEA.K0.INIT 0110011001101100
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R27C39:PLC2
|
|
arc: E1_H02E0101 V02S0101
|
|
arc: E1_H02E0501 V02S0501
|
|
arc: E1_H02E0701 V02S0701
|
|
arc: N1_V02N0101 V01N0101
|
|
arc: N1_V02N0201 V01N0001
|
|
arc: N1_V02N0301 S1_V02N0301
|
|
arc: S1_V02S0301 N1_V01S0100
|
|
arc: V00B0000 E1_H02W0601
|
|
arc: V00T0000 H02W0001
|
|
arc: V00T0100 V02N0701
|
|
arc: W1_H02W0001 E1_H02W0501
|
|
arc: W1_H02W0101 W3_H06E0103
|
|
arc: W1_H02W0301 E1_H02W0201
|
|
arc: W1_H02W0401 E1_H02W0101
|
|
arc: W1_H02W0501 E1_H02W0401
|
|
arc: W1_H02W0601 E1_H01W0000
|
|
arc: W1_H02W0701 E1_H01W0100
|
|
arc: A0 H02W0701
|
|
arc: A1 H02W0501
|
|
arc: A2 E1_H02W0701
|
|
arc: A3 V02N0701
|
|
arc: A4 V00T0100
|
|
arc: A5 V02N0301
|
|
arc: B0 V00T0000
|
|
arc: B1 V00B0000
|
|
arc: B2 V02S0301
|
|
arc: B3 H02W0301
|
|
arc: B4 H02W0301
|
|
arc: B5 V02N0701
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0001 F4
|
|
arc: E1_H01E0101 F4
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: H00R0000 F4
|
|
arc: H01W0100 Q3
|
|
arc: M5 H00R0000
|
|
arc: M6 N1_V01N0101
|
|
arc: M7 H00R0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q2
|
|
arc: N1_V01N0101 F4
|
|
arc: S1_V02S0101 Q1
|
|
arc: S1_V02S0201 Q0
|
|
arc: S1_V02S0401 F4
|
|
arc: S1_V02S0501 Q7
|
|
arc: S1_V02S0601 Q6
|
|
arc: V01S0000 Q5
|
|
arc: V01S0100 Q4
|
|
word: SLICED.K1.INIT 0000000000001110
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0110011001101100
|
|
word: SLICEC.K0.INIT 0110011001101010
|
|
word: SLICEB.K1.INIT 0110011001101010
|
|
word: SLICEB.K0.INIT 0110011001101010
|
|
word: SLICEA.K1.INIT 0110011001101100
|
|
word: SLICEA.K0.INIT 0110011001101100
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R27C3:PLC2
|
|
arc: S3_V06S0303 H06W0303
|
|
|
|
.tile R27C40:PLC2
|
|
arc: E1_H02E0501 V02S0501
|
|
arc: E1_H02E0701 W1_H02E0601
|
|
arc: H00L0000 N1_V02S0001
|
|
arc: H00R0000 V02S0401
|
|
arc: N1_V02N0001 V01N0001
|
|
arc: N1_V02N0101 H01E0101
|
|
arc: N1_V02N0301 E1_H02W0301
|
|
arc: N1_V02N0401 H01E0001
|
|
arc: N1_V02N0501 H06W0303
|
|
arc: N1_V02N0601 H01E0001
|
|
arc: N1_V02N0701 V01N0101
|
|
arc: S1_V02S0401 H01E0001
|
|
arc: V00B0000 V02S0001
|
|
arc: V00T0000 V02S0601
|
|
arc: W1_H02W0001 E1_H02W0001
|
|
arc: W1_H02W0301 V02S0301
|
|
arc: W1_H02W0501 W3_H06E0303
|
|
arc: W1_H02W0601 E1_H01W0000
|
|
arc: W1_H02W0701 W3_H06E0203
|
|
arc: A0 H00L0000
|
|
arc: A2 V00B0000
|
|
arc: A3 N1_V02S0701
|
|
arc: A4 V00T0000
|
|
arc: A5 V02S0101
|
|
arc: A6 H02E0701
|
|
arc: A7 N1_V01S0100
|
|
arc: B2 E1_H01W0100
|
|
arc: B3 H02W0301
|
|
arc: B4 H00R0000
|
|
arc: B5 V02S0701
|
|
arc: B6 N1_V01S0000
|
|
arc: B7 H02E0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 Q4
|
|
arc: H01W0100 Q5
|
|
arc: M0 H01E0001
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: S1_V02S0201 Q0
|
|
arc: W1_H02W0101 Q3
|
|
arc: W1_H02W0201 Q2
|
|
arc: W1_H02W0401 Q6
|
|
arc: W3_H06W0203 Q7
|
|
word: SLICED.K1.INIT 0110011001101010
|
|
word: SLICED.K0.INIT 0110011001101100
|
|
word: SLICEC.K1.INIT 0110011001101100
|
|
word: SLICEC.K0.INIT 0110011001101010
|
|
word: SLICEB.K1.INIT 0110011001101010
|
|
word: SLICEB.K0.INIT 0110011001101010
|
|
word: SLICEA.K1.INIT 1111111111111111
|
|
word: SLICEA.K0.INIT 0000000000001010
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 YES
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R27C41:PLC2
|
|
arc: H00L0000 V02S0201
|
|
arc: H00L0100 V02S0101
|
|
arc: H01W0100 W3_H06E0303
|
|
arc: N1_V02N0101 N3_V06S0103
|
|
arc: N1_V02N0501 H02W0501
|
|
arc: N1_V02N0701 E1_H02W0701
|
|
arc: N3_V06N0203 E3_H06W0203
|
|
arc: V00B0000 V02S0001
|
|
arc: V00T0000 V02S0401
|
|
arc: W1_H02W0301 W3_H06E0003
|
|
arc: W1_H02W0601 E1_H01W0000
|
|
arc: W1_H02W0701 E1_H01W0100
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
arc: A0 H02W0701
|
|
arc: A1 N1_V02S0501
|
|
arc: A2 H00L0100
|
|
arc: A3 H02E0701
|
|
arc: A4 V02N0301
|
|
arc: A5 W1_H02E0501
|
|
arc: A6 N1_V01S0100
|
|
arc: A7 H02E0501
|
|
arc: B0 V00B0000
|
|
arc: B1 H02W0101
|
|
arc: B2 H00L0000
|
|
arc: B3 V02S0301
|
|
arc: B4 N1_V01S0000
|
|
arc: B5 V02S0701
|
|
arc: B6 V00T0000
|
|
arc: B7 V02S0501
|
|
arc: CLK0 G_HPBX0000
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 Q1
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: V01S0000 Q4
|
|
arc: V01S0100 Q2
|
|
arc: W1_H02W0101 Q3
|
|
arc: W1_H02W0201 Q0
|
|
arc: W1_H02W0401 Q6
|
|
arc: W1_H02W0501 Q7
|
|
arc: W3_H06W0303 Q5
|
|
word: SLICED.K1.INIT 0110011001101100
|
|
word: SLICED.K0.INIT 0110011001101010
|
|
word: SLICEC.K1.INIT 0110011001101100
|
|
word: SLICEC.K0.INIT 0110011001101100
|
|
word: SLICEB.K1.INIT 0110011001101100
|
|
word: SLICEB.K0.INIT 0110011001101100
|
|
word: SLICEA.K1.INIT 0110011001101010
|
|
word: SLICEA.K0.INIT 0110011001101100
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R27C42:PLC2
|
|
arc: H00L0100 V02S0301
|
|
arc: N1_V01N0101 N3_V06S0203
|
|
arc: N1_V02N0101 N3_V06S0103
|
|
arc: N1_V02N0201 N3_V06S0103
|
|
arc: N1_V02N0701 N3_V06S0203
|
|
arc: V00B0000 V02S0201
|
|
arc: W1_H02W0101 W3_H06E0103
|
|
arc: W1_H02W0301 N3_V06S0003
|
|
arc: W1_H02W0501 N3_V06S0303
|
|
arc: W1_H02W0701 W3_H06E0203
|
|
arc: A0 H02W0501
|
|
arc: A1 H00L0100
|
|
arc: A2 N1_V02S0501
|
|
arc: A3 N1_V02S0501
|
|
arc: B0 V00B0000
|
|
arc: B1 H02W0301
|
|
arc: B2 V02S0101
|
|
arc: B3 V02S0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: H01W0000 Q1
|
|
arc: H01W0100 Q2
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: V01S0000 Q3
|
|
arc: W1_H02W0001 Q0
|
|
word: SLICEC.K1.INIT 0000000000001110
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0110011001101010
|
|
word: SLICEB.K0.INIT 0110011001101010
|
|
word: SLICEA.K1.INIT 0110011001101010
|
|
word: SLICEA.K0.INIT 0110011001101100
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R27C43:PLC2
|
|
arc: N1_V02N0501 S1_V02N0501
|
|
arc: N1_V02N0601 S1_V02N0601
|
|
arc: N1_V02N0701 S1_V02N0601
|
|
arc: W1_H02W0301 W3_H06E0003
|
|
arc: W1_H02W0501 W3_H06E0303
|
|
arc: W1_H02W0701 N3_V06S0203
|
|
arc: W3_H06W0303 N3_V06S0303
|
|
|
|
.tile R27C47:PLC2
|
|
arc: W3_H06W0203 E3_H06W0203
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
|
|
.tile R27C53:PLC2
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
arc: W3_H06W0303 E3_H06W0203
|
|
|
|
.tile R27C59:PLC2
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
arc: W3_H06W0203 E3_H06W0203
|
|
|
|
.tile R27C65:PLC2
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
|
|
.tile R27C6:PLC2
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
|
|
.tile R27C71:PLC2
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
|
|
.tile R27C77:PLC2
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
arc: W3_H06W0303 E3_H06W0203
|
|
|
|
.tile R27C83:PLC2
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
|
|
.tile R28C12:PLC2
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
|
|
.tile R28C13:PLC2
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
|
|
.tile R28C18:PLC2
|
|
arc: N1_V02N0501 S3_V06N0303
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
|
|
.tile R28C19:PLC2
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
|
|
.tile R28C22:PLC2
|
|
arc: N3_V06N0103 S3_V06N0103
|
|
|
|
.tile R28C23:PLC2
|
|
arc: N3_V06N0303 S3_V06N0303
|
|
|
|
.tile R28C24:PLC2
|
|
arc: W3_H06W0303 E3_H06W0203
|
|
|
|
.tile R28C25:PLC2
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
arc: N3_V06N0003 S3_V06N0003
|
|
arc: N3_V06N0303 S3_V06N0303
|
|
|
|
.tile R28C28:PLC2
|
|
arc: N1_V02N0501 S3_V06N0303
|
|
arc: N1_V02N0701 H06E0203
|
|
arc: N3_V06N0203 S3_V06N0103
|
|
|
|
.tile R28C29:PLC2
|
|
arc: N3_V06N0103 S3_V06N0103
|
|
|
|
.tile R28C30:PLC2
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
|
|
.tile R28C32:PLC2
|
|
arc: E1_H02E0101 V06S0103
|
|
|
|
.tile R28C33:PLC2
|
|
arc: N1_V02N0101 H02E0101
|
|
|
|
.tile R28C34:PLC2
|
|
arc: N1_V02N0001 S3_V06N0003
|
|
arc: N3_V06N0303 S3_V06N0203
|
|
|
|
.tile R28C35:PLC2
|
|
arc: N3_V06N0003 S3_V06N0003
|
|
arc: N3_V06N0103 S3_V06N0103
|
|
|
|
.tile R28C36:PLC2
|
|
arc: E1_H02E0501 N3_V06S0303
|
|
arc: N1_V02N0201 S3_V06N0103
|
|
arc: N3_V06N0303 S3_V06N0303
|
|
arc: V00B0000 S1_V02N0001
|
|
arc: V00B0100 H02W0701
|
|
arc: CE1 V02N0201
|
|
arc: CLK0 G_HPBX0000
|
|
arc: LSR0 V00B0100
|
|
arc: M2 V00B0000
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXLSR1 LSR0
|
|
arc: W3_H06W0103 Q2
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R28C37:PLC2
|
|
arc: E1_H02E0101 V02N0101
|
|
arc: E1_H02E0501 E1_H01W0100
|
|
arc: E1_H02E0701 V02S0701
|
|
arc: H00L0000 V02N0201
|
|
arc: N1_V02N0501 H02E0501
|
|
arc: N3_V06N0303 S3_V06N0303
|
|
arc: S1_V02S0401 N1_V02S0401
|
|
arc: V00B0000 V02S0001
|
|
arc: V00T0000 V02S0601
|
|
arc: W1_H02W0701 V02N0701
|
|
arc: A0 H02E0501
|
|
arc: A2 V00B0000
|
|
arc: A3 H00L0100
|
|
arc: A4 N1_V01S0100
|
|
arc: A5 Q5
|
|
arc: A6 V02N0301
|
|
arc: A7 Q7
|
|
arc: B2 H01W0100
|
|
arc: B3 V02S0101
|
|
arc: B4 H00R0000
|
|
arc: B5 N1_V01S0000
|
|
arc: B6 V00T0000
|
|
arc: B7 V02S0501
|
|
arc: CE1 V02N0201
|
|
arc: CE2 H00L0000
|
|
arc: CE3 H00L0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00L0100 Q3
|
|
arc: H00R0000 Q4
|
|
arc: H01W0100 Q2
|
|
arc: LSR1 H02W0501
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR1
|
|
arc: N1_V01N0001 Q5
|
|
arc: N1_V01N0101 Q3
|
|
arc: N1_V02N0201 Q2
|
|
arc: N1_V02N0401 Q4
|
|
arc: N1_V02N0601 Q6
|
|
arc: N1_V02N0701 Q7
|
|
arc: V01S0100 Q6
|
|
word: SLICED.K1.INIT 0110011001101010
|
|
word: SLICED.K0.INIT 0110011001101010
|
|
word: SLICEC.K1.INIT 0110011001101010
|
|
word: SLICEC.K0.INIT 0110011001101100
|
|
word: SLICEB.K1.INIT 0110011001101010
|
|
word: SLICEB.K0.INIT 0110011001101100
|
|
word: SLICEA.K1.INIT 1111111111111111
|
|
word: SLICEA.K0.INIT 0000000000001010
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 YES
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R28C38:PLC2
|
|
arc: E1_H02E0501 V02N0501
|
|
arc: E1_H02E0701 V02S0701
|
|
arc: H00L0000 V02S0201
|
|
arc: N1_V02N0301 H06W0003
|
|
arc: N1_V02N0501 H06W0303
|
|
arc: V00B0000 V02S0001
|
|
arc: V00T0000 V02S0601
|
|
arc: V00T0100 V02N0501
|
|
arc: W1_H02W0501 V02N0501
|
|
arc: A0 E1_H01E0001
|
|
arc: A1 H00L0100
|
|
arc: A2 H02E0501
|
|
arc: A3 H02E0701
|
|
arc: A4 N1_V01S0100
|
|
arc: A5 Q5
|
|
arc: A6 H02W0701
|
|
arc: A7 Q7
|
|
arc: B0 V00B0000
|
|
arc: B1 V02S0301
|
|
arc: B2 H00L0000
|
|
arc: B3 Q3
|
|
arc: B4 H00R0000
|
|
arc: B5 N1_V01S0000
|
|
arc: B6 V00T0000
|
|
arc: B7 V02S0501
|
|
arc: CE0 H02E0101
|
|
arc: CE1 H02E0101
|
|
arc: CE2 H02E0101
|
|
arc: CE3 H02E0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0001 Q0
|
|
arc: E1_H01E0101 Q6
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00L0100 Q1
|
|
arc: H00R0000 Q4
|
|
arc: H01W0100 Q2
|
|
arc: LSR0 V00T0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR0
|
|
arc: MUXLSR3 LSR0
|
|
arc: N1_V01N0001 Q3
|
|
arc: N1_V01N0101 Q0
|
|
arc: N1_V02N0101 Q1
|
|
arc: N1_V02N0201 Q2
|
|
arc: N1_V02N0601 Q4
|
|
arc: N1_V02N0701 Q5
|
|
arc: V01S0000 Q6
|
|
arc: V01S0100 Q7
|
|
word: SLICED.K1.INIT 0110011001101010
|
|
word: SLICED.K0.INIT 0110011001101010
|
|
word: SLICEC.K1.INIT 0110011001101010
|
|
word: SLICEC.K0.INIT 0110011001101100
|
|
word: SLICEB.K1.INIT 0110011001101100
|
|
word: SLICEB.K0.INIT 0110011001101010
|
|
word: SLICEA.K1.INIT 0110011001101010
|
|
word: SLICEA.K0.INIT 0110011001101010
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R28C39:PLC2
|
|
arc: E1_H02E0101 N1_V01S0100
|
|
arc: E1_H02E0301 V02S0301
|
|
arc: E1_H02E0501 V02S0501
|
|
arc: H00L0000 V02S0201
|
|
arc: H00R0000 V02S0601
|
|
arc: N1_V02N0301 H02W0301
|
|
arc: N1_V02N0701 H06W0203
|
|
arc: V00B0000 N1_V02S0201
|
|
arc: V00T0000 N1_V02S0601
|
|
arc: W1_H02W0701 H01E0101
|
|
arc: A0 H00L0000
|
|
arc: A1 H00L0100
|
|
arc: A2 V00T0000
|
|
arc: A3 H02E0701
|
|
arc: A4 H02W0501
|
|
arc: A5 Q5
|
|
arc: A6 H00R0000
|
|
arc: A7 Q7
|
|
arc: B0 H01W0100
|
|
arc: B1 V02S0101
|
|
arc: B2 V02N0301
|
|
arc: B3 Q3
|
|
arc: B4 S1_V02N0701
|
|
arc: B5 N1_V01S0000
|
|
arc: B6 V01S0000
|
|
arc: B7 V00B0000
|
|
arc: CE0 H02W0101
|
|
arc: CE1 H02W0101
|
|
arc: CE2 H02W0101
|
|
arc: CE3 H02W0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0001 Q7
|
|
arc: E1_H01E0101 Q4
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00L0100 Q1
|
|
arc: H01W0100 Q0
|
|
arc: LSR0 H02E0501
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR0
|
|
arc: MUXLSR3 LSR0
|
|
arc: N1_V01N0001 Q3
|
|
arc: N1_V01N0101 Q1
|
|
arc: N1_V02N0201 Q0
|
|
arc: N1_V02N0401 Q6
|
|
arc: N1_V02N0501 Q5
|
|
arc: N1_V02N0601 Q4
|
|
arc: V01S0000 Q6
|
|
arc: V01S0100 Q2
|
|
word: SLICED.K1.INIT 0110011001101010
|
|
word: SLICED.K0.INIT 0110011001101100
|
|
word: SLICEC.K1.INIT 0110011001101010
|
|
word: SLICEC.K0.INIT 0110011001101010
|
|
word: SLICEB.K1.INIT 0110011001101100
|
|
word: SLICEB.K0.INIT 0110011001101100
|
|
word: SLICEA.K1.INIT 0110011001101010
|
|
word: SLICEA.K0.INIT 0110011001101100
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R28C3:PLC2
|
|
arc: S3_V06S0203 H06W0203
|
|
|
|
.tile R28C40:PLC2
|
|
arc: E1_H02E0101 V02N0101
|
|
arc: H00L0000 V02S0201
|
|
arc: N1_V02N0601 H01E0001
|
|
arc: V00B0000 N1_V02S0201
|
|
arc: V00T0000 V02N0401
|
|
arc: W1_H02W0101 V02N0101
|
|
arc: W1_H02W0301 N1_V02S0301
|
|
arc: W1_H02W0501 H01E0101
|
|
arc: A0 H00L0000
|
|
arc: A1 V01N0101
|
|
arc: A2 H02E0501
|
|
arc: A3 H00L0100
|
|
arc: A4 H02W0501
|
|
arc: A5 Q5
|
|
arc: A6 H00R0000
|
|
arc: A7 Q7
|
|
arc: B0 H01W0100
|
|
arc: B1 Q1
|
|
arc: B2 V02N0301
|
|
arc: B3 V01N0001
|
|
arc: B4 H02E0301
|
|
arc: B5 V02N0501
|
|
arc: B6 V00B0000
|
|
arc: B7 V00T0000
|
|
arc: CE0 V02N0201
|
|
arc: CE1 V02N0201
|
|
arc: CE2 S1_V02N0601
|
|
arc: CE3 S1_V02N0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0101 Q4
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00L0100 Q3
|
|
arc: H00R0000 Q6
|
|
arc: H01W0100 Q0
|
|
arc: LSR1 W1_H02E0501
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR1
|
|
arc: N1_V01N0001 Q6
|
|
arc: N1_V01N0101 Q3
|
|
arc: N1_V02N0001 Q2
|
|
arc: N1_V02N0101 Q1
|
|
arc: N1_V02N0201 Q0
|
|
arc: N1_V02N0401 Q4
|
|
arc: N1_V02N0501 Q5
|
|
arc: N3_V06N0203 Q7
|
|
arc: V01S0100 Q2
|
|
word: SLICED.K1.INIT 0110011001101010
|
|
word: SLICED.K0.INIT 0110011001101010
|
|
word: SLICEC.K1.INIT 0110011001101010
|
|
word: SLICEC.K0.INIT 0110011001101010
|
|
word: SLICEB.K1.INIT 0110011001101010
|
|
word: SLICEB.K0.INIT 0110011001101100
|
|
word: SLICEA.K1.INIT 0110011001101100
|
|
word: SLICEA.K0.INIT 0110011001101100
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R28C41:PLC2
|
|
arc: H00R0000 N1_V02S0601
|
|
arc: N1_V02N0301 E1_H02W0301
|
|
arc: N1_V02N0701 N3_V06S0203
|
|
arc: V00T0000 V02N0601
|
|
arc: W1_H02W0501 H01E0101
|
|
arc: W3_H06W0003 N1_V01S0000
|
|
arc: W3_H06W0303 N1_V01S0100
|
|
arc: A0 H00L0000
|
|
arc: A1 H00R0000
|
|
arc: B0 W1_H02E0101
|
|
arc: B1 Q1
|
|
arc: CE0 H02E0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: H00L0000 Q0
|
|
arc: LSR0 V00T0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: N1_V02N0101 Q1
|
|
arc: N1_V02N0201 Q0
|
|
word: SLICEB.K1.INIT 0000000000001110
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0110011001101100
|
|
word: SLICEA.K0.INIT 0110011001101010
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R28C42:PLC2
|
|
arc: N3_V06N0103 S3_V06N0003
|
|
arc: W3_H06W0203 N1_V01S0000
|
|
|
|
.tile R28C43:PLC2
|
|
arc: N3_V06N0303 S3_V06N0203
|
|
arc: W1_H02W0301 N1_V02S0301
|
|
|
|
.tile R28C44:PLC2
|
|
arc: N3_V06N0003 S3_V06N0303
|
|
|
|
.tile R28C46:PLC2
|
|
arc: N1_V02N0501 H02W0501
|
|
|
|
.tile R28C47:PLC2
|
|
arc: N1_V02N0601 E3_H06W0303
|
|
arc: W1_H02W0501 S3_V06N0303
|
|
|
|
.tile R28C53:PLC2
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
|
|
.tile R28C59:PLC2
|
|
arc: W3_H06W0303 E3_H06W0203
|
|
|
|
.tile R28C65:PLC2
|
|
arc: W3_H06W0203 E3_H06W0203
|
|
|
|
.tile R28C6:PLC2
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
|
|
.tile R28C71:PLC2
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
|
|
.tile R28C77:PLC2
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
|
|
.tile R28C7:PLC2
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
|
|
.tile R28C83:PLC2
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
|
|
.tile R28C87:PLC2
|
|
arc: S3_V06S0303 N3_V06S0303
|
|
|
|
.tile R29C13:PLC2
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
|
|
.tile R29C16:PLC2
|
|
arc: N3_V06N0003 S3_V06N0303
|
|
|
|
.tile R29C19:PLC2
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
arc: N3_V06N0003 S3_V06N0003
|
|
arc: N3_V06N0303 W3_H06E0303
|
|
|
|
.tile R29C22:PLC2
|
|
arc: N1_V02N0201 S3_V06N0103
|
|
arc: N3_V06N0003 S3_V06N0303
|
|
arc: N3_V06N0103 S3_V06N0103
|
|
arc: N3_V06N0303 S3_V06N0203
|
|
|
|
.tile R29C25:PLC2
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
arc: N1_V02N0701 S3_V06N0203
|
|
arc: N3_V06N0003 S3_V06N0303
|
|
arc: N3_V06N0103 S3_V06N0103
|
|
arc: N3_V06N0203 S3_V06N0203
|
|
|
|
.tile R29C26:PLC2
|
|
arc: N1_V02N0101 N3_V06S0103
|
|
|
|
.tile R29C28:PLC2
|
|
arc: H00R0000 V02N0401
|
|
arc: H00R0100 V02N0501
|
|
arc: S1_V02S0401 H02W0401
|
|
arc: V00B0100 S1_V02N0101
|
|
arc: CE0 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: LSR0 V00B0100
|
|
arc: M1 H00R0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: S1_V02S0301 Q1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R29C29:PLC2
|
|
arc: S3_V06S0203 N3_V06S0203
|
|
arc: W1_H02W0401 N3_V06S0203
|
|
|
|
.tile R29C2:PLC2
|
|
arc: W1_H02W0701 N3_V06S0203
|
|
|
|
.tile R29C31:PLC2
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
arc: N1_V02N0601 S3_V06N0303
|
|
arc: N3_V06N0203 S3_V06N0203
|
|
|
|
.tile R29C32:PLC2
|
|
arc: N1_V02N0501 N3_V06S0303
|
|
arc: N3_V06N0003 S3_V06N0303
|
|
|
|
.tile R29C34:PLC2
|
|
arc: N1_V02N0201 S3_V06N0103
|
|
arc: N3_V06N0103 S3_V06N0103
|
|
arc: N3_V06N0203 S3_V06N0203
|
|
|
|
.tile R29C35:PLC2
|
|
arc: N3_V06N0003 S3_V06N0303
|
|
arc: N3_V06N0303 S1_V02N0601
|
|
|
|
.tile R29C36:PLC2
|
|
arc: N1_V02N0201 E1_H02W0201
|
|
|
|
.tile R29C37:PLC2
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
arc: N1_V02N0101 N3_V06S0103
|
|
arc: N1_V02N0201 N3_V06S0103
|
|
arc: N1_V02N0301 N1_V01S0100
|
|
arc: N1_V02N0401 S3_V06N0203
|
|
arc: N1_V02N0701 S3_V06N0203
|
|
arc: N3_V06N0103 S1_V02N0201
|
|
arc: N3_V06N0203 S3_V06N0203
|
|
arc: N3_V06N0303 S3_V06N0203
|
|
arc: S1_V02S0101 S3_V06N0103
|
|
arc: A0 S1_V02N0701
|
|
arc: B0 S1_V02N0101
|
|
arc: C0 V02S0401
|
|
arc: CE0 S1_V02N0201
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02N0201
|
|
arc: F0 F0_SLICE
|
|
arc: MUXCLK0 CLK0
|
|
arc: S1_V02S0001 Q0
|
|
word: SLICEA.K0.INIT 0011101000110010
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
|
|
.tile R29C38:PLC2
|
|
arc: E3_H06E0303 N3_V06S0303
|
|
arc: N1_V02N0001 N1_V01S0000
|
|
arc: N1_V02N0301 N1_V01S0100
|
|
arc: N1_V02N0501 N3_V06S0303
|
|
arc: S1_V02S0101 N3_V06S0103
|
|
arc: W1_H02W0201 N3_V06S0103
|
|
|
|
.tile R29C39:PLC2
|
|
arc: N1_V02N0301 N1_V01S0100
|
|
arc: V00T0000 N1_V02S0401
|
|
arc: CLK0 G_HPBX0000
|
|
arc: M0 V00T0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: V01S0100 Q0
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R29C3:PLC2
|
|
arc: S3_V06S0203 N3_V06S0203
|
|
|
|
.tile R29C40:PLC2
|
|
arc: H00R0000 N1_V02S0401
|
|
arc: N1_V02N0101 N3_V06S0103
|
|
arc: N1_V02N0201 N3_V06S0103
|
|
arc: N1_V02N0301 N1_V01S0100
|
|
arc: N3_V06N0103 S3_V06N0103
|
|
arc: V00T0000 N1_V02S0401
|
|
arc: V01S0000 N3_V06S0103
|
|
arc: CLK0 G_HPBX0000
|
|
arc: M3 H00R0000
|
|
arc: M4 V00T0000
|
|
arc: M5 H00R0000
|
|
arc: M6 V00T0000
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q4
|
|
arc: N1_V01N0101 Q3
|
|
arc: N1_V02N0401 Q6
|
|
arc: N1_V02N0501 Q5
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R29C41:PLC2
|
|
arc: N1_V02N0601 H06E0303
|
|
arc: N3_V06N0103 S3_V06N0003
|
|
|
|
.tile R29C43:PLC2
|
|
arc: N1_V02N0501 W3_H06E0303
|
|
arc: N1_V02N0601 S3_V06N0303
|
|
arc: N3_V06N0003 S3_V06N0303
|
|
arc: N3_V06N0103 S3_V06N0103
|
|
arc: N3_V06N0303 S3_V06N0203
|
|
|
|
.tile R29C44:PLC2
|
|
arc: N3_V06N0003 S3_V06N0003
|
|
|
|
.tile R29C45:PLC2
|
|
arc: N3_V06N0003 S3_V06N0003
|
|
|
|
.tile R29C47:PLC2
|
|
arc: N3_V06N0103 E3_H06W0103
|
|
|
|
.tile R29C53:PLC2
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
|
|
.tile R29C59:PLC2
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
|
|
.tile R29C65:PLC2
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
|
|
.tile R29C71:PLC2
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
|
|
.tile R29C77:PLC2
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
|
|
.tile R29C7:PLC2
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
|
|
.tile R29C83:PLC2
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
|
|
.tile R2C53:PLC2
|
|
arc: N1_V02N0501 S3_V06N0303
|
|
|
|
.tile R30C10:PLC2
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
|
|
.tile R30C16:PLC2
|
|
arc: N3_V06N0003 S1_V02N0301
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
|
|
.tile R30C22:PLC2
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
|
|
.tile R30C28:PLC2
|
|
arc: H00L0100 V02S0301
|
|
arc: H00R0000 V02S0401
|
|
arc: H00R0100 V02N0701
|
|
arc: N1_V02N0401 S1_V02N0101
|
|
arc: N1_V02N0501 N3_V06S0303
|
|
arc: N3_V06N0103 S3_V06N0103
|
|
arc: S1_V02S0601 N3_V06S0303
|
|
arc: V00B0100 V02N0101
|
|
arc: V01S0100 N3_V06S0303
|
|
arc: CE2 H00R0000
|
|
arc: CE3 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: LSR0 V00B0100
|
|
arc: M5 H00L0100
|
|
arc: M7 H02W0201
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR2 LSR0
|
|
arc: MUXLSR3 LSR0
|
|
arc: V01S0000 Q7
|
|
arc: W3_H06W0303 Q5
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R30C29:PLC2
|
|
arc: W1_H02W0201 S1_V02N0201
|
|
|
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.tile R30C34:PLC2
|
|
arc: N3_V06N0103 S1_V02N0201
|
|
|
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.tile R30C35:PLC2
|
|
arc: N3_V06N0003 S1_V02N0301
|
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arc: N3_V06N0103 S1_V02N0101
|
|
arc: N3_V06N0203 S3_V06N0203
|
|
|
|
.tile R30C36:PLC2
|
|
arc: E1_H02E0001 V02N0001
|
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arc: E1_H02E0301 V06S0003
|
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arc: N1_V02N0001 N3_V06S0003
|
|
|
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.tile R30C37:PLC2
|
|
arc: N1_V02N0201 N3_V06S0103
|
|
arc: V00B0100 V02S0101
|
|
arc: V00T0000 S1_V02N0601
|
|
arc: V00T0100 H02E0301
|
|
arc: CE0 H02W0101
|
|
arc: CE2 H02W0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E3_H06E0003 Q0
|
|
arc: E3_H06E0303 Q5
|
|
arc: LSR0 V00B0100
|
|
arc: LSR1 V00T0000
|
|
arc: M0 V00T0100
|
|
arc: M5 H02E0001
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR2 LSR0
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
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.tile R30C38:PLC2
|
|
arc: W1_H02W0101 V02S0101
|
|
|
|
.tile R30C39:PLC2
|
|
arc: N1_V02N0701 N1_V01S0100
|
|
|
|
.tile R30C3:PLC2
|
|
arc: S3_V06S0103 N3_V06S0003
|
|
|
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.tile R30C40:PLC2
|
|
arc: N1_V02N0601 N1_V01S0000
|
|
|
|
.tile R30C43:PLC2
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
arc: N3_V06N0003 S1_V02N0301
|
|
|
|
.tile R30C49:PLC2
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
|
|
.tile R30C4:PLC2
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
|
|
.tile R30C55:PLC2
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
|
|
.tile R30C61:PLC2
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
|
|
.tile R30C67:PLC2
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
|
|
.tile R30C73:PLC2
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
|
|
.tile R30C79:PLC2
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
|
|
.tile R30C85:PLC2
|
|
arc: E1_H01E0001 W3_H06E0003
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
|
|
.tile R30C86:PLC2
|
|
arc: E3_H06E0203 H01E0001
|
|
|
|
.tile R30C87:PLC2
|
|
arc: V01S0100 N3_V06S0303
|
|
|
|
.tile R30C88:PLC2
|
|
arc: S3_V06S0203 H06E0203
|
|
|
|
.tile R31C12:PLC2
|
|
arc: W3_H06W0303 E3_H06W0203
|
|
|
|
.tile R31C18:PLC2
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
|
|
.tile R31C24:PLC2
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
|
|
.tile R31C25:PLC2
|
|
arc: N3_V06N0003 S3_V06N0303
|
|
|
|
.tile R31C28:PLC2
|
|
arc: N1_V02N0101 S1_V02N0001
|
|
arc: N1_V02N0701 N1_V01S0100
|
|
arc: N3_V06N0003 S1_V02N0001
|
|
arc: N3_V06N0103 S1_V02N0101
|
|
arc: S1_V02S0401 N1_V01S0000
|
|
arc: V00B0100 S1_V02N0101
|
|
arc: CE3 V02S0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: LSR0 V00B0100
|
|
arc: M6 H02W0401
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR3 LSR0
|
|
arc: S1_V02S0601 Q6
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R31C29:PLC2
|
|
arc: N3_V06N0003 S3_V06N0003
|
|
arc: N3_V06N0103 S3_V06N0103
|
|
arc: W1_H02W0401 V02N0401
|
|
|
|
.tile R31C30:PLC2
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
|
|
.tile R31C31:PLC2
|
|
arc: N3_V06N0103 S3_V06N0103
|
|
|
|
.tile R31C35:PLC2
|
|
arc: N1_V02N0601 S3_V06N0303
|
|
arc: N3_V06N0303 E3_H06W0303
|
|
|
|
.tile R31C36:PLC2
|
|
arc: N1_V02N0001 N3_V06S0003
|
|
arc: CE2 E1_H02W0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: LSR1 H02W0501
|
|
arc: M5 H02W0001
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR2 LSR1
|
|
arc: W3_H06W0303 Q5
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R31C37:PLC2
|
|
arc: N1_V02N0101 N3_V06S0103
|
|
arc: N1_V02N0201 S1_V02N0201
|
|
arc: N1_V02N0701 N3_V06S0203
|
|
arc: N3_V06N0003 S3_V06N0003
|
|
arc: W1_H02W0001 N1_V02S0001
|
|
arc: W1_H02W0501 V02N0501
|
|
|
|
.tile R31C38:PLC2
|
|
arc: W1_H02W0101 N1_V02S0101
|
|
|
|
.tile R31C3:PLC2
|
|
arc: S3_V06S0003 H06W0003
|
|
arc: W1_H02W0701 V06S0203
|
|
|
|
.tile R31C40:PLC2
|
|
arc: N3_V06N0003 S3_V06N0303
|
|
|
|
.tile R31C41:PLC2
|
|
arc: N3_V06N0003 S3_V06N0303
|
|
arc: N3_V06N0103 S3_V06N0003
|
|
arc: W3_H06W0303 E3_H06W0203
|
|
|
|
.tile R31C43:PLC2
|
|
arc: N3_V06N0003 S3_V06N0303
|
|
|
|
.tile R31C45:PLC2
|
|
arc: N3_V06N0003 S3_V06N0303
|
|
|
|
.tile R31C46:PLC2
|
|
arc: N3_V06N0303 S3_V06N0203
|
|
|
|
.tile R31C47:PLC2
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
|
|
.tile R31C53:PLC2
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
|
|
.tile R31C59:PLC2
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
|
|
.tile R31C65:PLC2
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
|
|
.tile R31C6:PLC2
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
|
|
.tile R31C71:PLC2
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
|
|
.tile R31C77:PLC2
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
|
|
.tile R31C83:PLC2
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
|
|
.tile R31C87:PLC2
|
|
arc: E1_H02E0701 N1_V01S0100
|
|
|
|
.tile R32C10:PLC2
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
|
|
.tile R32C13:PLC2
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
|
|
.tile R32C16:PLC2
|
|
arc: N1_V02N0301 S1_V02N0201
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
|
|
.tile R32C19:PLC2
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
|
|
.tile R32C22:PLC2
|
|
arc: N3_V06N0103 S3_V06N0103
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
|
|
.tile R32C25:PLC2
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: E3_H06E0203 V06N0203
|
|
arc: N3_V06N0003 S3_V06N0003
|
|
|
|
.tile R32C27:PLC2
|
|
arc: N3_V06N0003 S3_V06N0003
|
|
|
|
.tile R32C28:PLC2
|
|
arc: H00R0000 V02S0401
|
|
arc: H00R0100 H02W0701
|
|
arc: N1_V02N0101 H06E0103
|
|
arc: V00B0000 V02N0001
|
|
arc: V00T0000 V02S0601
|
|
arc: CE0 H00R0100
|
|
arc: CE3 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: LSR0 V00B0000
|
|
arc: M1 H00R0000
|
|
arc: M6 V00T0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR3 LSR0
|
|
arc: W3_H06W0103 Q1
|
|
arc: W3_H06W0303 Q6
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R32C29:PLC2
|
|
arc: N1_V02N0201 S3_V06N0103
|
|
arc: N1_V02N0401 S1_V02N0101
|
|
arc: N3_V06N0303 E3_H06W0303
|
|
arc: W1_H02W0701 V06S0203
|
|
|
|
.tile R32C31:PLC2
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
|
|
.tile R32C34:PLC2
|
|
arc: N1_V02N0201 S1_V02N0701
|
|
|
|
.tile R32C35:PLC2
|
|
arc: N1_V02N0101 S1_V02N0001
|
|
arc: N1_V02N0301 S3_V06N0003
|
|
arc: N3_V06N0003 S3_V06N0303
|
|
arc: N3_V06N0303 S3_V06N0203
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
|
|
.tile R32C37:PLC2
|
|
arc: N1_V02N0501 W3_H06E0303
|
|
arc: N1_V02N0601 W3_H06E0303
|
|
arc: N3_V06N0203 S3_V06N0103
|
|
|
|
.tile R32C41:PLC2
|
|
arc: W3_H06W0303 E3_H06W0203
|
|
|
|
.tile R32C42:PLC2
|
|
arc: N3_V06N0103 S1_V02N0201
|
|
|
|
.tile R32C43:PLC2
|
|
arc: N1_V02N0301 S1_V02N0201
|
|
arc: N3_V06N0303 S3_V06N0303
|
|
|
|
.tile R32C45:PLC2
|
|
arc: N3_V06N0103 S3_V06N0103
|
|
|
|
.tile R32C47:PLC2
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
|
|
.tile R32C4:PLC2
|
|
arc: S3_V06S0203 E3_H06W0203
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
|
|
.tile R32C53:PLC2
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
|
|
.tile R32C59:PLC2
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
|
|
.tile R32C65:PLC2
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
|
|
.tile R32C71:PLC2
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
|
|
.tile R32C77:PLC2
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
|
|
.tile R32C7:PLC2
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
|
|
.tile R32C83:PLC2
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
|
|
.tile R33C28:PLC2
|
|
arc: N1_V02N0001 S1_V02N0001
|
|
arc: N1_V02N0101 S1_V02N0001
|
|
|
|
.tile R33C37:PLC2
|
|
arc: N1_V02N0201 S1_V02N0201
|
|
|
|
.tile R33C3:PLC2
|
|
arc: V01S0100 N3_V06S0303
|
|
|
|
.tile R35C13:PLC2
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
|
|
.tile R35C16:PLC2
|
|
arc: N3_V06N0303 S3_V06N0203
|
|
|
|
.tile R35C19:PLC2
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
arc: N3_V06N0003 S3_V06N0303
|
|
|
|
.tile R35C22:PLC2
|
|
arc: N3_V06N0103 S3_V06N0103
|
|
arc: N3_V06N0203 H06E0203
|
|
arc: N3_V06N0303 S3_V06N0203
|
|
|
|
.tile R35C25:PLC2
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
arc: N3_V06N0103 S3_V06N0003
|
|
arc: N3_V06N0203 S3_V06N0103
|
|
arc: N3_V06N0303 S3_V06N0203
|
|
|
|
.tile R35C28:PLC2
|
|
arc: N1_V02N0001 S3_V06N0003
|
|
|
|
.tile R35C31:PLC2
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: N3_V06N0203 S3_V06N0103
|
|
arc: N3_V06N0303 S3_V06N0203
|
|
|
|
.tile R35C32:PLC2
|
|
arc: N3_V06N0303 S3_V06N0303
|
|
|
|
.tile R35C34:PLC2
|
|
arc: N3_V06N0103 S3_V06N0103
|
|
arc: N3_V06N0203 S3_V06N0203
|
|
|
|
.tile R35C35:PLC2
|
|
arc: N3_V06N0303 S3_V06N0203
|
|
|
|
.tile R35C37:PLC2
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: N1_V02N0201 S3_V06N0103
|
|
arc: N3_V06N0103 S3_V06N0103
|
|
arc: N3_V06N0203 S3_V06N0103
|
|
|
|
.tile R35C3:PLC2
|
|
arc: W1_H02W0701 N3_V06S0203
|
|
|
|
.tile R35C40:PLC2
|
|
arc: N3_V06N0103 S3_V06N0103
|
|
|
|
.tile R35C41:PLC2
|
|
arc: N3_V06N0003 E3_H06W0003
|
|
|
|
.tile R35C43:PLC2
|
|
arc: N3_V06N0103 W3_H06E0103
|
|
arc: N3_V06N0203 S3_V06N0103
|
|
arc: N3_V06N0303 S3_V06N0203
|
|
|
|
.tile R35C44:PLC2
|
|
arc: N3_V06N0003 S3_V06N0003
|
|
|
|
.tile R35C45:PLC2
|
|
arc: N3_V06N0003 S3_V06N0003
|
|
|
|
.tile R35C47:PLC2
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
|
|
.tile R35C53:PLC2
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
|
|
.tile R35C59:PLC2
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
|
|
.tile R35C65:PLC2
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
|
|
.tile R35C71:PLC2
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arc: W3_H06W0003 E3_H06W0303
|
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.tile R35C77:PLC2
|
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arc: W3_H06W0303 E3_H06W0303
|
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.tile R35C7:PLC2
|
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arc: E3_H06E0003 W3_H06E0303
|
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arc: E3_H06E0103 W3_H06E0003
|
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.tile R35C83:PLC2
|
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arc: W3_H06W0303 E3_H06W0303
|
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.tile R36C13:PLC2
|
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arc: E3_H06E0003 W3_H06E0003
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.tile R36C19:PLC2
|
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arc: E3_H06E0003 W3_H06E0003
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.tile R36C25:PLC2
|
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arc: E3_H06E0103 W3_H06E0003
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.tile R36C28:PLC2
|
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arc: N3_V06N0103 H06E0103
|
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.tile R36C35:PLC2
|
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arc: N3_V06N0203 S1_V02N0401
|
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.tile R36C3:PLC2
|
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arc: S3_V06S0203 N3_V06S0103
|
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.tile R36C7:PLC2
|
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arc: E3_H06E0003 W3_H06E0303
|
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.tile R36C88:PLC2
|
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arc: S3_V06S0203 N3_V06S0203
|
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.tile R37C13:PLC2
|
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arc: E3_H06E0003 W3_H06E0003
|
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.tile R37C19:PLC2
|
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arc: E3_H06E0003 W3_H06E0003
|
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.tile R37C25:PLC2
|
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arc: E3_H06E0003 W3_H06E0003
|
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arc: N3_V06N0303 S3_V06N0203
|
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.tile R37C29:PLC2
|
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arc: N3_V06N0003 S3_V06N0303
|
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arc: N3_V06N0103 S3_V06N0003
|
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.tile R37C31:PLC2
|
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arc: E3_H06E0003 W3_H06E0003
|
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arc: N3_V06N0103 S3_V06N0103
|
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.tile R37C35:PLC2
|
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arc: N3_V06N0303 E3_H06W0303
|
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.tile R37C37:PLC2
|
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arc: N3_V06N0003 W3_H06E0003
|
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.tile R37C3:PLC2
|
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arc: S3_V06S0003 N3_V06S0003
|
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.tile R37C40:PLC2
|
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arc: N3_V06N0303 S3_V06N0203
|
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.tile R37C41:PLC2
|
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arc: N3_V06N0003 S3_V06N0303
|
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arc: N3_V06N0303 S3_V06N0203
|
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arc: W3_H06W0303 E3_H06W0303
|
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.tile R37C43:PLC2
|
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arc: N3_V06N0303 S3_V06N0203
|
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.tile R37C45:PLC2
|
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arc: N3_V06N0303 S3_V06N0203
|
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.tile R37C46:PLC2
|
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arc: N3_V06N0203 E3_H06W0203
|
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.tile R37C47:PLC2
|
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arc: W3_H06W0303 E3_H06W0203
|
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.tile R37C52:PLC2
|
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arc: W3_H06W0203 E3_H06W0103
|
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.tile R37C53:PLC2
|
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arc: W3_H06W0203 E3_H06W0103
|
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.tile R37C58:PLC2
|
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arc: W3_H06W0103 E3_H06W0103
|
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.tile R37C59:PLC2
|
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arc: W3_H06W0103 E3_H06W0103
|
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.tile R37C64:PLC2
|
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arc: W3_H06W0103 E3_H06W0103
|
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.tile R37C65:PLC2
|
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arc: W3_H06W0103 E3_H06W0103
|
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.tile R37C70:PLC2
|
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arc: W3_H06W0103 E3_H06W0003
|
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.tile R37C71:PLC2
|
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arc: W3_H06W0103 E3_H06W0003
|
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.tile R37C76:PLC2
|
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arc: W3_H06W0003 E3_H06W0003
|
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.tile R37C77:PLC2
|
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arc: W3_H06W0003 E3_H06W0003
|
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.tile R37C7:PLC2
|
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arc: E3_H06E0003 W3_H06E0303
|
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.tile R37C82:PLC2
|
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arc: W3_H06W0003 E3_H06W0303
|
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.tile R37C83:PLC2
|
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arc: W3_H06W0003 E3_H06W0303
|
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.tile R37C88:PLC2
|
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arc: W3_H06W0303 E1_H01W0100
|
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.tile R38C13:PLC2
|
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arc: E3_H06E0303 W3_H06E0303
|
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.tile R38C19:PLC2
|
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arc: E3_H06E0003 W3_H06E0303
|
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.tile R38C22:PLC2
|
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arc: N3_V06N0103 S3_V06N0103
|
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.tile R38C25:PLC2
|
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arc: N3_V06N0003 W3_H06E0003
|
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.tile R38C27:PLC2
|
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arc: N3_V06N0003 S3_V06N0003
|
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.tile R38C29:PLC2
|
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arc: N3_V06N0103 S3_V06N0103
|
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.tile R38C2:PLC2
|
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arc: W1_H02W0501 E1_H02W0401
|
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.tile R38C35:PLC2
|
|
arc: N1_V02N0401 S3_V06N0203
|
|
arc: N3_V06N0003 S3_V06N0003
|
|
arc: N3_V06N0203 E3_H06W0203
|
|
arc: N3_V06N0303 S3_V06N0303
|
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|
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.tile R38C37:PLC2
|
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arc: N3_V06N0103 S3_V06N0003
|
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|
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.tile R38C41:PLC2
|
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arc: W3_H06W0203 E3_H06W0103
|
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.tile R38C43:PLC2
|
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arc: N3_V06N0303 S3_V06N0203
|
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.tile R38C45:PLC2
|
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arc: N3_V06N0103 E3_H06W0103
|
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.tile R38C47:PLC2
|
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arc: W3_H06W0103 E3_H06W0103
|
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.tile R38C4:PLC2
|
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arc: W1_H02W0401 N3_V06S0203
|
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.tile R38C51:PLC2
|
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arc: W3_H06W0103 E3_H06W0003
|
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.tile R38C53:PLC2
|
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arc: W3_H06W0103 E3_H06W0003
|
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.tile R38C57:PLC2
|
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arc: W3_H06W0003 E3_H06W0303
|
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.tile R38C59:PLC2
|
|
arc: W3_H06W0003 E3_H06W0003
|
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.tile R38C63:PLC2
|
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arc: W3_H06W0303 E3_H06W0303
|
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|
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.tile R38C65:PLC2
|
|
arc: W3_H06W0003 E3_H06W0003
|
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.tile R38C69:PLC2
|
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arc: W3_H06W0303 E3_H06W0203
|
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|
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.tile R38C71:PLC2
|
|
arc: W3_H06W0003 E3_H06W0303
|
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.tile R38C75:PLC2
|
|
arc: W3_H06W0203 E3_H06W0203
|
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.tile R38C77:PLC2
|
|
arc: W3_H06W0303 E3_H06W0303
|
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.tile R38C7:PLC2
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
|
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.tile R38C81:PLC2
|
|
arc: W3_H06W0203 E3_H06W0203
|
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.tile R38C83:PLC2
|
|
arc: W3_H06W0303 E3_H06W0303
|
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|
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.tile R38C87:PLC2
|
|
arc: W3_H06W0203 E1_H02W0701
|
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|
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.tile R3C10:PLC2
|
|
arc: N1_V02N0501 S3_V06N0303
|
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|
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.tile R3C11:PLC2
|
|
arc: N1_V02N0701 H06W0203
|
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|
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.tile R3C13:PLC2
|
|
arc: N1_V02N0501 S1_V02N0401
|
|
|
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.tile R3C14:PLC2
|
|
arc: W3_H06W0203 S3_V06N0203
|
|
|
|
.tile R3C15:PLC2
|
|
arc: N1_V02N0701 S1_V02N0701
|
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|
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.tile R3C18:PLC2
|
|
arc: N1_V02N0501 S3_V06N0303
|
|
|
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.tile R3C27:PLC2
|
|
arc: S3_V06S0003 N1_V02S0001
|
|
|
|
.tile R3C57:PLC2
|
|
arc: N1_V02N0701 S3_V06N0203
|
|
|
|
.tile R3C60:PLC2
|
|
arc: N1_V02N0501 S3_V06N0303
|
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|
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.tile R3C64:PLC2
|
|
arc: N1_V02N0501 S1_V02N0401
|
|
|
|
.tile R40C13:PLC2
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
|
|
.tile R40C16:PLC2
|
|
arc: N3_V06N0103 S3_V06N0103
|
|
|
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.tile R40C18:PLC2
|
|
arc: N3_V06N0303 S3_V06N0303
|
|
|
|
.tile R40C19:PLC2
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
|
|
.tile R40C22:PLC2
|
|
arc: N3_V06N0003 S3_V06N0303
|
|
|
|
.tile R40C23:PLC2
|
|
arc: N3_V06N0203 S3_V06N0103
|
|
|
|
.tile R40C25:PLC2
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
arc: N3_V06N0203 S3_V06N0103
|
|
arc: N3_V06N0303 S3_V06N0303
|
|
|
|
.tile R40C28:PLC2
|
|
arc: N3_V06N0003 H06E0003
|
|
arc: N3_V06N0303 H06E0303
|
|
|
|
.tile R40C29:PLC2
|
|
arc: N3_V06N0003 S3_V06N0003
|
|
|
|
.tile R40C34:PLC2
|
|
arc: N3_V06N0003 E3_H06W0003
|
|
arc: N3_V06N0103 S3_V06N0103
|
|
arc: N3_V06N0203 S3_V06N0203
|
|
|
|
.tile R40C35:PLC2
|
|
arc: N3_V06N0003 E3_H06W0003
|
|
arc: N3_V06N0103 S3_V06N0103
|
|
arc: N3_V06N0303 S3_V06N0303
|
|
|
|
.tile R40C36:PLC2
|
|
arc: N3_V06N0103 S3_V06N0003
|
|
arc: N3_V06N0203 S3_V06N0103
|
|
|
|
.tile R40C40:PLC2
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
|
|
.tile R40C41:PLC2
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
|
|
.tile R40C42:PLC2
|
|
arc: N3_V06N0003 S3_V06N0303
|
|
arc: N3_V06N0103 S3_V06N0103
|
|
|
|
.tile R40C43:PLC2
|
|
arc: N3_V06N0103 S3_V06N0103
|
|
arc: N3_V06N0203 S3_V06N0203
|
|
|
|
.tile R40C44:PLC2
|
|
arc: N3_V06N0203 H06W0203
|
|
|
|
.tile R40C46:PLC2
|
|
arc: W3_H06W0303 E3_H06W0203
|
|
|
|
.tile R40C47:PLC2
|
|
arc: N3_V06N0203 S3_V06N0203
|
|
arc: W3_H06W0203 E3_H06W0203
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
|
|
.tile R40C52:PLC2
|
|
arc: W3_H06W0203 E3_H06W0203
|
|
|
|
.tile R40C53:PLC2
|
|
arc: W3_H06W0203 E3_H06W0203
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
|
|
.tile R40C58:PLC2
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
|
|
.tile R40C59:PLC2
|
|
arc: W3_H06W0203 E3_H06W0203
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
|
|
.tile R40C64:PLC2
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
|
|
.tile R40C65:PLC2
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
arc: W3_H06W0303 E3_H06W0203
|
|
|
|
.tile R40C70:PLC2
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
|
|
.tile R40C71:PLC2
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
arc: W3_H06W0203 E3_H06W0203
|
|
|
|
.tile R40C76:PLC2
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
|
|
.tile R40C77:PLC2
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
|
|
.tile R40C7:PLC2
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
|
|
.tile R40C82:PLC2
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
|
|
.tile R40C83:PLC2
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
|
|
.tile R40C87:PLC2
|
|
arc: S3_V06S0303 N3_V06S0303
|
|
|
|
.tile R40C88:PLC2
|
|
arc: W3_H06W0303 E1_H01W0100
|
|
|
|
.tile R41C13:PLC2
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
|
|
.tile R41C16:PLC2
|
|
arc: N3_V06N0203 S3_V06N0203
|
|
|
|
.tile R41C19:PLC2
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
arc: N3_V06N0303 S3_V06N0203
|
|
|
|
.tile R41C22:PLC2
|
|
arc: N3_V06N0103 S3_V06N0003
|
|
arc: N3_V06N0203 S3_V06N0103
|
|
|
|
.tile R41C25:PLC2
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
arc: N3_V06N0003 W3_H06E0003
|
|
arc: N3_V06N0103 S3_V06N0003
|
|
arc: N3_V06N0203 S3_V06N0103
|
|
|
|
.tile R41C28:PLC2
|
|
arc: N3_V06N0003 S3_V06N0003
|
|
|
|
.tile R41C31:PLC2
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: N3_V06N0103 S3_V06N0103
|
|
arc: N3_V06N0203 W3_H06E0203
|
|
|
|
.tile R41C32:PLC2
|
|
arc: N3_V06N0303 S3_V06N0303
|
|
|
|
.tile R41C34:PLC2
|
|
arc: N3_V06N0103 S3_V06N0003
|
|
arc: N3_V06N0203 S3_V06N0103
|
|
|
|
.tile R41C35:PLC2
|
|
arc: N3_V06N0203 S3_V06N0103
|
|
|
|
.tile R41C37:PLC2
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: N3_V06N0103 S3_V06N0003
|
|
|
|
.tile R41C40:PLC2
|
|
arc: N3_V06N0103 S3_V06N0103
|
|
|
|
.tile R41C43:PLC2
|
|
arc: N3_V06N0103 W3_H06E0103
|
|
arc: N3_V06N0203 S3_V06N0103
|
|
|
|
.tile R41C44:PLC2
|
|
arc: N3_V06N0003 H06W0003
|
|
|
|
.tile R41C45:PLC2
|
|
arc: N3_V06N0003 E3_H06W0003
|
|
|
|
.tile R41C47:PLC2
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
|
|
.tile R41C51:PLC2
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
|
|
.tile R41C53:PLC2
|
|
arc: W3_H06W0303 E3_H06W0203
|
|
|
|
.tile R41C57:PLC2
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
|
|
.tile R41C59:PLC2
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
|
|
.tile R41C63:PLC2
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
|
|
.tile R41C65:PLC2
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
|
|
.tile R41C69:PLC2
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
|
|
.tile R41C71:PLC2
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
|
|
.tile R41C75:PLC2
|
|
arc: W3_H06W0303 E3_H06W0203
|
|
|
|
.tile R41C77:PLC2
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
|
|
.tile R41C7:PLC2
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
|
|
.tile R41C81:PLC2
|
|
arc: W3_H06W0203 E3_H06W0203
|
|
|
|
.tile R41C83:PLC2
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
|
|
.tile R41C87:PLC2
|
|
arc: W3_H06W0203 E1_H02W0701
|
|
|
|
.tile R42C3:PLC2
|
|
arc: S3_V06S0303 N3_V06S0203
|
|
|
|
.tile R42C88:PLC2
|
|
arc: S3_V06S0303 N3_V06S0203
|
|
|
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.tile R43C13:PLC2
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arc: E3_H06E0003 W3_H06E0003
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.tile R43C19:PLC2
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arc: E3_H06E0003 W3_H06E0003
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.tile R43C25:PLC2
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arc: E3_H06E0103 W3_H06E0003
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arc: N3_V06N0203 S3_V06N0103
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.tile R43C29:PLC2
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arc: N3_V06N0003 S3_V06N0003
|
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arc: N3_V06N0303 S3_V06N0303
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.tile R43C31:PLC2
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arc: N3_V06N0103 W3_H06E0103
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.tile R43C3:PLC2
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arc: S3_V06S0103 N3_V06S0003
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.tile R43C40:PLC2
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arc: N3_V06N0203 S3_V06N0103
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.tile R43C41:PLC2
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arc: N3_V06N0203 E3_H06W0203
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arc: N3_V06N0303 S3_V06N0303
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.tile R43C43:PLC2
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arc: N3_V06N0203 S3_V06N0203
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.tile R43C45:PLC2
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arc: N3_V06N0203 S3_V06N0103
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.tile R43C47:PLC2
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arc: W3_H06W0203 E3_H06W0103
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.tile R43C53:PLC2
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arc: W3_H06W0103 E3_H06W0103
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.tile R43C59:PLC2
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arc: W3_H06W0103 E3_H06W0003
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.tile R43C65:PLC2
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arc: W3_H06W0003 E3_H06W0303
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.tile R43C71:PLC2
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arc: W3_H06W0303 E3_H06W0303
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.tile R43C77:PLC2
|
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arc: W3_H06W0303 E3_H06W0303
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.tile R43C7:PLC2
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arc: E3_H06E0003 W3_H06E0303
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.tile R43C83:PLC2
|
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arc: W3_H06W0303 E3_H06W0303
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.tile R44C13:PLC2
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arc: E3_H06E0003 W3_H06E0003
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.tile R44C19:PLC2
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arc: E3_H06E0103 W3_H06E0003
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.tile R44C22:PLC2
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arc: N3_V06N0103 H06E0103
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.tile R44C27:PLC2
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arc: N3_V06N0003 S3_V06N0303
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.tile R44C29:PLC2
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arc: N3_V06N0103 S3_V06N0103
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.tile R44C35:PLC2
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arc: N3_V06N0003 S3_V06N0303
|
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arc: N3_V06N0203 S3_V06N0203
|
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arc: N3_V06N0303 E3_H06W0303
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.tile R44C37:PLC2
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arc: N3_V06N0003 H06W0003
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.tile R44C40:PLC2
|
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arc: W3_H06W0003 E3_H06W0303
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.tile R44C41:PLC2
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arc: W3_H06W0303 E3_H06W0203
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.tile R44C43:PLC2
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arc: N3_V06N0203 S3_V06N0203
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.tile R44C46:PLC2
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arc: W3_H06W0303 E3_H06W0303
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.tile R44C47:PLC2
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arc: W3_H06W0203 E3_H06W0203
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.tile R44C52:PLC2
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arc: W3_H06W0303 E3_H06W0303
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.tile R44C53:PLC2
|
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arc: W3_H06W0203 E3_H06W0103
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.tile R44C58:PLC2
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arc: W3_H06W0303 E3_H06W0203
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.tile R44C59:PLC2
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arc: W3_H06W0103 E3_H06W0103
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.tile R44C64:PLC2
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arc: W3_H06W0203 E3_H06W0103
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.tile R44C65:PLC2
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arc: W3_H06W0103 E3_H06W0103
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.tile R44C70:PLC2
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arc: W3_H06W0103 E3_H06W0103
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.tile R44C71:PLC2
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arc: W3_H06W0103 E3_H06W0003
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.tile R44C76:PLC2
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arc: W3_H06W0103 E3_H06W0003
|
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.tile R44C77:PLC2
|
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arc: W3_H06W0003 E3_H06W0303
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.tile R44C7:PLC2
|
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arc: E3_H06E0003 W3_H06E0303
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.tile R44C82:PLC2
|
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arc: W3_H06W0003 E3_H06W0303
|
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.tile R44C83:PLC2
|
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arc: W3_H06W0303 E3_H06W0303
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.tile R44C88:PLC2
|
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arc: W3_H06W0303 E1_H01W0100
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.tile R47C13:PLC2
|
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arc: E3_H06E0003 W3_H06E0003
|
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.tile R47C16:PLC2
|
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arc: N3_V06N0203 S3_V06N0103
|
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.tile R47C19:PLC2
|
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arc: E3_H06E0103 W3_H06E0003
|
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arc: N3_V06N0203 S3_V06N0203
|
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.tile R47C22:PLC2
|
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arc: N3_V06N0003 S3_V06N0303
|
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arc: N3_V06N0103 H06E0103
|
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.tile R47C25:PLC2
|
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arc: N3_V06N0003 S3_V06N0303
|
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arc: N3_V06N0103 S3_V06N0003
|
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.tile R47C28:PLC2
|
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arc: N3_V06N0003 S3_V06N0303
|
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.tile R47C31:PLC2
|
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arc: N3_V06N0103 S3_V06N0003
|
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.tile R47C32:PLC2
|
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arc: N3_V06N0303 H06W0303
|
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.tile R47C34:PLC2
|
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arc: N3_V06N0003 S3_V06N0003
|
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arc: N3_V06N0103 E3_H06W0103
|
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.tile R47C35:PLC2
|
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arc: N3_V06N0103 S3_V06N0003
|
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arc: W3_H06W0303 E3_H06W0203
|
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.tile R47C37:PLC2
|
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arc: N3_V06N0003 S3_V06N0003
|
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.tile R47C40:PLC2
|
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arc: N3_V06N0103 S3_V06N0003
|
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arc: W3_H06W0103 E3_H06W0003
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.tile R47C41:PLC2
|
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arc: W3_H06W0203 E3_H06W0103
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.tile R47C43:PLC2
|
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arc: N3_V06N0103 S3_V06N0003
|
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.tile R47C46:PLC2
|
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arc: W3_H06W0003 E3_H06W0303
|
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.tile R47C47:PLC2
|
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arc: W3_H06W0103 E3_H06W0003
|
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.tile R47C52:PLC2
|
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arc: W3_H06W0303 E3_H06W0203
|
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.tile R47C53:PLC2
|
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arc: W3_H06W0003 E3_H06W0003
|
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.tile R47C58:PLC2
|
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arc: W3_H06W0203 E3_H06W0103
|
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.tile R47C59:PLC2
|
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arc: W3_H06W0003 E3_H06W0003
|
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.tile R47C64:PLC2
|
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arc: W3_H06W0103 E3_H06W0003
|
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.tile R47C65:PLC2
|
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arc: W3_H06W0003 E3_H06W0303
|
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.tile R47C70:PLC2
|
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arc: W3_H06W0003 E3_H06W0003
|
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.tile R47C71:PLC2
|
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arc: W3_H06W0303 E3_H06W0303
|
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.tile R47C76:PLC2
|
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arc: W3_H06W0003 E3_H06W0003
|
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.tile R47C77:PLC2
|
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arc: W3_H06W0303 E3_H06W0303
|
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.tile R47C7:PLC2
|
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arc: E3_H06E0003 W3_H06E0303
|
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.tile R47C82:PLC2
|
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arc: W3_H06W0003 E3_H06W0003
|
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.tile R47C83:PLC2
|
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arc: W3_H06W0303 E3_H06W0303
|
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.tile R47C88:PLC2
|
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arc: W3_H06W0003 E1_H01W0000
|
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.tile R48C3:PLC2
|
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arc: S3_V06S0303 N3_V06S0303
|
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.tile R48C88:PLC2
|
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arc: E1_H02E0501 N3_V06S0303
|
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.tile R49C13:PLC2
|
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arc: E3_H06E0103 W3_H06E0003
|
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.tile R49C19:PLC2
|
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arc: E3_H06E0103 W3_H06E0103
|
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.tile R49C25:PLC2
|
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arc: N3_V06N0103 W3_H06E0103
|
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.tile R49C29:PLC2
|
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arc: N3_V06N0003 E3_H06W0003
|
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arc: N3_V06N0303 S3_V06N0203
|
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.tile R49C35:PLC2
|
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arc: W3_H06W0003 E3_H06W0303
|
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.tile R49C3:PLC2
|
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arc: S3_V06S0203 N3_V06S0103
|
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.tile R49C40:PLC2
|
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arc: N3_V06N0103 S3_V06N0103
|
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.tile R49C41:PLC2
|
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arc: N3_V06N0303 S3_V06N0203
|
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arc: W3_H06W0303 E3_H06W0203
|
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.tile R49C43:PLC2
|
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arc: N3_V06N0203 S3_V06N0103
|
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.tile R49C45:PLC2
|
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arc: N3_V06N0103 E3_H06W0103
|
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.tile R49C47:PLC2
|
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arc: W3_H06W0203 E3_H06W0203
|
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.tile R49C51:PLC2
|
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arc: W3_H06W0103 E3_H06W0103
|
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.tile R49C53:PLC2
|
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arc: W3_H06W0203 E3_H06W0203
|
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.tile R49C57:PLC2
|
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arc: W3_H06W0103 E3_H06W0003
|
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.tile R49C59:PLC2
|
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arc: W3_H06W0203 E3_H06W0203
|
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.tile R49C63:PLC2
|
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arc: W3_H06W0003 E3_H06W0003
|
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.tile R49C65:PLC2
|
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arc: W3_H06W0203 E3_H06W0103
|
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.tile R49C69:PLC2
|
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arc: W3_H06W0003 E3_H06W0303
|
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.tile R49C71:PLC2
|
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arc: W3_H06W0103 E3_H06W0003
|
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.tile R49C75:PLC2
|
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arc: W3_H06W0303 E3_H06W0203
|
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.tile R49C77:PLC2
|
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arc: W3_H06W0003 E3_H06W0303
|
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.tile R49C7:PLC2
|
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arc: E3_H06E0003 W3_H06E0303
|
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.tile R49C81:PLC2
|
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arc: W3_H06W0203 E3_H06W0203
|
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.tile R49C83:PLC2
|
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arc: W3_H06W0303 E3_H06W0303
|
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.tile R49C87:PLC2
|
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arc: W3_H06W0203 E1_H02W0701
|
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.tile R4C19:PLC2
|
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arc: N3_V06N0303 S1_V02N0501
|
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.tile R4C24:PLC2
|
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arc: N3_V06N0303 S3_V06N0303
|
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.tile R4C70:PLC2
|
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arc: N3_V06N0203 S1_V02N0401
|
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.tile R50C13:PLC2
|
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arc: E3_H06E0103 W3_H06E0003
|
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.tile R50C15:PLC2
|
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arc: E3_H06E0303 W3_H06E0203
|
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.tile R50C19:PLC2
|
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arc: E3_H06E0103 W3_H06E0103
|
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.tile R50C21:PLC2
|
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arc: E3_H06E0303 W3_H06E0303
|
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.tile R50C25:PLC2
|
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arc: E3_H06E0103 W3_H06E0103
|
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.tile R50C27:PLC2
|
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arc: N3_V06N0303 W3_H06E0303
|
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.tile R50C29:PLC2
|
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arc: N3_V06N0103 E3_H06W0103
|
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.tile R50C31:PLC2
|
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arc: E3_H06E0103 W3_H06E0103
|
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|
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.tile R50C35:PLC2
|
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arc: N3_V06N0203 S3_V06N0203
|
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arc: N3_V06N0303 S3_V06N0303
|
|
arc: W3_H06W0103 E3_H06W0103
|
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|
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.tile R50C37:PLC2
|
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arc: E3_H06E0203 W3_H06E0103
|
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.tile R50C3:PLC2
|
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arc: E3_H06E0203 W1_H02E0701
|
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.tile R50C41:PLC2
|
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arc: W3_H06W0103 E3_H06W0003
|
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.tile R50C43:PLC2
|
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arc: N3_V06N0203 W3_H06E0203
|
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.tile R50C47:PLC2
|
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arc: W3_H06W0003 E3_H06W0303
|
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.tile R50C53:PLC2
|
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arc: W3_H06W0303 E3_H06W0303
|
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.tile R50C59:PLC2
|
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arc: W3_H06W0303 E3_H06W0203
|
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.tile R50C65:PLC2
|
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arc: W3_H06W0203 E3_H06W0103
|
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.tile R50C71:PLC2
|
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arc: W3_H06W0103 E3_H06W0003
|
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.tile R50C77:PLC2
|
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arc: W3_H06W0003 E3_H06W0303
|
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.tile R50C7:PLC2
|
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arc: E3_H06E0003 W3_H06E0303
|
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|
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.tile R50C83:PLC2
|
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arc: W3_H06W0303 E3_H06W0303
|
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.tile R50C9:PLC2
|
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arc: E3_H06E0203 W3_H06E0203
|
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.tile R52C13:PLC2
|
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arc: E3_H06E0003 W3_H06E0303
|
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|
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.tile R52C16:PLC2
|
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arc: N3_V06N0103 S3_V06N0103
|
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|
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.tile R52C18:PLC2
|
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arc: N3_V06N0203 S3_V06N0203
|
|
|
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.tile R52C19:PLC2
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
|
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.tile R52C22:PLC2
|
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arc: N3_V06N0303 S3_V06N0303
|
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|
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.tile R52C23:PLC2
|
|
arc: N3_V06N0103 S3_V06N0103
|
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|
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.tile R52C25:PLC2
|
|
arc: N3_V06N0103 W3_H06E0103
|
|
arc: N3_V06N0303 S3_V06N0203
|
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|
|
.tile R52C34:PLC2
|
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arc: N3_V06N0203 S3_V06N0103
|
|
|
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.tile R52C35:PLC2
|
|
arc: N3_V06N0003 S3_V06N0303
|
|
arc: N3_V06N0303 S3_V06N0203
|
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|
|
.tile R52C36:PLC2
|
|
arc: N3_V06N0003 S3_V06N0003
|
|
arc: N3_V06N0303 S3_V06N0303
|
|
|
|
.tile R52C3:PLC2
|
|
arc: W1_H02W0701 V06S0203
|
|
|
|
.tile R52C42:PLC2
|
|
arc: N3_V06N0003 S3_V06N0303
|
|
arc: N3_V06N0203 S3_V06N0103
|
|
|
|
.tile R52C43:PLC2
|
|
arc: N3_V06N0103 S3_V06N0003
|
|
|
|
.tile R52C47:PLC2
|
|
arc: N3_V06N0203 E3_H06W0203
|
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|
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.tile R52C53:PLC2
|
|
arc: W3_H06W0203 E3_H06W0203
|
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|
|
.tile R52C59:PLC2
|
|
arc: W3_H06W0203 E3_H06W0103
|
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|
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.tile R52C65:PLC2
|
|
arc: W3_H06W0103 E3_H06W0003
|
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|
|
.tile R52C71:PLC2
|
|
arc: W3_H06W0003 E3_H06W0303
|
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|
|
.tile R52C77:PLC2
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
|
|
.tile R52C7:PLC2
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
|
|
.tile R52C83:PLC2
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
|
|
.tile R52C87:PLC2
|
|
arc: E1_H02E0501 N3_V06S0303
|
|
|
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.tile R53C13:PLC2
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
|
|
.tile R53C16:PLC2
|
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arc: N3_V06N0103 S3_V06N0103
|
|
|
|
.tile R53C19:PLC2
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: N3_V06N0203 S3_V06N0103
|
|
|
|
.tile R53C22:PLC2
|
|
arc: N3_V06N0303 S3_V06N0203
|
|
|
|
.tile R53C25:PLC2
|
|
arc: N3_V06N0003 W3_H06E0003
|
|
arc: N3_V06N0303 S3_V06N0203
|
|
|
|
.tile R53C28:PLC2
|
|
arc: N3_V06N0303 S3_V06N0303
|
|
|
|
.tile R53C31:PLC2
|
|
arc: N3_V06N0003 S3_V06N0303
|
|
|
|
.tile R53C34:PLC2
|
|
arc: N3_V06N0003 S3_V06N0303
|
|
|
|
.tile R53C35:PLC2
|
|
arc: N3_V06N0003 E3_H06W0003
|
|
|
|
.tile R53C37:PLC2
|
|
arc: N3_V06N0003 S3_V06N0303
|
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.tile R53C40:PLC2
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arc: N3_V06N0003 S3_V06N0003
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.tile R53C41:PLC2
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arc: W3_H06W0003 E3_H06W0303
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.tile R53C43:PLC2
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arc: N3_V06N0003 S3_V06N0003
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.tile R53C47:PLC2
|
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arc: W3_H06W0303 E3_H06W0303
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.tile R53C53:PLC2
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arc: W3_H06W0303 E3_H06W0203
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.tile R53C59:PLC2
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arc: W3_H06W0203 E3_H06W0203
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.tile R53C65:PLC2
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arc: W3_H06W0203 E3_H06W0103
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.tile R53C71:PLC2
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arc: W3_H06W0103 E3_H06W0003
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.tile R53C77:PLC2
|
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arc: W3_H06W0003 E3_H06W0303
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.tile R53C7:PLC2
|
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arc: E3_H06E0003 W3_H06E0303
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.tile R53C83:PLC2
|
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arc: W3_H06W0303 E3_H06W0303
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.tile R54C3:PLC2
|
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arc: V01S0100 N3_V06S0303
|
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.tile R55C13:PLC2
|
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arc: E3_H06E0003 W3_H06E0303
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.tile R55C19:PLC2
|
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arc: E3_H06E0003 W3_H06E0003
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.tile R55C25:PLC2
|
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arc: E3_H06E0003 W3_H06E0003
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.tile R55C29:PLC2
|
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arc: N3_V06N0203 E3_H06W0203
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.tile R55C31:PLC2
|
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arc: E3_H06E0103 W3_H06E0003
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.tile R55C35:PLC2
|
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arc: W3_H06W0203 E3_H06W0103
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.tile R55C37:PLC2
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arc: E3_H06E0103 W3_H06E0103
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.tile R55C3:PLC2
|
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arc: W1_H02W0701 N1_V01S0100
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.tile R55C40:PLC2
|
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arc: N3_V06N0103 E3_H06W0103
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.tile R55C41:PLC2
|
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arc: N3_V06N0203 S3_V06N0103
|
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arc: W3_H06W0103 E3_H06W0003
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.tile R55C43:PLC2
|
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arc: N3_V06N0103 W3_H06E0103
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.tile R55C46:PLC2
|
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arc: W3_H06W0103 E3_H06W0103
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.tile R55C47:PLC2
|
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arc: W3_H06W0003 E3_H06W0003
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.tile R55C52:PLC2
|
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arc: W3_H06W0103 E3_H06W0003
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.tile R55C53:PLC2
|
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arc: W3_H06W0003 E3_H06W0303
|
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.tile R55C58:PLC2
|
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arc: W3_H06W0003 E3_H06W0003
|
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.tile R55C59:PLC2
|
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arc: W3_H06W0303 E3_H06W0303
|
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.tile R55C64:PLC2
|
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arc: W3_H06W0003 E3_H06W0303
|
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.tile R55C65:PLC2
|
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arc: W3_H06W0303 E3_H06W0303
|
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.tile R55C70:PLC2
|
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arc: W3_H06W0303 E3_H06W0303
|
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.tile R55C71:PLC2
|
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arc: W3_H06W0303 E3_H06W0303
|
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.tile R55C76:PLC2
|
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arc: W3_H06W0303 E3_H06W0203
|
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.tile R55C77:PLC2
|
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arc: W3_H06W0303 E3_H06W0303
|
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.tile R55C7:PLC2
|
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arc: E3_H06E0303 W3_H06E0303
|
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.tile R55C82:PLC2
|
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arc: W3_H06W0203 E3_H06W0103
|
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.tile R55C83:PLC2
|
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arc: W3_H06W0303 E3_H06W0303
|
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.tile R55C88:PLC2
|
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arc: W3_H06W0103 E1_H01W0100
|
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.tile R56C35:PLC2
|
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arc: N3_V06N0203 S1_V02N0401
|
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arc: N3_V06N0303 E3_H06W0303
|
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.tile R56C41:PLC2
|
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arc: W3_H06W0303 E3_H06W0303
|
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.tile R56C47:PLC2
|
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arc: W3_H06W0303 E3_H06W0303
|
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.tile R56C53:PLC2
|
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arc: W3_H06W0303 E3_H06W0203
|
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.tile R56C59:PLC2
|
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arc: W3_H06W0203 E3_H06W0203
|
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.tile R56C65:PLC2
|
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arc: W3_H06W0203 E3_H06W0103
|
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.tile R56C71:PLC2
|
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arc: W3_H06W0103 E3_H06W0103
|
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.tile R56C77:PLC2
|
|
arc: W3_H06W0103 E3_H06W0003
|
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.tile R56C83:PLC2
|
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arc: W3_H06W0003 E3_H06W0303
|
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.tile R59C13:PLC2
|
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arc: E3_H06E0103 W3_H06E0003
|
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.tile R59C16:PLC2
|
|
arc: N3_V06N0103 H06E0103
|
|
|
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.tile R59C19:PLC2
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: N3_V06N0103 W3_H06E0103
|
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|
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.tile R59C22:PLC2
|
|
arc: N3_V06N0203 H06E0203
|
|
|
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.tile R59C25:PLC2
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
arc: N3_V06N0203 W3_H06E0203
|
|
|
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.tile R59C28:PLC2
|
|
arc: N3_V06N0303 H06E0303
|
|
|
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.tile R59C31:PLC2
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
arc: N3_V06N0303 W3_H06E0303
|
|
|
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.tile R59C34:PLC2
|
|
arc: N3_V06N0303 H06E0303
|
|
|
|
.tile R59C37:PLC2
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: N3_V06N0303 W3_H06E0303
|
|
|
|
.tile R59C40:PLC2
|
|
arc: N3_V06N0003 H06E0003
|
|
|
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.tile R59C43:PLC2
|
|
arc: N3_V06N0003 W3_H06E0003
|
|
|
|
.tile R59C7:PLC2
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
|
|
.tile R5C13:PLC2
|
|
arc: N1_V02N0401 S3_V06N0203
|
|
|
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.tile R5C15:PLC2
|
|
arc: N1_V02N0701 H06W0203
|
|
|
|
.tile R5C18:PLC2
|
|
arc: W3_H06W0203 S3_V06N0203
|
|
|
|
.tile R5C64:PLC2
|
|
arc: N1_V02N0401 S3_V06N0203
|
|
|
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.tile R61C41:PLC2
|
|
arc: N3_V06N0103 E3_H06W0103
|
|
|
|
.tile R61C47:PLC2
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
|
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.tile R61C53:PLC2
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
|
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.tile R61C59:PLC2
|
|
arc: W3_H06W0303 E3_H06W0203
|
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|
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.tile R61C65:PLC2
|
|
arc: W3_H06W0203 E3_H06W0203
|
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|
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.tile R61C71:PLC2
|
|
arc: W3_H06W0203 E3_H06W0103
|
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|
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.tile R61C77:PLC2
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
|
|
.tile R61C83:PLC2
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
|
|
.tile R64C11:PLC2
|
|
arc: E3_H06E0003 S3_V06N0003
|
|
|
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.tile R64C15:PLC2
|
|
arc: E3_H06E0003 S3_V06N0003
|
|
|
|
.tile R64C16:PLC2
|
|
arc: N3_V06N0003 S3_V06N0003
|
|
|
|
.tile R64C17:PLC2
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
|
|
.tile R64C18:PLC2
|
|
arc: N3_V06N0103 S3_V06N0003
|
|
|
|
.tile R64C21:PLC2
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
|
|
.tile R64C22:PLC2
|
|
arc: N3_V06N0203 S3_V06N0203
|
|
|
|
.tile R64C23:PLC2
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: N3_V06N0003 S3_V06N0003
|
|
|
|
.tile R64C25:PLC2
|
|
arc: N3_V06N0103 S3_V06N0003
|
|
|
|
.tile R64C27:PLC2
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
|
|
.tile R64C29:PLC2
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
|
|
.tile R64C33:PLC2
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
|
|
.tile R64C34:PLC2
|
|
arc: N3_V06N0103 S3_V06N0103
|
|
|
|
.tile R64C35:PLC2
|
|
arc: N3_V06N0103 S3_V06N0103
|
|
arc: N3_V06N0203 W3_H06E0203
|
|
|
|
.tile R64C36:PLC2
|
|
arc: N3_V06N0203 S3_V06N0103
|
|
arc: N3_V06N0303 S3_V06N0303
|
|
|
|
.tile R64C39:PLC2
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
|
|
.tile R64C42:PLC2
|
|
arc: N3_V06N0103 H06E0103
|
|
arc: N3_V06N0203 S3_V06N0203
|
|
|
|
.tile R64C43:PLC2
|
|
arc: N3_V06N0003 S3_V06N0003
|
|
|
|
.tile R6C19:PLC2
|
|
arc: N1_V02N0501 S3_V06N0303
|
|
|
|
.tile R6C70:PLC2
|
|
arc: N1_V02N0401 S3_V06N0203
|
|
|
|
.tile R7C18:PLC2
|
|
arc: S3_V06S0003 N3_V06S0303
|
|
|
|
.tile R7C21:PLC2
|
|
arc: S3_V06S0103 N3_V06S0103
|
|
|
|
.tile R7C22:PLC2
|
|
arc: S3_V06S0003 N3_V06S0003
|
|
arc: S3_V06S0103 N3_V06S0103
|
|
arc: S3_V06S0303 N3_V06S0303
|
|
|
|
.tile R7C23:PLC2
|
|
arc: S3_V06S0303 N3_V06S0303
|
|
|
|
.tile R7C24:PLC2
|
|
arc: S3_V06S0103 N3_V06S0003
|
|
|
|
.tile R7C25:PLC2
|
|
arc: S3_V06S0103 N3_V06S0003
|
|
|
|
.tile R7C26:PLC2
|
|
arc: S3_V06S0103 N3_V06S0003
|
|
|
|
.tile R7C27:PLC2
|
|
arc: S3_V06S0103 N3_V06S0003
|
|
arc: S3_V06S0203 N3_V06S0203
|
|
arc: S3_V06S0303 N3_V06S0303
|
|
|
|
.tile R7C28:PLC2
|
|
arc: S1_V02S0701 N3_V06S0203
|
|
arc: S3_V06S0103 N3_V06S0003
|
|
arc: S3_V06S0203 N3_V06S0103
|
|
arc: S3_V06S0303 N3_V06S0303
|
|
|
|
.tile R7C29:PLC2
|
|
arc: S3_V06S0103 N3_V06S0003
|
|
|
|
.tile R7C30:PLC2
|
|
arc: S3_V06S0003 N3_V06S0003
|
|
arc: S3_V06S0303 N3_V06S0303
|
|
|
|
.tile R7C31:PLC2
|
|
arc: S3_V06S0103 N3_V06S0003
|
|
arc: S3_V06S0303 N3_V06S0203
|
|
|
|
.tile R7C32:PLC2
|
|
arc: S3_V06S0003 N3_V06S0003
|
|
|
|
.tile R7C34:PLC2
|
|
arc: S3_V06S0003 N3_V06S0003
|
|
|
|
.tile R7C35:PLC2
|
|
arc: S3_V06S0003 N3_V06S0003
|
|
arc: S3_V06S0203 N3_V06S0103
|
|
arc: S3_V06S0303 N3_V06S0203
|
|
|
|
.tile R7C36:PLC2
|
|
arc: S3_V06S0003 N3_V06S0303
|
|
arc: S3_V06S0103 N3_V06S0003
|
|
arc: S3_V06S0203 N3_V06S0103
|
|
arc: S3_V06S0303 N3_V06S0203
|
|
|
|
.tile R7C37:PLC2
|
|
arc: N3_V06N0203 S1_V02N0401
|
|
arc: S3_V06S0103 N3_V06S0103
|
|
arc: S3_V06S0203 N3_V06S0203
|
|
|
|
.tile R7C41:PLC2
|
|
arc: S3_V06S0103 N3_V06S0003
|
|
|
|
.tile R7C42:PLC2
|
|
arc: S3_V06S0003 N3_V06S0303
|
|
arc: S3_V06S0103 N3_V06S0003
|
|
|
|
.tile R7C43:PLC2
|
|
arc: S3_V06S0203 N3_V06S0203
|
|
|
|
.tile R7C44:PLC2
|
|
arc: S3_V06S0003 N3_V06S0003
|
|
arc: S3_V06S0103 N3_V06S0103
|
|
arc: S3_V06S0303 N3_V06S0303
|
|
|
|
.tile R7C45:PLC2
|
|
arc: S3_V06S0003 N3_V06S0003
|
|
|
|
.tile R7C60:PLC2
|
|
arc: N3_V06N0303 S1_V02N0601
|
|
|
|
.tile R7C61:PLC2
|
|
arc: N3_V06N0303 S1_V02N0601
|
|
|
|
.tile R8C53:PLC2
|
|
arc: N3_V06N0303 S3_V06N0203
|
|
|
|
.tile R9C10:PLC2
|
|
arc: N3_V06N0303 S3_V06N0303
|
|
|
|
.tile R9C14:PLC2
|
|
arc: N3_V06N0203 S1_V02N0401
|
|
|
|
.tile R9C18:PLC2
|
|
arc: N3_V06N0303 S1_V02N0601
|
|
|
|
.tile R9C27:PLC2
|
|
arc: S3_V06S0103 N3_V06S0003
|
|
|
|
.tile R9C28:PLC2
|
|
arc: S3_V06S0203 N1_V02S0701
|
|
|
|
.tile R9C37:PLC2
|
|
arc: N1_V02N0401 S1_V02N0101
|
|
|
|
.tile R9C57:PLC2
|
|
arc: N3_V06N0203 S1_V02N0701
|
|
|
|
.tile R9C60:PLC2
|
|
arc: N1_V02N0601 S1_V02N0301
|
|
arc: N3_V06N0303 S1_V02N0501
|
|
|
|
.tile R9C61:PLC2
|
|
arc: N1_V02N0601 S1_V02N0301
|
|
|
|
.tile TAP_R20C31:TAP_DRIVE
|
|
arc: L_HPBX0000 G_VPTX0000
|
|
arc: R_HPBX0000 G_VPTX0000
|
|
|
|
.tile TAP_R20C51:TAP_DRIVE
|
|
arc: L_HPBX0000 G_VPTX0000
|
|
|
|
.tile TAP_R21C13:TAP_DRIVE
|
|
arc: R_HPBX0000 G_VPTX0000
|
|
|
|
.tile TAP_R21C31:TAP_DRIVE
|
|
arc: L_HPBX0000 G_VPTX0000
|
|
arc: R_HPBX0000 G_VPTX0000
|
|
|
|
.tile TAP_R21C51:TAP_DRIVE
|
|
arc: L_HPBX0000 G_VPTX0000
|
|
|
|
.tile TAP_R23C13:TAP_DRIVE
|
|
arc: R_HPBX0000 G_VPTX0000
|
|
|
|
.tile TAP_R23C31:TAP_DRIVE
|
|
arc: L_HPBX0000 G_VPTX0000
|
|
arc: R_HPBX0000 G_VPTX0000
|
|
|
|
.tile TAP_R23C51:TAP_DRIVE
|
|
arc: L_HPBX0000 G_VPTX0000
|
|
|
|
.tile TAP_R24C13:TAP_DRIVE
|
|
arc: R_HPBX0000 G_VPTX0000
|
|
|
|
.tile TAP_R24C31:TAP_DRIVE
|
|
arc: L_HPBX0000 G_VPTX0000
|
|
arc: R_HPBX0000 G_VPTX0000
|
|
|
|
.tile TAP_R24C51:TAP_DRIVE
|
|
arc: L_HPBX0000 G_VPTX0000
|
|
|
|
.tile TAP_R25C31:TAP_DRIVE
|
|
arc: L_HPBX0000 G_VPTX0000
|
|
arc: R_HPBX0000 G_VPTX0000
|
|
|
|
.tile TAP_R25C51:TAP_DRIVE
|
|
arc: L_HPBX0000 G_VPTX0000
|
|
|
|
.tile TAP_R26C31:TAP_DRIVE
|
|
arc: L_HPBX0000 G_VPTX0000
|
|
arc: R_HPBX0000 G_VPTX0000
|
|
|
|
.tile TAP_R26C51:TAP_DRIVE
|
|
arc: L_HPBX0000 G_VPTX0000
|
|
|
|
.tile TAP_R27C31:TAP_DRIVE
|
|
arc: L_HPBX0000 G_VPTX0000
|
|
arc: R_HPBX0000 G_VPTX0000
|
|
|
|
.tile TAP_R27C51:TAP_DRIVE
|
|
arc: L_HPBX0000 G_VPTX0000
|
|
|
|
.tile TAP_R28C31:TAP_DRIVE
|
|
arc: R_HPBX0000 G_VPTX0000
|
|
|
|
.tile TAP_R28C51:TAP_DRIVE
|
|
arc: L_HPBX0000 G_VPTX0000
|
|
|
|
.tile TAP_R29C31:TAP_DRIVE
|
|
arc: L_HPBX0000 G_VPTX0000
|
|
arc: R_HPBX0000 G_VPTX0000
|
|
|
|
.tile TAP_R30C31:TAP_DRIVE
|
|
arc: L_HPBX0000 G_VPTX0000
|
|
arc: R_HPBX0000 G_VPTX0000
|
|
|
|
.tile TAP_R31C31:TAP_DRIVE
|
|
arc: L_HPBX0000 G_VPTX0000
|
|
arc: R_HPBX0000 G_VPTX0000
|
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.tile TAP_R32C31:TAP_DRIVE
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arc: L_HPBX0000 G_VPTX0000
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.tile_group MIB_R22C42:MIB_DSP0 MIB_R22C42:MIB2_DSP0 MIB_R22C43:MIB_DSP1 MIB_R22C43:MIB2_DSP1 MIB_R22C44:MIB_DSP2 MIB_R22C44:MIB2_DSP2 MIB_R22C45:MIB_DSP3 MIB_R22C45:MIB2_DSP3 MIB_R22C46:MIB_DSP4 MIB_R22C46:MIB2_DSP4
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enum: MULT18_0.REG_INPUTA_CLK NONE
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enum: MULT18_0.REG_INPUTA_CE CE0
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enum: MULT18_0.REG_INPUTA_RST RST0
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enum: MULT18_0.REG_INPUTB_CLK NONE
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enum: MULT18_0.REG_INPUTB_CE CE0
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enum: MULT18_0.REG_INPUTB_RST RST0
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enum: MULT18_0.REG_INPUTC_CLK NONE
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enum: MULT18_0.REG_PIPELINE_CLK NONE
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enum: MULT18_0.REG_PIPELINE_CE CE0
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enum: MULT18_0.REG_PIPELINE_RST RST0
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enum: MULT18_0.REG_OUTPUT_CLK NONE
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enum: MULT18_0.REG_OUTPUT_RST RST0
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enum: MULT18_0.CLK0_DIV ENABLED
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enum: MULT18_0.CLK1_DIV ENABLED
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enum: MULT18_0.CLK2_DIV ENABLED
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enum: MULT18_0.CLK3_DIV ENABLED
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enum: MULT18_0.GSR ENABLED
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enum: MULT18_0.SOURCEB_MODE B_SHIFT
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enum: MULT18_0.RESETMODE SYNC
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enum: MULT18_0.MODE MULT18X18D
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enum: MULT18_0.CIBOUT_BYP ON
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enum: DSP_LEFT.CIBOUT ON
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enum: MULT18_0.CLK0MUX CLK0
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enum: MULT18_0.CLK1MUX CLK1
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enum: MULT18_0.CLK2MUX CLK2
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enum: MULT18_0.CLK3MUX CLK3
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enum: MULT18_0.CE0MUX CE0
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enum: MULT18_0.CE1MUX CE1
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enum: MULT18_0.CE2MUX CE2
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enum: MULT18_0.CE3MUX CE3
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enum: MULT18_0.RST0MUX RST0
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enum: MULT18_0.RST1MUX RST1
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enum: MULT18_0.RST2MUX RST2
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enum: MULT18_0.RST3MUX RST3
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.tile_group MIB_R22C35:MIB_DSP4 MIB_R22C35:MIB2_DSP4 MIB_R22C36:MIB_DSP5 MIB_R22C36:MIB2_DSP5 MIB_R22C37:MIB_DSP6 MIB_R22C37:MIB2_DSP6 MIB_R22C38:MIB_DSP7 MIB_R22C38:MIB2_DSP7 MIB_R22C39:MIB_DSP8 MIB_R22C39:MIB2_DSP8
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enum: MULT18_5.REG_INPUTA_CLK NONE
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enum: MULT18_5.REG_INPUTA_CE CE0
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enum: MULT18_5.REG_INPUTA_RST RST0
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enum: MULT18_5.REG_INPUTB_CLK NONE
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enum: MULT18_5.REG_INPUTB_CE CE0
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enum: MULT18_5.REG_INPUTB_RST RST0
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enum: MULT18_5.REG_INPUTC_CLK NONE
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enum: MULT18_5.REG_PIPELINE_CLK NONE
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enum: MULT18_5.REG_PIPELINE_CE CE0
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enum: MULT18_5.REG_PIPELINE_RST RST0
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enum: MULT18_5.REG_OUTPUT_CLK NONE
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enum: MULT18_5.CLK0_DIV ENABLED
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enum: MULT18_5.CLK1_DIV ENABLED
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enum: MULT18_5.CLK2_DIV ENABLED
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enum: MULT18_5.CLK3_DIV ENABLED
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enum: MULT18_5.GSR ENABLED
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enum: MULT18_5.SOURCEB_MODE B_SHIFT
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enum: MULT18_5.RESETMODE SYNC
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enum: MULT18_5.MODE MULT18X18D
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enum: MULT18_5.CIBOUT_BYP ON
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enum: DSP_RIGHT.CIBOUT ON
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enum: MULT18_5.CLK0MUX CLK0
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enum: MULT18_5.CLK1MUX CLK1
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enum: MULT18_5.CLK2MUX CLK2
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enum: MULT18_5.CLK3MUX CLK3
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enum: MULT18_5.CE0MUX CE0
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enum: MULT18_5.CE1MUX CE1
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enum: MULT18_5.CE2MUX CE2
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enum: MULT18_5.CE3MUX CE3
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enum: MULT18_5.RST0MUX RST0
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enum: MULT18_5.RST1MUX RST1
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enum: MULT18_5.RST2MUX RST2
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enum: MULT18_5.RST3MUX RST3
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.tile_group MIB_R22C35:MIB_DSP4 MIB_R22C35:MIB2_DSP4 MIB_R22C36:MIB_DSP5 MIB_R22C36:MIB2_DSP5 MIB_R22C37:MIB_DSP6 MIB_R22C37:MIB2_DSP6 MIB_R22C38:MIB_DSP7 MIB_R22C38:MIB2_DSP7 MIB_R22C39:MIB_DSP8 MIB_R22C39:MIB2_DSP8
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enum: MULT18_4.REG_INPUTA_CLK NONE
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enum: MULT18_4.REG_INPUTA_CE CE0
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enum: MULT18_4.REG_INPUTA_RST RST0
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enum: MULT18_4.REG_INPUTB_CLK NONE
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enum: MULT18_4.REG_INPUTB_CE CE0
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enum: MULT18_4.REG_INPUTB_RST RST0
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enum: MULT18_4.REG_INPUTC_CLK NONE
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enum: MULT18_4.REG_PIPELINE_CLK NONE
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enum: MULT18_4.REG_PIPELINE_CE CE0
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enum: MULT18_4.REG_PIPELINE_RST RST0
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enum: MULT18_4.REG_OUTPUT_CLK NONE
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enum: MULT18_4.REG_OUTPUT_RST RST0
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enum: MULT18_4.CLK0_DIV ENABLED
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enum: MULT18_4.CLK1_DIV ENABLED
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enum: MULT18_4.CLK2_DIV ENABLED
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enum: MULT18_4.CLK3_DIV ENABLED
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enum: MULT18_4.GSR ENABLED
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enum: MULT18_4.SOURCEB_MODE B_SHIFT
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enum: MULT18_4.RESETMODE SYNC
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enum: MULT18_4.MODE MULT18X18D
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enum: MULT18_4.CIBOUT_BYP ON
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enum: DSP_RIGHT.CIBOUT ON
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enum: MULT18_4.CLK0MUX CLK0
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enum: MULT18_4.CLK1MUX CLK1
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enum: MULT18_4.CLK2MUX CLK2
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enum: MULT18_4.CLK3MUX CLK3
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enum: MULT18_4.CE0MUX CE0
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enum: MULT18_4.CE1MUX CE1
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enum: MULT18_4.CE2MUX CE2
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enum: MULT18_4.CE3MUX CE3
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enum: MULT18_4.RST0MUX RST0
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enum: MULT18_4.RST1MUX RST1
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enum: MULT18_4.RST2MUX RST2
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enum: MULT18_4.RST3MUX RST3
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.tile_group MIB_R22C42:MIB_DSP0 MIB_R22C42:MIB2_DSP0 MIB_R22C43:MIB_DSP1 MIB_R22C43:MIB2_DSP1 MIB_R22C44:MIB_DSP2 MIB_R22C44:MIB2_DSP2 MIB_R22C45:MIB_DSP3 MIB_R22C45:MIB2_DSP3 MIB_R22C46:MIB_DSP4 MIB_R22C46:MIB2_DSP4
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enum: MULT18_1.REG_INPUTA_CLK NONE
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enum: MULT18_1.REG_INPUTA_CE CE0
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enum: MULT18_1.REG_INPUTA_RST RST0
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enum: MULT18_1.REG_INPUTB_CLK NONE
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enum: MULT18_1.REG_INPUTB_CE CE0
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enum: MULT18_1.REG_INPUTB_RST RST0
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enum: MULT18_1.REG_INPUTC_CLK NONE
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enum: MULT18_1.REG_PIPELINE_CLK NONE
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enum: MULT18_1.REG_PIPELINE_CE CE0
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enum: MULT18_1.REG_PIPELINE_RST RST0
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enum: MULT18_1.REG_OUTPUT_CLK NONE
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enum: MULT18_1.CLK0_DIV ENABLED
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enum: MULT18_1.CLK1_DIV ENABLED
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enum: MULT18_1.CLK2_DIV ENABLED
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enum: MULT18_1.CLK3_DIV ENABLED
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enum: MULT18_1.GSR ENABLED
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enum: MULT18_1.SOURCEB_MODE B_SHIFT
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enum: MULT18_1.RESETMODE SYNC
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enum: MULT18_1.MODE MULT18X18D
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enum: MULT18_1.CIBOUT_BYP ON
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enum: DSP_LEFT.CIBOUT ON
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enum: MULT18_1.CLK0MUX CLK0
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enum: MULT18_1.CLK1MUX CLK1
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enum: MULT18_1.CLK2MUX CLK2
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enum: MULT18_1.CLK3MUX CLK3
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enum: MULT18_1.CE0MUX CE0
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enum: MULT18_1.CE1MUX CE1
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enum: MULT18_1.CE2MUX CE2
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enum: MULT18_1.CE3MUX CE3
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enum: MULT18_1.RST0MUX RST0
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enum: MULT18_1.RST1MUX RST1
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enum: MULT18_1.RST2MUX RST2
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enum: MULT18_1.RST3MUX RST3
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.tile_group MIB_R22C22:MIB_DSP0 MIB_R22C22:MIB2_DSP0 MIB_R22C23:MIB_DSP1 MIB_R22C23:MIB2_DSP1 MIB_R22C24:MIB_DSP2 MIB_R22C24:MIB2_DSP2 MIB_R22C25:MIB_DSP3 MIB_R22C25:MIB2_DSP3 MIB_R22C26:MIB_DSP4 MIB_R22C26:MIB2_DSP4
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enum: MULT18_0.REG_INPUTA_CLK NONE
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enum: MULT18_0.REG_INPUTA_CE CE0
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enum: MULT18_0.REG_INPUTA_RST RST0
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enum: MULT18_0.REG_INPUTB_CLK NONE
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enum: MULT18_0.REG_INPUTB_CE CE0
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enum: MULT18_0.REG_INPUTB_RST RST0
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enum: MULT18_0.REG_INPUTC_CLK NONE
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enum: MULT18_0.REG_PIPELINE_CLK NONE
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enum: MULT18_0.REG_PIPELINE_CE CE0
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enum: MULT18_0.REG_PIPELINE_RST RST0
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enum: MULT18_0.REG_OUTPUT_CLK NONE
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enum: MULT18_0.REG_OUTPUT_RST RST0
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enum: MULT18_0.CLK0_DIV ENABLED
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enum: MULT18_0.CLK1_DIV ENABLED
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enum: MULT18_0.CLK2_DIV ENABLED
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enum: MULT18_0.CLK3_DIV ENABLED
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enum: MULT18_0.GSR ENABLED
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enum: MULT18_0.SOURCEB_MODE B_SHIFT
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enum: MULT18_0.RESETMODE SYNC
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enum: MULT18_0.MODE MULT18X18D
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enum: MULT18_0.CIBOUT_BYP ON
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enum: DSP_LEFT.CIBOUT ON
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enum: MULT18_0.CLK0MUX CLK0
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enum: MULT18_0.CLK1MUX CLK1
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enum: MULT18_0.CLK2MUX CLK2
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enum: MULT18_0.CLK3MUX CLK3
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enum: MULT18_0.CE0MUX CE0
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enum: MULT18_0.CE1MUX CE1
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enum: MULT18_0.CE2MUX CE2
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enum: MULT18_0.CE3MUX CE3
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enum: MULT18_0.RST0MUX RST0
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enum: MULT18_0.RST1MUX RST1
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enum: MULT18_0.RST2MUX RST2
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enum: MULT18_0.RST3MUX RST3
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.tile_group MIB_R22C31:MIB_DSP0 MIB_R22C31:MIB2_DSP0 MIB_R22C32:MIB_DSP1 MIB_R22C32:MIB2_DSP1 MIB_R22C33:MIB_DSP2 MIB_R22C33:MIB2_DSP2 MIB_R22C34:MIB_DSP3 MIB_R22C34:MIB2_DSP3 MIB_R22C35:MIB_DSP4 MIB_R22C35:MIB2_DSP4
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enum: MULT18_1.REG_INPUTA_CLK NONE
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enum: MULT18_1.REG_INPUTA_CE CE0
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enum: MULT18_1.REG_INPUTA_RST RST0
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enum: MULT18_1.REG_INPUTB_CLK NONE
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enum: MULT18_1.REG_INPUTB_CE CE0
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enum: MULT18_1.REG_INPUTB_RST RST0
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enum: MULT18_1.REG_INPUTC_CLK NONE
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enum: MULT18_1.REG_PIPELINE_CLK NONE
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enum: MULT18_1.REG_PIPELINE_CE CE0
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enum: MULT18_1.REG_PIPELINE_RST RST0
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enum: MULT18_1.REG_OUTPUT_CLK NONE
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enum: MULT18_1.CLK0_DIV ENABLED
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enum: MULT18_1.CLK1_DIV ENABLED
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enum: MULT18_1.CLK2_DIV ENABLED
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enum: MULT18_1.CLK3_DIV ENABLED
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enum: MULT18_1.GSR ENABLED
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enum: MULT18_1.SOURCEB_MODE B_SHIFT
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enum: MULT18_1.RESETMODE SYNC
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enum: MULT18_1.MODE MULT18X18D
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enum: MULT18_1.CIBOUT_BYP ON
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enum: DSP_LEFT.CIBOUT ON
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enum: MULT18_1.CLK0MUX CLK0
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enum: MULT18_1.CLK1MUX CLK1
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enum: MULT18_1.CLK2MUX CLK2
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enum: MULT18_1.CLK3MUX CLK3
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enum: MULT18_1.CE0MUX CE0
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enum: MULT18_1.CE1MUX CE1
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enum: MULT18_1.CE2MUX CE2
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enum: MULT18_1.CE3MUX CE3
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enum: MULT18_1.RST0MUX RST0
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enum: MULT18_1.RST1MUX RST1
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enum: MULT18_1.RST2MUX RST2
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enum: MULT18_1.RST3MUX RST3
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.tile_group MIB_R22C26:MIB_DSP4 MIB_R22C26:MIB2_DSP4 MIB_R22C27:MIB_DSP5 MIB_R22C27:MIB2_DSP5 MIB_R22C28:MIB_DSP6 MIB_R22C28:MIB2_DSP6 MIB_R22C29:MIB_DSP7 MIB_R22C29:MIB2_DSP7 MIB_R22C30:MIB_DSP8 MIB_R22C30:MIB2_DSP8
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enum: MULT18_5.REG_INPUTA_CLK NONE
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enum: MULT18_5.REG_INPUTA_CE CE0
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enum: MULT18_5.REG_INPUTA_RST RST0
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enum: MULT18_5.REG_INPUTB_CLK NONE
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enum: MULT18_5.REG_INPUTB_CE CE0
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enum: MULT18_5.REG_INPUTB_RST RST0
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enum: MULT18_5.REG_INPUTC_CLK NONE
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enum: MULT18_5.REG_PIPELINE_CLK NONE
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enum: MULT18_5.REG_PIPELINE_CE CE0
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enum: MULT18_5.REG_PIPELINE_RST RST0
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enum: MULT18_5.REG_OUTPUT_CLK NONE
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enum: MULT18_5.CLK0_DIV ENABLED
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enum: MULT18_5.CLK1_DIV ENABLED
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enum: MULT18_5.CLK2_DIV ENABLED
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enum: MULT18_5.CLK3_DIV ENABLED
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enum: MULT18_5.GSR ENABLED
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enum: MULT18_5.SOURCEB_MODE B_SHIFT
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enum: MULT18_5.RESETMODE SYNC
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enum: MULT18_5.MODE MULT18X18D
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enum: MULT18_5.CIBOUT_BYP ON
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enum: DSP_RIGHT.CIBOUT ON
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enum: MULT18_5.CLK0MUX CLK0
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enum: MULT18_5.CLK1MUX CLK1
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enum: MULT18_5.CLK2MUX CLK2
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enum: MULT18_5.CLK3MUX CLK3
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enum: MULT18_5.CE0MUX CE0
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enum: MULT18_5.CE1MUX CE1
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enum: MULT18_5.CE2MUX CE2
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enum: MULT18_5.CE3MUX CE3
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enum: MULT18_5.RST0MUX RST0
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enum: MULT18_5.RST1MUX RST1
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enum: MULT18_5.RST2MUX RST2
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enum: MULT18_5.RST3MUX RST3
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.tile_group MIB_R22C26:MIB_DSP4 MIB_R22C26:MIB2_DSP4 MIB_R22C27:MIB_DSP5 MIB_R22C27:MIB2_DSP5 MIB_R22C28:MIB_DSP6 MIB_R22C28:MIB2_DSP6 MIB_R22C29:MIB_DSP7 MIB_R22C29:MIB2_DSP7 MIB_R22C30:MIB_DSP8 MIB_R22C30:MIB2_DSP8
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enum: MULT18_4.REG_INPUTA_CLK NONE
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enum: MULT18_4.REG_INPUTA_CE CE0
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enum: MULT18_4.REG_INPUTA_RST RST0
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enum: MULT18_4.REG_INPUTB_CLK NONE
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enum: MULT18_4.REG_INPUTB_CE CE0
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enum: MULT18_4.REG_INPUTB_RST RST0
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enum: MULT18_4.REG_INPUTC_CLK NONE
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enum: MULT18_4.REG_PIPELINE_CLK NONE
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enum: MULT18_4.REG_PIPELINE_CE CE0
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enum: MULT18_4.REG_PIPELINE_RST RST0
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enum: MULT18_4.REG_OUTPUT_CLK NONE
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enum: MULT18_4.REG_OUTPUT_RST RST0
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enum: MULT18_4.CLK0_DIV ENABLED
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enum: MULT18_4.CLK1_DIV ENABLED
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enum: MULT18_4.CLK2_DIV ENABLED
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enum: MULT18_4.CLK3_DIV ENABLED
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enum: MULT18_4.GSR ENABLED
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enum: MULT18_4.SOURCEB_MODE B_SHIFT
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enum: MULT18_4.RESETMODE SYNC
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enum: MULT18_4.MODE MULT18X18D
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enum: MULT18_4.CIBOUT_BYP ON
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enum: DSP_RIGHT.CIBOUT ON
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enum: MULT18_4.CLK0MUX CLK0
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enum: MULT18_4.CLK1MUX CLK1
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enum: MULT18_4.CLK2MUX CLK2
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enum: MULT18_4.CLK3MUX CLK3
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enum: MULT18_4.CE0MUX CE0
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enum: MULT18_4.CE1MUX CE1
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enum: MULT18_4.CE2MUX CE2
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enum: MULT18_4.CE3MUX CE3
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enum: MULT18_4.RST0MUX RST0
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enum: MULT18_4.RST1MUX RST1
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enum: MULT18_4.RST2MUX RST2
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enum: MULT18_4.RST3MUX RST3
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