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FPGA-Neural/hardware/v2/synthesis/neural_processor_p8/nextpnr.log
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micheleandClaude Sonnet 5 dc0b331d3e feat(v2): scaffold hardware/v1 frozen baseline + M1 Neural Processor 
Begins the V2 Neural Multiprocessor / Dataflow architecture per
docs/v2-description.md, per explicit user request to freeze V1 and
start V2 development, copying from V1 what's needed.

Scaffold:
- hardware/v1/: byte-exact, read-only copy of the current V1 codebase
  (rtl, testbenches, tools, constraints, a representative subset of
  synthesis results, and reference docs) -- verified identical via
  diff/cmp against the live top-level tree before being made
  filesystem-read-only. The live top-level tree is untouched and
  remains the project's "production" V1 (see hardware/v1/README.md
  and hardware/v2/logs/decisions.log DEC-0001 for why copy-not-move).
- hardware/v2/: mandatory structure (rtl/sim/constraints/synthesis/
  reports/scripts/logs/docs) plus the full logging system required by
  the spec (development/architecture/simulation/synthesis/timing/
  benchmark/decisions/experiments/errors.log).

M1 -- Neural Processor (hardware/v2/rtl/neural_processor.v):
- 8-stage pipelined perceptron unit (P_IN=8): input align, 8
  multipliers, 3-level adder tree, accumulator, bias+activation, INT8
  saturation. Genuine 1-tile/cycle throughput, not just a wider
  combinational datapath.
- 7-state FSM (NP_IDLE..NP_ERROR per docs/v2-description.md §6, with
  4 baseline states merged into NP_WAIT_OPERANDS -- see
  decisions.log DEC-0002); valid/ready/data/last stream interfaces
  per §7.
- Bit-exact vs the frozen hardware/v1/rtl/neuron_parallel.v + mac8.v
  + mac_unit.v: 7/7 tests pass (hardware/v2/sim/tb_neural_processor.v),
  covering regular/mixed-sign/extreme-INT8 vectors, both activations,
  a zero-idle-gap back-to-back-tiles throughput check, and an 8-tile
  job -- verified with Verilator (see below for why).
- Real synthesis + place&route (Yosys + nextpnr-ecp5): 0 CHECK
  problems, Fmax 183.12 MHz at ACC_WIDTH=32 (PASS at 80MHz, ~3x V1's
  isolated PARALLEL=8 Fmax of 61.71 MHz) and 176.21 MHz at ACC_WIDTH=24
  (a user-requested comparison experiment, also bit-exact-verified;
  see experiments.log EXP-0001/EXP-0002 and benchmark.log).

Three real bugs found and resolved during M1 development (full
diagnostic record in errors.log):
- Two independent, reproducible Icarus Verilog v13.0 scheduling
  defects (ERR-0001, ERR-0002) that silently produced wrong simulation
  results for standard sequential Verilog -- confirmed via Verilator
  5.050 giving correct results on the same minimal repros. Verilator
  is now the trusted simulator for hardware/v2/ (decisions.log
  DEC-0004); Icarus's affected protocol-violation check was removed
  from the RTL and deferred architecturally to the Neural Director
  (DEC-0003) rather than chased further.
- One real RTL bug (ERR-0003): last0 wasn't gated like valid0,
  letting a "last tile" tag leak into the pipeline ahead of its
  actual valid tile on back-to-back jobs. Fixed and verified.

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
2026-09-05 14:06:53 +02:00

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Info: Logic utilisation before packing:
Info: Total LUT4s: 247/43848 0%
Info: logic LUTs: 55/43848 0%
Info: carry LUTs: 192/43848 0%
Info: RAM LUTs: 0/ 5481 0%
Info: RAMW LUTs: 0/10962 0%
Info: Total DFFs: 533/43848 1%
Info: Packing IOs..
Info: Packing constants..
Info: Packing carries...
Info: Packing LUTs...
Info: Packing LUT5-7s...
Info: Packing FFs...
Info: 200 FFs paired with LUTs.
Info: Generating derived timing constraints...
Info: Promoting globals...
Info: promoting clock net clk$TRELLIS_IO_IN to global network
Info: Checksum: 0x25ed72db
Info: Device utilisation:
Info: TRELLIS_IO: 192/ 245 78%
Info: DCCA: 1/ 56 1%
Info: DP16KD: 0/ 108 0%
Info: MULT18X18D: 8/ 72 11%
Info: ALU54B: 0/ 36 0%
Info: EHXPLLL: 0/ 4 0%
Info: EXTREFB: 0/ 2 0%
Info: DCUA: 0/ 2 0%
Info: PCSCLKDIV: 0/ 2 0%
Info: IOLOGIC: 0/ 160 0%
Info: SIOLOGIC: 0/ 85 0%
Info: GSR: 0/ 1 0%
Info: JTAGG: 0/ 1 0%
Info: OSCG: 0/ 1 0%
Info: SEDGA: 0/ 1 0%
Info: DTR: 0/ 1 0%
Info: USRMCLK: 0/ 1 0%
Info: CLKDIVF: 0/ 4 0%
Info: ECLKSYNCB: 0/ 10 0%
Info: DLLDELD: 0/ 8 0%
Info: DDRDLL: 0/ 4 0%
Info: DQSBUFM: 0/ 10 0%
Info: TRELLIS_ECLKBUF: 0/ 8 0%
Info: ECLKBRIDGECS: 0/ 2 0%
Info: DCSC: 0/ 2 0%
Info: TRELLIS_FF: 533/ 43848 1%
Info: TRELLIS_COMB: 285/ 43848 0%
Info: TRELLIS_RAMW: 0/ 5481 0%
Info: Placed 0 cells based on constraints.
Info: Creating initial analytic placement for 398 cells, random placement wirelen = 48233.
Info: at initial placer iter 0, wirelen = 12124
Info: at initial placer iter 1, wirelen = 11322
Info: at initial placer iter 2, wirelen = 11157
Info: at initial placer iter 3, wirelen = 11173
Info: Running main analytical placer, max placement attempts per cell = 129795.
Info: at iteration #1, type ALL: wirelen solved = 11120, spread = 14753, legal = 16255; time = 0.01s
Info: at iteration #2, type ALL: wirelen solved = 11258, spread = 13822, legal = 15182; time = 0.00s
Info: at iteration #3, type ALL: wirelen solved = 11337, spread = 14156, legal = 15283; time = 0.00s
Info: at iteration #4, type ALL: wirelen solved = 11332, spread = 13597, legal = 13906; time = 0.00s
Info: HeAP Placer Time: 0.05s
Info: of which solving equations: 0.02s
Info: of which spreading cells: 0.00s
Info: of which strict legalisation: 0.00s
Info: Running simulated annealing placer for refinement.
Info: at iteration #1: temp = 0.000000, timing cost = 41, wirelen = 13906
Info: at iteration #5: temp = 0.000000, timing cost = 113, wirelen = 11955
Info: at iteration #8: temp = 0.000000, timing cost = 111, wirelen = 11890
Info: SA placement time 0.07s
Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 168.69 MHz (PASS at 80.00 MHz)
Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 8.82 ns
Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 5.91 ns
Info: Slack histogram:
Info: legend: * represents 2 endpoint(s)
Info: + represents [1,2) endpoint(s)
Info: [ 6572, 6831) |+
Info: [ 6831, 7090) |+
Info: [ 7090, 7349) |*****+
Info: [ 7349, 7608) |*****************+
Info: [ 7608, 7867) |************************************************************
Info: [ 7867, 8126) |*******************+
Info: [ 8126, 8385) |********+
Info: [ 8385, 8644) |*****+
Info: [ 8644, 8903) |**+
Info: [ 8903, 9162) |**+
Info: [ 9162, 9421) |*******+
Info: [ 9421, 9680) |*******+
Info: [ 9680, 9939) |*************************+
Info: [ 9939, 10198) |************************************+
Info: [ 10198, 10457) |************+
Info: [ 10457, 10716) |*********+
Info: [ 10716, 10975) |************+
Info: [ 10975, 11234) |******+
Info: [ 11234, 11493) |******+
Info: [ 11493, 11752) |*******+
Info: Checksum: 0x90337da1
Info: Routing globals...
Info: routing clock net $glbnet$clk$TRELLIS_IO_IN using global 0
Info: Routing..
Info: Setting up routing queue.
Info: Routing 2003 arcs.
Info: | (re-)routed arcs | delta | remaining| time spent |
Info: IterCnt | w/ripup wo/ripup | w/r wo/r | arcs| batch(sec) total(sec)|
Info: 1000 | 120 879 | 120 879 | 1169| 0.22 0.22|
Info: 2000 | 172 1715 | 52 836 | 224| 0.12 0.35|
Info: 2225 | 174 1929 | 2 214 | 0| 0.08 0.43|
Info: Routing complete.
Info: Router1 time 0.43s
Info: Checksum: 0x87c32d65
Info: Critical path report for clock '$glbnet$clk$TRELLIS_IO_IN' (posedge -> posedge):
Info: type curr total name
Info: clk-to-q 0.40 0.40 Source x0[1]_TRELLIS_FF_Q_7.Q
Info: routing 1.05 1.44 Net x0[1][7] (43,23) -> (43,22)
Info: Sink product_comb[1]_MULT18X18D_P9.A15
Info: Defined in:
Info: hardware/v2/rtl/neural_processor.v:99.44-99.46
Info: logic 3.07 4.51 Source product_comb[1]_MULT18X18D_P9.P1
Info: routing 0.95 5.46 Net product_comb[1][1] (43,22) -> (43,23)
Info: Sink prod1[1]_TRELLIS_FF_Q_1.M
Info: Defined in:
Info: hardware/v2/rtl/neural_processor.v:135.34-135.46
Info: setup 0.00 5.46 Source prod1[1]_TRELLIS_FF_Q_1.M
Info: 3.46 ns logic, 2.00 ns routing
Info: Critical path report for cross-domain path '<async>' -> 'posedge $glbnet$clk$TRELLIS_IO_IN':
Info: type curr total name
Info: source 0.00 0.00 Source operand_valid$tr_io.O
Info: routing 3.08 3.08 Net operand_valid$TRELLIS_IO_IN (90,29) -> (38,23)
Info: Sink operand_valid_LUT4_C.C
Info: Defined in:
Info: hardware/v2/rtl/neural_processor.v:50.43-50.56
Info: logic 0.18 3.26 Source operand_valid_LUT4_C.F
Info: routing 0.82 4.08 Net operand_valid_LUT4_C_Z[1] (38,23) -> (30,21)
Info: Sink operand_valid_LUT4_C_Z_LUT4_D.D
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 4.26 Source operand_valid_LUT4_C_Z_LUT4_D.F
Info: routing 0.85 5.12 Net operand_valid_LUT4_C_Z_LUT4_D_Z (30,21) -> (37,24)
Info: Sink last0_TRELLIS_FF_Q_LSR_LUT4_Z.D
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 5.30 Source last0_TRELLIS_FF_Q_LSR_LUT4_Z.F
Info: routing 0.43 5.72 Net last0_TRELLIS_FF_Q_LSR (37,24) -> (38,24)
Info: Sink last0_TRELLIS_FF_Q.LSR
Info: setup 0.29 6.01 Source last0_TRELLIS_FF_Q.LSR
Info: 0.83 ns logic, 5.18 ns routing
Info: Critical path report for cross-domain path 'posedge $glbnet$clk$TRELLIS_IO_IN' -> '<async>':
Info: type curr total name
Info: clk-to-q 0.40 0.40 Source np_state_TRELLIS_FF_Q_1.Q
Info: routing 0.68 1.07 Net np_state[1]$TRELLIS_IO_OUT (39,23) -> (38,23)
Info: Sink operand_ready_LUT4_D_C_LUT4_Z.C
Info: Defined in:
Info: hardware/v2/rtl/neural_processor.v:63.43-63.51
Info: logic 0.18 1.25 Source operand_ready_LUT4_D_C_LUT4_Z.F
Info: routing 0.03 1.29 Net operand_ready_LUT4_D_C[1] (38,23) -> (38,23)
Info: Sink valid6_LUT4_C_Z_LUT4_Z.D
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 1.47 Source valid6_LUT4_C_Z_LUT4_Z.F
Info: routing 0.49 1.95 Net job_valid_LUT4_C_Z[1] (38,23) -> (38,23)
Info: Sink job_ready_LUT4_Z.D
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 2.13 Source job_ready_LUT4_Z.F
Info: routing 2.34 4.47 Net job_ready$TRELLIS_IO_OUT (38,23) -> (0,29)
Info: Sink job_ready$tr_io.I
Info: Defined in:
Info: hardware/v2/rtl/neural_processor.v:44.42-44.51
Info: 0.94 ns logic, 3.53 ns routing
Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 183.12 MHz (PASS at 80.00 MHz)
Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 6.01 ns
Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 4.47 ns
Info: Slack histogram:
Info: legend: * represents 1 endpoint(s)
Info: + represents [1,1) endpoint(s)
Info: [ 7039, 7277) |*****************************+
Info: [ 7277, 7515) |*********************************************+
Info: [ 7515, 7753) |****+
Info: [ 7753, 7991) |***+
Info: [ 7991, 8229) |******+
Info: [ 8229, 8467) |****+
Info: [ 8467, 8705) |*****************+
Info: [ 8705, 8943) |*************************************+
Info: [ 8943, 9181) |**************************+
Info: [ 9181, 9419) |************+
Info: [ 9419, 9657) |***********+
Info: [ 9657, 9895) |***************************************+
Info: [ 9895, 10133) |************************************************************
Info: [ 10133, 10371) |*************************+
Info: [ 10371, 10609) |*********+
Info: [ 10609, 10847) |****+
Info: [ 10847, 11085) |*********+
Info: [ 11085, 11323) |***************+
Info: [ 11323, 11561) |*********+
Info: [ 11561, 11799) |*********+
Info: Program finished normally.
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