micheleandClaude Sonnet 5
175f697ae1
Implements M4: memory_manager.v (arbitration/buffering/forwarding/ latency hiding/double buffering, §12) + prefetch_engine.v (double-buffered tile fetch, §13), sitting on the REAL, UNMODIFIED V1 PSRAM backend chain (int8_memory_access.v -> memory_interface.v -> psram_controller.v, per §15's explicit mandate not to touch the controller). Verified fully end-to-end with Verilator: real neural_processor (M1) fed entirely by memory_manager, computing against PSRAM-resident X/W tiles (double-buffered prefetch across up to 5 tiles) and writing its result back to PSRAM -- checked via an independent PSRAM read-back, with poison bytes around the operand regions to catch addressing errors. 3/3 jobs pass (1/3/5-tile configurations). Three real RTL bugs found and fixed during integration (full diagnostic trail in errors.log ERR-0006): prefetch_engine had no single-in-flight-request discipline, letting a queued request corrupt the bank bookkeeping of a fetch already running; the fix's own !pf_busy guard had a one-cycle blind spot (pf_busy lags pf_start by a clock) that needed an explicit !pf_start term; and a state-based mux for the shared backend port was off by one cycle, silently dropping the PSRAM result write entirely. Real synthesis: 0 CHECK problems, 851 LUT4/789 FF/108 CCU2C/0 DSP (expected, no multiplication in this module). Real place&route (via a synthesis-only timing harness, needed for the same TRELLIS_IO pin- budget reason as M2's array): Fmax 165.86 MHz, PASS at 80MHz. Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
2345 lines
145 KiB
Plaintext
2345 lines
145 KiB
Plaintext
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/----------------------------------------------------------------------------\
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| yosys -- Yosys Open SYnthesis Suite |
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| Copyright (C) 2012 - 2026 Claire Xenia Wolf <claire@yosyshq.com> |
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| Distributed under an ISC-like license, type "license" to see terms |
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\----------------------------------------------------------------------------/
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Yosys 0.68+post (git sha1 c12172fbae8af5e20f6fb52e3d4e92d56ed587b6, Release, AppleClang clang++ 21.0.0.21000101)
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-- Parsing `hardware/v2/rtl/memory_manager.v' using frontend ` -vlog2k' --
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1. Executing Verilog-2005 frontend: hardware/v2/rtl/memory_manager.v
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Parsing Verilog input from `hardware/v2/rtl/memory_manager.v' to AST representation.
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Storing AST representation for module `$abstract\memory_manager'.
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Successfully finished Verilog frontend.
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-- Parsing `hardware/v2/rtl/prefetch_engine.v' using frontend ` -vlog2k' --
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2. Executing Verilog-2005 frontend: hardware/v2/rtl/prefetch_engine.v
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Parsing Verilog input from `hardware/v2/rtl/prefetch_engine.v' to AST representation.
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Storing AST representation for module `$abstract\prefetch_engine'.
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Successfully finished Verilog frontend.
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-- Running command `synth_ecp5 -json hardware/v2/synthesis/memory_manager_p8/top.json -top memory_manager' --
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3. Executing SYNTH_LATTICE pass.
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3.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v
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Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v' to AST representation.
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Generating RTLIL representation for module `\LUT4'.
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Generating RTLIL representation for module `\$__ABC9_LUT5'.
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Generating RTLIL representation for module `\$__ABC9_LUT6'.
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Generating RTLIL representation for module `\$__ABC9_LUT7'.
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Generating RTLIL representation for module `\L6MUX21'.
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Generating RTLIL representation for module `\TRELLIS_RAM16X2'.
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Generating RTLIL representation for module `\PFUMX'.
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Generating RTLIL representation for module `\TRELLIS_DPR16X4'.
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Generating RTLIL representation for module `\DPR16X4C'.
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Generating RTLIL representation for module `\LUT2'.
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Generating RTLIL representation for module `\TRELLIS_FF'.
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Generating RTLIL representation for module `\TRELLIS_IO'.
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Generating RTLIL representation for module `\INV'.
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Generating RTLIL representation for module `\TRELLIS_COMB'.
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Generating RTLIL representation for module `\VLO'.
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Generating RTLIL representation for module `\VHI'.
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Generating RTLIL representation for module `\FD1P3AX'.
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Generating RTLIL representation for module `\FD1P3AY'.
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Generating RTLIL representation for module `\FD1P3BX'.
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Generating RTLIL representation for module `\FD1P3DX'.
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Generating RTLIL representation for module `\FD1P3IX'.
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Generating RTLIL representation for module `\FD1P3JX'.
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Generating RTLIL representation for module `\FD1S3AX'.
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Generating RTLIL representation for module `\FD1S3AY'.
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Generating RTLIL representation for module `\FD1S3BX'.
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Generating RTLIL representation for module `\FD1S3DX'.
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Generating RTLIL representation for module `\FD1S3IX'.
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Generating RTLIL representation for module `\FD1S3JX'.
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Generating RTLIL representation for module `\IFS1P3BX'.
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Generating RTLIL representation for module `\IFS1P3DX'.
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Generating RTLIL representation for module `\IFS1P3IX'.
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Generating RTLIL representation for module `\IFS1P3JX'.
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Generating RTLIL representation for module `\OFS1P3BX'.
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Generating RTLIL representation for module `\OFS1P3DX'.
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Generating RTLIL representation for module `\OFS1P3IX'.
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Generating RTLIL representation for module `\OFS1P3JX'.
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Generating RTLIL representation for module `\IB'.
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Generating RTLIL representation for module `\IBPU'.
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Generating RTLIL representation for module `\IBPD'.
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Generating RTLIL representation for module `\OB'.
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Generating RTLIL representation for module `\OBZ'.
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Generating RTLIL representation for module `\OBZPU'.
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Generating RTLIL representation for module `\OBZPD'.
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Generating RTLIL representation for module `\OBCO'.
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Generating RTLIL representation for module `\BB'.
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Generating RTLIL representation for module `\BBPU'.
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Generating RTLIL representation for module `\BBPD'.
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Generating RTLIL representation for module `\ILVDS'.
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Generating RTLIL representation for module `\OLVDS'.
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Generating RTLIL representation for module `\CCU2C'.
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Generating RTLIL representation for module `\DP16KD'.
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Replacing existing blackbox module `\FD1P3AX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:2.1-2.261.
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Generating RTLIL representation for module `\FD1P3AX'.
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Replacing existing blackbox module `\FD1P3AY' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:3.1-3.261.
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Generating RTLIL representation for module `\FD1P3AY'.
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Replacing existing blackbox module `\FD1P3BX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:4.1-4.261.
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Generating RTLIL representation for module `\FD1P3BX'.
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Replacing existing blackbox module `\FD1P3DX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:5.1-5.261.
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Generating RTLIL representation for module `\FD1P3DX'.
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Replacing existing blackbox module `\FD1P3IX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:6.1-6.261.
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Generating RTLIL representation for module `\FD1P3IX'.
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Replacing existing blackbox module `\FD1P3JX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:7.1-7.261.
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Generating RTLIL representation for module `\FD1P3JX'.
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Replacing existing blackbox module `\FD1S3AX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:8.1-8.261.
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Generating RTLIL representation for module `\FD1S3AX'.
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Replacing existing blackbox module `\FD1S3AY' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:9.1-9.261.
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Generating RTLIL representation for module `\FD1S3AY'.
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Replacing existing blackbox module `\FD1S3BX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:10.1-10.261.
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Generating RTLIL representation for module `\FD1S3BX'.
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Replacing existing blackbox module `\FD1S3DX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:11.1-11.261.
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Generating RTLIL representation for module `\FD1S3DX'.
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Replacing existing blackbox module `\FD1S3IX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:12.1-12.261.
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Generating RTLIL representation for module `\FD1S3IX'.
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Replacing existing blackbox module `\FD1S3JX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:13.1-13.261.
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Generating RTLIL representation for module `\FD1S3JX'.
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Replacing existing blackbox module `\IFS1P3BX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:26.1-26.301.
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Generating RTLIL representation for module `\IFS1P3BX'.
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Replacing existing blackbox module `\IFS1P3DX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:27.1-27.301.
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Generating RTLIL representation for module `\IFS1P3DX'.
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Replacing existing blackbox module `\IFS1P3IX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:28.1-28.301.
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Generating RTLIL representation for module `\IFS1P3IX'.
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Replacing existing blackbox module `\IFS1P3JX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:29.1-29.301.
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Generating RTLIL representation for module `\IFS1P3JX'.
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Replacing existing blackbox module `\OFS1P3BX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:31.1-31.302.
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Generating RTLIL representation for module `\OFS1P3BX'.
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Replacing existing blackbox module `\OFS1P3DX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:32.1-32.302.
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Generating RTLIL representation for module `\OFS1P3DX'.
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Replacing existing blackbox module `\OFS1P3IX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:33.1-33.302.
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Generating RTLIL representation for module `\OFS1P3IX'.
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Replacing existing blackbox module `\OFS1P3JX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:34.1-34.302.
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Generating RTLIL representation for module `\OFS1P3JX'.
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Replacing existing blackbox module `\IB' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:2.1-2.157.
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Generating RTLIL representation for module `\IB'.
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Replacing existing blackbox module `\IBPU' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:3.1-3.157.
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Generating RTLIL representation for module `\IBPU'.
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Replacing existing blackbox module `\IBPD' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:4.1-4.157.
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Generating RTLIL representation for module `\IBPD'.
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Replacing existing blackbox module `\OB' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:5.1-5.157.
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Generating RTLIL representation for module `\OB'.
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Replacing existing blackbox module `\OBZ' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:6.1-6.164.
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Generating RTLIL representation for module `\OBZ'.
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Replacing existing blackbox module `\OBZPU' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:7.1-7.164.
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Generating RTLIL representation for module `\OBZPU'.
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Replacing existing blackbox module `\OBZPD' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:8.1-8.164.
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Generating RTLIL representation for module `\OBZPD'.
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Replacing existing blackbox module `\OBCO' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:9.1-9.90.
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Generating RTLIL representation for module `\OBCO'.
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Replacing existing blackbox module `\BB' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:10.1-10.179.
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Generating RTLIL representation for module `\BB'.
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Replacing existing blackbox module `\BBPU' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:11.1-11.179.
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Generating RTLIL representation for module `\BBPU'.
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Replacing existing blackbox module `\BBPD' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:12.1-12.179.
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Generating RTLIL representation for module `\BBPD'.
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Replacing existing blackbox module `\ILVDS' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:13.1-13.139.
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Generating RTLIL representation for module `\ILVDS'.
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Replacing existing blackbox module `\OLVDS' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:14.1-14.146.
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Generating RTLIL representation for module `\OLVDS'.
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Successfully finished Verilog frontend.
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3.2. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v
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Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v' to AST representation.
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Generating RTLIL representation for module `\GSR'.
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Generating RTLIL representation for module `\PUR'.
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Generating RTLIL representation for module `\SGSR'.
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Generating RTLIL representation for module `\PDPW16KD'.
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Generating RTLIL representation for module `\MULT18X18D'.
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Generating RTLIL representation for module `\ALU54B'.
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Generating RTLIL representation for module `\CLKDIVF'.
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Generating RTLIL representation for module `\PCSCLKDIV'.
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Generating RTLIL representation for module `\DCSC'.
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Generating RTLIL representation for module `\DCCA'.
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Generating RTLIL representation for module `\ECLKSYNCB'.
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Generating RTLIL representation for module `\ECLKBRIDGECS'.
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Generating RTLIL representation for module `\DELAYF'.
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Generating RTLIL representation for module `\DELAYG'.
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Generating RTLIL representation for module `\USRMCLK'.
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Generating RTLIL representation for module `\DQSBUFM'.
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Generating RTLIL representation for module `\DDRDLLA'.
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Generating RTLIL representation for module `\DLLDELD'.
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Generating RTLIL representation for module `\IDDRX1F'.
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Generating RTLIL representation for module `\IDDRX2F'.
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Generating RTLIL representation for module `\IDDR71B'.
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Generating RTLIL representation for module `\IDDRX2DQA'.
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Generating RTLIL representation for module `\ODDRX1F'.
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Generating RTLIL representation for module `\ODDRX2F'.
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Generating RTLIL representation for module `\ODDR71B'.
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Generating RTLIL representation for module `\OSHX2A'.
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Generating RTLIL representation for module `\TSHX2DQA'.
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Generating RTLIL representation for module `\TSHX2DQSA'.
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Generating RTLIL representation for module `\ODDRX2DQA'.
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Generating RTLIL representation for module `\ODDRX2DQSB'.
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Generating RTLIL representation for module `\EHXPLLL'.
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Generating RTLIL representation for module `\DTR'.
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Generating RTLIL representation for module `\OSCG'.
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Generating RTLIL representation for module `\EXTREFB'.
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Generating RTLIL representation for module `\JTAGG'.
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Generating RTLIL representation for module `\DCUA'.
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Successfully finished Verilog frontend.
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3.3. Executing HIERARCHY pass (managing design hierarchy).
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3.4. Executing AST frontend in derive mode using pre-parsed AST for module `\memory_manager'.
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Generating RTLIL representation for module `\memory_manager'.
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3.4.1. Analyzing design hierarchy..
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Top module: \memory_manager
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Parameter \DATA_WIDTH = 8
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Parameter \P_IN = 8
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Parameter \ADDR_WIDTH = 23
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3.4.2. Executing AST frontend in derive mode using pre-parsed AST for module `\prefetch_engine'.
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Parameter \DATA_WIDTH = 8
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Parameter \P_IN = 8
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Parameter \ADDR_WIDTH = 23
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Generating RTLIL representation for module `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\prefetch_engine'.
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3.4.3. Analyzing design hierarchy..
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Top module: \memory_manager
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Used module: $paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\prefetch_engine
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3.4.4. Analyzing design hierarchy..
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Top module: \memory_manager
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Used module: $paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\prefetch_engine
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Removing unused module `$abstract\prefetch_engine'.
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Removing unused module `$abstract\memory_manager'.
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Removed 2 unused modules.
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3.5. Executing PROC pass (convert processes to netlists).
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3.5.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
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Cleaned up 0 empty switches.
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3.5.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
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Removed 1 dead cases from process $proc$hardware/v2/rtl/prefetch_engine.v:58$325 in module $paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\prefetch_engine.
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Marked 6 switch rules as full_case in process $proc$hardware/v2/rtl/prefetch_engine.v:58$325 in module $paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\prefetch_engine.
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Marked 6 switch rules as full_case in process $proc$hardware/v2/rtl/memory_manager.v:157$238 in module memory_manager.
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Removed a total of 1 dead cases.
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3.5.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
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Removed 5 redundant assignments.
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Promoted 16 assignments to connections.
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3.5.4. Executing PROC_INIT pass (extract init attributes).
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3.5.5. Executing PROC_ARST pass (detect async resets in processes).
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3.5.6. Executing PROC_ROM pass (convert switches to ROMs).
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Converted 0 switches.
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<suppressed ~21 debug messages>
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3.5.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
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Creating decoders for process `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\prefetch_engine.$proc$hardware/v2/rtl/prefetch_engine.v:58$325'.
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1/20: $3$lookahead\tile_w$324[63:0]$354
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2/20: $3$bitselwrite$pos$hardware/v2/rtl/prefetch_engine.v:105$322[31:0]$353
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3/20: $3$lookahead\tile_x$323[63:0]$339
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4/20: $3$bitselwrite$pos$hardware/v2/rtl/prefetch_engine.v:87$321[31:0]$338
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5/20: $2$lookahead\tile_w$324[63:0]$337
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6/20: $2$lookahead\tile_x$323[63:0]$336
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7/20: $2$bitselwrite$pos$hardware/v2/rtl/prefetch_engine.v:105$322[31:0]$335
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8/20: $2$bitselwrite$pos$hardware/v2/rtl/prefetch_engine.v:87$321[31:0]$334
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9/20: $0\mem_req[0:0]
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10/20: $0\fetch_done[0:0]
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11/20: $1$lookahead\tile_w$324[63:0]$333
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12/20: $1$lookahead\tile_x$323[63:0]$332
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13/20: $1$bitselwrite$pos$hardware/v2/rtl/prefetch_engine.v:105$322[31:0]$331
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14/20: $1$bitselwrite$pos$hardware/v2/rtl/prefetch_engine.v:87$321[31:0]$330
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15/20: $0\byte_idx[3:0]
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16/20: $0\fetch_busy[0:0]
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17/20: $0\state[1:0]
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18/20: $0\mem_wdata[7:0]
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19/20: $0\mem_addr[22:0]
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20/20: $0\mem_wr[0:0]
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Creating decoders for process `\memory_manager.$proc$hardware/v2/rtl/memory_manager.v:157$238'.
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1/46: $5$lookahead\bank_ready$237[1:0]$292
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2/46: $3$bitselwrite$pos$hardware/v2/rtl/memory_manager.v:247$227[0:0]$291
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3/46: $4$lookahead\bank_ready$237[1:0]$278
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4/46: $3$lookahead\bank_ready$237[1:0]$277
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5/46: $2$bitselwrite$pos$hardware/v2/rtl/memory_manager.v:247$227[0:0]$276
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6/46: $2$lookahead\bank_ready$237[1:0]$264
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7/46: $2$bitselwrite$pos$hardware/v2/rtl/memory_manager.v:183$226[0:0]$257
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8/46: $2$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$229_EN[63:0]$263
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9/46: $2$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$229_DATA[63:0]$262
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10/46: $2$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$229_ADDR[0:0]$261
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11/46: $2$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$228_EN[63:0]$260
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12/46: $2$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$228_DATA[63:0]$259
|
|
13/46: $2$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$228_ADDR[0:0]$258
|
|
14/46: $1$lookahead\bank_ready$237[1:0]$256
|
|
15/46: $0\pf_start[0:0]
|
|
16/46: $0\result_ready[0:0]
|
|
17/46: $0\job_done[0:0]
|
|
18/46: $1$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$229_EN[63:0]$255
|
|
19/46: $1$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$229_DATA[63:0]$254
|
|
20/46: $1$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$229_ADDR[0:0]$253
|
|
21/46: $1$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$228_EN[63:0]$252
|
|
22/46: $1$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$228_DATA[63:0]$251
|
|
23/46: $1$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$228_ADDR[0:0]$250
|
|
24/46: $1$bitselwrite$pos$hardware/v2/rtl/memory_manager.v:247$227[0:0]$249
|
|
25/46: $1$bitselwrite$pos$hardware/v2/rtl/memory_manager.v:183$226[0:0]$248
|
|
26/46: $0\wr_mem_wdata[7:0]
|
|
27/46: $0\wr_mem_addr[22:0]
|
|
28/46: $0\wr_mem_req[0:0]
|
|
29/46: $0\pf_pending_bank[0:0]
|
|
30/46: $0\pf_pending_w[22:0]
|
|
31/46: $0\pf_pending_x[22:0]
|
|
32/46: $0\pf_pending[0:0]
|
|
33/46: $0\pf_target_bank[0:0]
|
|
34/46: $0\pf_w_addr[22:0]
|
|
35/46: $0\pf_x_addr[22:0]
|
|
36/46: $0\current_bank[0:0]
|
|
37/46: $0\tile_idx[15:0]
|
|
38/46: $0\n_tiles_reg[15:0]
|
|
39/46: $0\result_addr_reg[22:0]
|
|
40/46: $0\w_base_reg[22:0]
|
|
41/46: $0\x_base_reg[22:0]
|
|
42/46: $0\state[2:0]
|
|
43/46: $0\tile_last[0:0]
|
|
44/46: $0\weight_data[63:0]
|
|
45/46: $0\input_data[63:0]
|
|
46/46: $0\operand_valid[0:0]
|
|
|
|
3.5.8. Executing PROC_DLATCH pass (convert process syncs to latches).
|
|
|
|
3.5.9. Executing PROC_DFF pass (convert process syncs to FFs).
|
|
Creating register for signal `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\prefetch_engine.\mem_req' using process `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\prefetch_engine.$proc$hardware/v2/rtl/prefetch_engine.v:58$325'.
|
|
created $dff cell `$procdff$1066' with positive edge clock.
|
|
Creating register for signal `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\prefetch_engine.\mem_wr' using process `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\prefetch_engine.$proc$hardware/v2/rtl/prefetch_engine.v:58$325'.
|
|
created $dff cell `$procdff$1067' with positive edge clock.
|
|
Creating register for signal `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\prefetch_engine.\mem_addr' using process `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\prefetch_engine.$proc$hardware/v2/rtl/prefetch_engine.v:58$325'.
|
|
created $dff cell `$procdff$1068' with positive edge clock.
|
|
Creating register for signal `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\prefetch_engine.\mem_wdata' using process `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\prefetch_engine.$proc$hardware/v2/rtl/prefetch_engine.v:58$325'.
|
|
created $dff cell `$procdff$1069' with positive edge clock.
|
|
Creating register for signal `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\prefetch_engine.\state' using process `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\prefetch_engine.$proc$hardware/v2/rtl/prefetch_engine.v:58$325'.
|
|
created $dff cell `$procdff$1070' with positive edge clock.
|
|
Creating register for signal `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\prefetch_engine.\fetch_busy' using process `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\prefetch_engine.$proc$hardware/v2/rtl/prefetch_engine.v:58$325'.
|
|
created $dff cell `$procdff$1071' with positive edge clock.
|
|
Creating register for signal `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\prefetch_engine.\fetch_done' using process `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\prefetch_engine.$proc$hardware/v2/rtl/prefetch_engine.v:58$325'.
|
|
created $dff cell `$procdff$1072' with positive edge clock.
|
|
Creating register for signal `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\prefetch_engine.\tile_x' using process `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\prefetch_engine.$proc$hardware/v2/rtl/prefetch_engine.v:58$325'.
|
|
created $dff cell `$procdff$1073' with positive edge clock.
|
|
Creating register for signal `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\prefetch_engine.\tile_w' using process `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\prefetch_engine.$proc$hardware/v2/rtl/prefetch_engine.v:58$325'.
|
|
created $dff cell `$procdff$1074' with positive edge clock.
|
|
Creating register for signal `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\prefetch_engine.\byte_idx' using process `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\prefetch_engine.$proc$hardware/v2/rtl/prefetch_engine.v:58$325'.
|
|
created $dff cell `$procdff$1075' with positive edge clock.
|
|
Creating register for signal `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\prefetch_engine.$bitselwrite$pos$hardware/v2/rtl/prefetch_engine.v:87$321' using process `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\prefetch_engine.$proc$hardware/v2/rtl/prefetch_engine.v:58$325'.
|
|
created $dff cell `$procdff$1076' with positive edge clock.
|
|
Creating register for signal `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\prefetch_engine.$bitselwrite$pos$hardware/v2/rtl/prefetch_engine.v:105$322' using process `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\prefetch_engine.$proc$hardware/v2/rtl/prefetch_engine.v:58$325'.
|
|
created $dff cell `$procdff$1077' with positive edge clock.
|
|
Creating register for signal `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\prefetch_engine.$lookahead\tile_x$323' using process `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\prefetch_engine.$proc$hardware/v2/rtl/prefetch_engine.v:58$325'.
|
|
created $dff cell `$procdff$1078' with positive edge clock.
|
|
Creating register for signal `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\prefetch_engine.$lookahead\tile_w$324' using process `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\prefetch_engine.$proc$hardware/v2/rtl/prefetch_engine.v:58$325'.
|
|
created $dff cell `$procdff$1079' with positive edge clock.
|
|
Creating register for signal `\memory_manager.\job_done' using process `\memory_manager.$proc$hardware/v2/rtl/memory_manager.v:157$238'.
|
|
created $dff cell `$procdff$1080' with positive edge clock.
|
|
Creating register for signal `\memory_manager.\operand_valid' using process `\memory_manager.$proc$hardware/v2/rtl/memory_manager.v:157$238'.
|
|
created $dff cell `$procdff$1081' with positive edge clock.
|
|
Creating register for signal `\memory_manager.\input_data' using process `\memory_manager.$proc$hardware/v2/rtl/memory_manager.v:157$238'.
|
|
created $dff cell `$procdff$1082' with positive edge clock.
|
|
Creating register for signal `\memory_manager.\weight_data' using process `\memory_manager.$proc$hardware/v2/rtl/memory_manager.v:157$238'.
|
|
created $dff cell `$procdff$1083' with positive edge clock.
|
|
Creating register for signal `\memory_manager.\tile_last' using process `\memory_manager.$proc$hardware/v2/rtl/memory_manager.v:157$238'.
|
|
created $dff cell `$procdff$1084' with positive edge clock.
|
|
Creating register for signal `\memory_manager.\result_ready' using process `\memory_manager.$proc$hardware/v2/rtl/memory_manager.v:157$238'.
|
|
created $dff cell `$procdff$1085' with positive edge clock.
|
|
Creating register for signal `\memory_manager.\state' using process `\memory_manager.$proc$hardware/v2/rtl/memory_manager.v:157$238'.
|
|
created $dff cell `$procdff$1086' with positive edge clock.
|
|
Creating register for signal `\memory_manager.\x_base_reg' using process `\memory_manager.$proc$hardware/v2/rtl/memory_manager.v:157$238'.
|
|
created $dff cell `$procdff$1087' with positive edge clock.
|
|
Creating register for signal `\memory_manager.\w_base_reg' using process `\memory_manager.$proc$hardware/v2/rtl/memory_manager.v:157$238'.
|
|
created $dff cell `$procdff$1088' with positive edge clock.
|
|
Creating register for signal `\memory_manager.\result_addr_reg' using process `\memory_manager.$proc$hardware/v2/rtl/memory_manager.v:157$238'.
|
|
created $dff cell `$procdff$1089' with positive edge clock.
|
|
Creating register for signal `\memory_manager.\n_tiles_reg' using process `\memory_manager.$proc$hardware/v2/rtl/memory_manager.v:157$238'.
|
|
created $dff cell `$procdff$1090' with positive edge clock.
|
|
Creating register for signal `\memory_manager.\tile_idx' using process `\memory_manager.$proc$hardware/v2/rtl/memory_manager.v:157$238'.
|
|
created $dff cell `$procdff$1091' with positive edge clock.
|
|
Creating register for signal `\memory_manager.\current_bank' using process `\memory_manager.$proc$hardware/v2/rtl/memory_manager.v:157$238'.
|
|
created $dff cell `$procdff$1092' with positive edge clock.
|
|
Creating register for signal `\memory_manager.\bank_ready' using process `\memory_manager.$proc$hardware/v2/rtl/memory_manager.v:157$238'.
|
|
created $dff cell `$procdff$1093' with positive edge clock.
|
|
Creating register for signal `\memory_manager.\pf_start' using process `\memory_manager.$proc$hardware/v2/rtl/memory_manager.v:157$238'.
|
|
created $dff cell `$procdff$1094' with positive edge clock.
|
|
Creating register for signal `\memory_manager.\pf_x_addr' using process `\memory_manager.$proc$hardware/v2/rtl/memory_manager.v:157$238'.
|
|
created $dff cell `$procdff$1095' with positive edge clock.
|
|
Creating register for signal `\memory_manager.\pf_w_addr' using process `\memory_manager.$proc$hardware/v2/rtl/memory_manager.v:157$238'.
|
|
created $dff cell `$procdff$1096' with positive edge clock.
|
|
Creating register for signal `\memory_manager.\pf_target_bank' using process `\memory_manager.$proc$hardware/v2/rtl/memory_manager.v:157$238'.
|
|
created $dff cell `$procdff$1097' with positive edge clock.
|
|
Creating register for signal `\memory_manager.\pf_pending' using process `\memory_manager.$proc$hardware/v2/rtl/memory_manager.v:157$238'.
|
|
created $dff cell `$procdff$1098' with positive edge clock.
|
|
Creating register for signal `\memory_manager.\pf_pending_x' using process `\memory_manager.$proc$hardware/v2/rtl/memory_manager.v:157$238'.
|
|
created $dff cell `$procdff$1099' with positive edge clock.
|
|
Creating register for signal `\memory_manager.\pf_pending_w' using process `\memory_manager.$proc$hardware/v2/rtl/memory_manager.v:157$238'.
|
|
created $dff cell `$procdff$1100' with positive edge clock.
|
|
Creating register for signal `\memory_manager.\pf_pending_bank' using process `\memory_manager.$proc$hardware/v2/rtl/memory_manager.v:157$238'.
|
|
created $dff cell `$procdff$1101' with positive edge clock.
|
|
Creating register for signal `\memory_manager.\wr_mem_req' using process `\memory_manager.$proc$hardware/v2/rtl/memory_manager.v:157$238'.
|
|
created $dff cell `$procdff$1102' with positive edge clock.
|
|
Creating register for signal `\memory_manager.\wr_mem_addr' using process `\memory_manager.$proc$hardware/v2/rtl/memory_manager.v:157$238'.
|
|
created $dff cell `$procdff$1103' with positive edge clock.
|
|
Creating register for signal `\memory_manager.\wr_mem_wdata' using process `\memory_manager.$proc$hardware/v2/rtl/memory_manager.v:157$238'.
|
|
created $dff cell `$procdff$1104' with positive edge clock.
|
|
Creating register for signal `\memory_manager.$bitselwrite$pos$hardware/v2/rtl/memory_manager.v:183$226' using process `\memory_manager.$proc$hardware/v2/rtl/memory_manager.v:157$238'.
|
|
created $dff cell `$procdff$1105' with positive edge clock.
|
|
Creating register for signal `\memory_manager.$bitselwrite$pos$hardware/v2/rtl/memory_manager.v:247$227' using process `\memory_manager.$proc$hardware/v2/rtl/memory_manager.v:157$238'.
|
|
created $dff cell `$procdff$1106' with positive edge clock.
|
|
Creating register for signal `\memory_manager.$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$228_ADDR' using process `\memory_manager.$proc$hardware/v2/rtl/memory_manager.v:157$238'.
|
|
created $dff cell `$procdff$1107' with positive edge clock.
|
|
Creating register for signal `\memory_manager.$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$228_DATA' using process `\memory_manager.$proc$hardware/v2/rtl/memory_manager.v:157$238'.
|
|
created $dff cell `$procdff$1108' with positive edge clock.
|
|
Creating register for signal `\memory_manager.$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$228_EN' using process `\memory_manager.$proc$hardware/v2/rtl/memory_manager.v:157$238'.
|
|
created $dff cell `$procdff$1109' with positive edge clock.
|
|
Creating register for signal `\memory_manager.$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$229_ADDR' using process `\memory_manager.$proc$hardware/v2/rtl/memory_manager.v:157$238'.
|
|
created $dff cell `$procdff$1110' with positive edge clock.
|
|
Creating register for signal `\memory_manager.$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$229_DATA' using process `\memory_manager.$proc$hardware/v2/rtl/memory_manager.v:157$238'.
|
|
created $dff cell `$procdff$1111' with positive edge clock.
|
|
Creating register for signal `\memory_manager.$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$229_EN' using process `\memory_manager.$proc$hardware/v2/rtl/memory_manager.v:157$238'.
|
|
created $dff cell `$procdff$1112' with positive edge clock.
|
|
Creating register for signal `\memory_manager.$lookahead\bank_ready$237' using process `\memory_manager.$proc$hardware/v2/rtl/memory_manager.v:157$238'.
|
|
created $dff cell `$procdff$1113' with positive edge clock.
|
|
|
|
3.5.10. Executing PROC_MEMWR pass (convert process memory writes to cells).
|
|
|
|
3.5.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
|
|
Found and cleaned up 7 empty switches in `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\prefetch_engine.$proc$hardware/v2/rtl/prefetch_engine.v:58$325'.
|
|
Removing empty process `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\prefetch_engine.$proc$hardware/v2/rtl/prefetch_engine.v:58$325'.
|
|
Found and cleaned up 14 empty switches in `\memory_manager.$proc$hardware/v2/rtl/memory_manager.v:157$238'.
|
|
Removing empty process `memory_manager.$proc$hardware/v2/rtl/memory_manager.v:157$238'.
|
|
Cleaned up 21 empty switches.
|
|
|
|
3.5.12. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module $paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\prefetch_engine.
|
|
<suppressed ~10 debug messages>
|
|
Optimizing module memory_manager.
|
|
<suppressed ~19 debug messages>
|
|
|
|
3.6. Executing CHECK pass (checking for obvious problems).
|
|
Checking module $paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\prefetch_engine...
|
|
Checking module memory_manager...
|
|
Found and reported 0 problems.
|
|
|
|
3.7. Executing FLATTEN pass (flatten design).
|
|
Deleting now unused module $paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\prefetch_engine.
|
|
<suppressed ~1 debug messages>
|
|
|
|
3.8. Executing TRIBUF pass.
|
|
|
|
3.9. Executing DEMINOUT pass (demote inout ports to input or output).
|
|
|
|
3.10. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module memory_manager.
|
|
<suppressed ~10 debug messages>
|
|
|
|
3.11. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \memory_manager..
|
|
Removed 47 unused cells and 307 unused wires.
|
|
<suppressed ~50 debug messages>
|
|
|
|
3.12. Executing CHECK pass (checking for obvious problems).
|
|
Checking module memory_manager...
|
|
Found and reported 0 problems.
|
|
|
|
3.13. Executing OPT pass (performing simple optimizations).
|
|
|
|
3.13.1. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module memory_manager.
|
|
|
|
3.13.2. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\memory_manager'.
|
|
Computing hashes of 375 cells of `\memory_manager'.
|
|
Finding duplicate cells in `\memory_manager'.
|
|
Computing hashes of 300 cells of `\memory_manager'.
|
|
Finding duplicate cells in `\memory_manager'.
|
|
Computing hashes of 297 cells of `\memory_manager'.
|
|
Finding duplicate cells in `\memory_manager'.
|
|
Computing hashes of 296 cells of `\memory_manager'.
|
|
Finding duplicate cells in `\memory_manager'.
|
|
<suppressed ~237 debug messages>
|
|
Removed a total of 79 cells.
|
|
|
|
3.13.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \memory_manager..
|
|
Creating internal representation of mux trees.
|
|
Evaluating internal representation of mux trees.
|
|
Replacing known input bits on port B of cell $procmux$1049: \operand_valid -> 1'1
|
|
Replacing known input bits on port A of cell $procmux$1047: \operand_valid -> 1'0
|
|
Analyzing evaluation results.
|
|
dead port 1/2 on $mux $flatten\u_prefetch.$procmux$375.
|
|
dead port 2/2 on $mux $flatten\u_prefetch.$procmux$372.
|
|
dead port 1/2 on $mux $flatten\u_prefetch.$procmux$412.
|
|
dead port 1/2 on $mux $flatten\u_prefetch.$procmux$420.
|
|
dead port 1/2 on $mux $flatten\u_prefetch.$procmux$394.
|
|
dead port 2/2 on $mux $flatten\u_prefetch.$procmux$391.
|
|
dead port 1/2 on $mux $procmux$677.
|
|
dead port 1/2 on $mux $procmux$671.
|
|
dead port 1/2 on $mux $procmux$665.
|
|
dead port 1/2 on $mux $procmux$659.
|
|
dead port 1/2 on $mux $procmux$653.
|
|
dead port 1/2 on $mux $procmux$647.
|
|
dead port 1/2 on $mux $procmux$620.
|
|
dead port 1/2 on $mux $procmux$610.
|
|
dead port 2/2 on $mux $procmux$607.
|
|
dead port 1/2 on $mux $procmux$584.
|
|
dead port 2/2 on $mux $procmux$581.
|
|
Removed 17 multiplexer ports.
|
|
<suppressed ~246 debug messages>
|
|
|
|
3.13.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \memory_manager.
|
|
New ctrl vector for $pmux cell $flatten\u_prefetch.$procmux$414: { $auto$opt_reduce.cc:137:opt_pmux$1118 $flatten\u_prefetch.$procmux$409_CMP }
|
|
New ctrl vector for $pmux cell $flatten\u_prefetch.$procmux$406: { $auto$opt_reduce.cc:137:opt_pmux$1120 $flatten\u_prefetch.$procmux$408_CMP }
|
|
Consolidated identical input bits for $mux cell $procmux$662:
|
|
Old ports: A=64'0000000000000000000000000000000000000000000000000000000000000000, B=64'1111111111111111111111111111111111111111111111111111111111111111, Y=$procmux$662_Y
|
|
New ports: A=1'0, B=1'1, Y=$procmux$662_Y [0]
|
|
New connections: $procmux$662_Y [63:1] = { $procmux$662_Y [0] $procmux$662_Y [0] $procmux$662_Y [0] $procmux$662_Y [0] $procmux$662_Y [0] $procmux$662_Y [0] $procmux$662_Y [0] $procmux$662_Y [0] $procmux$662_Y [0] $procmux$662_Y [0] $procmux$662_Y [0] $procmux$662_Y [0] $procmux$662_Y [0] $procmux$662_Y [0] $procmux$662_Y [0] $procmux$662_Y [0] $procmux$662_Y [0] $procmux$662_Y [0] $procmux$662_Y [0] $procmux$662_Y [0] $procmux$662_Y [0] $procmux$662_Y [0] $procmux$662_Y [0] $procmux$662_Y [0] $procmux$662_Y [0] $procmux$662_Y [0] $procmux$662_Y [0] $procmux$662_Y [0] $procmux$662_Y [0] $procmux$662_Y [0] $procmux$662_Y [0] $procmux$662_Y [0] $procmux$662_Y [0] $procmux$662_Y [0] $procmux$662_Y [0] $procmux$662_Y [0] $procmux$662_Y [0] $procmux$662_Y [0] $procmux$662_Y [0] $procmux$662_Y [0] $procmux$662_Y [0] $procmux$662_Y [0] $procmux$662_Y [0] $procmux$662_Y [0] $procmux$662_Y [0] $procmux$662_Y [0] $procmux$662_Y [0] $procmux$662_Y [0] $procmux$662_Y [0] $procmux$662_Y [0] $procmux$662_Y [0] $procmux$662_Y [0] $procmux$662_Y [0] $procmux$662_Y [0] $procmux$662_Y [0] $procmux$662_Y [0] $procmux$662_Y [0] $procmux$662_Y [0] $procmux$662_Y [0] $procmux$662_Y [0] $procmux$662_Y [0] $procmux$662_Y [0] $procmux$662_Y [0] }
|
|
Consolidated identical input bits for $mux cell $procmux$644:
|
|
Old ports: A=64'0000000000000000000000000000000000000000000000000000000000000000, B=64'1111111111111111111111111111111111111111111111111111111111111111, Y=$procmux$644_Y
|
|
New ports: A=1'0, B=1'1, Y=$procmux$644_Y [0]
|
|
New connections: $procmux$644_Y [63:1] = { $procmux$644_Y [0] $procmux$644_Y [0] $procmux$644_Y [0] $procmux$644_Y [0] $procmux$644_Y [0] $procmux$644_Y [0] $procmux$644_Y [0] $procmux$644_Y [0] $procmux$644_Y [0] $procmux$644_Y [0] $procmux$644_Y [0] $procmux$644_Y [0] $procmux$644_Y [0] $procmux$644_Y [0] $procmux$644_Y [0] $procmux$644_Y [0] $procmux$644_Y [0] $procmux$644_Y [0] $procmux$644_Y [0] $procmux$644_Y [0] $procmux$644_Y [0] $procmux$644_Y [0] $procmux$644_Y [0] $procmux$644_Y [0] $procmux$644_Y [0] $procmux$644_Y [0] $procmux$644_Y [0] $procmux$644_Y [0] $procmux$644_Y [0] $procmux$644_Y [0] $procmux$644_Y [0] $procmux$644_Y [0] $procmux$644_Y [0] $procmux$644_Y [0] $procmux$644_Y [0] $procmux$644_Y [0] $procmux$644_Y [0] $procmux$644_Y [0] $procmux$644_Y [0] $procmux$644_Y [0] $procmux$644_Y [0] $procmux$644_Y [0] $procmux$644_Y [0] $procmux$644_Y [0] $procmux$644_Y [0] $procmux$644_Y [0] $procmux$644_Y [0] $procmux$644_Y [0] $procmux$644_Y [0] $procmux$644_Y [0] $procmux$644_Y [0] $procmux$644_Y [0] $procmux$644_Y [0] $procmux$644_Y [0] $procmux$644_Y [0] $procmux$644_Y [0] $procmux$644_Y [0] $procmux$644_Y [0] $procmux$644_Y [0] $procmux$644_Y [0] $procmux$644_Y [0] $procmux$644_Y [0] $procmux$644_Y [0] }
|
|
Optimizing cells in module \memory_manager.
|
|
Consolidated identical input bits for $mux cell $procmux$713:
|
|
Old ports: A=$2$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$228_EN[63:0]$260, B=64'0000000000000000000000000000000000000000000000000000000000000000, Y=$0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$228_EN[63:0]$243
|
|
New ports: A=$procmux$662_Y [0], B=1'0, Y=$0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$228_EN[63:0]$243 [0]
|
|
New connections: $0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$228_EN[63:0]$243 [63:1] = { $0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$228_EN[63:0]$243 [0] $0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$228_EN[63:0]$243 [0] $0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$228_EN[63:0]$243 [0] $0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$228_EN[63:0]$243 [0] $0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$228_EN[63:0]$243 [0] $0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$228_EN[63:0]$243 [0] $0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$228_EN[63:0]$243 [0] $0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$228_EN[63:0]$243 [0] $0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$228_EN[63:0]$243 [0] $0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$228_EN[63:0]$243 [0] $0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$228_EN[63:0]$243 [0] $0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$228_EN[63:0]$243 [0] $0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$228_EN[63:0]$243 [0] $0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$228_EN[63:0]$243 [0] $0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$228_EN[63:0]$243 [0] $0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$228_EN[63:0]$243 [0] $0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$228_EN[63:0]$243 [0] $0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$228_EN[63:0]$243 [0] $0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$228_EN[63:0]$243 [0] $0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$228_EN[63:0]$243 [0] $0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$228_EN[63:0]$243 [0] $0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$228_EN[63:0]$243 [0] $0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$228_EN[63:0]$243 [0] $0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$228_EN[63:0]$243 [0] $0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$228_EN[63:0]$243 [0] $0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$228_EN[63:0]$243 [0] $0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$228_EN[63:0]$243 [0] $0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$228_EN[63:0]$243 [0] $0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$228_EN[63:0]$243 [0] $0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$228_EN[63:0]$243 [0] $0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$228_EN[63:0]$243 [0] $0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$228_EN[63:0]$243 [0] $0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$228_EN[63:0]$243 [0] $0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$228_EN[63:0]$243 [0] $0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$228_EN[63:0]$243 [0] $0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$228_EN[63:0]$243 [0] $0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$228_EN[63:0]$243 [0] $0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$228_EN[63:0]$243 [0] $0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$228_EN[63:0]$243 [0] $0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$228_EN[63:0]$243 [0] $0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$228_EN[63:0]$243 [0] $0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$228_EN[63:0]$243 [0] $0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$228_EN[63:0]$243 [0] $0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$228_EN[63:0]$243 [0] $0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$228_EN[63:0]$243 [0] $0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$228_EN[63:0]$243 [0] $0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$228_EN[63:0]$243 [0] $0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$228_EN[63:0]$243 [0] $0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$228_EN[63:0]$243 [0] $0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$228_EN[63:0]$243 [0] $0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$228_EN[63:0]$243 [0] $0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$228_EN[63:0]$243 [0] $0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$228_EN[63:0]$243 [0] $0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$228_EN[63:0]$243 [0] $0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$228_EN[63:0]$243 [0] $0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$228_EN[63:0]$243 [0] $0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$228_EN[63:0]$243 [0] $0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$228_EN[63:0]$243 [0] $0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$228_EN[63:0]$243 [0] $0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$228_EN[63:0]$243 [0] $0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$228_EN[63:0]$243 [0] $0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$228_EN[63:0]$243 [0] $0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$228_EN[63:0]$243 [0] }
|
|
Consolidated identical input bits for $mux cell $procmux$704:
|
|
Old ports: A=$2$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$229_EN[63:0]$263, B=64'0000000000000000000000000000000000000000000000000000000000000000, Y=$0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$229_EN[63:0]$246
|
|
New ports: A=$procmux$644_Y [0], B=1'0, Y=$0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$229_EN[63:0]$246 [0]
|
|
New connections: $0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$229_EN[63:0]$246 [63:1] = { $0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$229_EN[63:0]$246 [0] $0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$229_EN[63:0]$246 [0] $0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$229_EN[63:0]$246 [0] $0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$229_EN[63:0]$246 [0] $0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$229_EN[63:0]$246 [0] $0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$229_EN[63:0]$246 [0] $0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$229_EN[63:0]$246 [0] $0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$229_EN[63:0]$246 [0] $0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$229_EN[63:0]$246 [0] $0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$229_EN[63:0]$246 [0] $0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$229_EN[63:0]$246 [0] $0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$229_EN[63:0]$246 [0] $0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$229_EN[63:0]$246 [0] $0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$229_EN[63:0]$246 [0] $0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$229_EN[63:0]$246 [0] $0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$229_EN[63:0]$246 [0] $0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$229_EN[63:0]$246 [0] $0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$229_EN[63:0]$246 [0] $0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$229_EN[63:0]$246 [0] $0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$229_EN[63:0]$246 [0] $0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$229_EN[63:0]$246 [0] $0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$229_EN[63:0]$246 [0] $0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$229_EN[63:0]$246 [0] $0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$229_EN[63:0]$246 [0] $0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$229_EN[63:0]$246 [0] $0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$229_EN[63:0]$246 [0] $0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$229_EN[63:0]$246 [0] $0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$229_EN[63:0]$246 [0] $0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$229_EN[63:0]$246 [0] $0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$229_EN[63:0]$246 [0] $0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$229_EN[63:0]$246 [0] $0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$229_EN[63:0]$246 [0] $0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$229_EN[63:0]$246 [0] $0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$229_EN[63:0]$246 [0] $0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$229_EN[63:0]$246 [0] $0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$229_EN[63:0]$246 [0] $0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$229_EN[63:0]$246 [0] $0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$229_EN[63:0]$246 [0] $0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$229_EN[63:0]$246 [0] $0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$229_EN[63:0]$246 [0] $0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$229_EN[63:0]$246 [0] $0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$229_EN[63:0]$246 [0] $0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$229_EN[63:0]$246 [0] $0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$229_EN[63:0]$246 [0] $0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$229_EN[63:0]$246 [0] $0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$229_EN[63:0]$246 [0] $0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$229_EN[63:0]$246 [0] $0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$229_EN[63:0]$246 [0] $0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$229_EN[63:0]$246 [0] $0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$229_EN[63:0]$246 [0] $0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$229_EN[63:0]$246 [0] $0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$229_EN[63:0]$246 [0] $0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$229_EN[63:0]$246 [0] $0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$229_EN[63:0]$246 [0] $0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$229_EN[63:0]$246 [0] $0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$229_EN[63:0]$246 [0] $0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$229_EN[63:0]$246 [0] $0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$229_EN[63:0]$246 [0] $0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$229_EN[63:0]$246 [0] $0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$229_EN[63:0]$246 [0] $0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$229_EN[63:0]$246 [0] $0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$229_EN[63:0]$246 [0] $0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$229_EN[63:0]$246 [0] }
|
|
Optimizing cells in module \memory_manager.
|
|
Performed a total of 6 changes.
|
|
|
|
3.13.5. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\memory_manager'.
|
|
Computing hashes of 281 cells of `\memory_manager'.
|
|
Finding duplicate cells in `\memory_manager'.
|
|
Computing hashes of 278 cells of `\memory_manager'.
|
|
Finding duplicate cells in `\memory_manager'.
|
|
Computing hashes of 276 cells of `\memory_manager'.
|
|
Finding duplicate cells in `\memory_manager'.
|
|
<suppressed ~15 debug messages>
|
|
Removed a total of 5 cells.
|
|
|
|
3.13.6. Executing OPT_DFF pass (perform DFF optimizations).
|
|
|
|
3.13.7. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \memory_manager..
|
|
Removed 0 unused cells and 101 unused wires.
|
|
<suppressed ~1 debug messages>
|
|
|
|
3.13.8. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module memory_manager.
|
|
|
|
3.13.9. Rerunning OPT passes. (Maybe there is more to do..)
|
|
|
|
3.13.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \memory_manager..
|
|
Creating internal representation of mux trees.
|
|
Evaluating internal representation of mux trees.
|
|
Analyzing evaluation results.
|
|
Removed 0 multiplexer ports.
|
|
<suppressed ~225 debug messages>
|
|
|
|
3.13.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \memory_manager.
|
|
Performed a total of 0 changes.
|
|
|
|
3.13.12. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\memory_manager'.
|
|
Computing hashes of 276 cells of `\memory_manager'.
|
|
Finding duplicate cells in `\memory_manager'.
|
|
Removed a total of 0 cells.
|
|
|
|
3.13.13. Executing OPT_DFF pass (perform DFF optimizations).
|
|
|
|
3.13.14. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \memory_manager..
|
|
|
|
3.13.15. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module memory_manager.
|
|
|
|
3.13.16. Finished fast OPT passes. (There is nothing left to do.)
|
|
|
|
3.14. Executing FSM pass (extract and optimize FSM).
|
|
|
|
3.14.1. Executing FSM_DETECT pass (finding FSMs in design).
|
|
Found FSM state register memory_manager.u_prefetch.state.
|
|
Not marking memory_manager.u_prefetch.mem_wdata as FSM state register:
|
|
Users of register don't seem to benefit from recoding.
|
|
Found FSM state register memory_manager.state.
|
|
|
|
3.14.2. Executing FSM_EXTRACT pass (extracting FSM from design).
|
|
Extracting FSM `\u_prefetch.state' from module `\memory_manager'.
|
|
found $dff cell for state register: $flatten\u_prefetch.$procdff$1070
|
|
root of input selection tree: $flatten\u_prefetch.$0\state[1:0]
|
|
found reset state: 2'00 (guessed from mux tree)
|
|
found ctrl input: \rst
|
|
found ctrl input: $flatten\u_prefetch.$procmux$407_CMP
|
|
found ctrl input: $flatten\u_prefetch.$procmux$373_CMP
|
|
found ctrl input: $flatten\u_prefetch.$procmux$392_CMP
|
|
found ctrl input: $flatten\u_prefetch.$procmux$410_CMP
|
|
found state code: 2'00
|
|
found ctrl input: \mem_ready
|
|
found ctrl input: $flatten\u_prefetch.$eq$hardware/v2/rtl/prefetch_engine.v:106$364_Y
|
|
found state code: 2'11
|
|
found state code: 2'10
|
|
found ctrl input: \pf_start
|
|
found state code: 2'01
|
|
found ctrl output: $flatten\u_prefetch.$procmux$410_CMP
|
|
found ctrl output: $flatten\u_prefetch.$procmux$392_CMP
|
|
found ctrl output: $flatten\u_prefetch.$procmux$373_CMP
|
|
found ctrl output: $flatten\u_prefetch.$procmux$407_CMP
|
|
ctrl inputs: { $flatten\u_prefetch.$eq$hardware/v2/rtl/prefetch_engine.v:106$364_Y \pf_start \mem_ready \rst }
|
|
ctrl outputs: { $flatten\u_prefetch.$0\state[1:0] $flatten\u_prefetch.$procmux$373_CMP $flatten\u_prefetch.$procmux$392_CMP $flatten\u_prefetch.$procmux$407_CMP $flatten\u_prefetch.$procmux$410_CMP }
|
|
transition: 2'00 4'-0-0 -> 2'00 6'000001
|
|
transition: 2'00 4'-1-0 -> 2'01 6'010001
|
|
transition: 2'00 4'---1 -> 2'00 6'000001
|
|
transition: 2'10 4'--00 -> 2'10 6'101000
|
|
transition: 2'10 4'0-10 -> 2'10 6'101000
|
|
transition: 2'10 4'1-10 -> 2'11 6'111000
|
|
transition: 2'10 4'---1 -> 2'00 6'001000
|
|
transition: 2'01 4'--00 -> 2'01 6'010100
|
|
transition: 2'01 4'0-10 -> 2'01 6'010100
|
|
transition: 2'01 4'1-10 -> 2'10 6'100100
|
|
transition: 2'01 4'---1 -> 2'00 6'000100
|
|
transition: 2'11 4'---0 -> 2'00 6'000010
|
|
transition: 2'11 4'---1 -> 2'00 6'000010
|
|
Extracting FSM `\state' from module `\memory_manager'.
|
|
found $dff cell for state register: $procdff$1086
|
|
root of input selection tree: $0\state[2:0]
|
|
found reset state: 3'000 (guessed from mux tree)
|
|
found ctrl input: \rst
|
|
found ctrl input: $eq$hardware/v2/rtl/memory_manager.v:151$231_Y
|
|
found ctrl input: $eq$hardware/v2/rtl/memory_manager.v:151$230_Y
|
|
found ctrl input: $procmux$691_CMP
|
|
found ctrl input: $procmux$1017_CMP
|
|
found ctrl input: $procmux$1001_CMP
|
|
found ctrl input: $procmux$1062_CMP
|
|
found state code: 3'000
|
|
found ctrl input: \mem_ready
|
|
found state code: 3'101
|
|
found ctrl input: $logic_and$hardware/v2/rtl/memory_manager.v:284$320_Y
|
|
found state code: 3'100
|
|
found ctrl input: $logic_and$hardware/v2/rtl/memory_manager.v:245$290_Y
|
|
found ctrl input: $eq$hardware/v2/rtl/memory_manager.v:252$303_Y
|
|
found state code: 3'011
|
|
found ctrl input: $logic_or$hardware/v2/rtl/memory_manager.v:227$281_Y
|
|
found state code: 3'010
|
|
found ctrl input: \job_start
|
|
found state code: 3'001
|
|
found ctrl output: $eq$hardware/v2/rtl/memory_manager.v:151$231_Y
|
|
found ctrl output: $eq$hardware/v2/rtl/memory_manager.v:151$230_Y
|
|
found ctrl output: $procmux$691_CMP
|
|
found ctrl output: $procmux$1017_CMP
|
|
found ctrl output: $procmux$1001_CMP
|
|
found ctrl output: $procmux$1062_CMP
|
|
ctrl inputs: { $logic_and$hardware/v2/rtl/memory_manager.v:284$320_Y $eq$hardware/v2/rtl/memory_manager.v:252$303_Y $logic_and$hardware/v2/rtl/memory_manager.v:245$290_Y $logic_or$hardware/v2/rtl/memory_manager.v:227$281_Y \mem_ready \job_start \rst }
|
|
ctrl outputs: { $procmux$1062_CMP $procmux$1017_CMP $procmux$1001_CMP $procmux$691_CMP $0\state[2:0] $eq$hardware/v2/rtl/memory_manager.v:151$231_Y $eq$hardware/v2/rtl/memory_manager.v:151$230_Y }
|
|
transition: 3'000 7'-----00 -> 3'000 9'100000000
|
|
transition: 3'000 7'-----10 -> 3'001 9'100000100
|
|
transition: 3'000 7'------1 -> 3'000 9'100000000
|
|
transition: 3'100 7'------0 -> 3'101 9'000010101
|
|
transition: 3'100 7'------1 -> 3'000 9'000000001
|
|
transition: 3'010 7'--0---0 -> 3'010 9'010001000
|
|
transition: 3'010 7'-01---0 -> 3'010 9'010001000
|
|
transition: 3'010 7'-11---0 -> 3'011 9'010001100
|
|
transition: 3'010 7'------1 -> 3'000 9'010000000
|
|
transition: 3'001 7'---0--0 -> 3'001 9'001000100
|
|
transition: 3'001 7'---1--0 -> 3'010 9'001001000
|
|
transition: 3'001 7'------1 -> 3'000 9'001000000
|
|
transition: 3'101 7'----0-0 -> 3'101 9'000010110
|
|
transition: 3'101 7'----1-0 -> 3'000 9'000000010
|
|
transition: 3'101 7'------1 -> 3'000 9'000000010
|
|
transition: 3'011 7'0-----0 -> 3'011 9'000101100
|
|
transition: 3'011 7'1-----0 -> 3'100 9'000110000
|
|
transition: 3'011 7'------1 -> 3'000 9'000100000
|
|
|
|
3.14.3. Executing FSM_OPT pass (simple optimizations of FSMs).
|
|
Optimizing FSM `$fsm$\state$1127' from module `\memory_manager'.
|
|
Optimizing FSM `$fsm$\u_prefetch.state$1121' from module `\memory_manager'.
|
|
Merging pattern 4'---0 and 4'---1 from group (3 0 6'000010).
|
|
Merging pattern 4'---1 and 4'---0 from group (3 0 6'000010).
|
|
|
|
3.14.4. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \memory_manager..
|
|
Removed 27 unused cells and 27 unused wires.
|
|
<suppressed ~28 debug messages>
|
|
|
|
3.14.5. Executing FSM_OPT pass (simple optimizations of FSMs).
|
|
Optimizing FSM `$fsm$\u_prefetch.state$1121' from module `\memory_manager'.
|
|
Removing unused output signal $flatten\u_prefetch.$0\state[1:0] [0].
|
|
Removing unused output signal $flatten\u_prefetch.$0\state[1:0] [1].
|
|
Optimizing FSM `$fsm$\state$1127' from module `\memory_manager'.
|
|
Removing unused output signal $0\state[2:0] [0].
|
|
Removing unused output signal $0\state[2:0] [1].
|
|
Removing unused output signal $0\state[2:0] [2].
|
|
|
|
3.14.6. Executing FSM_RECODE pass (re-assigning FSM state encoding).
|
|
Recoding FSM `$fsm$\u_prefetch.state$1121' from module `\memory_manager' using `auto' encoding:
|
|
mapping auto encoding to `one-hot` for this FSM.
|
|
00 -> ---1
|
|
10 -> --1-
|
|
01 -> -1--
|
|
11 -> 1---
|
|
Recoding FSM `$fsm$\state$1127' from module `\memory_manager' using `auto' encoding:
|
|
mapping auto encoding to `one-hot` for this FSM.
|
|
000 -> -----1
|
|
100 -> ----1-
|
|
010 -> ---1--
|
|
001 -> --1---
|
|
101 -> -1----
|
|
011 -> 1-----
|
|
|
|
3.14.7. Executing FSM_INFO pass (dumping all available information on FSM cells).
|
|
|
|
FSM `$fsm$\u_prefetch.state$1121' from module `memory_manager':
|
|
-------------------------------------
|
|
|
|
Information on FSM $fsm$\u_prefetch.state$1121 (\u_prefetch.state):
|
|
|
|
Number of input signals: 4
|
|
Number of output signals: 4
|
|
Number of state bits: 4
|
|
|
|
Input signals:
|
|
0: \rst
|
|
1: \mem_ready
|
|
2: \pf_start
|
|
3: $flatten\u_prefetch.$eq$hardware/v2/rtl/prefetch_engine.v:106$364_Y
|
|
|
|
Output signals:
|
|
0: $flatten\u_prefetch.$procmux$410_CMP
|
|
1: $flatten\u_prefetch.$procmux$407_CMP
|
|
2: $flatten\u_prefetch.$procmux$392_CMP
|
|
3: $flatten\u_prefetch.$procmux$373_CMP
|
|
|
|
State encoding:
|
|
0: 4'---1 <RESET STATE>
|
|
1: 4'--1-
|
|
2: 4'-1--
|
|
3: 4'1---
|
|
|
|
Transition Table (state_in, ctrl_in, state_out, ctrl_out):
|
|
0: 0 4'-0-0 -> 0 4'0001
|
|
1: 0 4'---1 -> 0 4'0001
|
|
2: 0 4'-1-0 -> 2 4'0001
|
|
3: 1 4'---1 -> 0 4'1000
|
|
4: 1 4'--00 -> 1 4'1000
|
|
5: 1 4'0-10 -> 1 4'1000
|
|
6: 1 4'1-10 -> 3 4'1000
|
|
7: 2 4'---1 -> 0 4'0100
|
|
8: 2 4'1-10 -> 1 4'0100
|
|
9: 2 4'--00 -> 2 4'0100
|
|
10: 2 4'0-10 -> 2 4'0100
|
|
11: 3 4'---- -> 0 4'0010
|
|
|
|
-------------------------------------
|
|
|
|
FSM `$fsm$\state$1127' from module `memory_manager':
|
|
-------------------------------------
|
|
|
|
Information on FSM $fsm$\state$1127 (\state):
|
|
|
|
Number of input signals: 7
|
|
Number of output signals: 6
|
|
Number of state bits: 6
|
|
|
|
Input signals:
|
|
0: \rst
|
|
1: \job_start
|
|
2: \mem_ready
|
|
3: $logic_or$hardware/v2/rtl/memory_manager.v:227$281_Y
|
|
4: $logic_and$hardware/v2/rtl/memory_manager.v:245$290_Y
|
|
5: $eq$hardware/v2/rtl/memory_manager.v:252$303_Y
|
|
6: $logic_and$hardware/v2/rtl/memory_manager.v:284$320_Y
|
|
|
|
Output signals:
|
|
0: $eq$hardware/v2/rtl/memory_manager.v:151$230_Y
|
|
1: $eq$hardware/v2/rtl/memory_manager.v:151$231_Y
|
|
2: $procmux$691_CMP
|
|
3: $procmux$1001_CMP
|
|
4: $procmux$1017_CMP
|
|
5: $procmux$1062_CMP
|
|
|
|
State encoding:
|
|
0: 6'-----1 <RESET STATE>
|
|
1: 6'----1-
|
|
2: 6'---1--
|
|
3: 6'--1---
|
|
4: 6'-1----
|
|
5: 6'1-----
|
|
|
|
Transition Table (state_in, ctrl_in, state_out, ctrl_out):
|
|
0: 0 7'-----00 -> 0 6'100000
|
|
1: 0 7'------1 -> 0 6'100000
|
|
2: 0 7'-----10 -> 3 6'100000
|
|
3: 1 7'------1 -> 0 6'000001
|
|
4: 1 7'------0 -> 4 6'000001
|
|
5: 2 7'------1 -> 0 6'010000
|
|
6: 2 7'--0---0 -> 2 6'010000
|
|
7: 2 7'-01---0 -> 2 6'010000
|
|
8: 2 7'-11---0 -> 5 6'010000
|
|
9: 3 7'------1 -> 0 6'001000
|
|
10: 3 7'---1--0 -> 2 6'001000
|
|
11: 3 7'---0--0 -> 3 6'001000
|
|
12: 4 7'----1-0 -> 0 6'000010
|
|
13: 4 7'------1 -> 0 6'000010
|
|
14: 4 7'----0-0 -> 4 6'000010
|
|
15: 5 7'------1 -> 0 6'000100
|
|
16: 5 7'1-----0 -> 1 6'000100
|
|
17: 5 7'0-----0 -> 5 6'000100
|
|
|
|
-------------------------------------
|
|
|
|
3.14.8. Executing FSM_MAP pass (mapping FSMs to basic logic).
|
|
Mapping FSM `$fsm$\u_prefetch.state$1121' from module `\memory_manager'.
|
|
Mapping FSM `$fsm$\state$1127' from module `\memory_manager'.
|
|
|
|
3.15. Executing OPT pass (performing simple optimizations).
|
|
|
|
3.15.1. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module memory_manager.
|
|
<suppressed ~11 debug messages>
|
|
|
|
3.15.2. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\memory_manager'.
|
|
Computing hashes of 299 cells of `\memory_manager'.
|
|
Finding duplicate cells in `\memory_manager'.
|
|
Computing hashes of 295 cells of `\memory_manager'.
|
|
Finding duplicate cells in `\memory_manager'.
|
|
<suppressed ~12 debug messages>
|
|
Removed a total of 4 cells.
|
|
|
|
3.15.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \memory_manager..
|
|
Creating internal representation of mux trees.
|
|
Evaluating internal representation of mux trees.
|
|
Analyzing evaluation results.
|
|
Removed 0 multiplexer ports.
|
|
<suppressed ~208 debug messages>
|
|
|
|
3.15.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \memory_manager.
|
|
Performed a total of 0 changes.
|
|
|
|
3.15.5. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\memory_manager'.
|
|
Computing hashes of 295 cells of `\memory_manager'.
|
|
Finding duplicate cells in `\memory_manager'.
|
|
Removed a total of 0 cells.
|
|
|
|
3.15.6. Executing OPT_DFF pass (perform DFF optimizations).
|
|
Adding SRST signal on $procdff$1084 ($dff) from module memory_manager (D = $procmux$997_Y, Q = \tile_last, rval = 1'0).
|
|
Adding EN signal on $auto$ff.cc:337:slice$1235 ($sdff) from module memory_manager (D = $procmux$997_Y, Q = \tile_last).
|
|
Adding SRST signal on $flatten\u_prefetch.$procdff$1068 ($dff) from module memory_manager (D = $flatten\u_prefetch.$procmux$538_Y, Q = \u_prefetch.mem_addr, rval = 23'00000000000000000000000).
|
|
Adding EN signal on $auto$ff.cc:337:slice$1249 ($sdff) from module memory_manager (D = $flatten\u_prefetch.$procmux$538_Y, Q = \u_prefetch.mem_addr).
|
|
Adding SRST signal on $procdff$1083 ($dff) from module memory_manager (D = $procmux$1016_Y, Q = \weight_data, rval = 64'0000000000000000000000000000000000000000000000000000000000000000).
|
|
Adding EN signal on $auto$ff.cc:337:slice$1263 ($sdff) from module memory_manager (D = $procmux$1016_Y, Q = \weight_data).
|
|
Adding SRST signal on $flatten\u_prefetch.$procdff$1067 ($dff) from module memory_manager (D = $flatten\u_prefetch.$procmux$560_Y, Q = \u_prefetch.mem_wr, rval = 1'0).
|
|
Adding EN signal on $auto$ff.cc:337:slice$1277 ($sdff) from module memory_manager (D = $flatten\u_prefetch.$procmux$560_Y, Q = \u_prefetch.mem_wr).
|
|
Adding SRST signal on $procdff$1081 ($dff) from module memory_manager (D = $procmux$1054_Y, Q = \operand_valid, rval = 1'0).
|
|
Adding EN signal on $auto$ff.cc:337:slice$1291 ($sdff) from module memory_manager (D = $procmux$1054_Y, Q = \operand_valid).
|
|
Adding SRST signal on $flatten\u_prefetch.$procdff$1066 ($dff) from module memory_manager (D = $flatten\u_prefetch.$procmux$445_Y, Q = \u_prefetch.mem_req, rval = 1'0).
|
|
Adding EN signal on $flatten\u_prefetch.$procdff$1069 ($dff) from module memory_manager (D = 8'00000000, Q = \u_prefetch.mem_wdata).
|
|
Adding SRST signal on $flatten\u_prefetch.$procdff$1071 ($dff) from module memory_manager (D = $flatten\u_prefetch.$procmux$498_Y, Q = \u_prefetch.fetch_busy, rval = 1'0).
|
|
Adding EN signal on $auto$ff.cc:337:slice$1303 ($sdff) from module memory_manager (D = $flatten\u_prefetch.$procmux$498_Y, Q = \u_prefetch.fetch_busy).
|
|
Adding SRST signal on $procdff$1092 ($dff) from module memory_manager (D = $procmux$879_Y, Q = \current_bank, rval = 1'0).
|
|
Adding EN signal on $auto$ff.cc:337:slice$1311 ($sdff) from module memory_manager (D = $procmux$879_Y, Q = \current_bank).
|
|
Adding SRST signal on $procdff$1091 ($dff) from module memory_manager (D = $procmux$895_Y, Q = \tile_idx, rval = 16'0000000000000000).
|
|
Adding EN signal on $auto$ff.cc:337:slice$1321 ($sdff) from module memory_manager (D = $procmux$895_Y, Q = \tile_idx).
|
|
Adding EN signal on $procdff$1090 ($dff) from module memory_manager (D = \n_tiles, Q = \n_tiles_reg).
|
|
Adding EN signal on $procdff$1089 ($dff) from module memory_manager (D = \result_addr, Q = \result_addr_reg).
|
|
Adding EN signal on $procdff$1088 ($dff) from module memory_manager (D = \w_base, Q = \w_base_reg).
|
|
Adding EN signal on $procdff$1087 ($dff) from module memory_manager (D = \x_base, Q = \x_base_reg).
|
|
Adding SRST signal on $procdff$1093 ($dff) from module memory_manager (D = $3$lookahead\bank_ready$237[1:0]$277, Q = \bank_ready, rval = 2'00).
|
|
Adding SRST signal on $procdff$1085 ($dff) from module memory_manager (D = $procmux$690_Y, Q = \result_ready, rval = 1'0).
|
|
Adding SRST signal on $procdff$1082 ($dff) from module memory_manager (D = $procmux$1035_Y, Q = \input_data, rval = 64'0000000000000000000000000000000000000000000000000000000000000000).
|
|
Adding EN signal on $auto$ff.cc:337:slice$1353 ($sdff) from module memory_manager (D = $procmux$1035_Y, Q = \input_data).
|
|
Adding SRST signal on $flatten\u_prefetch.$procdff$1075 ($dff) from module memory_manager (D = $flatten\u_prefetch.$procmux$483_Y, Q = \u_prefetch.byte_idx, rval = 4'0000).
|
|
Adding EN signal on $auto$ff.cc:337:slice$1367 ($sdff) from module memory_manager (D = $flatten\u_prefetch.$procmux$483_Y, Q = \u_prefetch.byte_idx).
|
|
Adding SRST signal on $procdff$1104 ($dff) from module memory_manager (D = $procmux$732_Y, Q = \wr_mem_wdata, rval = 8'00000000).
|
|
Adding EN signal on $auto$ff.cc:337:slice$1381 ($sdff) from module memory_manager (D = \result_data, Q = \wr_mem_wdata).
|
|
Adding SRST signal on $procdff$1103 ($dff) from module memory_manager (D = $procmux$739_Y, Q = \wr_mem_addr, rval = 23'00000000000000000000000).
|
|
Adding EN signal on $auto$ff.cc:337:slice$1385 ($sdff) from module memory_manager (D = \result_addr_reg, Q = \wr_mem_addr).
|
|
Adding SRST signal on $procdff$1102 ($dff) from module memory_manager (D = $procmux$745_Y, Q = \wr_mem_req, rval = 1'0).
|
|
Adding EN signal on $auto$ff.cc:337:slice$1387 ($sdff) from module memory_manager (D = $procmux$745_Y, Q = \wr_mem_req).
|
|
Adding EN signal on $procdff$1101 ($dff) from module memory_manager (D = $procmux$763_Y, Q = \pf_pending_bank).
|
|
Adding EN signal on $procdff$1100 ($dff) from module memory_manager (D = $procmux$789_Y, Q = \pf_pending_w).
|
|
Adding EN signal on $procdff$1099 ($dff) from module memory_manager (D = $procmux$815_Y, Q = \pf_pending_x).
|
|
Adding SRST signal on $procdff$1098 ($dff) from module memory_manager (D = $procmux$843_Y, Q = \pf_pending, rval = 1'0).
|
|
Adding EN signal on $flatten\u_prefetch.$procdff$1074 ($dff) from module memory_manager (D = $flatten\u_prefetch.$2$lookahead\tile_w$324[63:0]$337, Q = \u_prefetch.tile_w).
|
|
Adding EN signal on $procdff$1097 ($dff) from module memory_manager (D = \pf_pending_bank, Q = \pf_target_bank).
|
|
Adding EN signal on $flatten\u_prefetch.$procdff$1073 ($dff) from module memory_manager (D = $flatten\u_prefetch.$2$lookahead\tile_x$323[63:0]$336, Q = \u_prefetch.tile_x).
|
|
Adding SRST signal on $flatten\u_prefetch.$procdff$1072 ($dff) from module memory_manager (D = $flatten\u_prefetch.$procmux$459_Y, Q = \u_prefetch.fetch_done, rval = 1'0).
|
|
Adding EN signal on $procdff$1096 ($dff) from module memory_manager (D = \pf_pending_w, Q = \pf_w_addr).
|
|
Adding EN signal on $procdff$1095 ($dff) from module memory_manager (D = \pf_pending_x, Q = \pf_x_addr).
|
|
Adding SRST signal on $procdff$1094 ($dff) from module memory_manager (D = $procmux$682_Y, Q = \pf_start, rval = 1'0).
|
|
Adding SRST signal on $procdff$1080 ($dff) from module memory_manager (D = $flatten\u_prefetch.$procmux$450_Y, Q = \job_done, rval = 1'0).
|
|
Setting constant 0-bit at position 0 on $auto$ff.cc:337:slice$1302 ($dffe) from module memory_manager.
|
|
Setting constant 0-bit at position 1 on $auto$ff.cc:337:slice$1302 ($dffe) from module memory_manager.
|
|
Setting constant 0-bit at position 2 on $auto$ff.cc:337:slice$1302 ($dffe) from module memory_manager.
|
|
Setting constant 0-bit at position 3 on $auto$ff.cc:337:slice$1302 ($dffe) from module memory_manager.
|
|
Setting constant 0-bit at position 4 on $auto$ff.cc:337:slice$1302 ($dffe) from module memory_manager.
|
|
Setting constant 0-bit at position 5 on $auto$ff.cc:337:slice$1302 ($dffe) from module memory_manager.
|
|
Setting constant 0-bit at position 6 on $auto$ff.cc:337:slice$1302 ($dffe) from module memory_manager.
|
|
Setting constant 0-bit at position 7 on $auto$ff.cc:337:slice$1302 ($dffe) from module memory_manager.
|
|
|
|
3.15.7. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \memory_manager..
|
|
Removed 48 unused cells and 70 unused wires.
|
|
<suppressed ~49 debug messages>
|
|
|
|
3.15.8. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module memory_manager.
|
|
<suppressed ~16 debug messages>
|
|
|
|
3.15.9. Rerunning OPT passes. (Maybe there is more to do..)
|
|
|
|
3.15.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \memory_manager..
|
|
Creating internal representation of mux trees.
|
|
Evaluating internal representation of mux trees.
|
|
Analyzing evaluation results.
|
|
Removed 0 multiplexer ports.
|
|
<suppressed ~147 debug messages>
|
|
|
|
3.15.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \memory_manager.
|
|
New ctrl vector for $pmux cell $flatten\u_prefetch.$procmux$414: \u_prefetch.state [2]
|
|
New ctrl vector for $pmux cell $flatten\u_prefetch.$procmux$406: \u_prefetch.state [1]
|
|
Optimizing cells in module \memory_manager.
|
|
Performed a total of 2 changes.
|
|
|
|
3.15.12. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\memory_manager'.
|
|
Computing hashes of 350 cells of `\memory_manager'.
|
|
Finding duplicate cells in `\memory_manager'.
|
|
Computing hashes of 290 cells of `\memory_manager'.
|
|
Finding duplicate cells in `\memory_manager'.
|
|
Computing hashes of 278 cells of `\memory_manager'.
|
|
Finding duplicate cells in `\memory_manager'.
|
|
<suppressed ~216 debug messages>
|
|
Removed a total of 72 cells.
|
|
|
|
3.15.13. Executing OPT_DFF pass (perform DFF optimizations).
|
|
|
|
3.15.14. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \memory_manager..
|
|
Removed 0 unused cells and 72 unused wires.
|
|
<suppressed ~1 debug messages>
|
|
|
|
3.15.15. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module memory_manager.
|
|
|
|
3.15.16. Rerunning OPT passes. (Maybe there is more to do..)
|
|
|
|
3.15.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \memory_manager..
|
|
Creating internal representation of mux trees.
|
|
Evaluating internal representation of mux trees.
|
|
Analyzing evaluation results.
|
|
Removed 0 multiplexer ports.
|
|
<suppressed ~149 debug messages>
|
|
|
|
3.15.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \memory_manager.
|
|
Performed a total of 0 changes.
|
|
|
|
3.15.19. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\memory_manager'.
|
|
Computing hashes of 278 cells of `\memory_manager'.
|
|
Finding duplicate cells in `\memory_manager'.
|
|
Removed a total of 0 cells.
|
|
|
|
3.15.20. Executing OPT_DFF pass (perform DFF optimizations).
|
|
|
|
3.15.21. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \memory_manager..
|
|
|
|
3.15.22. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module memory_manager.
|
|
|
|
3.15.23. Finished fast OPT passes. (There is nothing left to do.)
|
|
|
|
3.16. Executing WREDUCE pass (reducing word size of cells).
|
|
Removed top 31 address bits (of 32) from memory read port memory_manager.$memrd$\bank_w$hardware/v2/rtl/memory_manager.v:232$284 (bank_w).
|
|
Removed top 31 address bits (of 32) from memory read port memory_manager.$memrd$\bank_x$hardware/v2/rtl/memory_manager.v:231$282 (bank_x).
|
|
Removed top 1 bits (of 2) from port B of cell memory_manager.$auto$opt_dff.cc:320:make_patterns_logic$1405 ($ne).
|
|
Removed top 1 bits (of 2) from port B of cell memory_manager.$auto$opt_dff.cc:320:make_patterns_logic$1401 ($ne).
|
|
Removed top 1 bits (of 2) from port B of cell memory_manager.$auto$opt_dff.cc:320:make_patterns_logic$1364 ($ne).
|
|
Removed top 1 bits (of 2) from port B of cell memory_manager.$auto$opt_dff.cc:320:make_patterns_logic$1362 ($ne).
|
|
Removed top 1 bits (of 2) from port B of cell memory_manager.$auto$opt_dff.cc:320:make_patterns_logic$1328 ($ne).
|
|
Removed top 1 bits (of 3) from port B of cell memory_manager.$auto$fsm_map.cc:77:implement_pattern_cache$1204 ($eq).
|
|
Removed top 1 bits (of 3) from port B of cell memory_manager.$auto$fsm_map.cc:77:implement_pattern_cache$1164 ($eq).
|
|
Converting cell memory_manager.$neg$hardware/v2/rtl/memory_manager.v:183$269 ($neg) from signed to unsigned.
|
|
Removed top 1 bits (of 2) from port A of cell memory_manager.$neg$hardware/v2/rtl/memory_manager.v:183$269 ($neg).
|
|
Removed top 15 bits (of 16) from port B of cell memory_manager.$eq$hardware/v2/rtl/memory_manager.v:233$286 ($eq).
|
|
Removed top 15 bits (of 16) from port B of cell memory_manager.$gt$hardware/v2/rtl/memory_manager.v:234$287 ($gt).
|
|
Removed top 19 bits (of 23) from port B of cell memory_manager.$add$hardware/v2/rtl/memory_manager.v:236$288 ($add).
|
|
Removed top 19 bits (of 23) from port B of cell memory_manager.$add$hardware/v2/rtl/memory_manager.v:237$289 ($add).
|
|
Converting cell memory_manager.$neg$hardware/v2/rtl/memory_manager.v:247$297 ($neg) from signed to unsigned.
|
|
Removed top 1 bits (of 2) from port A of cell memory_manager.$neg$hardware/v2/rtl/memory_manager.v:247$297 ($neg).
|
|
Removed top 15 bits (of 16) from port B of cell memory_manager.$add$hardware/v2/rtl/memory_manager.v:252$302 ($add).
|
|
Removed top 14 bits (of 16) from port B of cell memory_manager.$add$hardware/v2/rtl/memory_manager.v:255$304 ($add).
|
|
Removed top 14 bits (of 16) from port B of cell memory_manager.$add$hardware/v2/rtl/memory_manager.v:266$309 ($add).
|
|
Removed top 6 bits (of 23) from port Y of cell memory_manager.$add$hardware/v2/rtl/memory_manager.v:266$309 ($add).
|
|
Removed top 3 bits (of 23) from port B of cell memory_manager.$add$hardware/v2/rtl/memory_manager.v:266$311 ($add).
|
|
Removed top 15 bits (of 16) from port B of cell memory_manager.$sub$hardware/v2/rtl/memory_manager.v:277$318 ($sub).
|
|
Removed top 1 bits (of 4) from port B of cell memory_manager.$flatten\u_prefetch.$eq$hardware/v2/rtl/prefetch_engine.v:106$364 ($eq).
|
|
Removed top 25 bits (of 33) from port A of cell memory_manager.$flatten\u_prefetch.$neg$hardware/v2/rtl/prefetch_engine.v:105$361 ($neg).
|
|
Converting cell memory_manager.$flatten\u_prefetch.$neg$hardware/v2/rtl/prefetch_engine.v:105$361 ($neg) from signed to unsigned.
|
|
Removed top 1 bits (of 8) from port A of cell memory_manager.$flatten\u_prefetch.$neg$hardware/v2/rtl/prefetch_engine.v:105$361 ($neg).
|
|
Removed top 6 bits (of 23) from wire memory_manager.$add$hardware/v2/rtl/memory_manager.v:265$306_Y.
|
|
|
|
3.17. Executing PEEPOPT pass (run peephole optimizers).
|
|
|
|
3.18. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \memory_manager..
|
|
Removed 0 unused cells and 1 unused wires.
|
|
<suppressed ~1 debug messages>
|
|
|
|
3.19. Executing SHARE pass (SAT-based resource sharing).
|
|
Found 2 cells in module memory_manager that may be considered for resource sharing.
|
|
Analyzing resource sharing options for $memrd$\bank_x$hardware/v2/rtl/memory_manager.v:275$316 ($memrd):
|
|
Found 1 activation_patterns using ctrl signal { $logic_and$hardware/v2/rtl/memory_manager.v:273$315_Y $logic_and$hardware/v2/rtl/memory_manager.v:245$290_Y \state [2] \operand_valid }.
|
|
No candidates found.
|
|
Analyzing resource sharing options for $memrd$\bank_w$hardware/v2/rtl/memory_manager.v:276$317 ($memrd):
|
|
Found 1 activation_patterns using ctrl signal { $logic_and$hardware/v2/rtl/memory_manager.v:273$315_Y $logic_and$hardware/v2/rtl/memory_manager.v:245$290_Y \state [2] \operand_valid }.
|
|
No candidates found.
|
|
|
|
3.20. Executing TECHMAP pass (map to technology primitives).
|
|
|
|
3.20.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/cmp2lut.v
|
|
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/cmp2lut.v' to AST representation.
|
|
Generating RTLIL representation for module `\_90_lut_cmp_'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
3.20.2. Continuing TECHMAP pass.
|
|
No more expansions possible.
|
|
<suppressed ~62 debug messages>
|
|
|
|
3.21. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module memory_manager.
|
|
|
|
3.22. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \memory_manager..
|
|
|
|
3.23. Executing TECHMAP pass (map to technology primitives).
|
|
|
|
3.23.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/mul2dsp.v
|
|
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/mul2dsp.v' to AST representation.
|
|
Generating RTLIL representation for module `\_80_mul'.
|
|
Generating RTLIL representation for module `\_90_soft_mul'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
3.23.2. Continuing TECHMAP pass.
|
|
No more expansions possible.
|
|
<suppressed ~4 debug messages>
|
|
|
|
3.24. Executing TECHMAP pass (map to technology primitives).
|
|
|
|
3.24.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/dsp_map_18x18.v
|
|
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/dsp_map_18x18.v' to AST representation.
|
|
Generating RTLIL representation for module `$__MUL18X18'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
3.24.2. Continuing TECHMAP pass.
|
|
No more expansions possible.
|
|
<suppressed ~3 debug messages>
|
|
|
|
3.25. Executing ALUMACC pass (create $alu and $macc cells).
|
|
Extracting $alu and $macc cells in module memory_manager:
|
|
creating $macc model for $flatten\u_prefetch.$neg$hardware/v2/rtl/prefetch_engine.v:105$361 ($neg).
|
|
creating $macc model for $flatten\u_prefetch.$add$hardware/v2/rtl/prefetch_engine.v:98$352 ($add).
|
|
creating $macc model for $flatten\u_prefetch.$add$hardware/v2/rtl/prefetch_engine.v:98$351 ($add).
|
|
creating $macc model for $flatten\u_prefetch.$add$hardware/v2/rtl/prefetch_engine.v:112$367 ($add).
|
|
creating $macc model for $flatten\u_prefetch.$add$hardware/v2/rtl/prefetch_engine.v:112$366 ($add).
|
|
creating $macc model for $flatten\u_prefetch.$add$hardware/v2/rtl/prefetch_engine.v:109$365 ($add).
|
|
creating $macc model for $sub$hardware/v2/rtl/memory_manager.v:277$318 ($sub).
|
|
creating $macc model for $add$hardware/v2/rtl/memory_manager.v:266$311 ($add).
|
|
creating $macc model for $add$hardware/v2/rtl/memory_manager.v:266$309 ($add).
|
|
creating $macc model for $add$hardware/v2/rtl/memory_manager.v:265$308 ($add).
|
|
creating $macc model for $add$hardware/v2/rtl/memory_manager.v:255$304 ($add).
|
|
creating $macc model for $add$hardware/v2/rtl/memory_manager.v:252$302 ($add).
|
|
creating $macc model for $neg$hardware/v2/rtl/memory_manager.v:247$297 ($neg).
|
|
creating $macc model for $add$hardware/v2/rtl/memory_manager.v:237$289 ($add).
|
|
creating $macc model for $add$hardware/v2/rtl/memory_manager.v:236$288 ($add).
|
|
creating $macc model for $neg$hardware/v2/rtl/memory_manager.v:183$269 ($neg).
|
|
merging $macc model for $flatten\u_prefetch.$add$hardware/v2/rtl/prefetch_engine.v:112$366 into $flatten\u_prefetch.$add$hardware/v2/rtl/prefetch_engine.v:112$367.
|
|
merging $macc model for $flatten\u_prefetch.$add$hardware/v2/rtl/prefetch_engine.v:98$351 into $flatten\u_prefetch.$add$hardware/v2/rtl/prefetch_engine.v:98$352.
|
|
creating $alu model for $macc $add$hardware/v2/rtl/memory_manager.v:237$289.
|
|
creating $alu model for $macc $neg$hardware/v2/rtl/memory_manager.v:247$297.
|
|
creating $alu model for $macc $add$hardware/v2/rtl/memory_manager.v:252$302.
|
|
creating $alu model for $macc $add$hardware/v2/rtl/memory_manager.v:255$304.
|
|
creating $alu model for $macc $add$hardware/v2/rtl/memory_manager.v:265$308.
|
|
creating $alu model for $macc $add$hardware/v2/rtl/memory_manager.v:266$309.
|
|
creating $alu model for $macc $add$hardware/v2/rtl/memory_manager.v:266$311.
|
|
creating $alu model for $macc $sub$hardware/v2/rtl/memory_manager.v:277$318.
|
|
creating $alu model for $macc $flatten\u_prefetch.$add$hardware/v2/rtl/prefetch_engine.v:109$365.
|
|
creating $alu model for $macc $add$hardware/v2/rtl/memory_manager.v:236$288.
|
|
creating $alu model for $macc $flatten\u_prefetch.$add$hardware/v2/rtl/prefetch_engine.v:112$367.
|
|
creating $alu model for $macc $neg$hardware/v2/rtl/memory_manager.v:183$269.
|
|
creating $alu model for $macc $flatten\u_prefetch.$add$hardware/v2/rtl/prefetch_engine.v:98$352.
|
|
creating $alu model for $macc $flatten\u_prefetch.$neg$hardware/v2/rtl/prefetch_engine.v:105$361.
|
|
creating $alu model for $lt$hardware/v2/rtl/memory_manager.v:273$314 ($lt): new $alu
|
|
creating $alu model for $lt$hardware/v2/rtl/memory_manager.v:255$305 ($lt): new $alu
|
|
creating $alu model for $gt$hardware/v2/rtl/memory_manager.v:234$287 ($gt): merged with $sub$hardware/v2/rtl/memory_manager.v:277$318.
|
|
creating $alu model for $eq$hardware/v2/rtl/memory_manager.v:233$286 ($eq): merged with $sub$hardware/v2/rtl/memory_manager.v:277$318.
|
|
creating $alu cell for $lt$hardware/v2/rtl/memory_manager.v:255$305: $auto$alumacc.cc:548:replace_alu$1493
|
|
creating $alu cell for $lt$hardware/v2/rtl/memory_manager.v:273$314: $auto$alumacc.cc:548:replace_alu$1498
|
|
creating $alu cell for $flatten\u_prefetch.$neg$hardware/v2/rtl/prefetch_engine.v:105$361: $auto$alumacc.cc:548:replace_alu$1503
|
|
creating $alu cell for $flatten\u_prefetch.$add$hardware/v2/rtl/prefetch_engine.v:98$352: $auto$alumacc.cc:548:replace_alu$1506
|
|
creating $alu cell for $neg$hardware/v2/rtl/memory_manager.v:183$269: $auto$alumacc.cc:548:replace_alu$1509
|
|
creating $alu cell for $flatten\u_prefetch.$add$hardware/v2/rtl/prefetch_engine.v:112$367: $auto$alumacc.cc:548:replace_alu$1512
|
|
creating $alu cell for $add$hardware/v2/rtl/memory_manager.v:236$288: $auto$alumacc.cc:548:replace_alu$1515
|
|
creating $alu cell for $flatten\u_prefetch.$add$hardware/v2/rtl/prefetch_engine.v:109$365: $auto$alumacc.cc:548:replace_alu$1518
|
|
creating $alu cell for $sub$hardware/v2/rtl/memory_manager.v:277$318, $gt$hardware/v2/rtl/memory_manager.v:234$287, $eq$hardware/v2/rtl/memory_manager.v:233$286: $auto$alumacc.cc:548:replace_alu$1521
|
|
creating $alu cell for $add$hardware/v2/rtl/memory_manager.v:266$311: $auto$alumacc.cc:548:replace_alu$1532
|
|
creating $alu cell for $add$hardware/v2/rtl/memory_manager.v:265$308: $auto$alumacc.cc:548:replace_alu$1535
|
|
creating $alu cell for $add$hardware/v2/rtl/memory_manager.v:266$309: $auto$alumacc.cc:548:replace_alu$1538
|
|
creating $alu cell for $add$hardware/v2/rtl/memory_manager.v:255$304: $auto$alumacc.cc:548:replace_alu$1541
|
|
creating $alu cell for $add$hardware/v2/rtl/memory_manager.v:252$302: $auto$alumacc.cc:548:replace_alu$1544
|
|
creating $alu cell for $neg$hardware/v2/rtl/memory_manager.v:247$297: $auto$alumacc.cc:548:replace_alu$1547
|
|
creating $alu cell for $add$hardware/v2/rtl/memory_manager.v:237$289: $auto$alumacc.cc:548:replace_alu$1550
|
|
created 16 $alu and 0 $macc cells.
|
|
|
|
3.26. Executing OPT pass (performing simple optimizations).
|
|
|
|
3.26.1. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module memory_manager.
|
|
<suppressed ~8 debug messages>
|
|
|
|
3.26.2. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\memory_manager'.
|
|
Computing hashes of 282 cells of `\memory_manager'.
|
|
Finding duplicate cells in `\memory_manager'.
|
|
Removed a total of 0 cells.
|
|
|
|
3.26.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \memory_manager..
|
|
Creating internal representation of mux trees.
|
|
Evaluating internal representation of mux trees.
|
|
Analyzing evaluation results.
|
|
Removed 0 multiplexer ports.
|
|
<suppressed ~149 debug messages>
|
|
|
|
3.26.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \memory_manager.
|
|
Performed a total of 0 changes.
|
|
|
|
3.26.5. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\memory_manager'.
|
|
Computing hashes of 282 cells of `\memory_manager'.
|
|
Finding duplicate cells in `\memory_manager'.
|
|
Removed a total of 0 cells.
|
|
|
|
3.26.6. Executing OPT_DFF pass (perform DFF optimizations).
|
|
|
|
3.26.7. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \memory_manager..
|
|
Removed 2 unused cells and 6 unused wires.
|
|
<suppressed ~3 debug messages>
|
|
|
|
3.26.8. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module memory_manager.
|
|
|
|
3.26.9. Rerunning OPT passes. (Maybe there is more to do..)
|
|
|
|
3.26.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \memory_manager..
|
|
Creating internal representation of mux trees.
|
|
Evaluating internal representation of mux trees.
|
|
Analyzing evaluation results.
|
|
Removed 0 multiplexer ports.
|
|
<suppressed ~149 debug messages>
|
|
|
|
3.26.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \memory_manager.
|
|
Performed a total of 0 changes.
|
|
|
|
3.26.12. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\memory_manager'.
|
|
Computing hashes of 280 cells of `\memory_manager'.
|
|
Finding duplicate cells in `\memory_manager'.
|
|
Removed a total of 0 cells.
|
|
|
|
3.26.13. Executing OPT_DFF pass (perform DFF optimizations).
|
|
|
|
3.26.14. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \memory_manager..
|
|
|
|
3.26.15. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module memory_manager.
|
|
|
|
3.26.16. Finished fast OPT passes. (There is nothing left to do.)
|
|
|
|
3.27. Executing MEMORY pass.
|
|
|
|
3.27.1. Executing OPT_MEM pass (optimize memories).
|
|
Performed a total of 0 transformations.
|
|
|
|
3.27.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations).
|
|
Performed a total of 0 transformations.
|
|
|
|
3.27.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths).
|
|
Analyzing memory_manager.bank_w write port 0.
|
|
Analyzing memory_manager.bank_x write port 0.
|
|
|
|
3.27.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs).
|
|
|
|
3.27.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd).
|
|
Checking read port `\bank_w'[0] in module `\memory_manager': no output FF found.
|
|
Checking read port `\bank_w'[1] in module `\memory_manager': no output FF found.
|
|
Checking read port `\bank_x'[0] in module `\memory_manager': no output FF found.
|
|
Checking read port `\bank_x'[1] in module `\memory_manager': no output FF found.
|
|
Checking read port address `\bank_w'[0] in module `\memory_manager': no address FF found.
|
|
Checking read port address `\bank_w'[1] in module `\memory_manager': merged address FF to cell.
|
|
Checking read port address `\bank_x'[0] in module `\memory_manager': no address FF found.
|
|
Checking read port address `\bank_x'[1] in module `\memory_manager': merged address FF to cell.
|
|
|
|
3.27.6. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \memory_manager..
|
|
|
|
3.27.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells).
|
|
Consolidating read ports of memory memory_manager.bank_w by address:
|
|
Consolidating read ports of memory memory_manager.bank_x by address:
|
|
|
|
3.27.8. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide).
|
|
Performed a total of 0 transformations.
|
|
|
|
3.27.9. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \memory_manager..
|
|
|
|
3.27.10. Executing MEMORY_COLLECT pass (generating $mem cells).
|
|
|
|
3.28. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \memory_manager..
|
|
|
|
3.29. Executing MEMORY_LIBMAP pass (mapping memories to cells).
|
|
using FF mapping for memory memory_manager.bank_w
|
|
using FF mapping for memory memory_manager.bank_x
|
|
<suppressed ~152 debug messages>
|
|
|
|
3.30. Executing TECHMAP pass (map to technology primitives).
|
|
|
|
3.30.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/lutrams_map_trellis.v
|
|
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/lutrams_map_trellis.v' to AST representation.
|
|
Generating RTLIL representation for module `$__TRELLIS_DPR16X4_'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
3.30.2. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/brams_map_16kd.v
|
|
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/brams_map_16kd.v' to AST representation.
|
|
Generating RTLIL representation for module `$__DP16KD_'.
|
|
Generating RTLIL representation for module `$__PDPW16KD_'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
3.30.3. Continuing TECHMAP pass.
|
|
No more expansions possible.
|
|
<suppressed ~5 debug messages>
|
|
|
|
3.31. Executing OPT pass (performing simple optimizations).
|
|
|
|
3.31.1. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module memory_manager.
|
|
<suppressed ~85 debug messages>
|
|
|
|
3.31.2. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\memory_manager'.
|
|
Computing hashes of 215 cells of `\memory_manager'.
|
|
Finding duplicate cells in `\memory_manager'.
|
|
Computing hashes of 214 cells of `\memory_manager'.
|
|
Finding duplicate cells in `\memory_manager'.
|
|
Computing hashes of 213 cells of `\memory_manager'.
|
|
Finding duplicate cells in `\memory_manager'.
|
|
<suppressed ~6 debug messages>
|
|
Removed a total of 2 cells.
|
|
|
|
3.31.3. Executing OPT_DFF pass (perform DFF optimizations).
|
|
|
|
3.31.4. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \memory_manager..
|
|
Removed 0 unused cells and 67 unused wires.
|
|
<suppressed ~1 debug messages>
|
|
|
|
3.31.5. Finished fast OPT passes.
|
|
|
|
3.32. Executing MEMORY_MAP pass (converting memories to logic and flip-flops).
|
|
Mapping memory \bank_w in module \memory_manager:
|
|
created 2 $dff cells and 0 static cells of width 64.
|
|
Extracted addr FF from read port 1 of memory_manager.bank_w: $\bank_w$rdreg[1]
|
|
read interface: 1 $dff and 2 $mux cells.
|
|
write interface: 2 write mux blocks.
|
|
Mapping memory \bank_x in module \memory_manager:
|
|
created 2 $dff cells and 0 static cells of width 64.
|
|
Extracted addr FF from read port 1 of memory_manager.bank_x: $\bank_x$rdreg[1]
|
|
read interface: 1 $dff and 2 $mux cells.
|
|
write interface: 2 write mux blocks.
|
|
|
|
3.33. Executing OPT pass (performing simple optimizations).
|
|
|
|
3.33.1. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module memory_manager.
|
|
<suppressed ~4 debug messages>
|
|
|
|
3.33.2. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\memory_manager'.
|
|
Computing hashes of 228 cells of `\memory_manager'.
|
|
Finding duplicate cells in `\memory_manager'.
|
|
Computing hashes of 224 cells of `\memory_manager'.
|
|
Finding duplicate cells in `\memory_manager'.
|
|
<suppressed ~12 debug messages>
|
|
Removed a total of 4 cells.
|
|
|
|
3.33.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \memory_manager..
|
|
Creating internal representation of mux trees.
|
|
Evaluating internal representation of mux trees.
|
|
Analyzing evaluation results.
|
|
Removed 0 multiplexer ports.
|
|
<suppressed ~84 debug messages>
|
|
|
|
3.33.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \memory_manager.
|
|
Consolidated identical input bits for $pmux cell $flatten\u_prefetch.$procmux$560:
|
|
Old ports: A=1'0, B=2'00, Y=$flatten\u_prefetch.$procmux$560_Y
|
|
New connections: $flatten\u_prefetch.$procmux$560_Y = 1'0
|
|
Optimizing cells in module \memory_manager.
|
|
Performed a total of 1 changes.
|
|
|
|
3.33.5. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\memory_manager'.
|
|
Computing hashes of 223 cells of `\memory_manager'.
|
|
Finding duplicate cells in `\memory_manager'.
|
|
Removed a total of 0 cells.
|
|
|
|
3.33.6. Executing OPT_DFF pass (perform DFF optimizations).
|
|
Adding SRST signal on $\bank_x$rdreg[1] ($dff) from module memory_manager (D = $auto$rtlil.cc:3402:Mux$1560, Q = $\bank_x$rdreg[1]$q, rval = 1'0).
|
|
|
|
3.33.7. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \memory_manager..
|
|
Removed 1 unused cells and 21 unused wires.
|
|
<suppressed ~2 debug messages>
|
|
|
|
3.33.8. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module memory_manager.
|
|
|
|
3.33.9. Rerunning OPT passes. (Maybe there is more to do..)
|
|
|
|
3.33.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \memory_manager..
|
|
Creating internal representation of mux trees.
|
|
Evaluating internal representation of mux trees.
|
|
Analyzing evaluation results.
|
|
Removed 0 multiplexer ports.
|
|
<suppressed ~81 debug messages>
|
|
|
|
3.33.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \memory_manager.
|
|
Performed a total of 0 changes.
|
|
|
|
3.33.12. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\memory_manager'.
|
|
Computing hashes of 222 cells of `\memory_manager'.
|
|
Finding duplicate cells in `\memory_manager'.
|
|
Removed a total of 0 cells.
|
|
|
|
3.33.13. Executing OPT_DFF pass (perform DFF optimizations).
|
|
Adding EN signal on $memory\bank_x[1]$1723 ($dff) from module memory_manager (D = \u_prefetch.tile_x, Q = \bank_x[1]).
|
|
Adding EN signal on $memory\bank_x[0]$1721 ($dff) from module memory_manager (D = \u_prefetch.tile_x, Q = \bank_x[0]).
|
|
Adding EN signal on $memory\bank_w[0]$1699 ($dff) from module memory_manager (D = \u_prefetch.tile_w, Q = \bank_w[0]).
|
|
Adding EN signal on $memory\bank_w[1]$1701 ($dff) from module memory_manager (D = \u_prefetch.tile_w, Q = \bank_w[1]).
|
|
Setting constant 0-bit at position 0 on $auto$ff.cc:337:slice$1278 ($sdffe) from module memory_manager.
|
|
|
|
3.33.14. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \memory_manager..
|
|
Removed 4 unused cells and 4 unused wires.
|
|
<suppressed ~5 debug messages>
|
|
|
|
3.33.15. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module memory_manager.
|
|
<suppressed ~1 debug messages>
|
|
|
|
3.33.16. Rerunning OPT passes. (Maybe there is more to do..)
|
|
|
|
3.33.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \memory_manager..
|
|
Creating internal representation of mux trees.
|
|
Evaluating internal representation of mux trees.
|
|
Analyzing evaluation results.
|
|
Removed 0 multiplexer ports.
|
|
<suppressed ~71 debug messages>
|
|
|
|
3.33.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \memory_manager.
|
|
Performed a total of 0 changes.
|
|
|
|
3.33.19. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\memory_manager'.
|
|
Computing hashes of 216 cells of `\memory_manager'.
|
|
Finding duplicate cells in `\memory_manager'.
|
|
Removed a total of 0 cells.
|
|
|
|
3.33.20. Executing OPT_DFF pass (perform DFF optimizations).
|
|
|
|
3.33.21. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \memory_manager..
|
|
|
|
3.33.22. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module memory_manager.
|
|
|
|
3.33.23. Finished fast OPT passes. (There is nothing left to do.)
|
|
|
|
3.34. Executing TECHMAP pass (map to technology primitives).
|
|
|
|
3.34.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/techmap.v
|
|
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/techmap.v' to AST representation.
|
|
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
|
|
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
|
|
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
|
|
Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
|
|
Generating RTLIL representation for module `\_90_simplemap_various'.
|
|
Generating RTLIL representation for module `\_90_simplemap_registers'.
|
|
Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
|
|
Generating RTLIL representation for module `\_90_shift_shiftx'.
|
|
Generating RTLIL representation for module `\_90_fa'.
|
|
Generating RTLIL representation for module `\_90_lcu_brent_kung'.
|
|
Generating RTLIL representation for module `\_90_alu'.
|
|
Generating RTLIL representation for module `\_90_macc'.
|
|
Generating RTLIL representation for module `\_90_alumacc'.
|
|
Generating RTLIL representation for module `$__div_mod_u'.
|
|
Generating RTLIL representation for module `$__div_mod_trunc'.
|
|
Generating RTLIL representation for module `\_90_div'.
|
|
Generating RTLIL representation for module `\_90_mod'.
|
|
Generating RTLIL representation for module `$__div_mod_floor'.
|
|
Generating RTLIL representation for module `\_90_divfloor'.
|
|
Generating RTLIL representation for module `\_90_modfloor'.
|
|
Generating RTLIL representation for module `\_90_pow'.
|
|
Generating RTLIL representation for module `\_90_demux'.
|
|
Generating RTLIL representation for module `\_90_lut'.
|
|
Generating RTLIL representation for module `$connect'.
|
|
Generating RTLIL representation for module `$input_port'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
3.34.2. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v
|
|
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v' to AST representation.
|
|
Generating RTLIL representation for module `\_80_ccu2c_alu'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
3.34.3. Continuing TECHMAP pass.
|
|
Using extmapper simplemap for cells of type $dffe.
|
|
Using extmapper simplemap for cells of type $sdff.
|
|
Using extmapper simplemap for cells of type $not.
|
|
Using extmapper simplemap for cells of type $mux.
|
|
Using template $paramod$ce0ec84be7047712840b0952f343ee9e63ef75d1\_80_ccu2c_alu for cells of type $alu.
|
|
Using template $paramod$9e8c19db10db5b8954224cafa0587db20bab09bd\_90_alu for cells of type $alu.
|
|
Using template $paramod$2af30114e9bd4ccb04dad757b3f0a8f6bf0615b0\_80_ccu2c_alu for cells of type $alu.
|
|
Using template $paramod$3b7577489eb4433b1d5620cab7f3794743dee5ea\_80_ccu2c_alu for cells of type $alu.
|
|
Using template $paramod$6177de982a145c5b9397c76cce0d57e0a983739a\_80_ccu2c_alu for cells of type $alu.
|
|
Using template $paramod$6fc37af1c109ae54e8aed83fcd995c12d378ce93\_80_ccu2c_alu for cells of type $alu.
|
|
Using template $paramod$5a0392b4d8e708c73744507ba019664673a3d600\_80_ccu2c_alu for cells of type $alu.
|
|
Using extmapper simplemap for cells of type $or.
|
|
Using extmapper simplemap for cells of type $reduce_and.
|
|
Using template $paramod$a1665ef28c749ebcdbe9aecd466e644647b56463\_80_ccu2c_alu for cells of type $alu.
|
|
Using template $paramod$32a7b7b86c07519b7537abc18e96f0331f97914d\_90_alu for cells of type $alu.
|
|
Using template $paramod$7945baf943a7eaf2bd95deee6e66976c53d43b8d\_80_ccu2c_alu for cells of type $alu.
|
|
Using template $paramod$3e2546d640bb80c4407ce51aec1dbdbdc5bff143\_80_ccu2c_alu for cells of type $alu.
|
|
Using template $paramod$6df0329addda9228fcc2546de2aaf14ad26c98e1\_80_ccu2c_alu for cells of type $alu.
|
|
Using extmapper simplemap for cells of type $reduce_or.
|
|
Using extmapper simplemap for cells of type $ne.
|
|
Using extmapper simplemap for cells of type $reduce_bool.
|
|
Using extmapper simplemap for cells of type $sdffe.
|
|
Using extmapper simplemap for cells of type $and.
|
|
Using extmapper simplemap for cells of type $logic_not.
|
|
Using extmapper simplemap for cells of type $eq.
|
|
Using extmapper simplemap for cells of type $dff.
|
|
Using extmapper simplemap for cells of type $logic_or.
|
|
Using template $paramod$constmap:dd82805e02d0c05f7629d78043ee7bd4bcc370d0$paramod$5aa0fbdc3e385f336e95d2896ce5aed0c003c799\_90_shift_shiftx for cells of type $shift.
|
|
Using extmapper simplemap for cells of type $logic_and.
|
|
Analyzing pattern of constant bits for this cell:
|
|
Constant input on bit 0 of port A: 1'0
|
|
Creating constmapped module `$paramod$constmap:d8aefc1ccc4cc8f7577de99159ea22c4a240a5fa$paramod$5aa0fbdc3e385f336e95d2896ce5aed0c003c799\_90_shift_shiftx'.
|
|
|
|
3.34.35. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module $paramod$constmap:d8aefc1ccc4cc8f7577de99159ea22c4a240a5fa$paramod$5aa0fbdc3e385f336e95d2896ce5aed0c003c799\_90_shift_shiftx..
|
|
Creating internal representation of mux trees.
|
|
Evaluating internal representation of mux trees.
|
|
Analyzing evaluation results.
|
|
dead port 2/2 on $mux $procmux$3485.
|
|
Removed 1 multiplexer ports.
|
|
<suppressed ~632 debug messages>
|
|
|
|
3.34.36. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module $paramod$constmap:d8aefc1ccc4cc8f7577de99159ea22c4a240a5fa$paramod$5aa0fbdc3e385f336e95d2896ce5aed0c003c799\_90_shift_shiftx.
|
|
<suppressed ~4 debug messages>
|
|
Removed 0 unused cells and 9 unused wires.
|
|
Using template $paramod$constmap:d8aefc1ccc4cc8f7577de99159ea22c4a240a5fa$paramod$5aa0fbdc3e385f336e95d2896ce5aed0c003c799\_90_shift_shiftx for cells of type $shift.
|
|
Using template $paramod$constmap:de554f9cc18e049d5b7dc95f0bcf8e03e57019ff$paramod$1e265d9719406ee45a570be27d6567e3eeff81e5\_90_shift_shiftx for cells of type $shiftx.
|
|
Using extmapper simplemap for cells of type $pmux.
|
|
Using template $paramod$constmap:f559a679ff835ab881c809a3c11cd4b7ac7c221b$paramod$409781814c91f00d9cc7cbbb6c4394c1e0dab276\_90_shift_shiftx for cells of type $shift.
|
|
Analyzing pattern of constant bits for this cell:
|
|
Constant input on bit 0 of port A: 1'1
|
|
Constant input on bit 1 of port A: 1'1
|
|
Constant input on bit 2 of port A: 1'1
|
|
Constant input on bit 3 of port A: 1'1
|
|
Constant input on bit 4 of port A: 1'1
|
|
Constant input on bit 5 of port A: 1'1
|
|
Constant input on bit 6 of port A: 1'1
|
|
Constant input on bit 7 of port A: 1'1
|
|
Creating constmapped module `$paramod$constmap:27fc41eec160220305c22e2c40782fd680a452dd$paramod$409781814c91f00d9cc7cbbb6c4394c1e0dab276\_90_shift_shiftx'.
|
|
|
|
3.34.47. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module $paramod$constmap:27fc41eec160220305c22e2c40782fd680a452dd$paramod$409781814c91f00d9cc7cbbb6c4394c1e0dab276\_90_shift_shiftx..
|
|
Creating internal representation of mux trees.
|
|
Evaluating internal representation of mux trees.
|
|
Analyzing evaluation results.
|
|
dead port 2/2 on $mux $procmux$4621.
|
|
dead port 2/2 on $mux $procmux$4627.
|
|
dead port 2/2 on $mux $procmux$4633.
|
|
dead port 2/2 on $mux $procmux$4639.
|
|
dead port 2/2 on $mux $procmux$4645.
|
|
dead port 2/2 on $mux $procmux$4651.
|
|
dead port 2/2 on $mux $procmux$4657.
|
|
Removed 7 multiplexer ports.
|
|
<suppressed ~645 debug messages>
|
|
|
|
3.34.48. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module $paramod$constmap:27fc41eec160220305c22e2c40782fd680a452dd$paramod$409781814c91f00d9cc7cbbb6c4394c1e0dab276\_90_shift_shiftx.
|
|
<suppressed ~27 debug messages>
|
|
Removed 0 unused cells and 12 unused wires.
|
|
Using template $paramod$constmap:27fc41eec160220305c22e2c40782fd680a452dd$paramod$409781814c91f00d9cc7cbbb6c4394c1e0dab276\_90_shift_shiftx for cells of type $shift.
|
|
Using extmapper simplemap for cells of type $xor.
|
|
Using extmapper simplemap for cells of type $pos.
|
|
Using template $paramod\_90_fa\WIDTH=32'00000000000000000000000000000010 for cells of type $fa.
|
|
Using template $paramod\_90_lcu_brent_kung\WIDTH=32'00000000000000000000000000000010 for cells of type $lcu.
|
|
Using template $paramod\_90_fa\WIDTH=32'00000000000000000000000000000100 for cells of type $fa.
|
|
Using template $paramod\_90_lcu_brent_kung\WIDTH=32'00000000000000000000000000000100 for cells of type $lcu.
|
|
No more expansions possible.
|
|
<suppressed ~1014 debug messages>
|
|
|
|
3.35. Executing OPT pass (performing simple optimizations).
|
|
|
|
3.35.1. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module memory_manager.
|
|
<suppressed ~3675 debug messages>
|
|
|
|
3.35.2. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\memory_manager'.
|
|
Computing hashes of 3703 cells of `\memory_manager'.
|
|
Finding duplicate cells in `\memory_manager'.
|
|
Computing hashes of 3528 cells of `\memory_manager'.
|
|
Finding duplicate cells in `\memory_manager'.
|
|
Computing hashes of 3507 cells of `\memory_manager'.
|
|
Finding duplicate cells in `\memory_manager'.
|
|
Computing hashes of 3493 cells of `\memory_manager'.
|
|
Finding duplicate cells in `\memory_manager'.
|
|
Computing hashes of 3484 cells of `\memory_manager'.
|
|
Finding duplicate cells in `\memory_manager'.
|
|
Computing hashes of 3483 cells of `\memory_manager'.
|
|
Finding duplicate cells in `\memory_manager'.
|
|
Computing hashes of 3482 cells of `\memory_manager'.
|
|
Finding duplicate cells in `\memory_manager'.
|
|
Computing hashes of 3481 cells of `\memory_manager'.
|
|
Finding duplicate cells in `\memory_manager'.
|
|
Computing hashes of 3480 cells of `\memory_manager'.
|
|
Finding duplicate cells in `\memory_manager'.
|
|
Computing hashes of 3479 cells of `\memory_manager'.
|
|
Finding duplicate cells in `\memory_manager'.
|
|
Computing hashes of 3478 cells of `\memory_manager'.
|
|
Finding duplicate cells in `\memory_manager'.
|
|
Computing hashes of 3477 cells of `\memory_manager'.
|
|
Finding duplicate cells in `\memory_manager'.
|
|
Computing hashes of 3476 cells of `\memory_manager'.
|
|
Finding duplicate cells in `\memory_manager'.
|
|
Computing hashes of 3475 cells of `\memory_manager'.
|
|
Finding duplicate cells in `\memory_manager'.
|
|
Computing hashes of 3474 cells of `\memory_manager'.
|
|
Finding duplicate cells in `\memory_manager'.
|
|
Computing hashes of 3473 cells of `\memory_manager'.
|
|
Finding duplicate cells in `\memory_manager'.
|
|
Computing hashes of 3472 cells of `\memory_manager'.
|
|
Finding duplicate cells in `\memory_manager'.
|
|
Computing hashes of 3471 cells of `\memory_manager'.
|
|
Finding duplicate cells in `\memory_manager'.
|
|
Computing hashes of 3470 cells of `\memory_manager'.
|
|
Finding duplicate cells in `\memory_manager'.
|
|
Computing hashes of 3469 cells of `\memory_manager'.
|
|
Finding duplicate cells in `\memory_manager'.
|
|
Computing hashes of 3468 cells of `\memory_manager'.
|
|
Finding duplicate cells in `\memory_manager'.
|
|
Computing hashes of 3467 cells of `\memory_manager'.
|
|
Finding duplicate cells in `\memory_manager'.
|
|
Computing hashes of 3466 cells of `\memory_manager'.
|
|
Finding duplicate cells in `\memory_manager'.
|
|
Computing hashes of 3465 cells of `\memory_manager'.
|
|
Finding duplicate cells in `\memory_manager'.
|
|
Computing hashes of 3464 cells of `\memory_manager'.
|
|
Finding duplicate cells in `\memory_manager'.
|
|
Computing hashes of 3463 cells of `\memory_manager'.
|
|
Finding duplicate cells in `\memory_manager'.
|
|
<suppressed ~720 debug messages>
|
|
Removed a total of 240 cells.
|
|
|
|
3.35.3. Executing OPT_DFF pass (perform DFF optimizations).
|
|
Adding SRST signal on $auto$ff.cc:337:slice$3145 ($_SDFF_PP0_) from module memory_manager (D = $auto$simplemap.cc:189:logic_reduce$4509, Q = \u_prefetch.mem_req, rval = 1'0).
|
|
Adding SRST signal on $auto$ff.cc:337:slice$2847 ($_DFFE_PP_) from module memory_manager (D = $auto$simplemap.cc:189:logic_reduce$3768, Q = \pf_pending_bank, rval = 1'0).
|
|
|
|
3.35.4. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \memory_manager..
|
|
Removed 555 unused cells and 1183 unused wires.
|
|
<suppressed ~556 debug messages>
|
|
|
|
3.35.5. Rerunning OPT passes. (Removed registers in this run.)
|
|
|
|
3.35.6. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module memory_manager.
|
|
<suppressed ~6 debug messages>
|
|
|
|
3.35.7. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\memory_manager'.
|
|
Computing hashes of 2904 cells of `\memory_manager'.
|
|
Finding duplicate cells in `\memory_manager'.
|
|
Removed a total of 0 cells.
|
|
|
|
3.35.8. Executing OPT_DFF pass (perform DFF optimizations).
|
|
|
|
3.35.9. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \memory_manager..
|
|
|
|
3.35.10. Finished fast OPT passes.
|
|
|
|
3.36. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \memory_manager..
|
|
|
|
3.37. Executing DFFLEGALIZE pass (convert FFs to types supported by the target).
|
|
|
|
3.38. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\memory_manager'.
|
|
Computing hashes of 2906 cells of `\memory_manager'.
|
|
Finding duplicate cells in `\memory_manager'.
|
|
Removed a total of 0 cells.
|
|
|
|
3.39. Executing TECHMAP pass (map to technology primitives).
|
|
|
|
3.39.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v
|
|
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v' to AST representation.
|
|
Generating RTLIL representation for module `$_DFF_N_'.
|
|
Generating RTLIL representation for module `$_DFF_P_'.
|
|
Generating RTLIL representation for module `$_DFFE_NN_'.
|
|
Generating RTLIL representation for module `$_DFFE_PN_'.
|
|
Generating RTLIL representation for module `$_DFFE_NP_'.
|
|
Generating RTLIL representation for module `$_DFFE_PP_'.
|
|
Generating RTLIL representation for module `$_DFF_NP0_'.
|
|
Generating RTLIL representation for module `$_DFF_NP1_'.
|
|
Generating RTLIL representation for module `$_DFF_PP0_'.
|
|
Generating RTLIL representation for module `$_DFF_PP1_'.
|
|
Generating RTLIL representation for module `$_SDFF_NP0_'.
|
|
Generating RTLIL representation for module `$_SDFF_NP1_'.
|
|
Generating RTLIL representation for module `$_SDFF_PP0_'.
|
|
Generating RTLIL representation for module `$_SDFF_PP1_'.
|
|
Generating RTLIL representation for module `$_DFFE_NP0P_'.
|
|
Generating RTLIL representation for module `$_DFFE_NP1P_'.
|
|
Generating RTLIL representation for module `$_DFFE_PP0P_'.
|
|
Generating RTLIL representation for module `$_DFFE_PP1P_'.
|
|
Generating RTLIL representation for module `$_DFFE_NP0N_'.
|
|
Generating RTLIL representation for module `$_DFFE_NP1N_'.
|
|
Generating RTLIL representation for module `$_DFFE_PP0N_'.
|
|
Generating RTLIL representation for module `$_DFFE_PP1N_'.
|
|
Generating RTLIL representation for module `$_SDFFE_NP0P_'.
|
|
Generating RTLIL representation for module `$_SDFFE_NP1P_'.
|
|
Generating RTLIL representation for module `$_SDFFE_PP0P_'.
|
|
Generating RTLIL representation for module `$_SDFFE_PP1P_'.
|
|
Generating RTLIL representation for module `$_SDFFE_NP0N_'.
|
|
Generating RTLIL representation for module `$_SDFFE_NP1N_'.
|
|
Generating RTLIL representation for module `$_SDFFE_PP0N_'.
|
|
Generating RTLIL representation for module `$_SDFFE_PP1N_'.
|
|
Generating RTLIL representation for module `$_ALDFF_NP_'.
|
|
Generating RTLIL representation for module `$_ALDFF_PP_'.
|
|
Generating RTLIL representation for module `$_ALDFFE_NPN_'.
|
|
Generating RTLIL representation for module `$_ALDFFE_NPP_'.
|
|
Generating RTLIL representation for module `$_ALDFFE_PPN_'.
|
|
Generating RTLIL representation for module `$_ALDFFE_PPP_'.
|
|
Generating RTLIL representation for module `\FD1P3AX'.
|
|
Generating RTLIL representation for module `\FD1P3AY'.
|
|
Generating RTLIL representation for module `\FD1P3BX'.
|
|
Generating RTLIL representation for module `\FD1P3DX'.
|
|
Generating RTLIL representation for module `\FD1P3IX'.
|
|
Generating RTLIL representation for module `\FD1P3JX'.
|
|
Generating RTLIL representation for module `\FD1S3AX'.
|
|
Generating RTLIL representation for module `\FD1S3AY'.
|
|
Generating RTLIL representation for module `\FD1S3BX'.
|
|
Generating RTLIL representation for module `\FD1S3DX'.
|
|
Generating RTLIL representation for module `\FD1S3IX'.
|
|
Generating RTLIL representation for module `\FD1S3JX'.
|
|
Generating RTLIL representation for module `\IFS1P3BX'.
|
|
Generating RTLIL representation for module `\IFS1P3DX'.
|
|
Generating RTLIL representation for module `\IFS1P3IX'.
|
|
Generating RTLIL representation for module `\IFS1P3JX'.
|
|
Generating RTLIL representation for module `\OFS1P3BX'.
|
|
Generating RTLIL representation for module `\OFS1P3DX'.
|
|
Generating RTLIL representation for module `\OFS1P3IX'.
|
|
Generating RTLIL representation for module `\OFS1P3JX'.
|
|
Generating RTLIL representation for module `\IB'.
|
|
Generating RTLIL representation for module `\IBPU'.
|
|
Generating RTLIL representation for module `\IBPD'.
|
|
Generating RTLIL representation for module `\OB'.
|
|
Generating RTLIL representation for module `\OBZ'.
|
|
Generating RTLIL representation for module `\OBZPU'.
|
|
Generating RTLIL representation for module `\OBZPD'.
|
|
Generating RTLIL representation for module `\OBCO'.
|
|
Generating RTLIL representation for module `\BB'.
|
|
Generating RTLIL representation for module `\BBPU'.
|
|
Generating RTLIL representation for module `\BBPD'.
|
|
Generating RTLIL representation for module `\ILVDS'.
|
|
Generating RTLIL representation for module `\OLVDS'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
3.39.2. Continuing TECHMAP pass.
|
|
Using template $_SDFFE_PP0P_ for cells of type $_SDFFE_PP0P_.
|
|
Using template $_SDFF_PP0_ for cells of type $_SDFF_PP0_.
|
|
Using template $paramod$_DFF_P_\_TECHMAP_WIREINIT_Q_=1'x for cells of type $_DFF_P_.
|
|
Using template $paramod$_DFFE_PP_\_TECHMAP_WIREINIT_Q_=1'x for cells of type $_DFFE_PP_.
|
|
No more expansions possible.
|
|
<suppressed ~882 debug messages>
|
|
|
|
3.40. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module memory_manager.
|
|
|
|
3.41. Executing SIMPLEMAP pass (map simple cells to gate primitives).
|
|
|
|
3.42. Executing LATTICE_GSR pass (implement FF init values).
|
|
Handling GSR in memory_manager.
|
|
|
|
3.43. Executing ATTRMVCP pass (move or copy attributes).
|
|
|
|
3.44. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \memory_manager..
|
|
Removed 0 unused cells and 4143 unused wires.
|
|
<suppressed ~1 debug messages>
|
|
|
|
3.45. Executing CHECK pass (checking for obvious problems).
|
|
Checking module memory_manager...
|
|
Found and reported 0 problems.
|
|
|
|
3.46. Executing TECHMAP pass (map to technology primitives).
|
|
|
|
3.46.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/latches_map.v
|
|
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/latches_map.v' to AST representation.
|
|
Generating RTLIL representation for module `$_DLATCH_N_'.
|
|
Generating RTLIL representation for module `$_DLATCH_P_'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
3.46.2. Continuing TECHMAP pass.
|
|
No more expansions possible.
|
|
<suppressed ~4 debug messages>
|
|
|
|
3.47. Executing ABC9 pass.
|
|
|
|
3.47.1. Executing ABC9_OPS pass (helper functions for ABC9).
|
|
|
|
3.47.2. Executing ABC9_OPS pass (helper functions for ABC9).
|
|
|
|
3.47.3. Executing SCC pass (detecting logic loops).
|
|
Found 0 SCCs in module memory_manager.
|
|
Found 0 SCCs.
|
|
|
|
3.47.4. Executing ABC9_OPS pass (helper functions for ABC9).
|
|
|
|
3.47.5. Executing TECHMAP pass (map to technology primitives).
|
|
|
|
3.47.5.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/techmap.v
|
|
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/techmap.v' to AST representation.
|
|
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
|
|
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
|
|
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
|
|
Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
|
|
Generating RTLIL representation for module `\_90_simplemap_various'.
|
|
Generating RTLIL representation for module `\_90_simplemap_registers'.
|
|
Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
|
|
Generating RTLIL representation for module `\_90_shift_shiftx'.
|
|
Generating RTLIL representation for module `\_90_fa'.
|
|
Generating RTLIL representation for module `\_90_lcu_brent_kung'.
|
|
Generating RTLIL representation for module `\_90_alu'.
|
|
Generating RTLIL representation for module `\_90_macc'.
|
|
Generating RTLIL representation for module `\_90_alumacc'.
|
|
Generating RTLIL representation for module `$__div_mod_u'.
|
|
Generating RTLIL representation for module `$__div_mod_trunc'.
|
|
Generating RTLIL representation for module `\_90_div'.
|
|
Generating RTLIL representation for module `\_90_mod'.
|
|
Generating RTLIL representation for module `$__div_mod_floor'.
|
|
Generating RTLIL representation for module `\_90_divfloor'.
|
|
Generating RTLIL representation for module `\_90_modfloor'.
|
|
Generating RTLIL representation for module `\_90_pow'.
|
|
Generating RTLIL representation for module `\_90_demux'.
|
|
Generating RTLIL representation for module `\_90_lut'.
|
|
Generating RTLIL representation for module `$connect'.
|
|
Generating RTLIL representation for module `$input_port'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
3.47.5.2. Continuing TECHMAP pass.
|
|
No more expansions possible.
|
|
<suppressed ~166 debug messages>
|
|
|
|
3.47.6. Executing OPT pass (performing simple optimizations).
|
|
|
|
3.47.6.1. Executing OPT_EXPR pass (perform const folding).
|
|
|
|
3.47.6.2. Executing OPT_MERGE pass (detect identical cells).
|
|
Removed a total of 0 cells.
|
|
|
|
3.47.6.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Removed 0 multiplexer ports.
|
|
|
|
3.47.6.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Performed a total of 0 changes.
|
|
|
|
3.47.6.5. Executing OPT_MERGE pass (detect identical cells).
|
|
Removed a total of 0 cells.
|
|
|
|
3.47.6.6. Executing OPT_DFF pass (perform DFF optimizations).
|
|
|
|
3.47.6.7. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
|
|
3.47.6.8. Executing OPT_EXPR pass (perform const folding).
|
|
|
|
3.47.6.9. Finished fast OPT passes. (There is nothing left to do.)
|
|
|
|
3.47.7. Executing TECHMAP pass (map to technology primitives).
|
|
|
|
3.47.7.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/abc9_map.v
|
|
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/abc9_map.v' to AST representation.
|
|
Successfully finished Verilog frontend.
|
|
|
|
3.47.7.2. Continuing TECHMAP pass.
|
|
No more expansions possible.
|
|
<suppressed ~2 debug messages>
|
|
|
|
3.47.8. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/abc9_model.v
|
|
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/abc9_model.v' to AST representation.
|
|
Generating RTLIL representation for module `$__ABC9_DELAY'.
|
|
Generating RTLIL representation for module `$__ABC9_SCC_BREAKER'.
|
|
Generating RTLIL representation for module `$__DFF_N__$abc9_flop'.
|
|
Generating RTLIL representation for module `$__DFF_P__$abc9_flop'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
3.47.9. Executing ABC9_OPS pass (helper functions for ABC9).
|
|
<suppressed ~2 debug messages>
|
|
|
|
3.47.10. Executing ABC9_OPS pass (helper functions for ABC9).
|
|
|
|
3.47.11. Executing ABC9_OPS pass (helper functions for ABC9).
|
|
<suppressed ~2 debug messages>
|
|
|
|
3.47.12. Executing TECHMAP pass (map to technology primitives).
|
|
|
|
3.47.12.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/techmap.v
|
|
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/techmap.v' to AST representation.
|
|
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
|
|
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
|
|
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
|
|
Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
|
|
Generating RTLIL representation for module `\_90_simplemap_various'.
|
|
Generating RTLIL representation for module `\_90_simplemap_registers'.
|
|
Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
|
|
Generating RTLIL representation for module `\_90_shift_shiftx'.
|
|
Generating RTLIL representation for module `\_90_fa'.
|
|
Generating RTLIL representation for module `\_90_lcu_brent_kung'.
|
|
Generating RTLIL representation for module `\_90_alu'.
|
|
Generating RTLIL representation for module `\_90_macc'.
|
|
Generating RTLIL representation for module `\_90_alumacc'.
|
|
Generating RTLIL representation for module `$__div_mod_u'.
|
|
Generating RTLIL representation for module `$__div_mod_trunc'.
|
|
Generating RTLIL representation for module `\_90_div'.
|
|
Generating RTLIL representation for module `\_90_mod'.
|
|
Generating RTLIL representation for module `$__div_mod_floor'.
|
|
Generating RTLIL representation for module `\_90_divfloor'.
|
|
Generating RTLIL representation for module `\_90_modfloor'.
|
|
Generating RTLIL representation for module `\_90_pow'.
|
|
Generating RTLIL representation for module `\_90_demux'.
|
|
Generating RTLIL representation for module `\_90_lut'.
|
|
Generating RTLIL representation for module `$connect'.
|
|
Generating RTLIL representation for module `$input_port'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
3.47.12.2. Continuing TECHMAP pass.
|
|
Using template $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C for cells of type $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C.
|
|
Using extmapper simplemap for cells of type $or.
|
|
Using extmapper simplemap for cells of type $and.
|
|
Using extmapper simplemap for cells of type $not.
|
|
Using extmapper simplemap for cells of type $xor.
|
|
Using template $paramod\LUT2\INIT=4'1010 for cells of type LUT2.
|
|
Using template $paramod\LUT4\INIT=16'1001011010101010 for cells of type LUT4.
|
|
Using extmapper simplemap for cells of type $mux.
|
|
No more expansions possible.
|
|
<suppressed ~205 debug messages>
|
|
|
|
3.47.13. Executing OPT pass (performing simple optimizations).
|
|
|
|
3.47.13.1. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module memory_manager.
|
|
<suppressed ~18 debug messages>
|
|
|
|
3.47.13.2. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\memory_manager'.
|
|
Computing hashes of 59 cells of `\memory_manager'.
|
|
Finding duplicate cells in `\memory_manager'.
|
|
Computing hashes of 57 cells of `\memory_manager'.
|
|
Finding duplicate cells in `\memory_manager'.
|
|
<suppressed ~6 debug messages>
|
|
Removed a total of 2 cells.
|
|
|
|
3.47.13.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \memory_manager..
|
|
Creating internal representation of mux trees.
|
|
No muxes found in this module.
|
|
Removed 0 multiplexer ports.
|
|
|
|
3.47.13.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \memory_manager.
|
|
Performed a total of 0 changes.
|
|
|
|
3.47.13.5. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\memory_manager'.
|
|
Computing hashes of 57 cells of `\memory_manager'.
|
|
Finding duplicate cells in `\memory_manager'.
|
|
Removed a total of 0 cells.
|
|
|
|
3.47.13.6. Executing OPT_DFF pass (perform DFF optimizations).
|
|
|
|
3.47.13.7. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \memory_manager..
|
|
Removed 0 unused cells and 55 unused wires.
|
|
<suppressed ~1 debug messages>
|
|
|
|
3.47.13.8. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module memory_manager.
|
|
|
|
3.47.13.9. Rerunning OPT passes. (Maybe there is more to do..)
|
|
|
|
3.47.13.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \memory_manager..
|
|
Creating internal representation of mux trees.
|
|
No muxes found in this module.
|
|
Removed 0 multiplexer ports.
|
|
|
|
3.47.13.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \memory_manager.
|
|
Performed a total of 0 changes.
|
|
|
|
3.47.13.12. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\memory_manager'.
|
|
Computing hashes of 57 cells of `\memory_manager'.
|
|
Finding duplicate cells in `\memory_manager'.
|
|
Removed a total of 0 cells.
|
|
|
|
3.47.13.13. Executing OPT_DFF pass (perform DFF optimizations).
|
|
|
|
3.47.13.14. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \memory_manager..
|
|
|
|
3.47.13.15. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module memory_manager.
|
|
|
|
3.47.13.16. Finished fast OPT passes. (There is nothing left to do.)
|
|
|
|
3.47.14. Executing AIGMAP pass (map logic to AIG).
|
|
Module memory_manager: replaced 18 cells with 120 new cells, skipped 39 cells.
|
|
replaced 3 cell types:
|
|
14 $_MUX_
|
|
2 $_OR_
|
|
2 $_XOR_
|
|
not replaced 3 cell types:
|
|
4 $_AND_
|
|
4 $_NOT_
|
|
31 $specify2
|
|
|
|
3.47.15. Executing AIGMAP pass (map logic to AIG).
|
|
Module memory_manager: replaced 1493 cells with 9466 new cells, skipped 1413 cells.
|
|
replaced 4 cell types:
|
|
1105 $_MUX_
|
|
1 $_ORNOT_
|
|
327 $_OR_
|
|
60 $_XOR_
|
|
not replaced 5 cell types:
|
|
362 $_AND_
|
|
132 $_NOT_
|
|
1 $scopeinfo
|
|
789 TRELLIS_FF
|
|
129 $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C
|
|
|
|
3.47.15.1. Executing ABC9_OPS pass (helper functions for ABC9).
|
|
|
|
3.47.15.2. Executing ABC9_OPS pass (helper functions for ABC9).
|
|
|
|
3.47.15.3. Executing XAIGER backend.
|
|
<suppressed ~11 debug messages>
|
|
Extracted 4185 AND gates and 11738 wires from module `memory_manager' to a netlist network with 896 inputs and 750 outputs.
|
|
|
|
3.47.15.4. Executing ABC9_EXE pass (technology mapping using ABC9).
|
|
|
|
3.47.15.5. Executing ABC9.
|
|
Running ABC command: "<yosys-exe-dir>/yosys-abc" -s -f <abc-temp-dir>/abc.script 2>&1
|
|
ABC: ======== ABC command line "source <abc-temp-dir>/abc.script"
|
|
ABC: + read_lut <abc-temp-dir>/input.lut
|
|
ABC: + read_box <abc-temp-dir>/input.box
|
|
ABC: + &read <abc-temp-dir>/input.xaig
|
|
ABC: + &ps
|
|
ABC: <abc-temp-dir>/input : i/o = 896/ 750 and = 3196 lev = 40 (3.29) mem = 0.09 MB box = 129 bb = 0
|
|
ABC: + &scorr
|
|
ABC: Warning: The network is combinational.
|
|
ABC: + &sweep
|
|
ABC: + &dc2
|
|
ABC: + &dch -f -r
|
|
ABC: + &ps
|
|
ABC: <abc-temp-dir>/input : i/o = 896/ 750 and = 3447 lev = 24 (0.95) mem = 0.09 MB ch = 424 box = 108 bb = 0
|
|
ABC: cst = 0 cls = 382 lit = 424 unused = 3861 proof = 0
|
|
ABC: + &if -W 300 -v
|
|
ABC: K = 7. Memory (bytes): Truth = 0. Cut = 76. Obj = 156. Set = 780. CutMin = no
|
|
ABC: Node = 3447. Ch = 382. Total mem = 1.05 MB. Peak cut mem = 0.03 MB.
|
|
ABC: P: Del = 2687.00. Ar = 2021.0. Edge = 2622. Cut = 32074. T = 0.00 sec
|
|
ABC: P: Del = 2687.00. Ar = 2011.0. Edge = 2613. Cut = 32025. T = 0.00 sec
|
|
ABC: P: Del = 2687.00. Ar = 919.0. Edge = 2604. Cut = 34076. T = 0.00 sec
|
|
ABC: F: Del = 2680.00. Ar = 853.0. Edge = 2438. Cut = 33213. T = 0.00 sec
|
|
ABC: A: Del = 2680.00. Ar = 853.0. Edge = 2389. Cut = 32452. T = 0.00 sec
|
|
ABC: A: Del = 2680.00. Ar = 853.0. Edge = 2389. Cut = 32408. T = 0.00 sec
|
|
ABC: Total time = 0.02 sec
|
|
ABC: + &write -n <abc-temp-dir>/output.aig
|
|
ABC: + &mfs
|
|
ABC: + &ps -l
|
|
ABC: <abc-temp-dir>/input : i/o = 896/ 750 and = 2422 lev = 11 (0.93) mem = 0.07 MB box = 108 bb = 0
|
|
ABC: Mapping (K=7) : lut = 622 edge = 2309 lev = 4 (0.52) levB = 14 mem = 0.03 MB
|
|
ABC: LUT = 622 : 2=40 6.4 % 3=317 51.0 % 4=53 8.5 % 5=207 33.3 % 6=4 0.6 % 7=1 0.2 % Ave = 3.71
|
|
ABC: + &write -n <abc-temp-dir>/output.aig
|
|
ABC: + &verify
|
|
ABC: Networks are equivalent. Time = 0.03 sec
|
|
ABC: + time
|
|
ABC: elapse: 0.17 seconds, total: 0.17 seconds
|
|
|
|
3.47.15.6. Executing AIGER frontend.
|
|
<suppressed ~10 debug messages>
|
|
Removed 4102 unused cells and 6711 unused wires.
|
|
|
|
3.47.15.7. Executing ABC_OPS_REINTEGRATE pass (reintegrate ABC mapped design into module).
|
|
ABC RESULTS: $lut cells: 625
|
|
ABC RESULTS: $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C cells: 108
|
|
ABC RESULTS: input signals: 38
|
|
ABC RESULTS: output signals: 59
|
|
<suppressed ~3313 debug messages>
|
|
Removing temp directory.
|
|
|
|
3.47.16. Executing TECHMAP pass (map to technology primitives).
|
|
|
|
3.47.16.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/abc9_unmap.v
|
|
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/abc9_unmap.v' to AST representation.
|
|
Generating RTLIL representation for module `$__DFF_x__$abc9_flop'.
|
|
Generating RTLIL representation for module `$__ABC9_SCC_BREAKER'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
3.47.16.2. Continuing TECHMAP pass.
|
|
Using template $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C for cells of type $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C.
|
|
No more expansions possible.
|
|
<suppressed ~114 debug messages>
|
|
Removed 77 unused cells and 13057 unused wires.
|
|
|
|
3.48. Executing TECHMAP pass (map to technology primitives).
|
|
|
|
3.48.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v
|
|
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v' to AST representation.
|
|
Generating RTLIL representation for module `$_DFF_N_'.
|
|
Generating RTLIL representation for module `$_DFF_P_'.
|
|
Generating RTLIL representation for module `$_DFFE_NN_'.
|
|
Generating RTLIL representation for module `$_DFFE_PN_'.
|
|
Generating RTLIL representation for module `$_DFFE_NP_'.
|
|
Generating RTLIL representation for module `$_DFFE_PP_'.
|
|
Generating RTLIL representation for module `$_DFF_NP0_'.
|
|
Generating RTLIL representation for module `$_DFF_NP1_'.
|
|
Generating RTLIL representation for module `$_DFF_PP0_'.
|
|
Generating RTLIL representation for module `$_DFF_PP1_'.
|
|
Generating RTLIL representation for module `$_SDFF_NP0_'.
|
|
Generating RTLIL representation for module `$_SDFF_NP1_'.
|
|
Generating RTLIL representation for module `$_SDFF_PP0_'.
|
|
Generating RTLIL representation for module `$_SDFF_PP1_'.
|
|
Generating RTLIL representation for module `$_DFFE_NP0P_'.
|
|
Generating RTLIL representation for module `$_DFFE_NP1P_'.
|
|
Generating RTLIL representation for module `$_DFFE_PP0P_'.
|
|
Generating RTLIL representation for module `$_DFFE_PP1P_'.
|
|
Generating RTLIL representation for module `$_DFFE_NP0N_'.
|
|
Generating RTLIL representation for module `$_DFFE_NP1N_'.
|
|
Generating RTLIL representation for module `$_DFFE_PP0N_'.
|
|
Generating RTLIL representation for module `$_DFFE_PP1N_'.
|
|
Generating RTLIL representation for module `$_SDFFE_NP0P_'.
|
|
Generating RTLIL representation for module `$_SDFFE_NP1P_'.
|
|
Generating RTLIL representation for module `$_SDFFE_PP0P_'.
|
|
Generating RTLIL representation for module `$_SDFFE_PP1P_'.
|
|
Generating RTLIL representation for module `$_SDFFE_NP0N_'.
|
|
Generating RTLIL representation for module `$_SDFFE_NP1N_'.
|
|
Generating RTLIL representation for module `$_SDFFE_PP0N_'.
|
|
Generating RTLIL representation for module `$_SDFFE_PP1N_'.
|
|
Generating RTLIL representation for module `$_ALDFF_NP_'.
|
|
Generating RTLIL representation for module `$_ALDFF_PP_'.
|
|
Generating RTLIL representation for module `$_ALDFFE_NPN_'.
|
|
Generating RTLIL representation for module `$_ALDFFE_NPP_'.
|
|
Generating RTLIL representation for module `$_ALDFFE_PPN_'.
|
|
Generating RTLIL representation for module `$_ALDFFE_PPP_'.
|
|
Generating RTLIL representation for module `\FD1P3AX'.
|
|
Generating RTLIL representation for module `\FD1P3AY'.
|
|
Generating RTLIL representation for module `\FD1P3BX'.
|
|
Generating RTLIL representation for module `\FD1P3DX'.
|
|
Generating RTLIL representation for module `\FD1P3IX'.
|
|
Generating RTLIL representation for module `\FD1P3JX'.
|
|
Generating RTLIL representation for module `\FD1S3AX'.
|
|
Generating RTLIL representation for module `\FD1S3AY'.
|
|
Generating RTLIL representation for module `\FD1S3BX'.
|
|
Generating RTLIL representation for module `\FD1S3DX'.
|
|
Generating RTLIL representation for module `\FD1S3IX'.
|
|
Generating RTLIL representation for module `\FD1S3JX'.
|
|
Generating RTLIL representation for module `\IFS1P3BX'.
|
|
Generating RTLIL representation for module `\IFS1P3DX'.
|
|
Generating RTLIL representation for module `\IFS1P3IX'.
|
|
Generating RTLIL representation for module `\IFS1P3JX'.
|
|
Generating RTLIL representation for module `\OFS1P3BX'.
|
|
Generating RTLIL representation for module `\OFS1P3DX'.
|
|
Generating RTLIL representation for module `\OFS1P3IX'.
|
|
Generating RTLIL representation for module `\OFS1P3JX'.
|
|
Generating RTLIL representation for module `\IB'.
|
|
Generating RTLIL representation for module `\IBPU'.
|
|
Generating RTLIL representation for module `\IBPD'.
|
|
Generating RTLIL representation for module `\OB'.
|
|
Generating RTLIL representation for module `\OBZ'.
|
|
Generating RTLIL representation for module `\OBZPU'.
|
|
Generating RTLIL representation for module `\OBZPD'.
|
|
Generating RTLIL representation for module `\OBCO'.
|
|
Generating RTLIL representation for module `\BB'.
|
|
Generating RTLIL representation for module `\BBPU'.
|
|
Generating RTLIL representation for module `\BBPD'.
|
|
Generating RTLIL representation for module `\ILVDS'.
|
|
Generating RTLIL representation for module `\OLVDS'.
|
|
Generating RTLIL representation for module `$lut'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
3.48.2. Continuing TECHMAP pass.
|
|
Using template $paramod$658b9ed803f0d3d335616d3858b53e0a2522f1e8$lut for cells of type $lut.
|
|
Using template $paramod$6e238df02989b317f10820a22773676e71120644$lut for cells of type $lut.
|
|
Using template $paramod$8adf7fbd410d2cc654c288d5be5f7508ee8809b0$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11000100 for cells of type $lut.
|
|
Using template $paramod$e3e4230bb990723642112b292aa705ee0cbad0d4$lut for cells of type $lut.
|
|
Using template $paramod$b287726797d0722f64e731f1134f7c05af8f1578$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10110000 for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0010 for cells of type $lut.
|
|
Using template $paramod$8512f4fb47fa9596f76cdbe5b407a5b54df368e7$lut for cells of type $lut.
|
|
Using template $paramod$b5babc618720ace64bafddb303d6f59fd10af395$lut for cells of type $lut.
|
|
Using template $paramod$464d286cc302627c2e44b6c4a8450c9bebc28389$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1001 for cells of type $lut.
|
|
Using template $paramod$86d1a43c2f1d620ff2cef866448dd1258c868fad$lut for cells of type $lut.
|
|
Using template $paramod$f12fe2ef5af134a926cc7292d32ee6988934ef95$lut for cells of type $lut.
|
|
Using template $paramod$251994398653c4cf8de320f1e306e535d5d2d624$lut for cells of type $lut.
|
|
Using template $paramod$ac977fdb827743bc5fe009760f4eb846eab5907d$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1000 for cells of type $lut.
|
|
Using template $paramod$a34c3a113f6322a855b111888cced8dfe18cd967$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00101100 for cells of type $lut.
|
|
Using template $paramod$ff315d5084ed3c80e34901fe05add0db5feb0b93$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10000000 for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0100 for cells of type $lut.
|
|
Using template $paramod$a249737383b43f5fd82429cdb8b49973f28934bb$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11101010 for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10101000 for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00100011 for cells of type $lut.
|
|
Using template $paramod$d7fff18f4a1584e5dce7e6dfbc06d7e09d60216e$lut for cells of type $lut.
|
|
Using template $paramod$720c7833e3169f9dadd6b9edcfecd044664bf968$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0110 for cells of type $lut.
|
|
Using template $paramod$4abe3dc2dfc6ad230292110951d5330af081367b$lut for cells of type $lut.
|
|
Using template $paramod$98a845e3fcf8cfe488f4d5055f2cf6fcbfd5da81$lut for cells of type $lut.
|
|
Using template $paramod$4976b5f7a7b9f6e596e742c7d9dd919d8c62448f$lut for cells of type $lut.
|
|
Using template $paramod$2b26b4922e8ee12b5b5d0f35a909c50a2c48701c$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11100010 for cells of type $lut.
|
|
Using template $paramod$9664b2f5fd61944d7798b30cde43b99ccda87303$lut for cells of type $lut.
|
|
Using template $paramod$f81ecf3eb88491df8fecf1e071b57debc429282a$lut for cells of type $lut.
|
|
Using template $paramod$9c65fdfac74256c2eb67dd209b598e25d1f0a099$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11111000 for cells of type $lut.
|
|
Using template $paramod$c50474b30f5187625746303b03b42bd612263de0$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1110 for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1011 for cells of type $lut.
|
|
Using template $paramod$a5a9d48041af65bd5d7b6a1f6014e7ed22f6b87a$lut for cells of type $lut.
|
|
Using template $paramod$6ed7ed61521c2ee3ec4e86802248d93207c213e1$lut for cells of type $lut.
|
|
Using template $paramod$b27834385f52eaf4ed276ecbffb1b05d9c8a8b56$lut for cells of type $lut.
|
|
Using template $paramod$54feebfc143584f0d3dec83621f4f6627929f2a4$lut for cells of type $lut.
|
|
Using template $paramod$09d7ff7c3d1d9901344b01d38c40f254e5edc311$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00100000 for cells of type $lut.
|
|
Using template $paramod$4a0b7d2a2849f16773696ba19d68aee3da2f49f1$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11011100 for cells of type $lut.
|
|
Using template $paramod$77f0cd72667b23cc49e7a8bf984ad848b10003d7$lut for cells of type $lut.
|
|
Using template $paramod$2349469c9d9d0a3245a5c6f030ac99add533eb96$lut for cells of type $lut.
|
|
Using template $paramod$55f6f9cee16c7757093cb8f1db45e773789af9a7$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10101100 for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11001010 for cells of type $lut.
|
|
Using template $paramod$4f09540800ac966d6e31a7ccf5f32a559a8ce57a$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00001000 for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00010000 for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01000000 for cells of type $lut.
|
|
Using template $paramod$0c822c65361ce832091b6c90f1a02f1ee0b109d4$lut for cells of type $lut.
|
|
Using template $paramod$5669c8db8e6f25f93d37029b0fad4d742a70b03a$lut for cells of type $lut.
|
|
Using template $paramod$ea2b11aca30aa162d3b93de07d97b9c1565643dd$lut for cells of type $lut.
|
|
Using template $paramod$3a16cdc423338332acc062d6121d7f50fc30fbe6$lut for cells of type $lut.
|
|
Using template $paramod$dbc9832e8c07df12a10ac142cba717a43c21c0ab$lut for cells of type $lut.
|
|
Using template $paramod$cf52221ef2d451442dd7d72d5c8ad598e89310e9$lut for cells of type $lut.
|
|
Using template $paramod$c231c665eed0e54f6cd365c2b07ecdea418a10e6$lut for cells of type $lut.
|
|
Using template $paramod$eab8c2e20ad6848564bec45c7148558972138f5b$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11100000 for cells of type $lut.
|
|
Using template $paramod$fea512844f0598125018304dfe86621dbf348f27$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01110000 for cells of type $lut.
|
|
Using template $paramod$f8a9198ede5f55f66707edafc5a980c0d1845964$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000010 for cells of type $lut.
|
|
Using template $paramod$a4e96f70220c8c72bfba8aef01ed46347df8de63$lut for cells of type $lut.
|
|
Using template $paramod$183ec76ed3429a430a8be24b57f3de734985f568$lut for cells of type $lut.
|
|
Using template $paramod$d0f69fc2671bbe315699d75b65aae8328a796f77$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000001 for cells of type $lut.
|
|
Using template $paramod$41326ad8644342a66dfb051d050f2b6fbf15015b$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00001110 for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11100100 for cells of type $lut.
|
|
Using template $paramod$56e6d8a28a52006bb4e50e077743f0a2163235af$lut for cells of type $lut.
|
|
Using template $paramod$9f2673a51432cc74523a76959f201c232331430c$lut for cells of type $lut.
|
|
Using template $paramod$137d5d1409eb709bcd6ab98f2ead06fef72ee46f$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01001100 for cells of type $lut.
|
|
Using template $paramod$8829675bb8c52553aed9f101ec0d5ef0c865e5c7$lut for cells of type $lut.
|
|
Using template $paramod$9dfe2a25d99d8640a9f67a2438aaca85b684d257$lut for cells of type $lut.
|
|
Using template $paramod$5a203febca29678ab5583c0f96bc052b4d0c83a4$lut for cells of type $lut.
|
|
Using template $paramod$4133fe00eb18442862a284ccc67a95f8194d041c$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000001\LUT=2'01 for cells of type $lut.
|
|
No more expansions possible.
|
|
<suppressed ~1828 debug messages>
|
|
|
|
3.49. Executing OPT_LUT_INS pass (discard unused LUT inputs).
|
|
Optimizing LUTs in memory_manager.
|
|
Optimizing lut $abc$30601$lut$aiger$o1007.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
|
|
Optimizing lut $abc$30601$lut$aiger$o1096.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
|
|
Optimizing lut $abc$30601$lut$aiger$o1096.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
|
|
Optimizing lut $abc$30601$lut$aiger$o1036.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$30675.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
|
|
Optimizing lut $abc$30601$lut$aiger30600$1372.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
|
|
Optimizing lut $abc$30601$lut$aiger30600$1372.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
|
|
Optimizing lut $abc$30601$lut$aiger30600$1372.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
|
|
Optimizing lut $abc$30601$lut$aiger30600$1372.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
|
|
Optimizing lut $abc$30601$lut$aiger30600$1283.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$30604.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $abc$30601$lut$aiger30600$1299.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$30607.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$30610.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$30612.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$30663.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$30617.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$30618.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $abc$30601$lut$aiger$o983.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$30621.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$30624.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $abc$30601$lut$aiger30600$1401.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$30601$lut$aiger30600$1392.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$30660.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$30629.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$30631.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$30635.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$30637.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$30641.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $abc$30601$lut$aiger$o998.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$30642.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$30647.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$30648.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$30652.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $abc$30601$lut$aiger$o1096.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$30655.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$30659.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$30660.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$30662.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$30663.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$30601$lut$aiger$o1034.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$30665.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $abc$30601$lut$aiger$o1036.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$30601$lut$aiger$o1036.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$30666.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$30601$lut$aiger$o1043.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$30666.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$30669.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$30601$lut$aiger$o1047.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$30677.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$30677.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$30601$lut$aiger30600$1253.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $abc$30601$lut$aiger30600$1268.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$30679.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
|
|
Removed 0 unused cells and 1350 unused wires.
|
|
|
|
3.50. Executing AUTONAME pass.
|
|
Renamed 2900 objects in module memory_manager.
|
|
<suppressed ~2900 debug messages>
|
|
|
|
3.51. Executing HIERARCHY pass (managing design hierarchy).
|
|
Attribute `top' found on module `memory_manager'. Setting top module to memory_manager.
|
|
|
|
3.51.1. Analyzing design hierarchy..
|
|
Top module: \memory_manager
|
|
|
|
3.51.2. Analyzing design hierarchy..
|
|
Top module: \memory_manager
|
|
Removed 0 unused modules.
|
|
|
|
3.52. Printing statistics.
|
|
|
|
=== memory_manager ===
|
|
|
|
+----------Local Count, excluding submodules.
|
|
|
|
|
997 wires
|
|
3408 wire bits
|
|
997 public wires
|
|
3408 public wire bits
|
|
22 ports
|
|
272 port bits
|
|
1 cells
|
|
1 $scopeinfo
|
|
1974 submodules
|
|
108 CCU2C
|
|
7 L6MUX21
|
|
851 LUT4
|
|
219 PFUMX
|
|
789 TRELLIS_FF
|
|
|
|
=== design hierarchy ===
|
|
|
|
+----------Count including submodules.
|
|
|
|
|
1 memory_manager
|
|
|
|
+----------Count including submodules.
|
|
|
|
|
997 wires
|
|
3408 wire bits
|
|
997 public wires
|
|
3408 public wire bits
|
|
22 ports
|
|
272 port bits
|
|
- memories
|
|
- memory bits
|
|
- processes
|
|
1 cells
|
|
1 $scopeinfo
|
|
1974 submodules
|
|
108 CCU2C
|
|
7 L6MUX21
|
|
851 LUT4
|
|
219 PFUMX
|
|
789 TRELLIS_FF
|
|
|
|
3.53. Executing CHECK pass (checking for obvious problems).
|
|
Checking module memory_manager...
|
|
Found and reported 0 problems.
|
|
|
|
3.54. Executing JSON backend.
|
|
|
|
End of script. Logfile hash: bb7d874436, time: 0.82s, user: 0.63s, system: 0.03s, MEM: 76.50 MB peak
|
|
Yosys 0.68+post (git sha1 c12172fbae8af5e20f6fb52e3d4e92d56ed587b6, Release, AppleClang clang++ 21.0.0.21000101)
|
|
Time spent: 21% 23x read_verilog (0 sec), 21% 1x abc9_exe (0 sec), ...
|