micheleandClaude Sonnet 5
2e4cedc761
Implements M5: neural_director.v dispatches job descriptors to whichever of N_SLOTS (memory_manager, neural_processor) pairs is currently free (first-free scheduling per §9's initial policy), with a parametric-depth ready-queue FIFO for jobs arriving faster than slots can absorb them. Scope for this milestone (see decisions.log DEC-0007): a reduced 4-state FSM (DIR_IDLE/SCAN_READY/ALLOCATE/ERROR) rather than §9's full 8-state baseline -- dependency tracking, the waiting queue, and wake-up are §10's explicit responsibility (Dependency Manager, M6, not yet built), and slot-completion detection runs as an always-active per-slot tracker rather than a dedicated FSM state, for the same reason DEC-0002 already gave for the Neural Processor's own FSM (gating concurrent per-unit progress behind one shared state kills throughput). Verified with Verilator (N_SLOTS=2, each slot backed by its own independent behavioral memory rather than sharing V1's real PSRAM -- M4 already proved that path for one slot; this milestone's own concern is scheduling across multiple slots): 4/4 tests pass -- 3 jobs submitted to 2 slots (first two dispatch immediately, third correctly queues until a slot frees), and a deliberate burst that forces the ready queue to genuinely fill and recover. Real synthesis: 0 CHECK problems, 382 LUT4/366 FF/4 CCU2C/0 DSP. Real place&route (via a synthesis-only timing harness, same TRELLIS_IO pin-budget reason as M2/M4): Fmax 250.50 MHz, PASS at 80MHz. Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
2133 lines
142 KiB
Plaintext
2133 lines
142 KiB
Plaintext
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/----------------------------------------------------------------------------\
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| yosys -- Yosys Open SYnthesis Suite |
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| Copyright (C) 2012 - 2026 Claire Xenia Wolf <claire@yosyshq.com> |
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| Distributed under an ISC-like license, type "license" to see terms |
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\----------------------------------------------------------------------------/
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Yosys 0.68+post (git sha1 c12172fbae8af5e20f6fb52e3d4e92d56ed587b6, Release, AppleClang clang++ 21.0.0.21000101)
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-- Parsing `hardware/v2/rtl/neural_director.v' using frontend ` -vlog2k' --
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1. Executing Verilog-2005 frontend: hardware/v2/rtl/neural_director.v
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Parsing Verilog input from `hardware/v2/rtl/neural_director.v' to AST representation.
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Storing AST representation for module `$abstract\neural_director'.
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Successfully finished Verilog frontend.
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-- Parsing `hardware/v2/synthesis/harness_neural_director.v' using frontend ` -vlog2k' --
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2. Executing Verilog-2005 frontend: hardware/v2/synthesis/harness_neural_director.v
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Parsing Verilog input from `hardware/v2/synthesis/harness_neural_director.v' to AST representation.
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Storing AST representation for module `$abstract\harness_neural_director'.
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Successfully finished Verilog frontend.
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-- Running command `synth_ecp5 -json hardware/v2/synthesis/harness_neural_director/top.json -top harness_neural_director' --
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3. Executing SYNTH_LATTICE pass.
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3.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v
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Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v' to AST representation.
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Generating RTLIL representation for module `\LUT4'.
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Generating RTLIL representation for module `\$__ABC9_LUT5'.
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Generating RTLIL representation for module `\$__ABC9_LUT6'.
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Generating RTLIL representation for module `\$__ABC9_LUT7'.
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Generating RTLIL representation for module `\L6MUX21'.
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Generating RTLIL representation for module `\TRELLIS_RAM16X2'.
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Generating RTLIL representation for module `\PFUMX'.
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Generating RTLIL representation for module `\TRELLIS_DPR16X4'.
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Generating RTLIL representation for module `\DPR16X4C'.
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Generating RTLIL representation for module `\LUT2'.
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Generating RTLIL representation for module `\TRELLIS_FF'.
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Generating RTLIL representation for module `\TRELLIS_IO'.
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Generating RTLIL representation for module `\INV'.
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Generating RTLIL representation for module `\TRELLIS_COMB'.
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Generating RTLIL representation for module `\VLO'.
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Generating RTLIL representation for module `\VHI'.
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Generating RTLIL representation for module `\FD1P3AX'.
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Generating RTLIL representation for module `\FD1P3AY'.
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Generating RTLIL representation for module `\FD1P3BX'.
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Generating RTLIL representation for module `\FD1P3DX'.
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Generating RTLIL representation for module `\FD1P3IX'.
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Generating RTLIL representation for module `\FD1P3JX'.
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Generating RTLIL representation for module `\FD1S3AX'.
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Generating RTLIL representation for module `\FD1S3AY'.
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Generating RTLIL representation for module `\FD1S3BX'.
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Generating RTLIL representation for module `\FD1S3DX'.
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Generating RTLIL representation for module `\FD1S3IX'.
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Generating RTLIL representation for module `\FD1S3JX'.
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Generating RTLIL representation for module `\IFS1P3BX'.
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Generating RTLIL representation for module `\IFS1P3DX'.
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Generating RTLIL representation for module `\IFS1P3IX'.
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Generating RTLIL representation for module `\IFS1P3JX'.
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Generating RTLIL representation for module `\OFS1P3BX'.
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Generating RTLIL representation for module `\OFS1P3DX'.
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Generating RTLIL representation for module `\OFS1P3IX'.
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Generating RTLIL representation for module `\OFS1P3JX'.
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Generating RTLIL representation for module `\IB'.
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Generating RTLIL representation for module `\IBPU'.
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Generating RTLIL representation for module `\IBPD'.
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Generating RTLIL representation for module `\OB'.
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Generating RTLIL representation for module `\OBZ'.
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Generating RTLIL representation for module `\OBZPU'.
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Generating RTLIL representation for module `\OBZPD'.
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Generating RTLIL representation for module `\OBCO'.
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Generating RTLIL representation for module `\BB'.
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Generating RTLIL representation for module `\BBPU'.
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Generating RTLIL representation for module `\BBPD'.
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Generating RTLIL representation for module `\ILVDS'.
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Generating RTLIL representation for module `\OLVDS'.
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Generating RTLIL representation for module `\CCU2C'.
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Generating RTLIL representation for module `\DP16KD'.
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Replacing existing blackbox module `\FD1P3AX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:2.1-2.261.
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Generating RTLIL representation for module `\FD1P3AX'.
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Replacing existing blackbox module `\FD1P3AY' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:3.1-3.261.
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Generating RTLIL representation for module `\FD1P3AY'.
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Replacing existing blackbox module `\FD1P3BX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:4.1-4.261.
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Generating RTLIL representation for module `\FD1P3BX'.
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Replacing existing blackbox module `\FD1P3DX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:5.1-5.261.
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Generating RTLIL representation for module `\FD1P3DX'.
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Replacing existing blackbox module `\FD1P3IX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:6.1-6.261.
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Generating RTLIL representation for module `\FD1P3IX'.
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Replacing existing blackbox module `\FD1P3JX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:7.1-7.261.
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Generating RTLIL representation for module `\FD1P3JX'.
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Replacing existing blackbox module `\FD1S3AX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:8.1-8.261.
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Generating RTLIL representation for module `\FD1S3AX'.
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Replacing existing blackbox module `\FD1S3AY' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:9.1-9.261.
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Generating RTLIL representation for module `\FD1S3AY'.
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Replacing existing blackbox module `\FD1S3BX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:10.1-10.261.
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Generating RTLIL representation for module `\FD1S3BX'.
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Replacing existing blackbox module `\FD1S3DX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:11.1-11.261.
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Generating RTLIL representation for module `\FD1S3DX'.
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Replacing existing blackbox module `\FD1S3IX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:12.1-12.261.
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Generating RTLIL representation for module `\FD1S3IX'.
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Replacing existing blackbox module `\FD1S3JX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:13.1-13.261.
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Generating RTLIL representation for module `\FD1S3JX'.
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Replacing existing blackbox module `\IFS1P3BX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:26.1-26.301.
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Generating RTLIL representation for module `\IFS1P3BX'.
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Replacing existing blackbox module `\IFS1P3DX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:27.1-27.301.
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Generating RTLIL representation for module `\IFS1P3DX'.
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Replacing existing blackbox module `\IFS1P3IX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:28.1-28.301.
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Generating RTLIL representation for module `\IFS1P3IX'.
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Replacing existing blackbox module `\IFS1P3JX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:29.1-29.301.
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Generating RTLIL representation for module `\IFS1P3JX'.
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Replacing existing blackbox module `\OFS1P3BX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:31.1-31.302.
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Generating RTLIL representation for module `\OFS1P3BX'.
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Replacing existing blackbox module `\OFS1P3DX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:32.1-32.302.
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Generating RTLIL representation for module `\OFS1P3DX'.
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Replacing existing blackbox module `\OFS1P3IX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:33.1-33.302.
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Generating RTLIL representation for module `\OFS1P3IX'.
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Replacing existing blackbox module `\OFS1P3JX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:34.1-34.302.
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Generating RTLIL representation for module `\OFS1P3JX'.
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Replacing existing blackbox module `\IB' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:2.1-2.157.
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Generating RTLIL representation for module `\IB'.
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Replacing existing blackbox module `\IBPU' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:3.1-3.157.
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Generating RTLIL representation for module `\IBPU'.
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Replacing existing blackbox module `\IBPD' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:4.1-4.157.
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Generating RTLIL representation for module `\IBPD'.
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Replacing existing blackbox module `\OB' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:5.1-5.157.
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Generating RTLIL representation for module `\OB'.
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Replacing existing blackbox module `\OBZ' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:6.1-6.164.
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Generating RTLIL representation for module `\OBZ'.
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Replacing existing blackbox module `\OBZPU' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:7.1-7.164.
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Generating RTLIL representation for module `\OBZPU'.
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Replacing existing blackbox module `\OBZPD' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:8.1-8.164.
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Generating RTLIL representation for module `\OBZPD'.
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Replacing existing blackbox module `\OBCO' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:9.1-9.90.
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Generating RTLIL representation for module `\OBCO'.
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Replacing existing blackbox module `\BB' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:10.1-10.179.
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Generating RTLIL representation for module `\BB'.
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Replacing existing blackbox module `\BBPU' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:11.1-11.179.
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Generating RTLIL representation for module `\BBPU'.
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Replacing existing blackbox module `\BBPD' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:12.1-12.179.
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Generating RTLIL representation for module `\BBPD'.
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Replacing existing blackbox module `\ILVDS' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:13.1-13.139.
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Generating RTLIL representation for module `\ILVDS'.
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Replacing existing blackbox module `\OLVDS' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:14.1-14.146.
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Generating RTLIL representation for module `\OLVDS'.
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Successfully finished Verilog frontend.
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3.2. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v
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Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v' to AST representation.
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Generating RTLIL representation for module `\GSR'.
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Generating RTLIL representation for module `\PUR'.
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Generating RTLIL representation for module `\SGSR'.
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Generating RTLIL representation for module `\PDPW16KD'.
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Generating RTLIL representation for module `\MULT18X18D'.
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Generating RTLIL representation for module `\ALU54B'.
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Generating RTLIL representation for module `\CLKDIVF'.
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Generating RTLIL representation for module `\PCSCLKDIV'.
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Generating RTLIL representation for module `\DCSC'.
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Generating RTLIL representation for module `\DCCA'.
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Generating RTLIL representation for module `\ECLKSYNCB'.
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Generating RTLIL representation for module `\ECLKBRIDGECS'.
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Generating RTLIL representation for module `\DELAYF'.
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Generating RTLIL representation for module `\DELAYG'.
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Generating RTLIL representation for module `\USRMCLK'.
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Generating RTLIL representation for module `\DQSBUFM'.
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Generating RTLIL representation for module `\DDRDLLA'.
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Generating RTLIL representation for module `\DLLDELD'.
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Generating RTLIL representation for module `\IDDRX1F'.
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Generating RTLIL representation for module `\IDDRX2F'.
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Generating RTLIL representation for module `\IDDR71B'.
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Generating RTLIL representation for module `\IDDRX2DQA'.
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Generating RTLIL representation for module `\ODDRX1F'.
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Generating RTLIL representation for module `\ODDRX2F'.
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Generating RTLIL representation for module `\ODDR71B'.
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Generating RTLIL representation for module `\OSHX2A'.
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Generating RTLIL representation for module `\TSHX2DQA'.
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Generating RTLIL representation for module `\TSHX2DQSA'.
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Generating RTLIL representation for module `\ODDRX2DQA'.
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Generating RTLIL representation for module `\ODDRX2DQSB'.
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Generating RTLIL representation for module `\EHXPLLL'.
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Generating RTLIL representation for module `\DTR'.
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Generating RTLIL representation for module `\OSCG'.
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Generating RTLIL representation for module `\EXTREFB'.
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Generating RTLIL representation for module `\JTAGG'.
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Generating RTLIL representation for module `\DCUA'.
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Successfully finished Verilog frontend.
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3.3. Executing HIERARCHY pass (managing design hierarchy).
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3.4. Executing AST frontend in derive mode using pre-parsed AST for module `\harness_neural_director'.
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Generating RTLIL representation for module `\harness_neural_director'.
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3.4.1. Analyzing design hierarchy..
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Top module: \harness_neural_director
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Parameter \ADDR_WIDTH = 23
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Parameter \N_SLOTS = 4
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Parameter \QUEUE_DEPTH = 8
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3.4.2. Executing AST frontend in derive mode using pre-parsed AST for module `\neural_director'.
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Parameter \ADDR_WIDTH = 23
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Parameter \N_SLOTS = 4
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Parameter \QUEUE_DEPTH = 8
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Generating RTLIL representation for module `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director'.
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3.4.3. Analyzing design hierarchy..
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Top module: \harness_neural_director
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Used module: $paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director
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3.4.4. Analyzing design hierarchy..
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Top module: \harness_neural_director
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Used module: $paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director
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Removing unused module `$abstract\harness_neural_director'.
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Removing unused module `$abstract\neural_director'.
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Removed 2 unused modules.
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3.5. Executing PROC pass (convert processes to netlists).
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3.5.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
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Cleaned up 0 empty switches.
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3.5.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
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Marked 4 switch rules as full_case in process $proc$hardware/v2/rtl/neural_director.v:123$268 in module $paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.
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Marked 4 switch rules as full_case in process $proc$hardware/v2/rtl/neural_director.v:116$261 in module $paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.
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Marked 4 switch rules as full_case in process $proc$hardware/v2/rtl/neural_director.v:102$260 in module $paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.
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Marked 1 switch rules as full_case in process $proc$hardware/v2/synthesis/harness_neural_director.v:58$233 in module harness_neural_director.
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Marked 1 switch rules as full_case in process $proc$hardware/v2/synthesis/harness_neural_director.v:21$228 in module harness_neural_director.
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Removed a total of 0 dead cases.
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3.5.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
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Removed 4 redundant assignments.
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Promoted 37 assignments to connections.
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3.5.4. Executing PROC_INIT pass (extract init attributes).
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3.5.5. Executing PROC_ARST pass (detect async resets in processes).
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3.5.6. Executing PROC_ROM pass (convert switches to ROMs).
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Converted 0 switches.
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<suppressed ~16 debug messages>
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3.5.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
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Creating decoders for process `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$proc$hardware/v2/rtl/neural_director.v:123$268'.
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1/61: $2$lookahead\slot_busy$267[3:0]$356
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2/61: $2$lookahead\slot_result_addr$266[91:0]$355
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3/61: $2$lookahead\slot_n_tiles$265[63:0]$354
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4/61: $2$lookahead\slot_w_base$264[91:0]$353
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5/61: $2$lookahead\slot_x_base$263[91:0]$352
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6/61: $2$lookahead\slot_job_start$262[3:0]$351
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7/61: $2$bitselwrite$pos$hardware/v2/rtl/neural_director.v:195$249[1:0]$350
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8/61: $2$bitselwrite$pos$hardware/v2/rtl/neural_director.v:194$248[31:0]$349
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9/61: $2$bitselwrite$pos$hardware/v2/rtl/neural_director.v:193$247[31:0]$348
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10/61: $2$bitselwrite$pos$hardware/v2/rtl/neural_director.v:192$246[31:0]$347
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11/61: $2$bitselwrite$pos$hardware/v2/rtl/neural_director.v:191$245[31:0]$346
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12/61: $2$bitselwrite$pos$hardware/v2/rtl/neural_director.v:190$244[1:0]$345
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13/61: $2$memwr$\q_node_id$hardware/v2/rtl/neural_director.v:151$254_EN[15:0]$338
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14/61: $2$memwr$\q_node_id$hardware/v2/rtl/neural_director.v:151$254_DATA[15:0]$337
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15/61: $2$memwr$\q_node_id$hardware/v2/rtl/neural_director.v:151$254_ADDR[2:0]$336
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16/61: $2$memwr$\q_result_addr$hardware/v2/rtl/neural_director.v:150$253_EN[22:0]$335
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17/61: $2$memwr$\q_result_addr$hardware/v2/rtl/neural_director.v:150$253_DATA[22:0]$334
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18/61: $2$memwr$\q_result_addr$hardware/v2/rtl/neural_director.v:150$253_ADDR[2:0]$333
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19/61: $2$memwr$\q_n_tiles$hardware/v2/rtl/neural_director.v:149$252_EN[15:0]$332
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20/61: $2$memwr$\q_n_tiles$hardware/v2/rtl/neural_director.v:149$252_DATA[15:0]$331
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21/61: $2$memwr$\q_n_tiles$hardware/v2/rtl/neural_director.v:149$252_ADDR[2:0]$330
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22/61: $2$memwr$\q_w_base$hardware/v2/rtl/neural_director.v:148$251_EN[22:0]$329
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23/61: $2$memwr$\q_w_base$hardware/v2/rtl/neural_director.v:148$251_DATA[22:0]$328
|
|
24/61: $2$memwr$\q_w_base$hardware/v2/rtl/neural_director.v:148$251_ADDR[2:0]$327
|
|
25/61: $2$memwr$\q_x_base$hardware/v2/rtl/neural_director.v:147$250_EN[22:0]$326
|
|
26/61: $2$memwr$\q_x_base$hardware/v2/rtl/neural_director.v:147$250_DATA[22:0]$325
|
|
27/61: $2$memwr$\q_x_base$hardware/v2/rtl/neural_director.v:147$250_ADDR[2:0]$324
|
|
28/61: $0\job_out_done[0:0]
|
|
29/61: $1$lookahead\slot_result_addr$266[91:0]$321
|
|
30/61: $1$lookahead\slot_n_tiles$265[63:0]$320
|
|
31/61: $1$lookahead\slot_w_base$264[91:0]$319
|
|
32/61: $1$lookahead\slot_x_base$263[91:0]$318
|
|
33/61: $1$lookahead\slot_job_start$262[3:0]$317
|
|
34/61: $1$lookahead\slot_busy$267[3:0]$322
|
|
35/61: $0\q_count[3:0]
|
|
36/61: $1$memwr$\q_node_id$hardware/v2/rtl/neural_director.v:151$254_EN[15:0]$316
|
|
37/61: $1$memwr$\q_node_id$hardware/v2/rtl/neural_director.v:151$254_DATA[15:0]$315
|
|
38/61: $1$memwr$\q_node_id$hardware/v2/rtl/neural_director.v:151$254_ADDR[2:0]$314
|
|
39/61: $1$memwr$\q_result_addr$hardware/v2/rtl/neural_director.v:150$253_EN[22:0]$313
|
|
40/61: $1$memwr$\q_result_addr$hardware/v2/rtl/neural_director.v:150$253_DATA[22:0]$312
|
|
41/61: $1$memwr$\q_result_addr$hardware/v2/rtl/neural_director.v:150$253_ADDR[2:0]$311
|
|
42/61: $1$memwr$\q_n_tiles$hardware/v2/rtl/neural_director.v:149$252_EN[15:0]$310
|
|
43/61: $1$memwr$\q_n_tiles$hardware/v2/rtl/neural_director.v:149$252_DATA[15:0]$309
|
|
44/61: $1$memwr$\q_n_tiles$hardware/v2/rtl/neural_director.v:149$252_ADDR[2:0]$308
|
|
45/61: $1$memwr$\q_w_base$hardware/v2/rtl/neural_director.v:148$251_EN[22:0]$307
|
|
46/61: $1$memwr$\q_w_base$hardware/v2/rtl/neural_director.v:148$251_DATA[22:0]$306
|
|
47/61: $1$memwr$\q_w_base$hardware/v2/rtl/neural_director.v:148$251_ADDR[2:0]$305
|
|
48/61: $1$memwr$\q_x_base$hardware/v2/rtl/neural_director.v:147$250_EN[22:0]$304
|
|
49/61: $1$memwr$\q_x_base$hardware/v2/rtl/neural_director.v:147$250_DATA[22:0]$303
|
|
50/61: $1$memwr$\q_x_base$hardware/v2/rtl/neural_director.v:147$250_ADDR[2:0]$302
|
|
51/61: $1$bitselwrite$pos$hardware/v2/rtl/neural_director.v:195$249[1:0]$301
|
|
52/61: $1$bitselwrite$pos$hardware/v2/rtl/neural_director.v:194$248[31:0]$300
|
|
53/61: $1$bitselwrite$pos$hardware/v2/rtl/neural_director.v:193$247[31:0]$299
|
|
54/61: $1$bitselwrite$pos$hardware/v2/rtl/neural_director.v:192$246[31:0]$298
|
|
55/61: $1$bitselwrite$pos$hardware/v2/rtl/neural_director.v:191$245[31:0]$297
|
|
56/61: $1$bitselwrite$pos$hardware/v2/rtl/neural_director.v:190$244[1:0]$296
|
|
57/61: $0\q_tail[2:0]
|
|
58/61: $0\q_head[2:0]
|
|
59/61: $0\dir_error[0:0]
|
|
60/61: $0\dir_state[3:0]
|
|
61/61: $0\job_out_slot[1:0]
|
|
Creating decoders for process `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$proc$hardware/v2/rtl/neural_director.v:116$261'.
|
|
1/4: $4\done_slot_idx[1:0]
|
|
2/4: $3\done_slot_idx[1:0]
|
|
3/4: $2\done_slot_idx[1:0]
|
|
4/4: $1\done_slot_idx[1:0]
|
|
Creating decoders for process `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$proc$hardware/v2/rtl/neural_director.v:102$260'.
|
|
1/4: $4\free_slot_idx[1:0]
|
|
2/4: $3\free_slot_idx[1:0]
|
|
3/4: $2\free_slot_idx[1:0]
|
|
4/4: $1\free_slot_idx[1:0]
|
|
Creating decoders for process `\harness_neural_director.$proc$hardware/v2/synthesis/harness_neural_director.v:58$233'.
|
|
1/1: $0\chk[7:0]
|
|
Creating decoders for process `\harness_neural_director.$proc$hardware/v2/synthesis/harness_neural_director.v:21$228'.
|
|
1/1: $0\lfsr[31:0]
|
|
|
|
3.5.8. Executing PROC_DLATCH pass (convert process syncs to latches).
|
|
No latch inferred for signal `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.\done_slot_idx' from process `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$proc$hardware/v2/rtl/neural_director.v:116$261'.
|
|
No latch inferred for signal `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.\di' from process `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$proc$hardware/v2/rtl/neural_director.v:116$261'.
|
|
No latch inferred for signal `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.\free_slot_idx' from process `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$proc$hardware/v2/rtl/neural_director.v:102$260'.
|
|
No latch inferred for signal `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.\fi' from process `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$proc$hardware/v2/rtl/neural_director.v:102$260'.
|
|
|
|
3.5.9. Executing PROC_DFF pass (convert process syncs to FFs).
|
|
Creating register for signal `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.\slot_job_start' using process `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$proc$hardware/v2/rtl/neural_director.v:123$268'.
|
|
created $dff cell `$procdff$752' with positive edge clock.
|
|
Creating register for signal `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.\slot_x_base' using process `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$proc$hardware/v2/rtl/neural_director.v:123$268'.
|
|
created $dff cell `$procdff$753' with positive edge clock.
|
|
Creating register for signal `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.\slot_w_base' using process `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$proc$hardware/v2/rtl/neural_director.v:123$268'.
|
|
created $dff cell `$procdff$754' with positive edge clock.
|
|
Creating register for signal `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.\slot_result_addr' using process `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$proc$hardware/v2/rtl/neural_director.v:123$268'.
|
|
created $dff cell `$procdff$755' with positive edge clock.
|
|
Creating register for signal `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.\slot_n_tiles' using process `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$proc$hardware/v2/rtl/neural_director.v:123$268'.
|
|
created $dff cell `$procdff$756' with positive edge clock.
|
|
Creating register for signal `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.\job_out_done' using process `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$proc$hardware/v2/rtl/neural_director.v:123$268'.
|
|
created $dff cell `$procdff$757' with positive edge clock.
|
|
Creating register for signal `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.\job_out_slot' using process `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$proc$hardware/v2/rtl/neural_director.v:123$268'.
|
|
created $dff cell `$procdff$758' with positive edge clock.
|
|
Creating register for signal `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.\dir_state' using process `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$proc$hardware/v2/rtl/neural_director.v:123$268'.
|
|
created $dff cell `$procdff$759' with positive edge clock.
|
|
Creating register for signal `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.\dir_error' using process `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$proc$hardware/v2/rtl/neural_director.v:123$268'.
|
|
created $dff cell `$procdff$760' with positive edge clock.
|
|
Creating register for signal `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.\q_head' using process `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$proc$hardware/v2/rtl/neural_director.v:123$268'.
|
|
created $dff cell `$procdff$761' with positive edge clock.
|
|
Creating register for signal `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.\q_tail' using process `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$proc$hardware/v2/rtl/neural_director.v:123$268'.
|
|
created $dff cell `$procdff$762' with positive edge clock.
|
|
Creating register for signal `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.\q_count' using process `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$proc$hardware/v2/rtl/neural_director.v:123$268'.
|
|
created $dff cell `$procdff$763' with positive edge clock.
|
|
Creating register for signal `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.\slot_busy' using process `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$proc$hardware/v2/rtl/neural_director.v:123$268'.
|
|
created $dff cell `$procdff$764' with positive edge clock.
|
|
Creating register for signal `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$bitselwrite$pos$hardware/v2/rtl/neural_director.v:190$244' using process `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$proc$hardware/v2/rtl/neural_director.v:123$268'.
|
|
created $dff cell `$procdff$765' with positive edge clock.
|
|
Creating register for signal `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$bitselwrite$pos$hardware/v2/rtl/neural_director.v:191$245' using process `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$proc$hardware/v2/rtl/neural_director.v:123$268'.
|
|
created $dff cell `$procdff$766' with positive edge clock.
|
|
Creating register for signal `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$bitselwrite$pos$hardware/v2/rtl/neural_director.v:192$246' using process `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$proc$hardware/v2/rtl/neural_director.v:123$268'.
|
|
created $dff cell `$procdff$767' with positive edge clock.
|
|
Creating register for signal `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$bitselwrite$pos$hardware/v2/rtl/neural_director.v:193$247' using process `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$proc$hardware/v2/rtl/neural_director.v:123$268'.
|
|
created $dff cell `$procdff$768' with positive edge clock.
|
|
Creating register for signal `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$bitselwrite$pos$hardware/v2/rtl/neural_director.v:194$248' using process `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$proc$hardware/v2/rtl/neural_director.v:123$268'.
|
|
created $dff cell `$procdff$769' with positive edge clock.
|
|
Creating register for signal `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$bitselwrite$pos$hardware/v2/rtl/neural_director.v:195$249' using process `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$proc$hardware/v2/rtl/neural_director.v:123$268'.
|
|
created $dff cell `$procdff$770' with positive edge clock.
|
|
Creating register for signal `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$memwr$\q_x_base$hardware/v2/rtl/neural_director.v:147$250_ADDR' using process `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$proc$hardware/v2/rtl/neural_director.v:123$268'.
|
|
created $dff cell `$procdff$771' with positive edge clock.
|
|
Creating register for signal `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$memwr$\q_x_base$hardware/v2/rtl/neural_director.v:147$250_DATA' using process `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$proc$hardware/v2/rtl/neural_director.v:123$268'.
|
|
created $dff cell `$procdff$772' with positive edge clock.
|
|
Creating register for signal `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$memwr$\q_x_base$hardware/v2/rtl/neural_director.v:147$250_EN' using process `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$proc$hardware/v2/rtl/neural_director.v:123$268'.
|
|
created $dff cell `$procdff$773' with positive edge clock.
|
|
Creating register for signal `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$memwr$\q_w_base$hardware/v2/rtl/neural_director.v:148$251_ADDR' using process `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$proc$hardware/v2/rtl/neural_director.v:123$268'.
|
|
created $dff cell `$procdff$774' with positive edge clock.
|
|
Creating register for signal `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$memwr$\q_w_base$hardware/v2/rtl/neural_director.v:148$251_DATA' using process `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$proc$hardware/v2/rtl/neural_director.v:123$268'.
|
|
created $dff cell `$procdff$775' with positive edge clock.
|
|
Creating register for signal `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$memwr$\q_w_base$hardware/v2/rtl/neural_director.v:148$251_EN' using process `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$proc$hardware/v2/rtl/neural_director.v:123$268'.
|
|
created $dff cell `$procdff$776' with positive edge clock.
|
|
Creating register for signal `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$memwr$\q_n_tiles$hardware/v2/rtl/neural_director.v:149$252_ADDR' using process `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$proc$hardware/v2/rtl/neural_director.v:123$268'.
|
|
created $dff cell `$procdff$777' with positive edge clock.
|
|
Creating register for signal `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$memwr$\q_n_tiles$hardware/v2/rtl/neural_director.v:149$252_DATA' using process `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$proc$hardware/v2/rtl/neural_director.v:123$268'.
|
|
created $dff cell `$procdff$778' with positive edge clock.
|
|
Creating register for signal `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$memwr$\q_n_tiles$hardware/v2/rtl/neural_director.v:149$252_EN' using process `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$proc$hardware/v2/rtl/neural_director.v:123$268'.
|
|
created $dff cell `$procdff$779' with positive edge clock.
|
|
Creating register for signal `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$memwr$\q_result_addr$hardware/v2/rtl/neural_director.v:150$253_ADDR' using process `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$proc$hardware/v2/rtl/neural_director.v:123$268'.
|
|
created $dff cell `$procdff$780' with positive edge clock.
|
|
Creating register for signal `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$memwr$\q_result_addr$hardware/v2/rtl/neural_director.v:150$253_DATA' using process `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$proc$hardware/v2/rtl/neural_director.v:123$268'.
|
|
created $dff cell `$procdff$781' with positive edge clock.
|
|
Creating register for signal `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$memwr$\q_result_addr$hardware/v2/rtl/neural_director.v:150$253_EN' using process `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$proc$hardware/v2/rtl/neural_director.v:123$268'.
|
|
created $dff cell `$procdff$782' with positive edge clock.
|
|
Creating register for signal `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$memwr$\q_node_id$hardware/v2/rtl/neural_director.v:151$254_ADDR' using process `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$proc$hardware/v2/rtl/neural_director.v:123$268'.
|
|
created $dff cell `$procdff$783' with positive edge clock.
|
|
Creating register for signal `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$memwr$\q_node_id$hardware/v2/rtl/neural_director.v:151$254_DATA' using process `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$proc$hardware/v2/rtl/neural_director.v:123$268'.
|
|
created $dff cell `$procdff$784' with positive edge clock.
|
|
Creating register for signal `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$memwr$\q_node_id$hardware/v2/rtl/neural_director.v:151$254_EN' using process `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$proc$hardware/v2/rtl/neural_director.v:123$268'.
|
|
created $dff cell `$procdff$785' with positive edge clock.
|
|
Creating register for signal `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$lookahead\slot_job_start$262' using process `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$proc$hardware/v2/rtl/neural_director.v:123$268'.
|
|
created $dff cell `$procdff$786' with positive edge clock.
|
|
Creating register for signal `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$lookahead\slot_x_base$263' using process `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$proc$hardware/v2/rtl/neural_director.v:123$268'.
|
|
created $dff cell `$procdff$787' with positive edge clock.
|
|
Creating register for signal `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$lookahead\slot_w_base$264' using process `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$proc$hardware/v2/rtl/neural_director.v:123$268'.
|
|
created $dff cell `$procdff$788' with positive edge clock.
|
|
Creating register for signal `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$lookahead\slot_n_tiles$265' using process `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$proc$hardware/v2/rtl/neural_director.v:123$268'.
|
|
created $dff cell `$procdff$789' with positive edge clock.
|
|
Creating register for signal `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$lookahead\slot_result_addr$266' using process `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$proc$hardware/v2/rtl/neural_director.v:123$268'.
|
|
created $dff cell `$procdff$790' with positive edge clock.
|
|
Creating register for signal `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$lookahead\slot_busy$267' using process `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$proc$hardware/v2/rtl/neural_director.v:123$268'.
|
|
created $dff cell `$procdff$791' with positive edge clock.
|
|
Creating register for signal `\harness_neural_director.\chk' using process `\harness_neural_director.$proc$hardware/v2/synthesis/harness_neural_director.v:58$233'.
|
|
created $dff cell `$procdff$792' with positive edge clock.
|
|
Creating register for signal `\harness_neural_director.\lfsr' using process `\harness_neural_director.$proc$hardware/v2/synthesis/harness_neural_director.v:21$228'.
|
|
created $dff cell `$procdff$793' with positive edge clock.
|
|
|
|
3.5.10. Executing PROC_MEMWR pass (convert process memory writes to cells).
|
|
|
|
3.5.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
|
|
Found and cleaned up 6 empty switches in `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$proc$hardware/v2/rtl/neural_director.v:123$268'.
|
|
Removing empty process `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$proc$hardware/v2/rtl/neural_director.v:123$268'.
|
|
Found and cleaned up 4 empty switches in `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$proc$hardware/v2/rtl/neural_director.v:116$261'.
|
|
Removing empty process `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$proc$hardware/v2/rtl/neural_director.v:116$261'.
|
|
Found and cleaned up 4 empty switches in `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$proc$hardware/v2/rtl/neural_director.v:102$260'.
|
|
Removing empty process `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$proc$hardware/v2/rtl/neural_director.v:102$260'.
|
|
Found and cleaned up 1 empty switch in `\harness_neural_director.$proc$hardware/v2/synthesis/harness_neural_director.v:58$233'.
|
|
Removing empty process `harness_neural_director.$proc$hardware/v2/synthesis/harness_neural_director.v:58$233'.
|
|
Found and cleaned up 1 empty switch in `\harness_neural_director.$proc$hardware/v2/synthesis/harness_neural_director.v:21$228'.
|
|
Removing empty process `harness_neural_director.$proc$hardware/v2/synthesis/harness_neural_director.v:21$228'.
|
|
Cleaned up 16 empty switches.
|
|
|
|
3.5.12. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module $paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.
|
|
<suppressed ~4 debug messages>
|
|
Optimizing module harness_neural_director.
|
|
<suppressed ~1 debug messages>
|
|
|
|
3.6. Executing CHECK pass (checking for obvious problems).
|
|
Checking module $paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director...
|
|
Checking module harness_neural_director...
|
|
Found and reported 0 problems.
|
|
|
|
3.7. Executing FLATTEN pass (flatten design).
|
|
Deleting now unused module $paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.
|
|
<suppressed ~1 debug messages>
|
|
|
|
3.8. Executing TRIBUF pass.
|
|
|
|
3.9. Executing DEMINOUT pass (demote inout ports to input or output).
|
|
|
|
3.10. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module harness_neural_director.
|
|
<suppressed ~6 debug messages>
|
|
|
|
3.11. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \harness_neural_director..
|
|
Removed 64 unused cells and 276 unused wires.
|
|
<suppressed ~70 debug messages>
|
|
|
|
3.12. Executing CHECK pass (checking for obvious problems).
|
|
Checking module harness_neural_director...
|
|
Found and reported 0 problems.
|
|
|
|
3.13. Executing OPT pass (performing simple optimizations).
|
|
|
|
3.13.1. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module harness_neural_director.
|
|
|
|
3.13.2. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\harness_neural_director'.
|
|
Computing hashes of 192 cells of `\harness_neural_director'.
|
|
Finding duplicate cells in `\harness_neural_director'.
|
|
Computing hashes of 174 cells of `\harness_neural_director'.
|
|
Finding duplicate cells in `\harness_neural_director'.
|
|
Computing hashes of 170 cells of `\harness_neural_director'.
|
|
Finding duplicate cells in `\harness_neural_director'.
|
|
Computing hashes of 168 cells of `\harness_neural_director'.
|
|
Finding duplicate cells in `\harness_neural_director'.
|
|
Computing hashes of 166 cells of `\harness_neural_director'.
|
|
Finding duplicate cells in `\harness_neural_director'.
|
|
<suppressed ~78 debug messages>
|
|
Removed a total of 26 cells.
|
|
|
|
3.13.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \harness_neural_director..
|
|
Creating internal representation of mux trees.
|
|
Evaluating internal representation of mux trees.
|
|
Analyzing evaluation results.
|
|
dead port 1/2 on $mux $flatten\dut.$procmux$463.
|
|
dead port 1/2 on $mux $flatten\dut.$procmux$529.
|
|
dead port 1/2 on $mux $flatten\dut.$procmux$535.
|
|
dead port 1/2 on $mux $flatten\dut.$procmux$541.
|
|
dead port 1/2 on $mux $flatten\dut.$procmux$547.
|
|
dead port 1/2 on $mux $flatten\dut.$procmux$553.
|
|
dead port 1/2 on $mux $flatten\dut.$procmux$559.
|
|
dead port 1/2 on $mux $flatten\dut.$procmux$565.
|
|
dead port 1/2 on $mux $flatten\dut.$procmux$571.
|
|
dead port 1/2 on $mux $flatten\dut.$procmux$577.
|
|
dead port 1/2 on $mux $flatten\dut.$procmux$583.
|
|
dead port 1/2 on $mux $flatten\dut.$procmux$589.
|
|
dead port 1/2 on $mux $flatten\dut.$procmux$595.
|
|
dead port 1/2 on $mux $flatten\dut.$procmux$428.
|
|
dead port 1/2 on $mux $flatten\dut.$procmux$456.
|
|
dead port 1/2 on $mux $flatten\dut.$procmux$449.
|
|
dead port 1/2 on $mux $flatten\dut.$procmux$435.
|
|
dead port 1/2 on $mux $flatten\dut.$procmux$442.
|
|
Removed 18 multiplexer ports.
|
|
<suppressed ~108 debug messages>
|
|
|
|
3.13.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \harness_neural_director.
|
|
Consolidated identical input bits for $mux cell $flatten\dut.$procmux$526:
|
|
Old ports: A=23'00000000000000000000000, B=23'11111111111111111111111, Y=$flatten\dut.$procmux$526_Y
|
|
New ports: A=1'0, B=1'1, Y=$flatten\dut.$procmux$526_Y [0]
|
|
New connections: $flatten\dut.$procmux$526_Y [22:1] = { $flatten\dut.$procmux$526_Y [0] $flatten\dut.$procmux$526_Y [0] $flatten\dut.$procmux$526_Y [0] $flatten\dut.$procmux$526_Y [0] $flatten\dut.$procmux$526_Y [0] $flatten\dut.$procmux$526_Y [0] $flatten\dut.$procmux$526_Y [0] $flatten\dut.$procmux$526_Y [0] $flatten\dut.$procmux$526_Y [0] $flatten\dut.$procmux$526_Y [0] $flatten\dut.$procmux$526_Y [0] $flatten\dut.$procmux$526_Y [0] $flatten\dut.$procmux$526_Y [0] $flatten\dut.$procmux$526_Y [0] $flatten\dut.$procmux$526_Y [0] $flatten\dut.$procmux$526_Y [0] $flatten\dut.$procmux$526_Y [0] $flatten\dut.$procmux$526_Y [0] $flatten\dut.$procmux$526_Y [0] $flatten\dut.$procmux$526_Y [0] $flatten\dut.$procmux$526_Y [0] $flatten\dut.$procmux$526_Y [0] }
|
|
Consolidated identical input bits for $mux cell $flatten\dut.$procmux$544:
|
|
Old ports: A=16'0000000000000000, B=16'1111111111111111, Y=$flatten\dut.$procmux$544_Y
|
|
New ports: A=1'0, B=1'1, Y=$flatten\dut.$procmux$544_Y [0]
|
|
New connections: $flatten\dut.$procmux$544_Y [15:1] = { $flatten\dut.$procmux$544_Y [0] $flatten\dut.$procmux$544_Y [0] $flatten\dut.$procmux$544_Y [0] $flatten\dut.$procmux$544_Y [0] $flatten\dut.$procmux$544_Y [0] $flatten\dut.$procmux$544_Y [0] $flatten\dut.$procmux$544_Y [0] $flatten\dut.$procmux$544_Y [0] $flatten\dut.$procmux$544_Y [0] $flatten\dut.$procmux$544_Y [0] $flatten\dut.$procmux$544_Y [0] $flatten\dut.$procmux$544_Y [0] $flatten\dut.$procmux$544_Y [0] $flatten\dut.$procmux$544_Y [0] $flatten\dut.$procmux$544_Y [0] }
|
|
Consolidated identical input bits for $mux cell $flatten\dut.$procmux$562:
|
|
Old ports: A=23'00000000000000000000000, B=23'11111111111111111111111, Y=$flatten\dut.$procmux$562_Y
|
|
New ports: A=1'0, B=1'1, Y=$flatten\dut.$procmux$562_Y [0]
|
|
New connections: $flatten\dut.$procmux$562_Y [22:1] = { $flatten\dut.$procmux$562_Y [0] $flatten\dut.$procmux$562_Y [0] $flatten\dut.$procmux$562_Y [0] $flatten\dut.$procmux$562_Y [0] $flatten\dut.$procmux$562_Y [0] $flatten\dut.$procmux$562_Y [0] $flatten\dut.$procmux$562_Y [0] $flatten\dut.$procmux$562_Y [0] $flatten\dut.$procmux$562_Y [0] $flatten\dut.$procmux$562_Y [0] $flatten\dut.$procmux$562_Y [0] $flatten\dut.$procmux$562_Y [0] $flatten\dut.$procmux$562_Y [0] $flatten\dut.$procmux$562_Y [0] $flatten\dut.$procmux$562_Y [0] $flatten\dut.$procmux$562_Y [0] $flatten\dut.$procmux$562_Y [0] $flatten\dut.$procmux$562_Y [0] $flatten\dut.$procmux$562_Y [0] $flatten\dut.$procmux$562_Y [0] $flatten\dut.$procmux$562_Y [0] $flatten\dut.$procmux$562_Y [0] }
|
|
Consolidated identical input bits for $mux cell $flatten\dut.$procmux$580:
|
|
Old ports: A=23'00000000000000000000000, B=23'11111111111111111111111, Y=$flatten\dut.$procmux$580_Y
|
|
New ports: A=1'0, B=1'1, Y=$flatten\dut.$procmux$580_Y [0]
|
|
New connections: $flatten\dut.$procmux$580_Y [22:1] = { $flatten\dut.$procmux$580_Y [0] $flatten\dut.$procmux$580_Y [0] $flatten\dut.$procmux$580_Y [0] $flatten\dut.$procmux$580_Y [0] $flatten\dut.$procmux$580_Y [0] $flatten\dut.$procmux$580_Y [0] $flatten\dut.$procmux$580_Y [0] $flatten\dut.$procmux$580_Y [0] $flatten\dut.$procmux$580_Y [0] $flatten\dut.$procmux$580_Y [0] $flatten\dut.$procmux$580_Y [0] $flatten\dut.$procmux$580_Y [0] $flatten\dut.$procmux$580_Y [0] $flatten\dut.$procmux$580_Y [0] $flatten\dut.$procmux$580_Y [0] $flatten\dut.$procmux$580_Y [0] $flatten\dut.$procmux$580_Y [0] $flatten\dut.$procmux$580_Y [0] $flatten\dut.$procmux$580_Y [0] $flatten\dut.$procmux$580_Y [0] $flatten\dut.$procmux$580_Y [0] $flatten\dut.$procmux$580_Y [0] }
|
|
New ctrl vector for $pmux cell $flatten\dut.$procmux$707: { $flatten\dut.$procmux$708_CMP $auto$opt_reduce.cc:137:opt_pmux$801 $flatten\dut.$eq$hardware/v2/rtl/neural_director.v:212$416_Y }
|
|
Optimizing cells in module \harness_neural_director.
|
|
Consolidated identical input bits for $mux cell $flatten\dut.$procmux$637:
|
|
Old ports: A=$flatten\dut.$2$memwr$\q_result_addr$hardware/v2/rtl/neural_director.v:150$253_EN[22:0]$335, B=23'00000000000000000000000, Y=$flatten\dut.$0$memwr$\q_result_addr$hardware/v2/rtl/neural_director.v:150$253_EN[22:0]$286
|
|
New ports: A=$flatten\dut.$procmux$526_Y [0], B=1'0, Y=$flatten\dut.$0$memwr$\q_result_addr$hardware/v2/rtl/neural_director.v:150$253_EN[22:0]$286 [0]
|
|
New connections: $flatten\dut.$0$memwr$\q_result_addr$hardware/v2/rtl/neural_director.v:150$253_EN[22:0]$286 [22:1] = { $flatten\dut.$0$memwr$\q_result_addr$hardware/v2/rtl/neural_director.v:150$253_EN[22:0]$286 [0] $flatten\dut.$0$memwr$\q_result_addr$hardware/v2/rtl/neural_director.v:150$253_EN[22:0]$286 [0] $flatten\dut.$0$memwr$\q_result_addr$hardware/v2/rtl/neural_director.v:150$253_EN[22:0]$286 [0] $flatten\dut.$0$memwr$\q_result_addr$hardware/v2/rtl/neural_director.v:150$253_EN[22:0]$286 [0] $flatten\dut.$0$memwr$\q_result_addr$hardware/v2/rtl/neural_director.v:150$253_EN[22:0]$286 [0] $flatten\dut.$0$memwr$\q_result_addr$hardware/v2/rtl/neural_director.v:150$253_EN[22:0]$286 [0] $flatten\dut.$0$memwr$\q_result_addr$hardware/v2/rtl/neural_director.v:150$253_EN[22:0]$286 [0] $flatten\dut.$0$memwr$\q_result_addr$hardware/v2/rtl/neural_director.v:150$253_EN[22:0]$286 [0] $flatten\dut.$0$memwr$\q_result_addr$hardware/v2/rtl/neural_director.v:150$253_EN[22:0]$286 [0] $flatten\dut.$0$memwr$\q_result_addr$hardware/v2/rtl/neural_director.v:150$253_EN[22:0]$286 [0] $flatten\dut.$0$memwr$\q_result_addr$hardware/v2/rtl/neural_director.v:150$253_EN[22:0]$286 [0] $flatten\dut.$0$memwr$\q_result_addr$hardware/v2/rtl/neural_director.v:150$253_EN[22:0]$286 [0] $flatten\dut.$0$memwr$\q_result_addr$hardware/v2/rtl/neural_director.v:150$253_EN[22:0]$286 [0] $flatten\dut.$0$memwr$\q_result_addr$hardware/v2/rtl/neural_director.v:150$253_EN[22:0]$286 [0] $flatten\dut.$0$memwr$\q_result_addr$hardware/v2/rtl/neural_director.v:150$253_EN[22:0]$286 [0] $flatten\dut.$0$memwr$\q_result_addr$hardware/v2/rtl/neural_director.v:150$253_EN[22:0]$286 [0] $flatten\dut.$0$memwr$\q_result_addr$hardware/v2/rtl/neural_director.v:150$253_EN[22:0]$286 [0] $flatten\dut.$0$memwr$\q_result_addr$hardware/v2/rtl/neural_director.v:150$253_EN[22:0]$286 [0] $flatten\dut.$0$memwr$\q_result_addr$hardware/v2/rtl/neural_director.v:150$253_EN[22:0]$286 [0] $flatten\dut.$0$memwr$\q_result_addr$hardware/v2/rtl/neural_director.v:150$253_EN[22:0]$286 [0] $flatten\dut.$0$memwr$\q_result_addr$hardware/v2/rtl/neural_director.v:150$253_EN[22:0]$286 [0] $flatten\dut.$0$memwr$\q_result_addr$hardware/v2/rtl/neural_director.v:150$253_EN[22:0]$286 [0] }
|
|
Consolidated identical input bits for $mux cell $flatten\dut.$procmux$646:
|
|
Old ports: A=$flatten\dut.$2$memwr$\q_n_tiles$hardware/v2/rtl/neural_director.v:149$252_EN[15:0]$332, B=16'0000000000000000, Y=$flatten\dut.$0$memwr$\q_n_tiles$hardware/v2/rtl/neural_director.v:149$252_EN[15:0]$283
|
|
New ports: A=$flatten\dut.$procmux$544_Y [0], B=1'0, Y=$flatten\dut.$0$memwr$\q_n_tiles$hardware/v2/rtl/neural_director.v:149$252_EN[15:0]$283 [0]
|
|
New connections: $flatten\dut.$0$memwr$\q_n_tiles$hardware/v2/rtl/neural_director.v:149$252_EN[15:0]$283 [15:1] = { $flatten\dut.$0$memwr$\q_n_tiles$hardware/v2/rtl/neural_director.v:149$252_EN[15:0]$283 [0] $flatten\dut.$0$memwr$\q_n_tiles$hardware/v2/rtl/neural_director.v:149$252_EN[15:0]$283 [0] $flatten\dut.$0$memwr$\q_n_tiles$hardware/v2/rtl/neural_director.v:149$252_EN[15:0]$283 [0] $flatten\dut.$0$memwr$\q_n_tiles$hardware/v2/rtl/neural_director.v:149$252_EN[15:0]$283 [0] $flatten\dut.$0$memwr$\q_n_tiles$hardware/v2/rtl/neural_director.v:149$252_EN[15:0]$283 [0] $flatten\dut.$0$memwr$\q_n_tiles$hardware/v2/rtl/neural_director.v:149$252_EN[15:0]$283 [0] $flatten\dut.$0$memwr$\q_n_tiles$hardware/v2/rtl/neural_director.v:149$252_EN[15:0]$283 [0] $flatten\dut.$0$memwr$\q_n_tiles$hardware/v2/rtl/neural_director.v:149$252_EN[15:0]$283 [0] $flatten\dut.$0$memwr$\q_n_tiles$hardware/v2/rtl/neural_director.v:149$252_EN[15:0]$283 [0] $flatten\dut.$0$memwr$\q_n_tiles$hardware/v2/rtl/neural_director.v:149$252_EN[15:0]$283 [0] $flatten\dut.$0$memwr$\q_n_tiles$hardware/v2/rtl/neural_director.v:149$252_EN[15:0]$283 [0] $flatten\dut.$0$memwr$\q_n_tiles$hardware/v2/rtl/neural_director.v:149$252_EN[15:0]$283 [0] $flatten\dut.$0$memwr$\q_n_tiles$hardware/v2/rtl/neural_director.v:149$252_EN[15:0]$283 [0] $flatten\dut.$0$memwr$\q_n_tiles$hardware/v2/rtl/neural_director.v:149$252_EN[15:0]$283 [0] $flatten\dut.$0$memwr$\q_n_tiles$hardware/v2/rtl/neural_director.v:149$252_EN[15:0]$283 [0] }
|
|
Consolidated identical input bits for $mux cell $flatten\dut.$procmux$655:
|
|
Old ports: A=$flatten\dut.$2$memwr$\q_w_base$hardware/v2/rtl/neural_director.v:148$251_EN[22:0]$329, B=23'00000000000000000000000, Y=$flatten\dut.$0$memwr$\q_w_base$hardware/v2/rtl/neural_director.v:148$251_EN[22:0]$280
|
|
New ports: A=$flatten\dut.$procmux$562_Y [0], B=1'0, Y=$flatten\dut.$0$memwr$\q_w_base$hardware/v2/rtl/neural_director.v:148$251_EN[22:0]$280 [0]
|
|
New connections: $flatten\dut.$0$memwr$\q_w_base$hardware/v2/rtl/neural_director.v:148$251_EN[22:0]$280 [22:1] = { $flatten\dut.$0$memwr$\q_w_base$hardware/v2/rtl/neural_director.v:148$251_EN[22:0]$280 [0] $flatten\dut.$0$memwr$\q_w_base$hardware/v2/rtl/neural_director.v:148$251_EN[22:0]$280 [0] $flatten\dut.$0$memwr$\q_w_base$hardware/v2/rtl/neural_director.v:148$251_EN[22:0]$280 [0] $flatten\dut.$0$memwr$\q_w_base$hardware/v2/rtl/neural_director.v:148$251_EN[22:0]$280 [0] $flatten\dut.$0$memwr$\q_w_base$hardware/v2/rtl/neural_director.v:148$251_EN[22:0]$280 [0] $flatten\dut.$0$memwr$\q_w_base$hardware/v2/rtl/neural_director.v:148$251_EN[22:0]$280 [0] $flatten\dut.$0$memwr$\q_w_base$hardware/v2/rtl/neural_director.v:148$251_EN[22:0]$280 [0] $flatten\dut.$0$memwr$\q_w_base$hardware/v2/rtl/neural_director.v:148$251_EN[22:0]$280 [0] $flatten\dut.$0$memwr$\q_w_base$hardware/v2/rtl/neural_director.v:148$251_EN[22:0]$280 [0] $flatten\dut.$0$memwr$\q_w_base$hardware/v2/rtl/neural_director.v:148$251_EN[22:0]$280 [0] $flatten\dut.$0$memwr$\q_w_base$hardware/v2/rtl/neural_director.v:148$251_EN[22:0]$280 [0] $flatten\dut.$0$memwr$\q_w_base$hardware/v2/rtl/neural_director.v:148$251_EN[22:0]$280 [0] $flatten\dut.$0$memwr$\q_w_base$hardware/v2/rtl/neural_director.v:148$251_EN[22:0]$280 [0] $flatten\dut.$0$memwr$\q_w_base$hardware/v2/rtl/neural_director.v:148$251_EN[22:0]$280 [0] $flatten\dut.$0$memwr$\q_w_base$hardware/v2/rtl/neural_director.v:148$251_EN[22:0]$280 [0] $flatten\dut.$0$memwr$\q_w_base$hardware/v2/rtl/neural_director.v:148$251_EN[22:0]$280 [0] $flatten\dut.$0$memwr$\q_w_base$hardware/v2/rtl/neural_director.v:148$251_EN[22:0]$280 [0] $flatten\dut.$0$memwr$\q_w_base$hardware/v2/rtl/neural_director.v:148$251_EN[22:0]$280 [0] $flatten\dut.$0$memwr$\q_w_base$hardware/v2/rtl/neural_director.v:148$251_EN[22:0]$280 [0] $flatten\dut.$0$memwr$\q_w_base$hardware/v2/rtl/neural_director.v:148$251_EN[22:0]$280 [0] $flatten\dut.$0$memwr$\q_w_base$hardware/v2/rtl/neural_director.v:148$251_EN[22:0]$280 [0] $flatten\dut.$0$memwr$\q_w_base$hardware/v2/rtl/neural_director.v:148$251_EN[22:0]$280 [0] }
|
|
Consolidated identical input bits for $mux cell $flatten\dut.$procmux$664:
|
|
Old ports: A=$flatten\dut.$2$memwr$\q_x_base$hardware/v2/rtl/neural_director.v:147$250_EN[22:0]$326, B=23'00000000000000000000000, Y=$flatten\dut.$0$memwr$\q_x_base$hardware/v2/rtl/neural_director.v:147$250_EN[22:0]$277
|
|
New ports: A=$flatten\dut.$procmux$580_Y [0], B=1'0, Y=$flatten\dut.$0$memwr$\q_x_base$hardware/v2/rtl/neural_director.v:147$250_EN[22:0]$277 [0]
|
|
New connections: $flatten\dut.$0$memwr$\q_x_base$hardware/v2/rtl/neural_director.v:147$250_EN[22:0]$277 [22:1] = { $flatten\dut.$0$memwr$\q_x_base$hardware/v2/rtl/neural_director.v:147$250_EN[22:0]$277 [0] $flatten\dut.$0$memwr$\q_x_base$hardware/v2/rtl/neural_director.v:147$250_EN[22:0]$277 [0] $flatten\dut.$0$memwr$\q_x_base$hardware/v2/rtl/neural_director.v:147$250_EN[22:0]$277 [0] $flatten\dut.$0$memwr$\q_x_base$hardware/v2/rtl/neural_director.v:147$250_EN[22:0]$277 [0] $flatten\dut.$0$memwr$\q_x_base$hardware/v2/rtl/neural_director.v:147$250_EN[22:0]$277 [0] $flatten\dut.$0$memwr$\q_x_base$hardware/v2/rtl/neural_director.v:147$250_EN[22:0]$277 [0] $flatten\dut.$0$memwr$\q_x_base$hardware/v2/rtl/neural_director.v:147$250_EN[22:0]$277 [0] $flatten\dut.$0$memwr$\q_x_base$hardware/v2/rtl/neural_director.v:147$250_EN[22:0]$277 [0] $flatten\dut.$0$memwr$\q_x_base$hardware/v2/rtl/neural_director.v:147$250_EN[22:0]$277 [0] $flatten\dut.$0$memwr$\q_x_base$hardware/v2/rtl/neural_director.v:147$250_EN[22:0]$277 [0] $flatten\dut.$0$memwr$\q_x_base$hardware/v2/rtl/neural_director.v:147$250_EN[22:0]$277 [0] $flatten\dut.$0$memwr$\q_x_base$hardware/v2/rtl/neural_director.v:147$250_EN[22:0]$277 [0] $flatten\dut.$0$memwr$\q_x_base$hardware/v2/rtl/neural_director.v:147$250_EN[22:0]$277 [0] $flatten\dut.$0$memwr$\q_x_base$hardware/v2/rtl/neural_director.v:147$250_EN[22:0]$277 [0] $flatten\dut.$0$memwr$\q_x_base$hardware/v2/rtl/neural_director.v:147$250_EN[22:0]$277 [0] $flatten\dut.$0$memwr$\q_x_base$hardware/v2/rtl/neural_director.v:147$250_EN[22:0]$277 [0] $flatten\dut.$0$memwr$\q_x_base$hardware/v2/rtl/neural_director.v:147$250_EN[22:0]$277 [0] $flatten\dut.$0$memwr$\q_x_base$hardware/v2/rtl/neural_director.v:147$250_EN[22:0]$277 [0] $flatten\dut.$0$memwr$\q_x_base$hardware/v2/rtl/neural_director.v:147$250_EN[22:0]$277 [0] $flatten\dut.$0$memwr$\q_x_base$hardware/v2/rtl/neural_director.v:147$250_EN[22:0]$277 [0] $flatten\dut.$0$memwr$\q_x_base$hardware/v2/rtl/neural_director.v:147$250_EN[22:0]$277 [0] $flatten\dut.$0$memwr$\q_x_base$hardware/v2/rtl/neural_director.v:147$250_EN[22:0]$277 [0] }
|
|
Optimizing cells in module \harness_neural_director.
|
|
Performed a total of 9 changes.
|
|
|
|
3.13.5. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\harness_neural_director'.
|
|
Computing hashes of 149 cells of `\harness_neural_director'.
|
|
Finding duplicate cells in `\harness_neural_director'.
|
|
Computing hashes of 143 cells of `\harness_neural_director'.
|
|
Finding duplicate cells in `\harness_neural_director'.
|
|
Computing hashes of 137 cells of `\harness_neural_director'.
|
|
Finding duplicate cells in `\harness_neural_director'.
|
|
<suppressed ~36 debug messages>
|
|
Removed a total of 12 cells.
|
|
|
|
3.13.6. Executing OPT_DFF pass (perform DFF optimizations).
|
|
|
|
3.13.7. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \harness_neural_director..
|
|
Removed 0 unused cells and 56 unused wires.
|
|
<suppressed ~1 debug messages>
|
|
|
|
3.13.8. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module harness_neural_director.
|
|
|
|
3.13.9. Rerunning OPT passes. (Maybe there is more to do..)
|
|
|
|
3.13.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \harness_neural_director..
|
|
Creating internal representation of mux trees.
|
|
Evaluating internal representation of mux trees.
|
|
Analyzing evaluation results.
|
|
Removed 0 multiplexer ports.
|
|
<suppressed ~72 debug messages>
|
|
|
|
3.13.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \harness_neural_director.
|
|
Performed a total of 0 changes.
|
|
|
|
3.13.12. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\harness_neural_director'.
|
|
Computing hashes of 137 cells of `\harness_neural_director'.
|
|
Finding duplicate cells in `\harness_neural_director'.
|
|
Removed a total of 0 cells.
|
|
|
|
3.13.13. Executing OPT_DFF pass (perform DFF optimizations).
|
|
|
|
3.13.14. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \harness_neural_director..
|
|
|
|
3.13.15. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module harness_neural_director.
|
|
|
|
3.13.16. Finished fast OPT passes. (There is nothing left to do.)
|
|
|
|
3.14. Executing FSM pass (extract and optimize FSM).
|
|
|
|
3.14.1. Executing FSM_DETECT pass (finding FSMs in design).
|
|
Not marking harness_neural_director.dut.dir_state as FSM state register:
|
|
Users of register don't seem to benefit from recoding.
|
|
Not marking harness_neural_director.dut.job_out_slot as FSM state register:
|
|
Users of register don't seem to benefit from recoding.
|
|
|
|
3.14.2. Executing FSM_EXTRACT pass (extracting FSM from design).
|
|
|
|
3.14.3. Executing FSM_OPT pass (simple optimizations of FSMs).
|
|
|
|
3.14.4. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \harness_neural_director..
|
|
|
|
3.14.5. Executing FSM_OPT pass (simple optimizations of FSMs).
|
|
|
|
3.14.6. Executing FSM_RECODE pass (re-assigning FSM state encoding).
|
|
|
|
3.14.7. Executing FSM_INFO pass (dumping all available information on FSM cells).
|
|
|
|
3.14.8. Executing FSM_MAP pass (mapping FSMs to basic logic).
|
|
|
|
3.15. Executing OPT pass (performing simple optimizations).
|
|
|
|
3.15.1. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module harness_neural_director.
|
|
|
|
3.15.2. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\harness_neural_director'.
|
|
Computing hashes of 137 cells of `\harness_neural_director'.
|
|
Finding duplicate cells in `\harness_neural_director'.
|
|
Removed a total of 0 cells.
|
|
|
|
3.15.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \harness_neural_director..
|
|
Creating internal representation of mux trees.
|
|
Evaluating internal representation of mux trees.
|
|
Analyzing evaluation results.
|
|
Removed 0 multiplexer ports.
|
|
<suppressed ~72 debug messages>
|
|
|
|
3.15.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \harness_neural_director.
|
|
Performed a total of 0 changes.
|
|
|
|
3.15.5. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\harness_neural_director'.
|
|
Computing hashes of 137 cells of `\harness_neural_director'.
|
|
Finding duplicate cells in `\harness_neural_director'.
|
|
Removed a total of 0 cells.
|
|
|
|
3.15.6. Executing OPT_DFF pass (perform DFF optimizations).
|
|
Adding SRST signal on $procdff$793 ($dff) from module harness_neural_director (D = { \lfsr [30:7] $xor$hardware/v2/synthesis/harness_neural_director.v:23$232_Y }, Q = { \lfsr [31:8] \lfsr [0] }, rval = 25'0000000000000000000000001).
|
|
Adding SRST signal on $procdff$792 ($dff) from module harness_neural_director (D = $xor$hardware/v2/synthesis/harness_neural_director.v:60$243_Y, Q = \chk, rval = 8'00000000).
|
|
Adding SRST signal on $flatten\dut.$procdff$764 ($dff) from module harness_neural_director (D = $flatten\dut.$2$lookahead\slot_busy$267[3:0]$356, Q = \dut.slot_busy, rval = 4'0000).
|
|
Adding SRST signal on $flatten\dut.$procdff$763 ($dff) from module harness_neural_director (D = $flatten\dut.$procmux$621_Y, Q = \dut.q_count, rval = 4'0000).
|
|
Adding EN signal on $auto$ff.cc:337:slice$806 ($sdff) from module harness_neural_director (D = $flatten\dut.$procmux$621_Y, Q = \dut.q_count).
|
|
Adding SRST signal on $flatten\dut.$procdff$762 ($dff) from module harness_neural_director (D = $flatten\dut.$procmux$691_Y, Q = \dut.q_tail, rval = 3'000).
|
|
Adding EN signal on $auto$ff.cc:337:slice$810 ($sdff) from module harness_neural_director (D = $flatten\dut.$ternary$hardware/v2/rtl/neural_director.v:152$341_Y, Q = \dut.q_tail).
|
|
Adding SRST signal on $flatten\dut.$procdff$761 ($dff) from module harness_neural_director (D = $flatten\dut.$procmux$698_Y, Q = \dut.q_head, rval = 3'000).
|
|
Adding EN signal on $auto$ff.cc:337:slice$812 ($sdff) from module harness_neural_director (D = $flatten\dut.$ternary$hardware/v2/rtl/neural_director.v:196$415_Y, Q = \dut.q_head).
|
|
Adding EN signal on $flatten\dut.$procdff$760 ($dff) from module harness_neural_director (D = 1'0, Q = \dut.dir_error).
|
|
Adding SRST signal on $flatten\dut.$procdff$759 ($dff) from module harness_neural_director (D = $flatten\dut.$procmux$707_Y, Q = \dut.dir_state, rval = 4'0000).
|
|
Adding EN signal on $auto$ff.cc:337:slice$815 ($sdff) from module harness_neural_director (D = $flatten\dut.$procmux$707_Y, Q = \dut.dir_state).
|
|
Adding SRST signal on $flatten\dut.$procdff$758 ($dff) from module harness_neural_director (D = $flatten\dut.$procmux$717_Y, Q = \dut.job_out_slot, rval = 2'00).
|
|
Adding EN signal on $auto$ff.cc:337:slice$823 ($sdff) from module harness_neural_director (D = \dut.done_slot_idx, Q = \dut.job_out_slot).
|
|
Adding SRST signal on $flatten\dut.$procdff$757 ($dff) from module harness_neural_director (D = $flatten\dut.$procmux$597_Y, Q = \dut.job_out_done, rval = 1'0).
|
|
Adding SRST signal on $flatten\dut.$procdff$756 ($dff) from module harness_neural_director (D = $flatten\dut.$2$lookahead\slot_n_tiles$265[63:0]$354, Q = \dut.slot_n_tiles, rval = 64'0000000000000000000000000000000000000000000000000000000000000000).
|
|
Adding EN signal on $auto$ff.cc:337:slice$826 ($sdff) from module harness_neural_director (D = $flatten\dut.$or$hardware/v2/rtl/neural_director.v:193$395_Y, Q = \dut.slot_n_tiles).
|
|
Adding SRST signal on $flatten\dut.$procdff$755 ($dff) from module harness_neural_director (D = $flatten\dut.$2$lookahead\slot_result_addr$266[91:0]$355, Q = \dut.slot_result_addr, rval = 92'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000).
|
|
Adding EN signal on $auto$ff.cc:337:slice$828 ($sdff) from module harness_neural_director (D = $flatten\dut.$or$hardware/v2/rtl/neural_director.v:194$405_Y, Q = \dut.slot_result_addr).
|
|
Adding SRST signal on $flatten\dut.$procdff$754 ($dff) from module harness_neural_director (D = $flatten\dut.$2$lookahead\slot_w_base$264[91:0]$353, Q = \dut.slot_w_base, rval = 92'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000).
|
|
Adding EN signal on $auto$ff.cc:337:slice$830 ($sdff) from module harness_neural_director (D = $flatten\dut.$or$hardware/v2/rtl/neural_director.v:192$385_Y, Q = \dut.slot_w_base).
|
|
Adding SRST signal on $flatten\dut.$procdff$753 ($dff) from module harness_neural_director (D = $flatten\dut.$2$lookahead\slot_x_base$263[91:0]$352, Q = \dut.slot_x_base, rval = 92'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000).
|
|
Adding EN signal on $auto$ff.cc:337:slice$832 ($sdff) from module harness_neural_director (D = $flatten\dut.$or$hardware/v2/rtl/neural_director.v:191$375_Y, Q = \dut.slot_x_base).
|
|
Adding SRST signal on $flatten\dut.$procdff$752 ($dff) from module harness_neural_director (D = $flatten\dut.$or$hardware/v2/rtl/neural_director.v:190$365_Y, Q = \dut.slot_job_start, rval = 4'0000).
|
|
Setting constant 0-bit at position 0 on $auto$ff.cc:337:slice$814 ($dffe) from module harness_neural_director.
|
|
|
|
3.15.7. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \harness_neural_director..
|
|
Removed 22 unused cells and 22 unused wires.
|
|
<suppressed ~23 debug messages>
|
|
|
|
3.15.8. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module harness_neural_director.
|
|
<suppressed ~3 debug messages>
|
|
|
|
3.15.9. Rerunning OPT passes. (Maybe there is more to do..)
|
|
|
|
3.15.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \harness_neural_director..
|
|
Creating internal representation of mux trees.
|
|
Evaluating internal representation of mux trees.
|
|
Analyzing evaluation results.
|
|
Removed 0 multiplexer ports.
|
|
<suppressed ~43 debug messages>
|
|
|
|
3.15.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \harness_neural_director.
|
|
Performed a total of 0 changes.
|
|
|
|
3.15.12. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\harness_neural_director'.
|
|
Computing hashes of 120 cells of `\harness_neural_director'.
|
|
Finding duplicate cells in `\harness_neural_director'.
|
|
Removed a total of 0 cells.
|
|
|
|
3.15.13. Executing OPT_DFF pass (perform DFF optimizations).
|
|
|
|
3.15.14. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \harness_neural_director..
|
|
Removed 0 unused cells and 1 unused wires.
|
|
<suppressed ~1 debug messages>
|
|
|
|
3.15.15. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module harness_neural_director.
|
|
|
|
3.15.16. Rerunning OPT passes. (Maybe there is more to do..)
|
|
|
|
3.15.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \harness_neural_director..
|
|
Creating internal representation of mux trees.
|
|
Evaluating internal representation of mux trees.
|
|
Analyzing evaluation results.
|
|
Removed 0 multiplexer ports.
|
|
<suppressed ~43 debug messages>
|
|
|
|
3.15.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \harness_neural_director.
|
|
Performed a total of 0 changes.
|
|
|
|
3.15.19. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\harness_neural_director'.
|
|
Computing hashes of 120 cells of `\harness_neural_director'.
|
|
Finding duplicate cells in `\harness_neural_director'.
|
|
Removed a total of 0 cells.
|
|
|
|
3.15.20. Executing OPT_DFF pass (perform DFF optimizations).
|
|
|
|
3.15.21. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \harness_neural_director..
|
|
|
|
3.15.22. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module harness_neural_director.
|
|
|
|
3.15.23. Finished fast OPT passes. (There is nothing left to do.)
|
|
|
|
3.16. Executing WREDUCE pass (reducing word size of cells).
|
|
Removed top 1 bits (of 2) from port B of cell harness_neural_director.$auto$opt_dff.cc:320:make_patterns_logic$820 ($ne).
|
|
Removed top 7 bits (of 8) from port B of cell harness_neural_director.$xor$hardware/v2/synthesis/harness_neural_director.v:60$234 ($xor).
|
|
Removed top 7 bits (of 8) from port B of cell harness_neural_director.$xor$hardware/v2/synthesis/harness_neural_director.v:60$240 ($xor).
|
|
Removed top 6 bits (of 8) from port B of cell harness_neural_director.$xor$hardware/v2/synthesis/harness_neural_director.v:60$241 ($xor).
|
|
Removed top 24 bits (of 32) from mux cell harness_neural_director.$procmux$750 ($mux).
|
|
Removed top 2 bits (of 4) from port B of cell harness_neural_director.$flatten\dut.$procmux$708_CMP0 ($eq).
|
|
Removed top 1 bits (of 2) from port B of cell harness_neural_director.$flatten\dut.$procmux$622_CMP0 ($eq).
|
|
Removed top 2 bits (of 4) from port B of cell harness_neural_director.$flatten\dut.$procmux$426_CMP0 ($eq).
|
|
Removed top 3 bits (of 4) from port B of cell harness_neural_director.$flatten\dut.$eq$hardware/v2/rtl/neural_director.v:212$416 ($eq).
|
|
Converting cell harness_neural_director.$flatten\dut.$neg$hardware/v2/rtl/neural_director.v:195$406 ($neg) from signed to unsigned.
|
|
Removed top 1 bits (of 3) from port A of cell harness_neural_director.$flatten\dut.$neg$hardware/v2/rtl/neural_director.v:195$406 ($neg).
|
|
Converting cell harness_neural_director.$flatten\dut.$neg$hardware/v2/rtl/neural_director.v:194$403 ($neg) from signed to unsigned.
|
|
Removed top 1 bits (of 33) from port A of cell harness_neural_director.$flatten\dut.$neg$hardware/v2/rtl/neural_director.v:194$403 ($neg).
|
|
Removed top 27 bits (of 32) from port B of cell harness_neural_director.$flatten\dut.$mul$hardware/v2/rtl/neural_director.v:194$396 ($mul).
|
|
Removed top 25 bits (of 32) from port Y of cell harness_neural_director.$flatten\dut.$mul$hardware/v2/rtl/neural_director.v:194$396 ($mul).
|
|
Removed top 26 bits (of 33) from port A of cell harness_neural_director.$flatten\dut.$neg$hardware/v2/rtl/neural_director.v:193$393 ($neg).
|
|
Converting cell harness_neural_director.$flatten\dut.$neg$hardware/v2/rtl/neural_director.v:193$393 ($neg) from signed to unsigned.
|
|
Removed top 1 bits (of 7) from port A of cell harness_neural_director.$flatten\dut.$neg$hardware/v2/rtl/neural_director.v:193$393 ($neg).
|
|
Removed top 25 bits (of 32) from wire harness_neural_director.$flatten\dut.$add$hardware/v2/rtl/neural_director.v:191$367_Y.
|
|
Removed top 24 bits (of 32) from wire harness_neural_director.$0\lfsr[31:0].
|
|
|
|
3.17. Executing PEEPOPT pass (run peephole optimizers).
|
|
left shiftmul pattern in harness_neural_director: shift=$flatten\dut.$shift$hardware/v2/rtl/neural_director.v:194$399, mul=$flatten\dut.$mul$hardware/v2/rtl/neural_director.v:194$396
|
|
left shiftmul pattern in harness_neural_director: shift=$flatten\dut.$shift$hardware/v2/rtl/neural_director.v:194$404, mul=$flatten\dut.$mul$hardware/v2/rtl/neural_director.v:194$396
|
|
left shiftmul pattern in harness_neural_director: shift=$flatten\dut.$shift$hardware/v2/rtl/neural_director.v:192$384, mul=$flatten\dut.$mul$hardware/v2/rtl/neural_director.v:194$396
|
|
left shiftmul pattern in harness_neural_director: shift=$flatten\dut.$shift$hardware/v2/rtl/neural_director.v:191$374, mul=$flatten\dut.$mul$hardware/v2/rtl/neural_director.v:194$396
|
|
|
|
3.18. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \harness_neural_director..
|
|
Removed 2 unused cells and 4 unused wires.
|
|
<suppressed ~3 debug messages>
|
|
|
|
3.19. Executing SHARE pass (SAT-based resource sharing).
|
|
|
|
3.20. Executing TECHMAP pass (map to technology primitives).
|
|
|
|
3.20.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/cmp2lut.v
|
|
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/cmp2lut.v' to AST representation.
|
|
Generating RTLIL representation for module `\_90_lut_cmp_'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
3.20.2. Continuing TECHMAP pass.
|
|
No more expansions possible.
|
|
<suppressed ~6 debug messages>
|
|
|
|
3.21. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module harness_neural_director.
|
|
|
|
3.22. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \harness_neural_director..
|
|
|
|
3.23. Executing TECHMAP pass (map to technology primitives).
|
|
|
|
3.23.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/mul2dsp.v
|
|
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/mul2dsp.v' to AST representation.
|
|
Generating RTLIL representation for module `\_80_mul'.
|
|
Generating RTLIL representation for module `\_90_soft_mul'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
3.23.2. Continuing TECHMAP pass.
|
|
No more expansions possible.
|
|
<suppressed ~4 debug messages>
|
|
|
|
3.24. Executing TECHMAP pass (map to technology primitives).
|
|
|
|
3.24.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/dsp_map_18x18.v
|
|
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/dsp_map_18x18.v' to AST representation.
|
|
Generating RTLIL representation for module `$__MUL18X18'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
3.24.2. Continuing TECHMAP pass.
|
|
No more expansions possible.
|
|
<suppressed ~3 debug messages>
|
|
|
|
3.25. Executing ALUMACC pass (create $alu and $macc cells).
|
|
Extracting $alu and $macc cells in module harness_neural_director:
|
|
creating $macc model for $auto$peepopt_pm.h:1040:block_9$846 ($neg).
|
|
creating $macc model for $auto$peepopt_pm.h:1040:block_9$843 ($neg).
|
|
creating $macc model for $auto$peepopt_pm.h:1040:block_9$852 ($neg).
|
|
creating $macc model for $flatten\dut.$neg$hardware/v2/rtl/neural_director.v:195$406 ($neg).
|
|
creating $macc model for $flatten\dut.$add$hardware/v2/rtl/neural_director.v:213$421 ($add).
|
|
creating $macc model for $flatten\dut.$sub$hardware/v2/rtl/neural_director.v:214$422 ($sub).
|
|
creating $macc model for $auto$peepopt_pm.h:1040:block_9$849 ($neg).
|
|
creating $macc model for $flatten\dut.$add$hardware/v2/rtl/neural_director.v:196$414 ($add).
|
|
creating $macc model for $flatten\dut.$add$hardware/v2/rtl/neural_director.v:152$340 ($add).
|
|
creating $macc model for $flatten\dut.$neg$hardware/v2/rtl/neural_director.v:193$393 ($neg).
|
|
creating $alu model for $macc $flatten\dut.$neg$hardware/v2/rtl/neural_director.v:193$393.
|
|
creating $alu model for $macc $flatten\dut.$add$hardware/v2/rtl/neural_director.v:152$340.
|
|
creating $alu model for $macc $flatten\dut.$add$hardware/v2/rtl/neural_director.v:196$414.
|
|
creating $alu model for $macc $auto$peepopt_pm.h:1040:block_9$849.
|
|
creating $alu model for $macc $flatten\dut.$sub$hardware/v2/rtl/neural_director.v:214$422.
|
|
creating $alu model for $macc $flatten\dut.$add$hardware/v2/rtl/neural_director.v:213$421.
|
|
creating $alu model for $macc $flatten\dut.$neg$hardware/v2/rtl/neural_director.v:195$406.
|
|
creating $alu model for $macc $auto$peepopt_pm.h:1040:block_9$852.
|
|
creating $alu model for $macc $auto$peepopt_pm.h:1040:block_9$843.
|
|
creating $alu model for $macc $auto$peepopt_pm.h:1040:block_9$846.
|
|
creating $alu cell for $flatten\dut.$neg$hardware/v2/rtl/neural_director.v:195$406: $auto$alumacc.cc:548:replace_alu$854
|
|
creating $alu cell for $flatten\dut.$add$hardware/v2/rtl/neural_director.v:213$421: $auto$alumacc.cc:548:replace_alu$857
|
|
creating $alu cell for $flatten\dut.$sub$hardware/v2/rtl/neural_director.v:214$422: $auto$alumacc.cc:548:replace_alu$860
|
|
creating $alu cell for $auto$peepopt_pm.h:1040:block_9$846: $auto$alumacc.cc:548:replace_alu$863
|
|
creating $alu cell for $auto$peepopt_pm.h:1040:block_9$843: $auto$alumacc.cc:548:replace_alu$866
|
|
creating $alu cell for $auto$peepopt_pm.h:1040:block_9$852: $auto$alumacc.cc:548:replace_alu$869
|
|
creating $alu cell for $auto$peepopt_pm.h:1040:block_9$849: $auto$alumacc.cc:548:replace_alu$872
|
|
creating $alu cell for $flatten\dut.$add$hardware/v2/rtl/neural_director.v:196$414: $auto$alumacc.cc:548:replace_alu$875
|
|
creating $alu cell for $flatten\dut.$add$hardware/v2/rtl/neural_director.v:152$340: $auto$alumacc.cc:548:replace_alu$878
|
|
creating $alu cell for $flatten\dut.$neg$hardware/v2/rtl/neural_director.v:193$393: $auto$alumacc.cc:548:replace_alu$881
|
|
created 10 $alu and 0 $macc cells.
|
|
|
|
3.26. Executing OPT pass (performing simple optimizations).
|
|
|
|
3.26.1. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module harness_neural_director.
|
|
|
|
3.26.2. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\harness_neural_director'.
|
|
Computing hashes of 122 cells of `\harness_neural_director'.
|
|
Finding duplicate cells in `\harness_neural_director'.
|
|
Computing hashes of 119 cells of `\harness_neural_director'.
|
|
Finding duplicate cells in `\harness_neural_director'.
|
|
<suppressed ~15 debug messages>
|
|
Removed a total of 3 cells.
|
|
|
|
3.26.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \harness_neural_director..
|
|
Creating internal representation of mux trees.
|
|
Evaluating internal representation of mux trees.
|
|
Analyzing evaluation results.
|
|
Removed 0 multiplexer ports.
|
|
<suppressed ~43 debug messages>
|
|
|
|
3.26.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \harness_neural_director.
|
|
Performed a total of 0 changes.
|
|
|
|
3.26.5. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\harness_neural_director'.
|
|
Computing hashes of 119 cells of `\harness_neural_director'.
|
|
Finding duplicate cells in `\harness_neural_director'.
|
|
Removed a total of 0 cells.
|
|
|
|
3.26.6. Executing OPT_DFF pass (perform DFF optimizations).
|
|
|
|
3.26.7. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \harness_neural_director..
|
|
Removed 0 unused cells and 9 unused wires.
|
|
<suppressed ~1 debug messages>
|
|
|
|
3.26.8. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module harness_neural_director.
|
|
|
|
3.26.9. Rerunning OPT passes. (Maybe there is more to do..)
|
|
|
|
3.26.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \harness_neural_director..
|
|
Creating internal representation of mux trees.
|
|
Evaluating internal representation of mux trees.
|
|
Analyzing evaluation results.
|
|
Removed 0 multiplexer ports.
|
|
<suppressed ~43 debug messages>
|
|
|
|
3.26.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \harness_neural_director.
|
|
Performed a total of 0 changes.
|
|
|
|
3.26.12. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\harness_neural_director'.
|
|
Computing hashes of 119 cells of `\harness_neural_director'.
|
|
Finding duplicate cells in `\harness_neural_director'.
|
|
Removed a total of 0 cells.
|
|
|
|
3.26.13. Executing OPT_DFF pass (perform DFF optimizations).
|
|
|
|
3.26.14. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \harness_neural_director..
|
|
|
|
3.26.15. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module harness_neural_director.
|
|
|
|
3.26.16. Finished fast OPT passes. (There is nothing left to do.)
|
|
|
|
3.27. Executing MEMORY pass.
|
|
|
|
3.27.1. Executing OPT_MEM pass (optimize memories).
|
|
Performed a total of 0 transformations.
|
|
|
|
3.27.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations).
|
|
Performed a total of 0 transformations.
|
|
|
|
3.27.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths).
|
|
Analyzing harness_neural_director.dut.q_w_base write port 0.
|
|
Analyzing harness_neural_director.dut.q_n_tiles write port 0.
|
|
Analyzing harness_neural_director.dut.q_result_addr write port 0.
|
|
Analyzing harness_neural_director.dut.q_x_base write port 0.
|
|
|
|
3.27.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs).
|
|
|
|
3.27.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd).
|
|
Checking read port `\dut.q_w_base'[0] in module `\harness_neural_director': no output FF found.
|
|
Checking read port `\dut.q_n_tiles'[0] in module `\harness_neural_director': no output FF found.
|
|
Checking read port `\dut.q_result_addr'[0] in module `\harness_neural_director': no output FF found.
|
|
Checking read port `\dut.q_x_base'[0] in module `\harness_neural_director': no output FF found.
|
|
Checking read port address `\dut.q_w_base'[0] in module `\harness_neural_director': merged address FF to cell.
|
|
Checking read port address `\dut.q_n_tiles'[0] in module `\harness_neural_director': merged address FF to cell.
|
|
Checking read port address `\dut.q_result_addr'[0] in module `\harness_neural_director': merged address FF to cell.
|
|
Checking read port address `\dut.q_x_base'[0] in module `\harness_neural_director': merged address FF to cell.
|
|
|
|
3.27.6. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \harness_neural_director..
|
|
|
|
3.27.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells).
|
|
|
|
3.27.8. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide).
|
|
Performed a total of 0 transformations.
|
|
|
|
3.27.9. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \harness_neural_director..
|
|
|
|
3.27.10. Executing MEMORY_COLLECT pass (generating $mem cells).
|
|
|
|
3.28. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \harness_neural_director..
|
|
|
|
3.29. Executing MEMORY_LIBMAP pass (mapping memories to cells).
|
|
mapping memory harness_neural_director.dut.q_n_tiles via $__TRELLIS_DPR16X4_
|
|
Extracted addr FF from read port 0 of harness_neural_director.dut.q_n_tiles: $\dut.q_n_tiles$rdreg[0]
|
|
mapping memory harness_neural_director.dut.q_w_base via $__TRELLIS_DPR16X4_
|
|
Extracted addr FF from read port 0 of harness_neural_director.dut.q_w_base: $\dut.q_w_base$rdreg[0]
|
|
mapping memory harness_neural_director.dut.q_x_base via $__TRELLIS_DPR16X4_
|
|
Extracted addr FF from read port 0 of harness_neural_director.dut.q_x_base: $\dut.q_x_base$rdreg[0]
|
|
mapping memory harness_neural_director.dut.q_result_addr via $__TRELLIS_DPR16X4_
|
|
Extracted addr FF from read port 0 of harness_neural_director.dut.q_result_addr: $\dut.q_result_addr$rdreg[0]
|
|
<suppressed ~1782 debug messages>
|
|
|
|
3.30. Executing TECHMAP pass (map to technology primitives).
|
|
|
|
3.30.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/lutrams_map_trellis.v
|
|
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/lutrams_map_trellis.v' to AST representation.
|
|
Generating RTLIL representation for module `$__TRELLIS_DPR16X4_'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
3.30.2. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/brams_map_16kd.v
|
|
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/brams_map_16kd.v' to AST representation.
|
|
Generating RTLIL representation for module `$__DP16KD_'.
|
|
Generating RTLIL representation for module `$__PDPW16KD_'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
3.30.3. Continuing TECHMAP pass.
|
|
Using template $paramod$04778961cc1285a5efea28f98f28381eb2862208$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
|
|
No more expansions possible.
|
|
<suppressed ~40 debug messages>
|
|
|
|
3.31. Executing OPT pass (performing simple optimizations).
|
|
|
|
3.31.1. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module harness_neural_director.
|
|
<suppressed ~40 debug messages>
|
|
|
|
3.31.2. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\harness_neural_director'.
|
|
Computing hashes of 132 cells of `\harness_neural_director'.
|
|
Finding duplicate cells in `\harness_neural_director'.
|
|
Computing hashes of 129 cells of `\harness_neural_director'.
|
|
Finding duplicate cells in `\harness_neural_director'.
|
|
Computing hashes of 126 cells of `\harness_neural_director'.
|
|
Finding duplicate cells in `\harness_neural_director'.
|
|
Computing hashes of 123 cells of `\harness_neural_director'.
|
|
Finding duplicate cells in `\harness_neural_director'.
|
|
<suppressed ~27 debug messages>
|
|
Removed a total of 9 cells.
|
|
|
|
3.31.3. Executing OPT_DFF pass (perform DFF optimizations).
|
|
Adding SRST signal on $\dut.q_n_tiles$rdreg[0] ($dff) from module harness_neural_director (D = $auto$rtlil.cc:3402:Mux$895, Q = $\dut.q_n_tiles$rdreg[0]$q, rval = 3'000).
|
|
|
|
3.31.4. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \harness_neural_director..
|
|
Removed 1 unused cells and 168 unused wires.
|
|
<suppressed ~2 debug messages>
|
|
|
|
3.31.5. Rerunning OPT passes. (Removed registers in this run.)
|
|
|
|
3.31.6. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module harness_neural_director.
|
|
|
|
3.31.7. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\harness_neural_director'.
|
|
Computing hashes of 122 cells of `\harness_neural_director'.
|
|
Finding duplicate cells in `\harness_neural_director'.
|
|
Removed a total of 0 cells.
|
|
|
|
3.31.8. Executing OPT_DFF pass (perform DFF optimizations).
|
|
|
|
3.31.9. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \harness_neural_director..
|
|
|
|
3.31.10. Finished fast OPT passes.
|
|
|
|
3.32. Executing MEMORY_MAP pass (converting memories to logic and flip-flops).
|
|
|
|
3.33. Executing OPT pass (performing simple optimizations).
|
|
|
|
3.33.1. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module harness_neural_director.
|
|
|
|
3.33.2. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\harness_neural_director'.
|
|
Computing hashes of 122 cells of `\harness_neural_director'.
|
|
Finding duplicate cells in `\harness_neural_director'.
|
|
Removed a total of 0 cells.
|
|
|
|
3.33.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \harness_neural_director..
|
|
Creating internal representation of mux trees.
|
|
Evaluating internal representation of mux trees.
|
|
Analyzing evaluation results.
|
|
Removed 0 multiplexer ports.
|
|
<suppressed ~26 debug messages>
|
|
|
|
3.33.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \harness_neural_director.
|
|
Consolidated identical input bits for $pmux cell $flatten\dut.$procmux$707:
|
|
Old ports: A=4'0011, B=8'00010010, Y=$flatten\dut.$procmux$707_Y
|
|
New ports: A=2'11, B=4'0110, Y=$flatten\dut.$procmux$707_Y [1:0]
|
|
New connections: $flatten\dut.$procmux$707_Y [3:2] = 2'00
|
|
Consolidated identical input bits for $mux cell $flatten\dut.$procmux$732:
|
|
Old ports: A=2'00, B=2'11, Y=$flatten\dut.$1\done_slot_idx[1:0]
|
|
New ports: A=1'0, B=1'1, Y=$flatten\dut.$1\done_slot_idx[1:0] [0]
|
|
New connections: $flatten\dut.$1\done_slot_idx[1:0] [1] = $flatten\dut.$1\done_slot_idx[1:0] [0]
|
|
Consolidated identical input bits for $mux cell $flatten\dut.$procmux$744:
|
|
Old ports: A=2'00, B=2'11, Y=$flatten\dut.$1\free_slot_idx[1:0]
|
|
New ports: A=1'0, B=1'1, Y=$flatten\dut.$1\free_slot_idx[1:0] [0]
|
|
New connections: $flatten\dut.$1\free_slot_idx[1:0] [1] = $flatten\dut.$1\free_slot_idx[1:0] [0]
|
|
Optimizing cells in module \harness_neural_director.
|
|
Performed a total of 3 changes.
|
|
|
|
3.33.5. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\harness_neural_director'.
|
|
Computing hashes of 122 cells of `\harness_neural_director'.
|
|
Finding duplicate cells in `\harness_neural_director'.
|
|
Removed a total of 0 cells.
|
|
|
|
3.33.6. Executing OPT_DFF pass (perform DFF optimizations).
|
|
|
|
3.33.7. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \harness_neural_director..
|
|
|
|
3.33.8. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module harness_neural_director.
|
|
<suppressed ~2 debug messages>
|
|
|
|
3.33.9. Rerunning OPT passes. (Maybe there is more to do..)
|
|
|
|
3.33.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \harness_neural_director..
|
|
Creating internal representation of mux trees.
|
|
Evaluating internal representation of mux trees.
|
|
Analyzing evaluation results.
|
|
Removed 0 multiplexer ports.
|
|
<suppressed ~24 debug messages>
|
|
|
|
3.33.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \harness_neural_director.
|
|
Performed a total of 0 changes.
|
|
|
|
3.33.12. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\harness_neural_director'.
|
|
Computing hashes of 120 cells of `\harness_neural_director'.
|
|
Finding duplicate cells in `\harness_neural_director'.
|
|
Removed a total of 0 cells.
|
|
|
|
3.33.13. Executing OPT_DFF pass (perform DFF optimizations).
|
|
Setting constant 0-bit at position 2 on $auto$ff.cc:337:slice$816 ($sdffe) from module harness_neural_director.
|
|
Setting constant 0-bit at position 3 on $auto$ff.cc:337:slice$816 ($sdffe) from module harness_neural_director.
|
|
|
|
3.33.14. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \harness_neural_director..
|
|
Removed 0 unused cells and 2 unused wires.
|
|
<suppressed ~1 debug messages>
|
|
|
|
3.33.15. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module harness_neural_director.
|
|
<suppressed ~6 debug messages>
|
|
|
|
3.33.16. Rerunning OPT passes. (Maybe there is more to do..)
|
|
|
|
3.33.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \harness_neural_director..
|
|
Creating internal representation of mux trees.
|
|
Evaluating internal representation of mux trees.
|
|
Analyzing evaluation results.
|
|
Removed 0 multiplexer ports.
|
|
<suppressed ~24 debug messages>
|
|
|
|
3.33.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \harness_neural_director.
|
|
Performed a total of 0 changes.
|
|
|
|
3.33.19. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\harness_neural_director'.
|
|
Computing hashes of 120 cells of `\harness_neural_director'.
|
|
Finding duplicate cells in `\harness_neural_director'.
|
|
Removed a total of 0 cells.
|
|
|
|
3.33.20. Executing OPT_DFF pass (perform DFF optimizations).
|
|
|
|
3.33.21. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \harness_neural_director..
|
|
Removed 0 unused cells and 2 unused wires.
|
|
<suppressed ~1 debug messages>
|
|
|
|
3.33.22. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module harness_neural_director.
|
|
|
|
3.33.23. Rerunning OPT passes. (Maybe there is more to do..)
|
|
|
|
3.33.24. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \harness_neural_director..
|
|
Creating internal representation of mux trees.
|
|
Evaluating internal representation of mux trees.
|
|
Analyzing evaluation results.
|
|
Removed 0 multiplexer ports.
|
|
<suppressed ~24 debug messages>
|
|
|
|
3.33.25. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \harness_neural_director.
|
|
Performed a total of 0 changes.
|
|
|
|
3.33.26. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\harness_neural_director'.
|
|
Computing hashes of 120 cells of `\harness_neural_director'.
|
|
Finding duplicate cells in `\harness_neural_director'.
|
|
Removed a total of 0 cells.
|
|
|
|
3.33.27. Executing OPT_DFF pass (perform DFF optimizations).
|
|
|
|
3.33.28. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \harness_neural_director..
|
|
|
|
3.33.29. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module harness_neural_director.
|
|
|
|
3.33.30. Finished fast OPT passes. (There is nothing left to do.)
|
|
|
|
3.34. Executing TECHMAP pass (map to technology primitives).
|
|
|
|
3.34.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/techmap.v
|
|
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/techmap.v' to AST representation.
|
|
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
|
|
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
|
|
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
|
|
Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
|
|
Generating RTLIL representation for module `\_90_simplemap_various'.
|
|
Generating RTLIL representation for module `\_90_simplemap_registers'.
|
|
Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
|
|
Generating RTLIL representation for module `\_90_shift_shiftx'.
|
|
Generating RTLIL representation for module `\_90_fa'.
|
|
Generating RTLIL representation for module `\_90_lcu_brent_kung'.
|
|
Generating RTLIL representation for module `\_90_alu'.
|
|
Generating RTLIL representation for module `\_90_macc'.
|
|
Generating RTLIL representation for module `\_90_alumacc'.
|
|
Generating RTLIL representation for module `$__div_mod_u'.
|
|
Generating RTLIL representation for module `$__div_mod_trunc'.
|
|
Generating RTLIL representation for module `\_90_div'.
|
|
Generating RTLIL representation for module `\_90_mod'.
|
|
Generating RTLIL representation for module `$__div_mod_floor'.
|
|
Generating RTLIL representation for module `\_90_divfloor'.
|
|
Generating RTLIL representation for module `\_90_modfloor'.
|
|
Generating RTLIL representation for module `\_90_pow'.
|
|
Generating RTLIL representation for module `\_90_demux'.
|
|
Generating RTLIL representation for module `\_90_lut'.
|
|
Generating RTLIL representation for module `$connect'.
|
|
Generating RTLIL representation for module `$input_port'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
3.34.2. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v
|
|
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v' to AST representation.
|
|
Generating RTLIL representation for module `\_80_ccu2c_alu'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
3.34.3. Continuing TECHMAP pass.
|
|
Using extmapper simplemap for cells of type $xor.
|
|
Using extmapper simplemap for cells of type $sdffe.
|
|
Using extmapper simplemap for cells of type $sdff.
|
|
Using extmapper simplemap for cells of type $mux.
|
|
Using template $paramod$3ef274a4ad1e446c08416d1cf6cb5ab03146d407\_80_ccu2c_alu for cells of type $alu.
|
|
Using template $paramod$3ef7d3dd227da7627a99c5e5a6a4deb817573e39\_90_alu for cells of type $alu.
|
|
Using template $paramod$c9d98d2d0793a6d8797b9c088dbedb26a7be7121\_80_ccu2c_alu for cells of type $alu.
|
|
Using template $paramod$8742280fdebca84e1c87f2a86ed84f62d558f4cc\_90_alu for cells of type $alu.
|
|
Using template $paramod$32a7b7b86c07519b7537abc18e96f0331f97914d\_90_alu for cells of type $alu.
|
|
Using template $paramod$ef8fb1849064cca7dc908988762d3374786d9fdb\_90_alu for cells of type $alu.
|
|
Using extmapper simplemap for cells of type $reduce_or.
|
|
Using extmapper simplemap for cells of type $not.
|
|
Using extmapper simplemap for cells of type $reduce_and.
|
|
Using extmapper simplemap for cells of type $ne.
|
|
Using extmapper simplemap for cells of type $reduce_bool.
|
|
Using extmapper simplemap for cells of type $dff.
|
|
Using extmapper simplemap for cells of type $logic_not.
|
|
Using extmapper simplemap for cells of type $pmux.
|
|
Using extmapper simplemap for cells of type $eq.
|
|
Using extmapper simplemap for cells of type $logic_and.
|
|
Using extmapper simplemap for cells of type $or.
|
|
Using extmapper simplemap for cells of type $and.
|
|
Using template $paramod$constmap:d6fff7a1d5912e7277ff55b9a478b5115760128b$paramod$64b19f47ed5f126636dbd98d727ec46a7ec08d71\_90_shift_shiftx for cells of type $shift.
|
|
Using template $paramod$constmap:f30e016643cdb78b03bc6146a268597b7789262d$paramod$4e33147aa56d8c514f5e3e64af4e016a996d124e\_90_shift_shiftx for cells of type $shift.
|
|
Analyzing pattern of constant bits for this cell:
|
|
Constant input on bit 0 of port A: 1'1
|
|
Constant input on bit 1 of port A: 1'1
|
|
Constant input on bit 2 of port A: 1'1
|
|
Constant input on bit 3 of port A: 1'1
|
|
Constant input on bit 4 of port A: 1'1
|
|
Constant input on bit 5 of port A: 1'1
|
|
Constant input on bit 6 of port A: 1'1
|
|
Constant input on bit 7 of port A: 1'1
|
|
Constant input on bit 8 of port A: 1'1
|
|
Constant input on bit 9 of port A: 1'1
|
|
Constant input on bit 10 of port A: 1'1
|
|
Constant input on bit 11 of port A: 1'1
|
|
Constant input on bit 12 of port A: 1'1
|
|
Constant input on bit 13 of port A: 1'1
|
|
Constant input on bit 14 of port A: 1'1
|
|
Constant input on bit 15 of port A: 1'1
|
|
Constant input on bit 16 of port A: 1'1
|
|
Constant input on bit 17 of port A: 1'1
|
|
Constant input on bit 18 of port A: 1'1
|
|
Constant input on bit 19 of port A: 1'1
|
|
Constant input on bit 20 of port A: 1'1
|
|
Constant input on bit 21 of port A: 1'1
|
|
Constant input on bit 22 of port A: 1'1
|
|
Creating constmapped module `$paramod$constmap:fdf1d1b176de14bfd33690c77b41951c8a2dab34$paramod$4e33147aa56d8c514f5e3e64af4e016a996d124e\_90_shift_shiftx'.
|
|
|
|
3.34.30. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module $paramod$constmap:fdf1d1b176de14bfd33690c77b41951c8a2dab34$paramod$4e33147aa56d8c514f5e3e64af4e016a996d124e\_90_shift_shiftx..
|
|
Creating internal representation of mux trees.
|
|
Evaluating internal representation of mux trees.
|
|
Analyzing evaluation results.
|
|
dead port 2/2 on $mux $procmux$2056.
|
|
dead port 2/2 on $mux $procmux$2062.
|
|
dead port 2/2 on $mux $procmux$2068.
|
|
dead port 2/2 on $mux $procmux$2074.
|
|
dead port 2/2 on $mux $procmux$2080.
|
|
dead port 2/2 on $mux $procmux$2086.
|
|
dead port 2/2 on $mux $procmux$2092.
|
|
Removed 7 multiplexer ports.
|
|
<suppressed ~808 debug messages>
|
|
|
|
3.34.31. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module $paramod$constmap:fdf1d1b176de14bfd33690c77b41951c8a2dab34$paramod$4e33147aa56d8c514f5e3e64af4e016a996d124e\_90_shift_shiftx.
|
|
<suppressed ~2 debug messages>
|
|
Removed 0 unused cells and 12 unused wires.
|
|
Using template $paramod$constmap:fdf1d1b176de14bfd33690c77b41951c8a2dab34$paramod$4e33147aa56d8c514f5e3e64af4e016a996d124e\_90_shift_shiftx for cells of type $shift.
|
|
Using template $paramod$constmap:5a4bd879cde68fe23882c6a271f9c4bb8714bccb$paramod$08bf5f0725d292174acacf8edfe87d18d48f6e70\_90_shift_shiftx for cells of type $shift.
|
|
Analyzing pattern of constant bits for this cell:
|
|
Constant input on bit 0 of port A: 1'1
|
|
Constant input on bit 1 of port A: 1'1
|
|
Constant input on bit 2 of port A: 1'1
|
|
Constant input on bit 3 of port A: 1'1
|
|
Constant input on bit 4 of port A: 1'1
|
|
Constant input on bit 5 of port A: 1'1
|
|
Constant input on bit 6 of port A: 1'1
|
|
Constant input on bit 7 of port A: 1'1
|
|
Constant input on bit 8 of port A: 1'1
|
|
Constant input on bit 9 of port A: 1'1
|
|
Constant input on bit 10 of port A: 1'1
|
|
Constant input on bit 11 of port A: 1'1
|
|
Constant input on bit 12 of port A: 1'1
|
|
Constant input on bit 13 of port A: 1'1
|
|
Constant input on bit 14 of port A: 1'1
|
|
Constant input on bit 15 of port A: 1'1
|
|
Creating constmapped module `$paramod$constmap:decda5b4632abbcf04bf9650a2dac76960d9cb80$paramod$08bf5f0725d292174acacf8edfe87d18d48f6e70\_90_shift_shiftx'.
|
|
|
|
3.34.37. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module $paramod$constmap:decda5b4632abbcf04bf9650a2dac76960d9cb80$paramod$08bf5f0725d292174acacf8edfe87d18d48f6e70\_90_shift_shiftx..
|
|
Creating internal representation of mux trees.
|
|
Evaluating internal representation of mux trees.
|
|
Analyzing evaluation results.
|
|
dead port 2/2 on $mux $procmux$2380.
|
|
dead port 2/2 on $mux $procmux$2386.
|
|
dead port 2/2 on $mux $procmux$2392.
|
|
dead port 2/2 on $mux $procmux$2398.
|
|
dead port 2/2 on $mux $procmux$2404.
|
|
dead port 2/2 on $mux $procmux$2410.
|
|
dead port 2/2 on $mux $procmux$2416.
|
|
Removed 7 multiplexer ports.
|
|
<suppressed ~478 debug messages>
|
|
|
|
3.34.38. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module $paramod$constmap:decda5b4632abbcf04bf9650a2dac76960d9cb80$paramod$08bf5f0725d292174acacf8edfe87d18d48f6e70\_90_shift_shiftx.
|
|
<suppressed ~27 debug messages>
|
|
Removed 0 unused cells and 12 unused wires.
|
|
Using template $paramod$constmap:decda5b4632abbcf04bf9650a2dac76960d9cb80$paramod$08bf5f0725d292174acacf8edfe87d18d48f6e70\_90_shift_shiftx for cells of type $shift.
|
|
Using extmapper simplemap for cells of type $logic_or.
|
|
Using extmapper simplemap for cells of type $pos.
|
|
Using template $paramod\_90_fa\WIDTH=32'00000000000000000000000000000011 for cells of type $fa.
|
|
Using template $paramod\_90_lcu_brent_kung\WIDTH=32'00000000000000000000000000000011 for cells of type $lcu.
|
|
Using template $paramod\_90_fa\WIDTH=32'00000000000000000000000000000100 for cells of type $fa.
|
|
Using template $paramod\_90_lcu_brent_kung\WIDTH=32'00000000000000000000000000000100 for cells of type $lcu.
|
|
No more expansions possible.
|
|
<suppressed ~608 debug messages>
|
|
|
|
3.35. Executing OPT pass (performing simple optimizations).
|
|
|
|
3.35.1. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module harness_neural_director.
|
|
<suppressed ~8775 debug messages>
|
|
|
|
3.35.2. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\harness_neural_director'.
|
|
Computing hashes of 4902 cells of `\harness_neural_director'.
|
|
Finding duplicate cells in `\harness_neural_director'.
|
|
Computing hashes of 4819 cells of `\harness_neural_director'.
|
|
Finding duplicate cells in `\harness_neural_director'.
|
|
Computing hashes of 4767 cells of `\harness_neural_director'.
|
|
Finding duplicate cells in `\harness_neural_director'.
|
|
Computing hashes of 4719 cells of `\harness_neural_director'.
|
|
Finding duplicate cells in `\harness_neural_director'.
|
|
Computing hashes of 4679 cells of `\harness_neural_director'.
|
|
Finding duplicate cells in `\harness_neural_director'.
|
|
Computing hashes of 4655 cells of `\harness_neural_director'.
|
|
Finding duplicate cells in `\harness_neural_director'.
|
|
Computing hashes of 4654 cells of `\harness_neural_director'.
|
|
Finding duplicate cells in `\harness_neural_director'.
|
|
Computing hashes of 4653 cells of `\harness_neural_director'.
|
|
Finding duplicate cells in `\harness_neural_director'.
|
|
Computing hashes of 4652 cells of `\harness_neural_director'.
|
|
Finding duplicate cells in `\harness_neural_director'.
|
|
Computing hashes of 4651 cells of `\harness_neural_director'.
|
|
Finding duplicate cells in `\harness_neural_director'.
|
|
Computing hashes of 4650 cells of `\harness_neural_director'.
|
|
Finding duplicate cells in `\harness_neural_director'.
|
|
Computing hashes of 4649 cells of `\harness_neural_director'.
|
|
Finding duplicate cells in `\harness_neural_director'.
|
|
Computing hashes of 4648 cells of `\harness_neural_director'.
|
|
Finding duplicate cells in `\harness_neural_director'.
|
|
Computing hashes of 4647 cells of `\harness_neural_director'.
|
|
Finding duplicate cells in `\harness_neural_director'.
|
|
Computing hashes of 4646 cells of `\harness_neural_director'.
|
|
Finding duplicate cells in `\harness_neural_director'.
|
|
Computing hashes of 4645 cells of `\harness_neural_director'.
|
|
Finding duplicate cells in `\harness_neural_director'.
|
|
Computing hashes of 4644 cells of `\harness_neural_director'.
|
|
Finding duplicate cells in `\harness_neural_director'.
|
|
Computing hashes of 4643 cells of `\harness_neural_director'.
|
|
Finding duplicate cells in `\harness_neural_director'.
|
|
Computing hashes of 4642 cells of `\harness_neural_director'.
|
|
Finding duplicate cells in `\harness_neural_director'.
|
|
Computing hashes of 4641 cells of `\harness_neural_director'.
|
|
Finding duplicate cells in `\harness_neural_director'.
|
|
Computing hashes of 4640 cells of `\harness_neural_director'.
|
|
Finding duplicate cells in `\harness_neural_director'.
|
|
Computing hashes of 4639 cells of `\harness_neural_director'.
|
|
Finding duplicate cells in `\harness_neural_director'.
|
|
Computing hashes of 4638 cells of `\harness_neural_director'.
|
|
Finding duplicate cells in `\harness_neural_director'.
|
|
Computing hashes of 4637 cells of `\harness_neural_director'.
|
|
Finding duplicate cells in `\harness_neural_director'.
|
|
Computing hashes of 4636 cells of `\harness_neural_director'.
|
|
Finding duplicate cells in `\harness_neural_director'.
|
|
Computing hashes of 4635 cells of `\harness_neural_director'.
|
|
Finding duplicate cells in `\harness_neural_director'.
|
|
<suppressed ~801 debug messages>
|
|
Removed a total of 267 cells.
|
|
|
|
3.35.3. Executing OPT_DFF pass (perform DFF optimizations).
|
|
|
|
3.35.4. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \harness_neural_director..
|
|
Removed 3313 unused cells and 556 unused wires.
|
|
<suppressed ~3316 debug messages>
|
|
|
|
3.35.5. Finished fast OPT passes.
|
|
|
|
3.36. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \harness_neural_director..
|
|
|
|
3.37. Executing DFFLEGALIZE pass (convert FFs to types supported by the target).
|
|
|
|
3.38. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\harness_neural_director'.
|
|
Computing hashes of 1322 cells of `\harness_neural_director'.
|
|
Finding duplicate cells in `\harness_neural_director'.
|
|
Removed a total of 0 cells.
|
|
|
|
3.39. Executing TECHMAP pass (map to technology primitives).
|
|
|
|
3.39.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v
|
|
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v' to AST representation.
|
|
Generating RTLIL representation for module `$_DFF_N_'.
|
|
Generating RTLIL representation for module `$_DFF_P_'.
|
|
Generating RTLIL representation for module `$_DFFE_NN_'.
|
|
Generating RTLIL representation for module `$_DFFE_PN_'.
|
|
Generating RTLIL representation for module `$_DFFE_NP_'.
|
|
Generating RTLIL representation for module `$_DFFE_PP_'.
|
|
Generating RTLIL representation for module `$_DFF_NP0_'.
|
|
Generating RTLIL representation for module `$_DFF_NP1_'.
|
|
Generating RTLIL representation for module `$_DFF_PP0_'.
|
|
Generating RTLIL representation for module `$_DFF_PP1_'.
|
|
Generating RTLIL representation for module `$_SDFF_NP0_'.
|
|
Generating RTLIL representation for module `$_SDFF_NP1_'.
|
|
Generating RTLIL representation for module `$_SDFF_PP0_'.
|
|
Generating RTLIL representation for module `$_SDFF_PP1_'.
|
|
Generating RTLIL representation for module `$_DFFE_NP0P_'.
|
|
Generating RTLIL representation for module `$_DFFE_NP1P_'.
|
|
Generating RTLIL representation for module `$_DFFE_PP0P_'.
|
|
Generating RTLIL representation for module `$_DFFE_PP1P_'.
|
|
Generating RTLIL representation for module `$_DFFE_NP0N_'.
|
|
Generating RTLIL representation for module `$_DFFE_NP1N_'.
|
|
Generating RTLIL representation for module `$_DFFE_PP0N_'.
|
|
Generating RTLIL representation for module `$_DFFE_PP1N_'.
|
|
Generating RTLIL representation for module `$_SDFFE_NP0P_'.
|
|
Generating RTLIL representation for module `$_SDFFE_NP1P_'.
|
|
Generating RTLIL representation for module `$_SDFFE_PP0P_'.
|
|
Generating RTLIL representation for module `$_SDFFE_PP1P_'.
|
|
Generating RTLIL representation for module `$_SDFFE_NP0N_'.
|
|
Generating RTLIL representation for module `$_SDFFE_NP1N_'.
|
|
Generating RTLIL representation for module `$_SDFFE_PP0N_'.
|
|
Generating RTLIL representation for module `$_SDFFE_PP1N_'.
|
|
Generating RTLIL representation for module `$_ALDFF_NP_'.
|
|
Generating RTLIL representation for module `$_ALDFF_PP_'.
|
|
Generating RTLIL representation for module `$_ALDFFE_NPN_'.
|
|
Generating RTLIL representation for module `$_ALDFFE_NPP_'.
|
|
Generating RTLIL representation for module `$_ALDFFE_PPN_'.
|
|
Generating RTLIL representation for module `$_ALDFFE_PPP_'.
|
|
Generating RTLIL representation for module `\FD1P3AX'.
|
|
Generating RTLIL representation for module `\FD1P3AY'.
|
|
Generating RTLIL representation for module `\FD1P3BX'.
|
|
Generating RTLIL representation for module `\FD1P3DX'.
|
|
Generating RTLIL representation for module `\FD1P3IX'.
|
|
Generating RTLIL representation for module `\FD1P3JX'.
|
|
Generating RTLIL representation for module `\FD1S3AX'.
|
|
Generating RTLIL representation for module `\FD1S3AY'.
|
|
Generating RTLIL representation for module `\FD1S3BX'.
|
|
Generating RTLIL representation for module `\FD1S3DX'.
|
|
Generating RTLIL representation for module `\FD1S3IX'.
|
|
Generating RTLIL representation for module `\FD1S3JX'.
|
|
Generating RTLIL representation for module `\IFS1P3BX'.
|
|
Generating RTLIL representation for module `\IFS1P3DX'.
|
|
Generating RTLIL representation for module `\IFS1P3IX'.
|
|
Generating RTLIL representation for module `\IFS1P3JX'.
|
|
Generating RTLIL representation for module `\OFS1P3BX'.
|
|
Generating RTLIL representation for module `\OFS1P3DX'.
|
|
Generating RTLIL representation for module `\OFS1P3IX'.
|
|
Generating RTLIL representation for module `\OFS1P3JX'.
|
|
Generating RTLIL representation for module `\IB'.
|
|
Generating RTLIL representation for module `\IBPU'.
|
|
Generating RTLIL representation for module `\IBPD'.
|
|
Generating RTLIL representation for module `\OB'.
|
|
Generating RTLIL representation for module `\OBZ'.
|
|
Generating RTLIL representation for module `\OBZPU'.
|
|
Generating RTLIL representation for module `\OBZPD'.
|
|
Generating RTLIL representation for module `\OBCO'.
|
|
Generating RTLIL representation for module `\BB'.
|
|
Generating RTLIL representation for module `\BBPU'.
|
|
Generating RTLIL representation for module `\BBPD'.
|
|
Generating RTLIL representation for module `\ILVDS'.
|
|
Generating RTLIL representation for module `\OLVDS'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
3.39.2. Continuing TECHMAP pass.
|
|
Using template $paramod$_DFF_P_\_TECHMAP_WIREINIT_Q_=1'x for cells of type $_DFF_P_.
|
|
Using template $_SDFF_PP0_ for cells of type $_SDFF_PP0_.
|
|
Using template $_SDFF_PP1_ for cells of type $_SDFF_PP1_.
|
|
Using template $_SDFFE_PP0P_ for cells of type $_SDFFE_PP0P_.
|
|
No more expansions possible.
|
|
<suppressed ~180 debug messages>
|
|
|
|
3.40. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module harness_neural_director.
|
|
<suppressed ~314 debug messages>
|
|
|
|
3.41. Executing SIMPLEMAP pass (map simple cells to gate primitives).
|
|
|
|
3.42. Executing LATTICE_GSR pass (implement FF init values).
|
|
Handling GSR in harness_neural_director.
|
|
|
|
3.43. Executing ATTRMVCP pass (move or copy attributes).
|
|
|
|
3.44. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \harness_neural_director..
|
|
Removed 0 unused cells and 530 unused wires.
|
|
<suppressed ~1 debug messages>
|
|
|
|
3.45. Executing CHECK pass (checking for obvious problems).
|
|
Checking module harness_neural_director...
|
|
Found and reported 0 problems.
|
|
|
|
3.46. Executing TECHMAP pass (map to technology primitives).
|
|
|
|
3.46.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/latches_map.v
|
|
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/latches_map.v' to AST representation.
|
|
Generating RTLIL representation for module `$_DLATCH_N_'.
|
|
Generating RTLIL representation for module `$_DLATCH_P_'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
3.46.2. Continuing TECHMAP pass.
|
|
No more expansions possible.
|
|
<suppressed ~4 debug messages>
|
|
|
|
3.47. Executing ABC9 pass.
|
|
|
|
3.47.1. Executing ABC9_OPS pass (helper functions for ABC9).
|
|
|
|
3.47.2. Executing ABC9_OPS pass (helper functions for ABC9).
|
|
|
|
3.47.3. Executing PROC pass (convert processes to netlists).
|
|
|
|
3.47.3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
|
|
Found and cleaned up 1 empty switch in `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:151$15620'.
|
|
Cleaned up 1 empty switch.
|
|
|
|
3.47.3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
|
|
Marked 1 switch rules as full_case in process $proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:159$15621 in module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.
|
|
Removed a total of 0 dead cases.
|
|
|
|
3.47.3.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
|
|
Removed 0 redundant assignments.
|
|
Promoted 22 assignments to connections.
|
|
|
|
3.47.3.4. Executing PROC_INIT pass (extract init attributes).
|
|
|
|
3.47.3.5. Executing PROC_ARST pass (detect async resets in processes).
|
|
|
|
3.47.3.6. Executing PROC_ROM pass (convert switches to ROMs).
|
|
Converted 0 switches.
|
|
<suppressed ~1 debug messages>
|
|
|
|
3.47.3.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
|
|
Creating decoders for process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$15645'.
|
|
Creating decoders for process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:159$15621'.
|
|
1/3: $1$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:161$15619_EN[3:0]$15627
|
|
2/3: $1$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:161$15619_DATA[3:0]$15626
|
|
3/3: $1$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:161$15619_ADDR[3:0]$15625
|
|
Creating decoders for process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:151$15620'.
|
|
|
|
3.47.3.8. Executing PROC_DLATCH pass (convert process syncs to latches).
|
|
No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.\i' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$15645'.
|
|
No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:145$15603_EN' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$15645'.
|
|
No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:145$15604_EN' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$15645'.
|
|
No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:145$15605_EN' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$15645'.
|
|
No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:145$15606_EN' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$15645'.
|
|
No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:145$15607_EN' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$15645'.
|
|
No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:145$15608_EN' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$15645'.
|
|
No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:145$15609_EN' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$15645'.
|
|
No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:145$15610_EN' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$15645'.
|
|
No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:145$15611_EN' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$15645'.
|
|
No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:145$15612_EN' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$15645'.
|
|
No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:145$15613_EN' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$15645'.
|
|
No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:145$15614_EN' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$15645'.
|
|
No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:145$15615_EN' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$15645'.
|
|
No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:145$15616_EN' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$15645'.
|
|
No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:145$15617_EN' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$15645'.
|
|
No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:145$15618_EN' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$15645'.
|
|
No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.\muxwre' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:151$15620'.
|
|
|
|
3.47.3.9. Executing PROC_DFF pass (convert process syncs to FFs).
|
|
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:161$15619_ADDR' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:159$15621'.
|
|
created $dff cell `$procdff$15671' with positive edge clock.
|
|
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:161$15619_DATA' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:159$15621'.
|
|
created $dff cell `$procdff$15672' with positive edge clock.
|
|
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:161$15619_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:159$15621'.
|
|
created $dff cell `$procdff$15673' with positive edge clock.
|
|
|
|
3.47.3.10. Executing PROC_MEMWR pass (convert process memory writes to cells).
|
|
|
|
3.47.3.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
|
|
Removing empty process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$15645'.
|
|
Found and cleaned up 1 empty switch in `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:159$15621'.
|
|
Removing empty process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:159$15621'.
|
|
Removing empty process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:151$15620'.
|
|
Cleaned up 1 empty switch.
|
|
|
|
3.47.4. Executing SCC pass (detecting logic loops).
|
|
Found 0 SCCs in module harness_neural_director.
|
|
Found 0 SCCs.
|
|
|
|
3.47.5. Executing ABC9_OPS pass (helper functions for ABC9).
|
|
|
|
3.47.6. Executing TECHMAP pass (map to technology primitives).
|
|
|
|
3.47.6.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/techmap.v
|
|
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/techmap.v' to AST representation.
|
|
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
|
|
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
|
|
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
|
|
Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
|
|
Generating RTLIL representation for module `\_90_simplemap_various'.
|
|
Generating RTLIL representation for module `\_90_simplemap_registers'.
|
|
Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
|
|
Generating RTLIL representation for module `\_90_shift_shiftx'.
|
|
Generating RTLIL representation for module `\_90_fa'.
|
|
Generating RTLIL representation for module `\_90_lcu_brent_kung'.
|
|
Generating RTLIL representation for module `\_90_alu'.
|
|
Generating RTLIL representation for module `\_90_macc'.
|
|
Generating RTLIL representation for module `\_90_alumacc'.
|
|
Generating RTLIL representation for module `$__div_mod_u'.
|
|
Generating RTLIL representation for module `$__div_mod_trunc'.
|
|
Generating RTLIL representation for module `\_90_div'.
|
|
Generating RTLIL representation for module `\_90_mod'.
|
|
Generating RTLIL representation for module `$__div_mod_floor'.
|
|
Generating RTLIL representation for module `\_90_divfloor'.
|
|
Generating RTLIL representation for module `\_90_modfloor'.
|
|
Generating RTLIL representation for module `\_90_pow'.
|
|
Generating RTLIL representation for module `\_90_demux'.
|
|
Generating RTLIL representation for module `\_90_lut'.
|
|
Generating RTLIL representation for module `$connect'.
|
|
Generating RTLIL representation for module `$input_port'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
3.47.6.2. Continuing TECHMAP pass.
|
|
No more expansions possible.
|
|
<suppressed ~168 debug messages>
|
|
|
|
3.47.7. Executing OPT pass (performing simple optimizations).
|
|
|
|
3.47.7.1. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.
|
|
|
|
3.47.7.2. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4'.
|
|
Computing hashes of 2 cells of `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4'.
|
|
Finding duplicate cells in `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4'.
|
|
Removed a total of 0 cells.
|
|
|
|
3.47.7.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4..
|
|
Creating internal representation of mux trees.
|
|
No muxes found in this module.
|
|
Removed 0 multiplexer ports.
|
|
|
|
3.47.7.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.
|
|
Performed a total of 0 changes.
|
|
|
|
3.47.7.5. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4'.
|
|
Computing hashes of 2 cells of `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4'.
|
|
Finding duplicate cells in `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4'.
|
|
Removed a total of 0 cells.
|
|
|
|
3.47.7.6. Executing OPT_DFF pass (perform DFF optimizations).
|
|
|
|
3.47.7.7. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4..
|
|
|
|
3.47.7.8. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.
|
|
|
|
3.47.7.9. Finished fast OPT passes. (There is nothing left to do.)
|
|
|
|
3.47.8. Executing TECHMAP pass (map to technology primitives).
|
|
|
|
3.47.8.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/abc9_map.v
|
|
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/abc9_map.v' to AST representation.
|
|
Successfully finished Verilog frontend.
|
|
|
|
3.47.8.2. Continuing TECHMAP pass.
|
|
Using template $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4 for cells of type $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.
|
|
No more expansions possible.
|
|
<suppressed ~25 debug messages>
|
|
|
|
3.47.9. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/abc9_model.v
|
|
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/abc9_model.v' to AST representation.
|
|
Generating RTLIL representation for module `$__ABC9_DELAY'.
|
|
Generating RTLIL representation for module `$__ABC9_SCC_BREAKER'.
|
|
Generating RTLIL representation for module `$__DFF_N__$abc9_flop'.
|
|
Generating RTLIL representation for module `$__DFF_P__$abc9_flop'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
3.47.10. Executing ABC9_OPS pass (helper functions for ABC9).
|
|
<suppressed ~2 debug messages>
|
|
|
|
3.47.11. Executing ABC9_OPS pass (helper functions for ABC9).
|
|
|
|
3.47.12. Executing ABC9_OPS pass (helper functions for ABC9).
|
|
<suppressed ~2 debug messages>
|
|
|
|
3.47.13. Executing TECHMAP pass (map to technology primitives).
|
|
|
|
3.47.13.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/techmap.v
|
|
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/techmap.v' to AST representation.
|
|
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
|
|
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
|
|
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
|
|
Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
|
|
Generating RTLIL representation for module `\_90_simplemap_various'.
|
|
Generating RTLIL representation for module `\_90_simplemap_registers'.
|
|
Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
|
|
Generating RTLIL representation for module `\_90_shift_shiftx'.
|
|
Generating RTLIL representation for module `\_90_fa'.
|
|
Generating RTLIL representation for module `\_90_lcu_brent_kung'.
|
|
Generating RTLIL representation for module `\_90_alu'.
|
|
Generating RTLIL representation for module `\_90_macc'.
|
|
Generating RTLIL representation for module `\_90_alumacc'.
|
|
Generating RTLIL representation for module `$__div_mod_u'.
|
|
Generating RTLIL representation for module `$__div_mod_trunc'.
|
|
Generating RTLIL representation for module `\_90_div'.
|
|
Generating RTLIL representation for module `\_90_mod'.
|
|
Generating RTLIL representation for module `$__div_mod_floor'.
|
|
Generating RTLIL representation for module `\_90_divfloor'.
|
|
Generating RTLIL representation for module `\_90_modfloor'.
|
|
Generating RTLIL representation for module `\_90_pow'.
|
|
Generating RTLIL representation for module `\_90_demux'.
|
|
Generating RTLIL representation for module `\_90_lut'.
|
|
Generating RTLIL representation for module `$connect'.
|
|
Generating RTLIL representation for module `$input_port'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
3.47.13.2. Continuing TECHMAP pass.
|
|
Using template $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C for cells of type $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C.
|
|
Using extmapper simplemap for cells of type $or.
|
|
Using extmapper simplemap for cells of type $and.
|
|
Using extmapper simplemap for cells of type $not.
|
|
Using extmapper simplemap for cells of type $xor.
|
|
Using template $paramod\LUT2\INIT=4'1010 for cells of type LUT2.
|
|
Using template $paramod\LUT4\INIT=16'1001011010101010 for cells of type LUT4.
|
|
Using extmapper simplemap for cells of type $mux.
|
|
No more expansions possible.
|
|
<suppressed ~207 debug messages>
|
|
|
|
3.47.14. Executing OPT pass (performing simple optimizations).
|
|
|
|
3.47.14.1. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module harness_neural_director.
|
|
<suppressed ~18 debug messages>
|
|
|
|
3.47.14.2. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\harness_neural_director'.
|
|
Computing hashes of 59 cells of `\harness_neural_director'.
|
|
Finding duplicate cells in `\harness_neural_director'.
|
|
Computing hashes of 57 cells of `\harness_neural_director'.
|
|
Finding duplicate cells in `\harness_neural_director'.
|
|
<suppressed ~6 debug messages>
|
|
Removed a total of 2 cells.
|
|
|
|
3.47.14.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \harness_neural_director..
|
|
Creating internal representation of mux trees.
|
|
No muxes found in this module.
|
|
Removed 0 multiplexer ports.
|
|
|
|
3.47.14.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \harness_neural_director.
|
|
Performed a total of 0 changes.
|
|
|
|
3.47.14.5. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\harness_neural_director'.
|
|
Computing hashes of 57 cells of `\harness_neural_director'.
|
|
Finding duplicate cells in `\harness_neural_director'.
|
|
Removed a total of 0 cells.
|
|
|
|
3.47.14.6. Executing OPT_DFF pass (perform DFF optimizations).
|
|
|
|
3.47.14.7. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \harness_neural_director..
|
|
Removed 0 unused cells and 55 unused wires.
|
|
<suppressed ~1 debug messages>
|
|
|
|
3.47.14.8. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module harness_neural_director.
|
|
|
|
3.47.14.9. Rerunning OPT passes. (Maybe there is more to do..)
|
|
|
|
3.47.14.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \harness_neural_director..
|
|
Creating internal representation of mux trees.
|
|
No muxes found in this module.
|
|
Removed 0 multiplexer ports.
|
|
|
|
3.47.14.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \harness_neural_director.
|
|
Performed a total of 0 changes.
|
|
|
|
3.47.14.12. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\harness_neural_director'.
|
|
Computing hashes of 57 cells of `\harness_neural_director'.
|
|
Finding duplicate cells in `\harness_neural_director'.
|
|
Removed a total of 0 cells.
|
|
|
|
3.47.14.13. Executing OPT_DFF pass (perform DFF optimizations).
|
|
|
|
3.47.14.14. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \harness_neural_director..
|
|
|
|
3.47.14.15. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module harness_neural_director.
|
|
|
|
3.47.14.16. Finished fast OPT passes. (There is nothing left to do.)
|
|
|
|
3.47.15. Executing AIGMAP pass (map logic to AIG).
|
|
Module harness_neural_director: replaced 18 cells with 120 new cells, skipped 39 cells.
|
|
replaced 3 cell types:
|
|
14 $_MUX_
|
|
2 $_OR_
|
|
2 $_XOR_
|
|
not replaced 3 cell types:
|
|
4 $_AND_
|
|
4 $_NOT_
|
|
31 $specify2
|
|
|
|
3.47.16. Executing AIGMAP pass (map logic to AIG).
|
|
Module harness_neural_director: replaced 1065 cells with 7191 new cells, skipped 268 cells.
|
|
replaced 3 cell types:
|
|
896 $_MUX_
|
|
88 $_OR_
|
|
81 $_XOR_
|
|
not replaced 7 cell types:
|
|
52 $_AND_
|
|
52 $_NOT_
|
|
1 $scopeinfo
|
|
98 TRELLIS_FF
|
|
21 $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C
|
|
22 $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4
|
|
22 $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4_$abc9_byp
|
|
|
|
3.47.16.1. Executing ABC9_OPS pass (helper functions for ABC9).
|
|
|
|
3.47.16.2. Executing ABC9_OPS pass (helper functions for ABC9).
|
|
|
|
3.47.16.3. Executing XAIGER backend.
|
|
<suppressed ~11 debug messages>
|
|
Extracted 3071 AND gates and 7719 wires from module `harness_neural_director' to a netlist network with 196 inputs and 125 outputs.
|
|
|
|
3.47.16.4. Executing ABC9_EXE pass (technology mapping using ABC9).
|
|
|
|
3.47.16.5. Executing ABC9.
|
|
Running ABC command: "<yosys-exe-dir>/yosys-abc" -s -f <abc-temp-dir>/abc.script 2>&1
|
|
ABC: ======== ABC command line "source <abc-temp-dir>/abc.script"
|
|
ABC: + read_lut <abc-temp-dir>/input.lut
|
|
ABC: + read_box <abc-temp-dir>/input.box
|
|
ABC: + &read <abc-temp-dir>/input.xaig
|
|
ABC: + &ps
|
|
ABC: <abc-temp-dir>/input : i/o = 196/ 125 and = 2092 lev = 41 (1.99) mem = 0.04 MB box = 43 bb = 22
|
|
ABC: + &scorr
|
|
ABC: Warning: The network is combinational.
|
|
ABC: + &sweep
|
|
ABC: + &dc2
|
|
ABC: + &dch -f -r
|
|
ABC: + &ps
|
|
ABC: <abc-temp-dir>/input : i/o = 196/ 125 and = 622 lev = 12 (1.14) mem = 0.02 MB ch = 83 box = 12 bb = 8
|
|
ABC: cst = 0 cls = 80 lit = 83 unused = 699 proof = 0
|
|
ABC: + &if -W 300 -v
|
|
ABC: K = 7. Memory (bytes): Truth = 0. Cut = 76. Obj = 156. Set = 780. CutMin = no
|
|
ABC: Node = 622. Ch = 80. Total mem = 0.18 MB. Peak cut mem = 0.01 MB.
|
|
ABC: P: Del = 1909.00. Ar = 150.0. Edge = 319. Cut = 5224. T = 0.00 sec
|
|
ABC: P: Del = 1909.00. Ar = 145.0. Edge = 313. Cut = 5116. T = 0.00 sec
|
|
ABC: P: Del = 1909.00. Ar = 104.0. Edge = 302. Cut = 6433. T = 0.00 sec
|
|
ABC: F: Del = 1909.00. Ar = 104.0. Edge = 295. Cut = 5867. T = 0.00 sec
|
|
ABC: A: Del = 1909.00. Ar = 104.0. Edge = 289. Cut = 5947. T = 0.00 sec
|
|
ABC: A: Del = 1909.00. Ar = 104.0. Edge = 289. Cut = 5928. T = 0.00 sec
|
|
ABC: Total time = 0.00 sec
|
|
ABC: + &write -n <abc-temp-dir>/output.aig
|
|
ABC: + &mfs
|
|
ABC: + &ps -l
|
|
ABC: <abc-temp-dir>/input : i/o = 196/ 125 and = 513 lev = 12 (1.13) mem = 0.01 MB box = 12 bb = 8
|
|
ABC: Mapping (K=7) : lut = 87 edge = 288 lev = 3 (0.47) levB = 5 mem = 0.01 MB
|
|
ABC: LUT = 87 : 2=12 13.8 % 3=47 54.0 % 4=20 23.0 % 5=6 6.9 % 6=1 1.1 % 7=1 1.1 % Ave = 3.31
|
|
ABC: + &write -n <abc-temp-dir>/output.aig
|
|
ABC: + &verify
|
|
ABC: Networks are equivalent. Time = 0.01 sec
|
|
ABC: + time
|
|
ABC: elapse: 0.03 seconds, total: 0.03 seconds
|
|
|
|
3.47.16.6. Executing AIGER frontend.
|
|
<suppressed ~10 debug messages>
|
|
Removed 937 unused cells and 1357 unused wires.
|
|
|
|
3.47.16.7. Executing ABC_OPS_REINTEGRATE pass (reintegrate ABC mapped design into module).
|
|
ABC RESULTS: $lut cells: 91
|
|
ABC RESULTS: $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C cells: 4
|
|
ABC RESULTS: $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4_$abc9_byp cells: 8
|
|
ABC RESULTS: input signals: 36
|
|
ABC RESULTS: output signals: 29
|
|
<suppressed ~673 debug messages>
|
|
Removing temp directory.
|
|
|
|
3.47.17. Executing TECHMAP pass (map to technology primitives).
|
|
|
|
3.47.17.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/abc9_unmap.v
|
|
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/abc9_unmap.v' to AST representation.
|
|
Generating RTLIL representation for module `$__DFF_x__$abc9_flop'.
|
|
Generating RTLIL representation for module `$__ABC9_SCC_BREAKER'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
3.47.17.2. Continuing TECHMAP pass.
|
|
Using template $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4 for cells of type $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.
|
|
Using template $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C for cells of type $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C.
|
|
Using template $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4_$abc9_byp.
|
|
No more expansions possible.
|
|
<suppressed ~42 debug messages>
|
|
Removed 34 unused cells and 8174 unused wires.
|
|
|
|
3.48. Executing TECHMAP pass (map to technology primitives).
|
|
|
|
3.48.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v
|
|
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v' to AST representation.
|
|
Generating RTLIL representation for module `$_DFF_N_'.
|
|
Generating RTLIL representation for module `$_DFF_P_'.
|
|
Generating RTLIL representation for module `$_DFFE_NN_'.
|
|
Generating RTLIL representation for module `$_DFFE_PN_'.
|
|
Generating RTLIL representation for module `$_DFFE_NP_'.
|
|
Generating RTLIL representation for module `$_DFFE_PP_'.
|
|
Generating RTLIL representation for module `$_DFF_NP0_'.
|
|
Generating RTLIL representation for module `$_DFF_NP1_'.
|
|
Generating RTLIL representation for module `$_DFF_PP0_'.
|
|
Generating RTLIL representation for module `$_DFF_PP1_'.
|
|
Generating RTLIL representation for module `$_SDFF_NP0_'.
|
|
Generating RTLIL representation for module `$_SDFF_NP1_'.
|
|
Generating RTLIL representation for module `$_SDFF_PP0_'.
|
|
Generating RTLIL representation for module `$_SDFF_PP1_'.
|
|
Generating RTLIL representation for module `$_DFFE_NP0P_'.
|
|
Generating RTLIL representation for module `$_DFFE_NP1P_'.
|
|
Generating RTLIL representation for module `$_DFFE_PP0P_'.
|
|
Generating RTLIL representation for module `$_DFFE_PP1P_'.
|
|
Generating RTLIL representation for module `$_DFFE_NP0N_'.
|
|
Generating RTLIL representation for module `$_DFFE_NP1N_'.
|
|
Generating RTLIL representation for module `$_DFFE_PP0N_'.
|
|
Generating RTLIL representation for module `$_DFFE_PP1N_'.
|
|
Generating RTLIL representation for module `$_SDFFE_NP0P_'.
|
|
Generating RTLIL representation for module `$_SDFFE_NP1P_'.
|
|
Generating RTLIL representation for module `$_SDFFE_PP0P_'.
|
|
Generating RTLIL representation for module `$_SDFFE_PP1P_'.
|
|
Generating RTLIL representation for module `$_SDFFE_NP0N_'.
|
|
Generating RTLIL representation for module `$_SDFFE_NP1N_'.
|
|
Generating RTLIL representation for module `$_SDFFE_PP0N_'.
|
|
Generating RTLIL representation for module `$_SDFFE_PP1N_'.
|
|
Generating RTLIL representation for module `$_ALDFF_NP_'.
|
|
Generating RTLIL representation for module `$_ALDFF_PP_'.
|
|
Generating RTLIL representation for module `$_ALDFFE_NPN_'.
|
|
Generating RTLIL representation for module `$_ALDFFE_NPP_'.
|
|
Generating RTLIL representation for module `$_ALDFFE_PPN_'.
|
|
Generating RTLIL representation for module `$_ALDFFE_PPP_'.
|
|
Generating RTLIL representation for module `\FD1P3AX'.
|
|
Generating RTLIL representation for module `\FD1P3AY'.
|
|
Generating RTLIL representation for module `\FD1P3BX'.
|
|
Generating RTLIL representation for module `\FD1P3DX'.
|
|
Generating RTLIL representation for module `\FD1P3IX'.
|
|
Generating RTLIL representation for module `\FD1P3JX'.
|
|
Generating RTLIL representation for module `\FD1S3AX'.
|
|
Generating RTLIL representation for module `\FD1S3AY'.
|
|
Generating RTLIL representation for module `\FD1S3BX'.
|
|
Generating RTLIL representation for module `\FD1S3DX'.
|
|
Generating RTLIL representation for module `\FD1S3IX'.
|
|
Generating RTLIL representation for module `\FD1S3JX'.
|
|
Generating RTLIL representation for module `\IFS1P3BX'.
|
|
Generating RTLIL representation for module `\IFS1P3DX'.
|
|
Generating RTLIL representation for module `\IFS1P3IX'.
|
|
Generating RTLIL representation for module `\IFS1P3JX'.
|
|
Generating RTLIL representation for module `\OFS1P3BX'.
|
|
Generating RTLIL representation for module `\OFS1P3DX'.
|
|
Generating RTLIL representation for module `\OFS1P3IX'.
|
|
Generating RTLIL representation for module `\OFS1P3JX'.
|
|
Generating RTLIL representation for module `\IB'.
|
|
Generating RTLIL representation for module `\IBPU'.
|
|
Generating RTLIL representation for module `\IBPD'.
|
|
Generating RTLIL representation for module `\OB'.
|
|
Generating RTLIL representation for module `\OBZ'.
|
|
Generating RTLIL representation for module `\OBZPU'.
|
|
Generating RTLIL representation for module `\OBZPD'.
|
|
Generating RTLIL representation for module `\OBCO'.
|
|
Generating RTLIL representation for module `\BB'.
|
|
Generating RTLIL representation for module `\BBPU'.
|
|
Generating RTLIL representation for module `\BBPD'.
|
|
Generating RTLIL representation for module `\ILVDS'.
|
|
Generating RTLIL representation for module `\OLVDS'.
|
|
Generating RTLIL representation for module `$lut'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
3.48.2. Continuing TECHMAP pass.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0010 for cells of type $lut.
|
|
Using template $paramod$d5841602ab17202e972b290147d14b63f75b0ad1$lut for cells of type $lut.
|
|
Using template $paramod$359fe4e746656bf9c72aecaff84fc7bdea9f55a5$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1011 for cells of type $lut.
|
|
Using template $paramod$fd904e9e35cfd343a9df248824bd3f1408724879$lut for cells of type $lut.
|
|
Using template $paramod$571404c0889eaf57f492cb5e37f8acb5df5852f9$lut for cells of type $lut.
|
|
Using template $paramod$658b9ed803f0d3d335616d3858b53e0a2522f1e8$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000001 for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1101 for cells of type $lut.
|
|
Using template $paramod$e5759512db67494ff77fbdfc66dff4006376568f$lut for cells of type $lut.
|
|
Using template $paramod$b51fee016110db8338dd45ff659d0ba2666c78b1$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0110 for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01101010 for cells of type $lut.
|
|
Using template $paramod$4282def8dbd6df3d1248ad282c629bee684502c2$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01101001 for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0100 for cells of type $lut.
|
|
Using template $paramod$d9e869de4ea8677851dc452d380224cee441f821$lut for cells of type $lut.
|
|
Using template $paramod$a5516fc31d1e552de2435200bb732b4d4ad63a9c$lut for cells of type $lut.
|
|
Using template $paramod$a982cf8779b70ec0ac96f44f3dab0c5228c954b0$lut for cells of type $lut.
|
|
Using template $paramod$766866f5aa0715f9d5b453950f9c60b7c05612b0$lut for cells of type $lut.
|
|
Using template $paramod$6d6beead1425af15cf78b27fd9b11b41b5d4bce8$lut for cells of type $lut.
|
|
Using template $paramod$59848369e5f408d15e0c8c710ff689c98ce02999$lut for cells of type $lut.
|
|
Using template $paramod$f5c97e291c8b48d9f1b4239d871ab7639e5a24ac$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11001010 for cells of type $lut.
|
|
Using template $paramod$21a9cf1c7cffed4ea7970972274e8bcced7c7005$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11100010 for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10111000 for cells of type $lut.
|
|
Using template $paramod$cd6c4b4da6d8737b72fd2dc8f5d83d8967445809$lut for cells of type $lut.
|
|
Using template $paramod$7aa8140c7d6de3160b21e7ff84e0f93f69f7fcc6$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1000 for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01101100 for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10010110 for cells of type $lut.
|
|
Using template $paramod$5fd0af7ac35c6c117464e59fb19cf691eb70ce85$lut for cells of type $lut.
|
|
Using template $paramod$bba54c1ef87367812b4c15f4aed5ac70773df775$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000001\LUT=2'01 for cells of type $lut.
|
|
No more expansions possible.
|
|
<suppressed ~618 debug messages>
|
|
|
|
3.49. Executing OPT_LUT_INS pass (discard unused LUT inputs).
|
|
Optimizing LUTs in harness_neural_director.
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$30530.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$30530.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$30530.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$30530.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$30532.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$30530.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$30532.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$30532.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$30530.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
|
|
Optimizing lut $abc$30523$lut$aiger$o129.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
|
|
Removed 0 unused cells and 182 unused wires.
|
|
|
|
3.50. Executing AUTONAME pass.
|
|
Renamed 337 objects in module harness_neural_director.
|
|
<suppressed ~337 debug messages>
|
|
|
|
3.51. Executing HIERARCHY pass (managing design hierarchy).
|
|
Attribute `top' found on module `harness_neural_director'. Setting top module to harness_neural_director.
|
|
|
|
3.51.1. Analyzing design hierarchy..
|
|
Top module: \harness_neural_director
|
|
|
|
3.51.2. Analyzing design hierarchy..
|
|
Top module: \harness_neural_director
|
|
Removed 0 unused modules.
|
|
|
|
3.52. Printing statistics.
|
|
|
|
=== harness_neural_director ===
|
|
|
|
+----------Local Count, excluding submodules.
|
|
|
|
|
159 wires
|
|
1328 wire bits
|
|
159 public wires
|
|
1328 public wire bits
|
|
4 ports
|
|
18 port bits
|
|
1 cells
|
|
1 $scopeinfo
|
|
233 submodules
|
|
4 CCU2C
|
|
4 L6MUX21
|
|
107 LUT4
|
|
12 PFUMX
|
|
8 TRELLIS_DPR16X4
|
|
98 TRELLIS_FF
|
|
|
|
=== design hierarchy ===
|
|
|
|
+----------Count including submodules.
|
|
|
|
|
1 harness_neural_director
|
|
|
|
+----------Count including submodules.
|
|
|
|
|
159 wires
|
|
1328 wire bits
|
|
159 public wires
|
|
1328 public wire bits
|
|
4 ports
|
|
18 port bits
|
|
- memories
|
|
- memory bits
|
|
- processes
|
|
1 cells
|
|
1 $scopeinfo
|
|
233 submodules
|
|
4 CCU2C
|
|
4 L6MUX21
|
|
107 LUT4
|
|
12 PFUMX
|
|
8 TRELLIS_DPR16X4
|
|
98 TRELLIS_FF
|
|
|
|
3.53. Executing CHECK pass (checking for obvious problems).
|
|
Checking module harness_neural_director...
|
|
Found and reported 0 problems.
|
|
|
|
3.54. Executing JSON backend.
|
|
|
|
End of script. Logfile hash: f4bf1597d9, time: 0.54s, user: 0.53s, system: 0.02s, MEM: 66.97 MB peak
|
|
Yosys 0.68+post (git sha1 c12172fbae8af5e20f6fb52e3d4e92d56ed587b6, Release, AppleClang clang++ 21.0.0.21000101)
|
|
Time spent: 31% 23x read_verilog (0 sec), 10% 39x opt_expr (0 sec), ...
|