micheleandClaude Sonnet 5
3026dcd997
Implements M2 of the V2 roadmap: neural_processor_array.v instantiates
N_PROCESSORS independent neural_processor (M1) units, each with its
own dedicated point-to-point job/operand/result interface -- no shared
bus or mux at this level (arbitration is explicitly the Neural
Director's job, M5).
Verified with Verilator (tb_neural_processor_array.v, N_PROCESSORS=4):
7/7 tests pass, including a same-cycle 4-way concurrent launch with
different tile counts and a staggered-start test where a
later-launched, shorter job completes before an earlier-launched,
longer one -- confirming genuine independent concurrent execution
(§18/§34: a blocked/busy processor must not block the others).
Real resource/timing sweep for N_PROCESSORS in {1,2,4,8} (Yosys +
nextpnr-ecp5, real place&route): Fmax stays above the 80MHz target
throughout (159.11 -> 134.70 MHz), but MULT18X18D usage scales
linearly and reaches 88% of the LFE5U-45F's 72 DSPs at N=8 while
LUT/FF stay under 6% -- DSP, not LUT/FF/routing, is the first hard
ceiling on N_PROCESSORS at P_IN=8 (decisions.log DEC-0005). Measured
via a dedicated synthesis-only timing harness after the array's wide
per-processor buses were found to exhaust the device's TRELLIS_IO pin
budget as a bare top-level module beyond N=1 (errors.log ERR-0005) --
not a logic limit, an artifact of testing the array in isolation
before the Memory Manager/Director (M4/M5) exist to consume those
ports on-chip.
Full log trail (development/experiments/errors/decisions/simulation/
synthesis/timing/benchmark.log) in hardware/v2/logs/ per the project's
logging mandate.
Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
201 lines
10 KiB
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201 lines
10 KiB
Plaintext
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Info: Logic utilisation before packing:
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Info: Total LUT4s: 975/43848 2%
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Info: logic LUTs: 207/43848 0%
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Info: carry LUTs: 768/43848 1%
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Info: RAM LUTs: 0/ 5481 0%
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Info: RAMW LUTs: 0/10962 0%
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Info: Total DFFs: 1540/43848 3%
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Info: Packing IOs..
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Info: Packing constants..
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Info: Packing carries...
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Info: Packing LUTs...
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Info: Packing LUT5-7s...
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Info: Packing FFs...
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Info: 755 FFs paired with LUTs.
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Info: Generating derived timing constraints...
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Info: Promoting globals...
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Info: promoting clock net clk$TRELLIS_IO_IN to global network
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Info: Checksum: 0x560267d7
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Info: Device utilisation:
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Info: TRELLIS_IO: 18/ 245 7%
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Info: DCCA: 1/ 56 1%
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Info: DP16KD: 0/ 108 0%
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Info: MULT18X18D: 32/ 72 44%
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Info: ALU54B: 0/ 36 0%
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Info: EHXPLLL: 0/ 4 0%
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Info: EXTREFB: 0/ 2 0%
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Info: DCUA: 0/ 2 0%
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Info: PCSCLKDIV: 0/ 2 0%
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Info: IOLOGIC: 0/ 160 0%
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Info: SIOLOGIC: 0/ 85 0%
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Info: GSR: 0/ 1 0%
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Info: JTAGG: 0/ 1 0%
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Info: OSCG: 0/ 1 0%
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Info: SEDGA: 0/ 1 0%
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Info: DTR: 0/ 1 0%
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Info: USRMCLK: 0/ 1 0%
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Info: CLKDIVF: 0/ 4 0%
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Info: ECLKSYNCB: 0/ 10 0%
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Info: DLLDELD: 0/ 8 0%
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Info: DDRDLL: 0/ 4 0%
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Info: DQSBUFM: 0/ 10 0%
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Info: TRELLIS_ECLKBUF: 0/ 8 0%
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Info: ECLKBRIDGECS: 0/ 2 0%
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Info: DCSC: 0/ 2 0%
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Info: TRELLIS_FF: 1540/ 43848 3%
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Info: TRELLIS_COMB: 1121/ 43848 2%
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Info: TRELLIS_RAMW: 0/ 5481 0%
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Info: Placed 0 cells based on constraints.
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Info: Creating initial analytic placement for 1018 cells, random placement wirelen = 120985.
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Info: at initial placer iter 0, wirelen = 1796
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Info: at initial placer iter 1, wirelen = 1649
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Info: at initial placer iter 2, wirelen = 1698
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Info: at initial placer iter 3, wirelen = 1586
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Info: Running main analytical placer, max placement attempts per cell = 919368.
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Info: at iteration #1, type ALL: wirelen solved = 1546, spread = 31023, legal = 34537; time = 0.02s
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Info: at iteration #2, type ALL: wirelen solved = 1873, spread = 27635, legal = 31318; time = 0.02s
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Info: at iteration #3, type ALL: wirelen solved = 2361, spread = 26175, legal = 29501; time = 0.02s
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Info: at iteration #4, type ALL: wirelen solved = 2432, spread = 27276, legal = 30779; time = 0.02s
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Info: at iteration #5, type ALL: wirelen solved = 2485, spread = 28458, legal = 30586; time = 0.01s
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Info: at iteration #6, type ALL: wirelen solved = 2680, spread = 29235, legal = 32295; time = 0.02s
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Info: at iteration #7, type ALL: wirelen solved = 2809, spread = 29926, legal = 32990; time = 0.02s
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Info: at iteration #8, type ALL: wirelen solved = 2999, spread = 30221, legal = 32095; time = 0.01s
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Info: HeAP Placer Time: 0.22s
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Info: of which solving equations: 0.10s
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Info: of which spreading cells: 0.01s
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Info: of which strict legalisation: 0.06s
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Info: Running simulated annealing placer for refinement.
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Info: at iteration #1: temp = 0.000000, timing cost = 1110, wirelen = 29501
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Info: at iteration #5: temp = 0.000000, timing cost = 598, wirelen = 23863
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Info: at iteration #10: temp = 0.000000, timing cost = 442, wirelen = 20435
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Info: at iteration #15: temp = 0.000000, timing cost = 314, wirelen = 19582
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Info: at iteration #20: temp = 0.000000, timing cost = 211, wirelen = 18791
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Info: at iteration #25: temp = 0.000000, timing cost = 225, wirelen = 18367
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Info: at iteration #26: temp = 0.000000, timing cost = 244, wirelen = 18366
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Info: SA placement time 0.61s
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Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 120.63 MHz (PASS at 80.00 MHz)
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Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 11.00 ns
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Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 7.53 ns
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Info: Slack histogram:
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Info: legend: * represents 4 endpoint(s)
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Info: + represents [1,4) endpoint(s)
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Info: [ 4210, 4587) |+
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Info: [ 4587, 4964) |+
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Info: [ 4964, 5341) |***+
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Info: [ 5341, 5718) |***************************+
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Info: [ 5718, 6095) |*************************************+
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Info: [ 6095, 6472) |********************************+
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Info: [ 6472, 6849) |************+
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Info: [ 6849, 7226) |*****+
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Info: [ 7226, 7603) |****+
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Info: [ 7603, 7980) |********+
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Info: [ 7980, 8357) |***************+
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Info: [ 8357, 8734) |************+
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Info: [ 8734, 9111) |*******************+
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Info: [ 9111, 9488) |******************+
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Info: [ 9488, 9865) |*****************+
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Info: [ 9865, 10242) |**************************************************+
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Info: [ 10242, 10619) |************************************************************
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Info: [ 10619, 10996) |***************************+
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Info: [ 10996, 11373) |***************************+
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Info: [ 11373, 11750) |******************+
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Info: Checksum: 0xa617f308
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Info: Routing globals...
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Info: routing clock net $glbnet$clk$TRELLIS_IO_IN using global 0
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Info: Routing..
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Info: Setting up routing queue.
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Info: Routing 6674 arcs.
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Info: | (re-)routed arcs | delta | remaining| time spent |
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Info: IterCnt | w/ripup wo/ripup | w/r wo/r | arcs| batch(sec) total(sec)|
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Info: 1000 | 373 626 | 373 626 | 6229| 0.41 0.41|
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Info: 2000 | 577 1422 | 204 796 | 5542| 0.68 1.09|
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Info: 3000 | 761 2238 | 184 816 | 4800| 0.34 1.43|
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Info: 4000 | 1201 2798 | 440 560 | 4327| 0.28 1.71|
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Info: 5000 | 1272 3658 | 71 860 | 3465| 0.14 1.85|
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Info: 6000 | 1354 4460 | 82 802 | 2552| 0.09 1.93|
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Info: 7000 | 1432 5185 | 78 725 | 1634| 0.09 2.02|
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Info: 8000 | 1489 6074 | 57 889 | 700| 0.10 2.12|
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Info: 8706 | 1496 6719 | 7 645 | 0| 0.07 2.19|
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Info: Routing complete.
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Info: Router1 time 2.19s
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Info: Checksum: 0x9b8ba237
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Info: Critical path report for clock '$glbnet$clk$TRELLIS_IO_IN' (posedge -> posedge):
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Info: type curr total name
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Info: clk-to-q 0.40 0.40 Source dut.GEN_NP[0].u_np.w0[7]_TRELLIS_FF_Q.Q
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Info: routing 2.11 2.50 Net dut.GEN_NP[0].u_np.w0[6][7] (63,23) -> (27,22)
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Info: Sink dut.GEN_NP[0].u_np.product_comb[7]_MULT18X18D_P9.B6
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Info: Defined in:
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Info: hardware/v2/rtl/neural_processor.v:100.44-100.46
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Info: logic 3.07 5.57 Source dut.GEN_NP[0].u_np.product_comb[7]_MULT18X18D_P9.P9
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Info: routing 1.06 6.62 Net dut.GEN_NP[0].u_np.product_comb[7][9] (27,22) -> (27,21)
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Info: Sink dut.GEN_NP[0].u_np.prod1[7]_TRELLIS_FF_Q_9.M
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Info: Defined in:
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Info: hardware/v2/rtl/neural_processor.v:135.34-135.46
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Info: setup 0.00 6.62 Source dut.GEN_NP[0].u_np.prod1[7]_TRELLIS_FF_Q_9.M
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Info: 3.46 ns logic, 3.16 ns routing
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Info: Critical path report for cross-domain path '<async>' -> 'posedge $glbnet$clk$TRELLIS_IO_IN':
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Info: type curr total name
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Info: source 0.00 0.00 Source rst$tr_io.O
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Info: routing 6.36 6.36 Net rst$TRELLIS_IO_IN (15,71) -> (85,14)
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Info: Sink dut.GEN_NP[1].u_np.acc_reg_TRELLIS_FF_Q_LSR_LUT4_Z.A
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Info: Defined in:
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Info: hardware/v2/synthesis/harness_neural_processor_array.v:30.12-30.15
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Info: logic 0.18 6.54 Source dut.GEN_NP[1].u_np.acc_reg_TRELLIS_FF_Q_LSR_LUT4_Z.F
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Info: routing 0.68 7.22 Net dut.GEN_NP[1].u_np.acc_reg_TRELLIS_FF_Q_LSR (85,14) -> (87,15)
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Info: Sink dut.GEN_NP[1].u_np.acc_reg_TRELLIS_FF_Q_4.LSR
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Info: setup 0.29 7.50 Source dut.GEN_NP[1].u_np.acc_reg_TRELLIS_FF_Q_4.LSR
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Info: 0.47 ns logic, 7.04 ns routing
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Info: Critical path report for cross-domain path 'posedge $glbnet$clk$TRELLIS_IO_IN' -> '<async>':
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Info: type curr total name
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Info: clk-to-q 0.40 0.40 Source chk_TRELLIS_FF_Q_2.Q
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Info: routing 4.69 5.09 Net checksum[2]$TRELLIS_IO_OUT (75,29) -> (18,71)
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Info: Sink checksum[2]$tr_io.I
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Info: Defined in:
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Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
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Info: 0.40 ns logic, 4.69 ns routing
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Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 151.01 MHz (PASS at 80.00 MHz)
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Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 7.50 ns
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Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 5.09 ns
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Info: Slack histogram:
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Info: legend: * represents 4 endpoint(s)
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Info: + represents [1,4) endpoint(s)
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Info: [ 5878, 6174) |***************+
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Info: [ 6174, 6470) |**************************************+
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Info: [ 6470, 6766) |************************************+
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Info: [ 6766, 7062) |**********+
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Info: [ 7062, 7358) |*****+
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Info: [ 7358, 7654) |+
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Info: [ 7654, 7950) |+
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Info: [ 7950, 8246) |***************+
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Info: [ 8246, 8542) |**************+
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Info: [ 8542, 8838) |****************+
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Info: [ 8838, 9134) |*********************+
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Info: [ 9134, 9430) |*********************+
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Info: [ 9430, 9726) |*********************+
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Info: [ 9726, 10022) |************************************************************
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Info: [ 10022, 10318) |*********************************************+
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Info: [ 10318, 10614) |***************+
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Info: [ 10614, 10910) |***********+
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Info: [ 10910, 11206) |************************+
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Info: [ 11206, 11502) |********************+
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Info: [ 11502, 11798) |*************+
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Info: Program finished normally.
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