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FPGA-Neural/hardware/v2/synthesis/harness_memory_manager/top.config
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micheleandClaude Sonnet 5 175f697ae1 feat(v2): M4 Memory Manager + Prefetch Engine, real V1 PSRAM backend 
Implements M4: memory_manager.v (arbitration/buffering/forwarding/
latency hiding/double buffering, §12) + prefetch_engine.v
(double-buffered tile fetch, §13), sitting on the REAL, UNMODIFIED V1
PSRAM backend chain (int8_memory_access.v -> memory_interface.v ->
psram_controller.v, per §15's explicit mandate not to touch the
controller).

Verified fully end-to-end with Verilator: real neural_processor (M1)
fed entirely by memory_manager, computing against PSRAM-resident X/W
tiles (double-buffered prefetch across up to 5 tiles) and writing its
result back to PSRAM -- checked via an independent PSRAM read-back,
with poison bytes around the operand regions to catch addressing
errors. 3/3 jobs pass (1/3/5-tile configurations).

Three real RTL bugs found and fixed during integration (full
diagnostic trail in errors.log ERR-0006): prefetch_engine had no
single-in-flight-request discipline, letting a queued request corrupt
the bank bookkeeping of a fetch already running; the fix's own
!pf_busy guard had a one-cycle blind spot (pf_busy lags pf_start by a
clock) that needed an explicit !pf_start term; and a state-based mux
for the shared backend port was off by one cycle, silently dropping
the PSRAM result write entirely.

Real synthesis: 0 CHECK problems, 851 LUT4/789 FF/108 CCU2C/0 DSP
(expected, no multiplication in this module). Real place&route (via a
synthesis-only timing harness, needed for the same TRELLIS_IO pin-
budget reason as M2's array): Fmax 165.86 MHz, PASS at 80MHz.

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
2026-09-05 14:39:29 +02:00

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.device LFE5U-45F
.comment Part: LFE5U-45F-8CABGA381
.tile CIB_R10C13:CIB_EBR
arc: E3_H06E0103 W3_H06E0003
arc: E3_H06E0303 W3_H06E0303
.tile CIB_R10C19:CIB_EBR
arc: E3_H06E0003 W3_H06E0303
arc: E3_H06E0203 W3_H06E0103
.tile CIB_R10C1:CIB_LR_S
arc: E3_H06E0003 V01N0001
arc: E3_H06E0303 S3_V06N0303
.tile CIB_R10C25:CIB_EBR
arc: E3_H06E0103 W3_H06E0003
arc: E3_H06E0203 W3_H06E0203
.tile CIB_R10C30:CIB_EBR
arc: N1_V02N0401 E1_H01W0000
.tile CIB_R10C31:CIB_EBR
arc: E3_H06E0303 W3_H06E0203
arc: H01W0000 W3_H06E0103
.tile CIB_R10C33:CIB_EBR
arc: N1_V02N0401 N1_V01S0000
arc: N1_V02N0601 E1_H02W0601
.tile CIB_R10C35:CIB_EBR
arc: N1_V02N0601 E1_H02W0601
arc: W1_H02W0601 V02N0601
.tile CIB_R10C37:CIB_EBR
arc: W1_H02W0601 W3_H06E0303
.tile CIB_R10C3:PVT_COUNT2
unknown: F2B0
unknown: F3B0
unknown: F5B0
unknown: F11B0
unknown: F13B0
.tile CIB_R10C7:CIB_EBR
arc: E3_H06E0003 W3_H06E0003
arc: E3_H06E0303 W3_H06E0303
.tile CIB_R11C1:CIB_LR
arc: E3_H06E0303 JQ5
arc: N1_V01N0001 JF5
arc: S1_V02S0501 E1_H02W0501
arc: S1_V02S0701 N1_V02S0601
.tile CIB_R11C89:CIB_LR
arc: S1_V02S0701 N1_V02S0601
arc: W3_H06W0303 JQ5
.tile CIB_R13C1:CIB_LR
arc: JA0 N1_V02S0701
arc: JA3 N1_V02S0501
enum: CIB.JB3MUX 0
enum: CIB.JB0MUX 0
.tile CIB_R13C89:CIB_LR
arc: JA0 N1_V02S0701
enum: CIB.JB0MUX 0
.tile CIB_R14C1:CIB_LR
arc: N3_V06N0303 JF5
arc: S1_V02S0701 E1_H02W0701
.tile CIB_R16C1:CIB_LR
arc: JA0 N1_V02S0701
arc: N3_V06N0303 JQ5
enum: CIB.JB0MUX 0
.tile CIB_R1C31:CIB
arc: JA0 V02N0701
enum: CIB.JB0MUX 0
.tile CIB_R1C32:CIB
arc: S3_V06S0003 E3_H06W0003
.tile CIB_R1C33:CIB
arc: V01S0000 S3_V06N0103
.tile CIB_R1C34:CIB
arc: S1_V02S0201 H06W0103
arc: S3_V06S0103 H06W0103
.tile CIB_R1C36:CIB
arc: E1_H02E0001 S3_V06N0003
arc: S1_V02S0301 S3_V06N0003
.tile CIB_R1C37:CIB
arc: E3_H06E0303 S3_V06N0303
arc: JA0 V01N0101
arc: S1_V02S0301 E1_H01W0100
arc: S1_V02S0701 E1_H01W0100
arc: S3_V06S0103 E1_H01W0100
arc: W3_H06W0103 E1_H01W0100
enum: CIB.JB0MUX 0
.tile CIB_R1C38:CIB
arc: E1_H02E0401 E3_H06W0203
arc: H01W0100 JQ0
arc: S1_V02S0001 W1_H02E0001
arc: V01S0000 S3_V06N0103
arc: W3_H06W0003 JQ0
.tile CIB_R1C39:CIB
arc: S1_V02S0001 H06W0003
arc: S1_V02S0601 H06W0303
.tile CIB_R1C40:CIB
arc: S1_V02S0401 W1_H02E0401
.tile CIB_R1C42:CIB
arc: W3_H06W0003 JQ0
arc: W3_H06W0303 E1_H01W0100
.tile CIB_R1C43:CIB
arc: E3_H06E0303 W3_H06E0303
arc: H01W0100 JQ0
.tile CIB_R1C44:CIB
arc: H00L0000 V02N0201
arc: JA0 H00L0000
arc: W3_H06W0203 E1_H01W0000
enum: CIB.JB0MUX 0
.tile CIB_R1C45:CIB
arc: H01W0000 JQ0
.tile CIB_R1C46:CIB
arc: E1_H02E0701 V02N0701
.tile CIB_R1C48:CIB
arc: JA0 W1_H02E0701
arc: JD7 E1_H01W0100
enum: CIB.JB0MUX 0
.tile CIB_R1C49:CIB
arc: H01W0100 W3_H06E0303
.tile CIB_R5C1:CIB_PLL1
enum: CIB.JA3MUX 0
enum: CIB.JB3MUX 0
.tile CIB_R5C89:CIB_PLL1
enum: CIB.JA3MUX 0
enum: CIB.JB3MUX 0
.tile CIB_R70C3:CIB_PLL3
enum: CIB.JA3MUX 0
enum: CIB.JB3MUX 0
.tile CIB_R70C42:VCIB_DCU0
enum: CIB.JA1MUX 0
enum: CIB.JA3MUX 0
enum: CIB.JA5MUX 0
enum: CIB.JA7MUX 0
enum: CIB.JB1MUX 0
enum: CIB.JB3MUX 0
enum: CIB.JB5MUX 0
enum: CIB.JB7MUX 0
enum: CIB.JC0MUX 0
enum: CIB.JC2MUX 0
enum: CIB.JC4MUX 0
enum: CIB.JC6MUX 0
enum: CIB.JD0MUX 0
enum: CIB.JD2MUX 0
enum: CIB.JD4MUX 0
enum: CIB.JD6MUX 0
.tile CIB_R70C43:VCIB_DCUA
enum: CIB.JA1MUX 0
enum: CIB.JA3MUX 0
enum: CIB.JA5MUX 0
enum: CIB.JA7MUX 0
enum: CIB.JB1MUX 0
enum: CIB.JB3MUX 0
enum: CIB.JB5MUX 0
enum: CIB.JB7MUX 0
enum: CIB.JC0MUX 0
enum: CIB.JC2MUX 0
enum: CIB.JC4MUX 0
enum: CIB.JC6MUX 0
enum: CIB.JD0MUX 0
enum: CIB.JD2MUX 0
enum: CIB.JD4MUX 0
enum: CIB.JD6MUX 0
.tile CIB_R70C44:VCIB_DCUB
enum: CIB.JA1MUX 0
enum: CIB.JA3MUX 0
enum: CIB.JA5MUX 0
enum: CIB.JA7MUX 0
enum: CIB.JB1MUX 0
enum: CIB.JB3MUX 0
enum: CIB.JB5MUX 0
enum: CIB.JB7MUX 0
enum: CIB.JC0MUX 0
enum: CIB.JC2MUX 0
enum: CIB.JC4MUX 0
enum: CIB.JC6MUX 0
enum: CIB.JD0MUX 0
enum: CIB.JD2MUX 0
enum: CIB.JD4MUX 0
enum: CIB.JD6MUX 0
.tile CIB_R70C45:VCIB_DCUC
enum: CIB.JA1MUX 0
enum: CIB.JA3MUX 0
enum: CIB.JA5MUX 0
enum: CIB.JA7MUX 0
enum: CIB.JB1MUX 0
enum: CIB.JB3MUX 0
enum: CIB.JB5MUX 0
enum: CIB.JB7MUX 0
enum: CIB.JC0MUX 0
enum: CIB.JC2MUX 0
enum: CIB.JC4MUX 0
enum: CIB.JC6MUX 0
enum: CIB.JD0MUX 0
enum: CIB.JD2MUX 0
enum: CIB.JD4MUX 0
enum: CIB.JD6MUX 0
.tile CIB_R70C46:VCIB_DCUD
enum: CIB.JA1MUX 0
enum: CIB.JA5MUX 0
enum: CIB.JA7MUX 0
enum: CIB.JB1MUX 0
enum: CIB.JB3MUX 0
enum: CIB.JB5MUX 0
enum: CIB.JB7MUX 0
enum: CIB.JC0MUX 0
enum: CIB.JC2MUX 0
enum: CIB.JC4MUX 0
enum: CIB.JC6MUX 0
enum: CIB.JD0MUX 0
enum: CIB.JD2MUX 0
enum: CIB.JD4MUX 0
enum: CIB.JD6MUX 0
.tile CIB_R70C47:VCIB_DCUF
enum: CIB.JA1MUX 0
enum: CIB.JA3MUX 0
enum: CIB.JA5MUX 0
enum: CIB.JA7MUX 0
enum: CIB.JB1MUX 0
enum: CIB.JB3MUX 0
enum: CIB.JB5MUX 0
enum: CIB.JB7MUX 0
enum: CIB.JC0MUX 0
enum: CIB.JC2MUX 0
enum: CIB.JC4MUX 0
enum: CIB.JC6MUX 0
enum: CIB.JD0MUX 0
enum: CIB.JD2MUX 0
enum: CIB.JD4MUX 0
enum: CIB.JD6MUX 0
.tile CIB_R70C48:VCIB_DCU3
enum: CIB.JA5MUX 0
enum: CIB.JA7MUX 0
enum: CIB.JB1MUX 0
enum: CIB.JB3MUX 0
enum: CIB.JB5MUX 0
enum: CIB.JB7MUX 0
enum: CIB.JC0MUX 0
enum: CIB.JC4MUX 0
enum: CIB.JC6MUX 0
enum: CIB.JD0MUX 0
enum: CIB.JD2MUX 0
enum: CIB.JD4MUX 0
enum: CIB.JD6MUX 0
.tile CIB_R70C49:VCIB_DCU2
enum: CIB.JB1MUX 0
enum: CIB.JB3MUX 0
enum: CIB.JB5MUX 0
enum: CIB.JB7MUX 0
enum: CIB.JD0MUX 0
enum: CIB.JD2MUX 0
enum: CIB.JD4MUX 0
enum: CIB.JD6MUX 0
.tile CIB_R70C50:VCIB_DCUG
enum: CIB.JB1MUX 0
enum: CIB.JB3MUX 0
enum: CIB.JB5MUX 0
enum: CIB.JB7MUX 0
enum: CIB.JD0MUX 0
enum: CIB.JD2MUX 0
enum: CIB.JD4MUX 0
enum: CIB.JD6MUX 0
.tile CIB_R70C51:VCIB_DCUH
enum: CIB.JB1MUX 0
enum: CIB.JB3MUX 0
enum: CIB.JB5MUX 0
enum: CIB.JB7MUX 0
enum: CIB.JD0MUX 0
enum: CIB.JD2MUX 0
enum: CIB.JD4MUX 0
enum: CIB.JD6MUX 0
.tile CIB_R70C52:VCIB_DCUI
enum: CIB.JB1MUX 0
enum: CIB.JB3MUX 0
enum: CIB.JB5MUX 0
enum: CIB.JB7MUX 0
enum: CIB.JD0MUX 0
enum: CIB.JD2MUX 0
enum: CIB.JD4MUX 0
enum: CIB.JD6MUX 0
.tile CIB_R70C53:VCIB_DCU1
enum: CIB.JB1MUX 0
enum: CIB.JB3MUX 0
enum: CIB.JB5MUX 0
enum: CIB.JD0MUX 0
enum: CIB.JD2MUX 0
.tile CIB_R70C69:VCIB_DCU0
enum: CIB.JA1MUX 0
enum: CIB.JA3MUX 0
enum: CIB.JA5MUX 0
enum: CIB.JA7MUX 0
enum: CIB.JB1MUX 0
enum: CIB.JB3MUX 0
enum: CIB.JB5MUX 0
enum: CIB.JB7MUX 0
enum: CIB.JC0MUX 0
enum: CIB.JC2MUX 0
enum: CIB.JC4MUX 0
enum: CIB.JC6MUX 0
enum: CIB.JD0MUX 0
enum: CIB.JD2MUX 0
enum: CIB.JD4MUX 0
enum: CIB.JD6MUX 0
.tile CIB_R70C6:CIB_EFB0
enum: CIB.JB3MUX 0
enum: CIB.JC6MUX 0
enum: CIB.JD6MUX 0
.tile CIB_R70C70:VCIB_DCUA
enum: CIB.JA1MUX 0
enum: CIB.JA3MUX 0
enum: CIB.JA5MUX 0
enum: CIB.JA7MUX 0
enum: CIB.JB1MUX 0
enum: CIB.JB3MUX 0
enum: CIB.JB5MUX 0
enum: CIB.JB7MUX 0
enum: CIB.JC0MUX 0
enum: CIB.JC2MUX 0
enum: CIB.JC4MUX 0
enum: CIB.JC6MUX 0
enum: CIB.JD0MUX 0
enum: CIB.JD2MUX 0
enum: CIB.JD4MUX 0
enum: CIB.JD6MUX 0
.tile CIB_R70C71:VCIB_DCUB
enum: CIB.JA1MUX 0
enum: CIB.JA3MUX 0
enum: CIB.JA5MUX 0
enum: CIB.JA7MUX 0
enum: CIB.JB1MUX 0
enum: CIB.JB3MUX 0
enum: CIB.JB5MUX 0
enum: CIB.JB7MUX 0
enum: CIB.JC0MUX 0
enum: CIB.JC2MUX 0
enum: CIB.JC4MUX 0
enum: CIB.JC6MUX 0
enum: CIB.JD0MUX 0
enum: CIB.JD2MUX 0
enum: CIB.JD4MUX 0
enum: CIB.JD6MUX 0
.tile CIB_R70C72:VCIB_DCUC
enum: CIB.JA1MUX 0
enum: CIB.JA3MUX 0
enum: CIB.JA5MUX 0
enum: CIB.JA7MUX 0
enum: CIB.JB1MUX 0
enum: CIB.JB3MUX 0
enum: CIB.JB5MUX 0
enum: CIB.JB7MUX 0
enum: CIB.JC0MUX 0
enum: CIB.JC2MUX 0
enum: CIB.JC4MUX 0
enum: CIB.JC6MUX 0
enum: CIB.JD0MUX 0
enum: CIB.JD2MUX 0
enum: CIB.JD4MUX 0
enum: CIB.JD6MUX 0
.tile CIB_R70C73:VCIB_DCUD
enum: CIB.JA1MUX 0
enum: CIB.JA5MUX 0
enum: CIB.JA7MUX 0
enum: CIB.JB1MUX 0
enum: CIB.JB3MUX 0
enum: CIB.JB5MUX 0
enum: CIB.JB7MUX 0
enum: CIB.JC0MUX 0
enum: CIB.JC2MUX 0
enum: CIB.JC4MUX 0
enum: CIB.JC6MUX 0
enum: CIB.JD0MUX 0
enum: CIB.JD2MUX 0
enum: CIB.JD4MUX 0
enum: CIB.JD6MUX 0
.tile CIB_R70C74:VCIB_DCUF
enum: CIB.JA1MUX 0
enum: CIB.JA3MUX 0
enum: CIB.JA5MUX 0
enum: CIB.JA7MUX 0
enum: CIB.JB1MUX 0
enum: CIB.JB3MUX 0
enum: CIB.JB5MUX 0
enum: CIB.JB7MUX 0
enum: CIB.JC0MUX 0
enum: CIB.JC2MUX 0
enum: CIB.JC4MUX 0
enum: CIB.JC6MUX 0
enum: CIB.JD0MUX 0
enum: CIB.JD2MUX 0
enum: CIB.JD4MUX 0
enum: CIB.JD6MUX 0
.tile CIB_R70C75:VCIB_DCU3
enum: CIB.JA5MUX 0
enum: CIB.JA7MUX 0
enum: CIB.JB1MUX 0
enum: CIB.JB3MUX 0
enum: CIB.JB5MUX 0
enum: CIB.JB7MUX 0
enum: CIB.JC0MUX 0
enum: CIB.JC4MUX 0
enum: CIB.JC6MUX 0
enum: CIB.JD0MUX 0
enum: CIB.JD2MUX 0
enum: CIB.JD4MUX 0
enum: CIB.JD6MUX 0
.tile CIB_R70C76:VCIB_DCU2
enum: CIB.JB1MUX 0
enum: CIB.JB3MUX 0
enum: CIB.JB5MUX 0
enum: CIB.JB7MUX 0
enum: CIB.JD0MUX 0
enum: CIB.JD2MUX 0
enum: CIB.JD4MUX 0
enum: CIB.JD6MUX 0
.tile CIB_R70C77:VCIB_DCUG
enum: CIB.JB1MUX 0
enum: CIB.JB3MUX 0
enum: CIB.JB5MUX 0
enum: CIB.JB7MUX 0
enum: CIB.JD0MUX 0
enum: CIB.JD2MUX 0
enum: CIB.JD4MUX 0
enum: CIB.JD6MUX 0
.tile CIB_R70C78:VCIB_DCUH
enum: CIB.JB1MUX 0
enum: CIB.JB3MUX 0
enum: CIB.JB5MUX 0
enum: CIB.JB7MUX 0
enum: CIB.JD0MUX 0
enum: CIB.JD2MUX 0
enum: CIB.JD4MUX 0
enum: CIB.JD6MUX 0
.tile CIB_R70C79:VCIB_DCUI
enum: CIB.JB1MUX 0
enum: CIB.JB3MUX 0
enum: CIB.JB5MUX 0
enum: CIB.JB7MUX 0
enum: CIB.JD0MUX 0
enum: CIB.JD2MUX 0
enum: CIB.JD4MUX 0
enum: CIB.JD6MUX 0
.tile CIB_R70C7:CIB_EFB1
enum: CIB.JA3MUX 0
enum: CIB.JA4MUX 0
enum: CIB.JA5MUX 0
enum: CIB.JA6MUX 0
enum: CIB.JB3MUX 0
enum: CIB.JB4MUX 0
enum: CIB.JB5MUX 0
enum: CIB.JB6MUX 0
enum: CIB.JC3MUX 0
enum: CIB.JC4MUX 0
enum: CIB.JC5MUX 0
enum: CIB.JD3MUX 0
enum: CIB.JD4MUX 0
enum: CIB.JD5MUX 0
.tile CIB_R70C80:VCIB_DCU1
enum: CIB.JB1MUX 0
enum: CIB.JB3MUX 0
enum: CIB.JB5MUX 0
enum: CIB.JD0MUX 0
enum: CIB.JD2MUX 0
.tile CIB_R70C87:CIB_PLL3
enum: CIB.JA3MUX 0
enum: CIB.JB3MUX 0
.tile CIB_R8C1:CIB_LR
arc: E3_H06E0303 S3_V06N0303
.tile CIB_R9C1:CIB_LR
arc: S1_V02S0601 E3_H06W0303
.tile CIB_R9C89:CIB_LR
arc: S1_V02S0601 H06E0303
.tile MIB_R0C31:PIOT0
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
.tile MIB_R0C37:PIOT1
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
.tile MIB_R0C38:PIOT0
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
enum: PIOA.HYSTERESIS ON
.tile MIB_R0C3:BANKREF0
enum: BANK.VCCIO 3V3
.tile MIB_R0C40:TMID_0
arc: G_TDCC0CLKI G_JTRQPCLKCIB1
.tile MIB_R0C42:PIOT0
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
enum: PIOA.HYSTERESIS ON
.tile MIB_R0C43:PIOT1
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
enum: PIOB.HYSTERESIS ON
.tile MIB_R0C44:PIOT0
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
.tile MIB_R0C45:PIOT1
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
enum: PIOB.HYSTERESIS ON
.tile MIB_R0C48:PIOT1
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
.tile MIB_R0C87:BANKREF1
enum: BANK.VCCIO 3V3
.tile MIB_R10C0:BANKREF7
enum: BANK.VCCIO 3V3
.tile MIB_R10C30:EBR_SPINE_UL0
arc: G_VPTX0000 G_HPRX0000
.tile MIB_R10C40:CMUX_UL_0
arc: G_DCS0CLK0 G_VPFN0000
arc: G_ULPCLK0 G_VPFS0000
.tile MIB_R10C41:CMUX_UR_0
arc: G_DCS0CLK1 G_VPFN0000
arc: G_URPCLK0 G_VPFS0000
.tile MIB_R10C90:BANKREF2
enum: BANK.VCCIO 3V3
.tile MIB_R11C0:PICL0
arc: JDIA JPADDIA_PIO
arc: JDIB JPADDIB_PIO
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
.tile MIB_R11C90:PICR0
arc: JDIB JPADDIB_PIO
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
.tile MIB_R12C0:PICL1
enum: PIOD.BASE_TYPE OUTPUT_LVCMOS33
enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
enum: PIOA.HYSTERESIS ON
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
enum: PIOB.HYSTERESIS ON
.tile MIB_R12C90:PICR1
enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
enum: PIOB.HYSTERESIS ON
.tile MIB_R13C0:PICL2
enum: PIOD.BASE_TYPE OUTPUT_LVCMOS33
enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33
.tile MIB_R13C90:PICR2
enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33
.tile MIB_R14C0:PICL0
arc: JDIA JPADDIA_PIO
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
.tile MIB_R15C0:PICL1_DQS0
enum: PIOD.BASE_TYPE INPUT_LVCMOS33
enum: PIOD.HYSTERESIS ON
enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
enum: PIOA.HYSTERESIS ON
.tile MIB_R16C0:PICL2_DQS1
enum: PIOD.BASE_TYPE INPUT_LVCMOS33
enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33
.tile MIB_R1C31:PICT0
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
.tile MIB_R1C37:PICT1
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
.tile MIB_R1C38:PICT0
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
.tile MIB_R1C42:PICT0
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
.tile MIB_R1C43:PICT1
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
.tile MIB_R1C44:PICT0
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
.tile MIB_R1C45:PICT1
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
.tile MIB_R1C48:PICT1
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
.tile MIB_R58C40:CMUX_LL_0
arc: G_DCS1CLK0 G_VPFN0000
arc: G_LLPCLK0 G_VPFS0000
.tile MIB_R58C41:CMUX_LR_0
arc: G_DCS1CLK1 G_VPFN0000
arc: G_LRPCLK0 G_VPFS0000
.tile MIB_R71C4:EFB0_PICB0
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
enum: PIOA.HYSTERESIS ON
unknown: F54B1
unknown: F56B1
unknown: F82B1
unknown: F94B1
.tile R11C13:PLC2
arc: E3_H06E0303 W3_H06E0303
.tile R11C19:PLC2
arc: E3_H06E0003 W3_H06E0303
.tile R11C25:PLC2
arc: E3_H06E0103 W3_H06E0003
.tile R11C31:PLC2
arc: E3_H06E0203 W3_H06E0103
.tile R11C35:PLC2
arc: N1_V02N0601 E1_H02W0601
.tile R11C37:PLC2
arc: E1_H02E0601 N3_V06S0303
arc: N1_V02N0401 W3_H06E0203
arc: N1_V02N0701 N3_V06S0203
arc: W1_H02W0601 N3_V06S0303
.tile R11C38:PLC2
arc: N1_V02N0601 H02E0601
.tile R11C3:PLC2
arc: W1_H02W0501 V06S0303
.tile R11C41:PLC2
arc: N1_V02N0601 E3_H06W0303
.tile R11C47:PLC2
arc: W3_H06W0303 E3_H06W0303
.tile R11C53:PLC2
arc: W3_H06W0303 E3_H06W0203
.tile R11C59:PLC2
arc: W3_H06W0203 E3_H06W0103
.tile R11C65:PLC2
arc: W3_H06W0103 E3_H06W0003
.tile R11C71:PLC2
arc: W3_H06W0003 E3_H06W0303
.tile R11C77:PLC2
arc: W3_H06W0303 E3_H06W0303
.tile R11C7:PLC2
arc: E3_H06E0303 W3_H06E0303
.tile R11C83:PLC2
arc: W3_H06W0303 E3_H06W0303
.tile R14C3:PLC2
arc: W1_H02W0701 N3_V06S0203
.tile R2C30:PLC2
arc: E1_H02E0001 V06N0003
arc: E1_H02E0501 E3_H06W0303
arc: S3_V06S0303 E3_H06W0303
.tile R2C31:PLC2
arc: E1_H02E0101 V06N0103
arc: N1_V02N0701 S1_V02N0601
arc: A0 H02W0701
arc: A1 H02W0701
arc: B0 E1_H02W0101
arc: B1 E1_H02W0101
arc: C0 E1_H02W0401
arc: C1 E1_H02W0401
arc: D0 H02E0001
arc: D1 H02E0001
arc: F0 F5A_SLICE
arc: M0 E1_H02W0601
arc: S1_V02S0001 F0
word: SLICEA.K0.INIT 1100101000000000
word: SLICEA.K1.INIT 1100101011111111
enum: SLICEA.MODE LOGIC
enum: SLICEA.CCU2.INJECT1_0 _NONE_
enum: SLICEA.MODE LOGIC
enum: SLICEA.CCU2.INJECT1_1 _NONE_
.tile R2C32:PLC2
arc: E1_H02E0101 V06N0103
arc: E3_H06E0303 S3_V06N0303
arc: V00T0000 V02N0401
arc: W1_H02W0701 E1_H02W0601
arc: A0 W1_H02E0501
arc: A3 V01N0101
arc: A5 V02N0301
arc: B2 V01N0001
arc: B4 H02E0101
arc: B6 V00T0000
arc: B7 S1_V02N0701
arc: E1_H01E0001 F3
arc: E1_H01E0101 F6
arc: E1_H02E0401 F4
arc: E1_H02E0501 F5
arc: E1_H02E0701 F7
arc: F3 F3_SLICE
arc: F4 F4_SLICE
arc: F5 F5_SLICE
arc: F6 F6_SLICE
arc: F7 F7_SLICE
arc: S1_V02S0301 F3
arc: S1_V02S0501 F5
arc: V01S0100 F4
word: SLICED.K0.INIT 1100110011000000
word: SLICED.K1.INIT 1100110011000000
word: SLICEA.K0.INIT 0000000000001010
word: SLICEA.K1.INIT 1111111111111111
word: SLICEB.K0.INIT 0110011001101010
word: SLICEB.K1.INIT 1010101010100000
word: SLICEC.K0.INIT 1100110011000000
word: SLICEC.K1.INIT 1010101010100000
enum: SLICED.MODE CCU2
enum: SLICED.CCU2.INJECT1_0 NO
enum: SLICED.A0MUX 1
enum: SLICED.C0MUX 1
enum: SLICED.D0MUX 1
enum: SLICED.MODE CCU2
enum: SLICED.CCU2.INJECT1_1 NO
enum: SLICED.A1MUX 1
enum: SLICED.C1MUX 1
enum: SLICED.D1MUX 1
enum: SLICEA.MODE CCU2
enum: SLICEA.CCU2.INJECT1_0 NO
enum: SLICEA.B0MUX 1
enum: SLICEA.C0MUX 1
enum: SLICEA.D0MUX 1
enum: SLICEA.MODE CCU2
enum: SLICEA.CCU2.INJECT1_1 YES
enum: SLICEA.A1MUX 1
enum: SLICEA.B1MUX 1
enum: SLICEA.C1MUX 1
enum: SLICEA.D1MUX 1
enum: SLICEB.MODE CCU2
enum: SLICEB.CCU2.INJECT1_0 NO
enum: SLICEB.A0MUX 1
enum: SLICEB.C0MUX 1
enum: SLICEB.D0MUX 1
enum: SLICEB.MODE CCU2
enum: SLICEB.CCU2.INJECT1_1 NO
enum: SLICEB.B1MUX 1
enum: SLICEB.C1MUX 1
enum: SLICEB.D1MUX 1
enum: SLICEC.MODE CCU2
enum: SLICEC.CCU2.INJECT1_0 NO
enum: SLICEC.A0MUX 1
enum: SLICEC.C0MUX 1
enum: SLICEC.D0MUX 1
enum: SLICEC.MODE CCU2
enum: SLICEC.CCU2.INJECT1_1 NO
enum: SLICEC.B1MUX 1
enum: SLICEC.C1MUX 1
enum: SLICEC.D1MUX 1
.tile R2C33:PLC2
arc: E1_H02E0001 N1_V01S0000
arc: E1_H02E0601 H01E0001
arc: S1_V02S0001 E3_H06W0003
arc: S1_V02S0101 H01E0101
arc: S3_V06S0003 E3_H06W0003
arc: V00B0000 S1_V02N0001
arc: W1_H02W0101 E1_H01W0100
arc: W1_H02W0401 E1_H02W0401
arc: W1_H02W0601 E1_H01W0000
arc: A0 H02W0501
arc: A1 S1_V02N0501
arc: A2 H02W0701
arc: A4 V00B0000
arc: B3 S1_V02N0101
arc: B5 V02N0701
arc: B6 H02W0101
arc: B7 H02E0101
arc: E1_H01E0001 F4
arc: E1_H01E0101 F0
arc: E1_H02E0101 F1
arc: E1_H02E0701 F7
arc: F0 F0_SLICE
arc: F1 F1_SLICE
arc: F2 F2_SLICE
arc: F3 F3_SLICE
arc: F4 F4_SLICE
arc: F5 F5_SLICE
arc: F6 F6_SLICE
arc: F7 F7_SLICE
arc: S1_V02S0301 F3
arc: S1_V02S0501 F5
arc: V01S0000 F6
arc: V01S0100 F2
word: SLICEA.K0.INIT 1010101010100000
word: SLICEA.K1.INIT 1010101010100000
word: SLICEB.K0.INIT 1010101010100000
word: SLICEB.K1.INIT 1100110011000000
word: SLICEC.K0.INIT 1010101010100000
word: SLICEC.K1.INIT 1100110011000000
word: SLICED.K0.INIT 1100110011000000
word: SLICED.K1.INIT 1100110011000000
enum: SLICEA.MODE CCU2
enum: SLICEA.CCU2.INJECT1_0 NO
enum: SLICEA.B0MUX 1
enum: SLICEA.C0MUX 1
enum: SLICEA.D0MUX 1
enum: SLICEA.MODE CCU2
enum: SLICEA.CCU2.INJECT1_1 NO
enum: SLICEA.B1MUX 1
enum: SLICEA.C1MUX 1
enum: SLICEA.D1MUX 1
enum: SLICEB.MODE CCU2
enum: SLICEB.CCU2.INJECT1_0 NO
enum: SLICEB.B0MUX 1
enum: SLICEB.C0MUX 1
enum: SLICEB.D0MUX 1
enum: SLICEB.MODE CCU2
enum: SLICEB.CCU2.INJECT1_1 NO
enum: SLICEB.A1MUX 1
enum: SLICEB.C1MUX 1
enum: SLICEB.D1MUX 1
enum: SLICEC.MODE CCU2
enum: SLICEC.CCU2.INJECT1_0 NO
enum: SLICEC.B0MUX 1
enum: SLICEC.C0MUX 1
enum: SLICEC.D0MUX 1
enum: SLICEC.MODE CCU2
enum: SLICEC.CCU2.INJECT1_1 NO
enum: SLICEC.A1MUX 1
enum: SLICEC.C1MUX 1
enum: SLICEC.D1MUX 1
enum: SLICED.MODE CCU2
enum: SLICED.CCU2.INJECT1_0 NO
enum: SLICED.A0MUX 1
enum: SLICED.C0MUX 1
enum: SLICED.D0MUX 1
enum: SLICED.MODE CCU2
enum: SLICED.CCU2.INJECT1_1 NO
enum: SLICED.A1MUX 1
enum: SLICED.C1MUX 1
enum: SLICED.D1MUX 1
.tile R2C34:PLC2
arc: E1_H02E0001 W1_H02E0501
arc: E1_H02E0301 V06N0003
arc: E1_H02E0501 W1_H02E0401
arc: H00R0000 H02W0601
arc: H00R0100 E1_H02W0501
arc: S1_V02S0001 H01E0001
arc: S1_V02S0101 H02E0101
arc: S1_V02S0301 H01E0101
arc: S1_V02S0701 W1_H02E0701
arc: W1_H02W0101 E1_H02W0001
arc: W1_H02W0501 V06N0303
arc: W1_H02W0701 V06N0203
arc: A6 S1_V02N0101
arc: B0 E1_H02W0101
arc: B4 V02N0701
arc: C4 Q4
arc: C6 Q6
arc: CE1 H00R0000
arc: CE2 V02N0601
arc: CE3 H00R0100
arc: CLK0 G_HPBX0000
arc: D4 H02E0001
arc: D6 V00B0000
arc: E1_H01E0101 F0
arc: F0 F0_SLICE
arc: F4 F4_SLICE
arc: F6 F6_SLICE
arc: H01W0000 F6
arc: H01W0100 Q2
arc: M2 V00B0000
arc: M6 V00B0000
arc: MUXCLK1 CLK0
arc: MUXCLK2 CLK0
arc: MUXCLK3 CLK0
arc: V00B0000 Q4
arc: W1_H02W0601 Q6
word: SLICEA.K0.INIT 1100110011000000
word: SLICEA.K1.INIT 0000000000000000
word: SLICEB.K0.INIT 0000000000000000
word: SLICEB.K1.INIT 0000000000001110
word: SLICED.K0.INIT 1111101001010000
word: SLICEC.K0.INIT 1111000011001100
enum: SLICEA.MODE CCU2
enum: SLICEA.CCU2.INJECT1_0 NO
enum: SLICEA.A0MUX 1
enum: SLICEA.C0MUX 1
enum: SLICEA.D0MUX 1
enum: SLICEA.MODE CCU2
enum: SLICEA.CCU2.INJECT1_1 NO
enum: SLICEA.A1MUX 1
enum: SLICEA.B1MUX 1
enum: SLICEA.C1MUX 1
enum: SLICEA.D1MUX 1
enum: SLICEB.MODE CCU2
enum: SLICEB.CCU2.INJECT1_0 NO
enum: SLICEB.A0MUX 1
enum: SLICEB.B0MUX 1
enum: SLICEB.C0MUX 1
enum: SLICEB.D0MUX 1
enum: SLICEB.MODE CCU2
enum: SLICEB.CCU2.INJECT1_1 NO
enum: SLICEB.A1MUX 1
enum: SLICEB.B1MUX 1
enum: SLICEB.C1MUX 1
enum: SLICEB.D1MUX 1
enum: SLICED.MODE LOGIC
enum: SLICED.CCU2.INJECT1_0 _NONE_
enum: SLICED.B0MUX 1
enum: SLICEC.GSR DISABLED
enum: SLICEC.REG0.SD 1
enum: SLICEC.REG0.REGSET RESET
enum: SLICEC.REG0.LSRMODE LSR
enum: SLICEC.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEC.MODE LOGIC
enum: SLICEC.CCU2.INJECT1_0 _NONE_
enum: SLICEC.A0MUX 1
enum: SLICEB.GSR DISABLED
enum: SLICEB.REG0.SD 0
enum: SLICEB.REG0.REGSET RESET
enum: SLICEB.REG0.LSRMODE LSR
enum: SLICEB.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICED.GSR DISABLED
enum: SLICED.REG0.SD 0
enum: SLICED.REG0.REGSET RESET
enum: SLICED.REG0.LSRMODE LSR
enum: SLICED.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
.tile R2C35:PLC2
arc: E1_H02E0001 V02N0001
arc: E1_H02E0101 S3_V06N0103
arc: E1_H02E0401 S3_V06N0203
arc: E1_H02E0701 S1_V02N0701
arc: H00L0000 S1_V02N0001
arc: H00R0000 W1_H02E0601
arc: S1_V02S0201 V01N0001
arc: S1_V02S0501 H01E0101
arc: S1_V02S0601 E1_H01W0000
arc: S1_V02S0701 W1_H02E0701
arc: V00T0000 H02E0001
arc: W1_H02W0401 E1_H02W0401
arc: W1_H02W0601 E1_H02W0601
arc: A0 H02W0701
arc: A2 S1_V02N0701
arc: A3 S1_V02N0501
arc: A4 V02N0101
arc: A5 H02E0501
arc: A6 E1_H02W0501
arc: B2 H02E0301
arc: B3 H00L0000
arc: B4 H00R0000
arc: B5 V02N0701
arc: B6 V00T0000
arc: E1_H01E0001 F3
arc: E1_H02E0501 F5
arc: E1_H02E0601 F6
arc: F3 F3_SLICE
arc: F4 F4_SLICE
arc: F5 F5_SLICE
arc: F6 F6_SLICE
arc: S1_V02S0401 F4
word: SLICEA.K0.INIT 0000000000001010
word: SLICEA.K1.INIT 1111111111111111
word: SLICEB.K0.INIT 0110011001101010
word: SLICEB.K1.INIT 0110011001101100
word: SLICEC.K0.INIT 0110011001101010
word: SLICEC.K1.INIT 0110011001101100
word: SLICED.K0.INIT 0110011001101010
word: SLICED.K1.INIT 0000000000000000
enum: SLICEA.MODE CCU2
enum: SLICEA.CCU2.INJECT1_0 NO
enum: SLICEA.B0MUX 1
enum: SLICEA.C0MUX 1
enum: SLICEA.D0MUX 1
enum: SLICEA.MODE CCU2
enum: SLICEA.CCU2.INJECT1_1 YES
enum: SLICEA.A1MUX 1
enum: SLICEA.B1MUX 1
enum: SLICEA.C1MUX 1
enum: SLICEA.D1MUX 1
enum: SLICEB.MODE CCU2
enum: SLICEB.CCU2.INJECT1_0 NO
enum: SLICEB.C0MUX 1
enum: SLICEB.D0MUX 1
enum: SLICEB.MODE CCU2
enum: SLICEB.CCU2.INJECT1_1 NO
enum: SLICEB.C1MUX 1
enum: SLICEB.D1MUX 1
enum: SLICEC.MODE CCU2
enum: SLICEC.CCU2.INJECT1_0 NO
enum: SLICEC.C0MUX 1
enum: SLICEC.D0MUX 1
enum: SLICEC.MODE CCU2
enum: SLICEC.CCU2.INJECT1_1 NO
enum: SLICEC.C1MUX 1
enum: SLICEC.D1MUX 1
enum: SLICED.MODE CCU2
enum: SLICED.CCU2.INJECT1_0 NO
enum: SLICED.C0MUX 1
enum: SLICED.D0MUX 1
enum: SLICED.MODE CCU2
enum: SLICED.CCU2.INJECT1_1 NO
enum: SLICED.A1MUX 1
enum: SLICED.B1MUX 1
enum: SLICED.C1MUX 1
enum: SLICED.D1MUX 1
.tile R2C36:PLC2
arc: E1_H02E0301 V02S0301
arc: H00L0100 V02N0301
arc: H00R0000 H02E0401
arc: H00R0100 H02E0701
arc: S1_V02S0001 H01E0001
arc: S1_V02S0101 H02E0101
arc: S1_V02S0301 H06W0003
arc: S1_V02S0401 H06W0203
arc: S1_V02S0501 H02E0501
arc: S1_V02S0701 H06W0203
arc: V00B0000 H02E0601
arc: V00B0100 H02W0701
arc: W1_H02W0001 S1_V02N0001
arc: W1_H02W0101 E1_H02W0001
arc: W1_H02W0501 E1_H02W0501
arc: W1_H02W0701 E1_H01W0100
arc: W3_H06W0303 E1_H01W0100
arc: A2 F5
arc: A5 Q5
arc: A6 V02S0301
arc: A7 V02S0301
arc: B2 H02W0301
arc: B3 H01W0100
arc: B6 E1_H02W0301
arc: B7 E1_H02W0101
arc: C2 H00L0000
arc: C3 E1_H02W0601
arc: C5 E1_H02W0601
arc: C6 V02N0201
arc: C7 E1_H02W0401
arc: CE2 H00R0000
arc: CE3 H02E0101
arc: CLK0 G_HPBX0000
arc: D2 V01S0100
arc: D3 V02N0001
arc: D5 S1_V02N0401
arc: D6 E1_H02W0201
arc: D7 V02N0401
arc: E3_H06E0103 Q2
arc: F2 F2_SLICE
arc: F3 F3_SLICE
arc: F5 F5_SLICE
arc: F6 F5D_SLICE
arc: H00L0000 Q2
arc: H01W0000 F6
arc: H01W0100 Q7
arc: LSR0 V00B0100
arc: LSR1 V00B0100
arc: M5 H00L0100
arc: M6 V00B0000
arc: M7 H00R0100
arc: MUXCLK1 CLK0
arc: MUXCLK2 CLK0
arc: MUXCLK3 CLK0
arc: MUXLSR1 LSR1
arc: MUXLSR2 LSR0
arc: MUXLSR3 LSR1
arc: V01S0100 F3
word: SLICED.K0.INIT 1111000001000100
word: SLICED.K1.INIT 1111111010101110
word: SLICEB.K1.INIT 1100111111000000
word: SLICEC.K1.INIT 0101111110100000
word: SLICEB.K0.INIT 0110100110010110
word: SLICEA.K0.INIT 0000000000000000
word: SLICEA.K1.INIT 0000000000001110
enum: SLICEC.GSR DISABLED
enum: SLICEC.REG1.SD 0
enum: SLICEC.REG1.REGSET RESET
enum: SLICEC.REG1.LSRMODE LSR
enum: SLICEC.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICED.GSR DISABLED
enum: SLICED.REG1.SD 0
enum: SLICED.REG1.REGSET RESET
enum: SLICED.REG1.LSRMODE LSR
enum: SLICED.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICED.MODE LOGIC
enum: SLICED.CCU2.INJECT1_0 _NONE_
enum: SLICED.MODE LOGIC
enum: SLICED.CCU2.INJECT1_1 _NONE_
enum: SLICEB.MODE LOGIC
enum: SLICEB.CCU2.INJECT1_1 _NONE_
enum: SLICEB.A1MUX 1
enum: SLICEC.MODE LOGIC
enum: SLICEC.CCU2.INJECT1_1 _NONE_
enum: SLICEC.B1MUX 1
enum: SLICEB.MODE LOGIC
enum: SLICEB.CCU2.INJECT1_0 _NONE_
enum: SLICEA.MODE CCU2
enum: SLICEA.CCU2.INJECT1_0 NO
enum: SLICEA.A0MUX 1
enum: SLICEA.B0MUX 1
enum: SLICEA.C0MUX 1
enum: SLICEA.D0MUX 1
enum: SLICEA.MODE CCU2
enum: SLICEA.CCU2.INJECT1_1 NO
enum: SLICEA.A1MUX 1
enum: SLICEA.B1MUX 1
enum: SLICEA.C1MUX 1
enum: SLICEA.D1MUX 1
enum: SLICEB.GSR DISABLED
enum: SLICEB.REG0.SD 1
enum: SLICEB.REG0.REGSET RESET
enum: SLICEB.REG0.LSRMODE LSR
enum: SLICEB.CEMUX 1
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
.tile R2C37:PLC2
arc: E1_H02E0301 V02S0301
arc: E1_H02E0401 V06N0203
arc: E1_H02E0501 E1_H01W0100
arc: E1_H02E0601 V06N0303
arc: E1_H02E0701 V02S0701
arc: H00R0000 W1_H02E0401
arc: H00R0100 E1_H02W0501
arc: V00B0000 V02N0001
arc: V00T0100 V02S0701
arc: W1_H02W0301 V02N0301
arc: W1_H02W0401 V06N0203
arc: W1_H02W0501 S1_V02N0501
arc: W1_H02W0601 V06N0303
arc: W1_H02W0701 V02S0701
arc: A0 H02W0701
arc: B0 F3
arc: B2 E1_H01W0100
arc: B3 E1_H01W0100
arc: C0 H00L0000
arc: C2 N1_V01N0001
arc: C3 E1_H01W0000
arc: CE1 H00R0000
arc: CE2 H00R0000
arc: CE3 W1_H02E0101
arc: CLK0 G_HPBX0000
arc: D0 F2
arc: D2 S1_V02N0001
arc: D3 V00B0100
arc: E1_H01E0001 Q3
arc: F0 F0_SLICE
arc: F2 F2_SLICE
arc: F3 F3_SLICE
arc: F4 F4_SLICE
arc: H00L0000 Q0
arc: H01W0100 F4
arc: LSR0 V00T0100
arc: LSR1 V00T0100
arc: M3 H00R0100
arc: M5 W1_H02E0001
arc: M6 V00B0000
arc: MUXCLK0 CLK0
arc: MUXCLK1 CLK0
arc: MUXCLK2 CLK0
arc: MUXCLK3 CLK0
arc: MUXLSR0 LSR0
arc: MUXLSR1 LSR1
arc: MUXLSR2 LSR1
arc: MUXLSR3 LSR0
arc: N1_V01N0001 Q6
arc: N1_V01N0101 Q0
arc: S1_V02S0601 F4
arc: V00B0100 Q5
word: SLICEC.K0.INIT 0000000000000000
word: SLICEB.K0.INIT 1111001111000000
word: SLICEB.K1.INIT 0011110011110000
word: SLICEA.K0.INIT 0110100110010110
enum: SLICEB.GSR DISABLED
enum: SLICEB.REG1.SD 0
enum: SLICEB.REG1.REGSET RESET
enum: SLICEB.REG1.LSRMODE LSR
enum: SLICEB.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEC.GSR DISABLED
enum: SLICEC.REG1.SD 0
enum: SLICEC.REG1.REGSET RESET
enum: SLICEC.REG1.LSRMODE LSR
enum: SLICEC.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICED.GSR DISABLED
enum: SLICED.REG0.SD 0
enum: SLICED.REG0.REGSET RESET
enum: SLICED.REG0.LSRMODE LSR
enum: SLICED.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEC.MODE LOGIC
enum: SLICEC.CCU2.INJECT1_0 _NONE_
enum: SLICEC.A0MUX 1
enum: SLICEC.B0MUX 1
enum: SLICEC.C0MUX 1
enum: SLICEC.D0MUX 1
enum: SLICEB.MODE LOGIC
enum: SLICEB.CCU2.INJECT1_0 _NONE_
enum: SLICEB.A0MUX 1
enum: SLICEB.MODE LOGIC
enum: SLICEB.CCU2.INJECT1_1 _NONE_
enum: SLICEB.A1MUX 1
enum: SLICEA.MODE LOGIC
enum: SLICEA.CCU2.INJECT1_0 _NONE_
enum: SLICEA.GSR DISABLED
enum: SLICEA.REG0.SD 1
enum: SLICEA.REG0.REGSET RESET
enum: SLICEA.REG0.LSRMODE LSR
enum: SLICEA.CEMUX 1
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
.tile R2C38:PLC2
arc: E1_H02E0501 V06N0303
arc: H00L0000 S1_V02N0001
arc: H00L0100 S1_V02N0301
arc: H00R0100 H02E0501
arc: H01W0100 W3_H06E0303
arc: S1_V02S0601 H02E0601
arc: V00B0000 V02N0001
arc: V00T0100 V02N0701
arc: W1_H02W0001 V06N0003
arc: W1_H02W0101 E1_H01W0100
arc: W1_H02W0201 N1_V01S0000
arc: W1_H02W0301 E1_H01W0100
arc: W1_H02W0401 N1_V01S0000
arc: W1_H02W0501 V06N0303
arc: W1_H02W0601 W3_H06E0303
arc: A0 V01N0101
arc: A1 V01N0101
arc: A2 V00B0000
arc: A3 V00B0000
arc: A4 F5
arc: B0 V01N0001
arc: B1 V01N0001
arc: B2 W1_H02E0301
arc: B3 W1_H02E0301
arc: B4 H00R0000
arc: B5 V01S0000
arc: B7 S1_V02N0701
arc: C0 H02E0401
arc: C1 H02E0401
arc: C2 H02E0401
arc: C3 H02E0401
arc: C4 E1_H01E0101
arc: C5 H01E0001
arc: C7 V02N0201
arc: CE0 S1_V02N0201
arc: CE1 S1_V02N0201
arc: CE3 H00L0100
arc: CLK0 G_HPBX0000
arc: D0 V02S0001
arc: D1 V02S0001
arc: D2 V02N0201
arc: D3 V02N0201
arc: D4 S1_V02N0601
arc: D5 H00R0100
arc: D7 S1_V02N0401
arc: E1_H01E0001 F0
arc: E1_H01E0101 Q6
arc: E3_H06E0203 Q4
arc: F0 F5A_SLICE
arc: F2 F5B_SLICE
arc: F4 F4_SLICE
arc: F5 F5_SLICE
arc: F7 F7_SLICE
arc: H00R0000 Q4
arc: H01W0000 Q1
arc: LSR0 H02E0301
arc: LSR1 H02E0301
arc: M0 V00T0100
arc: M1 H02W0001
arc: M2 V00B0100
arc: M3 H00L0000
arc: M6 V00T0000
arc: M7 H02W0201
arc: MUXCLK0 CLK0
arc: MUXCLK1 CLK0
arc: MUXCLK2 CLK0
arc: MUXCLK3 CLK0
arc: MUXLSR0 LSR0
arc: MUXLSR1 LSR1
arc: MUXLSR2 LSR1
arc: MUXLSR3 LSR0
arc: V00B0100 F7
arc: V00T0000 F2
arc: V01S0000 Q3
arc: W1_H02W0701 Q7
word: SLICEA.K0.INIT 1100101000000000
word: SLICEA.K1.INIT 1100101011111111
word: SLICED.K1.INIT 1100110011110000
word: SLICEB.K0.INIT 1000110010000000
word: SLICEB.K1.INIT 1011111110110011
word: SLICEC.K1.INIT 0011110011001100
word: SLICEC.K0.INIT 0110100110010110
enum: SLICEA.MODE LOGIC
enum: SLICEA.CCU2.INJECT1_0 _NONE_
enum: SLICEA.MODE LOGIC
enum: SLICEA.CCU2.INJECT1_1 _NONE_
enum: SLICED.MODE LOGIC
enum: SLICED.CCU2.INJECT1_1 _NONE_
enum: SLICED.A1MUX 1
enum: SLICEB.MODE LOGIC
enum: SLICEB.CCU2.INJECT1_0 _NONE_
enum: SLICEB.MODE LOGIC
enum: SLICEB.CCU2.INJECT1_1 _NONE_
enum: SLICED.GSR DISABLED
enum: SLICED.REG0.SD 0
enum: SLICED.REG0.REGSET RESET
enum: SLICED.REG0.LSRMODE LSR
enum: SLICED.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICED.GSR DISABLED
enum: SLICED.REG1.SD 0
enum: SLICED.REG1.REGSET RESET
enum: SLICED.REG1.LSRMODE LSR
enum: SLICED.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEC.MODE LOGIC
enum: SLICEC.CCU2.INJECT1_1 _NONE_
enum: SLICEC.A1MUX 1
enum: SLICEC.MODE LOGIC
enum: SLICEC.CCU2.INJECT1_0 _NONE_
enum: SLICEB.GSR DISABLED
enum: SLICEB.REG1.SD 0
enum: SLICEB.REG1.REGSET RESET
enum: SLICEB.REG1.LSRMODE LSR
enum: SLICEB.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEA.GSR DISABLED
enum: SLICEA.REG1.SD 0
enum: SLICEA.REG1.REGSET RESET
enum: SLICEA.REG1.LSRMODE LSR
enum: SLICEA.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEC.GSR DISABLED
enum: SLICEC.REG0.SD 1
enum: SLICEC.REG0.REGSET RESET
enum: SLICEC.REG0.LSRMODE LSR
enum: SLICEC.CEMUX 1
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
.tile R2C39:PLC2
arc: E1_H02E0301 W1_H02E0301
arc: H00L0000 V02N0201
arc: H00R0000 W1_H02E0601
arc: H00R0100 H02E0501
arc: S1_V02S0601 W1_H02E0601
arc: W1_H02W0201 H01E0001
arc: W1_H02W0501 E1_H01W0100
arc: W3_H06W0203 E1_H01W0000
arc: A0 W1_H02E0701
arc: A2 H00L0100
arc: A3 H00L0100
arc: A7 V00T0100
arc: B1 W1_H02E0301
arc: B2 S1_V02N0301
arc: B3 S1_V02N0301
arc: C0 V02S0601
arc: C1 E1_H01W0000
arc: C2 W1_H02E0401
arc: C3 W1_H02E0401
arc: C7 V02N0201
arc: CE1 H00R0100
arc: CE2 H00R0000
arc: CLK0 G_HPBX0000
arc: D0 V02N0001
arc: D1 V02S0001
arc: D2 V01S0100
arc: D3 V01S0100
arc: D7 E1_H02W0201
arc: F0 F0_SLICE
arc: F1 F1_SLICE
arc: F2 F5B_SLICE
arc: F7 F7_SLICE
arc: H00L0100 Q3
arc: H01W0100 Q1
arc: M2 V00B0100
arc: M3 H00L0000
arc: M5 H00L0000
arc: MUXCLK0 CLK0
arc: MUXCLK1 CLK0
arc: MUXCLK2 CLK0
arc: S3_V06S0103 Q1
arc: V00B0100 F7
arc: V00T0100 Q3
arc: V01S0100 Q5
arc: W1_H02W0001 F2
arc: W3_H06W0003 Q0
word: SLICEA.K1.INIT 1111110000110000
word: SLICEA.K0.INIT 1111010110100000
word: SLICED.K1.INIT 1111000010101010
word: SLICEB.K0.INIT 1100100000001000
word: SLICEB.K1.INIT 1111101100111011
enum: SLICEA.MODE LOGIC
enum: SLICEA.CCU2.INJECT1_1 _NONE_
enum: SLICEA.A1MUX 1
enum: SLICEA.MODE LOGIC
enum: SLICEA.CCU2.INJECT1_0 _NONE_
enum: SLICEA.B0MUX 1
enum: SLICEA.GSR DISABLED
enum: SLICEA.REG0.SD 1
enum: SLICEA.REG0.REGSET RESET
enum: SLICEA.REG0.LSRMODE LSR
enum: SLICEA.CEMUX 1
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICED.MODE LOGIC
enum: SLICED.CCU2.INJECT1_1 _NONE_
enum: SLICED.B1MUX 1
enum: SLICEB.MODE LOGIC
enum: SLICEB.CCU2.INJECT1_0 _NONE_
enum: SLICEB.MODE LOGIC
enum: SLICEB.CCU2.INJECT1_1 _NONE_
enum: SLICEC.GSR DISABLED
enum: SLICEC.REG1.SD 0
enum: SLICEC.REG1.REGSET RESET
enum: SLICEC.REG1.LSRMODE LSR
enum: SLICEC.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEB.GSR DISABLED
enum: SLICEB.REG1.SD 0
enum: SLICEB.REG1.REGSET RESET
enum: SLICEB.REG1.LSRMODE LSR
enum: SLICEB.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEA.GSR DISABLED
enum: SLICEA.REG1.SD 1
enum: SLICEA.REG1.REGSET RESET
enum: SLICEA.REG1.LSRMODE LSR
enum: SLICEA.CEMUX 1
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
.tile R2C40:PLC2
arc: B0 H02E0301
arc: C0 V02S0401
arc: CLK0 G_HPBX0000
arc: D0 V02N0001
arc: F0 F0_SLICE
arc: H01W0000 Q0
arc: H01W0100 Q0
arc: MUXCLK0 CLK0
word: SLICEA.K0.INIT 1111001111000000
enum: SLICEA.MODE LOGIC
enum: SLICEA.CCU2.INJECT1_0 _NONE_
enum: SLICEA.A0MUX 1
enum: SLICEA.GSR DISABLED
enum: SLICEA.REG0.SD 1
enum: SLICEA.REG0.REGSET RESET
enum: SLICEA.REG0.LSRMODE LSR
enum: SLICEA.CEMUX 1
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
.tile R2C41:PLC2
arc: W1_H02W0201 S1_V02N0201
.tile R2C42:PLC2
arc: E1_H02E0201 W3_H06E0103
.tile R2C44:PLC2
arc: E1_H02E0701 W3_H06E0203
arc: N1_V02N0201 W1_H02E0201
.tile R2C46:PLC2
arc: N1_V02N0701 W1_H02E0701
.tile R3C30:PLC2
arc: E1_H02E0001 S1_V02N0001
arc: E1_H02E0301 E3_H06W0003
arc: E1_H02E0601 S1_V02N0601
arc: E3_H06E0003 S3_V06N0003
arc: S1_V02S0301 S3_V06N0003
.tile R3C31:PLC2
arc: E1_H02E0101 S1_V02N0101
arc: E1_H02E0201 S1_V02N0201
arc: E1_H02E0301 V02N0301
arc: E1_H02E0701 S1_V02N0701
arc: S1_V02S0601 E1_H01W0000
.tile R3C32:PLC2
arc: E1_H02E0101 V02N0101
arc: E1_H02E0301 V02S0301
arc: E1_H02E0501 V02S0501
arc: E1_H02E0601 W1_H02E0301
arc: E1_H02E0701 N1_V01S0100
arc: H00R0000 S1_V02N0601
arc: S1_V02S0701 H02W0701
arc: V00B0000 W1_H02E0601
arc: V00T0000 W1_H02E0001
arc: A2 V00T0000
arc: A3 V00T0000
arc: A4 S1_V02N0101
arc: B0 V00B0000
arc: B2 E1_H01W0100
arc: B3 E1_H01W0100
arc: B5 W1_H02E0301
arc: C0 S1_V02N0401
arc: C1 W1_H02E0601
arc: C2 W1_H02E0601
arc: C3 W1_H02E0601
arc: C5 E1_H02W0601
arc: C6 V02N0201
arc: CE0 H02E0101
arc: CE2 V02N0601
arc: CE3 V02N0601
arc: CLK0 G_HPBX0000
arc: D1 H00R0000
arc: D2 E1_H02W0201
arc: D3 E1_H02W0001
arc: D4 V00B0000
arc: D5 E1_H02W0001
arc: D6 V00B0000
arc: E1_H01E0001 F2
arc: F0 F0_SLICE
arc: F1 F1_SLICE
arc: F2 F5B_SLICE
arc: F4 F4_SLICE
arc: F5 F5_SLICE
arc: F6 F6_SLICE
arc: H01W0000 Q4
arc: LSR0 H02E0301
arc: LSR1 H02E0301
arc: M2 V00B0100
arc: MUXCLK0 CLK0
arc: MUXCLK2 CLK0
arc: MUXCLK3 CLK0
arc: MUXLSR0 LSR0
arc: MUXLSR2 LSR0
arc: MUXLSR3 LSR1
arc: N1_V01N0001 Q4
arc: N1_V01N0101 Q0
arc: N1_V02N0301 Q1
arc: N1_V02N0401 Q6
arc: S1_V02S0101 Q1
arc: S1_V02S0201 Q0
arc: S1_V02S0401 Q6
arc: S1_V02S0601 Q4
arc: V00B0100 F5
arc: V01S0000 Q1
arc: V01S0100 Q6
word: SLICEA.K1.INIT 1111000000000000
word: SLICEC.K0.INIT 1010101000000000
word: SLICEA.K0.INIT 1100000011000000
word: SLICEC.K1.INIT 1100111111000000
word: SLICEB.K0.INIT 1101000010000000
word: SLICEB.K1.INIT 1101111110001111
word: SLICED.K0.INIT 1111000000000000
enum: SLICEA.MODE LOGIC
enum: SLICEA.CCU2.INJECT1_1 _NONE_
enum: SLICEA.A1MUX 1
enum: SLICEA.B1MUX 1
enum: SLICEC.MODE LOGIC
enum: SLICEC.CCU2.INJECT1_0 _NONE_
enum: SLICEC.B0MUX 1
enum: SLICEC.C0MUX 1
enum: SLICEA.MODE LOGIC
enum: SLICEA.CCU2.INJECT1_0 _NONE_
enum: SLICEA.A0MUX 1
enum: SLICEA.D0MUX 1
enum: SLICED.GSR DISABLED
enum: SLICED.REG0.SD 1
enum: SLICED.REG0.REGSET RESET
enum: SLICED.REG0.LSRMODE LSR
enum: SLICED.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEA.GSR DISABLED
enum: SLICEA.REG1.SD 1
enum: SLICEA.REG1.REGSET RESET
enum: SLICEA.REG1.LSRMODE LSR
enum: SLICEA.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEA.GSR DISABLED
enum: SLICEA.REG0.SD 1
enum: SLICEA.REG0.REGSET RESET
enum: SLICEA.REG0.LSRMODE LSR
enum: SLICEA.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEC.GSR DISABLED
enum: SLICEC.REG0.SD 1
enum: SLICEC.REG0.REGSET RESET
enum: SLICEC.REG0.LSRMODE LSR
enum: SLICEC.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEC.MODE LOGIC
enum: SLICEC.CCU2.INJECT1_1 _NONE_
enum: SLICEC.A1MUX 1
enum: SLICEB.MODE LOGIC
enum: SLICEB.CCU2.INJECT1_0 _NONE_
enum: SLICEB.MODE LOGIC
enum: SLICEB.CCU2.INJECT1_1 _NONE_
enum: SLICED.MODE LOGIC
enum: SLICED.CCU2.INJECT1_0 _NONE_
enum: SLICED.A0MUX 1
enum: SLICED.B0MUX 1
.tile R3C33:PLC2
arc: E1_H02E0201 W1_H02E0701
arc: E1_H02E0301 V02S0301
arc: E1_H02E0401 N1_V01S0000
arc: E1_H02E0501 V02S0501
arc: E1_H02E0601 V06N0303
arc: E1_H02E0701 N1_V01S0100
arc: H00R0000 S1_V02N0401
arc: N1_V02N0701 S1_V02N0601
arc: S1_V02S0201 H01E0001
arc: S1_V02S0301 E1_H02W0301
arc: S1_V02S0501 H06W0303
arc: S1_V02S0701 H06W0203
arc: V00B0000 V02N0201
arc: V00T0000 W1_H02E0201
arc: W1_H02W0701 V02N0701
arc: A0 V02N0701
arc: A2 V00T0000
arc: A3 S1_V02N0701
arc: A4 V02N0301
arc: A5 H02E0701
arc: A6 H02E0501
arc: A7 V02S0101
arc: B3 H02E0101
arc: B4 H02E0301
arc: B5 H02W0301
arc: B6 V00B0000
arc: B7 E1_H02W0101
arc: CE0 H00R0000
arc: CLK0 G_HPBX0000
arc: H01W0100 Q0
arc: M0 H02E0601
arc: MUXCLK0 CLK0
word: SLICED.K1.INIT 1001100110011010
word: SLICED.K0.INIT 1001100110011010
word: SLICEC.K1.INIT 1001100110011010
word: SLICEC.K0.INIT 1001100110011100
word: SLICEB.K1.INIT 1001100110011100
word: SLICEB.K0.INIT 1001100110011010
word: SLICEA.K1.INIT 1111111111111111
word: SLICEA.K0.INIT 0000000000001010
enum: SLICED.MODE CCU2
enum: SLICED.CCU2.INJECT1_1 NO
enum: SLICED.C1MUX 1
enum: SLICED.D1MUX 1
enum: SLICED.MODE CCU2
enum: SLICED.CCU2.INJECT1_0 NO
enum: SLICED.C0MUX 1
enum: SLICED.D0MUX 1
enum: SLICEC.MODE CCU2
enum: SLICEC.CCU2.INJECT1_1 NO
enum: SLICEC.C1MUX 1
enum: SLICEC.D1MUX 1
enum: SLICEC.MODE CCU2
enum: SLICEC.CCU2.INJECT1_0 NO
enum: SLICEC.C0MUX 1
enum: SLICEC.D0MUX 1
enum: SLICEB.MODE CCU2
enum: SLICEB.CCU2.INJECT1_1 NO
enum: SLICEB.C1MUX 1
enum: SLICEB.D1MUX 1
enum: SLICEB.MODE CCU2
enum: SLICEB.CCU2.INJECT1_0 NO
enum: SLICEB.B0MUX 1
enum: SLICEB.C0MUX 1
enum: SLICEB.D0MUX 1
enum: SLICEA.MODE CCU2
enum: SLICEA.CCU2.INJECT1_1 YES
enum: SLICEA.A1MUX 1
enum: SLICEA.B1MUX 1
enum: SLICEA.C1MUX 1
enum: SLICEA.D1MUX 1
enum: SLICEA.MODE CCU2
enum: SLICEA.CCU2.INJECT1_0 NO
enum: SLICEA.B0MUX 1
enum: SLICEA.C0MUX 1
enum: SLICEA.D0MUX 1
enum: SLICEA.GSR DISABLED
enum: SLICEA.REG0.SD 0
enum: SLICEA.REG0.REGSET RESET
enum: SLICEA.REG0.LSRMODE LSR
enum: SLICEA.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
.tile R3C34:PLC2
arc: E1_H02E0001 S3_V06N0003
arc: E1_H02E0201 S1_V02N0201
arc: E1_H02E0401 S1_V02N0401
arc: H00L0000 H02E0201
arc: H00R0000 H02E0401
arc: H00R0100 E1_H02W0701
arc: N1_V02N0601 E1_H02W0601
arc: N1_V02N0701 S1_V02N0601
arc: S1_V02S0001 H02W0001
arc: S1_V02S0301 N1_V02S0201
arc: S1_V02S0401 E1_H02W0401
arc: S1_V02S0601 H06W0303
arc: S3_V06S0203 E1_H01W0000
arc: V00B0000 V02S0001
arc: V00B0100 H02W0701
arc: V00T0000 E1_H02W0201
arc: W1_H02W0301 V01N0101
arc: W1_H02W0601 V06N0303
arc: A0 V02S0701
arc: A1 E1_H02W0501
arc: A2 S1_V02N0701
arc: A3 H02E0701
arc: A4 V02N0301
arc: A5 V00B0000
arc: A6 H02E0501
arc: A7 H00R0000
arc: B0 H00R0100
arc: B1 V02S0301
arc: B2 V02S0101
arc: B3 V01N0001
arc: B4 H02E0301
arc: B5 V00B0100
arc: B6 E1_H02W0301
arc: B7 V02N0701
arc: CE0 V02N0201
arc: CE1 H00L0000
arc: CLK0 G_HPBX0000
arc: M1 E1_H02W0001
arc: M2 V00T0000
arc: MUXCLK0 CLK0
arc: MUXCLK1 CLK0
arc: S1_V02S0101 Q1
arc: S3_V06S0103 Q1
arc: V01S0000 Q1
arc: W1_H02W0001 Q2
arc: W1_H02W0201 Q2
word: SLICED.K1.INIT 1001100110011010
word: SLICED.K0.INIT 1001100110011010
word: SLICEC.K1.INIT 1001100110011010
word: SLICEC.K0.INIT 1001100110011100
word: SLICEB.K1.INIT 1001100110011010
word: SLICEB.K0.INIT 1001100110011100
word: SLICEA.K1.INIT 1001100110011100
word: SLICEA.K0.INIT 1001100110011010
enum: SLICED.MODE CCU2
enum: SLICED.CCU2.INJECT1_1 NO
enum: SLICED.C1MUX 1
enum: SLICED.D1MUX 1
enum: SLICED.MODE CCU2
enum: SLICED.CCU2.INJECT1_0 NO
enum: SLICED.C0MUX 1
enum: SLICED.D0MUX 1
enum: SLICEC.MODE CCU2
enum: SLICEC.CCU2.INJECT1_1 NO
enum: SLICEC.C1MUX 1
enum: SLICEC.D1MUX 1
enum: SLICEC.MODE CCU2
enum: SLICEC.CCU2.INJECT1_0 NO
enum: SLICEC.C0MUX 1
enum: SLICEC.D0MUX 1
enum: SLICEB.MODE CCU2
enum: SLICEB.CCU2.INJECT1_1 NO
enum: SLICEB.C1MUX 1
enum: SLICEB.D1MUX 1
enum: SLICEB.MODE CCU2
enum: SLICEB.CCU2.INJECT1_0 NO
enum: SLICEB.C0MUX 1
enum: SLICEB.D0MUX 1
enum: SLICEA.MODE CCU2
enum: SLICEA.CCU2.INJECT1_1 NO
enum: SLICEA.C1MUX 1
enum: SLICEA.D1MUX 1
enum: SLICEA.MODE CCU2
enum: SLICEA.CCU2.INJECT1_0 NO
enum: SLICEA.C0MUX 1
enum: SLICEA.D0MUX 1
enum: SLICEA.GSR DISABLED
enum: SLICEA.REG1.SD 0
enum: SLICEA.REG1.REGSET RESET
enum: SLICEA.REG1.LSRMODE LSR
enum: SLICEA.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEB.GSR DISABLED
enum: SLICEB.REG0.SD 0
enum: SLICEB.REG0.REGSET RESET
enum: SLICEB.REG0.LSRMODE LSR
enum: SLICEB.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
.tile R3C35:PLC2
arc: E1_H02E0401 S1_V02N0401
arc: E1_H02E0701 V02N0701
arc: H00R0000 V02S0601
arc: H00R0100 E1_H02W0501
arc: N1_V01N0001 S3_V06N0003
arc: N1_V02N0001 S3_V06N0003
arc: N1_V02N0101 S1_V02N0001
arc: N1_V02N0701 H02W0701
arc: V00B0000 E1_H02W0401
arc: V00T0000 V02S0401
arc: V00T0100 H02W0101
arc: W1_H02W0101 S1_V02N0101
arc: W1_H02W0701 E1_H01W0100
arc: A0 V02S0701
arc: A1 V02S0501
arc: A4 N1_V01N0101
arc: A5 N1_V01N0101
arc: A6 S1_V02N0301
arc: A7 V00T0100
arc: B0 V02N0101
arc: B1 V02N0301
arc: B4 E1_H02W0101
arc: B5 E1_H02W0101
arc: B6 H02W0101
arc: B7 S1_V02N0701
arc: C4 W1_H02E0601
arc: C5 W1_H02E0601
arc: C6 V02S0201
arc: C7 E1_H02W0401
arc: CE0 H00R0100
arc: CE1 S1_V02N0201
arc: CE2 S1_V02N0601
arc: CE3 S1_V02N0601
arc: CLK0 G_HPBX0000
arc: D4 H02E0201
arc: D5 H02E0201
arc: D6 V00B0000
arc: D7 H02E0001
arc: E1_H01E0001 Q7
arc: E1_H02E0601 F4
arc: F2 F2_SLICE
arc: F4 F5C_SLICE
arc: F6 F5D_SLICE
arc: H00L0100 Q3
arc: H01W0000 Q0
arc: H01W0100 F6
arc: M0 V00B0100
arc: M1 H00L0100
arc: M2 E1_H02W0601
arc: M3 H01W0100
arc: M4 H02E0401
arc: M5 H00R0000
arc: M6 V00T0000
arc: M7 E1_H01W0000
arc: MUXCLK0 CLK0
arc: MUXCLK1 CLK0
arc: MUXCLK2 CLK0
arc: MUXCLK3 CLK0
arc: N1_V01N0101 Q1
arc: S1_V02S0001 F2
arc: S1_V02S0201 F2
arc: S3_V06S0003 Q0
arc: S3_V06S0103 F2
arc: V00B0100 Q5
arc: V01S0000 F2
arc: W1_H02W0001 Q2
arc: W1_H02W0301 Q1
word: SLICEB.K1.INIT 0000000000001110
word: SLICEB.K0.INIT 0000000000000000
word: SLICEA.K1.INIT 1001100110011010
word: SLICEA.K0.INIT 1001100110011010
word: SLICEC.K0.INIT 1111000011100010
word: SLICEC.K1.INIT 1111100010101010
word: SLICED.K1.INIT 1111110111101100
word: SLICED.K0.INIT 1101110000010000
enum: SLICEB.MODE CCU2
enum: SLICEB.CCU2.INJECT1_1 NO
enum: SLICEB.A1MUX 1
enum: SLICEB.B1MUX 1
enum: SLICEB.C1MUX 1
enum: SLICEB.D1MUX 1
enum: SLICEB.MODE CCU2
enum: SLICEB.CCU2.INJECT1_0 NO
enum: SLICEB.A0MUX 1
enum: SLICEB.B0MUX 1
enum: SLICEB.C0MUX 1
enum: SLICEB.D0MUX 1
enum: SLICEA.MODE CCU2
enum: SLICEA.CCU2.INJECT1_1 NO
enum: SLICEA.C1MUX 1
enum: SLICEA.D1MUX 1
enum: SLICEA.MODE CCU2
enum: SLICEA.CCU2.INJECT1_0 NO
enum: SLICEA.C0MUX 1
enum: SLICEA.D0MUX 1
enum: SLICEC.MODE LOGIC
enum: SLICEC.CCU2.INJECT1_0 _NONE_
enum: SLICEC.MODE LOGIC
enum: SLICEC.CCU2.INJECT1_1 _NONE_
enum: SLICED.MODE LOGIC
enum: SLICED.CCU2.INJECT1_1 _NONE_
enum: SLICED.MODE LOGIC
enum: SLICED.CCU2.INJECT1_0 _NONE_
enum: SLICEA.GSR DISABLED
enum: SLICEA.REG0.SD 0
enum: SLICEA.REG0.REGSET RESET
enum: SLICEA.REG0.LSRMODE LSR
enum: SLICEA.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEA.GSR DISABLED
enum: SLICEA.REG1.SD 0
enum: SLICEA.REG1.REGSET RESET
enum: SLICEA.REG1.LSRMODE LSR
enum: SLICEA.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEC.GSR DISABLED
enum: SLICEC.REG1.SD 0
enum: SLICEC.REG1.REGSET RESET
enum: SLICEC.REG1.LSRMODE LSR
enum: SLICEC.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICED.GSR DISABLED
enum: SLICED.REG1.SD 0
enum: SLICED.REG1.REGSET RESET
enum: SLICED.REG1.LSRMODE LSR
enum: SLICED.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEB.GSR DISABLED
enum: SLICEB.REG1.SD 0
enum: SLICEB.REG1.REGSET RESET
enum: SLICEB.REG1.LSRMODE LSR
enum: SLICEB.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEB.GSR DISABLED
enum: SLICEB.REG0.SD 0
enum: SLICEB.REG0.REGSET RESET
enum: SLICEB.REG0.LSRMODE LSR
enum: SLICEB.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
.tile R3C36:PLC2
arc: E1_H02E0001 S3_V06N0003
arc: E3_H06E0003 W3_H06E0003
arc: H00L0000 W1_H02E0201
arc: H00L0100 V02S0301
arc: H00R0000 H02E0401
arc: H00R0100 V02S0701
arc: N1_V02N0001 V01N0001
arc: N1_V02N0201 E1_H01W0000
arc: N1_V02N0301 W3_H06E0003
arc: N1_V02N0401 E1_H01W0000
arc: V00B0000 V02S0001
arc: V00B0100 N1_V02S0301
arc: V00T0100 V02S0501
arc: W1_H02W0001 H01E0001
arc: W1_H02W0101 E1_H02W0001
arc: W1_H02W0301 S1_V02N0301
arc: W1_H02W0501 V06N0303
arc: A0 S1_V02N0501
arc: A1 H00L0100
arc: A2 H02W0701
arc: A3 H02W0701
arc: A4 V02S0301
arc: A6 V02S0301
arc: A7 V02S0301
arc: B1 H02W0101
arc: B2 N1_V02S0301
arc: B3 N1_V02S0301
arc: B4 H02W0101
arc: B6 E1_H02W0101
arc: B7 E1_H02W0101
arc: C0 S1_V02N0401
arc: C1 H00L0000
arc: C2 V02S0401
arc: C3 V02S0401
arc: C4 H02E0401
arc: C6 V00B0100
arc: C7 V00B0100
arc: CE0 V02N0201
arc: CE2 V02N0601
arc: CLK0 G_HPBX0000
arc: D0 Q0
arc: D1 H00R0000
arc: D2 E1_H02W0001
arc: D3 E1_H02W0001
arc: D4 W1_H02E0201
arc: D6 E1_H01W0100
arc: D7 E1_H01W0100
arc: E1_H01E0001 F6
arc: E1_H02E0101 F1
arc: E1_H02E0601 F4
arc: E1_H02E0701 Q5
arc: E3_H06E0103 F1
arc: E3_H06E0203 F4
arc: F0 F0_SLICE
arc: F1 F1_SLICE
arc: F2 F5B_SLICE
arc: F4 F4_SLICE
arc: F6 F5D_SLICE
arc: H01W0000 F2
arc: H01W0100 Q4
arc: M2 V00T0100
arc: M4 E1_H02W0401
arc: M5 H00R0100
arc: M6 V00B0000
arc: MUXCLK0 CLK0
arc: MUXCLK2 CLK0
arc: S1_V02S0501 Q5
arc: S1_V02S0601 F4
arc: S3_V06S0103 F1
arc: S3_V06S0203 F4
arc: V01S0000 F1
arc: V01S0100 Q4
arc: W1_H02W0201 Q0
arc: W1_H02W0401 Q4
arc: W1_H02W0601 F4
arc: W1_H02W0701 Q5
arc: W3_H06W0003 Q0
arc: W3_H06W0203 Q4
arc: W3_H06W0303 Q5
word: SLICEB.K0.INIT 1010101000110000
word: SLICEB.K1.INIT 1110111011111100
word: SLICED.K0.INIT 1100111000000010
word: SLICED.K1.INIT 1111111011110010
word: SLICEA.K0.INIT 1111101000001010
word: SLICEC.K0.INIT 0010000000110000
word: SLICEA.K1.INIT 0000101100000000
enum: SLICEC.GSR DISABLED
enum: SLICEC.REG1.SD 0
enum: SLICEC.REG1.REGSET RESET
enum: SLICEC.REG1.LSRMODE LSR
enum: SLICEC.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEB.MODE LOGIC
enum: SLICEB.CCU2.INJECT1_0 _NONE_
enum: SLICEB.MODE LOGIC
enum: SLICEB.CCU2.INJECT1_1 _NONE_
enum: SLICED.MODE LOGIC
enum: SLICED.CCU2.INJECT1_0 _NONE_
enum: SLICED.MODE LOGIC
enum: SLICED.CCU2.INJECT1_1 _NONE_
enum: SLICEA.MODE LOGIC
enum: SLICEA.CCU2.INJECT1_0 _NONE_
enum: SLICEA.B0MUX 1
enum: SLICEC.MODE LOGIC
enum: SLICEC.CCU2.INJECT1_0 _NONE_
enum: SLICEA.MODE LOGIC
enum: SLICEA.CCU2.INJECT1_1 _NONE_
enum: SLICEC.GSR DISABLED
enum: SLICEC.REG0.SD 0
enum: SLICEC.REG0.REGSET RESET
enum: SLICEC.REG0.LSRMODE LSR
enum: SLICEC.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEA.GSR DISABLED
enum: SLICEA.REG0.SD 1
enum: SLICEA.REG0.REGSET RESET
enum: SLICEA.REG0.LSRMODE LSR
enum: SLICEA.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
.tile R3C37:PLC2
arc: E1_H02E0601 E1_H01W0000
arc: H00R0000 W1_H02E0601
arc: N1_V02N0001 S1_V02N0501
arc: S1_V02S0001 H02E0001
arc: S3_V06S0003 N1_V02S0301
arc: V00B0100 N1_V02S0301
arc: V00T0000 V02S0601
arc: V00T0100 N1_V02S0701
arc: W1_H02W0101 V06N0103
arc: W1_H02W0501 V06N0303
arc: W1_H02W0601 H01E0001
arc: W3_H06W0303 V06N0303
arc: A2 W1_H02E0701
arc: A5 H02E0701
arc: B0 V00T0000
arc: B3 V02N0101
arc: B4 S1_V02N0501
arc: B6 V02N0501
arc: CE1 V02N0201
arc: CE3 V02N0601
arc: CLK0 G_HPBX0000
arc: F3 F3_SLICE
arc: F4 F4_SLICE
arc: F5 F5_SLICE
arc: F6 F6_SLICE
arc: H01W0000 F6
arc: H01W0100 F3
arc: LSR0 V00B0100
arc: LSR1 V00T0100
arc: M3 H02W0201
arc: M7 H00R0000
arc: MUXCLK1 CLK0
arc: MUXCLK3 CLK0
arc: MUXLSR1 LSR1
arc: MUXLSR3 LSR0
arc: N1_V02N0301 Q3
arc: V01S0000 Q7
arc: W1_H02W0401 F4
arc: W1_H02W0701 F5
word: SLICEA.K0.INIT 0000000000001100
word: SLICEA.K1.INIT 1111111111111111
word: SLICEB.K0.INIT 0110011001101100
word: SLICEB.K1.INIT 1100110011000000
word: SLICEC.K0.INIT 1100110011000000
word: SLICEC.K1.INIT 1010101010100000
word: SLICED.K0.INIT 1100110011000000
word: SLICED.K1.INIT 0000000000000000
enum: SLICED.GSR DISABLED
enum: SLICED.REG1.SD 0
enum: SLICED.REG1.REGSET RESET
enum: SLICED.REG1.LSRMODE LSR
enum: SLICED.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEA.MODE CCU2
enum: SLICEA.CCU2.INJECT1_0 NO
enum: SLICEA.A0MUX 1
enum: SLICEA.C0MUX 1
enum: SLICEA.D0MUX 1
enum: SLICEA.MODE CCU2
enum: SLICEA.CCU2.INJECT1_1 YES
enum: SLICEA.A1MUX 1
enum: SLICEA.B1MUX 1
enum: SLICEA.C1MUX 1
enum: SLICEA.D1MUX 1
enum: SLICEB.MODE CCU2
enum: SLICEB.CCU2.INJECT1_0 NO
enum: SLICEB.B0MUX 1
enum: SLICEB.C0MUX 1
enum: SLICEB.D0MUX 1
enum: SLICEB.MODE CCU2
enum: SLICEB.CCU2.INJECT1_1 NO
enum: SLICEB.A1MUX 1
enum: SLICEB.C1MUX 1
enum: SLICEB.D1MUX 1
enum: SLICEC.MODE CCU2
enum: SLICEC.CCU2.INJECT1_0 NO
enum: SLICEC.A0MUX 1
enum: SLICEC.C0MUX 1
enum: SLICEC.D0MUX 1
enum: SLICEC.MODE CCU2
enum: SLICEC.CCU2.INJECT1_1 NO
enum: SLICEC.B1MUX 1
enum: SLICEC.C1MUX 1
enum: SLICEC.D1MUX 1
enum: SLICED.MODE CCU2
enum: SLICED.CCU2.INJECT1_0 NO
enum: SLICED.A0MUX 1
enum: SLICED.C0MUX 1
enum: SLICED.D0MUX 1
enum: SLICED.MODE CCU2
enum: SLICED.CCU2.INJECT1_1 NO
enum: SLICED.A1MUX 1
enum: SLICED.B1MUX 1
enum: SLICED.C1MUX 1
enum: SLICED.D1MUX 1
enum: SLICEB.GSR DISABLED
enum: SLICEB.REG1.SD 0
enum: SLICEB.REG1.REGSET RESET
enum: SLICEB.REG1.LSRMODE LSR
enum: SLICEB.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
.tile R3C38:PLC2
arc: E1_H02E0101 W1_H02E0101
arc: E1_H02E0501 S1_V02N0501
arc: H00L0000 N1_V02S0001
arc: H00R0000 V02S0601
arc: H00R0100 H02W0701
arc: N1_V02N0201 H02W0201
arc: S1_V02S0201 E1_H01W0000
arc: S1_V02S0401 E1_H01W0000
arc: S1_V02S0601 W1_H02E0601
arc: V00B0100 H02W0501
arc: V00T0100 V02N0701
arc: W1_H02W0001 S1_V02N0001
arc: W1_H02W0101 S1_V02N0101
arc: W1_H02W0401 S1_V02N0401
arc: A2 E1_H01E0001
arc: A3 E1_H01E0001
arc: A5 V02N0101
arc: B2 S1_V02N0301
arc: B3 S1_V02N0301
arc: B4 H02W0101
arc: C2 H02E0601
arc: C3 H00L0000
arc: C4 Q4
arc: C5 H02W0601
arc: CE0 H00R0000
arc: CE1 H00R0100
arc: CE2 S1_V02N0601
arc: CE3 V02S0601
arc: CLK0 G_HPBX0000
arc: D2 N1_V02S0001
arc: D3 V01S0100
arc: D4 V02N0401
arc: D5 H00L0100
arc: E1_H01E0001 Q6
arc: F2 F5B_SLICE
arc: F4 F4_SLICE
arc: F5 F5_SLICE
arc: H00L0100 Q3
arc: H01W0000 Q4
arc: M0 V00T0100
arc: M2 V00B0000
arc: M3 E1_H02W0201
arc: M4 V00B0100
arc: M6 V00B0100
arc: M7 E1_H02W0201
arc: MUXCLK0 CLK0
arc: MUXCLK1 CLK0
arc: MUXCLK2 CLK0
arc: MUXCLK3 CLK0
arc: N1_V01N0001 Q7
arc: N1_V01N0101 Q3
arc: N1_V02N0001 Q0
arc: N1_V02N0701 F5
arc: V00B0000 F4
arc: V01S0100 Q4
arc: W1_H02W0201 F2
word: SLICEC.K1.INIT 1111010110100000
word: SLICEA.K0.INIT 0000000000000000
word: SLICEA.K1.INIT 0000000000001110
word: SLICEC.K0.INIT 1100110011110000
word: SLICEB.K0.INIT 1011100000000000
word: SLICEB.K1.INIT 1011111110001111
enum: SLICEC.MODE LOGIC
enum: SLICEC.CCU2.INJECT1_1 _NONE_
enum: SLICEC.B1MUX 1
enum: SLICEA.MODE CCU2
enum: SLICEA.CCU2.INJECT1_0 NO
enum: SLICEA.A0MUX 1
enum: SLICEA.B0MUX 1
enum: SLICEA.C0MUX 1
enum: SLICEA.D0MUX 1
enum: SLICEA.MODE CCU2
enum: SLICEA.CCU2.INJECT1_1 NO
enum: SLICEA.A1MUX 1
enum: SLICEA.B1MUX 1
enum: SLICEA.C1MUX 1
enum: SLICEA.D1MUX 1
enum: SLICEC.MODE LOGIC
enum: SLICEC.CCU2.INJECT1_0 _NONE_
enum: SLICEC.A0MUX 1
enum: SLICEB.MODE LOGIC
enum: SLICEB.CCU2.INJECT1_0 _NONE_
enum: SLICEB.MODE LOGIC
enum: SLICEB.CCU2.INJECT1_1 _NONE_
enum: SLICED.GSR DISABLED
enum: SLICED.REG0.SD 0
enum: SLICED.REG0.REGSET RESET
enum: SLICED.REG0.LSRMODE LSR
enum: SLICED.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEC.GSR DISABLED
enum: SLICEC.REG0.SD 0
enum: SLICEC.REG0.REGSET RESET
enum: SLICEC.REG0.LSRMODE LSR
enum: SLICEC.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEA.GSR DISABLED
enum: SLICEA.REG0.SD 0
enum: SLICEA.REG0.REGSET RESET
enum: SLICEA.REG0.LSRMODE LSR
enum: SLICEA.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICED.GSR DISABLED
enum: SLICED.REG1.SD 0
enum: SLICED.REG1.REGSET RESET
enum: SLICED.REG1.LSRMODE LSR
enum: SLICED.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEB.GSR DISABLED
enum: SLICEB.REG1.SD 0
enum: SLICEB.REG1.REGSET RESET
enum: SLICEB.REG1.LSRMODE LSR
enum: SLICEB.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
.tile R3C39:PLC2
arc: H00L0000 S1_V02N0001
arc: H00R0100 S1_V02N0701
arc: N1_V02N0001 H06E0003
arc: S1_V02S0201 H06E0103
arc: S1_V02S0701 H06E0203
arc: V00B0100 V02N0101
arc: W1_H02W0101 V01N0101
arc: W1_H02W0501 V01N0101
arc: W1_H02W0601 V01N0001
arc: W1_H02W0701 S1_V02N0701
arc: A1 H02E0501
arc: B0 S1_V02N0101
arc: B1 Q1
arc: C0 H00L0000
arc: CE0 H02E0101
arc: CE1 H00R0100
arc: CLK0 G_HPBX0000
arc: D0 Q0
arc: D1 S1_V02N0201
arc: F0 F0_SLICE
arc: F1 F1_SLICE
arc: H01W0000 Q1
arc: M2 V00B0100
arc: MUXCLK0 CLK0
arc: MUXCLK1 CLK0
arc: N1_V02N0201 Q0
arc: S1_V02S0301 Q1
arc: W1_H02W0201 Q2
word: SLICEA.K0.INIT 1111110000110000
word: SLICEA.K1.INIT 1100110010101010
enum: SLICEA.MODE LOGIC
enum: SLICEA.CCU2.INJECT1_0 _NONE_
enum: SLICEA.A0MUX 1
enum: SLICEA.MODE LOGIC
enum: SLICEA.CCU2.INJECT1_1 _NONE_
enum: SLICEA.C1MUX 1
enum: SLICEA.GSR DISABLED
enum: SLICEA.REG1.SD 1
enum: SLICEA.REG1.REGSET RESET
enum: SLICEA.REG1.LSRMODE LSR
enum: SLICEA.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEA.GSR DISABLED
enum: SLICEA.REG0.SD 1
enum: SLICEA.REG0.REGSET RESET
enum: SLICEA.REG0.LSRMODE LSR
enum: SLICEA.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEB.GSR DISABLED
enum: SLICEB.REG0.SD 0
enum: SLICEB.REG0.REGSET RESET
enum: SLICEB.REG0.LSRMODE LSR
enum: SLICEB.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
.tile R3C40:PLC2
arc: N1_V02N0001 H02W0001
arc: W1_H02W0201 V02N0201
.tile R3C41:PLC2
arc: W1_H02W0001 S3_V06N0003
.tile R4C30:PLC2
arc: E1_H02E0301 V02S0301
.tile R4C31:PLC2
arc: E1_H02E0001 S1_V02N0001
arc: E1_H02E0301 V01N0101
arc: H00L0000 N1_V02S0001
arc: H00R0100 V02N0501
arc: N1_V02N0301 H02W0301
arc: S1_V02S0301 H02W0301
arc: A1 H00L0100
arc: A2 V00B0000
arc: A3 V00B0000
arc: B1 V02N0301
arc: B2 H01W0100
arc: B3 Q3
arc: C1 V02N0601
arc: C2 E1_H01W0000
arc: C3 E1_H01W0000
arc: CE0 E1_H02W0101
arc: CE1 S1_V02N0201
arc: CLK0 G_HPBX0000
arc: D1 H02W0001
arc: D2 V02N0001
arc: D3 V02N0001
arc: D4 V02S0601
arc: E1_H01E0101 F4
arc: F1 F1_SLICE
arc: F2 F5B_SLICE
arc: F4 F4_SLICE
arc: H00L0100 Q1
arc: H01W0100 Q3
arc: LSR0 H02W0301
arc: LSR1 H02W0301
arc: M1 H00R0100
arc: M2 V00T0100
arc: M3 H00L0000
arc: M6 V00T0000
arc: MUXCLK0 CLK0
arc: MUXCLK1 CLK0
arc: MUXCLK3 CLK0
arc: MUXLSR0 LSR0
arc: MUXLSR1 LSR0
arc: MUXLSR3 LSR1
arc: N1_V02N0601 Q6
arc: V00B0000 Q6
arc: V00T0000 F2
arc: V00T0100 F1
word: SLICEC.K0.INIT 0000000011111111
word: SLICEA.K1.INIT 0110111101100000
word: SLICEB.K1.INIT 1001011001101001
word: SLICEB.K0.INIT 0110100110010110
enum: SLICEA.GSR DISABLED
enum: SLICEA.REG1.SD 0
enum: SLICEA.REG1.REGSET RESET
enum: SLICEA.REG1.LSRMODE LSR
enum: SLICEA.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEC.MODE LOGIC
enum: SLICEC.CCU2.INJECT1_0 _NONE_
enum: SLICEC.A0MUX 1
enum: SLICEC.B0MUX 1
enum: SLICEC.C0MUX 1
enum: SLICEB.GSR DISABLED
enum: SLICEB.REG1.SD 0
enum: SLICEB.REG1.REGSET RESET
enum: SLICEB.REG1.LSRMODE LSR
enum: SLICEB.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEA.MODE LOGIC
enum: SLICEA.CCU2.INJECT1_1 _NONE_
enum: SLICEB.MODE LOGIC
enum: SLICEB.CCU2.INJECT1_1 _NONE_
enum: SLICEB.MODE LOGIC
enum: SLICEB.CCU2.INJECT1_0 _NONE_
enum: SLICED.GSR DISABLED
enum: SLICED.REG0.SD 0
enum: SLICED.REG0.REGSET RESET
enum: SLICED.REG0.LSRMODE LSR
enum: SLICED.CEMUX 1
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
.tile R4C32:PLC2
arc: E1_H02E0601 W1_H02E0301
arc: E1_H02E0701 E3_H06W0203
arc: E3_H06E0303 H01E0101
arc: H00L0000 E1_H02W0201
arc: H00L0100 S1_V02N0101
arc: H00R0000 V02S0601
arc: N1_V02N0101 H01E0101
arc: N1_V02N0201 V01N0001
arc: N1_V02N0601 S1_V02N0601
arc: N1_V02N0701 H06W0203
arc: S1_V02S0701 E1_H01W0100
arc: S3_V06S0203 E1_H01W0000
arc: V00B0000 V02S0201
arc: V00T0000 S1_V02N0401
arc: W1_H02W0001 S1_V02N0001
arc: W1_H02W0301 V06S0003
arc: A0 V02S0701
arc: A3 V02N0501
arc: A4 V00B0000
arc: A5 V02N0301
arc: A6 E1_H01W0000
arc: A7 N1_V01S0100
arc: B2 H02E0301
arc: B3 H00R0000
arc: B4 S1_V02N0501
arc: B5 H00L0000
arc: B6 N1_V01S0000
arc: B7 V02N0701
arc: CE3 H00L0100
arc: CLK0 G_HPBX0000
arc: H01W0000 Q7
arc: LSR1 V00T0000
arc: M7 H02W0201
arc: MUXCLK3 CLK0
arc: MUXLSR3 LSR1
word: SLICEA.K0.INIT 0000000000001010
word: SLICEA.K1.INIT 1111111111111111
word: SLICEB.K0.INIT 1001100110011100
word: SLICEB.K1.INIT 1001100110011100
word: SLICEC.K0.INIT 1001100110011010
word: SLICEC.K1.INIT 1001100110011010
word: SLICED.K0.INIT 1001100110011100
word: SLICED.K1.INIT 1001100110011010
enum: SLICEA.MODE CCU2
enum: SLICEA.CCU2.INJECT1_0 NO
enum: SLICEA.B0MUX 1
enum: SLICEA.C0MUX 1
enum: SLICEA.D0MUX 1
enum: SLICEA.MODE CCU2
enum: SLICEA.CCU2.INJECT1_1 YES
enum: SLICEA.A1MUX 1
enum: SLICEA.B1MUX 1
enum: SLICEA.C1MUX 1
enum: SLICEA.D1MUX 1
enum: SLICEB.MODE CCU2
enum: SLICEB.CCU2.INJECT1_0 NO
enum: SLICEB.A0MUX 1
enum: SLICEB.C0MUX 1
enum: SLICEB.D0MUX 1
enum: SLICEB.MODE CCU2
enum: SLICEB.CCU2.INJECT1_1 NO
enum: SLICEB.C1MUX 1
enum: SLICEB.D1MUX 1
enum: SLICEC.MODE CCU2
enum: SLICEC.CCU2.INJECT1_0 NO
enum: SLICEC.C0MUX 1
enum: SLICEC.D0MUX 1
enum: SLICEC.MODE CCU2
enum: SLICEC.CCU2.INJECT1_1 NO
enum: SLICEC.C1MUX 1
enum: SLICEC.D1MUX 1
enum: SLICED.MODE CCU2
enum: SLICED.CCU2.INJECT1_0 NO
enum: SLICED.C0MUX 1
enum: SLICED.D0MUX 1
enum: SLICED.MODE CCU2
enum: SLICED.CCU2.INJECT1_1 NO
enum: SLICED.C1MUX 1
enum: SLICED.D1MUX 1
enum: SLICED.GSR DISABLED
enum: SLICED.REG1.SD 0
enum: SLICED.REG1.REGSET RESET
enum: SLICED.REG1.LSRMODE LSR
enum: SLICED.CEMUX CE
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
.tile R4C33:PLC2
arc: E1_H02E0101 W1_H02E0001
arc: E1_H02E0201 V01N0001
arc: E1_H02E0501 V01N0101
arc: E1_H02E0701 S1_V02N0701
arc: H00R0000 V02N0601
arc: N1_V02N0001 H06W0003
arc: N1_V02N0101 H06W0103
arc: N1_V02N0301 S1_V02N0201
arc: N1_V02N0501 H06W0303
arc: N1_V02N0701 S1_V02N0601
arc: S1_V02S0101 H06W0103
arc: S1_V02S0301 H06W0003
arc: S1_V02S0501 H06W0303
arc: S1_V02S0701 H06W0203
arc: V00B0000 N1_V02S0001
arc: V00T0000 E1_H02W0001
arc: W1_H02W0101 S1_V02N0101
arc: W1_H02W0201 V02S0201
arc: A0 V02S0501
arc: A1 S1_V02N0501
arc: A2 E1_H02W0701
arc: A3 H02W0501
arc: A4 E1_H01W0000
arc: A5 E1_H02W0501
arc: A6 H00R0000
arc: A7 H02E0701
arc: B0 V00T0000
arc: B1 V02N0301
arc: B2 E1_H02W0101
arc: B3 E1_H01W0100
arc: B4 H02W0101
arc: B5 V02S0701
arc: B6 V02N0501
arc: B7 H02W0301
arc: CE1 V02N0201
arc: CLK0 G_HPBX0000
arc: E1_H01E0001 Q2
arc: E1_H02E0001 Q2
arc: H01W0000 Q2
arc: H01W0100 Q2
arc: M2 V00B0000
arc: MUXCLK1 CLK0
arc: N1_V02N0201 Q2
arc: V01S0100 Q2
word: SLICEA.K0.INIT 1001100110011100
word: SLICEA.K1.INIT 1001100110011100
word: SLICEB.K0.INIT 1001100110011100
word: SLICEB.K1.INIT 1001100110011010
word: SLICEC.K0.INIT 1001100110011100
word: SLICEC.K1.INIT 1001100110011010
word: SLICED.K0.INIT 1001100110011010
word: SLICED.K1.INIT 1001100110011100
enum: SLICEB.GSR DISABLED
enum: SLICEB.REG0.SD 0
enum: SLICEB.REG0.REGSET RESET
enum: SLICEB.REG0.LSRMODE LSR
enum: SLICEB.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEA.MODE CCU2
enum: SLICEA.CCU2.INJECT1_0 NO
enum: SLICEA.C0MUX 1
enum: SLICEA.D0MUX 1
enum: SLICEA.MODE CCU2
enum: SLICEA.CCU2.INJECT1_1 NO
enum: SLICEA.C1MUX 1
enum: SLICEA.D1MUX 1
enum: SLICEB.MODE CCU2
enum: SLICEB.CCU2.INJECT1_0 NO
enum: SLICEB.C0MUX 1
enum: SLICEB.D0MUX 1
enum: SLICEB.MODE CCU2
enum: SLICEB.CCU2.INJECT1_1 NO
enum: SLICEB.C1MUX 1
enum: SLICEB.D1MUX 1
enum: SLICEC.MODE CCU2
enum: SLICEC.CCU2.INJECT1_0 NO
enum: SLICEC.C0MUX 1
enum: SLICEC.D0MUX 1
enum: SLICEC.MODE CCU2
enum: SLICEC.CCU2.INJECT1_1 NO
enum: SLICEC.C1MUX 1
enum: SLICEC.D1MUX 1
enum: SLICED.MODE CCU2
enum: SLICED.CCU2.INJECT1_0 NO
enum: SLICED.C0MUX 1
enum: SLICED.D0MUX 1
enum: SLICED.MODE CCU2
enum: SLICED.CCU2.INJECT1_1 NO
enum: SLICED.C1MUX 1
enum: SLICED.D1MUX 1
.tile R4C34:PLC2
arc: E1_H02E0201 V06S0103
arc: H00L0000 V02S0001
arc: H00L0100 V02S0101
arc: H00R0000 E1_H02W0601
arc: N1_V02N0101 S1_V02N0101
arc: N1_V02N0201 S1_V02N0701
arc: N1_V02N0701 W1_H02E0701
arc: S1_V02S0401 H01E0001
arc: V00B0000 V02N0201
arc: V00B0100 V02N0101
arc: V00T0000 V02N0601
arc: V00T0100 H02E0101
arc: W1_H02W0101 E1_H02W0101
arc: W1_H02W0301 E1_H02W0201
arc: W1_H02W0501 V01N0101
arc: A0 V02N0501
arc: A1 H00R0000
arc: A4 V00B0000
arc: A5 V00B0000
arc: A6 H02E0701
arc: A7 H02E0701
arc: B0 E1_H02W0301
arc: B1 V02N0301
arc: B4 S1_V02N0501
arc: B5 S1_V02N0501
arc: B6 N1_V01S0000
arc: B7 H02E0101
arc: C4 V00T0100
arc: C5 V00T0100
arc: C6 V00T0100
arc: C7 V02N0201
arc: CE0 S1_V02N0201
arc: CE1 S1_V02N0201
arc: CE2 V02S0601
arc: CE3 V02S0601
arc: CLK0 G_HPBX0000
arc: D4 H00R0100
arc: D5 H00R0100
arc: D6 V00B0000
arc: D7 H00L0100
arc: E1_H01E0001 F2
arc: E1_H01E0101 Q2
arc: E1_H02E0001 Q0
arc: E1_H02E0101 Q3
arc: E1_H02E0301 Q3
arc: E1_H02E0401 F4
arc: E1_H02E0601 F6
arc: F2 F2_SLICE
arc: F4 F5C_SLICE
arc: F6 F5D_SLICE
arc: H00R0100 Q7
arc: H01W0000 Q3
arc: H01W0100 Q0
arc: M0 V00T0000
arc: M2 W1_H02E0601
arc: M3 H02W0201
arc: M4 V00B0100
arc: M5 H00L0000
arc: M6 V00B0100
arc: M7 E1_H01W0000
arc: MUXCLK0 CLK0
arc: MUXCLK1 CLK0
arc: MUXCLK2 CLK0
arc: MUXCLK3 CLK0
arc: N1_V01N0001 Q0
arc: N1_V01N0101 Q2
arc: N1_V02N0301 Q3
arc: S1_V02S0001 Q0
arc: S1_V02S0201 Q2
arc: S1_V02S0501 Q5
arc: S1_V02S0701 Q7
arc: V01S0000 Q2
arc: V01S0100 Q3
arc: W1_H02W0201 Q2
word: SLICEC.K0.INIT 1100110111001000
word: SLICEC.K1.INIT 1111110110001000
word: SLICED.K0.INIT 1010101010101100
word: SLICED.K1.INIT 1110111110100000
word: SLICEA.K0.INIT 1001100110011010
word: SLICEA.K1.INIT 1001100110011100
word: SLICEB.K0.INIT 0000000000000000
word: SLICEB.K1.INIT 0000000000001110
enum: SLICEC.MODE LOGIC
enum: SLICEC.CCU2.INJECT1_0 _NONE_
enum: SLICEC.MODE LOGIC
enum: SLICEC.CCU2.INJECT1_1 _NONE_
enum: SLICED.MODE LOGIC
enum: SLICED.CCU2.INJECT1_0 _NONE_
enum: SLICED.MODE LOGIC
enum: SLICED.CCU2.INJECT1_1 _NONE_
enum: SLICEB.GSR DISABLED
enum: SLICEB.REG0.SD 0
enum: SLICEB.REG0.REGSET RESET
enum: SLICEB.REG0.LSRMODE LSR
enum: SLICEB.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEC.GSR DISABLED
enum: SLICEC.REG1.SD 0
enum: SLICEC.REG1.REGSET RESET
enum: SLICEC.REG1.LSRMODE LSR
enum: SLICEC.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICED.GSR DISABLED
enum: SLICED.REG1.SD 0
enum: SLICED.REG1.REGSET RESET
enum: SLICED.REG1.LSRMODE LSR
enum: SLICED.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEB.GSR DISABLED
enum: SLICEB.REG1.SD 0
enum: SLICEB.REG1.REGSET RESET
enum: SLICEB.REG1.LSRMODE LSR
enum: SLICEB.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEA.GSR DISABLED
enum: SLICEA.REG0.SD 0
enum: SLICEA.REG0.REGSET RESET
enum: SLICEA.REG0.LSRMODE LSR
enum: SLICEA.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEA.MODE CCU2
enum: SLICEA.CCU2.INJECT1_0 NO
enum: SLICEA.C0MUX 1
enum: SLICEA.D0MUX 1
enum: SLICEA.MODE CCU2
enum: SLICEA.CCU2.INJECT1_1 NO
enum: SLICEA.C1MUX 1
enum: SLICEA.D1MUX 1
enum: SLICEB.MODE CCU2
enum: SLICEB.CCU2.INJECT1_0 NO
enum: SLICEB.A0MUX 1
enum: SLICEB.B0MUX 1
enum: SLICEB.C0MUX 1
enum: SLICEB.D0MUX 1
enum: SLICEB.MODE CCU2
enum: SLICEB.CCU2.INJECT1_1 NO
enum: SLICEB.A1MUX 1
enum: SLICEB.B1MUX 1
enum: SLICEB.C1MUX 1
enum: SLICEB.D1MUX 1
.tile R4C35:PLC2
arc: E1_H02E0001 W1_H02E0501
arc: E1_H02E0101 W1_H02E0001
arc: E1_H02E0201 W1_H02E0201
arc: E1_H02E0301 V06N0003
arc: E1_H02E0501 V06N0303
arc: E1_H02E0601 V06N0303
arc: E1_H02E0701 H01E0101
arc: E3_H06E0003 H01E0001
arc: H00L0000 S1_V02N0201
arc: H00R0000 E1_H02W0601
arc: H00R0100 H02W0701
arc: N1_V02N0001 W1_H02E0001
arc: N1_V02N0101 H06W0103
arc: N1_V02N0301 H06W0003
arc: N1_V02N0501 H06E0303
arc: N1_V02N0701 H01E0101
arc: S1_V02S0201 H06W0103
arc: S1_V02S0301 H02E0301
arc: S1_V02S0401 H06W0203
arc: V00B0100 E1_H02W0501
arc: V00T0100 V02N0501
arc: W1_H02W0001 E1_H01W0000
arc: W1_H02W0101 E1_H02W0001
arc: W1_H02W0201 E1_H02W0701
arc: W1_H02W0501 E1_H01W0100
arc: W1_H02W0701 V01N0101
arc: W3_H06W0203 E1_H01W0000
arc: A0 H02W0501
arc: A1 H02W0701
arc: A2 H02W0701
arc: A3 H02W0701
arc: A4 E1_H02W0501
arc: A5 H02W0501
arc: A6 E1_H02W0501
arc: A7 E1_H02W0501
arc: B0 E1_H02W0301
arc: B1 V02N0301
arc: B2 E1_H02W0101
arc: B3 E1_H02W0101
arc: B4 V02N0701
arc: B5 N1_V01S0000
arc: B6 V02N0701
arc: B7 V02N0701
arc: C0 S1_V02N0601
arc: C2 S1_V02N0601
arc: C3 S1_V02N0601
arc: C4 V02S0001
arc: C5 V00B0100
arc: C6 V02S0201
arc: C7 V02S0001
arc: CE3 H00L0100
arc: CLK0 G_HPBX0000
arc: D0 V02S0001
arc: D1 V00B0100
arc: D2 V02S0201
arc: D3 N1_V01S0000
arc: D4 H00R0100
arc: D5 H02W0001
arc: D6 H00R0100
arc: D7 H00R0100
arc: F0 F5A_SLICE
arc: F1 FXA_SLICE
arc: F2 F5B_SLICE
arc: F3 FXB_SLICE
arc: F4 F5C_SLICE
arc: F5 FXC_SLICE
arc: F6 F5D_SLICE
arc: H00L0100 F3
arc: H01W0000 Q7
arc: M0 V00T0100
arc: M1 H00L0000
arc: M2 V00T0100
arc: M3 E1_H02W0201
arc: M4 V00T0100
arc: M5 H00L0000
arc: M6 V00T0100
arc: M7 H00R0000
arc: MUXCLK3 CLK0
arc: S1_V02S0101 F3
arc: V01S0000 F3
word: SLICEA.K0.INIT 0000001000100010
word: SLICEA.K1.INIT 0000000000100010
word: SLICEB.K0.INIT 0000001000100010
word: SLICEB.K1.INIT 0000001000100010
word: SLICEC.K0.INIT 0001010100000000
word: SLICEC.K1.INIT 0000001000001010
word: SLICED.K0.INIT 0001010100000000
word: SLICED.K1.INIT 0001010100000000
enum: SLICEA.MODE LOGIC
enum: SLICEA.CCU2.INJECT1_0 _NONE_
enum: SLICEA.MODE LOGIC
enum: SLICEA.CCU2.INJECT1_1 _NONE_
enum: SLICEA.C1MUX 1
enum: SLICEB.MODE LOGIC
enum: SLICEB.CCU2.INJECT1_0 _NONE_
enum: SLICEB.MODE LOGIC
enum: SLICEB.CCU2.INJECT1_1 _NONE_
enum: SLICEC.MODE LOGIC
enum: SLICEC.CCU2.INJECT1_0 _NONE_
enum: SLICEC.MODE LOGIC
enum: SLICEC.CCU2.INJECT1_1 _NONE_
enum: SLICED.MODE LOGIC
enum: SLICED.CCU2.INJECT1_0 _NONE_
enum: SLICED.MODE LOGIC
enum: SLICED.CCU2.INJECT1_1 _NONE_
enum: SLICED.GSR DISABLED
enum: SLICED.REG1.SD 0
enum: SLICED.REG1.REGSET RESET
enum: SLICED.REG1.LSRMODE LSR
enum: SLICED.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
.tile R4C36:PLC2
arc: E1_H02E0101 N1_V02S0101
arc: E1_H02E0301 W1_H02E0201
arc: E1_H02E0501 V02S0501
arc: E1_H02E0701 W1_H02E0601
arc: E3_H06E0003 V06N0003
arc: H00L0100 V02N0101
arc: H00R0000 W1_H02E0401
arc: H00R0100 H02E0501
arc: N1_V02N0201 N1_V01S0000
arc: N1_V02N0401 E1_H01W0000
arc: N1_V02N0601 S1_V02N0301
arc: V00B0000 E1_H02W0601
arc: V00B0100 S1_V02N0101
arc: V00T0000 W1_H02E0201
arc: W1_H02W0001 V06N0003
arc: W1_H02W0301 E1_H02W0201
arc: W1_H02W0601 E1_H02W0301
arc: W3_H06W0303 E1_H01W0100
arc: A3 F5
arc: A4 S1_V02N0101
arc: A5 V00B0000
arc: A6 N1_V01S0100
arc: A7 E1_H02W0501
arc: B1 S1_V02N0101
arc: B2 S1_V02N0101
arc: B5 H02E0301
arc: B6 W1_H02E0101
arc: B7 E1_H02W0101
arc: C0 V02N0601
arc: C3 S1_V02N0601
arc: C4 V02N0001
arc: C5 H02W0401
arc: C7 V02N0201
arc: CE0 H00L0100
arc: CE1 H00L0100
arc: CE2 H00L0100
arc: CE3 H00R0100
arc: CLK0 G_HPBX0000
arc: D0 V00B0100
arc: D1 H02E0201
arc: D2 H02E0001
arc: D3 E1_H02W0001
arc: D5 S1_V02N0401
arc: D6 E1_H02W0201
arc: D7 W1_H02E0001
arc: E1_H01E0101 F6
arc: F0 F0_SLICE
arc: F1 F1_SLICE
arc: F2 F2_SLICE
arc: F3 F3_SLICE
arc: F4 F4_SLICE
arc: F5 F5_SLICE
arc: F6 F6_SLICE
arc: F7 F7_SLICE
arc: H01W0000 Q4
arc: H01W0100 Q0
arc: LSR0 V00T0000
arc: LSR1 V00T0000
arc: M7 H00R0000
arc: MUXCLK0 CLK0
arc: MUXCLK1 CLK0
arc: MUXCLK2 CLK0
arc: MUXCLK3 CLK0
arc: MUXLSR0 LSR0
arc: MUXLSR1 LSR1
arc: MUXLSR2 LSR1
arc: MUXLSR3 LSR0
arc: N1_V01N0001 Q7
arc: N1_V02N0001 Q2
arc: S1_V02S0101 F3
arc: S1_V02S0401 F6
arc: S1_V02S0501 F7
arc: V01S0000 Q2
arc: W1_H02W0101 Q1
arc: W1_H02W0201 Q2
arc: W1_H02W0501 F5
arc: W1_H02W0701 F5
arc: W3_H06W0003 Q0
arc: W3_H06W0103 Q1
arc: W3_H06W0203 Q4
word: SLICEC.K0.INIT 1010000010100000
word: SLICEB.K0.INIT 1100110000000000
word: SLICEA.K1.INIT 1100110000000000
word: SLICEA.K0.INIT 1111000000000000
word: SLICEC.K1.INIT 1100000011001000
word: SLICED.K0.INIT 0000000000010001
word: SLICED.K1.INIT 0000000000000001
word: SLICEB.K1.INIT 0000000000001010
enum: SLICEC.MODE LOGIC
enum: SLICEC.CCU2.INJECT1_0 _NONE_
enum: SLICEC.B0MUX 1
enum: SLICEC.D0MUX 1
enum: SLICED.GSR DISABLED
enum: SLICED.REG1.SD 0
enum: SLICED.REG1.REGSET RESET
enum: SLICED.REG1.LSRMODE LSR
enum: SLICED.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEB.MODE LOGIC
enum: SLICEB.CCU2.INJECT1_0 _NONE_
enum: SLICEB.A0MUX 1
enum: SLICEB.C0MUX 1
enum: SLICEA.MODE LOGIC
enum: SLICEA.CCU2.INJECT1_1 _NONE_
enum: SLICEA.A1MUX 1
enum: SLICEA.C1MUX 1
enum: SLICEA.GSR DISABLED
enum: SLICEA.REG1.SD 1
enum: SLICEA.REG1.REGSET RESET
enum: SLICEA.REG1.LSRMODE LSR
enum: SLICEA.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEC.GSR DISABLED
enum: SLICEC.REG0.SD 1
enum: SLICEC.REG0.REGSET RESET
enum: SLICEC.REG0.LSRMODE LSR
enum: SLICEC.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEB.GSR DISABLED
enum: SLICEB.REG0.SD 1
enum: SLICEB.REG0.REGSET RESET
enum: SLICEB.REG0.LSRMODE LSR
enum: SLICEB.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEA.GSR DISABLED
enum: SLICEA.REG0.SD 1
enum: SLICEA.REG0.REGSET RESET
enum: SLICEA.REG0.LSRMODE LSR
enum: SLICEA.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEA.MODE LOGIC
enum: SLICEA.CCU2.INJECT1_0 _NONE_
enum: SLICEA.A0MUX 1
enum: SLICEA.B0MUX 1
enum: SLICEC.MODE LOGIC
enum: SLICEC.CCU2.INJECT1_1 _NONE_
enum: SLICED.MODE LOGIC
enum: SLICED.CCU2.INJECT1_0 _NONE_
enum: SLICED.C0MUX 1
enum: SLICED.MODE LOGIC
enum: SLICED.CCU2.INJECT1_1 _NONE_
enum: SLICEB.MODE LOGIC
enum: SLICEB.CCU2.INJECT1_1 _NONE_
enum: SLICEB.B1MUX 1
.tile R4C37:PLC2
arc: E1_H02E0101 S1_V02N0101
arc: E1_H02E0601 V02N0601
arc: H00L0100 V02N0301
arc: H00R0000 V02N0401
arc: H00R0100 H02E0701
arc: N1_V02N0001 N1_V01S0000
arc: N1_V02N0101 W1_H02E0101
arc: N1_V02N0201 S1_V02N0701
arc: N1_V02N0501 S1_V02N0501
arc: N1_V02N0601 W1_H02E0601
arc: S1_V02S0101 H01E0101
arc: S1_V02S0301 E1_H01W0100
arc: S1_V02S0401 E1_H01W0000
arc: V00B0100 H02E0501
arc: V00T0000 V02N0601
arc: W1_H02W0101 V01N0101
arc: W1_H02W0201 V01N0001
arc: W1_H02W0301 V01N0101
arc: W1_H02W0401 V06N0203
arc: W1_H02W0501 V01N0101
arc: W1_H02W0701 V02N0701
arc: A4 W1_H02E0701
arc: A5 W1_H02E0701
arc: B7 V00B0000
arc: C0 V02N0601
arc: C4 V02S0001
arc: C5 V02N0001
arc: C7 V00T0100
arc: CE0 H00L0100
arc: CE1 H00R0000
arc: CE2 E1_H02W0101
arc: CE3 H02E0101
arc: CLK0 G_HPBX0000
arc: D0 V02N0201
arc: D4 H02W0001
arc: D5 H02W0001
arc: D7 S1_V02N0601
arc: E1_H01E0001 F7
arc: F0 F0_SLICE
arc: F4 F5C_SLICE
arc: F7 F7_SLICE
arc: H01W0000 Q5
arc: H01W0100 Q0
arc: LSR0 H02E0301
arc: LSR1 H02E0301
arc: M3 H00R0100
arc: M4 V00T0000
arc: M5 E1_H02W0001
arc: M6 V00B0100
arc: MUXCLK0 CLK0
arc: MUXCLK1 CLK0
arc: MUXCLK2 CLK0
arc: MUXCLK3 CLK0
arc: MUXLSR0 LSR1
arc: MUXLSR1 LSR1
arc: MUXLSR2 LSR0
arc: MUXLSR3 LSR1
arc: V00B0000 Q6
arc: V00T0100 Q3
arc: W1_H02W0001 Q0
arc: W1_H02W0601 F4
word: SLICEC.K0.INIT 0101010111110000
word: SLICEC.K1.INIT 0101111101011010
word: SLICED.K1.INIT 1100110011110000
word: SLICEA.K0.INIT 1111000000000000
enum: SLICEB.GSR DISABLED
enum: SLICEB.REG1.SD 0
enum: SLICEB.REG1.REGSET RESET
enum: SLICEB.REG1.LSRMODE LSR
enum: SLICEB.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICED.GSR DISABLED
enum: SLICED.REG0.SD 0
enum: SLICED.REG0.REGSET RESET
enum: SLICED.REG0.LSRMODE LSR
enum: SLICED.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEC.GSR DISABLED
enum: SLICEC.REG1.SD 0
enum: SLICEC.REG1.REGSET RESET
enum: SLICEC.REG1.LSRMODE LSR
enum: SLICEC.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEC.MODE LOGIC
enum: SLICEC.CCU2.INJECT1_0 _NONE_
enum: SLICEC.B0MUX 1
enum: SLICEC.MODE LOGIC
enum: SLICEC.CCU2.INJECT1_1 _NONE_
enum: SLICEC.B1MUX 1
enum: SLICED.MODE LOGIC
enum: SLICED.CCU2.INJECT1_1 _NONE_
enum: SLICED.A1MUX 1
enum: SLICEA.MODE LOGIC
enum: SLICEA.CCU2.INJECT1_0 _NONE_
enum: SLICEA.A0MUX 1
enum: SLICEA.B0MUX 1
enum: SLICEA.GSR DISABLED
enum: SLICEA.REG0.SD 1
enum: SLICEA.REG0.REGSET RESET
enum: SLICEA.REG0.LSRMODE LSR
enum: SLICEA.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
.tile R4C38:PLC2
arc: H00L0000 V02S0201
arc: H00R0000 V02N0601
arc: H00R0100 H02W0501
arc: N1_V02N0101 S1_V02N0101
arc: N1_V02N0201 S1_V02N0201
arc: N1_V02N0301 S1_V02N0201
arc: N1_V02N0401 S1_V02N0101
arc: N1_V02N0601 H01E0001
arc: N1_V02N0701 E1_H01W0100
arc: S1_V02S0001 H06E0003
arc: V00B0000 H02W0601
arc: V00T0100 V02N0501
arc: W1_H02W0001 V02N0001
arc: W1_H02W0601 S1_V02N0601
arc: A0 V02N0701
arc: A1 V02N0701
arc: A5 S1_V02N0101
arc: B0 V00B0000
arc: B1 V00B0000
arc: B4 V01S0000
arc: C0 H02E0601
arc: C1 H02E0601
arc: C4 V02N0201
arc: C5 E1_H01E0101
arc: CE0 H00R0000
arc: CE1 H02E0101
arc: CE2 V02S0601
arc: CE3 H02E0101
arc: CLK0 G_HPBX0000
arc: D0 V01S0100
arc: D1 V01S0100
arc: D4 H02W0201
arc: D5 V02S0401
arc: E1_H01E0101 Q1
arc: E1_H02E0401 Q4
arc: F0 F5A_SLICE
arc: F4 F4_SLICE
arc: F5 F5_SLICE
arc: H01W0000 Q3
arc: H01W0100 Q2
arc: M0 V00B0100
arc: M1 H00L0000
arc: M2 V00T0100
arc: M3 H00R0100
arc: M7 E1_H02W0201
arc: MUXCLK0 CLK0
arc: MUXCLK1 CLK0
arc: MUXCLK2 CLK0
arc: MUXCLK3 CLK0
arc: N1_V02N0001 F0
arc: V00B0100 F5
arc: V01S0000 Q4
arc: V01S0100 Q1
arc: W1_H02W0101 Q3
arc: W1_H02W0201 Q2
arc: W1_H02W0301 Q3
arc: W1_H02W0501 Q7
arc: W3_H06W0003 Q3
arc: W3_H06W0103 Q2
arc: W3_H06W0203 Q7
word: SLICEC.K1.INIT 1111101001010000
word: SLICEA.K0.INIT 1101000010000000
word: SLICEA.K1.INIT 1101111110001111
word: SLICEC.K0.INIT 1100110011110000
enum: SLICEB.GSR DISABLED
enum: SLICEB.REG1.SD 0
enum: SLICEB.REG1.REGSET RESET
enum: SLICEB.REG1.LSRMODE LSR
enum: SLICEB.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEB.GSR DISABLED
enum: SLICEB.REG0.SD 0
enum: SLICEB.REG0.REGSET RESET
enum: SLICEB.REG0.LSRMODE LSR
enum: SLICEB.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICED.GSR DISABLED
enum: SLICED.REG1.SD 0
enum: SLICED.REG1.REGSET RESET
enum: SLICED.REG1.LSRMODE LSR
enum: SLICED.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEC.MODE LOGIC
enum: SLICEC.CCU2.INJECT1_1 _NONE_
enum: SLICEC.B1MUX 1
enum: SLICEA.MODE LOGIC
enum: SLICEA.CCU2.INJECT1_0 _NONE_
enum: SLICEA.MODE LOGIC
enum: SLICEA.CCU2.INJECT1_1 _NONE_
enum: SLICEA.GSR DISABLED
enum: SLICEA.REG1.SD 0
enum: SLICEA.REG1.REGSET RESET
enum: SLICEA.REG1.LSRMODE LSR
enum: SLICEA.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEC.MODE LOGIC
enum: SLICEC.CCU2.INJECT1_0 _NONE_
enum: SLICEC.A0MUX 1
enum: SLICEC.GSR DISABLED
enum: SLICEC.REG0.SD 1
enum: SLICEC.REG0.REGSET RESET
enum: SLICEC.REG0.LSRMODE LSR
enum: SLICEC.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
.tile R4C39:PLC2
arc: H00L0000 V02N0001
arc: H00R0000 H02E0401
arc: H00R0100 V02S0701
arc: N1_V02N0301 H06E0003
arc: V00B0100 V02S0301
arc: W1_H02W0001 V01N0001
arc: W1_H02W0101 S1_V02N0101
arc: W1_H02W0201 V02N0201
arc: W1_H02W0501 V01N0101
arc: A0 E1_H01E0001
arc: A1 V02N0501
arc: B1 Q1
arc: B2 V02N0301
arc: C0 H00L0000
arc: C2 V02N0401
arc: CE0 H00R0100
arc: CE1 V02S0201
arc: CE2 V02N0601
arc: CE3 N1_V02S0601
arc: CLK0 G_HPBX0000
arc: D0 V02N0201
arc: D1 V02N0201
arc: D2 Q2
arc: E1_H01E0001 Q0
arc: F0 F0_SLICE
arc: F1 F1_SLICE
arc: F2 F2_SLICE
arc: H01W0100 Q1
arc: M5 H00R0000
arc: M6 V00B0100
arc: M7 H00R0000
arc: MUXCLK0 CLK0
arc: MUXCLK1 CLK0
arc: MUXCLK2 CLK0
arc: MUXCLK3 CLK0
arc: N1_V01N0001 Q0
arc: N1_V01N0101 Q2
arc: N1_V02N0101 Q1
arc: S1_V02S0501 Q7
arc: V01S0000 Q5
arc: V01S0100 Q5
arc: W1_H02W0601 Q6
word: SLICEB.K0.INIT 1111110000110000
word: SLICEA.K0.INIT 1010101011110000
word: SLICEA.K1.INIT 1100110010101010
enum: SLICEB.MODE LOGIC
enum: SLICEB.CCU2.INJECT1_0 _NONE_
enum: SLICEB.A0MUX 1
enum: SLICEB.GSR DISABLED
enum: SLICEB.REG0.SD 1
enum: SLICEB.REG0.REGSET RESET
enum: SLICEB.REG0.LSRMODE LSR
enum: SLICEB.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICED.GSR DISABLED
enum: SLICED.REG0.SD 0
enum: SLICED.REG0.REGSET RESET
enum: SLICED.REG0.LSRMODE LSR
enum: SLICED.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEA.MODE LOGIC
enum: SLICEA.CCU2.INJECT1_0 _NONE_
enum: SLICEA.B0MUX 1
enum: SLICED.GSR DISABLED
enum: SLICED.REG1.SD 0
enum: SLICED.REG1.REGSET RESET
enum: SLICED.REG1.LSRMODE LSR
enum: SLICED.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEC.GSR DISABLED
enum: SLICEC.REG1.SD 0
enum: SLICEC.REG1.REGSET RESET
enum: SLICEC.REG1.LSRMODE LSR
enum: SLICEC.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEA.MODE LOGIC
enum: SLICEA.CCU2.INJECT1_1 _NONE_
enum: SLICEA.C1MUX 1
enum: SLICEA.GSR DISABLED
enum: SLICEA.REG1.SD 1
enum: SLICEA.REG1.REGSET RESET
enum: SLICEA.REG1.LSRMODE LSR
enum: SLICEA.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEA.GSR DISABLED
enum: SLICEA.REG0.SD 1
enum: SLICEA.REG0.REGSET RESET
enum: SLICEA.REG0.LSRMODE LSR
enum: SLICEA.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
.tile R4C40:PLC2
arc: N1_V02N0201 H01E0001
arc: W1_H02W0201 V02N0201
.tile R4C41:PLC2
arc: N1_V02N0201 S1_V02N0201
.tile R5C30:PLC2
arc: E1_H02E0301 S1_V02N0301
arc: E1_H02E0501 V06S0303
arc: N1_V02N0001 E3_H06W0003
arc: N1_V02N0601 S1_V02N0301
arc: N3_V06N0003 S1_V02N0301
.tile R5C31:PLC2
arc: N1_V02N0001 E3_H06W0003
arc: N1_V02N0101 E3_H06W0103
arc: N1_V02N0301 E1_H01W0100
arc: N1_V02N0501 E1_H02W0501
arc: N1_V02N0601 H02W0601
arc: N1_V02N0701 E3_H06W0203
arc: V00B0100 V02S0301
arc: V00T0100 H02E0301
arc: A0 E1_H01E0001
arc: B2 H02E0301
arc: C2 E1_H01W0000
arc: CE0 E1_H02W0101
arc: CE1 E1_H02W0101
arc: CLK0 G_HPBX0000
arc: D0 V00T0100
arc: E1_H01E0001 Q0
arc: E1_H01E0101 Q2
arc: E3_H06E0003 Q0
arc: F0 F0_SLICE
arc: F2 F2_SLICE
arc: LSR0 V00B0100
arc: MUXCLK0 CLK0
arc: MUXCLK1 CLK0
arc: MUXLSR0 LSR0
arc: MUXLSR1 LSR0
arc: N1_V01N0101 Q0
arc: N1_V02N0201 Q0
arc: N3_V06N0103 Q2
word: SLICEB.K0.INIT 1100000011000000
word: SLICEA.K0.INIT 0101010100000000
enum: SLICEB.MODE LOGIC
enum: SLICEB.CCU2.INJECT1_0 _NONE_
enum: SLICEB.A0MUX 1
enum: SLICEB.D0MUX 1
enum: SLICEA.MODE LOGIC
enum: SLICEA.CCU2.INJECT1_0 _NONE_
enum: SLICEA.B0MUX 1
enum: SLICEA.C0MUX 1
enum: SLICEB.GSR DISABLED
enum: SLICEB.REG0.SD 1
enum: SLICEB.REG0.REGSET RESET
enum: SLICEB.REG0.LSRMODE LSR
enum: SLICEB.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEA.GSR DISABLED
enum: SLICEA.REG0.SD 1
enum: SLICEA.REG0.REGSET RESET
enum: SLICEA.REG0.LSRMODE LSR
enum: SLICEA.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: CLK0.CLKMUX CLK
.tile R5C32:PLC2
arc: E1_H02E0301 S1_V02N0301
arc: H00R0000 N1_V02S0401
arc: H00R0100 V02N0701
arc: N1_V02N0301 H01E0101
arc: N1_V02N0501 E1_H01W0100
arc: N1_V02N0701 H06W0203
arc: N3_V06N0103 E3_H06W0103
arc: S1_V02S0501 E1_H01W0100
arc: V00B0000 N1_V02S0201
arc: V00B0100 S1_V02N0301
arc: V00T0000 N1_V02S0601
arc: W1_H02W0601 V06N0303
arc: A0 W1_H02E0501
arc: A2 H01E0001
arc: A3 V00T0000
arc: A4 V00B0000
arc: A6 N1_V02S0101
arc: A7 H00R0000
arc: B5 H01E0101
arc: CE1 H00R0100
arc: CLK0 G_HPBX0000
arc: E1_H02E0401 F6
arc: E1_H02E0501 F5
arc: E3_H06E0203 F7
arc: F3 F3_SLICE
arc: F4 F4_SLICE
arc: F5 F5_SLICE
arc: F6 F6_SLICE
arc: F7 F7_SLICE
arc: H01W0000 F5
arc: H01W0100 Q3
arc: LSR1 V00B0100
arc: M3 E1_H02W0201
arc: MUXCLK1 CLK0
arc: MUXLSR1 LSR1
arc: N1_V01N0001 F7
arc: N1_V02N0101 F3
arc: N1_V02N0401 F4
arc: N1_V02N0601 F6
arc: S1_V02S0301 F3
arc: S1_V02S0401 F4
arc: V01S0000 F6
arc: V01S0100 F4
word: SLICED.K1.INIT 1010101010100000
word: SLICED.K0.INIT 1010101010100000
word: SLICEC.K1.INIT 1100110011000000
word: SLICEC.K0.INIT 1010101010100000
word: SLICEB.K1.INIT 1010101010100000
word: SLICEB.K0.INIT 0110011001101100
word: SLICEA.K1.INIT 1111111111111111
word: SLICEA.K0.INIT 0000000000001010
enum: SLICED.MODE CCU2
enum: SLICED.CCU2.INJECT1_1 NO
enum: SLICED.B1MUX 1
enum: SLICED.C1MUX 1
enum: SLICED.D1MUX 1
enum: SLICED.MODE CCU2
enum: SLICED.CCU2.INJECT1_0 NO
enum: SLICED.B0MUX 1
enum: SLICED.C0MUX 1
enum: SLICED.D0MUX 1
enum: SLICEC.MODE CCU2
enum: SLICEC.CCU2.INJECT1_1 NO
enum: SLICEC.A1MUX 1
enum: SLICEC.C1MUX 1
enum: SLICEC.D1MUX 1
enum: SLICEC.MODE CCU2
enum: SLICEC.CCU2.INJECT1_0 NO
enum: SLICEC.B0MUX 1
enum: SLICEC.C0MUX 1
enum: SLICEC.D0MUX 1
enum: SLICEB.MODE CCU2
enum: SLICEB.CCU2.INJECT1_1 NO
enum: SLICEB.B1MUX 1
enum: SLICEB.C1MUX 1
enum: SLICEB.D1MUX 1
enum: SLICEB.MODE CCU2
enum: SLICEB.CCU2.INJECT1_0 NO
enum: SLICEB.B0MUX 1
enum: SLICEB.C0MUX 1
enum: SLICEB.D0MUX 1
enum: SLICEA.MODE CCU2
enum: SLICEA.CCU2.INJECT1_1 YES
enum: SLICEA.A1MUX 1
enum: SLICEA.B1MUX 1
enum: SLICEA.C1MUX 1
enum: SLICEA.D1MUX 1
enum: SLICEA.MODE CCU2
enum: SLICEA.CCU2.INJECT1_0 NO
enum: SLICEA.B0MUX 1
enum: SLICEA.C0MUX 1
enum: SLICEA.D0MUX 1
enum: SLICEB.GSR DISABLED
enum: SLICEB.REG1.SD 0
enum: SLICEB.REG1.REGSET RESET
enum: SLICEB.REG1.LSRMODE LSR
enum: SLICEB.CEMUX CE
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
.tile R5C33:PLC2
arc: E1_H02E0101 N1_V01S0100
arc: E1_H02E0401 V02N0401
arc: H00R0000 H02W0601
arc: H00R0100 S1_V02N0701
arc: N1_V02N0201 S1_V02N0701
arc: N1_V02N0301 E1_H01W0100
arc: N1_V02N0401 E1_H02W0401
arc: N1_V02N0501 E1_H02W0501
arc: N1_V02N0601 E1_H01W0000
arc: S1_V02S0001 H06W0003
arc: S1_V02S0301 N1_V02S0301
arc: W1_H02W0101 E1_H02W0001
arc: A0 V02S0701
arc: A2 V02S0501
arc: A4 V02S0101
arc: A5 V02S0301
arc: A6 E1_H01W0000
arc: B1 E1_H01W0100
arc: B3 H00R0000
arc: B7 H02W0101
arc: CE3 H00R0100
arc: CLK0 G_HPBX0000
arc: E1_H01E0001 F3
arc: E1_H01E0101 F6
arc: E1_H02E0001 F0
arc: E1_H02E0201 F2
arc: E1_H02E0301 F1
arc: E1_H02E0601 F4
arc: E1_H02E0701 F5
arc: E3_H06E0003 F0
arc: E3_H06E0103 F2
arc: E3_H06E0303 F5
arc: F0 F0_SLICE
arc: F1 F1_SLICE
arc: F2 F2_SLICE
arc: F3 F3_SLICE
arc: F4 F4_SLICE
arc: F5 F5_SLICE
arc: F6 F6_SLICE
arc: F7 F7_SLICE
arc: H01W0100 Q7
arc: M7 H02W0201
arc: MUXCLK3 CLK0
arc: N1_V01N0001 F4
arc: N1_V01N0101 F7
arc: N1_V02N0701 Q7
arc: S1_V02S0201 F2
arc: S1_V02S0701 F7
arc: V01S0000 F6
arc: V01S0100 Q7
arc: W1_H02W0501 Q7
word: SLICED.K1.INIT 1100110011000000
word: SLICED.K0.INIT 1010101010100000
word: SLICEC.K1.INIT 1010101010100000
word: SLICEC.K0.INIT 1010101010100000
word: SLICEB.K1.INIT 1100110011000000
word: SLICEB.K0.INIT 1010101010100000
word: SLICEA.K1.INIT 1100110011000000
word: SLICEA.K0.INIT 1010101010100000
enum: SLICED.MODE CCU2
enum: SLICED.CCU2.INJECT1_1 NO
enum: SLICED.A1MUX 1
enum: SLICED.C1MUX 1
enum: SLICED.D1MUX 1
enum: SLICED.MODE CCU2
enum: SLICED.CCU2.INJECT1_0 NO
enum: SLICED.B0MUX 1
enum: SLICED.C0MUX 1
enum: SLICED.D0MUX 1
enum: SLICEC.MODE CCU2
enum: SLICEC.CCU2.INJECT1_1 NO
enum: SLICEC.B1MUX 1
enum: SLICEC.C1MUX 1
enum: SLICEC.D1MUX 1
enum: SLICEC.MODE CCU2
enum: SLICEC.CCU2.INJECT1_0 NO
enum: SLICEC.B0MUX 1
enum: SLICEC.C0MUX 1
enum: SLICEC.D0MUX 1
enum: SLICEB.MODE CCU2
enum: SLICEB.CCU2.INJECT1_1 NO
enum: SLICEB.A1MUX 1
enum: SLICEB.C1MUX 1
enum: SLICEB.D1MUX 1
enum: SLICEB.MODE CCU2
enum: SLICEB.CCU2.INJECT1_0 NO
enum: SLICEB.B0MUX 1
enum: SLICEB.C0MUX 1
enum: SLICEB.D0MUX 1
enum: SLICEA.MODE CCU2
enum: SLICEA.CCU2.INJECT1_1 NO
enum: SLICEA.A1MUX 1
enum: SLICEA.C1MUX 1
enum: SLICEA.D1MUX 1
enum: SLICEA.MODE CCU2
enum: SLICEA.CCU2.INJECT1_0 NO
enum: SLICEA.B0MUX 1
enum: SLICEA.C0MUX 1
enum: SLICEA.D0MUX 1
enum: SLICED.GSR DISABLED
enum: SLICED.REG1.SD 0
enum: SLICED.REG1.REGSET RESET
enum: SLICED.REG1.LSRMODE LSR
enum: SLICED.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
.tile R5C34:PLC2
arc: E1_H02E0001 W1_H02E0501
arc: E1_H02E0401 W1_H02E0401
arc: E1_H02E0501 N1_V01S0100
arc: E1_H02E0601 N1_V01S0000
arc: E1_H02E0701 H01E0101
arc: H00R0100 H02W0701
arc: N1_V02N0101 S1_V02N0101
arc: N1_V02N0201 S1_V02N0701
arc: N1_V02N0301 E1_H02W0301
arc: N1_V02N0401 S1_V02N0101
arc: N1_V02N0501 H06W0303
arc: N1_V02N0601 H02W0601
arc: N1_V02N0701 E1_H01W0100
arc: N3_V06N0003 H06E0003
arc: S1_V02S0101 E1_H01W0100
arc: S1_V02S0301 N1_V02S0301
arc: S1_V02S0401 H02W0401
arc: S1_V02S0601 E1_H02W0601
arc: V00B0000 V02S0001
arc: V00B0100 N1_V02S0301
arc: W1_H02W0101 E1_H02W0001
arc: W1_H02W0201 S1_V02N0201
arc: A7 H02E0701
arc: B0 E1_H02W0101
arc: B1 E1_H02W0301
arc: B5 H02E0301
arc: B6 H01E0101
arc: B7 V00B0000
arc: C4 H01E0001
arc: C7 H01E0001
arc: CE2 H02W0101
arc: CE3 H02W0101
arc: CLK0 G_HPBX0000
arc: D4 H00R0100
arc: D5 H00R0100
arc: D6 H00R0100
arc: D7 N1_V02S0401
arc: E1_H01E0001 F0
arc: E1_H01E0101 F7
arc: E1_H02E0201 F0
arc: E1_H02E0301 F1
arc: E3_H06E0103 F1
arc: F0 F0_SLICE
arc: F1 F1_SLICE
arc: F4 F4_SLICE
arc: F5 F5_SLICE
arc: F6 F6_SLICE
arc: F7 F7_SLICE
arc: H01W0000 Q6
arc: H01W0100 Q5
arc: LSR0 W1_H02E0301
arc: LSR1 V00B0100
arc: MUXCLK2 CLK0
arc: MUXCLK3 CLK0
arc: MUXLSR2 LSR1
arc: MUXLSR3 LSR0
arc: N1_V01N0101 Q4
arc: N3_V06N0203 Q4
arc: N3_V06N0303 Q5
arc: W1_H02W0601 Q4
word: SLICEB.K1.INIT 0000000000001110
word: SLICEB.K0.INIT 0000000000000000
word: SLICEA.K1.INIT 1100110011000000
word: SLICEA.K0.INIT 1100110011000000
word: SLICED.K0.INIT 1100110000000000
word: SLICEC.K1.INIT 1100110000000000
word: SLICED.K1.INIT 1000001001000001
word: SLICEC.K0.INIT 1111000000000000
enum: SLICEB.MODE CCU2
enum: SLICEB.CCU2.INJECT1_1 NO
enum: SLICEB.A1MUX 1
enum: SLICEB.B1MUX 1
enum: SLICEB.C1MUX 1
enum: SLICEB.D1MUX 1
enum: SLICEB.MODE CCU2
enum: SLICEB.CCU2.INJECT1_0 NO
enum: SLICEB.A0MUX 1
enum: SLICEB.B0MUX 1
enum: SLICEB.C0MUX 1
enum: SLICEB.D0MUX 1
enum: SLICEA.MODE CCU2
enum: SLICEA.CCU2.INJECT1_1 NO
enum: SLICEA.A1MUX 1
enum: SLICEA.C1MUX 1
enum: SLICEA.D1MUX 1
enum: SLICEA.MODE CCU2
enum: SLICEA.CCU2.INJECT1_0 NO
enum: SLICEA.A0MUX 1
enum: SLICEA.C0MUX 1
enum: SLICEA.D0MUX 1
enum: SLICED.MODE LOGIC
enum: SLICED.CCU2.INJECT1_0 _NONE_
enum: SLICED.A0MUX 1
enum: SLICED.C0MUX 1
enum: SLICEC.MODE LOGIC
enum: SLICEC.CCU2.INJECT1_1 _NONE_
enum: SLICEC.A1MUX 1
enum: SLICEC.C1MUX 1
enum: SLICED.MODE LOGIC
enum: SLICED.CCU2.INJECT1_1 _NONE_
enum: SLICEC.MODE LOGIC
enum: SLICEC.CCU2.INJECT1_0 _NONE_
enum: SLICEC.A0MUX 1
enum: SLICEC.B0MUX 1
enum: SLICEC.GSR DISABLED
enum: SLICEC.REG0.SD 1
enum: SLICEC.REG0.REGSET RESET
enum: SLICEC.REG0.LSRMODE LSR
enum: SLICEC.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEC.GSR DISABLED
enum: SLICEC.REG1.SD 1
enum: SLICEC.REG1.REGSET RESET
enum: SLICEC.REG1.LSRMODE LSR
enum: SLICEC.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICED.GSR DISABLED
enum: SLICED.REG0.SD 1
enum: SLICED.REG0.REGSET RESET
enum: SLICED.REG0.LSRMODE LSR
enum: SLICED.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
.tile R5C35:PLC2
arc: E1_H02E0001 H01E0001
arc: E1_H02E0201 S1_V02N0201
arc: E1_H02E0401 S1_V02N0401
arc: E1_H02E0501 H01E0101
arc: E1_H02E0601 W1_H02E0301
arc: H00L0000 V02N0001
arc: H00L0100 E1_H02W0301
arc: H00R0000 H02W0401
arc: H00R0100 H02E0701
arc: N1_V02N0001 E1_H01W0000
arc: N1_V02N0101 E1_H01W0100
arc: N1_V02N0201 N1_V01S0000
arc: N1_V02N0301 S1_V02N0301
arc: N1_V02N0401 S1_V02N0101
arc: N1_V02N0601 N1_V01S0000
arc: N1_V02N0701 S1_V02N0701
arc: S1_V02S0001 H01E0001
arc: S1_V02S0501 H06W0303
arc: W1_H02W0001 E1_H02W0501
arc: W1_H02W0101 E1_H02W0101
arc: W1_H02W0401 E1_H02W0401
arc: W1_H02W0601 E1_H02W0601
arc: W1_H02W0701 S1_V02N0701
arc: W3_H06W0203 E1_H01W0000
arc: A0 E1_H01E0001
arc: A1 H02E0501
arc: A7 H02W0501
arc: B0 V02S0301
arc: B1 H01W0100
arc: B2 V02S0301
arc: B3 V02S0301
arc: B7 W1_H02E0101
arc: C0 N1_V01N0001
arc: C1 V02N0401
arc: C2 N1_V01N0001
arc: C3 N1_V01N0001
arc: C7 H02E0401
arc: CE1 H00R0000
arc: CE3 H00R0000
arc: CLK0 G_HPBX0000
arc: D0 W1_H02E0201
arc: D1 W1_H02E0201
arc: D2 W1_H02E0201
arc: D3 W1_H02E0201
arc: D7 W1_H02E0001
arc: E1_H01E0001 Q7
arc: E1_H01E0101 Q7
arc: E1_H02E0701 F5
arc: F0 F5A_SLICE
arc: F1 FXA_SLICE
arc: F2 F5B_SLICE
arc: F4 F5C_SLICE
arc: F5 FXC_SLICE
arc: F6 F5D_SLICE
arc: H01W0100 Q3
arc: M0 W1_H02E0601
arc: M1 H00R0100
arc: M2 W1_H02E0601
arc: M3 H00L0100
arc: M4 W1_H02E0401
arc: M5 H00L0000
arc: M6 W1_H02E0401
arc: M7 E1_H02W0201
arc: MUXCLK1 CLK0
arc: MUXCLK3 CLK0
arc: N1_V01N0001 Q3
arc: N1_V01N0101 Q3
arc: N1_V02N0501 F5
arc: S1_V02S0101 F1
arc: S1_V02S0701 F5
arc: V01S0000 Q7
arc: V01S0100 Q3
arc: W1_H02W0501 Q7
word: SLICEC.K0.INIT 0000000000000000
word: SLICEC.K1.INIT 0000000000000000
word: SLICED.K0.INIT 0000000000000000
word: SLICED.K1.INIT 1010001001010001
word: SLICEA.K0.INIT 0010001000000010
word: SLICEA.K1.INIT 1010000000100000
word: SLICEB.K0.INIT 0011001100000011
word: SLICEB.K1.INIT 1100110000001100
enum: SLICEC.MODE LOGIC
enum: SLICEC.CCU2.INJECT1_0 _NONE_
enum: SLICEC.A0MUX 1
enum: SLICEC.B0MUX 1
enum: SLICEC.C0MUX 1
enum: SLICEC.D0MUX 1
enum: SLICEC.MODE LOGIC
enum: SLICEC.CCU2.INJECT1_1 _NONE_
enum: SLICEC.A1MUX 1
enum: SLICEC.B1MUX 1
enum: SLICEC.C1MUX 1
enum: SLICEC.D1MUX 1
enum: SLICED.MODE LOGIC
enum: SLICED.CCU2.INJECT1_0 _NONE_
enum: SLICED.A0MUX 1
enum: SLICED.B0MUX 1
enum: SLICED.C0MUX 1
enum: SLICED.D0MUX 1
enum: SLICED.MODE LOGIC
enum: SLICED.CCU2.INJECT1_1 _NONE_
enum: SLICED.GSR DISABLED
enum: SLICED.REG1.SD 0
enum: SLICED.REG1.REGSET RESET
enum: SLICED.REG1.LSRMODE LSR
enum: SLICED.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEB.GSR DISABLED
enum: SLICEB.REG1.SD 0
enum: SLICEB.REG1.REGSET RESET
enum: SLICEB.REG1.LSRMODE LSR
enum: SLICEB.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEA.MODE LOGIC
enum: SLICEA.CCU2.INJECT1_0 _NONE_
enum: SLICEA.MODE LOGIC
enum: SLICEA.CCU2.INJECT1_1 _NONE_
enum: SLICEB.MODE LOGIC
enum: SLICEB.CCU2.INJECT1_0 _NONE_
enum: SLICEB.A0MUX 1
enum: SLICEB.MODE LOGIC
enum: SLICEB.CCU2.INJECT1_1 _NONE_
enum: SLICEB.A1MUX 1
.tile R5C36:PLC2
arc: E1_H02E0201 W1_H02E0201
arc: E1_H02E0301 V01N0101
arc: E1_H02E0401 V01N0001
arc: E1_H02E0601 W1_H02E0301
arc: H00L0000 S1_V02N0001
arc: H00R0000 H02E0601
arc: H00R0100 V02N0501
arc: N1_V02N0001 H06E0003
arc: N1_V02N0101 H02W0101
arc: N1_V02N0201 H01E0001
arc: N1_V02N0301 H01E0101
arc: N1_V02N0401 S1_V02N0101
arc: N1_V02N0501 E1_H01W0100
arc: N1_V02N0601 H06E0303
arc: S1_V02S0001 N1_V02S0501
arc: S1_V02S0701 N1_V02S0601
arc: S3_V06S0003 E1_H01W0000
arc: V00B0000 E1_H02W0401
arc: V00B0100 E1_H02W0701
arc: W1_H02W0001 N1_V01S0000
arc: W1_H02W0101 E1_H02W0001
arc: W1_H02W0301 E1_H02W0201
arc: W1_H02W0401 S1_V02N0401
arc: W1_H02W0501 N1_V02S0501
arc: W1_H02W0601 E1_H02W0601
arc: W3_H06W0003 E1_H01W0000
arc: A0 V02N0701
arc: A1 V02N0701
arc: A2 V02N0701
arc: A3 V02N0701
arc: B0 H01W0100
arc: B1 H01W0100
arc: B2 H01W0100
arc: B3 H01W0100
arc: C0 W1_H02E0601
arc: C1 W1_H02E0601
arc: C2 W1_H02E0601
arc: C3 W1_H02E0601
arc: CE3 H00L0000
arc: CLK0 G_HPBX0000
arc: D0 W1_H02E0001
arc: D1 W1_H02E0001
arc: D2 W1_H02E0001
arc: D3 W1_H02E0001
arc: E1_H01E0001 F3
arc: E1_H01E0101 Q7
arc: F0 F5A_SLICE
arc: F1 FXA_SLICE
arc: F2 F5B_SLICE
arc: F3 FXB_SLICE
arc: F4 F5C_SLICE
arc: F5 FXC_SLICE
arc: F6 F5D_SLICE
arc: H01W0000 Q7
arc: H01W0100 Q7
arc: M0 V00B0000
arc: M1 H00R0000
arc: M2 V00B0100
arc: M3 H00R0100
arc: M4 E1_H02W0401
arc: M5 H00R0000
arc: M6 E1_H02W0401
arc: M7 H02E0201
arc: MUXCLK3 CLK0
arc: V01S0000 Q7
word: SLICEA.K0.INIT 0010000000000010
word: SLICEA.K1.INIT 1000000000001000
word: SLICEB.K0.INIT 0001000000000001
word: SLICEB.K1.INIT 0100000000000100
word: SLICEC.K0.INIT 0000000000000000
word: SLICEC.K1.INIT 0000000000000000
word: SLICED.K0.INIT 0000000000000000
word: SLICED.K1.INIT 0000000000000000
enum: SLICED.GSR DISABLED
enum: SLICED.REG1.SD 0
enum: SLICED.REG1.REGSET RESET
enum: SLICED.REG1.LSRMODE LSR
enum: SLICED.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEA.MODE LOGIC
enum: SLICEA.CCU2.INJECT1_0 _NONE_
enum: SLICEA.MODE LOGIC
enum: SLICEA.CCU2.INJECT1_1 _NONE_
enum: SLICEB.MODE LOGIC
enum: SLICEB.CCU2.INJECT1_0 _NONE_
enum: SLICEB.MODE LOGIC
enum: SLICEB.CCU2.INJECT1_1 _NONE_
enum: SLICEC.MODE LOGIC
enum: SLICEC.CCU2.INJECT1_0 _NONE_
enum: SLICEC.A0MUX 1
enum: SLICEC.B0MUX 1
enum: SLICEC.C0MUX 1
enum: SLICEC.D0MUX 1
enum: SLICEC.MODE LOGIC
enum: SLICEC.CCU2.INJECT1_1 _NONE_
enum: SLICEC.A1MUX 1
enum: SLICEC.B1MUX 1
enum: SLICEC.C1MUX 1
enum: SLICEC.D1MUX 1
enum: SLICED.MODE LOGIC
enum: SLICED.CCU2.INJECT1_0 _NONE_
enum: SLICED.A0MUX 1
enum: SLICED.B0MUX 1
enum: SLICED.C0MUX 1
enum: SLICED.D0MUX 1
enum: SLICED.MODE LOGIC
enum: SLICED.CCU2.INJECT1_1 _NONE_
enum: SLICED.A1MUX 1
enum: SLICED.B1MUX 1
enum: SLICED.C1MUX 1
enum: SLICED.D1MUX 1
.tile R5C37:PLC2
arc: E1_H01E0001 W3_H06E0003
arc: E1_H02E0101 V01N0101
arc: E1_H02E0201 S1_V02N0201
arc: H00L0100 E1_H02W0101
arc: N1_V02N0001 W3_H06E0003
arc: N1_V02N0201 E1_H02W0201
arc: N1_V02N0301 V01N0101
arc: N1_V02N0401 W1_H02E0401
arc: N1_V02N0501 H01E0101
arc: N1_V02N0601 S1_V02N0601
arc: S1_V02S0301 H02E0301
arc: S3_V06S0203 E1_H01W0000
arc: V00B0000 S1_V02N0201
arc: W1_H02W0101 V01N0101
arc: W1_H02W0201 E1_H02W0701
arc: W1_H02W0501 V01N0101
arc: W3_H06W0103 V01N0101
arc: W3_H06W0203 E1_H01W0000
arc: W3_H06W0303 E1_H01W0100
arc: A0 E1_H01E0001
arc: A1 E1_H01E0001
arc: A3 W1_H02E0701
arc: A4 S1_V02N0301
arc: A5 S1_V02N0301
arc: A6 V02N0301
arc: A7 W1_H02E0501
arc: B0 V02S0301
arc: B1 V02S0301
arc: B2 S1_V02N0301
arc: B3 S1_V02N0301
arc: B5 H02W0101
arc: C0 V02S0401
arc: C1 V02S0401
arc: C2 H02E0401
arc: C3 H02E0401
arc: C4 V01N0101
arc: C5 E1_H02W0601
arc: C6 S1_V02N0201
arc: C7 H01E0001
arc: CE1 V02N0201
arc: CLK0 G_HPBX0000
arc: D0 H02E0201
arc: D1 W1_H02E0001
arc: D3 V02N0001
arc: D4 V02N0401
arc: D6 V01N0001
arc: D7 F0
arc: E1_H01E0101 Q4
arc: E1_H02E0501 F5
arc: E3_H06E0203 Q7
arc: F0 F5A_SLICE
arc: F2 F5B_SLICE
arc: F4 F4_SLICE
arc: F5 F5_SLICE
arc: F6 F6_SLICE
arc: F7 F7_SLICE
arc: H00L0000 F2
arc: H00R0000 Q6
arc: H01W0000 Q4
arc: H01W0100 Q6
arc: LSR1 V00B0000
arc: M0 H02E0601
arc: M1 H00L0100
arc: M2 V00B0100
arc: M3 H00L0000
arc: M6 V00T0100
arc: M7 H00R0000
arc: MUXCLK0 CLK0
arc: MUXCLK1 CLK0
arc: MUXCLK2 CLK0
arc: MUXCLK3 CLK0
arc: MUXLSR0 LSR1
arc: MUXLSR1 LSR1
arc: MUXLSR2 LSR1
arc: MUXLSR3 LSR1
arc: N1_V01N0001 F7
arc: N1_V01N0101 F5
arc: N1_V02N0701 Q7
arc: N3_V06N0203 Q4
arc: N3_V06N0303 F6
arc: S1_V02S0101 Q1
arc: S1_V02S0401 Q4
arc: S1_V02S0501 F5
arc: S1_V02S0601 F6
arc: S1_V02S0701 F7
arc: S3_V06S0303 F6
arc: V00B0100 F7
arc: V00T0100 Q1
arc: V01S0000 F7
arc: W1_H02W0301 Q1
arc: W1_H02W0401 F6
arc: W1_H02W0601 Q6
arc: W3_H06W0003 Q3
word: SLICED.K1.INIT 1010000000000000
word: SLICEC.K1.INIT 0010101000101010
word: SLICEB.K0.INIT 0011000000110000
word: SLICEB.K1.INIT 1011100000110000
word: SLICED.K0.INIT 0000101000000000
word: SLICEC.K0.INIT 0000111110100000
word: SLICEA.K0.INIT 0000010100000001
word: SLICEA.K1.INIT 0101000000010000
enum: SLICED.MODE LOGIC
enum: SLICED.CCU2.INJECT1_1 _NONE_
enum: SLICED.B1MUX 1
enum: SLICEC.MODE LOGIC
enum: SLICEC.CCU2.INJECT1_1 _NONE_
enum: SLICEC.D1MUX 1
enum: SLICEB.MODE LOGIC
enum: SLICEB.CCU2.INJECT1_0 _NONE_
enum: SLICEB.A0MUX 1
enum: SLICEB.D0MUX 1
enum: SLICEB.MODE LOGIC
enum: SLICEB.CCU2.INJECT1_1 _NONE_
enum: SLICEB.GSR DISABLED
enum: SLICEB.REG1.SD 0
enum: SLICEB.REG1.REGSET RESET
enum: SLICEB.REG1.LSRMODE LSR
enum: SLICEB.CEMUX CE
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICED.GSR DISABLED
enum: SLICED.REG1.SD 0
enum: SLICED.REG1.REGSET RESET
enum: SLICED.REG1.LSRMODE LSR
enum: SLICED.CEMUX 1
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICED.GSR DISABLED
enum: SLICED.REG0.SD 0
enum: SLICED.REG0.REGSET RESET
enum: SLICED.REG0.LSRMODE LSR
enum: SLICED.CEMUX 1
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICED.MODE LOGIC
enum: SLICED.CCU2.INJECT1_0 _NONE_
enum: SLICED.B0MUX 1
enum: SLICEC.GSR DISABLED
enum: SLICEC.REG0.SD 1
enum: SLICEC.REG0.REGSET RESET
enum: SLICEC.REG0.LSRMODE LSR
enum: SLICEC.CEMUX 1
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEC.MODE LOGIC
enum: SLICEC.CCU2.INJECT1_0 _NONE_
enum: SLICEC.B0MUX 1
enum: SLICEA.GSR DISABLED
enum: SLICEA.REG1.SD 0
enum: SLICEA.REG1.REGSET RESET
enum: SLICEA.REG1.LSRMODE LSR
enum: SLICEA.CEMUX 1
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEA.MODE LOGIC
enum: SLICEA.CCU2.INJECT1_0 _NONE_
enum: SLICEA.MODE LOGIC
enum: SLICEA.CCU2.INJECT1_1 _NONE_
.tile R5C38:PLC2
arc: E1_H02E0101 H01E0101
arc: E1_H02E0601 N1_V01S0000
arc: H00L0000 E1_H02W0001
arc: H00R0100 V02N0701
arc: N1_V02N0001 S1_V02N0001
arc: N1_V02N0101 S1_V02N0001
arc: N1_V02N0201 E1_H01W0000
arc: N1_V02N0301 H01E0101
arc: N1_V02N0401 E1_H01W0000
arc: N1_V02N0701 H01E0101
arc: S1_V02S0501 H02E0501
arc: V00B0100 V02N0101
arc: V00T0000 H02E0201
arc: V00T0100 H02E0101
arc: W1_H02W0101 V01N0101
arc: W1_H02W0401 W3_H06E0203
arc: W1_H02W0701 W3_H06E0203
arc: W3_H06W0303 E1_H01W0100
arc: A5 V02N0101
arc: A6 V02N0101
arc: B0 S1_V02N0301
arc: B2 S1_V02N0301
arc: B4 V01S0000
arc: B5 V02N0501
arc: C4 V00B0100
arc: C5 V02N0001
arc: C6 V00T0000
arc: CE0 H02E0101
arc: CE1 H02E0101
arc: CLK0 G_HPBX0000
arc: D0 E1_H02W0201
arc: D2 W1_H02E0201
arc: D4 H00R0100
arc: D5 V02N0401
arc: D6 H00R0100
arc: E1_H01E0001 F6
arc: E1_H01E0101 F6
arc: E1_H02E0501 Q7
arc: E1_H02E0701 Q7
arc: F0 F0_SLICE
arc: F2 F2_SLICE
arc: F4 F5C_SLICE
arc: F6 F6_SLICE
arc: H00R0000 F4
arc: H01W0000 F6
arc: H01W0100 Q2
arc: LSR0 V00T0000
arc: LSR1 V00T0000
arc: M4 V00T0100
arc: M5 H00R0000
arc: M7 H00L0000
arc: MUXCLK0 CLK0
arc: MUXCLK1 CLK0
arc: MUXCLK2 CLK0
arc: MUXCLK3 CLK0
arc: MUXLSR0 LSR1
arc: MUXLSR1 LSR0
arc: MUXLSR2 LSR0
arc: MUXLSR3 LSR1
arc: N1_V02N0501 Q7
arc: N1_V02N0601 F6
arc: N3_V06N0003 Q0
arc: N3_V06N0303 F6
arc: S1_V02S0601 F6
arc: V01S0000 Q5
arc: V01S0100 F6
arc: W1_H02W0001 Q2
arc: W1_H02W0201 Q0
arc: W1_H02W0601 F6
arc: W3_H06W0103 Q2
word: SLICEA.K0.INIT 1100110000000000
word: SLICED.K0.INIT 0000000000001010
word: SLICEC.K0.INIT 1111110011001100
word: SLICEC.K1.INIT 1111100000000000
word: SLICEB.K0.INIT 1100110000000000
enum: SLICEA.MODE LOGIC
enum: SLICEA.CCU2.INJECT1_0 _NONE_
enum: SLICEA.A0MUX 1
enum: SLICEA.C0MUX 1
enum: SLICED.GSR DISABLED
enum: SLICED.REG1.SD 0
enum: SLICED.REG1.REGSET RESET
enum: SLICED.REG1.LSRMODE LSR
enum: SLICED.CEMUX 1
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEA.GSR DISABLED
enum: SLICEA.REG0.SD 1
enum: SLICEA.REG0.REGSET RESET
enum: SLICEA.REG0.LSRMODE LSR
enum: SLICEA.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEB.GSR DISABLED
enum: SLICEB.REG0.SD 1
enum: SLICEB.REG0.REGSET RESET
enum: SLICEB.REG0.LSRMODE LSR
enum: SLICEB.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICED.MODE LOGIC
enum: SLICED.CCU2.INJECT1_0 _NONE_
enum: SLICED.B0MUX 1
enum: SLICEC.MODE LOGIC
enum: SLICEC.CCU2.INJECT1_0 _NONE_
enum: SLICEC.A0MUX 1
enum: SLICEC.MODE LOGIC
enum: SLICEC.CCU2.INJECT1_1 _NONE_
enum: SLICEB.MODE LOGIC
enum: SLICEB.CCU2.INJECT1_0 _NONE_
enum: SLICEB.A0MUX 1
enum: SLICEB.C0MUX 1
enum: SLICEC.GSR DISABLED
enum: SLICEC.REG1.SD 0
enum: SLICEC.REG1.REGSET RESET
enum: SLICEC.REG1.LSRMODE LSR
enum: SLICEC.CEMUX 1
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
.tile R5C39:PLC2
arc: H00R0100 H02E0701
arc: N1_V02N0101 S1_V02N0101
arc: N1_V02N0201 S1_V02N0201
arc: N1_V02N0301 S1_V02N0201
arc: N1_V02N0501 H02E0501
arc: N1_V02N0601 H01E0001
arc: N1_V02N0701 H01E0101
arc: V00T0000 W1_H02E0201
arc: W1_H02W0101 V06S0103
arc: W1_H02W0201 W3_H06E0103
arc: W1_H02W0601 S1_V02N0601
arc: A0 V02S0501
arc: A1 V02S0501
arc: B0 H02E0101
arc: B1 H02E0101
arc: B3 E1_H02W0101
arc: C0 N1_V01S0100
arc: C1 N1_V01S0100
arc: C3 H02E0601
arc: CLK0 G_HPBX0000
arc: D0 S1_V02N0001
arc: D1 S1_V02N0001
arc: D3 N1_V01S0000
arc: E1_H01E0001 Q2
arc: F0 F5A_SLICE
arc: F3 F3_SLICE
arc: H00R0000 Q4
arc: H01W0000 Q4
arc: H01W0100 Q7
arc: LSR0 V00T0000
arc: LSR1 V00T0000
arc: M0 V00T0100
arc: M2 V00B0100
arc: M4 E1_H02W0401
arc: M5 H00R0100
arc: M7 H00R0000
arc: MUXCLK1 CLK0
arc: MUXCLK2 CLK0
arc: MUXCLK3 CLK0
arc: MUXLSR1 LSR0
arc: MUXLSR2 LSR1
arc: MUXLSR3 LSR0
arc: N1_V01N0001 F0
arc: N1_V01N0101 Q5
arc: N1_V02N0001 Q2
arc: N1_V02N0401 Q4
arc: S1_V02S0701 Q5
arc: V00B0100 Q7
arc: V00T0100 F3
arc: V01S0100 Q5
arc: W1_H02W0701 Q7
word: SLICEB.K1.INIT 1111001111000000
word: SLICEA.K0.INIT 1011100000000000
word: SLICEA.K1.INIT 1011100011111111
enum: SLICEB.MODE LOGIC
enum: SLICEB.CCU2.INJECT1_1 _NONE_
enum: SLICEB.A1MUX 1
enum: SLICEA.MODE LOGIC
enum: SLICEA.CCU2.INJECT1_0 _NONE_
enum: SLICEA.MODE LOGIC
enum: SLICEA.CCU2.INJECT1_1 _NONE_
enum: SLICEC.GSR DISABLED
enum: SLICEC.REG1.SD 0
enum: SLICEC.REG1.REGSET RESET
enum: SLICEC.REG1.LSRMODE LSR
enum: SLICEC.CEMUX 1
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEB.GSR DISABLED
enum: SLICEB.REG0.SD 0
enum: SLICEB.REG0.REGSET RESET
enum: SLICEB.REG0.LSRMODE LSR
enum: SLICEB.CEMUX 1
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICED.GSR DISABLED
enum: SLICED.REG1.SD 0
enum: SLICED.REG1.REGSET RESET
enum: SLICED.REG1.LSRMODE LSR
enum: SLICED.CEMUX 1
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEC.GSR DISABLED
enum: SLICEC.REG0.SD 0
enum: SLICEC.REG0.REGSET RESET
enum: SLICEC.REG0.LSRMODE LSR
enum: SLICEC.CEMUX 1
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
.tile R5C40:PLC2
arc: N1_V02N0201 H01E0001
arc: S1_V02S0401 H06E0203
arc: W1_H02W0001 H01E0001
arc: W1_H02W0201 W3_H06E0103
.tile R5C41:PLC2
arc: W1_H02W0101 V02N0101
arc: W1_H02W0401 E1_H02W0401
.tile R5C43:PLC2
arc: W1_H02W0401 W3_H06E0203
.tile R6C31:PLC2
arc: E1_H02E0301 V02N0301
arc: E1_H02E0501 V01N0101
arc: N1_V02N0201 E1_H01W0000
arc: S1_V02S0101 E1_H01W0100
arc: V00B0000 S1_V02N0001
arc: V00B0100 V02N0301
arc: A0 E1_H02W0701
arc: A1 E1_H02W0701
arc: A2 V02N0501
arc: A3 V00T0000
arc: A4 S1_V02N0301
arc: B0 V00T0000
arc: B1 V00T0000
arc: B2 E1_H02W0101
arc: B4 V00B0100
arc: C0 V02N0601
arc: C1 V02N0601
arc: C2 H00L0100
arc: C3 E1_H02W0601
arc: C4 Q4
arc: CLK0 G_HPBX0000
arc: D0 H02W0001
arc: D1 H02W0001
arc: D2 H02W0201
arc: D3 S1_V02N0001
arc: D4 V00B0000
arc: E1_H02E0201 Q2
arc: E3_H06E0103 Q2
arc: F0 F5A_SLICE
arc: F2 F2_SLICE
arc: F3 F3_SLICE
arc: F4 F4_SLICE
arc: H00L0100 F3
arc: M0 E1_H02W0601
arc: MUXCLK1 CLK0
arc: MUXCLK2 CLK0
arc: N1_V02N0001 Q2
arc: S1_V02S0201 F0
arc: S1_V02S0401 Q4
arc: S3_V06S0203 Q4
arc: V00T0000 Q2
arc: V01S0100 Q2
word: SLICEA.K0.INIT 1010101110101000
word: SLICEA.K1.INIT 1110111110100000
word: SLICEB.K1.INIT 0000101010101010
word: SLICEB.K0.INIT 0000000011111000
word: SLICEC.K0.INIT 0010001000110010
enum: SLICEA.MODE LOGIC
enum: SLICEA.CCU2.INJECT1_0 _NONE_
enum: SLICEA.MODE LOGIC
enum: SLICEA.CCU2.INJECT1_1 _NONE_
enum: SLICEB.MODE LOGIC
enum: SLICEB.CCU2.INJECT1_1 _NONE_
enum: SLICEB.B1MUX 1
enum: SLICEB.GSR DISABLED
enum: SLICEB.REG0.SD 1
enum: SLICEB.REG0.REGSET RESET
enum: SLICEB.REG0.LSRMODE LSR
enum: SLICEB.CEMUX 1
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEB.MODE LOGIC
enum: SLICEB.CCU2.INJECT1_0 _NONE_
enum: SLICEC.GSR DISABLED
enum: SLICEC.REG0.SD 1
enum: SLICEC.REG0.REGSET RESET
enum: SLICEC.REG0.LSRMODE LSR
enum: SLICEC.CEMUX 1
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEC.MODE LOGIC
enum: SLICEC.CCU2.INJECT1_0 _NONE_
.tile R6C32:PLC2
arc: E1_H02E0001 V01N0001
arc: E1_H02E0701 E1_H01W0100
arc: H00R0100 V02N0501
arc: H01W0000 E3_H06W0103
arc: N1_V02N0101 E3_H06W0103
arc: N1_V02N0401 V01N0001
arc: N1_V02N0501 E1_H01W0100
arc: N1_V02N0601 H06W0303
arc: N1_V02N0701 S1_V02N0701
arc: S1_V02S0101 E3_H06W0103
arc: S1_V02S0301 H06W0003
arc: S1_V02S0401 H06W0203
arc: S1_V02S0601 V01N0001
arc: V00T0000 H02W0201
arc: W1_H02W0001 E1_H02W0501
arc: W1_H02W0201 V01N0001
arc: A1 N1_V02S0701
arc: A4 V02S0301
arc: A5 N1_V01N0101
arc: B0 H02W0301
arc: B1 E1_H01W0100
arc: B4 V02S0501
arc: B5 V00B0100
arc: C0 F6
arc: C1 N1_V01S0100
arc: C3 F6
arc: C4 V00T0000
arc: C5 V02N0001
arc: C6 E1_H02W0601
arc: CE0 H00R0100
arc: CE1 H00R0100
arc: CE2 V02N0601
arc: CLK0 G_HPBX0000
arc: D0 V02N0001
arc: D1 N1_V01S0000
arc: D2 V00T0100
arc: D3 V01S0100
arc: D4 V02S0401
arc: D5 V00B0000
arc: D6 H02E0201
arc: E1_H01E0001 F4
arc: E1_H01E0101 F1
arc: E1_H02E0401 F6
arc: E1_H02E0501 Q5
arc: E3_H06E0303 F6
arc: F0 F0_SLICE
arc: F1 F1_SLICE
arc: F2 F2_SLICE
arc: F3 F3_SLICE
arc: F4 F4_SLICE
arc: F5 F5_SLICE
arc: F6 F6_SLICE
arc: H01W0100 F6
arc: LSR0 E1_H02W0301
arc: LSR1 H02E0301
arc: MUXCLK0 CLK0
arc: MUXCLK1 CLK0
arc: MUXCLK2 CLK0
arc: MUXLSR0 LSR1
arc: MUXLSR1 LSR0
arc: MUXLSR2 LSR1
arc: N1_V01N0101 Q3
arc: N1_V02N0001 Q0
arc: S1_V02S0201 Q2
arc: V00B0000 F6
arc: V00B0100 Q5
arc: V00T0100 F3
arc: V01S0000 Q5
arc: V01S0100 Q3
word: SLICEC.K0.INIT 1001000010011001
word: SLICEC.K1.INIT 0000000001101100
word: SLICEB.K1.INIT 0000000000001111
word: SLICEA.K1.INIT 1010001011110011
word: SLICEA.K0.INIT 1100110011000011
word: SLICEB.K0.INIT 0000000011111111
word: SLICED.K0.INIT 0000000000001111
enum: SLICEA.GSR DISABLED
enum: SLICEA.REG0.SD 1
enum: SLICEA.REG0.REGSET RESET
enum: SLICEA.REG0.LSRMODE LSR
enum: SLICEA.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEB.GSR DISABLED
enum: SLICEB.REG0.SD 1
enum: SLICEB.REG0.REGSET RESET
enum: SLICEB.REG0.LSRMODE LSR
enum: SLICEB.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEC.MODE LOGIC
enum: SLICEC.CCU2.INJECT1_0 _NONE_
enum: SLICEC.MODE LOGIC
enum: SLICEC.CCU2.INJECT1_1 _NONE_
enum: SLICEB.MODE LOGIC
enum: SLICEB.CCU2.INJECT1_1 _NONE_
enum: SLICEB.A1MUX 1
enum: SLICEB.B1MUX 1
enum: SLICEA.MODE LOGIC
enum: SLICEA.CCU2.INJECT1_1 _NONE_
enum: SLICEA.MODE LOGIC
enum: SLICEA.CCU2.INJECT1_0 _NONE_
enum: SLICEA.A0MUX 1
enum: SLICEB.MODE LOGIC
enum: SLICEB.CCU2.INJECT1_0 _NONE_
enum: SLICEB.A0MUX 1
enum: SLICEB.B0MUX 1
enum: SLICEB.C0MUX 1
enum: SLICEB.GSR DISABLED
enum: SLICEB.REG1.SD 1
enum: SLICEB.REG1.REGSET RESET
enum: SLICEB.REG1.LSRMODE LSR
enum: SLICEB.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEC.GSR DISABLED
enum: SLICEC.REG1.SD 1
enum: SLICEC.REG1.REGSET RESET
enum: SLICEC.REG1.LSRMODE LSR
enum: SLICEC.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICED.MODE LOGIC
enum: SLICED.CCU2.INJECT1_0 _NONE_
enum: SLICED.A0MUX 1
enum: SLICED.B0MUX 1
.tile R6C33:PLC2
arc: E1_H02E0001 N1_V01S0000
arc: E1_H02E0201 V02S0201
arc: E1_H02E0301 N1_V01S0100
arc: E1_H02E0401 V01N0001
arc: E1_H02E0501 N1_V01S0100
arc: E1_H02E0601 E1_H01W0000
arc: E1_H02E0701 V02S0701
arc: E3_H06E0303 H01E0101
arc: H00R0000 V02N0401
arc: H00R0100 H02E0501
arc: N1_V02N0101 S1_V02N0001
arc: N1_V02N0401 H01E0001
arc: N1_V02N0501 H06W0303
arc: N1_V02N0601 S1_V02N0301
arc: S1_V02S0101 E3_H06W0103
arc: S1_V02S0201 W1_H02E0201
arc: S1_V02S0601 H06W0303
arc: V00B0000 V02N0201
arc: V00T0000 H02W0001
arc: W1_H02W0101 E1_H02W0001
arc: W1_H02W0301 E1_H01W0100
arc: W1_H02W0601 V02N0601
arc: A2 W1_H02E0501
arc: A3 V00T0000
arc: A4 H02W0701
arc: A5 H02W0501
arc: A6 V02S0301
arc: B0 S1_V02N0101
arc: B2 E1_H01W0100
arc: B3 H00R0100
arc: B4 S1_V02N0701
arc: B7 H02W0101
arc: CE0 H00R0000
arc: CLK0 G_HPBX0000
arc: E1_H01E0101 F4
arc: E1_H02E0101 F3
arc: F3 F3_SLICE
arc: F4 F4_SLICE
arc: F5 F5_SLICE
arc: F6 F6_SLICE
arc: F7 F7_SLICE
arc: H01W0100 Q0
arc: M0 V00B0000
arc: MUXCLK0 CLK0
arc: N1_V02N0201 Q0
arc: N1_V02N0701 F7
arc: N3_V06N0303 F6
arc: V01S0100 Q0
arc: W1_H02W0201 Q0
arc: W1_H02W0701 F5
word: SLICED.K0.INIT 1010101010100000
word: SLICEC.K1.INIT 1010101010100000
word: SLICEC.K0.INIT 0110011001101100
word: SLICEB.K1.INIT 0110011001101100
word: SLICEB.K0.INIT 0110011001101010
word: SLICEA.K1.INIT 1111111111111111
word: SLICEA.K0.INIT 0000000000001100
word: SLICED.K1.INIT 1100110011000000
enum: SLICED.MODE CCU2
enum: SLICED.CCU2.INJECT1_0 NO
enum: SLICED.B0MUX 1
enum: SLICED.C0MUX 1
enum: SLICED.D0MUX 1
enum: SLICEC.MODE CCU2
enum: SLICEC.CCU2.INJECT1_1 NO
enum: SLICEC.B1MUX 1
enum: SLICEC.C1MUX 1
enum: SLICEC.D1MUX 1
enum: SLICEC.MODE CCU2
enum: SLICEC.CCU2.INJECT1_0 NO
enum: SLICEC.C0MUX 1
enum: SLICEC.D0MUX 1
enum: SLICEB.MODE CCU2
enum: SLICEB.CCU2.INJECT1_1 NO
enum: SLICEB.C1MUX 1
enum: SLICEB.D1MUX 1
enum: SLICEB.MODE CCU2
enum: SLICEB.CCU2.INJECT1_0 NO
enum: SLICEB.C0MUX 1
enum: SLICEB.D0MUX 1
enum: SLICEA.MODE CCU2
enum: SLICEA.CCU2.INJECT1_1 YES
enum: SLICEA.A1MUX 1
enum: SLICEA.B1MUX 1
enum: SLICEA.C1MUX 1
enum: SLICEA.D1MUX 1
enum: SLICEA.MODE CCU2
enum: SLICEA.CCU2.INJECT1_0 NO
enum: SLICEA.A0MUX 1
enum: SLICEA.C0MUX 1
enum: SLICEA.D0MUX 1
enum: SLICED.MODE CCU2
enum: SLICED.CCU2.INJECT1_1 NO
enum: SLICED.A1MUX 1
enum: SLICED.C1MUX 1
enum: SLICED.D1MUX 1
enum: SLICEA.GSR DISABLED
enum: SLICEA.REG0.SD 0
enum: SLICEA.REG0.REGSET RESET
enum: SLICEA.REG0.LSRMODE LSR
enum: SLICEA.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
.tile R6C34:PLC2
arc: E1_H02E0201 E1_H01W0000
arc: E1_H02E0301 V02S0301
arc: E1_H02E0501 W1_H02E0401
arc: E1_H02E0701 V06S0203
arc: E3_H06E0203 W1_H02E0701
arc: H00R0100 H02W0701
arc: N1_V02N0101 E1_H01W0100
arc: N1_V02N0201 H06W0103
arc: N1_V02N0501 H01E0101
arc: N1_V02N0701 H02W0701
arc: N3_V06N0303 E1_H01W0100
arc: S1_V02S0001 H06W0003
arc: S1_V02S0201 H06E0103
arc: S1_V02S0301 E1_H01W0100
arc: S1_V02S0601 H06W0303
arc: V00B0000 V02N0001
arc: W1_H02W0101 V06S0103
arc: W1_H02W0301 V02S0301
arc: W1_H02W0501 N1_V02S0501
arc: W1_H02W0601 V01N0001
arc: W1_H02W0701 N1_V02S0701
arc: A4 W1_H02E0701
arc: A5 V02N0301
arc: A6 H02E0501
arc: A7 V02S0101
arc: B0 H02W0301
arc: B4 H02E0301
arc: B5 V02N0501
arc: B6 E1_H02W0301
arc: C4 N1_V02S0201
arc: C5 S1_V02N0001
arc: C6 V02N0201
arc: CE0 H00R0100
arc: CE3 H02W0101
arc: CLK0 G_HPBX0000
arc: D4 N1_V02S0401
arc: D5 W1_H02E0001
arc: D6 V02N0401
arc: D7 H02E0201
arc: E1_H01E0001 F7
arc: E1_H02E0001 F0
arc: E1_H02E0401 F4
arc: E1_H02E0601 F4
arc: E3_H06E0303 Q5
arc: F0 F0_SLICE
arc: F4 F4_SLICE
arc: F5 F5_SLICE
arc: F6 F6_SLICE
arc: F7 F7_SLICE
arc: H00R0000 Q6
arc: H01W0000 Q0
arc: H01W0100 Q1
arc: M0 V00B0000
arc: M1 H00R0000
arc: MUXCLK0 CLK0
arc: MUXCLK2 CLK0
arc: MUXCLK3 CLK0
arc: V01S0000 Q5
arc: V01S0100 Q5
arc: W1_H02W0001 Q0
word: SLICED.K1.INIT 0101010100000000
word: SLICEA.K1.INIT 0000000000000000
word: SLICEB.K0.INIT 0000000000000000
word: SLICEB.K1.INIT 0000000000001110
word: SLICED.K0.INIT 1010101010111000
word: SLICEC.K0.INIT 0000000000000001
word: SLICEA.K0.INIT 1100110011000000
word: SLICEC.K1.INIT 0000000010000000
enum: SLICED.MODE LOGIC
enum: SLICED.CCU2.INJECT1_1 _NONE_
enum: SLICED.B1MUX 1
enum: SLICED.C1MUX 1
enum: SLICEA.MODE CCU2
enum: SLICEA.CCU2.INJECT1_1 NO
enum: SLICEA.A1MUX 1
enum: SLICEA.B1MUX 1
enum: SLICEA.C1MUX 1
enum: SLICEA.D1MUX 1
enum: SLICEB.MODE CCU2
enum: SLICEB.CCU2.INJECT1_0 NO
enum: SLICEB.A0MUX 1
enum: SLICEB.B0MUX 1
enum: SLICEB.C0MUX 1
enum: SLICEB.D0MUX 1
enum: SLICEB.MODE CCU2
enum: SLICEB.CCU2.INJECT1_1 NO
enum: SLICEB.A1MUX 1
enum: SLICEB.B1MUX 1
enum: SLICEB.C1MUX 1
enum: SLICEB.D1MUX 1
enum: SLICEC.GSR DISABLED
enum: SLICEC.REG1.SD 1
enum: SLICEC.REG1.REGSET RESET
enum: SLICEC.REG1.LSRMODE LSR
enum: SLICEC.CEMUX 1
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICED.MODE LOGIC
enum: SLICED.CCU2.INJECT1_0 _NONE_
enum: SLICEA.GSR DISABLED
enum: SLICEA.REG0.SD 0
enum: SLICEA.REG0.REGSET RESET
enum: SLICEA.REG0.LSRMODE LSR
enum: SLICEA.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEA.GSR DISABLED
enum: SLICEA.REG1.SD 0
enum: SLICEA.REG1.REGSET RESET
enum: SLICEA.REG1.LSRMODE LSR
enum: SLICEA.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEC.MODE LOGIC
enum: SLICEC.CCU2.INJECT1_0 _NONE_
enum: SLICEA.MODE CCU2
enum: SLICEA.CCU2.INJECT1_0 NO
enum: SLICEA.A0MUX 1
enum: SLICEA.C0MUX 1
enum: SLICEA.D0MUX 1
enum: SLICED.GSR DISABLED
enum: SLICED.REG0.SD 1
enum: SLICED.REG0.REGSET RESET
enum: SLICED.REG0.LSRMODE LSR
enum: SLICED.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEC.MODE LOGIC
enum: SLICEC.CCU2.INJECT1_1 _NONE_
.tile R6C35:PLC2
arc: E1_H02E0101 N1_V02S0101
arc: E1_H02E0201 V06S0103
arc: E1_H02E0401 V01N0001
arc: E1_H02E0501 N1_V01S0100
arc: E1_H02E0701 V02S0701
arc: H00L0000 N1_V02S0201
arc: H00R0100 W1_H02E0701
arc: N1_V02N0001 H01E0001
arc: N1_V02N0401 N1_V01S0000
arc: N1_V02N0601 H02W0601
arc: S1_V02S0201 H02W0201
arc: S1_V02S0401 N1_V02S0101
arc: S1_V02S0601 H06E0303
arc: S1_V02S0701 V01N0101
arc: V00B0100 V02S0101
arc: W1_H02W0101 N1_V02S0101
arc: W1_H02W0301 V06S0003
arc: W1_H02W0701 E1_H02W0601
arc: W3_H06W0303 E1_H02W0501
arc: A3 F7
arc: A4 H02E0701
arc: A5 H02E0701
arc: A6 H02E0501
arc: B0 S1_V02N0301
arc: B3 H00R0100
arc: B4 E1_H02W0101
arc: B5 E1_H02W0101
arc: B6 W1_H02E0101
arc: B7 N1_V01S0000
arc: C0 H00L0100
arc: C1 H00L0000
arc: C3 N1_V02S0401
arc: C4 V02N0001
arc: C5 V02N0001
arc: C6 W1_H02E0601
arc: CE3 V02N0601
arc: CLK0 G_HPBX0000
arc: D0 Q0
arc: D1 V02S0001
arc: D3 V00T0100
arc: D4 H02E0001
arc: D5 H02E0001
arc: D7 W1_H02E0001
arc: E1_H01E0001 F2
arc: E1_H01E0101 F0
arc: E1_H02E0001 F2
arc: E1_H02E0301 Q1
arc: E1_H02E0601 Q6
arc: E3_H06E0103 Q1
arc: F0 F0_SLICE
arc: F1 F1_SLICE
arc: F2 F5B_SLICE
arc: F4 F5C_SLICE
arc: F6 F6_SLICE
arc: F7 F7_SLICE
arc: H00L0100 Q3
arc: H00R0000 F4
arc: H01W0000 Q3
arc: H01W0100 Q1
arc: LSR0 H02E0301
arc: LSR1 H02E0301
arc: M1 H02W0001
arc: M2 V00B0100
arc: M3 E1_H02W0201
arc: M4 W1_H02E0401
arc: M7 H00R0000
arc: MUXCLK0 CLK0
arc: MUXCLK1 CLK0
arc: MUXCLK3 CLK0
arc: MUXLSR0 LSR1
arc: MUXLSR1 LSR1
arc: MUXLSR3 LSR0
arc: N1_V02N0201 F2
arc: S1_V02S0001 Q0
arc: V00T0100 F1
arc: V01S0000 F2
arc: V01S0100 Q1
arc: W1_H02W0001 Q0
arc: W3_H06W0003 Q0
arc: W3_H06W0203 Q7
word: SLICEA.K0.INIT 0000000000110000
word: SLICEC.K0.INIT 1111111000000010
word: SLICEC.K1.INIT 1111101010001010
word: SLICED.K0.INIT 1110010011100100
word: SLICEB.K0.INIT 0000000000000000
word: SLICEB.K1.INIT 0000000001000001
word: SLICEA.K1.INIT 0000111100000000
word: SLICED.K1.INIT 0000000011001100
enum: SLICED.GSR DISABLED
enum: SLICED.REG0.SD 1
enum: SLICED.REG0.REGSET RESET
enum: SLICED.REG0.LSRMODE LSR
enum: SLICED.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEA.GSR DISABLED
enum: SLICEA.REG1.SD 0
enum: SLICEA.REG1.REGSET RESET
enum: SLICEA.REG1.LSRMODE LSR
enum: SLICEA.CEMUX 1
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEA.MODE LOGIC
enum: SLICEA.CCU2.INJECT1_0 _NONE_
enum: SLICEA.A0MUX 1
enum: SLICED.GSR DISABLED
enum: SLICED.REG1.SD 0
enum: SLICED.REG1.REGSET RESET
enum: SLICED.REG1.LSRMODE LSR
enum: SLICED.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEC.MODE LOGIC
enum: SLICEC.CCU2.INJECT1_0 _NONE_
enum: SLICEC.MODE LOGIC
enum: SLICEC.CCU2.INJECT1_1 _NONE_
enum: SLICED.MODE LOGIC
enum: SLICED.CCU2.INJECT1_0 _NONE_
enum: SLICED.D0MUX 1
enum: SLICEA.GSR DISABLED
enum: SLICEA.REG0.SD 1
enum: SLICEA.REG0.REGSET RESET
enum: SLICEA.REG0.LSRMODE LSR
enum: SLICEA.CEMUX 1
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEB.GSR DISABLED
enum: SLICEB.REG1.SD 0
enum: SLICEB.REG1.REGSET RESET
enum: SLICEB.REG1.LSRMODE LSR
enum: SLICEB.CEMUX 1
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEB.MODE LOGIC
enum: SLICEB.CCU2.INJECT1_0 _NONE_
enum: SLICEB.A0MUX 1
enum: SLICEB.B0MUX 1
enum: SLICEB.C0MUX 1
enum: SLICEB.D0MUX 1
enum: SLICEB.MODE LOGIC
enum: SLICEB.CCU2.INJECT1_1 _NONE_
enum: SLICEA.MODE LOGIC
enum: SLICEA.CCU2.INJECT1_1 _NONE_
enum: SLICEA.A1MUX 1
enum: SLICEA.B1MUX 1
enum: SLICED.MODE LOGIC
enum: SLICED.CCU2.INJECT1_1 _NONE_
enum: SLICED.A1MUX 1
enum: SLICED.C1MUX 1
.tile R6C36:PLC2
arc: E1_H02E0101 V06S0103
arc: E1_H02E0201 W1_H02E0201
arc: E1_H02E0301 H01E0101
arc: E1_H02E0401 V06S0203
arc: E1_H02E0501 N1_V02S0501
arc: E1_H02E0601 W1_H02E0601
arc: H00L0000 E1_H02W0001
arc: N1_V02N0101 V01N0101
arc: N1_V02N0301 H02W0301
arc: N1_V02N0501 H06E0303
arc: N1_V02N0601 V01N0001
arc: N1_V02N0701 H02W0701
arc: N3_V06N0303 E1_H01W0100
arc: S1_V02S0201 E1_H02W0201
arc: S1_V02S0601 H02E0601
arc: V00B0000 H02W0401
arc: V00B0100 N1_V02S0101
arc: V00T0000 H02E0001
arc: W1_H02W0001 E1_H02W0501
arc: W1_H02W0201 V06S0103
arc: W1_H02W0301 V01N0101
arc: W1_H02W0601 V01N0001
arc: W3_H06W0303 E1_H01W0100
arc: A0 F5
arc: A1 H02E0701
arc: A2 F5
arc: A3 F5
arc: A4 V02N0301
arc: A6 F7
arc: A7 H02E0501
arc: B1 H00R0100
arc: B5 H00L0000
arc: B6 N1_V02S0501
arc: B7 N1_V01S0000
arc: C0 E1_H01W0000
arc: C1 E1_H01W0000
arc: C2 E1_H01W0000
arc: C3 E1_H01W0000
arc: C4 E1_H02W0601
arc: C5 V01N0101
arc: C6 W1_H02E0401
arc: C7 V02S0001
arc: CE2 H02E0101
arc: CLK0 G_HPBX0000
arc: D0 H02E0201
arc: D1 H02E0201
arc: D2 H02E0201
arc: D3 H02E0201
arc: D4 V00B0000
arc: D5 V02N0601
arc: D6 N1_V02S0401
arc: D7 E1_H01W0100
arc: E1_H01E0001 F1
arc: E1_H01E0101 F7
arc: F0 F5A_SLICE
arc: F1 FXA_SLICE
arc: F2 F5B_SLICE
arc: F4 F4_SLICE
arc: F5 F5_SLICE
arc: F6 F6_SLICE
arc: F7 F7_SLICE
arc: H00R0100 F5
arc: LSR0 V00B0100
arc: M0 H01E0001
arc: M1 H02W0001
arc: M2 V00T0000
arc: MUXCLK2 CLK0
arc: MUXLSR2 LSR0
arc: N1_V01N0001 F6
arc: N1_V01N0101 Q4
arc: N1_V02N0401 F6
arc: S1_V02S0701 F5
arc: V01S0100 F5
word: SLICED.K0.INIT 1000000000000000
word: SLICEC.K1.INIT 1100000000000000
word: SLICED.K1.INIT 0000000000000001
word: SLICEC.K0.INIT 1111101011110000
word: SLICEA.K0.INIT 0000111110101111
word: SLICEA.K1.INIT 0000111101001111
word: SLICEB.K0.INIT 0000111110101111
word: SLICEB.K1.INIT 0000111110101111
enum: SLICED.MODE LOGIC
enum: SLICED.CCU2.INJECT1_0 _NONE_
enum: SLICEC.MODE LOGIC
enum: SLICEC.CCU2.INJECT1_1 _NONE_
enum: SLICEC.A1MUX 1
enum: SLICED.MODE LOGIC
enum: SLICED.CCU2.INJECT1_1 _NONE_
enum: SLICEC.MODE LOGIC
enum: SLICEC.CCU2.INJECT1_0 _NONE_
enum: SLICEC.B0MUX 1
enum: SLICEC.GSR DISABLED
enum: SLICEC.REG0.SD 1
enum: SLICEC.REG0.REGSET RESET
enum: SLICEC.REG0.LSRMODE LSR
enum: SLICEC.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEA.MODE LOGIC
enum: SLICEA.CCU2.INJECT1_0 _NONE_
enum: SLICEA.B0MUX 1
enum: SLICEA.MODE LOGIC
enum: SLICEA.CCU2.INJECT1_1 _NONE_
enum: SLICEB.MODE LOGIC
enum: SLICEB.CCU2.INJECT1_0 _NONE_
enum: SLICEB.B0MUX 1
enum: SLICEB.MODE LOGIC
enum: SLICEB.CCU2.INJECT1_1 _NONE_
enum: SLICEB.B1MUX 1
.tile R6C37:PLC2
arc: E1_H02E0201 V02N0201
arc: E1_H02E0601 W1_H02E0301
arc: H00L0100 V02S0301
arc: N1_V02N0001 W1_H02E0001
arc: N1_V02N0101 V01N0101
arc: N1_V02N0201 E1_H01W0000
arc: N1_V02N0301 W1_H02E0301
arc: N1_V02N0401 E1_H02W0401
arc: N1_V02N0601 S1_V02N0301
arc: N1_V02N0701 E1_H01W0100
arc: N3_V06N0103 W3_H06E0103
arc: S1_V02S0301 W1_H02E0301
arc: S1_V02S0401 H02E0401
arc: S1_V02S0601 E1_H01W0000
arc: S1_V02S0701 H06E0203
arc: V00B0000 W1_H02E0401
arc: W1_H02W0001 N1_V01S0000
arc: W1_H02W0101 W3_H06E0103
arc: W1_H02W0201 H01E0001
arc: W1_H02W0301 V01N0101
arc: W1_H02W0401 E1_H02W0401
arc: W3_H06W0003 E1_H01W0000
arc: W3_H06W0103 V01N0101
arc: W3_H06W0303 E1_H01W0100
arc: A0 E1_H02W0701
arc: A3 H02E0501
arc: A4 V00B0000
arc: A5 E1_H02W0701
arc: A7 V00T0100
arc: B0 H02E0301
arc: B3 N1_V02S0101
arc: B4 V00B0100
arc: B5 V02S0501
arc: B6 H02E0301
arc: B7 W1_H02E0301
arc: C0 W1_H02E0401
arc: C3 H00R0100
arc: C4 V02N0001
arc: C5 W1_H02E0401
arc: C6 V02N0201
arc: C7 H02W0401
arc: CE0 H00R0000
arc: CE3 H02W0101
arc: CLK0 G_HPBX0000
arc: D0 H02E0201
arc: D2 V00B0100
arc: D3 H01E0101
arc: D4 V01N0001
arc: D5 V02N0601
arc: D7 V02N0401
arc: E1_H01E0001 F7
arc: E1_H01E0101 Q1
arc: E1_H02E0401 F4
arc: E1_H02E0701 F5
arc: F0 F5A_SLICE
arc: F2 F5B_SLICE
arc: F4 F4_SLICE
arc: F5 F5_SLICE
arc: F6 F6_SLICE
arc: F7 F7_SLICE
arc: H00R0000 F6
arc: H00R0100 F7
arc: H01W0000 F0
arc: H01W0100 Q7
arc: M0 V00T0000
arc: M1 H00L0100
arc: M2 H02E0601
arc: M7 E1_H02W0201
arc: MUXCLK0 CLK0
arc: MUXCLK3 CLK0
arc: N1_V01N0001 Q1
arc: N1_V01N0101 F5
arc: N1_V02N0501 Q7
arc: N3_V06N0303 F6
arc: V00B0100 F7
arc: V00T0000 F2
arc: V00T0100 Q1
arc: V01S0000 F7
arc: W1_H02W0501 F5
arc: W1_H02W0601 F6
arc: W1_H02W0701 Q7
word: SLICEB.K0.INIT 1111111100000000
word: SLICEB.K1.INIT 0111000011110000
word: SLICED.K0.INIT 0000110000001100
word: SLICEC.K0.INIT 1111010111000100
word: SLICED.K1.INIT 1111010000000000
word: SLICEC.K1.INIT 0010001100100000
word: SLICEA.K1.INIT 0000000000000000
word: SLICEA.K0.INIT 0100110001011111
enum: SLICEB.MODE LOGIC
enum: SLICEB.CCU2.INJECT1_0 _NONE_
enum: SLICEB.A0MUX 1
enum: SLICEB.B0MUX 1
enum: SLICEB.C0MUX 1
enum: SLICEB.MODE LOGIC
enum: SLICEB.CCU2.INJECT1_1 _NONE_
enum: SLICED.MODE LOGIC
enum: SLICED.CCU2.INJECT1_0 _NONE_
enum: SLICED.A0MUX 1
enum: SLICED.D0MUX 1
enum: SLICEC.MODE LOGIC
enum: SLICEC.CCU2.INJECT1_0 _NONE_
enum: SLICEA.GSR DISABLED
enum: SLICEA.REG1.SD 0
enum: SLICEA.REG1.REGSET RESET
enum: SLICEA.REG1.LSRMODE LSR
enum: SLICEA.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICED.GSR DISABLED
enum: SLICED.REG1.SD 0
enum: SLICED.REG1.REGSET RESET
enum: SLICED.REG1.LSRMODE LSR
enum: SLICED.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICED.MODE LOGIC
enum: SLICED.CCU2.INJECT1_1 _NONE_
enum: SLICEC.MODE LOGIC
enum: SLICEC.CCU2.INJECT1_1 _NONE_
enum: SLICEA.MODE LOGIC
enum: SLICEA.CCU2.INJECT1_1 _NONE_
enum: SLICEA.A1MUX 1
enum: SLICEA.B1MUX 1
enum: SLICEA.C1MUX 1
enum: SLICEA.D1MUX 1
enum: SLICEA.MODE LOGIC
enum: SLICEA.CCU2.INJECT1_0 _NONE_
.tile R6C38:PLC2
arc: E1_H02E0101 W1_H02E0101
arc: E1_H02E0401 W1_H02E0401
arc: H00R0000 H02E0401
arc: H00R0100 H02E0701
arc: N1_V02N0001 N1_V01S0000
arc: N1_V02N0101 H06E0103
arc: N1_V02N0501 H01E0101
arc: N1_V02N0601 H01E0001
arc: N1_V02N0701 H01E0101
arc: S1_V02S0001 E1_H01W0000
arc: S1_V02S0101 H06E0103
arc: S1_V02S0301 V01N0101
arc: S1_V02S0701 N1_V01S0100
arc: V00B0100 V02N0301
arc: V00T0000 H02E0201
arc: V00T0100 V02S0501
arc: W1_H02W0101 V02N0101
arc: W1_H02W0501 E1_H02W0501
arc: W1_H02W0601 V01N0001
arc: A0 F5
arc: A2 F7
arc: A3 F7
arc: A5 V00B0000
arc: A6 H02E0701
arc: B0 V01N0001
arc: B1 V00B0000
arc: B2 V01N0001
arc: B3 V02N0301
arc: B5 N1_V01S0000
arc: B6 F1
arc: B7 F1
arc: C0 H00L0000
arc: C1 H02E0601
arc: C3 H00L0000
arc: C4 V00B0100
arc: C5 N1_V02S0001
arc: C6 V00B0100
arc: C7 V02N0201
arc: CE0 H00R0000
arc: CE2 H00R0100
arc: CLK0 G_HPBX0000
arc: D0 V00T0100
arc: D1 H01E0101
arc: D2 V00B0100
arc: D3 V02N0201
arc: D4 H02W0001
arc: D5 H02W0001
arc: D6 V02N0401
arc: E1_H01E0001 Q4
arc: E1_H01E0101 F2
arc: F0 F0_SLICE
arc: F1 F1_SLICE
arc: F2 F5B_SLICE
arc: F4 F4_SLICE
arc: F5 F5_SLICE
arc: F6 F6_SLICE
arc: F7 F7_SLICE
arc: H00L0000 Q0
arc: H01W0000 F2
arc: H01W0100 F2
arc: LSR0 V00T0000
arc: LSR1 V00T0000
arc: M2 N1_V01N0001
arc: MUXCLK0 CLK0
arc: MUXCLK2 CLK0
arc: MUXCLK3 CLK0
arc: MUXLSR0 LSR1
arc: MUXLSR2 LSR0
arc: MUXLSR3 LSR0
arc: N1_V01N0001 F5
arc: N1_V01N0101 Q0
arc: N1_V02N0201 F2
arc: N1_V02N0401 F4
arc: S1_V02S0201 F2
arc: V00B0000 Q6
arc: V01S0000 Q4
arc: V01S0100 F7
arc: W1_H02W0001 Q0
arc: W1_H02W0201 F2
arc: W1_H02W0401 Q6
arc: W3_H06W0103 F2
word: SLICEB.K0.INIT 0000000001000100
word: SLICEB.K1.INIT 0001010100000100
word: SLICEC.K0.INIT 0000000011110000
word: SLICEA.K1.INIT 0011001100000011
word: SLICEA.K0.INIT 1111111011001100
word: SLICEC.K1.INIT 0000110000001010
word: SLICED.K1.INIT 1100000011000000
word: SLICED.K0.INIT 0011000100010001
enum: SLICEA.GSR DISABLED
enum: SLICEA.REG0.SD 1
enum: SLICEA.REG0.REGSET RESET
enum: SLICEA.REG0.LSRMODE LSR
enum: SLICEA.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEB.MODE LOGIC
enum: SLICEB.CCU2.INJECT1_0 _NONE_
enum: SLICEB.C0MUX 1
enum: SLICEB.MODE LOGIC
enum: SLICEB.CCU2.INJECT1_1 _NONE_
enum: SLICEC.GSR DISABLED
enum: SLICEC.REG0.SD 1
enum: SLICEC.REG0.REGSET RESET
enum: SLICEC.REG0.LSRMODE LSR
enum: SLICEC.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEC.MODE LOGIC
enum: SLICEC.CCU2.INJECT1_0 _NONE_
enum: SLICEC.A0MUX 1
enum: SLICEC.B0MUX 1
enum: SLICEA.MODE LOGIC
enum: SLICEA.CCU2.INJECT1_1 _NONE_
enum: SLICEA.A1MUX 1
enum: SLICEA.MODE LOGIC
enum: SLICEA.CCU2.INJECT1_0 _NONE_
enum: SLICEC.MODE LOGIC
enum: SLICEC.CCU2.INJECT1_1 _NONE_
enum: SLICED.MODE LOGIC
enum: SLICED.CCU2.INJECT1_1 _NONE_
enum: SLICED.A1MUX 1
enum: SLICED.D1MUX 1
enum: SLICED.MODE LOGIC
enum: SLICED.CCU2.INJECT1_0 _NONE_
enum: SLICED.GSR DISABLED
enum: SLICED.REG0.SD 1
enum: SLICED.REG0.REGSET RESET
enum: SLICED.REG0.LSRMODE LSR
enum: SLICED.CEMUX 1
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
.tile R6C39:PLC2
arc: E1_H02E0101 V02N0101
arc: N1_V02N0101 H01E0101
arc: W1_H02W0001 H01E0001
arc: W1_H02W0201 S1_V02N0201
arc: W1_H02W0401 H01E0001
arc: W1_H02W0701 V01N0101
arc: B0 V02N0101
arc: B2 V02N0101
arc: C0 H02W0401
arc: C2 N1_V01S0100
arc: CE0 H02E0101
arc: CE1 H02E0101
arc: CLK0 G_HPBX0000
arc: D0 Q0
arc: D2 Q2
arc: F0 F0_SLICE
arc: F2 F2_SLICE
arc: H01W0000 Q0
arc: MUXCLK0 CLK0
arc: MUXCLK1 CLK0
arc: S1_V02S0001 Q0
arc: S3_V06S0003 Q0
arc: W3_H06W0103 Q2
word: SLICEB.K0.INIT 1111110000110000
word: SLICEA.K0.INIT 1111110000110000
enum: SLICEB.MODE LOGIC
enum: SLICEB.CCU2.INJECT1_0 _NONE_
enum: SLICEB.A0MUX 1
enum: SLICEA.MODE LOGIC
enum: SLICEA.CCU2.INJECT1_0 _NONE_
enum: SLICEA.A0MUX 1
enum: SLICEB.GSR DISABLED
enum: SLICEB.REG0.SD 1
enum: SLICEB.REG0.REGSET RESET
enum: SLICEB.REG0.LSRMODE LSR
enum: SLICEB.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEA.GSR DISABLED
enum: SLICEA.REG0.SD 1
enum: SLICEA.REG0.REGSET RESET
enum: SLICEA.REG0.LSRMODE LSR
enum: SLICEA.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
.tile R6C40:PLC2
arc: H00R0000 W1_H02E0401
arc: W1_H02W0401 V02S0401
arc: W1_H02W0501 W3_H06E0303
arc: B2 H02E0101
arc: C2 V02S0401
arc: CE1 H00R0000
arc: CLK0 G_HPBX0000
arc: D2 Q2
arc: F2 F2_SLICE
arc: MUXCLK1 CLK0
arc: V01S0000 Q2
word: SLICEB.K0.INIT 1111110000110000
enum: SLICEB.GSR DISABLED
enum: SLICEB.REG0.SD 1
enum: SLICEB.REG0.REGSET RESET
enum: SLICEB.REG0.LSRMODE LSR
enum: SLICEB.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEB.MODE LOGIC
enum: SLICEB.CCU2.INJECT1_0 _NONE_
enum: SLICEB.A0MUX 1
.tile R6C41:PLC2
arc: N1_V02N0101 W3_H06E0103
arc: N1_V02N0201 W3_H06E0103
.tile R7C30:PLC2
arc: N1_V02N0301 E3_H06W0003
arc: S1_V02S0301 E1_H02W0301
arc: S1_V02S0601 H06W0303
.tile R7C31:PLC2
arc: H00L0000 V02S0201
arc: H00L0100 V02N0301
arc: H00R0000 E1_H02W0401
arc: H00R0100 E1_H02W0701
arc: N1_V02N0301 H02W0301
arc: N1_V02N0501 E1_H02W0501
arc: N1_V02N0601 H06W0303
arc: V00B0000 V02N0001
arc: V00B0100 V02S0101
arc: A1 H00R0000
arc: B1 V00B0000
arc: B3 E1_H02W0101
arc: B4 V02N0501
arc: C0 V02S0401
arc: C1 N1_V01S0100
arc: C2 E1_H01W0000
arc: C3 H02W0601
arc: C4 Q4
arc: CE0 H02W0101
arc: CE1 H00R0100
arc: CE2 H00L0100
arc: CE3 H00R0100
arc: CLK0 G_HPBX0000
arc: D1 E1_H02W0201
arc: D2 V00B0100
arc: D3 V00B0100
arc: D4 H01W0000
arc: E1_H01E0101 Q2
arc: E1_H02E0001 Q2
arc: F0 F0_SLICE
arc: F1 F1_SLICE
arc: F2 F2_SLICE
arc: F3 F3_SLICE
arc: F4 F4_SLICE
arc: H01W0000 Q7
arc: LSR1 H02W0301
arc: M4 H02W0401
arc: M7 H00L0000
arc: MUXCLK0 CLK0
arc: MUXCLK1 CLK0
arc: MUXCLK2 CLK0
arc: MUXCLK3 CLK0
arc: MUXLSR0 LSR1
arc: MUXLSR1 LSR1
arc: MUXLSR2 LSR1
arc: MUXLSR3 LSR1
arc: N1_V01N0101 Q2
arc: S1_V02S0101 F3
arc: S1_V02S0401 F4
arc: V01S0000 F1
arc: V01S0100 Q0
word: SLICEA.K0.INIT 0000111100001111
word: SLICEB.K0.INIT 0000000011110000
word: SLICEC.K0.INIT 1111001111000000
word: SLICEB.K1.INIT 1111001111110000
word: SLICEA.K1.INIT 1100010011000000
enum: SLICED.GSR DISABLED
enum: SLICED.REG1.SD 0
enum: SLICED.REG1.REGSET RESET
enum: SLICED.REG1.LSRMODE LSR
enum: SLICED.CEMUX CE
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEA.MODE LOGIC
enum: SLICEA.CCU2.INJECT1_0 _NONE_
enum: SLICEA.A0MUX 1
enum: SLICEA.B0MUX 1
enum: SLICEA.D0MUX 1
enum: SLICEA.GSR DISABLED
enum: SLICEA.REG0.SD 1
enum: SLICEA.REG0.REGSET RESET
enum: SLICEA.REG0.LSRMODE LSR
enum: SLICEA.CEMUX CE
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEC.GSR DISABLED
enum: SLICEC.REG0.SD 0
enum: SLICEC.REG0.REGSET RESET
enum: SLICEC.REG0.LSRMODE LSR
enum: SLICEC.CEMUX CE
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEB.MODE LOGIC
enum: SLICEB.CCU2.INJECT1_0 _NONE_
enum: SLICEB.A0MUX 1
enum: SLICEB.B0MUX 1
enum: SLICEB.GSR DISABLED
enum: SLICEB.REG0.SD 1
enum: SLICEB.REG0.REGSET RESET
enum: SLICEB.REG0.LSRMODE LSR
enum: SLICEB.CEMUX CE
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEC.MODE LOGIC
enum: SLICEC.CCU2.INJECT1_0 _NONE_
enum: SLICEC.A0MUX 1
enum: SLICEB.MODE LOGIC
enum: SLICEB.CCU2.INJECT1_1 _NONE_
enum: SLICEB.A1MUX 1
enum: SLICEA.MODE LOGIC
enum: SLICEA.CCU2.INJECT1_1 _NONE_
.tile R7C32:PLC2
arc: E1_H02E0001 N3_V06S0003
arc: E1_H02E0101 N1_V01S0100
arc: E1_H02E0301 N3_V06S0003
arc: E1_H02E0601 N1_V01S0000
arc: N1_V01N0001 N3_V06S0003
arc: N1_V02N0001 H02E0001
arc: N1_V02N0301 N3_V06S0003
arc: N1_V02N0501 H06W0303
arc: N1_V02N0601 H06W0303
arc: S1_V02S0001 N3_V06S0003
arc: S1_V02S0301 H02W0301
arc: V00B0000 V02N0001
arc: V00T0000 V02S0601
arc: W1_H02W0101 V01N0101
arc: W1_H02W0301 N3_V06S0003
arc: W1_H02W0401 V06S0203
arc: W1_H02W0601 V02S0601
arc: A5 N1_V01S0100
arc: B0 V00B0000
arc: B6 H01E0101
arc: B7 N1_V01S0000
arc: CE0 V02N0201
arc: CLK0 G_HPBX0000
arc: F6 F6_SLICE
arc: H01W0000 F6
arc: LSR0 V00T0000
arc: M0 H02W0601
arc: MUXCLK0 CLK0
arc: MUXLSR0 LSR0
arc: V01S0000 Q0
word: SLICED.K1.INIT 0011001100110000
word: SLICED.K0.INIT 0011001100110000
word: SLICEC.K1.INIT 0101010101010000
word: SLICEC.K0.INIT 1111111111110000
word: SLICEB.K1.INIT 1111111111110000
word: SLICEB.K0.INIT 1111111111110000
word: SLICEA.K1.INIT 1111111111111111
word: SLICEA.K0.INIT 0000000000001100
enum: SLICED.MODE CCU2
enum: SLICED.CCU2.INJECT1_1 NO
enum: SLICED.A1MUX 1
enum: SLICED.C1MUX 1
enum: SLICED.D1MUX 1
enum: SLICED.MODE CCU2
enum: SLICED.CCU2.INJECT1_0 NO
enum: SLICED.A0MUX 1
enum: SLICED.C0MUX 1
enum: SLICED.D0MUX 1
enum: SLICEC.MODE CCU2
enum: SLICEC.CCU2.INJECT1_1 NO
enum: SLICEC.B1MUX 1
enum: SLICEC.C1MUX 1
enum: SLICEC.D1MUX 1
enum: SLICEC.MODE CCU2
enum: SLICEC.CCU2.INJECT1_0 NO
enum: SLICEC.A0MUX 1
enum: SLICEC.B0MUX 1
enum: SLICEC.C0MUX 1
enum: SLICEC.D0MUX 1
enum: SLICEB.MODE CCU2
enum: SLICEB.CCU2.INJECT1_1 NO
enum: SLICEB.A1MUX 1
enum: SLICEB.B1MUX 1
enum: SLICEB.C1MUX 1
enum: SLICEB.D1MUX 1
enum: SLICEB.MODE CCU2
enum: SLICEB.CCU2.INJECT1_0 NO
enum: SLICEB.A0MUX 1
enum: SLICEB.B0MUX 1
enum: SLICEB.C0MUX 1
enum: SLICEB.D0MUX 1
enum: SLICEA.MODE CCU2
enum: SLICEA.CCU2.INJECT1_1 YES
enum: SLICEA.A1MUX 1
enum: SLICEA.B1MUX 1
enum: SLICEA.C1MUX 1
enum: SLICEA.D1MUX 1
enum: SLICEA.MODE CCU2
enum: SLICEA.CCU2.INJECT1_0 NO
enum: SLICEA.A0MUX 1
enum: SLICEA.C0MUX 1
enum: SLICEA.D0MUX 1
enum: SLICEA.GSR DISABLED
enum: SLICEA.REG0.SD 0
enum: SLICEA.REG0.REGSET RESET
enum: SLICEA.REG0.LSRMODE LSR
enum: SLICEA.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: CLK0.CLKMUX CLK
.tile R7C33:PLC2
arc: E1_H02E0001 N1_V02S0001
arc: E1_H02E0101 N1_V01S0100
arc: E1_H02E0201 S1_V02N0201
arc: E1_H02E0401 V01N0001
arc: H00R0000 E1_H02W0601
arc: N1_V02N0201 S1_V02N0201
arc: N1_V02N0401 H06W0203
arc: N1_V02N0701 H06W0203
arc: S1_V02S0001 N1_V02S0001
arc: S1_V02S0301 H06W0003
arc: S1_V02S0701 E1_H02W0701
arc: W1_H02W0101 E1_H01W0100
arc: W1_H02W0201 E1_H01W0000
arc: W1_H02W0301 E3_H06W0003
arc: W1_H02W0501 E1_H01W0100
arc: W1_H02W0601 V02S0601
arc: W1_H02W0701 E1_H02W0601
arc: W3_H06W0303 E1_H01W0100
arc: A4 E1_H01W0000
arc: A6 F5
arc: B0 V00B0000
arc: B4 V01S0000
arc: B5 H02E0101
arc: C4 V02S0201
arc: C5 H02E0601
arc: CE2 H00R0000
arc: CLK0 G_HPBX0000
arc: D4 H00R0100
arc: D5 W1_H02E0001
arc: D6 V00B0000
arc: E1_H01E0101 F6
arc: E1_H02E0301 F1
arc: E1_H02E0601 F6
arc: E3_H06E0103 F1
arc: F1 F1_SLICE
arc: F4 F4_SLICE
arc: F5 F5_SLICE
arc: F6 F6_SLICE
arc: H00R0100 F5
arc: LSR1 H02E0301
arc: MUXCLK2 CLK0
arc: MUXLSR2 LSR1
arc: N1_V01N0001 F6
arc: N1_V02N0601 F6
arc: N3_V06N0103 F1
arc: V00B0000 Q4
arc: V01S0000 Q4
arc: V01S0100 Q4
arc: W1_H02W0401 F6
word: SLICEB.K1.INIT 0000000000001110
word: SLICEB.K0.INIT 0000000000000000
word: SLICEA.K1.INIT 1111111111110000
word: SLICEA.K0.INIT 0011001100110000
word: SLICEC.K1.INIT 1100000000000000
word: SLICED.K0.INIT 0000000010101010
word: SLICEC.K0.INIT 0010001011001000
enum: SLICEB.MODE CCU2
enum: SLICEB.CCU2.INJECT1_1 NO
enum: SLICEB.A1MUX 1
enum: SLICEB.B1MUX 1
enum: SLICEB.C1MUX 1
enum: SLICEB.D1MUX 1
enum: SLICEB.MODE CCU2
enum: SLICEB.CCU2.INJECT1_0 NO
enum: SLICEB.A0MUX 1
enum: SLICEB.B0MUX 1
enum: SLICEB.C0MUX 1
enum: SLICEB.D0MUX 1
enum: SLICEA.MODE CCU2
enum: SLICEA.CCU2.INJECT1_1 NO
enum: SLICEA.A1MUX 1
enum: SLICEA.B1MUX 1
enum: SLICEA.C1MUX 1
enum: SLICEA.D1MUX 1
enum: SLICEA.MODE CCU2
enum: SLICEA.CCU2.INJECT1_0 NO
enum: SLICEA.A0MUX 1
enum: SLICEA.C0MUX 1
enum: SLICEA.D0MUX 1
enum: SLICEC.MODE LOGIC
enum: SLICEC.CCU2.INJECT1_1 _NONE_
enum: SLICEC.A1MUX 1
enum: SLICED.MODE LOGIC
enum: SLICED.CCU2.INJECT1_0 _NONE_
enum: SLICED.B0MUX 1
enum: SLICED.C0MUX 1
enum: SLICEC.MODE LOGIC
enum: SLICEC.CCU2.INJECT1_0 _NONE_
enum: SLICEC.GSR DISABLED
enum: SLICEC.REG0.SD 1
enum: SLICEC.REG0.REGSET RESET
enum: SLICEC.REG0.LSRMODE LSR
enum: SLICEC.CEMUX CE
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
.tile R7C34:PLC2
arc: E1_H02E0001 N1_V01S0000
arc: H00L0000 H02W0201
arc: H00R0000 N1_V02S0401
arc: H00R0100 E1_H02W0701
arc: N1_V02N0001 E1_H01W0000
arc: N1_V02N0101 H01E0101
arc: N1_V02N0201 S1_V02N0201
arc: N1_V02N0301 H01E0101
arc: N1_V02N0401 H06W0203
arc: S1_V02S0101 N3_V06S0103
arc: S1_V02S0201 N1_V01S0000
arc: S1_V02S0701 H02W0701
arc: V00T0000 H02E0001
arc: A1 E1_H01E0001
arc: A2 H02W0501
arc: A4 N1_V01S0100
arc: A6 V00T0100
arc: A7 Q7
arc: B1 W1_H02E0301
arc: B2 H02E0301
arc: B3 V02S0301
arc: B4 W1_H02E0301
arc: B6 E1_H02W0101
arc: B7 E1_H02W0301
arc: C0 N1_V01N0001
arc: C1 H02E0401
arc: C3 H00L0000
arc: C4 Q4
arc: C6 V00B0100
arc: C7 V00T0000
arc: CE0 H00R0000
arc: CE1 H00R0100
arc: CE3 N1_V02S0601
arc: CLK0 G_HPBX0000
arc: D0 W1_H02E0001
arc: D1 V02S0201
arc: D2 Q2
arc: D3 V01S0100
arc: D4 H02W0001
arc: D6 H02E0001
arc: D7 H00L0100
arc: E1_H01E0001 Q5
arc: E1_H01E0101 Q4
arc: E1_H02E0601 Q4
arc: E1_H02E0701 Q5
arc: F0 F5A_SLICE
arc: F2 F2_SLICE
arc: F3 F3_SLICE
arc: F4 F4_SLICE
arc: F6 F5D_SLICE
arc: H00L0100 Q1
arc: H01W0000 Q5
arc: H01W0100 Q4
arc: M0 H02E0601
arc: M1 H00L0000
arc: M5 V01S0000
arc: M6 N1_V01N0101
arc: M7 H02W0201
arc: MUXCLK0 CLK0
arc: MUXCLK1 CLK0
arc: MUXCLK2 CLK0
arc: MUXCLK3 CLK0
arc: N1_V01N0001 Q5
arc: N1_V01N0101 F3
arc: N1_V02N0501 Q5
arc: N1_V02N0701 Q5
arc: S1_V02S0001 Q2
arc: S1_V02S0401 Q4
arc: S1_V02S0601 F6
arc: V00B0100 Q7
arc: V00T0100 Q1
arc: V01S0000 F0
arc: V01S0100 Q7
arc: W3_H06W0303 Q5
word: SLICEA.K1.INIT 0011001000000010
word: SLICEA.K0.INIT 0000000011110000
word: SLICEB.K1.INIT 1111001111000000
word: SLICED.K0.INIT 1000100011000000
word: SLICED.K1.INIT 1111101100111011
word: SLICEB.K0.INIT 1110111000100010
word: SLICEC.K0.INIT 1110111011111110
enum: SLICEC.GSR DISABLED
enum: SLICEC.REG0.SD 1
enum: SLICEC.REG0.REGSET RESET
enum: SLICEC.REG0.LSRMODE LSR
enum: SLICEC.CEMUX 1
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEC.GSR DISABLED
enum: SLICEC.REG1.SD 0
enum: SLICEC.REG1.REGSET RESET
enum: SLICEC.REG1.LSRMODE LSR
enum: SLICEC.CEMUX 1
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEA.MODE LOGIC
enum: SLICEA.CCU2.INJECT1_1 _NONE_
enum: SLICEA.MODE LOGIC
enum: SLICEA.CCU2.INJECT1_0 _NONE_
enum: SLICEA.A0MUX 1
enum: SLICEA.B0MUX 1
enum: SLICEB.MODE LOGIC
enum: SLICEB.CCU2.INJECT1_1 _NONE_
enum: SLICEB.A1MUX 1
enum: SLICED.MODE LOGIC
enum: SLICED.CCU2.INJECT1_0 _NONE_
enum: SLICED.MODE LOGIC
enum: SLICED.CCU2.INJECT1_1 _NONE_
enum: SLICEA.GSR DISABLED
enum: SLICEA.REG1.SD 0
enum: SLICEA.REG1.REGSET RESET
enum: SLICEA.REG1.LSRMODE LSR
enum: SLICEA.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICED.GSR DISABLED
enum: SLICED.REG1.SD 0
enum: SLICED.REG1.REGSET RESET
enum: SLICED.REG1.LSRMODE LSR
enum: SLICED.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEB.MODE LOGIC
enum: SLICEB.CCU2.INJECT1_0 _NONE_
enum: SLICEB.C0MUX 1
enum: SLICEB.GSR DISABLED
enum: SLICEB.REG0.SD 1
enum: SLICEB.REG0.REGSET RESET
enum: SLICEB.REG0.LSRMODE LSR
enum: SLICEB.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEC.MODE LOGIC
enum: SLICEC.CCU2.INJECT1_0 _NONE_
.tile R7C35:PLC2
arc: E1_H02E0201 W1_H02E0201
arc: E1_H02E0401 N1_V01S0000
arc: E1_H02E0601 N1_V01S0000
arc: E1_H02E0701 N1_V02S0701
arc: H00L0000 V02S0001
arc: H00L0100 H02W0101
arc: H00R0000 V02S0401
arc: H00R0100 H02E0701
arc: N1_V02N0001 H01E0001
arc: N1_V02N0201 S1_V02N0201
arc: N1_V02N0301 E1_H01W0100
arc: N1_V02N0701 E1_H01W0100
arc: S1_V02S0101 E1_H02W0101
arc: S1_V02S0401 E1_H02W0401
arc: S1_V02S0501 N1_V01S0100
arc: S1_V02S0701 E1_H01W0100
arc: V00T0100 N1_V02S0501
arc: W1_H02W0001 V02S0001
arc: W1_H02W0201 E1_H02W0201
arc: W1_H02W0501 N1_V02S0501
arc: W1_H02W0701 N1_V01S0100
arc: A0 V02S0701
arc: A2 H00L0100
arc: A6 F7
arc: A7 H00L0000
arc: B0 W1_H02E0301
arc: B1 E1_H02W0101
arc: B2 W1_H02E0101
arc: B3 E1_H02W0101
arc: B4 F3
arc: B7 H01E0101
arc: C1 H02E0601
arc: C2 E1_H02W0601
arc: C3 N1_V01N0001
arc: C4 V02N0001
arc: C6 W1_H02E0601
arc: C7 V02N0001
arc: CE0 V02S0201
arc: CE1 H00R0000
arc: CLK0 G_HPBX0000
arc: D0 V00T0100
arc: D1 H02E0001
arc: D2 W1_H02E0201
arc: D3 E1_H02W0001
arc: D4 V02N0401
arc: D6 H00R0100
arc: D7 V02S0601
arc: E1_H01E0001 Q4
arc: F0 F0_SLICE
arc: F1 F1_SLICE
arc: F2 F2_SLICE
arc: F3 F3_SLICE
arc: F4 F4_SLICE
arc: F6 F6_SLICE
arc: F7 F7_SLICE
arc: H01W0000 Q2
arc: M7 E1_H01W0000
arc: MUXCLK0 CLK0
arc: MUXCLK1 CLK0
arc: MUXCLK2 CLK0
arc: MUXCLK3 CLK0
arc: N1_V01N0001 Q4
arc: N1_V01N0101 Q0
arc: N1_V02N0101 F1
arc: N1_V02N0401 F6
arc: N1_V02N0601 F6
arc: N3_V06N0003 F3
arc: N3_V06N0303 F6
arc: S1_V02S0001 Q0
arc: V01S0000 Q7
arc: V01S0100 Q7
arc: W1_H02W0601 F6
arc: W3_H06W0303 F6
word: SLICEB.K0.INIT 1100110111001000
word: SLICEA.K0.INIT 1011101110001000
word: SLICEA.K1.INIT 0000000000000011
word: SLICEB.K1.INIT 0011001100000011
word: SLICEC.K0.INIT 1111001100110011
word: SLICED.K0.INIT 0000101010101010
word: SLICED.K1.INIT 1000100010110000
enum: SLICEB.MODE LOGIC
enum: SLICEB.CCU2.INJECT1_0 _NONE_
enum: SLICEA.MODE LOGIC
enum: SLICEA.CCU2.INJECT1_0 _NONE_
enum: SLICEA.C0MUX 1
enum: SLICED.GSR DISABLED
enum: SLICED.REG1.SD 0
enum: SLICED.REG1.REGSET RESET
enum: SLICED.REG1.LSRMODE LSR
enum: SLICED.CEMUX 1
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEA.MODE LOGIC
enum: SLICEA.CCU2.INJECT1_1 _NONE_
enum: SLICEA.A1MUX 1
enum: SLICEC.GSR DISABLED
enum: SLICEC.REG0.SD 1
enum: SLICEC.REG0.REGSET RESET
enum: SLICEC.REG0.LSRMODE LSR
enum: SLICEC.CEMUX 1
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEB.MODE LOGIC
enum: SLICEB.CCU2.INJECT1_1 _NONE_
enum: SLICEB.A1MUX 1
enum: SLICEC.MODE LOGIC
enum: SLICEC.CCU2.INJECT1_0 _NONE_
enum: SLICEC.A0MUX 1
enum: SLICEA.GSR DISABLED
enum: SLICEA.REG0.SD 1
enum: SLICEA.REG0.REGSET RESET
enum: SLICEA.REG0.LSRMODE LSR
enum: SLICEA.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICED.MODE LOGIC
enum: SLICED.CCU2.INJECT1_0 _NONE_
enum: SLICED.B0MUX 1
enum: SLICED.MODE LOGIC
enum: SLICED.CCU2.INJECT1_1 _NONE_
enum: SLICEB.GSR DISABLED
enum: SLICEB.REG0.SD 1
enum: SLICEB.REG0.REGSET RESET
enum: SLICEB.REG0.LSRMODE LSR
enum: SLICEB.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
.tile R7C36:PLC2
arc: E1_H02E0001 H01E0001
arc: E1_H02E0101 S1_V02N0101
arc: E1_H02E0401 H01E0001
arc: H00R0100 H02W0701
arc: N1_V02N0001 E1_H01W0000
arc: N1_V02N0101 H06E0103
arc: N1_V02N0401 E1_H01W0000
arc: N1_V02N0601 S1_V02N0301
arc: S1_V02S0001 W1_H02E0001
arc: S1_V02S0101 H02W0101
arc: V00B0100 H02E0701
arc: V00T0100 V02S0701
arc: W1_H02W0701 N1_V02S0701
arc: W3_H06W0203 E1_H01W0000
arc: A0 H02W0501
arc: A1 H02W0501
arc: A2 H02W0501
arc: A3 H02W0501
arc: A5 H02E0701
arc: B0 H02W0101
arc: B1 H02W0101
arc: B2 H02W0101
arc: B3 H02W0101
arc: B4 H02W0101
arc: B5 V02S0701
arc: B6 H02W0101
arc: B7 H02W0101
arc: C1 N1_V01S0100
arc: C5 S1_V02N0001
arc: CLK0 G_HPBX0000
arc: D0 V00T0100
arc: D1 V00B0100
arc: D2 V00T0100
arc: D3 V00T0100
arc: D4 V02N0601
arc: D5 V02N0401
arc: D6 V02N0401
arc: D7 V02N0601
arc: E1_H01E0001 Q3
arc: E1_H02E0301 Q3
arc: E3_H06E0003 Q3
arc: F0 F5A_SLICE
arc: F1 FXA_SLICE
arc: F2 F5B_SLICE
arc: F4 F5C_SLICE
arc: F5 FXC_SLICE
arc: F6 F5D_SLICE
arc: H00L0100 F1
arc: H01W0000 F5
arc: H01W0100 Q3
arc: M0 H02E0601
arc: M1 H00R0100
arc: M2 H02E0601
arc: M3 H00L0100
arc: M4 H02E0401
arc: M5 H00R0100
arc: M6 H02E0401
arc: MUXCLK1 CLK0
arc: N1_V01N0001 Q3
arc: N1_V01N0101 Q3
arc: N1_V02N0301 Q3
arc: N3_V06N0003 Q3
arc: V01S0000 Q3
arc: W1_H02W0101 Q3
arc: W1_H02W0301 Q3
arc: W3_H06W0003 Q3
word: SLICEA.K0.INIT 0011001100010001
word: SLICEA.K1.INIT 0001000100110001
word: SLICEB.K0.INIT 0011001100010001
word: SLICEB.K1.INIT 0011001100010001
word: SLICEC.K0.INIT 0011001100000000
word: SLICEC.K1.INIT 0000111100001000
word: SLICED.K0.INIT 0011001100000000
word: SLICED.K1.INIT 0011001100000000
enum: SLICEB.GSR DISABLED
enum: SLICEB.REG1.SD 0
enum: SLICEB.REG1.REGSET RESET
enum: SLICEB.REG1.LSRMODE LSR
enum: SLICEB.CEMUX 1
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEA.MODE LOGIC
enum: SLICEA.CCU2.INJECT1_0 _NONE_
enum: SLICEA.C0MUX 1
enum: SLICEA.MODE LOGIC
enum: SLICEA.CCU2.INJECT1_1 _NONE_
enum: SLICEB.MODE LOGIC
enum: SLICEB.CCU2.INJECT1_0 _NONE_
enum: SLICEB.C0MUX 1
enum: SLICEB.MODE LOGIC
enum: SLICEB.CCU2.INJECT1_1 _NONE_
enum: SLICEB.C1MUX 1
enum: SLICEC.MODE LOGIC
enum: SLICEC.CCU2.INJECT1_0 _NONE_
enum: SLICEC.A0MUX 1
enum: SLICEC.C0MUX 1
enum: SLICEC.MODE LOGIC
enum: SLICEC.CCU2.INJECT1_1 _NONE_
enum: SLICED.MODE LOGIC
enum: SLICED.CCU2.INJECT1_0 _NONE_
enum: SLICED.A0MUX 1
enum: SLICED.C0MUX 1
enum: SLICED.MODE LOGIC
enum: SLICED.CCU2.INJECT1_1 _NONE_
enum: SLICED.A1MUX 1
enum: SLICED.C1MUX 1
.tile R7C37:PLC2
arc: E1_H02E0101 N3_V06S0103
arc: E1_H02E0401 N1_V02S0401
arc: H00L0100 N1_V02S0101
arc: H00R0000 V02S0401
arc: H00R0100 N1_V02S0501
arc: N1_V02N0001 E1_H02W0001
arc: N1_V02N0201 N3_V06S0103
arc: N1_V02N0301 H02E0301
arc: N1_V02N0401 E1_H01W0000
arc: N1_V02N0601 H01E0001
arc: N3_V06N0303 S1_V02N0501
arc: S1_V02S0101 N3_V06S0103
arc: S1_V02S0201 W1_H02E0201
arc: V00B0100 E1_H02W0701
arc: W1_H02W0001 E1_H02W0001
arc: W1_H02W0101 N3_V06S0103
arc: W1_H02W0401 N1_V02S0401
arc: W1_H02W0601 E1_H01W0000
arc: W1_H02W0701 N1_V02S0701
arc: W3_H06W0203 E1_H01W0000
arc: A3 E1_H01E0001
arc: A7 E1_H01W0000
arc: B0 E1_H02W0101
arc: B1 V02N0101
arc: B2 E1_H02W0101
arc: B3 E1_H02W0101
arc: B5 N1_V01S0000
arc: C0 H00L0100
arc: C1 H02E0401
arc: C2 H00L0100
arc: C7 H01E0001
arc: CE0 H02E0101
arc: CE1 H00R0000
arc: CE3 N1_V02S0601
arc: CLK0 G_HPBX0000
arc: D0 Q0
arc: D1 E1_H02W0001
arc: D2 Q2
arc: D3 V00B0100
arc: D5 H00R0100
arc: D7 H02E0001
arc: E1_H01E0001 Q3
arc: E1_H01E0101 F1
arc: F0 F0_SLICE
arc: F1 F1_SLICE
arc: F2 F2_SLICE
arc: F3 F3_SLICE
arc: F5 F5_SLICE
arc: F7 F7_SLICE
arc: H01W0000 F1
arc: M7 H02W0201
arc: MUXCLK0 CLK0
arc: MUXCLK1 CLK0
arc: MUXCLK3 CLK0
arc: N1_V01N0001 F7
arc: N1_V01N0101 F1
arc: N3_V06N0203 F7
arc: S1_V02S0301 Q3
arc: S1_V02S0501 Q7
arc: S1_V02S0701 Q7
arc: V01S0000 Q2
arc: V01S0100 Q3
arc: W1_H02W0201 Q0
arc: W1_H02W0501 F5
word: SLICEA.K0.INIT 1111110000110000
word: SLICEC.K1.INIT 0000000000110011
word: SLICEA.K1.INIT 0011000000000000
word: SLICEB.K0.INIT 1111110000110000
word: SLICEB.K1.INIT 1011101110001000
word: SLICED.K1.INIT 0101010101010000
enum: SLICEA.MODE LOGIC
enum: SLICEA.CCU2.INJECT1_0 _NONE_
enum: SLICEA.A0MUX 1
enum: SLICEA.GSR DISABLED
enum: SLICEA.REG0.SD 1
enum: SLICEA.REG0.REGSET RESET
enum: SLICEA.REG0.LSRMODE LSR
enum: SLICEA.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEC.MODE LOGIC
enum: SLICEC.CCU2.INJECT1_1 _NONE_
enum: SLICEC.A1MUX 1
enum: SLICEC.C1MUX 1
enum: SLICEA.MODE LOGIC
enum: SLICEA.CCU2.INJECT1_1 _NONE_
enum: SLICEA.A1MUX 1
enum: SLICEB.MODE LOGIC
enum: SLICEB.CCU2.INJECT1_0 _NONE_
enum: SLICEB.A0MUX 1
enum: SLICED.GSR DISABLED
enum: SLICED.REG1.SD 0
enum: SLICED.REG1.REGSET RESET
enum: SLICED.REG1.LSRMODE LSR
enum: SLICED.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEB.MODE LOGIC
enum: SLICEB.CCU2.INJECT1_1 _NONE_
enum: SLICEB.C1MUX 1
enum: SLICEB.GSR DISABLED
enum: SLICEB.REG1.SD 1
enum: SLICEB.REG1.REGSET RESET
enum: SLICEB.REG1.LSRMODE LSR
enum: SLICEB.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICED.MODE LOGIC
enum: SLICED.CCU2.INJECT1_1 _NONE_
enum: SLICED.B1MUX 1
enum: SLICEB.GSR DISABLED
enum: SLICEB.REG0.SD 1
enum: SLICEB.REG0.REGSET RESET
enum: SLICEB.REG0.LSRMODE LSR
enum: SLICEB.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
.tile R7C38:PLC2
arc: H00L0000 V02S0001
arc: H00R0100 V02S0701
arc: N1_V02N0101 H01E0101
arc: N1_V02N0301 W1_H02E0301
arc: N1_V02N0401 N1_V01S0000
arc: S1_V02S0301 W1_H02E0301
arc: V00T0100 W1_H02E0301
arc: W1_H02W0201 H01E0001
arc: A0 H00R0000
arc: A1 E1_H01E0001
arc: A4 V02S0101
arc: B0 H01W0100
arc: B1 W1_H02E0301
arc: B2 H02E0101
arc: C0 H02E0401
arc: C1 H02E0401
arc: C2 N1_V01S0100
arc: C4 Q4
arc: CE0 H00R0100
arc: CE2 N1_V02S0601
arc: CE3 V02N0601
arc: CLK0 G_HPBX0000
arc: D0 V00T0100
arc: D1 H00R0000
arc: D2 H01E0101
arc: D4 E1_H02W0201
arc: E1_H01E0001 Q6
arc: F0 F5A_SLICE
arc: F2 F2_SLICE
arc: F4 F4_SLICE
arc: H00R0000 Q4
arc: H01W0000 Q2
arc: H01W0100 Q6
arc: M0 V00B0000
arc: M1 H00L0000
arc: M4 E1_H02W0401
arc: M6 E1_H02W0401
arc: MUXCLK0 CLK0
arc: MUXCLK1 CLK0
arc: MUXCLK2 CLK0
arc: MUXCLK3 CLK0
arc: N1_V01N0001 Q2
arc: N1_V01N0101 F0
arc: N1_V02N0001 Q2
arc: N1_V02N0201 Q2
arc: N3_V06N0103 Q2
arc: V00B0000 F4
arc: V01S0000 Q1
arc: V01S0100 Q1
word: SLICEC.K0.INIT 1111101001010000
word: SLICEA.K0.INIT 1100101000000000
word: SLICEA.K1.INIT 1011111110110011
word: SLICEB.K0.INIT 1111111100110000
enum: SLICEC.MODE LOGIC
enum: SLICEC.CCU2.INJECT1_0 _NONE_
enum: SLICEC.B0MUX 1
enum: SLICEA.MODE LOGIC
enum: SLICEA.CCU2.INJECT1_0 _NONE_
enum: SLICEA.MODE LOGIC
enum: SLICEA.CCU2.INJECT1_1 _NONE_
enum: SLICEB.GSR DISABLED
enum: SLICEB.REG0.SD 1
enum: SLICEB.REG0.REGSET RESET
enum: SLICEB.REG0.LSRMODE LSR
enum: SLICEB.CEMUX 1
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEB.MODE LOGIC
enum: SLICEB.CCU2.INJECT1_0 _NONE_
enum: SLICEB.A0MUX 1
enum: SLICEA.GSR DISABLED
enum: SLICEA.REG1.SD 0
enum: SLICEA.REG1.REGSET RESET
enum: SLICEA.REG1.LSRMODE LSR
enum: SLICEA.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICED.GSR DISABLED
enum: SLICED.REG0.SD 0
enum: SLICED.REG0.REGSET RESET
enum: SLICED.REG0.LSRMODE LSR
enum: SLICED.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEC.GSR DISABLED
enum: SLICEC.REG0.SD 0
enum: SLICEC.REG0.REGSET RESET
enum: SLICEC.REG0.LSRMODE LSR
enum: SLICEC.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
.tile R7C39:PLC2
arc: N1_V02N0001 H06E0003
arc: N1_V02N0101 W3_H06E0103
arc: N1_V02N0201 W3_H06E0103
arc: N1_V02N0601 S1_V02N0301
arc: S1_V02S0101 W1_H02E0101
arc: V00B0100 V02N0101
arc: V00T0000 V02N0401
arc: V00T0100 N1_V02S0701
arc: W1_H02W0101 W3_H06E0103
arc: W1_H02W0701 N1_V02S0701
arc: A0 V02N0501
arc: B0 V00B0000
arc: C0 H00L0000
arc: CLK0 G_HPBX0000
arc: D0 Q0
arc: E1_H01E0101 Q1
arc: F0 F0_SLICE
arc: H00L0000 Q2
arc: H00L0100 Q3
arc: H00R0000 Q6
arc: H00R0100 Q5
arc: LSR0 V00B0100
arc: LSR1 V00B0100
arc: M1 H00L0100
arc: M2 V00T0000
arc: M3 H00R0100
arc: M4 E1_H01E0101
arc: M5 V01S0000
arc: M6 V00T0100
arc: M7 H00R0000
arc: MUXCLK0 CLK0
arc: MUXCLK1 CLK0
arc: MUXCLK2 CLK0
arc: MUXCLK3 CLK0
arc: MUXLSR0 LSR0
arc: MUXLSR1 LSR1
arc: MUXLSR2 LSR1
arc: MUXLSR3 LSR1
arc: N1_V01N0101 Q0
arc: S1_V02S0001 Q0
arc: S1_V02S0401 Q4
arc: V00B0000 Q4
arc: V01S0000 Q7
arc: W1_H02W0001 Q0
arc: W3_H06W0003 Q0
word: SLICEA.K0.INIT 0110100110010110
enum: SLICEB.GSR DISABLED
enum: SLICEB.REG0.SD 0
enum: SLICEB.REG0.REGSET RESET
enum: SLICEB.REG0.LSRMODE LSR
enum: SLICEB.CEMUX 1
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEA.MODE LOGIC
enum: SLICEA.CCU2.INJECT1_0 _NONE_
enum: SLICEA.GSR DISABLED
enum: SLICEA.REG0.SD 1
enum: SLICEA.REG0.REGSET SET
enum: SLICEA.REG0.LSRMODE LSR
enum: SLICEA.CEMUX 1
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEC.GSR DISABLED
enum: SLICEC.REG0.SD 0
enum: SLICEC.REG0.REGSET RESET
enum: SLICEC.REG0.LSRMODE LSR
enum: SLICEC.CEMUX 1
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEA.GSR DISABLED
enum: SLICEA.REG1.SD 0
enum: SLICEA.REG1.REGSET RESET
enum: SLICEA.REG1.LSRMODE LSR
enum: SLICEA.CEMUX 1
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEB.GSR DISABLED
enum: SLICEB.REG1.SD 0
enum: SLICEB.REG1.REGSET RESET
enum: SLICEB.REG1.LSRMODE LSR
enum: SLICEB.CEMUX 1
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEC.GSR DISABLED
enum: SLICEC.REG1.SD 0
enum: SLICEC.REG1.REGSET RESET
enum: SLICEC.REG1.LSRMODE LSR
enum: SLICEC.CEMUX 1
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICED.GSR DISABLED
enum: SLICED.REG1.SD 0
enum: SLICED.REG1.REGSET RESET
enum: SLICED.REG1.LSRMODE LSR
enum: SLICED.CEMUX 1
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICED.GSR DISABLED
enum: SLICED.REG0.SD 0
enum: SLICED.REG0.REGSET RESET
enum: SLICED.REG0.LSRMODE LSR
enum: SLICED.CEMUX 1
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
.tile R7C40:PLC2
arc: W1_H02W0201 N1_V01S0000
arc: W1_H02W0401 N1_V01S0000
.tile R8C12:PLC2
arc: W3_H06W0103 E3_H06W0003
arc: W3_H06W0203 E3_H06W0103
.tile R8C13:PLC2
arc: E3_H06E0103 W3_H06E0003
.tile R8C18:PLC2
arc: W3_H06W0003 E3_H06W0003
arc: W3_H06W0103 E3_H06W0103
.tile R8C19:PLC2
arc: E3_H06E0103 W3_H06E0103
.tile R8C24:PLC2
arc: W3_H06W0003 E3_H06W0003
arc: W3_H06W0103 E3_H06W0103
.tile R8C25:PLC2
arc: E3_H06E0203 W3_H06E0103
.tile R8C28:PLC2
arc: E1_H02E0501 E3_H06W0303
.tile R8C30:PLC2
arc: E1_H02E0401 E3_H06W0203
arc: E1_H02E0601 V02S0601
arc: V00B0100 V02S0301
arc: A0 W1_H02E0501
arc: B0 E1_H02W0101
arc: C0 E1_H02W0401
arc: CLK0 G_HPBX0000
arc: D0 Q0
arc: E1_H02E0001 Q2
arc: E1_H02E0201 Q2
arc: F0 F0_SLICE
arc: LSR0 V00B0100
arc: M2 E1_H02W0601
arc: MUXCLK0 CLK0
arc: MUXCLK1 CLK0
arc: MUXLSR0 LSR0
arc: MUXLSR1 LSR0
arc: W3_H06W0003 Q0
arc: W3_H06W0103 Q2
word: SLICEA.K0.INIT 0110100110010110
enum: SLICEA.MODE LOGIC
enum: SLICEA.CCU2.INJECT1_0 _NONE_
enum: SLICEA.GSR DISABLED
enum: SLICEA.REG0.SD 1
enum: SLICEA.REG0.REGSET RESET
enum: SLICEA.REG0.LSRMODE LSR
enum: SLICEA.CEMUX 1
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEB.GSR DISABLED
enum: SLICEB.REG0.SD 0
enum: SLICEB.REG0.REGSET RESET
enum: SLICEB.REG0.LSRMODE LSR
enum: SLICEB.CEMUX 1
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: CLK0.CLKMUX CLK
.tile R8C31:PLC2
arc: E1_H02E0401 N1_V02S0401
arc: E1_H02E0701 W3_H06E0203
arc: N1_V02N0001 E1_H02W0001
arc: N1_V02N0301 H06W0003
arc: N1_V02N0501 H02W0501
arc: S1_V02S0701 H02W0701
arc: V00B0100 V02S0101
arc: V00T0000 E1_H02W0201
arc: A2 V00T0000
arc: A3 V00T0000
arc: A4 N1_V01S0100
arc: B0 H02W0301
arc: B2 E1_H02W0101
arc: B3 E1_H02W0101
arc: C0 H02E0601
arc: C2 F4
arc: C3 F4
arc: C4 E1_H01E0101
arc: CLK0 G_HPBX0000
arc: D0 N1_V01S0000
arc: D2 H02E0001
arc: D3 H02E0201
arc: D4 E1_H01W0100
arc: E1_H01E0001 F2
arc: E1_H01E0101 Q0
arc: F0 F0_SLICE
arc: F2 F5B_SLICE
arc: F4 F4_SLICE
arc: LSR0 V00B0100
arc: M2 E1_H02W0601
arc: MUXCLK0 CLK0
arc: MUXLSR0 LSR0
word: SLICEC.K0.INIT 1010101000001111
word: SLICEA.K0.INIT 1111111111000000
word: SLICEB.K0.INIT 1001011001101001
word: SLICEB.K1.INIT 0110100110010110
enum: SLICEC.MODE LOGIC
enum: SLICEC.CCU2.INJECT1_0 _NONE_
enum: SLICEC.B0MUX 1
enum: SLICEA.GSR DISABLED
enum: SLICEA.REG0.SD 1
enum: SLICEA.REG0.REGSET RESET
enum: SLICEA.REG0.LSRMODE LSR
enum: SLICEA.CEMUX 1
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEA.MODE LOGIC
enum: SLICEA.CCU2.INJECT1_0 _NONE_
enum: SLICEA.A0MUX 1
enum: SLICEB.MODE LOGIC
enum: SLICEB.CCU2.INJECT1_0 _NONE_
enum: SLICEB.MODE LOGIC
enum: SLICEB.CCU2.INJECT1_1 _NONE_
.tile R8C32:PLC2
arc: E1_H02E0001 V02S0001
arc: E1_H02E0101 N1_V02S0101
arc: H00L0000 H02W0001
arc: H00R0000 E1_H02W0401
arc: N1_V02N0201 E1_H02W0201
arc: N1_V02N0701 H06W0203
arc: S1_V02S0001 H02W0001
arc: S1_V02S0601 N1_V02S0601
arc: V00B0000 N1_V02S0201
arc: V00B0100 V02S0301
arc: V00T0000 N1_V02S0601
arc: W1_H02W0101 E1_H01W0100
arc: W1_H02W0301 N1_V02S0301
arc: W1_H02W0601 H01E0001
arc: A2 F5
arc: A3 V00B0000
arc: A4 F5
arc: A7 F5
arc: B2 V01N0001
arc: B3 V02N0301
arc: B4 N1_V01S0000
arc: B7 E1_H02W0301
arc: C2 W1_H02E0401
arc: C3 N1_V01N0001
arc: C5 H02E0401
arc: CE0 H00R0000
arc: CE1 E1_H02W0101
arc: CE3 E1_H02W0101
arc: CLK0 G_HPBX0000
arc: D2 Q2
arc: D3 F2
arc: D4 N1_V02S0401
arc: D5 E1_H02W0001
arc: D7 H00R0100
arc: E1_H01E0001 F3
arc: E1_H01E0101 F0
arc: E3_H06E0303 F5
arc: F0 F0_SLICE
arc: F2 F2_SLICE
arc: F3 F3_SLICE
arc: F4 F4_SLICE
arc: F5 F5_SLICE
arc: F7 F7_SLICE
arc: H00R0100 Q7
arc: H01W0100 F5
arc: LSR0 V00T0000
arc: LSR1 V00T0000
arc: M2 V00B0100
arc: M7 H00L0000
arc: MUXCLK0 CLK0
arc: MUXCLK1 CLK0
arc: MUXCLK3 CLK0
arc: MUXLSR0 LSR1
arc: MUXLSR1 LSR0
arc: MUXLSR3 LSR0
arc: N1_V01N0001 F5
arc: N1_V01N0101 F5
arc: N1_V02N0001 F0
arc: N3_V06N0303 F5
arc: V01S0100 Q0
arc: W1_H02W0401 F4
arc: W1_H02W0501 F5
arc: W1_H02W0701 F7
word: SLICEB.K1.INIT 0011010111001010
word: SLICEC.K1.INIT 1111111111110000
word: SLICEA.K0.INIT 1111111111111111
word: SLICED.K1.INIT 0110011011001100
word: SLICEC.K0.INIT 1101110110001000
word: SLICEB.K0.INIT 1001011000111100
enum: SLICEB.GSR DISABLED
enum: SLICEB.REG0.SD 0
enum: SLICEB.REG0.REGSET RESET
enum: SLICEB.REG0.LSRMODE LSR
enum: SLICEB.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICED.GSR DISABLED
enum: SLICED.REG1.SD 0
enum: SLICED.REG1.REGSET RESET
enum: SLICED.REG1.LSRMODE LSR
enum: SLICED.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEB.MODE LOGIC
enum: SLICEB.CCU2.INJECT1_1 _NONE_
enum: SLICEA.GSR DISABLED
enum: SLICEA.REG0.SD 1
enum: SLICEA.REG0.REGSET RESET
enum: SLICEA.REG0.LSRMODE LSR
enum: SLICEA.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEC.MODE LOGIC
enum: SLICEC.CCU2.INJECT1_1 _NONE_
enum: SLICEC.A1MUX 1
enum: SLICEC.B1MUX 1
enum: SLICEA.MODE LOGIC
enum: SLICEA.CCU2.INJECT1_0 _NONE_
enum: SLICEA.A0MUX 1
enum: SLICEA.B0MUX 1
enum: SLICEA.C0MUX 1
enum: SLICEA.D0MUX 1
enum: SLICED.MODE LOGIC
enum: SLICED.CCU2.INJECT1_1 _NONE_
enum: SLICED.C1MUX 1
enum: SLICEC.MODE LOGIC
enum: SLICEC.CCU2.INJECT1_0 _NONE_
enum: SLICEC.C0MUX 1
enum: SLICEB.MODE LOGIC
enum: SLICEB.CCU2.INJECT1_0 _NONE_
.tile R8C33:PLC2
arc: E1_H02E0001 N3_V06S0003
arc: E1_H02E0101 N1_V02S0101
arc: E1_H02E0401 W1_H02E0401
arc: H00R0000 E1_H02W0401
arc: H00R0100 V02S0701
arc: N1_V01N0001 N3_V06S0003
arc: N1_V02N0001 H02W0001
arc: N1_V02N0101 H01E0101
arc: N1_V02N0301 H01E0101
arc: N1_V02N0701 N1_V01S0100
arc: S1_V02S0001 E1_H02W0001
arc: S1_V02S0401 N1_V02S0101
arc: S1_V02S0701 W1_H02E0701
arc: V00B0100 E1_H02W0701
arc: V00T0000 H02E0001
arc: V00T0100 V02S0701
arc: W1_H02W0001 N3_V06S0003
arc: W1_H02W0101 E1_H01W0100
arc: W1_H02W0201 E1_H01W0000
arc: W1_H02W0601 H01E0001
arc: A0 E1_H02W0501
arc: A1 E1_H02W0701
arc: A2 V01N0101
arc: A3 V01N0101
arc: A6 N1_V02S0101
arc: B0 V02S0301
arc: B1 V02S0301
arc: B2 V02S0301
arc: B3 V02S0301
arc: B4 H00R0000
arc: C0 S1_V02N0401
arc: C1 S1_V02N0401
arc: C2 E1_H02W0401
arc: C3 E1_H02W0401
arc: C4 V00T0100
arc: C6 V00B0100
arc: CE2 H02E0101
arc: CE3 H02E0101
arc: CLK0 G_HPBX0000
arc: D0 V02S0001
arc: D1 V02S0001
arc: D2 V02S0001
arc: D3 V02S0001
arc: D4 E1_H02W0001
arc: D6 H00R0100
arc: E1_H01E0001 F6
arc: E1_H01E0101 F2
arc: F0 F5A_SLICE
arc: F2 F5B_SLICE
arc: F4 F4_SLICE
arc: F6 F6_SLICE
arc: H00L0000 F0
arc: H01W0100 Q7
arc: LSR0 V00T0000
arc: M0 H02W0601
arc: M2 V00B0000
arc: M4 E1_H01E0101
arc: M7 H00L0000
arc: MUXCLK2 CLK0
arc: MUXCLK3 CLK0
arc: MUXLSR2 LSR0
arc: MUXLSR3 LSR0
arc: V00B0000 F4
arc: V01S0100 Q4
word: SLICED.K0.INIT 1010101011110000
word: SLICEA.K0.INIT 1100000010001000
word: SLICEA.K1.INIT 1111001110111011
word: SLICEC.K0.INIT 1111110000001100
word: SLICEB.K0.INIT 1000100011000000
word: SLICEB.K1.INIT 1011101111110011
enum: SLICED.MODE LOGIC
enum: SLICED.CCU2.INJECT1_0 _NONE_
enum: SLICED.B0MUX 1
enum: SLICEA.MODE LOGIC
enum: SLICEA.CCU2.INJECT1_0 _NONE_
enum: SLICEA.MODE LOGIC
enum: SLICEA.CCU2.INJECT1_1 _NONE_
enum: SLICEC.MODE LOGIC
enum: SLICEC.CCU2.INJECT1_0 _NONE_
enum: SLICEC.A0MUX 1
enum: SLICEB.MODE LOGIC
enum: SLICEB.CCU2.INJECT1_0 _NONE_
enum: SLICEB.MODE LOGIC
enum: SLICEB.CCU2.INJECT1_1 _NONE_
enum: SLICED.GSR DISABLED
enum: SLICED.REG1.SD 0
enum: SLICED.REG1.REGSET RESET
enum: SLICED.REG1.LSRMODE LSR
enum: SLICED.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEC.GSR DISABLED
enum: SLICEC.REG0.SD 0
enum: SLICEC.REG0.REGSET RESET
enum: SLICEC.REG0.LSRMODE LSR
enum: SLICEC.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: CLK0.CLKMUX CLK
.tile R8C34:PLC2
arc: E1_H02E0001 V02S0001
arc: E1_H02E0201 V02S0201
arc: E1_H02E0401 V02S0401
arc: H00L0000 N1_V02S0001
arc: H00R0000 V02S0601
arc: H00R0100 V02S0701
arc: N1_V02N0001 H02E0001
arc: V00B0100 V02S0101
arc: V00T0000 W1_H02E0001
arc: W1_H02W0001 E1_H01W0000
arc: W1_H02W0101 E1_H01W0100
arc: W1_H02W0201 E1_H01W0000
arc: W1_H02W0401 E1_H01W0000
arc: W1_H02W0601 H01E0001
arc: W3_H06W0003 E1_H01W0000
arc: W3_H06W0303 E1_H02W0501
arc: A0 E1_H02W0701
arc: A1 E1_H02W0701
arc: B0 H02W0301
arc: B1 H02W0301
arc: B6 E1_H02W0101
arc: C0 E1_H02W0401
arc: C1 E1_H02W0601
arc: C6 V02S0001
arc: CE0 H00L0000
arc: CE2 N1_V02S0601
arc: CLK0 G_HPBX0000
arc: D0 E1_H02W0001
arc: D1 E1_H02W0001
arc: D6 H00R0100
arc: E1_H02E0301 Q3
arc: F0 F5A_SLICE
arc: F6 F6_SLICE
arc: H01W0000 Q3
arc: H01W0100 Q5
arc: LSR0 V00B0100
arc: LSR1 V00T0000
arc: M0 V00B0000
arc: M1 V01S0100
arc: M3 H02W0201
arc: M5 H00R0000
arc: MUXCLK0 CLK0
arc: MUXCLK1 CLK0
arc: MUXCLK2 CLK0
arc: MUXLSR0 LSR1
arc: MUXLSR1 LSR0
arc: MUXLSR2 LSR1
arc: V00B0000 F6
arc: V01S0100 F0
arc: W1_H02W0301 Q1
word: SLICED.K0.INIT 1111000011001100
word: SLICEA.K0.INIT 1100000010100000
word: SLICEA.K1.INIT 1100111110101111
enum: SLICED.MODE LOGIC
enum: SLICED.CCU2.INJECT1_0 _NONE_
enum: SLICED.A0MUX 1
enum: SLICEA.MODE LOGIC
enum: SLICEA.CCU2.INJECT1_0 _NONE_
enum: SLICEA.MODE LOGIC
enum: SLICEA.CCU2.INJECT1_1 _NONE_
enum: SLICEA.GSR DISABLED
enum: SLICEA.REG1.SD 0
enum: SLICEA.REG1.REGSET RESET
enum: SLICEA.REG1.LSRMODE LSR
enum: SLICEA.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEB.GSR DISABLED
enum: SLICEB.REG1.SD 0
enum: SLICEB.REG1.REGSET RESET
enum: SLICEB.REG1.LSRMODE LSR
enum: SLICEB.CEMUX 1
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEC.GSR DISABLED
enum: SLICEC.REG1.SD 0
enum: SLICEC.REG1.REGSET RESET
enum: SLICEC.REG1.LSRMODE LSR
enum: SLICEC.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
.tile R8C35:PLC2
arc: H00L0000 N1_V02S0001
arc: H00L0100 W1_H02E0101
arc: H00R0000 E1_H02W0401
arc: H00R0100 E1_H02W0501
arc: N1_V02N0001 W1_H02E0001
arc: N1_V02N0301 E1_H01W0100
arc: N1_V02N0401 W1_H02E0401
arc: S1_V02S0001 W1_H02E0001
arc: V00T0000 H02E0001
arc: V00T0100 N1_V02S0701
arc: W1_H02W0001 V02S0001
arc: W1_H02W0201 N1_V01S0000
arc: A0 V02S0701
arc: A1 V02S0701
arc: A4 N1_V01S0100
arc: A7 H00L0000
arc: B0 V01N0001
arc: B1 V01N0001
arc: B2 V02S0101
arc: B3 H02E0301
arc: B4 H02E0301
arc: B6 V02S0501
arc: C0 V02S0401
arc: C1 V02S0401
arc: C2 F4
arc: C3 N1_V01S0100
arc: C4 V02N0001
arc: C6 V00B0100
arc: C7 H02E0401
arc: CE0 H00R0100
arc: CE2 H00R0000
arc: CE3 H00R0000
arc: CLK0 G_HPBX0000
arc: D0 V00B0100
arc: D1 V00B0100
arc: D3 V02N0001
arc: D6 E1_H02W0001
arc: D7 H02E0201
arc: E1_H01E0001 F3
arc: E1_H01E0101 Q6
arc: E1_H02E0001 Q2
arc: E1_H02E0201 F0
arc: E1_H02E0401 F4
arc: E1_H02E0501 F7
arc: E1_H02E0601 F4
arc: F0 F5A_SLICE
arc: F2 F2_SLICE
arc: F3 F3_SLICE
arc: F4 F4_SLICE
arc: F6 F6_SLICE
arc: F7 F7_SLICE
arc: H01W0000 Q2
arc: H01W0100 F4
arc: M0 V00B0000
arc: M1 H02E0001
arc: M4 V00T0100
arc: M5 H00L0100
arc: M6 V00T0000
arc: M7 E1_H02W0201
arc: MUXCLK0 CLK0
arc: MUXCLK1 CLK0
arc: MUXCLK2 CLK0
arc: MUXCLK3 CLK0
arc: N3_V06N0103 Q2
arc: N3_V06N0203 F4
arc: V00B0000 F6
arc: V00B0100 Q7
arc: W1_H02W0301 Q1
arc: W1_H02W0401 Q4
arc: W1_H02W0501 Q5
arc: W1_H02W0701 Q5
arc: W3_H06W0203 F4
word: SLICED.K1.INIT 1010111110100000
word: SLICEA.K0.INIT 1000101010000000
word: SLICEA.K1.INIT 1101111111010101
word: SLICEB.K0.INIT 0011000000110000
word: SLICEB.K1.INIT 0011000011110000
word: SLICEC.K0.INIT 1000000010000000
word: SLICED.K0.INIT 1111110000110000
enum: SLICED.MODE LOGIC
enum: SLICED.CCU2.INJECT1_1 _NONE_
enum: SLICED.B1MUX 1
enum: SLICEA.MODE LOGIC
enum: SLICEA.CCU2.INJECT1_0 _NONE_
enum: SLICEA.MODE LOGIC
enum: SLICEA.CCU2.INJECT1_1 _NONE_
enum: SLICEB.MODE LOGIC
enum: SLICEB.CCU2.INJECT1_0 _NONE_
enum: SLICEB.A0MUX 1
enum: SLICEB.D0MUX 1
enum: SLICEB.GSR DISABLED
enum: SLICEB.REG0.SD 1
enum: SLICEB.REG0.REGSET RESET
enum: SLICEB.REG0.LSRMODE LSR
enum: SLICEB.CEMUX 1
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEB.MODE LOGIC
enum: SLICEB.CCU2.INJECT1_1 _NONE_
enum: SLICEB.A1MUX 1
enum: SLICEC.MODE LOGIC
enum: SLICEC.CCU2.INJECT1_0 _NONE_
enum: SLICEC.D0MUX 1
enum: SLICED.MODE LOGIC
enum: SLICED.CCU2.INJECT1_0 _NONE_
enum: SLICED.A0MUX 1
enum: SLICEC.GSR DISABLED
enum: SLICEC.REG1.SD 0
enum: SLICEC.REG1.REGSET RESET
enum: SLICEC.REG1.LSRMODE LSR
enum: SLICEC.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEC.GSR DISABLED
enum: SLICEC.REG0.SD 0
enum: SLICEC.REG0.REGSET RESET
enum: SLICEC.REG0.LSRMODE LSR
enum: SLICEC.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEA.GSR DISABLED
enum: SLICEA.REG1.SD 0
enum: SLICEA.REG1.REGSET RESET
enum: SLICEA.REG1.LSRMODE LSR
enum: SLICEA.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICED.GSR DISABLED
enum: SLICED.REG1.SD 0
enum: SLICED.REG1.REGSET RESET
enum: SLICED.REG1.LSRMODE LSR
enum: SLICED.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICED.GSR DISABLED
enum: SLICED.REG0.SD 0
enum: SLICED.REG0.REGSET RESET
enum: SLICED.REG0.LSRMODE LSR
enum: SLICED.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
.tile R8C36:PLC2
arc: E1_H02E0001 V06S0003
arc: E1_H02E0101 V02S0101
arc: E1_H02E0401 N1_V01S0000
arc: E1_H02E0601 N1_V02S0601
arc: H00L0000 N1_V02S0201
arc: H00L0100 H02W0301
arc: H00R0000 H02E0401
arc: H00R0100 H02E0501
arc: N1_V02N0401 H01E0001
arc: N1_V02N0601 H01E0001
arc: V00B0100 V02S0101
arc: W1_H02W0001 V06S0003
arc: W1_H02W0101 H01E0101
arc: W1_H02W0401 N1_V01S0000
arc: W1_H02W0601 N1_V01S0000
arc: W1_H02W0701 H01E0101
arc: A5 Q5
arc: C5 E1_H02W0601
arc: CE0 H00R0100
arc: CE2 H00R0000
arc: CE3 H00L0000
arc: CLK0 G_HPBX0000
arc: D0 V02S0001
arc: D5 E1_H01W0100
arc: F0 F0_SLICE
arc: F5 F5_SLICE
arc: H01W0100 Q0
arc: LSR0 V00B0100
arc: LSR1 V00B0100
arc: M5 H00L0100
arc: M7 H02E0201
arc: MUXCLK0 CLK0
arc: MUXCLK2 CLK0
arc: MUXCLK3 CLK0
arc: MUXLSR0 LSR1
arc: MUXLSR2 LSR1
arc: MUXLSR3 LSR0
arc: W1_H02W0501 F5
arc: W3_H06W0203 Q7
word: SLICEA.K0.INIT 0000000011111111
word: SLICEC.K1.INIT 0101111110100000
enum: SLICEA.MODE LOGIC
enum: SLICEA.CCU2.INJECT1_0 _NONE_
enum: SLICEA.A0MUX 1
enum: SLICEA.B0MUX 1
enum: SLICEA.C0MUX 1
enum: SLICEA.GSR DISABLED
enum: SLICEA.REG0.SD 1
enum: SLICEA.REG0.REGSET RESET
enum: SLICEA.REG0.LSRMODE LSR
enum: SLICEA.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEC.GSR DISABLED
enum: SLICEC.REG1.SD 0
enum: SLICEC.REG1.REGSET RESET
enum: SLICEC.REG1.LSRMODE LSR
enum: SLICEC.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICED.GSR DISABLED
enum: SLICED.REG1.SD 0
enum: SLICED.REG1.REGSET RESET
enum: SLICED.REG1.LSRMODE LSR
enum: SLICED.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEC.MODE LOGIC
enum: SLICEC.CCU2.INJECT1_1 _NONE_
enum: SLICEC.B1MUX 1
.tile R8C37:PLC2
arc: E1_H02E0101 V02S0101
arc: E1_H02E0601 V06S0303
arc: E1_H02E0701 E1_H01W0100
arc: H00L0000 W1_H02E0001
arc: H00R0000 W1_H02E0601
arc: H00R0100 N1_V02S0701
arc: N1_V02N0101 H02E0101
arc: N1_V02N0301 E1_H01W0100
arc: S1_V02S0201 N1_V01S0000
arc: V00B0000 V02S0201
arc: V00B0100 V02S0101
arc: W1_H02W0001 N1_V01S0000
arc: W1_H02W0201 N1_V01S0000
arc: W1_H02W0301 E1_H02W0201
arc: W1_H02W0401 V06S0203
arc: W1_H02W0501 V06S0303
arc: A0 V02S0701
arc: A1 V02S0501
arc: A3 V01N0101
arc: A7 H02W0501
arc: B0 V02N0301
arc: B1 V02N0101
arc: B3 N1_V02S0301
arc: C0 H02E0401
arc: C1 H02E0401
arc: C3 N1_V01S0100
arc: C7 H02E0601
arc: CE0 H00L0000
arc: CE2 N1_V02S0601
arc: CE3 H00R0000
arc: CLK0 G_HPBX0000
arc: D0 H02E0001
arc: D1 H02E0001
arc: D7 H00L0100
arc: E1_H01E0101 F7
arc: E1_H02E0401 Q6
arc: F0 F5A_SLICE
arc: F3 F3_SLICE
arc: F7 F7_SLICE
arc: H00L0100 Q1
arc: H01W0100 Q4
arc: LSR1 V00B0100
arc: M0 V00T0100
arc: M1 H00R0100
arc: M4 V00T0000
arc: M6 V00B0000
arc: MUXCLK0 CLK0
arc: MUXCLK2 CLK0
arc: MUXCLK3 CLK0
arc: MUXLSR0 LSR1
arc: MUXLSR2 LSR1
arc: MUXLSR3 LSR1
arc: V00T0000 F0
arc: V00T0100 F3
word: SLICEB.K1.INIT 1110001011100010
word: SLICEA.K0.INIT 1010000011000000
word: SLICEA.K1.INIT 1010111111001111
word: SLICED.K1.INIT 1111101001010000
enum: SLICED.GSR DISABLED
enum: SLICED.REG0.SD 0
enum: SLICED.REG0.REGSET RESET
enum: SLICED.REG0.LSRMODE LSR
enum: SLICED.CEMUX CE
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEA.GSR DISABLED
enum: SLICEA.REG1.SD 0
enum: SLICEA.REG1.REGSET RESET
enum: SLICEA.REG1.LSRMODE LSR
enum: SLICEA.CEMUX CE
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEB.MODE LOGIC
enum: SLICEB.CCU2.INJECT1_1 _NONE_
enum: SLICEB.D1MUX 1
enum: SLICEA.MODE LOGIC
enum: SLICEA.CCU2.INJECT1_0 _NONE_
enum: SLICEA.MODE LOGIC
enum: SLICEA.CCU2.INJECT1_1 _NONE_
enum: SLICEC.GSR DISABLED
enum: SLICEC.REG0.SD 0
enum: SLICEC.REG0.REGSET RESET
enum: SLICEC.REG0.LSRMODE LSR
enum: SLICEC.CEMUX CE
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICED.MODE LOGIC
enum: SLICED.CCU2.INJECT1_1 _NONE_
enum: SLICED.B1MUX 1
.tile R8C38:PLC2
arc: H00L0000 N1_V02S0201
arc: H00L0100 N1_V02S0301
arc: H00R0100 H02E0701
arc: H01W0100 W3_H06E0303
arc: N1_V02N0601 H02E0601
arc: V00T0100 H02E0101
arc: W1_H02W0501 W3_H06E0303
arc: W1_H02W0601 W3_H06E0303
arc: A0 F5
arc: A2 V02N0501
arc: A3 V02N0701
arc: A4 N1_V02S0101
arc: B0 V02N0301
arc: B2 V02S0301
arc: B3 V02S0301
arc: B4 N1_V01S0000
arc: B5 V00B0100
arc: C0 N1_V01N0001
arc: C2 N1_V01S0100
arc: C3 N1_V01S0100
arc: C5 H02E0401
arc: CE3 H00L0000
arc: CLK0 G_HPBX0000
arc: D0 H01E0101
arc: D2 W1_H02E0001
arc: D3 W1_H02E0001
arc: D4 H02W0001
arc: D5 H00R0100
arc: F0 F0_SLICE
arc: F2 F5B_SLICE
arc: F4 F4_SLICE
arc: F5 F5_SLICE
arc: LSR1 V00T0100
arc: M2 V00B0000
arc: M6 V00T0000
arc: M7 H00L0100
arc: MUXCLK0 CLK0
arc: MUXCLK3 CLK0
arc: MUXLSR0 LSR1
arc: MUXLSR3 LSR1
arc: N1_V01N0001 Q6
arc: V00B0000 F4
arc: V00B0100 Q7
arc: V00T0000 F2
arc: V01S0100 Q0
word: SLICEC.K1.INIT 0011110011001100
word: SLICEA.K0.INIT 0110100110010110
word: SLICEC.K0.INIT 1110111001000100
word: SLICEB.K0.INIT 1000100011000000
word: SLICEB.K1.INIT 1011101111110011
enum: SLICED.GSR DISABLED
enum: SLICED.REG1.SD 0
enum: SLICED.REG1.REGSET RESET
enum: SLICED.REG1.LSRMODE LSR
enum: SLICED.CEMUX CE
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEC.MODE LOGIC
enum: SLICEC.CCU2.INJECT1_1 _NONE_
enum: SLICEC.A1MUX 1
enum: SLICEA.MODE LOGIC
enum: SLICEA.CCU2.INJECT1_0 _NONE_
enum: SLICEC.MODE LOGIC
enum: SLICEC.CCU2.INJECT1_0 _NONE_
enum: SLICEC.C0MUX 1
enum: SLICEB.MODE LOGIC
enum: SLICEB.CCU2.INJECT1_0 _NONE_
enum: SLICEB.MODE LOGIC
enum: SLICEB.CCU2.INJECT1_1 _NONE_
enum: SLICED.GSR DISABLED
enum: SLICED.REG0.SD 0
enum: SLICED.REG0.REGSET RESET
enum: SLICED.REG0.LSRMODE LSR
enum: SLICED.CEMUX CE
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEA.GSR DISABLED
enum: SLICEA.REG0.SD 1
enum: SLICEA.REG0.REGSET RESET
enum: SLICEA.REG0.LSRMODE LSR
enum: SLICEA.CEMUX 1
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
.tile R8C39:PLC2
arc: E1_H02E0101 V02S0101
arc: E1_H02E0401 W1_H02E0101
arc: H00L0100 H02W0101
arc: N1_V02N0101 W1_H02E0101
arc: N1_V02N0201 N3_V06S0103
arc: N1_V02N0501 V01N0101
arc: V00B0100 V02S0101
arc: V00T0000 V02S0401
arc: W1_H02W0001 N1_V02S0001
arc: W1_H02W0201 N3_V06S0103
arc: CLK0 G_HPBX0000
arc: E1_H01E0101 Q2
arc: E1_H02E0501 Q7
arc: H00R0000 Q6
arc: H00R0100 Q5
arc: LSR0 V00B0100
arc: LSR1 V00B0100
arc: M0 V00T0000
arc: M2 V00T0100
arc: M3 H00R0100
arc: M4 E1_H01E0101
arc: M5 H00L0100
arc: M6 N1_V01N0101
arc: M7 H00R0000
arc: MUXCLK0 CLK0
arc: MUXCLK1 CLK0
arc: MUXCLK2 CLK0
arc: MUXCLK3 CLK0
arc: MUXLSR0 LSR1
arc: MUXLSR1 LSR1
arc: MUXLSR2 LSR1
arc: MUXLSR3 LSR0
arc: N1_V01N0101 Q0
arc: N1_V02N0401 Q4
arc: V00T0100 Q3
enum: SLICEC.GSR DISABLED
enum: SLICEC.REG0.SD 0
enum: SLICEC.REG0.REGSET RESET
enum: SLICEC.REG0.LSRMODE LSR
enum: SLICEC.CEMUX 1
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEB.GSR DISABLED
enum: SLICEB.REG0.SD 0
enum: SLICEB.REG0.REGSET RESET
enum: SLICEB.REG0.LSRMODE LSR
enum: SLICEB.CEMUX 1
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEB.GSR DISABLED
enum: SLICEB.REG1.SD 0
enum: SLICEB.REG1.REGSET RESET
enum: SLICEB.REG1.LSRMODE LSR
enum: SLICEB.CEMUX 1
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEC.GSR DISABLED
enum: SLICEC.REG1.SD 0
enum: SLICEC.REG1.REGSET RESET
enum: SLICEC.REG1.LSRMODE LSR
enum: SLICEC.CEMUX 1
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICED.GSR DISABLED
enum: SLICED.REG1.SD 0
enum: SLICED.REG1.REGSET RESET
enum: SLICED.REG1.LSRMODE LSR
enum: SLICED.CEMUX 1
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICED.GSR DISABLED
enum: SLICED.REG0.SD 0
enum: SLICED.REG0.REGSET RESET
enum: SLICED.REG0.LSRMODE LSR
enum: SLICED.CEMUX 1
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEA.GSR DISABLED
enum: SLICEA.REG0.SD 0
enum: SLICEA.REG0.REGSET RESET
enum: SLICEA.REG0.LSRMODE LSR
enum: SLICEA.CEMUX 1
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
.tile R8C3:PLC2
arc: S3_V06S0203 H06W0203
arc: S3_V06S0303 H06W0303
.tile R8C40:PLC2
arc: H00R0100 H02E0501
arc: V00B0000 H02E0401
arc: V00T0100 H02E0101
arc: CLK0 G_HPBX0000
arc: LSR0 V00B0000
arc: LSR1 V00T0100
arc: M1 V01S0100
arc: M5 H00R0100
arc: MUXCLK0 CLK0
arc: MUXCLK2 CLK0
arc: MUXLSR0 LSR1
arc: MUXLSR2 LSR0
arc: V01S0100 Q5
arc: W1_H02W0101 Q1
enum: SLICEA.GSR DISABLED
enum: SLICEA.REG1.SD 0
enum: SLICEA.REG1.REGSET RESET
enum: SLICEA.REG1.LSRMODE LSR
enum: SLICEA.CEMUX 1
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEC.GSR DISABLED
enum: SLICEC.REG1.SD 0
enum: SLICEC.REG1.REGSET RESET
enum: SLICEC.REG1.LSRMODE LSR
enum: SLICEC.CEMUX 1
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
.tile R8C6:PLC2
arc: W3_H06W0203 E3_H06W0103
arc: W3_H06W0303 E3_H06W0203
.tile R8C7:PLC2
arc: E3_H06E0003 W3_H06E0303
.tile R9C13:PLC2
arc: W3_H06W0203 E3_H06W0103
.tile R9C19:PLC2
arc: W3_H06W0103 E3_H06W0103
.tile R9C25:PLC2
arc: W3_H06W0103 E3_H06W0003
.tile R9C30:PLC2
arc: B0 N1_V02S0301
arc: C0 V02N0401
arc: CLK0 G_HPBX0000
arc: D0 E1_H02W0201
arc: E3_H06E0003 Q0
arc: F0 F0_SLICE
arc: MUXCLK0 CLK0
arc: N3_V06N0003 Q0
word: SLICEA.K0.INIT 1111001111000000
enum: SLICEA.MODE LOGIC
enum: SLICEA.CCU2.INJECT1_0 _NONE_
enum: SLICEA.A0MUX 1
enum: SLICEA.GSR DISABLED
enum: SLICEA.REG0.SD 1
enum: SLICEA.REG0.REGSET RESET
enum: SLICEA.REG0.LSRMODE LSR
enum: SLICEA.CEMUX 1
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
.tile R9C31:PLC2
arc: E1_H02E0401 V06S0203
arc: V00T0000 H02W0001
arc: A0 V02S0701
arc: B0 E1_H02W0101
arc: C0 N1_V02S0401
arc: CLK0 G_HPBX0000
arc: D0 Q0
arc: F0 F0_SLICE
arc: LSR1 V00T0000
arc: MUXCLK0 CLK0
arc: MUXLSR0 LSR1
arc: W3_H06W0003 Q0
word: SLICEA.K0.INIT 0110100110010110
enum: SLICEA.MODE LOGIC
enum: SLICEA.CCU2.INJECT1_0 _NONE_
enum: SLICEA.GSR DISABLED
enum: SLICEA.REG0.SD 1
enum: SLICEA.REG0.REGSET RESET
enum: SLICEA.REG0.LSRMODE LSR
enum: SLICEA.CEMUX 1
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
.tile R9C32:PLC2
arc: E1_H02E0001 N1_V02S0001
arc: N1_V02N0301 N1_V01S0100
arc: V00B0000 V02S0001
arc: W1_H02W0001 N1_V02S0001
arc: W1_H02W0201 E1_H01W0000
arc: C6 H02E0401
arc: CLK0 G_HPBX0000
arc: D6 V02S0601
arc: E1_H01E0101 F6
arc: F6 F6_SLICE
arc: LSR1 H02W0501
arc: M0 V00B0000
arc: MUXCLK0 CLK0
arc: MUXLSR0 LSR1
arc: N1_V01N0001 Q0
word: SLICED.K0.INIT 1111111100001111
enum: SLICED.MODE LOGIC
enum: SLICED.CCU2.INJECT1_0 _NONE_
enum: SLICED.A0MUX 1
enum: SLICED.B0MUX 1
enum: SLICEA.GSR DISABLED
enum: SLICEA.REG0.SD 0
enum: SLICEA.REG0.REGSET RESET
enum: SLICEA.REG0.LSRMODE LSR
enum: SLICEA.CEMUX 1
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
.tile R9C33:PLC2
arc: E1_H01E0001 E3_H06W0003
arc: H00R0000 V02S0401
arc: H00R0100 V02S0701
arc: V00B0000 V02S0001
arc: W1_H02W0101 N1_V01S0100
arc: W1_H02W0501 H01E0101
arc: A0 E1_H01E0001
arc: C0 H00R0100
arc: CE2 V02N0601
arc: CE3 V02N0601
arc: CLK0 G_HPBX0000
arc: D0 H02E0001
arc: E3_H06E0003 Q0
arc: F0 F0_SLICE
arc: H01W0000 Q0
arc: M4 V00B0000
arc: M7 H00R0000
arc: MUXCLK0 CLK0
arc: MUXCLK2 CLK0
arc: MUXCLK3 CLK0
arc: N1_V01N0101 Q4
arc: N1_V02N0201 Q0
arc: V01S0000 Q7
word: SLICEA.K0.INIT 1111000010101010
enum: SLICEA.MODE LOGIC
enum: SLICEA.CCU2.INJECT1_0 _NONE_
enum: SLICEA.B0MUX 1
enum: SLICEA.GSR DISABLED
enum: SLICEA.REG0.SD 1
enum: SLICEA.REG0.REGSET RESET
enum: SLICEA.REG0.LSRMODE LSR
enum: SLICEA.CEMUX 1
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICED.GSR DISABLED
enum: SLICED.REG1.SD 0
enum: SLICED.REG1.REGSET RESET
enum: SLICED.REG1.LSRMODE LSR
enum: SLICED.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEC.GSR DISABLED
enum: SLICEC.REG0.SD 0
enum: SLICEC.REG0.REGSET RESET
enum: SLICEC.REG0.LSRMODE LSR
enum: SLICEC.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
.tile R9C34:PLC2
arc: E1_H02E0101 N1_V02S0101
arc: N1_V02N0201 H01E0001
arc: N3_V06N0003 E1_H01W0000
.tile R9C35:PLC2
arc: N1_V02N0001 H02W0001
arc: B0 H02E0101
arc: C0 V02N0601
arc: CE3 S1_V02N0601
arc: CLK0 G_HPBX0000
arc: D0 V02S0001
arc: E3_H06E0003 Q0
arc: F0 F0_SLICE
arc: H01W0000 Q0
arc: M7 E1_H02W0201
arc: MUXCLK0 CLK0
arc: MUXCLK3 CLK0
arc: N1_V01N0001 Q7
arc: N1_V02N0201 Q0
arc: N3_V06N0003 Q0
word: SLICEA.K0.INIT 1111001111000000
enum: SLICEA.MODE LOGIC
enum: SLICEA.CCU2.INJECT1_0 _NONE_
enum: SLICEA.A0MUX 1
enum: SLICEA.GSR DISABLED
enum: SLICEA.REG0.SD 1
enum: SLICEA.REG0.REGSET RESET
enum: SLICEA.REG0.LSRMODE LSR
enum: SLICEA.CEMUX 1
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICED.GSR DISABLED
enum: SLICED.REG1.SD 0
enum: SLICED.REG1.REGSET RESET
enum: SLICED.REG1.LSRMODE LSR
enum: SLICED.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
.tile R9C36:PLC2
arc: N1_V02N0001 H02W0001
arc: N1_V02N0101 N3_V06S0103
arc: N1_V02N0301 H06E0003
arc: N3_V06N0003 W3_H06E0003
arc: W1_H02W0001 W3_H06E0003
.tile R9C37:PLC2
arc: H00L0100 N1_V02S0301
arc: H00R0100 S1_V02N0701
arc: N1_V02N0501 S1_V02N0401
arc: W1_H02W0001 N3_V06S0003
arc: W1_H02W0201 V02S0201
arc: CE1 H00R0100
arc: CLK0 G_HPBX0000
arc: M3 H00L0100
arc: MUXCLK1 CLK0
arc: N1_V01N0101 Q3
arc: N1_V02N0101 Q3
arc: N1_V02N0301 Q3
enum: SLICEB.GSR DISABLED
enum: SLICEB.REG1.SD 0
enum: SLICEB.REG1.REGSET RESET
enum: SLICEB.REG1.LSRMODE LSR
enum: SLICEB.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
.tile R9C38:PLC2
arc: E3_H06E0303 N1_V01S0100
arc: H00L0000 H02W0001
arc: N1_V02N0301 N1_V01S0100
arc: CE3 S1_V02N0601
arc: CLK0 G_HPBX0000
arc: M7 H00L0000
arc: MUXCLK3 CLK0
arc: N1_V02N0501 Q7
arc: N1_V02N0701 Q7
enum: SLICED.GSR DISABLED
enum: SLICED.REG1.SD 0
enum: SLICED.REG1.REGSET RESET
enum: SLICED.REG1.LSRMODE LSR
enum: SLICED.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
.tile R9C39:PLC2
arc: N1_V02N0301 W3_H06E0003
arc: W1_H02W0001 V06S0003
arc: B0 N1_V02S0101
arc: C0 E1_H02W0601
arc: CLK0 G_HPBX0000
arc: D0 N1_V02S0001
arc: F0 F0_SLICE
arc: MUXCLK0 CLK0
arc: N1_V01N0101 Q0
arc: W3_H06W0003 Q0
word: SLICEA.K0.INIT 1111001111000000
enum: SLICEA.MODE LOGIC
enum: SLICEA.CCU2.INJECT1_0 _NONE_
enum: SLICEA.A0MUX 1
enum: SLICEA.GSR DISABLED
enum: SLICEA.REG0.SD 1
enum: SLICEA.REG0.REGSET RESET
enum: SLICEA.REG0.LSRMODE LSR
enum: SLICEA.CEMUX 1
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
.tile R9C41:PLC2
arc: N3_V06N0003 W3_H06E0003
arc: W1_H02W0601 S1_V02N0601
.tile R9C44:PLC2
arc: E3_H06E0303 W3_H06E0303
.tile R9C50:PLC2
arc: E3_H06E0003 W3_H06E0303
.tile R9C56:PLC2
arc: E3_H06E0003 W3_H06E0003
.tile R9C62:PLC2
arc: E3_H06E0103 W3_H06E0003
.tile R9C68:PLC2
arc: E3_H06E0103 W3_H06E0103
.tile R9C74:PLC2
arc: E3_H06E0103 W3_H06E0103
.tile R9C7:PLC2
arc: W3_H06W0303 E3_H06W0203
.tile R9C80:PLC2
arc: E3_H06E0203 W3_H06E0103
.tile R9C86:PLC2
arc: E3_H06E0303 W3_H06E0203
.tile TAP_R2C31:TAP_DRIVE
arc: R_HPBX0000 G_VPTX0000
.tile TAP_R3C31:TAP_DRIVE
arc: R_HPBX0000 G_VPTX0000
.tile TAP_R4C31:TAP_DRIVE
arc: R_HPBX0000 G_VPTX0000
.tile TAP_R5C31:TAP_DRIVE
arc: R_HPBX0000 G_VPTX0000
.tile TAP_R6C31:TAP_DRIVE
arc: R_HPBX0000 G_VPTX0000
.tile TAP_R7C31:TAP_DRIVE
arc: R_HPBX0000 G_VPTX0000
.tile TAP_R8C31:TAP_DRIVE
arc: L_HPBX0000 G_VPTX0000
arc: R_HPBX0000 G_VPTX0000
.tile TAP_R9C31:TAP_DRIVE
arc: L_HPBX0000 G_VPTX0000
arc: R_HPBX0000 G_VPTX0000
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