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FPGA-Neural/hardware/v2/nms/synthesis/act_rep_n8_t256/nextpnr.log
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micheleandClaude Sonnet 5 8e014d8d49 V2.0.0 hardware freeze - single SDRAM 
FASE #1 hardware freeze for FPGA-Neural V2, N4/P8, single external
SDRAM (Alliance Memory AS4C4M16SA-6TIN) serving weights, activations,
and results through one physical sdram_controller.v instance. Removes
the PSRAM dependency (hardware/v1/rtl/psram_controller.v +
memory_interface.v) from the V2 physical path entirely -- V1 itself
remains fully unmodified, the golden reference.

New RTL: sdram_unified_backend.v (2-way W/AR arbitration over one
SDRAM controller, real per-byte DQM write masking added to
sdram_controller.v for correct single-byte result writes with no
read-modify-write), nms_neural_multiprocessor_sdram_unified.v (the
frozen top-level). Two real bugs found and fixed via full-system
testing before being accepted (ERR-0023): a deadlock and an off-by-one
data-shift bug in the new arbitration logic.

Real results: N=4 and N=2 D-Stress bit-exact (256/256 neurons), 40
real AUTO REFRESH events interleaved with zero corruption, real
Yosys+nextpnr-ecp5 synthesis/P&R for LFE5U-45F-8CABGA381 (149/245
TRELLIS_IO, a real 45-pin reduction from the prior dual-memory
design). Timing is MARGINAL (1/8 P&R seeds >=80MHz), reported honestly
rather than masked by the best seed.

Real, sourced ball-level pinout for the SDRAM bus + clk/rst (39/149
signals, P&R-verified) using the official Lattice ECP5U-45 pinout CSV
found on disk during this step's own pre-commit review -- corrects an
earlier draft that wrongly assumed no real pinout data was available.

Chip readiness: NO. Real, disclosed blockers remain (no physical host
interface exists yet -- the RTL's own reg_* ports are a 110-pin raw
test-harness bus; clock source/PLL decision; power/configuration
component selection) -- see hardware/v2/docs/{HARDWARE_FREEZE,
CHIP_READINESS,OPEN_ITEMS}.md for the complete, itemized status.

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
2026-09-06 13:39:55 +02:00

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Info: Logic utilisation before packing:
Info: Total LUT4s: 135/43848 0%
Info: logic LUTs: 135/43848 0%
Info: carry LUTs: 0/43848 0%
Info: RAM LUTs: 0/ 5481 0%
Info: RAMW LUTs: 0/10962 0%
Info: Total DFFs: 136/43848 0%
Info: Packing IOs..
Info: Packing constants..
Info: Packing carries...
Info: Packing LUTs...
Info: Packing LUT5-7s...
Info: Packing FFs...
Info: 12 FFs paired with LUTs.
Info: Generating derived timing constraints...
Info: Promoting globals...
Info: promoting clock net clk$TRELLIS_IO_IN to global network
Info: Checksum: 0x3465a66a
Info: Device utilisation:
Info: TRELLIS_IO: 18/ 245 7%
Info: DCCA: 1/ 56 1%
Info: DP16KD: 8/ 108 7%
Info: MULT18X18D: 0/ 72 0%
Info: ALU54B: 0/ 36 0%
Info: EHXPLLL: 0/ 4 0%
Info: EXTREFB: 0/ 2 0%
Info: DCUA: 0/ 2 0%
Info: PCSCLKDIV: 0/ 2 0%
Info: IOLOGIC: 0/ 160 0%
Info: SIOLOGIC: 0/ 85 0%
Info: GSR: 0/ 1 0%
Info: JTAGG: 0/ 1 0%
Info: OSCG: 0/ 1 0%
Info: SEDGA: 0/ 1 0%
Info: DTR: 0/ 1 0%
Info: USRMCLK: 0/ 1 0%
Info: CLKDIVF: 0/ 4 0%
Info: ECLKSYNCB: 0/ 10 0%
Info: DLLDELD: 0/ 8 0%
Info: DDRDLL: 0/ 4 0%
Info: DQSBUFM: 0/ 10 0%
Info: TRELLIS_ECLKBUF: 0/ 8 0%
Info: ECLKBRIDGECS: 0/ 2 0%
Info: DCSC: 0/ 2 0%
Info: TRELLIS_FF: 136/ 43848 0%
Info: TRELLIS_COMB: 137/ 43848 0%
Info: TRELLIS_RAMW: 0/ 5481 0%
Info: Placed 0 cells based on constraints.
Info: Creating initial analytic placement for 234 cells, random placement wirelen = 20216.
Info: at initial placer iter 0, wirelen = 1287
Info: at initial placer iter 1, wirelen = 1268
Info: at initial placer iter 2, wirelen = 1125
Info: at initial placer iter 3, wirelen = 1242
Info: Running main analytical placer, max placement attempts per cell = 11250.
Info: at iteration #1, type ALL: wirelen solved = 1102, spread = 5281, legal = 5096; time = 0.01s
Info: at iteration #2, type ALL: wirelen solved = 1089, spread = 4459, legal = 4472; time = 0.00s
Info: at iteration #3, type ALL: wirelen solved = 1165, spread = 4233, legal = 4268; time = 0.00s
Info: at iteration #4, type ALL: wirelen solved = 1160, spread = 4531, legal = 4593; time = 0.00s
Info: at iteration #5, type ALL: wirelen solved = 1190, spread = 4586, legal = 4614; time = 0.00s
Info: at iteration #6, type ALL: wirelen solved = 1216, spread = 4637, legal = 4688; time = 0.00s
Info: at iteration #7, type ALL: wirelen solved = 1273, spread = 4686, legal = 4720; time = 0.00s
Info: at iteration #8, type ALL: wirelen solved = 1297, spread = 4821, legal = 4849; time = 0.00s
Info: HeAP Placer Time: 0.05s
Info: of which solving equations: 0.03s
Info: of which spreading cells: 0.01s
Info: of which strict legalisation: 0.00s
Info: Running simulated annealing placer for refinement.
Info: at iteration #1: temp = 0.000000, timing cost = 75, wirelen = 4268
Info: at iteration #5: temp = 0.000000, timing cost = 60, wirelen = 3430
Info: at iteration #10: temp = 0.000000, timing cost = 71, wirelen = 3374
Info: at iteration #11: temp = 0.000000, timing cost = 71, wirelen = 3365
Info: SA placement time 0.03s
Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 119.60 MHz (PASS at 80.00 MHz)
Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 5.57 ns
Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 5.97 ns
Info: Slack histogram:
Info: legend: * represents 2 endpoint(s)
Info: + represents [1,2) endpoint(s)
Info: [ 4139, 4519) |*+
Info: [ 4519, 4899) |+
Info: [ 4899, 5279) |+
Info: [ 5279, 5659) |
Info: [ 5659, 6039) |
Info: [ 6039, 6419) |
Info: [ 6419, 6799) |
Info: [ 6799, 7179) |
Info: [ 7179, 7559) |
Info: [ 7559, 7939) |
Info: [ 7939, 8319) |
Info: [ 8319, 8699) |*+
Info: [ 8699, 9079) |*+
Info: [ 9079, 9459) |****+
Info: [ 9459, 9839) |*********************+
Info: [ 9839, 10219) |************************************************************
Info: [ 10219, 10599) |**********************************************************+
Info: [ 10599, 10979) |**********************************+
Info: [ 10979, 11359) |**********************+
Info: [ 11359, 11739) |************+
Info: Checksum: 0x53011214
Info: Routing globals...
Info: routing clock net $glbnet$clk$TRELLIS_IO_IN using global 0
Info: Routing..
Info: Setting up routing queue.
Info: Routing 1160 arcs.
Info: | (re-)routed arcs | delta | remaining| time spent |
Info: IterCnt | w/ripup wo/ripup | w/r wo/r | arcs| batch(sec) total(sec)|
Info: 1000 | 251 733 | 251 733 | 452| 0.14 0.14|
Info: 1521 | 317 1176 | 66 443 | 0| 0.08 0.22|
Info: Routing complete.
Info: Router1 time 0.22s
Info: Checksum: 0x10253a26
Info: Critical path report for clock '$glbnet$clk$TRELLIS_IO_IN' (posedge -> posedge):
Info: type curr total name
Info: clk-to-q 4.10 4.10 Source dut.GEN_COPY[2].mem.0.0.DOA7
Info: routing 1.55 5.65 Net dut.GEN_COPY[2].mem.0.0_DOA7[1] (15,34) -> (8,23)
Info: Sink dut.GEN_COPY[1].mem.0.0_DOA7_LUT4_Z.C
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 5.83 Source dut.GEN_COPY[1].mem.0.0_DOA7_LUT4_Z.F
Info: routing 0.46 6.29 Net dut.GEN_COPY[1].mem.0.0_DOA7[3] (8,23) -> (8,23)
Info: Sink dut.GEN_COPY[0].mem.0.0_DOA7_LUT4_C_Z_LUT4_Z_2.D
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 6.47 Source dut.GEN_COPY[0].mem.0.0_DOA7_LUT4_C_Z_LUT4_Z_2.F
Info: routing 0.60 7.07 Net dut.GEN_COPY[0].mem.0.0_DOA7_LUT4_C_Z[3] (8,23) -> (8,20)
Info: Sink dut.GEN_COPY[4].mem.0.0_DOA1_LUT4_C_Z_LUT4_D_Z_PFUMX_Z_4_ALUT_LUT4_Z.D
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 7.25 Source dut.GEN_COPY[4].mem.0.0_DOA1_LUT4_C_Z_LUT4_D_Z_PFUMX_Z_4_ALUT_LUT4_Z.F
Info: routing 0.00 7.25 Net dut.GEN_COPY[4].mem.0.0_DOA1_LUT4_C_Z_LUT4_D_Z_PFUMX_Z_4_ALUT (8,20) -> (8,20)
Info: Sink dut.GEN_COPY[4].mem.0.0_DOA1_LUT4_C_Z_LUT4_D_Z_PFUMX_Z_4_BLUT_LUT4_Z.F1
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:133.22-133.24
Info: logic 0.13 7.38 Source dut.GEN_COPY[4].mem.0.0_DOA1_LUT4_C_Z_LUT4_D_Z_PFUMX_Z_4_BLUT_LUT4_Z.OFX
Info: routing 0.27 7.65 Net dut.GEN_COPY[4].mem.0.0_DOA1_LUT4_C_Z_LUT4_D_Z[7] (8,20) -> (8,20)
Info: Sink chk_TRELLIS_FF_Q_7.M
Info: setup 0.00 7.65 Source chk_TRELLIS_FF_Q_7.M
Info: 4.76 ns logic, 2.89 ns routing
Info: Critical path report for cross-domain path '<async>' -> 'posedge $glbnet$clk$TRELLIS_IO_IN':
Info: type curr total name
Info: source 0.00 0.00 Source seed[4]$tr_io.O
Info: routing 3.47 3.47 Net seed[4]$TRELLIS_IO_IN (90,23) -> (14,23)
Info: Sink seed_LUT4_B_Z_LUT4_Z_4.B
Info: Defined in:
Info: hardware/v2/nms/synthesis/harness_nms_activation_replicated.v:23.23-23.27
Info: logic 0.18 3.65 Source seed_LUT4_B_Z_LUT4_Z_4.F
Info: routing 0.12 3.77 Net seed_LUT4_B_Z[4] (14,23) -> (14,23)
Info: Sink lfsr_TRELLIS_FF_Q_28.DI
Info: setup 0.00 3.77 Source lfsr_TRELLIS_FF_Q_28.DI
Info: 0.18 ns logic, 3.59 ns routing
Info: Critical path report for cross-domain path 'posedge $glbnet$clk$TRELLIS_IO_IN' -> '<async>':
Info: type curr total name
Info: clk-to-q 0.40 0.40 Source chk_TRELLIS_FF_Q_5.Q
Info: routing 3.56 3.95 Net checksum[5]$TRELLIS_IO_OUT (11,20) -> (90,20)
Info: Sink checksum[5]$tr_io.I
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: 0.40 ns logic, 3.56 ns routing
Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 130.70 MHz (PASS at 80.00 MHz)
Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 3.77 ns
Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 3.95 ns
Info: Slack histogram:
Info: legend: * represents 4 endpoint(s)
Info: + represents [1,4) endpoint(s)
Info: [ 4849, 5197) |+
Info: [ 5197, 5545) |+
Info: [ 5545, 5893) |+
Info: [ 5893, 6241) |
Info: [ 6241, 6589) |
Info: [ 6589, 6937) |
Info: [ 6937, 7285) |
Info: [ 7285, 7633) |
Info: [ 7633, 7981) |
Info: [ 7981, 8329) |
Info: [ 8329, 8677) |
Info: [ 8677, 9025) |+
Info: [ 9025, 9373) |*+
Info: [ 9373, 9721) |+
Info: [ 9721, 10069) |**+
Info: [ 10069, 10417) |*************************+
Info: [ 10417, 10765) |************************************************************
Info: [ 10765, 11113) |****************************+
Info: [ 11113, 11461) |******************+
Info: [ 11461, 11809) |*****+
Info: Program finished normally.
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