\chapter{Overview}

FPGA-Neural V2 succeeds V1 with three architectural changes, all
frozen and verified in this revision:

\begin{enumerate}
\item \textbf{Neural multiprocessor}: N\_PROCESSORS (4, frozen
  reference) independent Neural Processors instead of V1's single
  engine, scheduled by a real dependency-graph Dependency Manager and
  Neural Director.
\item \textbf{Unified single-SDRAM memory}: one physical Alliance
  Memory \code{AS4C4M16SA-6TIN} SDRAM serves weights, activations,
  \emph{and} results. V1's PSRAM (\code{IS66WVE4M16EBLL-70BLI}) and
  its controller are not part of V2's physical path at all.
\item \textbf{Real physical host interface}: a from-scratch SPI
  protocol engine (\code{spi\_host\_bridge.v}) replaces the internal
  110-pin \code{reg\_*} testbench bus as the board-level top's own
  physical interface.
\end{enumerate}

V1 itself (\code{hardware/v1/**}) is untouched and remains the golden,
independently certified reference design; V2 shares no RTL file with
it.

\section{Document scope and status labels}
\label{sec:status-labels}
This datasheet distinguishes explicitly between:
\begin{itemize}
\item \textbf{RTL verified} -- verified through RTL simulation only.
\item \textbf{Simulation verified} -- verified in simulation for the
  specific configuration named.
\item \textbf{Synthesis verified} -- synthesizes cleanly for the
  target FPGA (Yosys, real run, zero unintended latches or
  multi-driver issues beyond a small, previously-reviewed benign set).
\item \textbf{P\&R verified} -- successfully placed, routed, and
  timing-analyzed by nextpnr-ecp5 for a real, ball-assigned LPF.
\item \textbf{Hardware designed} -- schematic/PCB electrically
  designed but not fabricated.
\item \textbf{Hardware validated} -- physically tested on fabricated
  hardware.
\item \textbf{Silicon validated} -- the actual physical FPGA has been
  programmed and tested.
\end{itemize}
As of \datasheetdate, V2 is \textbf{RTL verified}, \textbf{simulation
verified} (bit-exact), \textbf{synthesis verified}, and \textbf{P\&R
verified}. No item in this datasheet is presented as hardware- or
silicon-validated -- no fabricated V2 board exists. See
Chapter~\ref{ch:status} for the complete, itemized status.

\section{Frozen reference configuration}
\begin{tabularx}{\textwidth}{L{4cm}Y}
\toprule
\rowh \thd{Parameter} & \thd{Value} \\
\midrule
FPGA & Lattice \code{LFE5U-45F-8BG381}, speed grade $-8$, CABGA381 \\
\rowa N\_PROCESSORS & 4 (frozen reference; N=2 also fully validated) \\
P\_IN & 8 (MAC width per processor) \\
\rowa ACC\_WIDTH & 32 \\
External memory & 1 $\times$ SDRAM, Alliance Memory \code{AS4C4M16SA-6TIN}, 8\,MB \\
\rowa Oscillator & 16\,MHz (board-level, external) \\
System clock & 64\,MHz, generated by a real ECP5 \code{EHXPLLL} \\
\rowa Host interface & real SPI (4 pins), \code{spi\_host\_bridge.v} \\
\bottomrule
\end{tabularx}