% ======================================================================
%  FPGA-Neural V2 -- INT8 Neural Network Engine, single-SDRAM architecture
%  Datasheet / Technical reference manual
%  Repository: github.com/manvalan/FPGA-Neural
%  Ported from the V1 LaTeX datasheet (hardware/v1/docs/DatasheetLatex/):
%  same preamble, macros, typography, and title-page/features-page
%  structure -- content rewritten for the V2 architecture throughout.
% ======================================================================
\documentclass[11pt,a4paper,openany]{report}

\newcommand{\datasheetrev}{B0}
\newcommand{\datasheetdate}{September 2026}

\input{preamble}

\begin{document}
\sloppy

% ======================================================================
%  TITLE PAGE
% ======================================================================
\begin{titlepage}
\thispagestyle{empty}
\begin{tikzpicture}[remember picture,overlay]
  \fill[fnDark] (current page.north west) rectangle
       ([yshift=-4.3cm]current page.north east);
  \fill[fnTeal] ([yshift=-4.3cm]current page.north west) rectangle
       ([yshift=-4.55cm]current page.north east);
  \node[anchor=north west,text=white,font=\Huge\bfseries]
       at ([xshift=2.2cm,yshift=-1.15cm]current page.north west)
       {FPGA\,--\,Neural V2};
  \node[anchor=north west,text=fnLight,font=\large]
       at ([xshift=2.25cm,yshift=-2.15cm]current page.north west)
       {INT8 Neural Multiprocessor, unified single-SDRAM architecture};
  \node[anchor=north west,text=fnLight2,font=\normalsize]
       at ([xshift=2.25cm,yshift=-2.85cm]current page.north west)
       {Parametric N-processor hardware accelerator -- Datasheet and reference manual};
  \node[anchor=north east,text=white,font=\ttfamily\small]
       at ([xshift=-2.2cm,yshift=-3.55cm]current page.north east)
       {Rev.~\datasheetrev~~\textbullet~~\datasheetdate};
\end{tikzpicture}

\vspace*{5.0cm}

% --- compact block diagram on the title page ---
\begin{center}
\begin{tikzpicture}[node distance=7mm and 12mm]
  \node[fnblockD,minimum width=30mm] (host) {HOST\\{\scriptsize MCU / PC (SPI master)}};
  \node[fnblockT,right=18mm of host,minimum width=34mm] (fpga)
       {FPGA\\{\scriptsize Neural Multiprocessor, N=4}};
  \node[fnblock,right=18mm of fpga,minimum width=26mm] (ram)
       {SDRAM\\{\scriptsize 8\,MB, unified}};
  \draw[fnbus] (host) -- node[fnlbl,above]{SPI Mode 0} (fpga);
  \draw[fnbus] (fpga) -- node[fnlbl,above]{16-bit, single chip} (ram);
  \node[below=1mm of fpga,font=\scriptsize\itshape,text=fnGrey]
       {weights + activations + results, ONE physical memory};
\end{tikzpicture}
\end{center}

\vfill
\begin{center}
\begin{tikzpicture}
\node[draw=fnRule,rounded corners=3pt,inner sep=10pt,fill=fnLight,text width=15.5cm]{
\footnotesize
\textbf{\color{fnDark}Reference target device:} Lattice ECP5 \code{LFE5U-45F-8BG381}
(speed grade $-8$, CABGA381, 72$\times$MULT18X18D, $\approx$44k LUT).\\[2pt]
\textbf{\color{fnDark}Baseline configuration:} INT8/INT32, \code{N\_PROCESSORS}=4,
\code{P\_IN}=8, single external SDRAM Alliance Memory \code{AS4C4M16SA-6TIN}
(weights + activations + results, unified). No PSRAM anywhere in the V2
physical path.\\[2pt]
\textbf{\color{fnDark}Clock:} 16\,MHz board oscillator $\rightarrow$ real
ECP5 \code{EHXPLLL} $\rightarrow$ 64\,MHz system clock, timing-closed
across 8 real place-and-route seeds (worst 68.51\,MHz, best 74.17\,MHz).\\[2pt]
\textbf{\color{fnDark}Host:} real SPI protocol engine
(\code{spi\_host\_bridge.v}) -- WRITE\_JOB / WRITE\_MEM / READ\_MEM /
STATUS / RESET.\\[2pt]
\textbf{\color{fnDark}Status:} RTL verified in simulation (Verilator,
bit-exact), real synthesis (Yosys) and real place-and-route
(nextpnr-ecp5). No fabricated hardware exists -- see \S\ref{ch:status}
for the precise, itemized readiness state. Document describing the
project as of \datasheetdate.
};
\end{tikzpicture}
\end{center}
\vspace{0.6cm}
{\footnotesize\color{fnGrey}\raggedright
Project author: Michele Bigi \textbullet{} MIKILAB / manvalan.\\
This datasheet documents the RTL code, documentation and benchmarks
present in the repository \texttt{github.com/manvalan/FPGA-Neural},
ported from the V1 datasheet's own LaTeX structure (same preamble and
macros, content rewritten for V2).\par}
\end{titlepage}

% ======================================================================
%  "FEATURES" PAGE (datasheet style)
% ======================================================================
\input{chapters/00-features}

% ======================================================================
%  TABLE OF CONTENTS
% ======================================================================
\newpage
\pagenumbering{roman}
{\color{fnDark}\tableofcontents}
\newpage
\pagenumbering{arabic}

% ======================================================================
%  CHAPTERS
% ======================================================================
\include{chapters/01-overview}
\include{chapters/02-architecture}
\include{chapters/03-clock-reset}
\include{chapters/04-host-interface}
\include{chapters/05-pinout-timing}
\include{chapters/06-power-configuration}
\include{chapters/07-benchmarks}
\include{chapters/08-status-roadmap}

\end{document}