\chapter{Host interface (SPI)}

\code{spi\_host\_bridge.v} is the real, physical host interface for
V2's board-level top (\code{fpga\_neural\_v2\_top.v}). It replaces the
internal 110-pin \code{reg\_*} bus (a simulation/testbench convenience
that must never be represented as a physical board interface) with 4
real pins: \sig{spi\_sclk}, \sig{spi\_mosi}, \sig{spi\_miso},
\sig{spi\_cs\_n}. Mode 0 (CPOL=0/CPHA=0), MSB-first, one opcode per
CS-low period.

\section{Opcodes}
\begin{tabularx}{\textwidth}{L{2cm}L{3.2cm}Y}
\toprule
\rowh \thd{Opcode} & \thd{Name} & \thd{Function} \\
\midrule
\op{0x10} & \op{WRITE\_JOB} & 15-byte payload: node id, required
  dependency count, producer ids, \sig{x\_base}, \sig{w\_base},
  \sig{n\_tiles}, \sig{result\_addr}. Registers one Dependency Manager
  job; \sig{reg\_valid} is held until the same-cycle
  \sig{reg\_valid}\,\&\&\,\sig{reg\_ready} acceptance fires. \\
\rowa \op{0x01} & \op{WRITE\_MEM} & word-addressed raw SDRAM write,
  via a second, arbitrated AR port. \\
\op{0x02} & \op{READ\_MEM} & word-addressed raw SDRAM read. \\
\rowa \op{0x20} & \op{STATUS} & 1-byte status: job-busy, mem-busy,
  sticky last-job-accepted. \\
\op{0x0F} & \op{RESET} & pulses a soft-reset into the compute+memory
  core (not the SPI bridge's own state, avoiding a self-reset hazard). \\
\bottomrule
\end{tabularx}

\section{Verification}
\label{sec:host}
The protocol engine is verified in two independent ways:
\begin{itemize}
\item \textbf{Isolated}: \code{tb\_spi\_host\_bridge.v}, 18/18 PASS --
  every opcode, including a real DQM-style byte-masked
  \op{WRITE\_MEM}.
\item \textbf{End-to-end}: \code{tb\_fpga\_neural\_v2\_top\_smoke.v},
  11/11 PASS -- a single job, two jobs back-to-back, two jobs across a
  realistic $\sim$85\,\textmu s SPI-paced gap, and a parametric sweep
  of inter-job gaps (100\,ns / 5\,000\,ns / 50\,000\,ns), all checked
  bit-exact against a software golden model via a real SDRAM backdoor
  readback.
\end{itemize}
Both regressions pass with \textbf{zero regression} to the existing
N=2/N=4 D-Stress bit-exact baseline (identical cycle counts before and
after every fix applied during this interface's own development).