\thispagestyle{plain}
\noindent
\begin{tikzpicture}
\node[fill=fnDark,text=white,rounded corners=2pt,inner sep=6pt,
      minimum width=\textwidth,anchor=west]
  {\large\bfseries FPGA-Neural V2 --- General description and features};
\end{tikzpicture}

\vspace{6pt}
\noindent
{\small FPGA-Neural V2 is a \textbf{parametric hardware neural
multiprocessor} built around \code{N\_PROCESSORS} independent INT8 MAC
engines dispatched by a real dependency-graph scheduler
(Dependency Manager $\to$ Neural Director $\to$ per-slot Memory
Manager), streaming weight/activation tiles from, and writing results
to, a \textbf{single external SDRAM chip} -- no PSRAM, no second
memory device anywhere in the V2 physical path. Job registration is
via a real SPI host protocol engine; the host never participates in
the compute datapath.}

\vspace{8pt}
\begin{multicols}{2}
{\color{fnDark}\large\bfseries Features}\\[2pt]
{\footnotesize
\begin{itemize}[leftmargin=1.1em]
\item \textbf{INT8 $\times$ INT8 $\to$ INT32} datapath per processor,
      \code{P\_IN}=8-wide parallel MAC, balanced adder tree.
\item \textbf{N\_PROCESSORS} independent Neural Processors (frozen
      reference: N=4; N=2 also fully validated; N=8 is a future
      evolution).
\item \textbf{Unified single-SDRAM memory}: weights, activations, AND
      results all share ONE physical Alliance Memory
      \code{AS4C4M16SA-6TIN} (8\,MB, 16-bit), through one
      \code{sdram\_unified\_backend} arbitrating a read-only,
      cached weight (W) port and a read/write, byte-maskable
      activation+result (AR) port.
\item Real dependency-graph scheduling: the Dependency Manager tracks
      per-node WAITING/READY/DISPATCHED state and producer/consumer
      wake-up; the Neural Director allocates the first free processor
      slot.
\item \textbf{Real SPI host protocol engine}
      (\code{spi\_host\_bridge.v}): \code{WRITE\_JOB} (job
      registration), \code{WRITE\_MEM}/\code{READ\_MEM} (raw SDRAM
      access), \code{STATUS}, \code{RESET}.
\item \textbf{Real ECP5 clock generation}: 16\,MHz oscillator
      $\to$ \code{EHXPLLL} (real Project Trellis \code{ecppll}
      parameters) $\to$ 64\,MHz system clock.
\item Real reset architecture (\code{reset\_sync.v}): asynchronous
      assertion, synchronous deassertion, gated by external POR and
      PLL lock.
\item Verified in \textbf{simulation} (Verilator, bit-exact) and real
      synthesis + place-and-route (Yosys + nextpnr-ecp5).
\end{itemize}}

\columnbreak

{\color{fnDark}\large\bfseries Applications}\\[2pt]
{\footnotesize
\begin{itemize}[leftmargin=1.1em]
\item Deterministic low-latency inference as an SPI peripheral of a
      microcontroller or SoC host.
\item Reusable dependency-graph compute fabric, not a single fixed
      network topology.
\item Edge AI on compact, INT8-quantized dense/DAG-structured
      networks.
\item Off-loading neural workload from a constrained host CPU to
      dedicated hardware with predictable, measured throughput.
\end{itemize}}

\vspace{4pt}
{\color{fnDark}\large\bfseries Target \& toolchain}\\[2pt]
{\footnotesize
\begin{itemize}[leftmargin=1.1em]
\item FPGA: Lattice ECP5 \code{LFE5U-45F-8BG381} ($-8$, CABGA381).
\item Synthesis: Yosys; place\&route: nextpnr-ecp5.
\item Simulation: Verilator (trusted per this project's own DEC-0004
      protocol) and Icarus Verilog (cross-checked).
\item SDRAM: Alliance Memory \code{AS4C4M16SA-6TIN} (4M$\times$16, 8\,MB).
\end{itemize}}
\end{multicols}

\vspace{2pt}
% --- key parameter table ---
\noindent
{\small\color{fnDark}\bfseries Key parameters (frozen V2 reference configuration)}
\vspace{2pt}

\noindent
\begin{tabularx}{\textwidth}{L{3.4cm}L{3.8cm}Y}
\toprule
\rowh \thd{Quantity} & \thd{Value} & \thd{Notes} \\
\midrule
Data precision & INT8 (signed) & \code{DATA\_WIDTH}=8 \\
\rowa Accumulator & INT32 (signed) & \code{ACC\_WIDTH}=32 \\
Processors & 4 (N=2 also validated) & \code{N\_PROCESSORS} \\
\rowa MAC width per processor & 8 & \code{P\_IN}=8 \\
Activation & ReLU + INT8 saturate & fixed, matches golden model \\
\rowa External memory & 1 $\times$ SDRAM, 8\,MB & \code{AS4C4M16SA-6TIN}, unified \\
System clock & 64\,MHz (real P\&R, 8/8 seeds PASS) & 16\,MHz osc.\ $\to$ EHXPLLL \\
\rowa Bit-exact regression & 256/256, N=2 and N=4 & Verilator, D-Stress workload \\
Host interface & real SPI (4 pins) & \code{spi\_host\_bridge.v} \\
\bottomrule
\end{tabularx}

\vspace{8pt}
\noindent
{\small\color{fnDark}\bfseries System block diagram}
\begin{center}
\begin{tikzpicture}[node distance=6mm and 10mm,font=\footnotesize]
  \node[fnblockD,minimum width=26mm,minimum height=13mm] (host){HOST\\{\scriptsize SPI master}};
  \node[fnblockT,right=16mm of host,minimum width=56mm,minimum height=24mm] (eng){};
  \node[anchor=north,font=\footnotesize\bfseries,text=fnDark] at (eng.north){FPGA -- Neural Multiprocessor (N=4)};
  \node[fnreg,fill=white] (spi) at ([yshift=-3mm]eng.center){\code{spi\_host\_bridge} + Dependency Manager};
  \node[fnreg,fill=white,below=2.5mm of spi] (mm){Neural Director $\to$ 4$\times$ Memory Manager $\to$ Neural Processor};
  \node[fnreg,fill=white,above=2.5mm of spi] (be){\code{sdram\_unified\_backend} (W + AR arbitration)};
  \node[fnblock,right=16mm of eng,minimum width=24mm,minimum height=13mm] (ram){SDRAM 8\,MB\\{\scriptsize unified: W+A+R}};
  \draw[fnbus] (host) -- node[fnlbl,above]{SPI} (eng.west|-host);
  \draw[fnbus] (eng.east|-ram) -- node[fnlbl,above]{16-bit} (ram);
\end{tikzpicture}
\end{center}
\begin{center}\footnotesize\itshape\color{fnGrey}
Weights, activations and results all share the single physical SDRAM;
the host only registers jobs and reads back results over SPI.\end{center}