Info: Logic utilisation before packing: Info: Total LUT4s: 281/43848 0% Info: logic LUTs: 77/43848 0% Info: carry LUTs: 204/43848 0% Info: RAM LUTs: 0/ 5481 0% Info: RAMW LUTs: 0/10962 0% Info: Total DFFs: 561/43848 1% Info: Packing IOs.. Info: Packing constants.. Info: Packing carries... Info: Packing LUTs... Info: Packing LUT5-7s... Info: Packing FFs... Info: 212 FFs paired with LUTs. Info: Generating derived timing constraints... Info: Promoting globals... Info: promoting clock net clk$TRELLIS_IO_IN to global network Info: Checksum: 0xe4bf0be0 Info: Device utilisation: Info: TRELLIS_IO: 192/ 245 78% Info: DCCA: 1/ 56 1% Info: DP16KD: 0/ 108 0% Info: MULT18X18D: 8/ 72 11% Info: ALU54B: 0/ 36 0% Info: EHXPLLL: 0/ 4 0% Info: EXTREFB: 0/ 2 0% Info: DCUA: 0/ 2 0% Info: PCSCLKDIV: 0/ 2 0% Info: IOLOGIC: 0/ 160 0% Info: SIOLOGIC: 0/ 85 0% Info: GSR: 0/ 1 0% Info: JTAGG: 0/ 1 0% Info: OSCG: 0/ 1 0% Info: SEDGA: 0/ 1 0% Info: DTR: 0/ 1 0% Info: USRMCLK: 0/ 1 0% Info: CLKDIVF: 0/ 4 0% Info: ECLKSYNCB: 0/ 10 0% Info: DLLDELD: 0/ 8 0% Info: DDRDLL: 0/ 4 0% Info: DQSBUFM: 0/ 10 0% Info: TRELLIS_ECLKBUF: 0/ 8 0% Info: ECLKBRIDGECS: 0/ 2 0% Info: DCSC: 0/ 2 0% Info: TRELLIS_FF: 561/ 43848 1% Info: TRELLIS_COMB: 319/ 43848 0% Info: TRELLIS_RAMW: 0/ 5481 0% Info: Placed 0 cells based on constraints. Info: Creating initial analytic placement for 424 cells, random placement wirelen = 50455. Info: at initial placer iter 0, wirelen = 12005 Info: at initial placer iter 1, wirelen = 11180 Info: at initial placer iter 2, wirelen = 11007 Info: at initial placer iter 3, wirelen = 11030 Info: Running main analytical placer, max placement attempts per cell = 146070. Info: at iteration #1, type ALL: wirelen solved = 11022, spread = 14876, legal = 16032; time = 0.01s Info: at iteration #2, type ALL: wirelen solved = 11185, spread = 13525, legal = 14773; time = 0.01s Info: at iteration #3, type ALL: wirelen solved = 11171, spread = 14157, legal = 15687; time = 0.01s Info: at iteration #4, type ALL: wirelen solved = 11247, spread = 13660, legal = 15080; time = 0.01s Info: at iteration #5, type ALL: wirelen solved = 11256, spread = 14501, legal = 16195; time = 0.01s Info: at iteration #6, type ALL: wirelen solved = 11281, spread = 14413, legal = 15627; time = 0.01s Info: at iteration #7, type ALL: wirelen solved = 11322, spread = 14088, legal = 15088; time = 0.01s Info: HeAP Placer Time: 0.07s Info: of which solving equations: 0.04s Info: of which spreading cells: 0.01s Info: of which strict legalisation: 0.00s Info: Running simulated annealing placer for refinement. Info: at iteration #1: temp = 0.000000, timing cost = 131, wirelen = 14773 Info: at iteration #5: temp = 0.000000, timing cost = 106, wirelen = 11964 Info: at iteration #9: temp = 0.000000, timing cost = 77, wirelen = 12024 Info: SA placement time 0.09s Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 158.73 MHz (PASS at 80.00 MHz) Info: Max delay -> posedge $glbnet$clk$TRELLIS_IO_IN: 7.92 ns Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> : 8.14 ns Info: Slack histogram: Info: legend: * represents 1 endpoint(s) Info: + represents [1,1) endpoint(s) Info: [ 6200, 6477) |*+ Info: [ 6477, 6754) |***+ Info: [ 6754, 7031) |********+ Info: [ 7031, 7308) |*******************************************+ Info: [ 7308, 7585) |******************************************+ Info: [ 7585, 7862) |************************************************************ Info: [ 7862, 8139) |*************************+ Info: [ 8139, 8416) |*******+ Info: [ 8416, 8693) |******+ Info: [ 8693, 8970) |**************+ Info: [ 8970, 9247) |*******************+ Info: [ 9247, 9524) |******************+ Info: [ 9524, 9801) |**********************+ Info: [ 9801, 10078) |**************************************+ Info: [ 10078, 10355) |***************************************************+ Info: [ 10355, 10632) |**********************+ Info: [ 10632, 10909) |********+ Info: [ 10909, 11186) |*****+ Info: [ 11186, 11463) |***+ Info: [ 11463, 11740) |************+ Info: Checksum: 0x34ea3833 Info: Routing globals... Info: routing clock net $glbnet$clk$TRELLIS_IO_IN using global 0 Info: Routing.. Info: Setting up routing queue. Info: Routing 2137 arcs. Info: | (re-)routed arcs | delta | remaining| time spent | Info: IterCnt | w/ripup wo/ripup | w/r wo/r | arcs| batch(sec) total(sec)| Info: 1000 | 108 891 | 108 891 | 1309| 0.20 0.20| Info: 2000 | 230 1654 | 122 763 | 437| 0.15 0.35| Info: 2450 | 244 2069 | 14 415 | 0| 0.12 0.47| Info: Routing complete. Info: Router1 time 0.47s Info: Checksum: 0xf8fda93b Info: Critical path report for clock '$glbnet$clk$TRELLIS_IO_IN' (posedge -> posedge): Info: type curr total name Info: clk-to-q 0.40 0.40 Source GEN_NP[0].u_np.w0[4]_TRELLIS_FF_Q_3.Q Info: routing 1.15 1.55 Net GEN_NP[0].u_np.w0[4][3] (25,20) -> (27,22) Info: Sink GEN_NP[0].u_np.product_comb[4]_MULT18X18D_P9.B3 Info: Defined in: Info: hardware/v2/rtl/neural_processor.v:100.44-100.46 Info: logic 3.07 4.62 Source GEN_NP[0].u_np.product_comb[4]_MULT18X18D_P9.P9 Info: routing 0.97 5.58 Net GEN_NP[0].u_np.product_comb[4][9] (27,22) -> (27,27) Info: Sink GEN_NP[0].u_np.prod1[4]_TRELLIS_FF_Q_9.M Info: Defined in: Info: hardware/v2/rtl/neural_processor.v:135.34-135.46 Info: setup 0.00 5.58 Source GEN_NP[0].u_np.prod1[4]_TRELLIS_FF_Q_9.M Info: 3.46 ns logic, 2.12 ns routing Info: Critical path report for cross-domain path '' -> 'posedge $glbnet$clk$TRELLIS_IO_IN': Info: type curr total name Info: source 0.00 0.00 Source tile_last$tr_io.O Info: routing 4.08 4.08 Net tile_last$TRELLIS_IO_IN (90,50) -> (19,31) Info: Sink job_valid_LUT4_C_Z_LUT4_Z.C Info: Defined in: Info: hardware/v2/rtl/neural_processor_array.v:43.57-43.66 Info: logic 0.18 4.26 Source job_valid_LUT4_C_Z_LUT4_Z.F Info: routing 0.64 4.90 Net job_valid_LUT4_C_Z[2] (19,31) -> (18,31) Info: Sink result_ready_LUT4_A_Z_LUT4_B.C Info: Defined in: Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24 Info: logic 0.18 5.08 Source result_ready_LUT4_A_Z_LUT4_B.F Info: routing 0.49 5.57 Net result_ready_LUT4_A_Z_LUT4_B_Z (18,31) -> (18,32) Info: Sink GEN_NP[0].u_np.np_state_TRELLIS_FF_Q_2.CE Info: setup 0.00 5.57 Source GEN_NP[0].u_np.np_state_TRELLIS_FF_Q_2.CE Info: 0.36 ns logic, 5.21 ns routing Info: Critical path report for cross-domain path 'posedge $glbnet$clk$TRELLIS_IO_IN' -> '': Info: type curr total name Info: clk-to-q 0.40 0.40 Source GEN_NP[0].u_np.np_state_TRELLIS_FF_Q_1.Q Info: routing 0.64 1.03 Net np_state[2]$TRELLIS_IO_OUT (18,32) -> (18,32) Info: Sink operand_ready_LUT4_Z.B Info: Defined in: Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24 Info: logic 0.18 1.21 Source operand_ready_LUT4_Z.F Info: routing 4.40 5.61 Net operand_ready$TRELLIS_IO_OUT (18,32) -> (90,56) Info: Sink operand_ready$tr_io.I Info: Defined in: Info: hardware/v2/rtl/neural_processor_array.v:40.58-40.71 Info: 0.57 ns logic, 5.03 ns routing Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 179.08 MHz (PASS at 80.00 MHz) Info: Max delay -> posedge $glbnet$clk$TRELLIS_IO_IN: 5.57 ns Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> : 5.61 ns Info: Slack histogram: Info: legend: * represents 1 endpoint(s) Info: + represents [1,1) endpoint(s) Info: [ 6916, 7160) |**********************+ Info: [ 7160, 7404) |************************************************************ Info: [ 7404, 7648) |********+ Info: [ 7648, 7892) |********+ Info: [ 7892, 8136) |***+ Info: [ 8136, 8380) |******+ Info: [ 8380, 8624) |*********************+ Info: [ 8624, 8868) |**************************************+ Info: [ 8868, 9112) |***************************************+ Info: [ 9112, 9356) |**********+ Info: [ 9356, 9600) |*****************************************+ Info: [ 9600, 9844) |*************************************+ Info: [ 9844, 10088) |****************************************************+ Info: [ 10088, 10332) |******************************+ Info: [ 10332, 10576) |********+ Info: [ 10576, 10820) |***************+ Info: [ 10820, 11064) |***************+ Info: [ 11064, 11308) |******+ Info: [ 11308, 11552) |*****+ Info: [ 11552, 11796) |**********+ Info: Program finished normally.