Warning: IO 'y_bus[31]' is unconstrained in LPF and will be automatically placed Warning: IO 'y_bus[30]' is unconstrained in LPF and will be automatically placed Warning: IO 'y_bus[29]' is unconstrained in LPF and will be automatically placed Warning: IO 'y_bus[28]' is unconstrained in LPF and will be automatically placed Warning: IO 'y_bus[27]' is unconstrained in LPF and will be automatically placed Warning: IO 'y_bus[26]' is unconstrained in LPF and will be automatically placed Warning: IO 'y_bus[25]' is unconstrained in LPF and will be automatically placed Warning: IO 'y_bus[24]' is unconstrained in LPF and will be automatically placed Warning: IO 'y_bus[23]' is unconstrained in LPF and will be automatically placed Warning: IO 'y_bus[22]' is unconstrained in LPF and will be automatically placed Warning: IO 'y_bus[21]' is unconstrained in LPF and will be automatically placed Warning: IO 'y_bus[20]' is unconstrained in LPF and will be automatically placed Warning: IO 'y_bus[19]' is unconstrained in LPF and will be automatically placed Warning: IO 'y_bus[18]' is unconstrained in LPF and will be automatically placed Warning: IO 'y_bus[17]' is unconstrained in LPF and will be automatically placed Warning: IO 'y_bus[16]' is unconstrained in LPF and will be automatically placed Warning: IO 'y_bus[15]' is unconstrained in LPF and will be automatically placed Warning: IO 'y_bus[14]' is unconstrained in LPF and will be automatically placed Warning: IO 'y_bus[13]' is unconstrained in LPF and will be automatically placed Warning: IO 'y_bus[12]' is unconstrained in LPF and will be automatically placed Warning: IO 'y_bus[11]' is unconstrained in LPF and will be automatically placed Warning: IO 'y_bus[10]' is unconstrained in LPF and will be automatically placed Warning: IO 'y_bus[9]' is unconstrained in LPF and will be automatically placed Warning: IO 'y_bus[8]' is unconstrained in LPF and will be automatically placed Warning: IO 'y_bus[7]' is unconstrained in LPF and will be automatically placed Warning: IO 'y_bus[6]' is unconstrained in LPF and will be automatically placed Warning: IO 'y_bus[5]' is unconstrained in LPF and will be automatically placed Warning: IO 'y_bus[4]' is unconstrained in LPF and will be automatically placed Warning: IO 'y_bus[3]' is unconstrained in LPF and will be automatically placed Warning: IO 'y_bus[2]' is unconstrained in LPF and will be automatically placed Warning: IO 'y_bus[1]' is unconstrained in LPF and will be automatically placed Warning: IO 'y_bus[0]' is unconstrained in LPF and will be automatically placed Warning: IO 'start' is unconstrained in LPF and will be automatically placed Warning: IO 'rst' is unconstrained in LPF and will be automatically placed Warning: IO 'done' is unconstrained in LPF and will be automatically placed Warning: IO 'clk' is unconstrained in LPF and will be automatically placed Warning: IO 'busy' is unconstrained in LPF and will be automatically placed Info: Logic utilisation before packing: Info: Total LUT4s: 804/43848 1% Info: logic LUTs: 356/43848 0% Info: carry LUTs: 448/43848 1% Info: RAM LUTs: 0/ 5481 0% Info: RAMW LUTs: 0/10962 0% Info: Total DFFs: 194/43848 0% Info: Packing IOs.. Info: Packing constants.. Info: Packing carries... Info: Packing LUTs... Info: Packing LUT5-7s... Info: Packing FFs... Info: 191 FFs paired with LUTs. Info: Generating derived timing constraints... Info: Promoting globals... Info: promoting clock net clk$TRELLIS_IO_IN to global network Info: Checksum: 0x93c68254 Info: Device utilisation: Info: TRELLIS_IO: 37/ 245 15% Info: DCCA: 1/ 56 1% Info: DP16KD: 0/ 108 0% Info: MULT18X18D: 16/ 72 22% Info: ALU54B: 0/ 36 0% Info: EHXPLLL: 0/ 4 0% Info: EXTREFB: 0/ 2 0% Info: DCUA: 0/ 2 0% Info: PCSCLKDIV: 0/ 2 0% Info: IOLOGIC: 0/ 160 0% Info: SIOLOGIC: 0/ 85 0% Info: GSR: 0/ 1 0% Info: JTAGG: 0/ 1 0% Info: OSCG: 0/ 1 0% Info: SEDGA: 0/ 1 0% Info: DTR: 0/ 1 0% Info: USRMCLK: 0/ 1 0% Info: CLKDIVF: 0/ 4 0% Info: ECLKSYNCB: 0/ 10 0% Info: DLLDELD: 0/ 8 0% Info: DDRDLL: 0/ 4 0% Info: DQSBUFM: 0/ 10 0% Info: TRELLIS_ECLKBUF: 0/ 8 0% Info: ECLKBRIDGECS: 0/ 2 0% Info: DCSC: 0/ 2 0% Info: TRELLIS_FF: 194/ 43848 0% Info: TRELLIS_COMB: 890/ 43848 2% Info: TRELLIS_RAMW: 0/ 5481 0% Info: Placed 0 cells based on constraints. Info: Creating initial analytic placement for 398 cells, random placement wirelen = 65706. Info: at initial placer iter 0, wirelen = 3255 Info: at initial placer iter 1, wirelen = 2910 Info: at initial placer iter 2, wirelen = 2817 Info: at initial placer iter 3, wirelen = 2693 Info: Running main analytical placer, max placement attempts per cell = 161880. Info: at iteration #1, type ALL: wirelen solved = 2654, spread = 6917, legal = 7559; time = 0.01s Info: at iteration #2, type ALL: wirelen solved = 2701, spread = 7543, legal = 8208; time = 0.01s Info: at iteration #3, type ALL: wirelen solved = 2730, spread = 8315, legal = 8393; time = 0.01s Info: at iteration #4, type ALL: wirelen solved = 2702, spread = 6982, legal = 7415; time = 0.01s Info: at iteration #5, type ALL: wirelen solved = 2846, spread = 6733, legal = 7431; time = 0.01s Info: at iteration #6, type ALL: wirelen solved = 2766, spread = 7088, legal = 7527; time = 0.01s Info: at iteration #7, type ALL: wirelen solved = 2848, spread = 7040, legal = 7862; time = 0.01s Info: at iteration #8, type ALL: wirelen solved = 2953, spread = 6901, legal = 8121; time = 0.01s Info: at iteration #9, type ALL: wirelen solved = 2945, spread = 6701, legal = 8004; time = 0.01s Info: HeAP Placer Time: 0.10s Info: of which solving equations: 0.06s Info: of which spreading cells: 0.01s Info: of which strict legalisation: 0.00s Info: Running simulated annealing placer for refinement. Info: at iteration #1: temp = 0.000000, timing cost = 277, wirelen = 7415 Info: at iteration #5: temp = 0.000000, timing cost = 202, wirelen = 5008 Info: at iteration #10: temp = 0.000000, timing cost = 301, wirelen = 4801 Info: at iteration #15: temp = 0.000000, timing cost = 280, wirelen = 4741 Info: at iteration #20: temp = 0.000000, timing cost = 272, wirelen = 4694 Info: at iteration #20: temp = 0.000000, timing cost = 271, wirelen = 4699 Info: SA placement time 0.33s Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 76.41 MHz (FAIL at 80.00 MHz) Info: Max delay -> posedge $glbnet$clk$TRELLIS_IO_IN: 6.72 ns Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> : 7.09 ns Info: Slack histogram: Info: legend: * represents 2 endpoint(s) Info: + represents [1,2) endpoint(s) Info: [ -588, 38) |****+ Info: [ 38, 664) |*+ Info: [ 664, 1290) | Info: [ 1290, 1916) | Info: [ 1916, 2542) |**+ Info: [ 2542, 3168) |**************+ Info: [ 3168, 3794) |******+ Info: [ 3794, 4420) |+ Info: [ 4420, 5046) |*+ Info: [ 5046, 5672) |*+ Info: [ 5672, 6298) | Info: [ 6298, 6924) |********+ Info: [ 6924, 7550) |*****+ Info: [ 7550, 8176) |*+ Info: [ 8176, 8802) |**+ Info: [ 8802, 9428) |************+ Info: [ 9428, 10054) |************************************************************ Info: [ 10054, 10680) |******************************************+ Info: [ 10680, 11306) |*************************************+ Info: [ 11306, 11932) |*******+ Info: Checksum: 0x87182704 Info: Routing globals... Info: routing clock net $glbnet$clk$TRELLIS_IO_IN using global 0 Info: Routing.. Info: Setting up routing queue. Info: Routing 2833 arcs. Info: | (re-)routed arcs | delta | remaining| time spent | Info: IterCnt | w/ripup wo/ripup | w/r wo/r | arcs| batch(sec) total(sec)| Info: 1000 | 615 384 | 615 384 | 2543| 0.16 0.16| Info: 2000 | 1342 657 | 727 273 | 2390| 0.18 0.34| Info: 3000 | 2021 978 | 679 321 | 2204| 0.17 0.51| Info: 4000 | 2356 1549 | 335 571 | 1570| 0.11 0.61| Info: 5000 | 2415 2379 | 59 830 | 638| 0.06 0.67| Info: 5643 | 2421 2956 | 6 577 | 0| 0.09 0.76| Info: Routing complete. Info: Router1 time 0.76s Info: Checksum: 0xf9732732 Info: Critical path report for clock '$glbnet$clk$TRELLIS_IO_IN' (posedge -> posedge): Info: type curr total name Info: clk-to-q 0.40 0.40 Source u_layer.GEN_NEURON[0].u_neuron.u_mac8.w_bus_TRELLIS_FF_Q.Q Info: routing 1.14 1.53 Net u_layer.GEN_NEURON[0].u_neuron.w_group[0] (31,23) -> (23,22) Info: Sink u_layer.GEN_NEURON[0].u_neuron.u_mac8.GEN_MAC[0].u_mac.product_MULT18X18D_P9.B0 Info: Defined in: Info: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:58.43-58.50 Info: logic 3.07 4.60 Source u_layer.GEN_NEURON[0].u_neuron.u_mac8.GEN_MAC[0].u_mac.product_MULT18X18D_P9.P2 Info: routing 1.52 6.12 Net u_layer.GEN_NEURON[0].u_neuron.u_mac8.products[0][2] (23,22) -> (31,20) Info: Sink u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_S1_CCU2C_S1$CCU2_COMB0.B Info: Defined in: Info: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:73.9-73.13 Info: logic 0.35 6.47 Source u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_S1_CCU2C_S1$CCU2_COMB0.FCO Info: routing 0.00 6.47 Net u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_S1_CCU2C_S1$CCU2_FCI_INT (31,20) -> (31,20) Info: Sink u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_S1_CCU2C_S1$CCU2_COMB1.FCI Info: logic 0.00 6.47 Source u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_S1_CCU2C_S1$CCU2_COMB1.FCO Info: routing 0.00 6.47 Net u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_S1_CCU2C_S1_COUT (31,20) -> (31,20) Info: Sink u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_CCU2C_S1$CCU2_COMB0.FCI Info: Defined in: Info: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44 Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4 Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13 Info: logic 0.06 6.53 Source u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_CCU2C_S1$CCU2_COMB0.FCO Info: routing 0.00 6.53 Net u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_CCU2C_S1$CCU2_FCI_INT (31,20) -> (31,20) Info: Sink u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_CCU2C_S1$CCU2_COMB1.FCI Info: logic 0.00 6.53 Source u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_CCU2C_S1$CCU2_COMB1.FCO Info: routing 0.00 6.53 Net u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_CCU2C_S1_COUT (31,20) -> (32,20) Info: Sink u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_CCU2C_S1$CCU2_COMB0.FCI Info: Defined in: Info: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44 Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4 Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13 Info: logic 0.33 6.86 Source u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_CCU2C_S1$CCU2_COMB0.F Info: routing 0.68 7.54 Net u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S0[2] (32,20) -> (34,20) Info: Sink u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_13_A0_LUT4_Z.D Info: Defined in: Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24 Info: logic 0.18 7.72 Source u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_13_A0_LUT4_Z.F Info: routing 1.09 8.81 Net u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_13_A0 (34,20) -> (35,19) Info: Sink u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_13$CCU2_COMB0.A Info: logic 0.35 9.16 Source u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_13$CCU2_COMB0.FCO Info: routing 0.00 9.16 Net u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_13$CCU2_FCI_INT (35,19) -> (35,19) Info: Sink u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_13$CCU2_COMB1.FCI Info: logic 0.00 9.16 Source u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_13$CCU2_COMB1.FCO Info: routing 0.00 9.16 Net u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_13_COUT (35,19) -> (35,19) Info: Sink u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_12$CCU2_COMB0.FCI Info: Defined in: Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4 Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13 Info: logic 0.06 9.22 Source u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_12$CCU2_COMB0.FCO Info: routing 0.00 9.22 Net u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_12$CCU2_FCI_INT (35,19) -> (35,19) Info: Sink u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_12$CCU2_COMB1.FCI Info: logic 0.00 9.22 Source u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_12$CCU2_COMB1.FCO Info: routing 0.00 9.22 Net u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_12_COUT (35,19) -> (35,19) Info: Sink u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_10$CCU2_COMB0.FCI Info: Defined in: Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4 Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13 Info: logic 0.06 9.27 Source u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_10$CCU2_COMB0.FCO Info: routing 0.00 9.27 Net u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_10$CCU2_FCI_INT (35,19) -> (35,19) Info: Sink u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_10$CCU2_COMB1.FCI Info: logic 0.00 9.27 Source u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_10$CCU2_COMB1.FCO Info: routing 0.00 9.27 Net u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_10_COUT (35,19) -> (35,19) Info: Sink u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1$CCU2_COMB0.FCI Info: Defined in: Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4 Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13 Info: logic 0.06 9.33 Source u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1$CCU2_COMB0.FCO Info: routing 0.00 9.33 Net u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1$CCU2_FCI_INT (35,19) -> (35,19) Info: Sink u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1$CCU2_COMB1.FCI Info: logic 0.00 9.33 Source u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1$CCU2_COMB1.FCO Info: routing 0.00 9.33 Net u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_COUT (35,19) -> (36,19) Info: Sink u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_14$CCU2_COMB0.FCI Info: Defined in: Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4 Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13 Info: logic 0.06 9.38 Source u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_14$CCU2_COMB0.FCO Info: routing 0.00 9.38 Net u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_14$CCU2_FCI_INT (36,19) -> (36,19) Info: Sink u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_14$CCU2_COMB1.FCI Info: logic 0.00 9.38 Source u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_14$CCU2_COMB1.FCO Info: routing 0.00 9.38 Net u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_14_COUT (36,19) -> (36,19) Info: Sink u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_1$CCU2_COMB0.FCI Info: Defined in: Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4 Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13 Info: logic 0.06 9.44 Source u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_1$CCU2_COMB0.FCO Info: routing 0.00 9.44 Net u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_1$CCU2_FCI_INT (36,19) -> (36,19) Info: Sink u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_1$CCU2_COMB1.FCI Info: logic 0.00 9.44 Source u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_1$CCU2_COMB1.FCO Info: routing 0.00 9.44 Net u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_1_COUT (36,19) -> (36,19) Info: Sink u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_2$CCU2_COMB0.FCI Info: Defined in: Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4 Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13 Info: logic 0.06 9.50 Source u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_2$CCU2_COMB0.FCO Info: routing 0.00 9.50 Net u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_2$CCU2_FCI_INT (36,19) -> (36,19) Info: Sink u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_2$CCU2_COMB1.FCI Info: logic 0.00 9.50 Source u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_2$CCU2_COMB1.FCO Info: routing 0.00 9.50 Net u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_2_COUT (36,19) -> (36,19) Info: Sink u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_3$CCU2_COMB0.FCI Info: Defined in: Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4 Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13 Info: logic 0.33 9.82 Source u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_3$CCU2_COMB0.F Info: routing 0.85 10.67 Net u_layer.GEN_NEURON[0].u_neuron.acc_next[20] (36,19) -> (36,18) Info: Sink u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.A Info: Defined in: Info: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:9.35-9.42 Info: logic 0.35 11.02 Source u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO Info: routing 0.00 11.02 Net u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (36,18) -> (36,18) Info: Sink u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI Info: logic 0.00 11.02 Source u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO Info: routing 0.00 11.02 Net u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (36,18) -> (37,18) Info: Sink u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI Info: Defined in: Info: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45 Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4 Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13 Info: logic 0.06 11.08 Source u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO Info: routing 0.00 11.08 Net u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (37,18) -> (37,18) Info: Sink u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI Info: logic 0.00 11.08 Source u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO Info: routing 0.00 11.08 Net u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (37,18) -> (37,18) Info: Sink u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI Info: Defined in: Info: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45 Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4 Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13 Info: logic 0.06 11.14 Source u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO Info: routing 0.00 11.14 Net u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (37,18) -> (37,18) Info: Sink u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI Info: logic 0.00 11.14 Source u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO Info: routing 0.00 11.14 Net u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN (37,18) -> (37,18) Info: Sink u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI Info: Defined in: Info: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45 Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4 Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13 Info: logic 0.06 11.19 Source u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO Info: routing 0.00 11.19 Net u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (37,18) -> (37,18) Info: Sink u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI Info: logic 0.00 11.19 Source u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO Info: routing 0.00 11.19 Net u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN (37,18) -> (37,18) Info: Sink u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT$CCU2_COMB0.FCI Info: Defined in: Info: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45 Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4 Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13 Info: logic 0.06 11.25 Source u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT$CCU2_COMB0.FCO Info: routing 0.00 11.25 Net u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT$CCU2_FCI_INT (37,18) -> (37,18) Info: Sink u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT$CCU2_COMB1.FCI Info: logic 0.00 11.25 Source u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT$CCU2_COMB1.FCO Info: routing 0.00 11.25 Net $nextpnr_CCU2C_19$CIN (37,18) -> (38,18) Info: Sink $nextpnr_CCU2C_19$CCU2_COMB0.FCI Info: logic 0.33 11.58 Source $nextpnr_CCU2C_19$CCU2_COMB0.F Info: routing 0.63 12.21 Net u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D (38,18) -> (38,23) Info: Sink u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z.D Info: Defined in: Info: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45 Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4 Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13 Info: logic 0.18 12.39 Source u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z.F Info: routing 0.64 13.03 Net u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C[1] (38,23) -> (36,23) Info: Sink u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_4.C Info: Defined in: Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24 Info: logic 0.18 13.21 Source u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_4.F Info: routing 0.12 13.33 Net u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI[5] (36,23) -> (36,23) Info: Sink u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_5.DI Info: setup 0.00 13.33 Source u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_5.DI Info: 6.67 ns logic, 6.66 ns routing Info: Critical path report for cross-domain path '' -> 'posedge $glbnet$clk$TRELLIS_IO_IN': Info: type curr total name Info: source 0.00 0.00 Source rst$tr_io.O Info: routing 3.60 3.60 Net rst$TRELLIS_IO_IN (0,23) -> (63,24) Info: Sink start_LUT4_B_2.C Info: Defined in: Info: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer.v:9.11-9.14 Info: logic 0.18 3.78 Source start_LUT4_B_2.F Info: routing 1.31 5.09 Net start_LUT4_B_2_Z (63,24) -> (67,27) Info: Sink u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_31.LSR Info: setup 0.29 5.38 Source u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_31.LSR Info: 0.47 ns logic, 4.91 ns routing Info: Critical path report for cross-domain path 'posedge $glbnet$clk$TRELLIS_IO_IN' -> '': Info: type curr total name Info: clk-to-q 0.40 0.40 Source u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_4.Q Info: routing 4.40 4.79 Net y_bus[20]$TRELLIS_IO_OUT (64,25) -> (18,71) Info: Sink y_bus[20]$tr_io.I Info: Defined in: Info: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/synth/ecp5/p4/top.v:6.26-6.31 Info: 0.40 ns logic, 4.40 ns routing ERROR: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 75.01 MHz (FAIL at 80.00 MHz) Info: Max delay -> posedge $glbnet$clk$TRELLIS_IO_IN: 5.38 ns Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> : 4.79 ns Info: Slack histogram: Info: legend: * represents 1 endpoint(s) Info: + represents [1,1) endpoint(s) Info: [ -831, -207) |*******+ Info: [ -207, 417) | Info: [ 417, 1041) | Info: [ 1041, 1665) | Info: [ 1665, 2289) |*+ Info: [ 2289, 2913) |*********************+ Info: [ 2913, 3537) |*******+ Info: [ 3537, 4161) |***+ Info: [ 4161, 4785) |**+ Info: [ 4785, 5409) | Info: [ 5409, 6033) |***+ Info: [ 6033, 6657) |**********+ Info: [ 6657, 7281) |****+ Info: [ 7281, 7905) |*+ Info: [ 7905, 8529) |*+ Info: [ 8529, 9153) |********************+ Info: [ 9153, 9777) |************************+ Info: [ 9777, 10401) |************************************************************ Info: [ 10401, 11025) |*******************************************************+ Info: [ 11025, 11649) |**********************************************+ 37 warnings, 1 error Info: Program finished normally.