\babel@toc {english}{}\relax 
\contentsline {chapter}{\numberline {1}System overview}{1}{chapter.1}%
\contentsline {section}{\numberline {1.1}Project goal}{1}{section.1.1}%
\contentsline {section}{\numberline {1.2}Hardware configuration versus network configuration}{1}{section.1.2}%
\contentsline {section}{\numberline {1.3}Boot and initialization}{2}{section.1.3}%
\contentsline {section}{\numberline {1.4}Training and inference}{2}{section.1.4}%
\contentsline {section}{\numberline {1.5}Design philosophy and reuse}{2}{section.1.5}%
\contentsline {chapter}{\numberline {2}RTL architecture}{3}{chapter.2}%
\contentsline {section}{\numberline {2.1}Hierarchical organization}{3}{section.2.1}%
\contentsline {section}{\numberline {2.2}Role of each module}{3}{section.2.2}%
\contentsline {section}{\numberline {2.3}Two execution paths}{4}{section.2.3}%
\contentsline {chapter}{\numberline {3}Compute datapath}{6}{chapter.3}%
\contentsline {section}{\numberline {3.1}INT8/INT32 arithmetic chain}{6}{section.3.1}%
\contentsline {section}{\numberline {3.2}\texttt {mac\_unit} --- multiply-accumulator}{6}{section.3.2}%
\contentsline {section}{\numberline {3.3}\texttt {mac8} --- parallel MAC and balanced adder tree}{6}{section.3.3}%
\contentsline {section}{\numberline {3.4}\texttt {neuron\_parallel} --- neuron FSM}{7}{section.3.4}%
\contentsline {subsection}{\numberline {3.4.1}Parameter guard (elaboration-time)}{7}{subsection.3.4.1}%
\contentsline {section}{\numberline {3.5}Activation functions}{8}{section.3.5}%
\contentsline {section}{\numberline {3.6}INT8 saturation}{8}{section.3.6}%
\contentsline {section}{\numberline {3.7}\texttt {layer} --- neurons in parallel}{8}{section.3.7}%
\contentsline {chapter}{\numberline {4}Parameters and configurability}{9}{chapter.4}%
\contentsline {section}{\numberline {4.1}Build parameters (synthesis-time)}{9}{section.4.1}%
\contentsline {section}{\numberline {4.2}Runtime network width}{9}{section.4.2}%
\contentsline {subsection}{\numberline {4.2.1}Measured savings}{10}{subsection.4.2.1}%
\contentsline {section}{\numberline {4.3}Characterized configurations}{10}{section.4.3}%
\contentsline {section}{\numberline {4.4}Build versus runtime summary}{10}{section.4.4}%
\contentsline {chapter}{\numberline {5}Memory subsystem}{11}{chapter.5}%
\contentsline {section}{\numberline {5.1}Memory chain}{11}{section.5.1}%
\contentsline {section}{\numberline {5.2}\texttt {int8\_memory\_access} --- byte/word conversion}{11}{section.5.2}%
\contentsline {section}{\numberline {5.3}\texttt {memory\_interface} --- handshake}{11}{section.5.3}%
\contentsline {section}{\numberline {5.4}\texttt {psram\_controller} --- physical bus}{11}{section.5.4}%
\contentsline {subsection}{\numberline {5.4.1}Timing}{12}{subsection.5.4.1}%
\contentsline {section}{\numberline {5.5}Read page mode}{12}{section.5.5}%
\contentsline {section}{\numberline {5.6}Address map and conventions}{13}{section.5.6}%
\contentsline {subsection}{\numberline {5.6.1}PSRAM physical addressing}{13}{subsection.5.6.1}%
\contentsline {section}{\numberline {5.7}Bandwidth}{13}{section.5.7}%
\contentsline {chapter}{\numberline {6}Memory, multi-neuron and multi-layer}{15}{chapter.6}%
\contentsline {section}{\numberline {6.1}\texttt {neuron\_memory} --- memory/neuron bridge}{15}{section.6.1}%
\contentsline {section}{\numberline {6.2}\texttt {layer\_sequencer} --- multi-layer network}{15}{section.6.2}%
\contentsline {subsection}{\numberline {6.2.1}Ping-pong buffers}{16}{subsection.6.2.1}%
\contentsline {subsection}{\numberline {6.2.2}Descriptor table}{16}{subsection.6.2.2}%
\contentsline {section}{\numberline {6.3}Hierarchy of the \texttt {busy}/\texttt {done} signals}{16}{section.6.3}%
\contentsline {chapter}{\numberline {7}Graph network (Type \#2)}{17}{chapter.7}%
\contentsline {section}{\numberline {7.1}Two network types}{17}{section.7.1}%
\contentsline {section}{\numberline {7.2}Global activation buffer}{17}{section.7.2}%
\contentsline {section}{\numberline {7.3}Feed-forward DAG and the \texttt {src\_id < out\_id} rule}{17}{section.7.3}%
\contentsline {section}{\numberline {7.4}Data formats}{17}{section.7.4}%
\contentsline {subsection}{\numberline {7.4.1}Type \#2 descriptor (graph)}{18}{subsection.7.4.1}%
\contentsline {subsection}{\numberline {7.4.2}Graph edge (4~bytes, aligned)}{18}{subsection.7.4.2}%
\contentsline {section}{\numberline {7.5}\texttt {graph\_engine} --- graph engine}{18}{section.7.5}%
\contentsline {section}{\numberline {7.6}Type \#2 opcodes and registers}{19}{section.7.6}%
\contentsline {section}{\numberline {7.7}Occupancy (Type \#2 enabled)}{19}{section.7.7}%
\contentsline {section}{\numberline {7.8}Gather bandwidth (measured)}{20}{section.7.8}%
\contentsline {section}{\numberline {7.9}\texttt {netasm} host assembler}{20}{section.7.9}%
\contentsline {chapter}{\numberline {8}SPI host interface}{21}{chapter.8}%
\contentsline {section}{\numberline {8.1}Physical layer}{21}{section.8.1}%
\contentsline {section}{\numberline {8.2}Framing and explicit length}{21}{section.8.2}%
\contentsline {section}{\numberline {8.3}Opcode table}{21}{section.8.3}%
\contentsline {section}{\numberline {8.4}\texttt {SET\_BASE} selectors}{23}{section.8.4}%
\contentsline {section}{\numberline {8.5}\texttt {STATUS.done} sticky / clear-on-read}{24}{section.8.5}%
\contentsline {section}{\numberline {8.6}Host attention pins (\texttt {data\_ready\_n}, \texttt {irq\_n})}{24}{section.8.6}%
\contentsline {section}{\numberline {8.7}\texttt {READ\_CONFIG}}{25}{section.8.7}%
\contentsline {section}{\numberline {8.8}Flash subsystem (opcodes 0x40--0x47, completed 2026-09-04)}{25}{section.8.8}%
\contentsline {section}{\numberline {8.9}Session sequences}{26}{section.8.9}%
\contentsline {subsection}{\numberline {8.9.1}Single-layer path}{26}{subsection.8.9.1}%
\contentsline {subsection}{\numberline {8.9.2}Multi-layer path (RUN\_NETWORK)}{26}{subsection.8.9.2}%
\contentsline {chapter}{\numberline {9}Network programming}{28}{chapter.9}%
\contentsline {section}{\numberline {9.1}General flow}{28}{section.9.1}%
\contentsline {section}{\numberline {9.2}Registers and opcodes involved}{28}{section.9.2}%
\contentsline {section}{\numberline {9.3}Type \#1 --- dense network}{29}{section.9.3}%
\contentsline {subsection}{\numberline {9.3.1}Memory layout}{29}{subsection.9.3.1}%
\contentsline {subsection}{\numberline {9.3.2}Worked example: a $4\to 4\to 2$ network}{29}{subsection.9.3.2}%
\contentsline {subsection}{\numberline {9.3.3}Host pseudocode (dense)}{29}{subsection.9.3.3}%
\contentsline {section}{\numberline {9.4}Type \#2 --- graph network}{30}{section.9.4}%
\contentsline {subsection}{\numberline {9.4.1}Memory layout}{30}{subsection.9.4.1}%
\contentsline {subsection}{\numberline {9.4.2}Worked example}{30}{subsection.9.4.2}%
\contentsline {subsection}{\numberline {9.4.3}Host pseudocode (graph)}{30}{subsection.9.4.3}%
\contentsline {subsection}{\numberline {9.4.4}\texttt {netasm} pseudo-assembly}{31}{subsection.9.4.4}%
\contentsline {chapter}{\numberline {10}Arbitration and top-level}{32}{chapter.10}%
\contentsline {section}{\numberline {10.1}\texttt {mem\_arbiter} --- three-port arbiter}{32}{section.10.1}%
\contentsline {section}{\numberline {10.2}\texttt {spi\_neuron\_top} --- full integration}{32}{section.10.2}%
\contentsline {chapter}{\numberline {11}ECP5 implementation}{34}{chapter.11}%
\contentsline {section}{\numberline {11.1}Flow and verification}{34}{section.11.1}%
\contentsline {section}{\numberline {11.2}Datapath benchmark (256$\times $4)}{34}{section.11.2}%
\contentsline {subsection}{\numberline {11.2.1}Fmax and throughput versus parallelism}{35}{subsection.11.2.1}%
\contentsline {subsection}{\numberline {11.2.2}Interpretation}{35}{subsection.11.2.2}%
\contentsline {subsection}{\numberline {11.2.3}Critical path and the 100~MHz limit}{35}{subsection.11.2.3}%
\contentsline {section}{\numberline {11.3}Full integrated system}{35}{section.11.3}%
\contentsline {subsection}{\numberline {11.3.1}Cause: the saturation/ReLU carry chain}{35}{subsection.11.3.1}%
\contentsline {subsection}{\numberline {11.3.2}Timing closure (2026-09-03)}{36}{subsection.11.3.2}%
\contentsline {chapter}{\numberline {12}Hardware design and pinout}{37}{chapter.12}%
\contentsline {section}{\numberline {12.1}Target device}{37}{section.12.1}%
\contentsline {section}{\numberline {12.2}Pin budget}{37}{section.12.2}%
\contentsline {section}{\numberline {12.3}Signal map (top-level \texttt {spi\_neuron\_top}) --- real balls}{38}{section.12.3}%
\contentsline {section}{\numberline {12.4}Per-bank allocation (real die geometry)}{40}{section.12.4}%
\contentsline {section}{\numberline {12.5}PSRAM subsystem}{40}{section.12.5}%
\contentsline {subsection}{\numberline {12.5.1}PSRAM connection (FPGA-exclusive)}{40}{subsection.12.5.1}%
\contentsline {section}{\numberline {12.6}Clock}{41}{section.12.6}%
\contentsline {section}{\numberline {12.7}Power}{41}{section.12.7}%
\contentsline {section}{\numberline {12.8}Configuration and programming}{41}{section.12.8}%
\contentsline {subsection}{\numberline {12.8.1}JTAG (development / debug)}{41}{subsection.12.8.1}%
\contentsline {subsection}{\numberline {12.8.2}Config-SPI to boot flash}{41}{subsection.12.8.2}%
\contentsline {subsection}{\numberline {12.8.3}Configuration modes (\texttt {CFGMDN})}{42}{subsection.12.8.3}%
\contentsline {section}{\numberline {12.9}Open tasks before schematic capture}{42}{section.12.9}%
\contentsline {chapter}{\numberline {13}Quick reference}{44}{chapter.13}%
\contentsline {section}{\numberline {13.1}SPI opcodes}{44}{section.13.1}%
\contentsline {section}{\numberline {13.2}STATUS byte}{44}{section.13.2}%
\contentsline {section}{\numberline {13.3}SET\_BASE selectors}{44}{section.13.3}%
\contentsline {section}{\numberline {13.4}Descriptor table (11 bytes/layer, MSB-first)}{44}{section.13.4}%
\contentsline {section}{\numberline {13.5}Build parameters}{44}{section.13.5}%
\contentsline {chapter}{\numberline {14}Roadmap and development status}{45}{chapter.14}%
\contentsline {section}{\numberline {14.1}Development phases}{45}{section.14.1}%
\contentsline {section}{\numberline {14.2}Component status}{45}{section.14.2}%
\contentsline {section}{\numberline {14.3}Architectural principle (summary)}{46}{section.14.3}%
\contentsline {section}{\numberline {14.4}Long-term vision}{46}{section.14.4}%
\contentsline {chapter}{\numberline {A}Modules and toolchain}{47}{appendix.A}%
\contentsline {section}{\numberline {A.1}List of RTL modules}{47}{section.A.1}%
\contentsline {section}{\numberline {A.2}Ports of the top-level \texttt {spi\_neuron\_top}}{47}{section.A.2}%
\contentsline {section}{\numberline {A.3}Toolchain}{47}{section.A.3}%
\contentsline {subsection}{\numberline {A.3.1}Main nextpnr parameters}{47}{subsection.A.3.1}%
\contentsline {subsection}{\numberline {A.3.2}Simulation example}{48}{subsection.A.3.2}%
\contentsline {section}{\numberline {A.4}Main testbenches}{48}{section.A.4}%