Info: Logic utilisation before packing: Info: Total LUT4s: 42/43848 0% Info: logic LUTs: 42/43848 0% Info: carry LUTs: 0/43848 0% Info: RAM LUTs: 0/ 5481 0% Info: RAMW LUTs: 0/10962 0% Info: Total DFFs: 56/43848 0% Info: Packing IOs.. Info: Packing constants.. Info: Packing carries... Info: Packing LUTs... Info: Packing LUT5-7s... Info: Packing FFs... Info: 16 FFs paired with LUTs. Info: Generating derived timing constraints... Info: Promoting globals... Info: promoting clock net clk$TRELLIS_IO_IN to global network Info: Checksum: 0xb4abc577 Info: Device utilisation: Info: TRELLIS_IO: 18/ 245 7% Info: DCCA: 1/ 56 1% Info: DP16KD: 4/ 108 3% Info: MULT18X18D: 0/ 72 0% Info: ALU54B: 0/ 36 0% Info: EHXPLLL: 0/ 4 0% Info: EXTREFB: 0/ 2 0% Info: DCUA: 0/ 2 0% Info: PCSCLKDIV: 0/ 2 0% Info: IOLOGIC: 0/ 160 0% Info: SIOLOGIC: 0/ 85 0% Info: GSR: 0/ 1 0% Info: JTAGG: 0/ 1 0% Info: OSCG: 0/ 1 0% Info: SEDGA: 0/ 1 0% Info: DTR: 0/ 1 0% Info: USRMCLK: 0/ 1 0% Info: CLKDIVF: 0/ 4 0% Info: ECLKSYNCB: 0/ 10 0% Info: DLLDELD: 0/ 8 0% Info: DDRDLL: 0/ 4 0% Info: DQSBUFM: 0/ 10 0% Info: TRELLIS_ECLKBUF: 0/ 8 0% Info: ECLKBRIDGECS: 0/ 2 0% Info: DCSC: 0/ 2 0% Info: TRELLIS_FF: 56/ 43848 0% Info: TRELLIS_COMB: 44/ 43848 0% Info: TRELLIS_RAMW: 0/ 5481 0% Info: Placed 0 cells based on constraints. Info: Creating initial analytic placement for 75 cells, random placement wirelen = 7922. Info: at initial placer iter 0, wirelen = 1177 Info: at initial placer iter 1, wirelen = 1085 Info: at initial placer iter 2, wirelen = 1038 Info: at initial placer iter 3, wirelen = 1014 Info: Running main analytical placer, max placement attempts per cell = 10000. Info: at iteration #1, type ALL: wirelen solved = 1012, spread = 1503, legal = 2089; time = 0.00s Info: at iteration #2, type ALL: wirelen solved = 1002, spread = 1408, legal = 2121; time = 0.00s Info: at iteration #3, type ALL: wirelen solved = 1045, spread = 1417, legal = 2123; time = 0.00s Info: at iteration #4, type ALL: wirelen solved = 998, spread = 1452, legal = 2320; time = 0.00s Info: at iteration #5, type ALL: wirelen solved = 1010, spread = 1419, legal = 2320; time = 0.00s Info: at iteration #6, type ALL: wirelen solved = 1012, spread = 1464, legal = 2353; time = 0.00s Info: HeAP Placer Time: 0.03s Info: of which solving equations: 0.00s Info: of which spreading cells: 0.00s Info: of which strict legalisation: 0.00s Info: Running simulated annealing placer for refinement. Info: at iteration #1: temp = 0.000000, timing cost = 31, wirelen = 2089 Info: at iteration #5: temp = 0.000000, timing cost = 31, wirelen = 1310 Info: at iteration #10: temp = 0.000000, timing cost = 31, wirelen = 1292 Info: at iteration #15: temp = 0.000000, timing cost = 28, wirelen = 1285 Info: at iteration #20: temp = 0.000000, timing cost = 27, wirelen = 1236 Info: at iteration #20: temp = 0.000000, timing cost = 27, wirelen = 1236 Info: SA placement time 0.02s Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 159.67 MHz (PASS at 80.00 MHz) Info: Max delay -> posedge $glbnet$clk$TRELLIS_IO_IN: 5.95 ns Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> : 6.35 ns Info: Slack histogram: Info: legend: * represents 1 endpoint(s) Info: + represents [1,1) endpoint(s) Info: [ 6237, 6512) |****** Info: [ 6512, 6787) | Info: [ 6787, 7062) |* Info: [ 7062, 7337) |* Info: [ 7337, 7612) | Info: [ 7612, 7887) | Info: [ 7887, 8162) |* Info: [ 8162, 8437) | Info: [ 8437, 8712) | Info: [ 8712, 8987) | Info: [ 8987, 9262) | Info: [ 9262, 9537) | Info: [ 9537, 9812) | Info: [ 9812, 10087) |** Info: [ 10087, 10362) |**** Info: [ 10362, 10637) |************* Info: [ 10637, 10912) |************************** Info: [ 10912, 11187) |********************** Info: [ 11187, 11462) |******************************** Info: [ 11462, 11737) |******************************* Info: Checksum: 0x22f96075 Info: Routing globals... Info: routing clock net $glbnet$clk$TRELLIS_IO_IN using global 0 Info: Routing.. Info: Setting up routing queue. Info: Routing 317 arcs. Info: | (re-)routed arcs | delta | remaining| time spent | Info: IterCnt | w/ripup wo/ripup | w/r wo/r | arcs| batch(sec) total(sec)| Info: 440 | 117 316 | 117 316 | 0| 0.07 0.07| Info: Routing complete. Info: Router1 time 0.07s Info: Checksum: 0xcc51a16f Info: Critical path report for clock '$glbnet$clk$TRELLIS_IO_IN' (posedge -> posedge): Info: type curr total name Info: clk-to-q 4.10 4.10 Source dut.GEN_SLOT[1].GEN_LANE[0].mem.0.0.DOA0 Info: routing 1.43 5.53 Net rd_data_flat[64] (13,34) -> (9,25) Info: Sink dut.GEN_SLOT[0].GEN_LANE[0].mem.0.0_DOB0_LUT4_C.A Info: Defined in: Info: hardware/v2/nms/rtl/nms_weight_packed.v:30.50-30.62 Info: logic 0.18 5.71 Source dut.GEN_SLOT[0].GEN_LANE[0].mem.0.0_DOB0_LUT4_C.F Info: routing 0.32 6.03 Net dut.GEN_SLOT[0].GEN_LANE[0].mem.0.0_DOB0_LUT4_C_Z[2] (9,25) -> (9,25) Info: Sink dut.GEN_SLOT[0].GEN_LANE[0].mem.0.0_DOB0_LUT4_C_Z_LUT4_D.D Info: Defined in: Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24 Info: logic 0.18 6.21 Source dut.GEN_SLOT[0].GEN_LANE[0].mem.0.0_DOB0_LUT4_C_Z_LUT4_D.F Info: routing 0.12 6.33 Net dut.GEN_SLOT[0].GEN_LANE[0].mem.0.0_DOB0_LUT4_C_Z_LUT4_D_Z[0] (9,25) -> (9,25) Info: Sink chk_TRELLIS_FF_Q_2.DI Info: setup 0.00 6.33 Source chk_TRELLIS_FF_Q_2.DI Info: 4.46 ns logic, 1.87 ns routing Info: Critical path report for cross-domain path '' -> 'posedge $glbnet$clk$TRELLIS_IO_IN': Info: type curr total name Info: source 0.00 0.00 Source seed[7]$tr_io.O Info: routing 3.88 3.88 Net seed[7]$TRELLIS_IO_IN (90,35) -> (12,33) Info: Sink seed_LUT4_B_Z_LUT4_Z.B Info: Defined in: Info: hardware/v2/nms/synthesis/harness_nms_weight_packed.v:14.23-14.27 Info: logic 0.18 4.06 Source seed_LUT4_B_Z_LUT4_Z.F Info: routing 0.12 4.18 Net seed_LUT4_B_Z[7] (12,33) -> (12,33) Info: Sink lfsr_TRELLIS_FF_Q_8.DI Info: setup 0.00 4.18 Source lfsr_TRELLIS_FF_Q_8.DI Info: 0.18 ns logic, 4.00 ns routing Info: Critical path report for cross-domain path 'posedge $glbnet$clk$TRELLIS_IO_IN' -> '': Info: type curr total name Info: clk-to-q 0.40 0.40 Source chk_TRELLIS_FF_Q_7.Q Info: routing 3.72 4.11 Net checksum[5]$TRELLIS_IO_OUT (8,33) -> (90,32) Info: Sink checksum[5]$tr_io.I Info: Defined in: Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24 Info: 0.40 ns logic, 3.72 ns routing Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 157.98 MHz (PASS at 80.00 MHz) Info: Max delay -> posedge $glbnet$clk$TRELLIS_IO_IN: 4.18 ns Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> : 4.11 ns Info: Slack histogram: Info: legend: * represents 1 endpoint(s) Info: + represents [1,1) endpoint(s) Info: [ 6170, 6455) |*** Info: [ 6455, 6740) |***** Info: [ 6740, 7025) | Info: [ 7025, 7310) | Info: [ 7310, 7595) | Info: [ 7595, 7880) | Info: [ 7880, 8165) | Info: [ 8165, 8450) | Info: [ 8450, 8735) | Info: [ 8735, 9020) | Info: [ 9020, 9305) |* Info: [ 9305, 9590) | Info: [ 9590, 9875) | Info: [ 9875, 10160) | Info: [ 10160, 10445) |* Info: [ 10445, 10730) |******** Info: [ 10730, 11015) |******************************** Info: [ 11015, 11300) |********************************************** Info: [ 11300, 11585) |********************** Info: [ 11585, 11870) |********************* Info: Program finished normally.